* [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more)
@ 2021-12-11 21:13 Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 01/28] dt-bindings: ARM: tegra: Document ASUS Transformers Dmitry Osipenko
` (27 more replies)
0 siblings, 28 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
In this patchset you will find:
- New device-trees of ASUS Transformer and Pegatron Chagall tablets.
- New device-tree of Nyan Big Chromebook variant that has 1080p display
panel.
- Enabled video decoder on Tegra114.
- Minor cleanup of Nexus7 device-tree.
- Renamed clocks and regulator nodes.
- Fixes for T124 device-trees.
Changelog:
v6: - Added my s-o-b to all patches.
- Separated clk/regulator nodes renaming patch and gave Thierry Reding
credit for that.
- Borrowed "ARM: tegra: Add #reset-cells for Tegra114 MC" patch from
Thierry to resolve merge conflict with the video decoder patch.
- Added old patch from Stefan Agner that enables gpio-ranges, it was
brought up in the other DT thread. I borrowed "ARM: tegra: Remove stray
#reset-cells property" patch from Thierry to resolve merge conflict of
these patches.
- Reordered all DT nodes alphabetically.
- Enabled couple more options in tegra_defconfig needed by Nyan
Chromebook, as was requested by Thomas Graichen.
- Improved thermal zones of TF101, making them to match what latest
DT of Acer A500 uses. Previous versions used older variant of the
A500 zones.
v5: - Minor update. Maxim improved commit messages. We added links to the
postmarketOS Wiki.
v4: - Factored out common parts of ASUS device-trees into separate patches.
I retained the original author of the tegra30-asus-transformer-common.dtsi
after chatting with Svyatoslav. Initially I wanted to change the
authorship to Michał, but not that much left from the original DT that
was created by Michał, so it's fair to keep Svyatoslav the author.
I explained in the commit message that the common DT was derived from
the Michał's TF300T DT and then reworked heavily, I also added Michał
as co-developer of the common part.
- Added new T124 patches that were requested by Thomas Graichen. They
restore USB, CPUFreq and fix overheating of Nyan Chromebooks.
- Added patches that update tegra_defconfig and multi_v7_defconfig with
enabled drivers used by ASUS Transformers and Nyan Chromebooks.
- Added acks that were given by Rob Herring to v3.
- Changed display panel compatible of ASUS TF701T like it was suggested
by Rob Herring in other thread.
- Removed yet unused SDMMC1 pinmux from TF701T DT as was requested by
Anton Bambura.
- Added patch which adds node labels to T30 DTSI. It eases porting
devices to upstream. This was requested by Michał Mirosław.
v3: - Maxim added couple "FIXME" comments to Transformer device-trees for
things that are yet missing on kernel side, and thus, can't be enabled
in the DT for now.
- Maxim also found that v2 had a small problem in the patch which adds
device-tree for Chagall tablet. Turned out I made a mistake during
rebase of the patches and haven't noticed it, it's fixed now.
v2: - Svyatoslav and Maxim made couple corrections to regulators, comments
and default brightness of the device-trees.
- Added thermtrip node to transformers DT as we now have PMIC fix for
it [1], it works properly now.
[1] https://patchwork.ozlabs.org/project/linux-tegra/patch/20211124190104.23554-1-digetx@gmail.com/
- Changed sound card model names to make them per-device and consistent
with the names that other Tegra DTs already use in upstream. This will
prevent potential ABI breakages in the future if we will find that sound
of some device needs extra differentiation.
Anton Bambura (3):
ARM: tegra: Add labels to tegra114.dtsi
ARM: tegra: Add device-tree for ASUS Transformer Pad TF701T
ARM: tegra: Enable video decoder on Tegra114
David Heidelberg (3):
dt-bindings: ARM: tegra: Document Pegatron Chagall
ARM: tegra: Rename top-level clocks
ARM: tegra: nexus7: Drop clock-frequency from NFC node
Dmitry Osipenko (7):
ARM: tegra: Add device-tree for 1080p version of Nyan Big
ARM: tegra: Enable HDMI CEC on Nyan
ARM: tegra: Enable CPU DFLL on Nyan
ARM: tegra: Add CPU thermal zones to Nyan device-tree
ARM: tegra: Rename top-level regulators
ARM: tegra_defconfig: Enable drivers wanted by Acer Chromebooks and
ASUS tablets
ARM: config: multi v7: Enable display drivers used by Tegra devices
Maxim Schwalm (2):
ARM: tegra: Add common device-tree for LVDS display panels of Tegra30
ASUS tablets
ARM: tegra: nexus7: Use common LVDS display device-tree
Michał Mirosław (2):
ARM: tegra: Add labels to tegra30.dtsi
ARM: tegra: Add device-tree for ASUS Transformer Pad TF300T
Nikola Milosavljevic (1):
ARM: tegra: Add device-tree for ASUS Transformer EeePad TF101
Stefan Agner (1):
ARM: tegra: Re-add gpio-ranges properties
Stefan Eichenberger (1):
ARM: tegra: Add usb-role-switch property to USB OTG ports
Svyatoslav Ryhel (6):
dt-bindings: ARM: tegra: Document ASUS Transformers
ARM: tegra: Add common device-tree base for Tegra30 ASUS Transformers
ARM: tegra: Add device-tree for ASUS Transformer Prime TF201
ARM: tegra: Add device-tree for ASUS Transformer Pad TF300TG
ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T
ARM: tegra: Add device-tree for Pegatron Chagall
Thierry Reding (2):
ARM: tegra: Add #reset-cells for Tegra114 MC
ARM: tegra: Remove stray #reset-cells property
.../devicetree/bindings/arm/tegra.yaml | 19 +
arch/arm/boot/dts/Makefile | 10 +-
arch/arm/boot/dts/tegra114-asus-tf701t.dts | 788 +++++
arch/arm/boot/dts/tegra114-dalmore.dts | 16 +-
arch/arm/boot/dts/tegra114-roth.dts | 14 +-
arch/arm/boot/dts/tegra114-tn7.dts | 8 +-
arch/arm/boot/dts/tegra114.dtsi | 92 +-
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 1 +
arch/arm/boot/dts/tegra124-apalis.dtsi | 1 +
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 26 +-
arch/arm/boot/dts/tegra124-nyan-big-fhd.dts | 11 +
arch/arm/boot/dts/tegra124-nyan.dtsi | 84 +-
arch/arm/boot/dts/tegra124-venice2.dts | 30 +-
arch/arm/boot/dts/tegra124.dtsi | 2 -
.../boot/dts/tegra20-acer-a500-picasso.dts | 12 +-
arch/arm/boot/dts/tegra20-asus-tf101.dts | 1228 ++++++++
arch/arm/boot/dts/tegra20-harmony.dts | 16 +-
arch/arm/boot/dts/tegra20-medcom-wide.dts | 8 +-
arch/arm/boot/dts/tegra20-paz00.dts | 6 +-
arch/arm/boot/dts/tegra20-plutux.dts | 8 +-
arch/arm/boot/dts/tegra20-seaboard.dts | 16 +-
arch/arm/boot/dts/tegra20-tamonten.dtsi | 4 +-
arch/arm/boot/dts/tegra20-tec.dts | 8 +-
arch/arm/boot/dts/tegra20-trimslice.dts | 12 +-
arch/arm/boot/dts/tegra20-ventana.dts | 12 +-
arch/arm/boot/dts/tegra20.dtsi | 2 -
.../boot/dts/tegra30-asus-lvds-display.dtsi | 61 +
.../tegra30-asus-nexus7-grouper-common.dtsi | 64 +-
...egra30-asus-nexus7-grouper-maxim-pmic.dtsi | 4 +-
.../tegra30-asus-nexus7-grouper-ti-pmic.dtsi | 2 +-
.../boot/dts/tegra30-asus-nexus7-grouper.dtsi | 1 -
.../boot/dts/tegra30-asus-nexus7-tilapia.dtsi | 2 -
arch/arm/boot/dts/tegra30-asus-tf201.dts | 623 ++++
arch/arm/boot/dts/tegra30-asus-tf300t.dts | 1030 ++++++
arch/arm/boot/dts/tegra30-asus-tf300tg.dts | 1072 +++++++
arch/arm/boot/dts/tegra30-asus-tf700t.dts | 818 +++++
.../dts/tegra30-asus-transformer-common.dtsi | 1729 ++++++++++
arch/arm/boot/dts/tegra30-beaver.dts | 20 +-
arch/arm/boot/dts/tegra30-cardhu-a02.dts | 12 +-
arch/arm/boot/dts/tegra30-cardhu-a04.dts | 14 +-
arch/arm/boot/dts/tegra30-cardhu.dtsi | 28 +-
arch/arm/boot/dts/tegra30-ouya.dts | 5 -
.../arm/boot/dts/tegra30-pegatron-chagall.dts | 2794 +++++++++++++++++
arch/arm/boot/dts/tegra30.dtsi | 38 +-
arch/arm/configs/multi_v7_defconfig | 5 +
arch/arm/configs/tegra_defconfig | 12 +
46 files changed, 10497 insertions(+), 271 deletions(-)
create mode 100644 arch/arm/boot/dts/tegra114-asus-tf701t.dts
create mode 100644 arch/arm/boot/dts/tegra124-nyan-big-fhd.dts
create mode 100644 arch/arm/boot/dts/tegra20-asus-tf101.dts
create mode 100644 arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi
create mode 100644 arch/arm/boot/dts/tegra30-asus-tf201.dts
create mode 100644 arch/arm/boot/dts/tegra30-asus-tf300t.dts
create mode 100644 arch/arm/boot/dts/tegra30-asus-tf300tg.dts
create mode 100644 arch/arm/boot/dts/tegra30-asus-tf700t.dts
create mode 100644 arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi
create mode 100644 arch/arm/boot/dts/tegra30-pegatron-chagall.dts
--
2.33.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v6 01/28] dt-bindings: ARM: tegra: Document ASUS Transformers
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 02/28] dt-bindings: ARM: tegra: Document Pegatron Chagall Dmitry Osipenko
` (26 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Svyatoslav Ryhel <clamor95@gmail.com>
Document Tegra20/30/114-based ASUS Transformer Series tablet devices.
This group includes EeePad TF101, Prime TF201, Pad TF300T, TF300TG
Infinity TF700T, TF701T.
Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Anton Bambura <jenneron@protonmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
Documentation/devicetree/bindings/arm/tegra.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml
index 3bd0920da274..64b7b770a0dc 100644
--- a/Documentation/devicetree/bindings/arm/tegra.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra.yaml
@@ -36,6 +36,9 @@ properties:
- toradex,colibri_t20-iris
- const: toradex,colibri_t20
- const: nvidia,tegra20
+ - items:
+ - const: asus,tf101
+ - const: nvidia,tegra20
- items:
- const: acer,picasso
- const: nvidia,tegra20
@@ -49,6 +52,18 @@ properties:
- nvidia,cardhu-a04
- const: nvidia,cardhu
- const: nvidia,tegra30
+ - items:
+ - const: asus,tf201
+ - const: nvidia,tegra30
+ - items:
+ - const: asus,tf300t
+ - const: nvidia,tegra30
+ - items:
+ - const: asus,tf300tg
+ - const: nvidia,tegra30
+ - items:
+ - const: asus,tf700t
+ - const: nvidia,tegra30
- items:
- const: toradex,apalis_t30-eval
- const: toradex,apalis_t30
@@ -76,6 +91,7 @@ properties:
- const: nvidia,tegra30
- items:
- enum:
+ - asus,tf701t
- nvidia,dalmore
- nvidia,roth
- nvidia,tn7
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 02/28] dt-bindings: ARM: tegra: Document Pegatron Chagall
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 01/28] dt-bindings: ARM: tegra: Document ASUS Transformers Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 03/28] ARM: tegra: Add labels to tegra30.dtsi Dmitry Osipenko
` (25 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: David Heidelberg <david@ixit.cz>
Document Pegatron Chagall, which is Tegra30-based tablet device.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
Documentation/devicetree/bindings/arm/tegra.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml
index 64b7b770a0dc..49841ca272ee 100644
--- a/Documentation/devicetree/bindings/arm/tegra.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra.yaml
@@ -89,6 +89,9 @@ properties:
- items:
- const: ouya,ouya
- const: nvidia,tegra30
+ - items:
+ - const: pegatron,chagall
+ - const: nvidia,tegra30
- items:
- enum:
- asus,tf701t
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 03/28] ARM: tegra: Add labels to tegra30.dtsi
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 01/28] dt-bindings: ARM: tegra: Document ASUS Transformers Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 02/28] dt-bindings: ARM: tegra: Document Pegatron Chagall Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 04/28] ARM: tegra: Add labels to tegra114.dtsi Dmitry Osipenko
` (24 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Add phandle names for memory/I2C/SPI/USB/SDMMC controller nodes to allow
for cleaner device descriptions.
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra30.dtsi | 36 +++++++++++++++++-----------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index ae3df73c20a7..a6772171c910 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -585,7 +585,7 @@ rtc@7000e000 {
clocks = <&tegra_car TEGRA30_CLK_RTC>;
};
- i2c@7000c000 {
+ i2c1: i2c@7000c000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -601,7 +601,7 @@ i2c@7000c000 {
status = "disabled";
};
- i2c@7000c400 {
+ i2c2: i2c@7000c400 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c400 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -617,7 +617,7 @@ i2c@7000c400 {
status = "disabled";
};
- i2c@7000c500 {
+ i2c3: i2c@7000c500 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c500 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -633,7 +633,7 @@ i2c@7000c500 {
status = "disabled";
};
- i2c@7000c700 {
+ i2c4: i2c@7000c700 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c700 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
@@ -649,7 +649,7 @@ i2c@7000c700 {
status = "disabled";
};
- i2c@7000d000 {
+ i2c5: i2c@7000d000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000d000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
@@ -665,7 +665,7 @@ i2c@7000d000 {
status = "disabled";
};
- spi@7000d400 {
+ spi1: spi@7000d400 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d400 0x200>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
@@ -679,7 +679,7 @@ spi@7000d400 {
status = "disabled";
};
- spi@7000d600 {
+ spi2: spi@7000d600 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -693,7 +693,7 @@ spi@7000d600 {
status = "disabled";
};
- spi@7000d800 {
+ spi3: spi@7000d800 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d800 0x200>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -707,7 +707,7 @@ spi@7000d800 {
status = "disabled";
};
- spi@7000da00 {
+ spi4: spi@7000da00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000da00 0x200>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
@@ -721,7 +721,7 @@ spi@7000da00 {
status = "disabled";
};
- spi@7000dc00 {
+ spi5: spi@7000dc00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000dc00 0x200>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
@@ -735,7 +735,7 @@ spi@7000dc00 {
status = "disabled";
};
- spi@7000de00 {
+ spi6: spi@7000de00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000de00 0x200>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
@@ -913,7 +913,7 @@ tegra_i2s4: i2s@70080700 {
};
};
- mmc@78000000 {
+ sdmmc1: mmc@78000000 {
compatible = "nvidia,tegra30-sdhci";
reg = <0x78000000 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@@ -924,7 +924,7 @@ mmc@78000000 {
status = "disabled";
};
- mmc@78000200 {
+ sdmmc2: mmc@78000200 {
compatible = "nvidia,tegra30-sdhci";
reg = <0x78000200 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
@@ -935,7 +935,7 @@ mmc@78000200 {
status = "disabled";
};
- mmc@78000400 {
+ sdmmc3: mmc@78000400 {
compatible = "nvidia,tegra30-sdhci";
reg = <0x78000400 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@@ -946,7 +946,7 @@ mmc@78000400 {
status = "disabled";
};
- mmc@78000600 {
+ sdmmc4: mmc@78000600 {
compatible = "nvidia,tegra30-sdhci";
reg = <0x78000600 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
@@ -957,7 +957,7 @@ mmc@78000600 {
status = "disabled";
};
- usb@7d000000 {
+ usb1: usb@7d000000 {
compatible = "nvidia,tegra30-ehci";
reg = <0x7d000000 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -999,7 +999,7 @@ phy1: usb-phy@7d000000 {
status = "disabled";
};
- usb@7d004000 {
+ usb2: usb@7d004000 {
compatible = "nvidia,tegra30-ehci";
reg = <0x7d004000 0x4000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
@@ -1039,7 +1039,7 @@ phy2: usb-phy@7d004000 {
status = "disabled";
};
- usb@7d008000 {
+ usb3: usb@7d008000 {
compatible = "nvidia,tegra30-ehci";
reg = <0x7d008000 0x4000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 04/28] ARM: tegra: Add labels to tegra114.dtsi
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (2 preceding siblings ...)
2021-12-11 21:13 ` [PATCH v6 03/28] ARM: tegra: Add labels to tegra30.dtsi Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 05/28] ARM: tegra: Add device-tree for ASUS Transformer EeePad TF101 Dmitry Osipenko
` (23 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Anton Bambura <jenneron@protonmail.com>
Add more labels in order to use label reference in device-specific
dts files. Labels make device-trees more readable and prevent typos
that are difficult to notice.
Signed-off-by: Anton Bambura <jenneron@protonmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra114.dtsi | 52 ++++++++++++++++-----------------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 546272e396b4..563ee262f41d 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -93,7 +93,7 @@ rgb {
};
};
- hdmi@54280000 {
+ hdmi: hdmi@54280000 {
compatible = "nvidia,tegra114-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -105,7 +105,7 @@ hdmi@54280000 {
status = "disabled";
};
- dsi@54300000 {
+ dsia: dsi@54300000 {
compatible = "nvidia,tegra114-dsi";
reg = <0x54300000 0x00040000>;
clocks = <&tegra_car TEGRA114_CLK_DSIA>,
@@ -121,7 +121,7 @@ dsi@54300000 {
#size-cells = <0>;
};
- dsi@54400000 {
+ dsib: dsi@54400000 {
compatible = "nvidia,tegra114-dsi";
reg = <0x54400000 0x00040000>;
clocks = <&tegra_car TEGRA114_CLK_DSIB>,
@@ -335,7 +335,7 @@ pwm: pwm@7000a000 {
status = "disabled";
};
- i2c@7000c000 {
+ i2c1: i2c@7000c000 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -350,7 +350,7 @@ i2c@7000c000 {
status = "disabled";
};
- i2c@7000c400 {
+ i2c2: i2c@7000c400 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c400 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -365,7 +365,7 @@ i2c@7000c400 {
status = "disabled";
};
- i2c@7000c500 {
+ i2c3: i2c@7000c500 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c500 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -380,7 +380,7 @@ i2c@7000c500 {
status = "disabled";
};
- i2c@7000c700 {
+ i2c4: i2c@7000c700 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c700 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
@@ -395,7 +395,7 @@ i2c@7000c700 {
status = "disabled";
};
- i2c@7000d000 {
+ i2c5: i2c@7000d000 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000d000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
@@ -410,7 +410,7 @@ i2c@7000d000 {
status = "disabled";
};
- spi@7000d400 {
+ spi1: spi@7000d400 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d400 0x200>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
@@ -425,7 +425,7 @@ spi@7000d400 {
status = "disabled";
};
- spi@7000d600 {
+ spi2: spi@7000d600 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d600 0x200>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -440,7 +440,7 @@ spi@7000d600 {
status = "disabled";
};
- spi@7000d800 {
+ spi3: spi@7000d800 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d800 0x200>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -455,7 +455,7 @@ spi@7000d800 {
status = "disabled";
};
- spi@7000da00 {
+ spi4: spi@7000da00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000da00 0x200>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
@@ -470,7 +470,7 @@ spi@7000da00 {
status = "disabled";
};
- spi@7000dc00 {
+ spi5: spi@7000dc00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000dc00 0x200>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
@@ -485,7 +485,7 @@ spi@7000dc00 {
status = "disabled";
};
- spi@7000de00 {
+ spi6: spi@7000de00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000de00 0x200>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
@@ -500,14 +500,14 @@ spi@7000de00 {
status = "disabled";
};
- rtc@7000e000 {
+ tegra_rtc: rtc@7000e000 {
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_RTC>;
};
- kbc@7000e200 {
+ tegra_kbc: kbc@7000e200 {
compatible = "nvidia,tegra114-kbc";
reg = <0x7000e200 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -646,7 +646,7 @@ mipi: mipi@700e3000 {
#nvidia,mipi-calibrate-cells = <1>;
};
- mmc@78000000 {
+ sdmmc1: mmc@78000000 {
compatible = "nvidia,tegra114-sdhci";
reg = <0x78000000 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@@ -657,7 +657,7 @@ mmc@78000000 {
status = "disabled";
};
- mmc@78000200 {
+ sdmmc2: mmc@78000200 {
compatible = "nvidia,tegra114-sdhci";
reg = <0x78000200 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
@@ -668,7 +668,7 @@ mmc@78000200 {
status = "disabled";
};
- mmc@78000400 {
+ sdmmc3: mmc@78000400 {
compatible = "nvidia,tegra114-sdhci";
reg = <0x78000400 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@@ -679,7 +679,7 @@ mmc@78000400 {
status = "disabled";
};
- mmc@78000600 {
+ sdmmc4: mmc@78000600 {
compatible = "nvidia,tegra114-sdhci";
reg = <0x78000600 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
@@ -690,7 +690,7 @@ mmc@78000600 {
status = "disabled";
};
- usb@7d000000 {
+ usb1: usb@7d000000 {
compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
reg = <0x7d000000 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -698,11 +698,11 @@ usb@7d000000 {
clocks = <&tegra_car TEGRA114_CLK_USBD>;
resets = <&tegra_car 22>;
reset-names = "usb";
- nvidia,phy = <&phy1>;
+ nvidia,phy = <&usb1_phy>;
status = "disabled";
};
- phy1: usb-phy@7d000000 {
+ usb1_phy: usb-phy@7d000000 {
compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x7d000000 0x4000>,
<0x7d000000 0x4000>;
@@ -730,7 +730,7 @@ phy1: usb-phy@7d000000 {
status = "disabled";
};
- usb@7d008000 {
+ usb3: usb@7d008000 {
compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
reg = <0x7d008000 0x4000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
@@ -738,11 +738,11 @@ usb@7d008000 {
clocks = <&tegra_car TEGRA114_CLK_USB3>;
resets = <&tegra_car 59>;
reset-names = "usb";
- nvidia,phy = <&phy3>;
+ nvidia,phy = <&usb3_phy>;
status = "disabled";
};
- phy3: usb-phy@7d008000 {
+ usb3_phy: usb-phy@7d008000 {
compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x7d008000 0x4000>,
<0x7d000000 0x4000>;
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 05/28] ARM: tegra: Add device-tree for ASUS Transformer EeePad TF101
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (3 preceding siblings ...)
2021-12-11 21:13 ` [PATCH v6 04/28] ARM: tegra: Add labels to tegra114.dtsi Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 06/28] ARM: tegra: Add common device-tree base for Tegra30 ASUS Transformers Dmitry Osipenko
` (22 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Nikola Milosavljevic <mnidza@outlook.com>
Add device-tree for Tegra20-based ASUS Transformer EeePad TF101.
Link: https://wiki.postmarketos.org/wiki/ASUS_Eee_Pad_Transformer_(asus-tf101)
Co-developed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
Co-developed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Co-developed-by: Antoni Aloy Torrens <aaloytorrens@gmail.com>
Signed-off-by: Antoni Aloy Torrens <aaloytorrens@gmail.com>
Signed-off-by: Nikola Milosavljevic <mnidza@outlook.com>
Co-developed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/tegra20-asus-tf101.dts | 1228 ++++++++++++++++++++++
2 files changed, 1229 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra20-asus-tf101.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8a2dfdf01ce3..8fdebf7c1afe 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1304,6 +1304,7 @@ dtb-$(CONFIG_MACH_SUNIV) += \
suniv-f1c100s-licheepi-nano.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-acer-a500-picasso.dtb \
+ tegra20-asus-tf101.dtb \
tegra20-harmony.dtb \
tegra20-colibri-eval-v3.dtb \
tegra20-colibri-iris.dtb \
diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts
new file mode 100644
index 000000000000..e6cfb390d947
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts
@@ -0,0 +1,1228 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/atmel-maxtouch.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/thermal/thermal.h>
+
+#include "tegra20.dtsi"
+#include "tegra20-cpu-opp.dtsi"
+#include "tegra20-cpu-opp-microvolt.dtsi"
+
+/ {
+ model = "ASUS EeePad Transformer TF101";
+ compatible = "asus,tf101", "nvidia,tegra20";
+ chassis-type = "convertible";
+
+ aliases {
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc3; /* MicroSD */
+ mmc2 = &sdmmc1; /* WiFi */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ serial0 = &uartd;
+ serial1 = &uartc; /* Bluetooth */
+ serial2 = &uartb; /* GPS */
+ };
+
+ /*
+ * The decompressor and also some bootloaders rely on a
+ * pre-existing /chosen node to be available to insert the
+ * command line and merge other ATAGS info.
+ */
+ chosen {};
+
+ memory@0 {
+ reg = <0x00000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ramoops@2ffe0000 {
+ compatible = "ramoops";
+ reg = <0x2ffe0000 0x10000>; /* 64kB */
+ console-size = <0x8000>; /* 32kB */
+ record-size = <0x400>; /* 1kB */
+ ecc-size = <16>;
+ };
+
+ linux,cma@30000000 {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x30000000 0x10000000>;
+ size = <0x10000000>; /* 256MiB */
+ linux,cma-default;
+ reusable;
+ };
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ rgb {
+ status = "okay";
+
+ port@0 {
+ lcd_output: endpoint {
+ remote-endpoint = <&lvds_encoder_input>;
+ bus-width = <18>;
+ };
+ };
+ };
+ };
+
+ hdmi@54280000 {
+ status = "okay";
+
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+ hdmi-supply = <&vdd_hdmi_en>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio@6000d000 {
+ charging-enable-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+
+ pinmux@70000014 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata";
+ nvidia,function = "ide";
+ };
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+ atc {
+ nvidia,pins = "atc";
+ nvidia,function = "nand";
+ };
+ atd {
+ nvidia,pins = "atd", "ate", "gmb", "spia",
+ "spib", "spic";
+ nvidia,function = "gmi";
+ };
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+ crtp {
+ nvidia,pins = "crtp";
+ nvidia,function = "crt";
+ };
+ lm1 {
+ nvidia,pins = "lm1";
+ nvidia,function = "rsvd3";
+ };
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ };
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+ dap2 {
+ nvidia,pins = "dap2";
+ nvidia,function = "dap2";
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+ dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+ nvidia,function = "vi";
+ };
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+ gmc {
+ nvidia,pins = "gmc";
+ nvidia,function = "uartd";
+ };
+ gmd {
+ nvidia,pins = "gmd";
+ nvidia,function = "sflash";
+ };
+ gpu {
+ nvidia,pins = "gpu";
+ nvidia,function = "pwm";
+ };
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+ gpv {
+ nvidia,pins = "gpv", "slxa";
+ nvidia,function = "pcie";
+ };
+ hdint {
+ nvidia,pins = "hdint";
+ nvidia,function = "hdmi";
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uartb";
+ };
+ kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+ lcsn {
+ nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+ "lsdi", "lvp0";
+ nvidia,function = "rsvd4";
+ };
+ ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lpp", "lpw0",
+ "lpw2", "lsc0", "lsc1", "lsck", "lsda",
+ "lspi", "lvp1", "lvs";
+ nvidia,function = "displaya";
+ };
+ owc {
+ nvidia,pins = "owc", "spdi", "spdo", "uac";
+ nvidia,function = "rsvd2";
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+ sdb {
+ nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
+ nvidia,function = "sdio3";
+ };
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+ slxd {
+ nvidia,pins = "slxd";
+ nvidia,function = "spdif";
+ };
+ spid {
+ nvidia,pins = "spid", "spie", "spif";
+ nvidia,function = "spi1";
+ };
+ spig {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+ uaa {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ };
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "irda";
+ };
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+ conf_ata {
+ nvidia,pins = "ata", "atb", "atc", "atd",
+ "cdev1", "cdev2", "dap1", "dap4",
+ "dte", "ddc", "dtf", "gma", "gmc",
+ "gme", "gpu", "gpu7", "gpv", "i2cp",
+ "irrx", "irtx", "pta", "rm", "sdc",
+ "sdd", "slxc", "slxd", "slxk", "spdi",
+ "spdo", "uac", "uad",
+ "uda", "csus";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_ate {
+ nvidia,pins = "ate", "dap2", "dap3", "gmb", "gmd",
+ "owc", "spia", "spib", "spic",
+ "spid", "spie", "spig", "slxa";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+ "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ };
+ conf_crtp {
+ nvidia,pins = "crtp", "spih";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_spif {
+ nvidia,pins = "spif";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_hdint {
+ nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+ "lpw1", "lsck", "lsda", "lsdi", "lvp0";
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf", "sdio1", "uaa", "uab",
+ "uca", "ucb";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_lc {
+ nvidia,pins = "lc", "ls";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ };
+ conf_ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lm0", "lpp",
+ "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
+ "lvp1", "lvs", "pmc", "sdb";
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+ "ld23_22";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ };
+ drive_sdio1 {
+ nvidia,pins = "drive_sdio1", "drive_ddc", "drive_vi1";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+ drive_csus {
+ nvidia,pins = "drive_csus";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+ };
+
+ state_i2cmux_ddc: pinmux_i2cmux_ddc {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+
+ state_i2cmux_pta: pinmux_i2cmux_pta {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "i2c2";
+ };
+ };
+
+ state_i2cmux_idle: pinmux_i2cmux_idle {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+ };
+
+ i2s@70002800 {
+ status = "okay";
+ };
+
+ uartb: serial@70006040 {
+ compatible = "nvidia,tegra20-hsuart";
+ /* GPS BCM4751 */
+ };
+
+ uartc: serial@70006200 {
+ compatible = "nvidia,tegra20-hsuart";
+ status = "okay";
+
+ /* Azurewave AW-NH615 BCM4329B1 */
+ bluetooth {
+ compatible = "brcm,bcm4329-bt";
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "host-wakeup";
+
+ /* PLLP 216MHz / 16 / 4 */
+ max-speed = <3375000>;
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
+ clock-names = "txco";
+
+ vbat-supply = <&vdd_3v3_sys>;
+ vddio-supply = <&vdd_1v8_sys>;
+
+ device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ serial@70006300 {
+ status = "okay";
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Aichi AMI306 digital compass */
+ magnetometer@e {
+ compatible = "asahi-kasei,ak8974";
+ reg = <0xe>;
+
+ avdd-supply = <&vdd_3v3_sys>;
+ dvdd-supply = <&vdd_1v8_sys>;
+
+ mount-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "-1";
+ };
+
+ wm8903: audio-codec@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_BOTH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0x83>;
+ micdet-delay = <100>;
+
+ gpio-cfg = <
+ 0xffffffff /* don't touch */
+ 0xffffffff /* don't touch */
+ 0x00000000 /* Speaker-enable GPIO, output, low */
+ 0x00000400 /* Mic bias current detect */
+ 0xffffffff /* don't touch */
+ >;
+
+ AVDD-supply = <&vdd_1v8_sys>;
+ CPVDD-supply = <&vdd_1v8_sys>;
+ DBVDD-supply = <&vdd_1v8_sys>;
+ DCVDD-supply = <&vdd_1v8_sys>;
+ };
+
+ /* Atmel MXT1386 Touchscreen */
+ touchscreen@5b {
+ compatible = "atmel,maxtouch";
+ reg = <0x5b>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
+
+ vdda-supply = <&vdd_3v3_sys>;
+ vdd-supply = <&vdd_3v3_sys>;
+
+ atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>;
+ };
+
+ gyroscope@68 {
+ compatible = "invensense,mpu3050";
+ reg = <0x68>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&vdd_3v3_sys>;
+ vlogic-supply = <&vdd_1v8_sys>;
+
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
+
+ i2c-gate {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@f {
+ compatible = "kionix,kxtf9";
+ reg = <0xf>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(N, 4) IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&vdd_1v8_sys>;
+ vddio-supply = <&vdd_1v8_sys>;
+
+ mount-matrix = "1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "1";
+ };
+ };
+ };
+ };
+
+ i2c2: i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2cmux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-parent = <&i2c2>;
+
+ pinctrl-names = "ddc", "pta", "idle";
+ pinctrl-0 = <&state_i2cmux_ddc>;
+ pinctrl-1 = <&state_i2cmux_pta>;
+ pinctrl-2 = <&state_i2cmux_idle>;
+
+ hdmi_ddc: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ lvds_ddc: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ smart-battery@b {
+ compatible = "ti,bq20z75", "sbs,sbs-battery";
+ reg = <0xb>;
+ sbs,i2c-retry-count = <2>;
+ sbs,poll-retry-count = <10>;
+ power-supplies = <&mains>;
+ };
+ };
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: pmic@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&vdd_5v0_sys>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ sys_reg: sys {
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ vdd_core: sm0 {
+ regulator-name = "vdd_sm0,vdd_core";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
+ regulator-coupled-max-spread = <170000 550000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ nvidia,tegra-core-regulator;
+ };
+
+ vdd_cpu: sm1 {
+ regulator-name = "vdd_sm1,vdd_cpu";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1125000>;
+ regulator-coupled-with = <&vdd_core &rtc_vdd>;
+ regulator-coupled-max-spread = <550000 550000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ nvidia,tegra-cpu-regulator;
+ };
+
+ sm2_reg: sm2 {
+ regulator-name = "vdd_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ /* LDO0 is not connected to anything */
+
+ ldo1 {
+ regulator-name = "vdd_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ rtc_vdd: ldo2 {
+ regulator-name = "vdd_ldo2,vdd_rtc";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-coupled-with = <&vdd_core &vdd_cpu>;
+ regulator-coupled-max-spread = <170000 550000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ nvidia,tegra-rtc-regulator;
+ };
+
+ ldo3 {
+ regulator-name = "vdd_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo4 {
+ regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vcore_emmc: ldo5 {
+ regulator-name = "vdd_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo6 {
+ regulator-name = "vdd_ldo6,avdd_vdac";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ hdmi_vdd_reg: ldo7 {
+ regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ hdmi_pll_reg: ldo8 {
+ regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo9 {
+ regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo_rtc {
+ regulator-name = "vdd_rtc_out,vdd_cell";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ nct1008: temperature-sensor@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+ vcc-supply = <&vdd_3v3_sys>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>;
+
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ pmc@7000e400 {
+ nvidia,invert-interrupt;
+ nvidia,suspend-mode = <1>;
+ nvidia,cpu-pwr-good-time = <2000>;
+ nvidia,cpu-pwr-off-time = <100>;
+ nvidia,core-pwr-good-time = <3845 3845>;
+ nvidia,core-pwr-off-time = <458>;
+ nvidia,sys-clock-req-active-high;
+ core-supply = <&vdd_core>;
+ };
+
+ /* Peripheral USB via ASUS connector */
+ usb@c5000000 {
+ compatible = "nvidia,tegra20-udc";
+ status = "okay";
+ dr_mode = "peripheral";
+ };
+
+ usb-phy@c5000000 {
+ status = "okay";
+ dr_mode = "peripheral";
+ nvidia,xcvr-setup-use-fuses;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ vbus-supply = <&vdd_5v0_sys>;
+ };
+
+ /* Dock's USB port */
+ usb@c5008000 {
+ status = "okay";
+ };
+
+ usb-phy@c5008000 {
+ status = "okay";
+ nvidia,xcvr-setup-use-fuses;
+ vbus-supply = <&vdd_5v0_sys>;
+ };
+
+ brcm_wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
+ clock-names = "ext_clock";
+
+ reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ power-off-delay-us = <200>;
+ };
+
+ sdmmc1: mmc@c8000000 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
+ assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
+ assigned-clock-rates = <40000000>;
+
+ max-frequency = <40000000>;
+ keep-power-in-suspend;
+ bus-width = <4>;
+ non-removable;
+
+ mmc-pwrseq = <&brcm_wifi_pwrseq>;
+ vmmc-supply = <&vdd_3v3_sys>;
+ vqmmc-supply = <&vdd_3v3_sys>;
+
+ /* Azurewave AW-NH615 BCM4329B1 */
+ wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+ };
+
+ sdmmc3: mmc@c8000400 {
+ status = "okay";
+ bus-width = <4>;
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <&vdd_3v3_sys>;
+ vqmmc-supply = <&vdd_3v3_sys>;
+ };
+
+ sdmmc4: mmc@c8000600 {
+ status = "okay";
+ bus-width = <8>;
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_3v3_sys>;
+ non-removable;
+ };
+
+ mains: ac-adapter-detect {
+ compatible = "gpio-charger";
+ charger-type = "mains";
+ gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_3v3_sys>;
+ pwms = <&pwm 2 4000000>;
+
+ brightness-levels = <7 255>;
+ num-interpolated-steps = <248>;
+ default-brightness-level = <20>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k-in {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@1 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ dock-hall-sensor {
+ label = "Lid";
+ gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ debounce-interval = <500>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
+
+ display-panel {
+ compatible = "panel-lvds";
+
+ /* AUO B101EW05 using custom timings */
+
+ backlight = <&backlight>;
+ ddc-i2c-bus = <&lvds_ddc>;
+ power-supply = <&vdd_pnl_reg>;
+
+ width-mm = <218>;
+ height-mm = <135>;
+
+ data-mapping = "jeida-18";
+
+ panel-timing {
+ clock-frequency = <71200000>;
+ hactive = <1280>;
+ vactive = <800>;
+ hfront-porch = <8>;
+ hback-porch = <18>;
+ hsync-len = <184>;
+ vsync-len = <3>;
+ vfront-porch = <4>;
+ vback-porch = <8>;
+ };
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&lvds_encoder_output>;
+ };
+ };
+ };
+
+ lvds-encoder {
+ compatible = "ti,sn75lvds83", "lvds-encoder";
+
+ powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
+ power-supply = <&vdd_3v3_sys>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lvds_encoder_input: endpoint {
+ remote-endpoint = <&lcd_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds_encoder_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+ };
+
+ vdd_5v0_sys: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_3v3_sys: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3_vs";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ regulator-pcie {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie_vdd";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ };
+
+ vdd_pnl_reg: regulator-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_pnl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_1v8_sys: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v8_vs";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_hdmi_en: regulator-hdmi {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0_hdmi_en";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ vin-supply = <&vdd_5v0_sys>;
+ gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "asus,tegra-audio-wm8903-tf101",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "Asus EeePad Transformer WM8903";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "Mic Jack", "MICBIAS",
+ "IN1L", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ nvidia,headset;
+
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+ };
+
+ thermal-zones {
+ /*
+ * NCT1008 has two sensors:
+ *
+ * 0: internal that monitors ambient/skin temperature
+ * 1: external that is connected to the CPU's diode
+ *
+ * Ideally we should use userspace thermal governor,
+ * but it's a much more complex solution. The "skin"
+ * zone is a simpler solution which prevents TF101 from
+ * getting too hot from a user's tactile perspective.
+ * The CPU zone is intended to protect silicon from damage.
+ */
+
+ skin-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&nct1008 0>;
+
+ trips {
+ trip0: skin-alert {
+ /* start throttling at 60C */
+ temperature = <60000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+
+ trip1: skin-crit {
+ /* shut down at 70C */
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&trip0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&nct1008 1>;
+
+ trips {
+ trip2: cpu-alert {
+ /* throttle at 85C until temperature drops to 84.8C */
+ temperature = <85000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+
+ trip3: cpu-crit {
+ /* shut down at 90C */
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&trip2>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ memory-controller@7000f400 {
+ nvidia,use-ram-code;
+
+ emc-tables@3 {
+ reg = <0x3>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lpddr2 {
+ compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";
+ revision-id1 = <1>;
+ density = <2048>;
+ io-width = <16>;
+ };
+
+ emc-table@25000 {
+ reg = <25000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <25000>;
+ nvidia,emc-registers = <0x00000002 0x00000006
+ 0x00000003 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000004
+ 0x00000003 0x00000008 0x0000000b 0x0000004d
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000004
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000068 0x00000000 0x00000003
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x00070000 0x00000000 0x00000000 0x00000003
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@50000 {
+ reg = <50000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <50000>;
+ nvidia,emc-registers = <0x00000003 0x00000007
+ 0x00000003 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x0000009f
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000007
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x000000d0 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x00070000 0x00000000 0x00000000 0x00000005
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@75000 {
+ reg = <75000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <75000>;
+ nvidia,emc-registers = <0x00000005 0x0000000a
+ 0x00000004 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x000000ff
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x0000000b
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000138 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x00070000 0x00000000 0x00000000 0x00000007
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@150000 {
+ reg = <150000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <150000>;
+ nvidia,emc-registers = <0x00000009 0x00000014
+ 0x00000007 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x0000021f
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000015
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000270 0x00000000 0x00000001
+ 0x00000000 0x00000000 0x00000282 0xa07c04ae
+ 0x007dc010 0x00000000 0x00000000 0x0000000e
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@300000 {
+ reg = <300000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <300000>;
+ nvidia,emc-registers = <0x00000012 0x00000027
+ 0x0000000d 0x00000006 0x00000007 0x00000005
+ 0x00000003 0x00000009 0x00000006 0x00000006
+ 0x00000003 0x00000003 0x00000002 0x00000006
+ 0x00000003 0x00000009 0x0000000c 0x0000045f
+ 0x00000000 0x00000004 0x00000004 0x00000006
+ 0x00000008 0x00000001 0x0000000e 0x0000002a
+ 0x00000003 0x0000000f 0x00000007 0x00000005
+ 0x00000002 0x000004e0 0x00000005 0x00000002
+ 0x00000000 0x00000000 0x00000282 0xe059048b
+ 0x007e0010 0x00000000 0x00000000 0x0000001b
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
+ };
+};
+
+&emc_icc_dvfs_opp_table {
+ /delete-node/ opp-666000000;
+ /delete-node/ opp-760000000;
+};
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 06/28] ARM: tegra: Add common device-tree base for Tegra30 ASUS Transformers
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (4 preceding siblings ...)
2021-12-11 21:13 ` [PATCH v6 05/28] ARM: tegra: Add device-tree for ASUS Transformer EeePad TF101 Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 07/28] ARM: tegra: Add common device-tree for LVDS display panels of Tegra30 ASUS tablets Dmitry Osipenko
` (21 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Svyatoslav Ryhel <clamor95@gmail.com>
Add common DTSI for Tegra30 ASUS Transformers. It will be used by multiple
device-trees of ASUS devices. The common part initially was born out of
the ASUS TF300T tablet's device-tree that was created by Michał Mirosław.
It was heavily reworked and improved by Svyatoslav Ryhel, Maxim Schwalm,
Ion Agorria et al.
[digetx@gmail.com: factored out common part into separate patch and wrote commit message]
Co-developed-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Ion Agorria <ion@agorria.com>
Co-developed-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Co-developed-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
.../dts/tegra30-asus-transformer-common.dtsi | 1729 +++++++++++++++++
1 file changed, 1729 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi
diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi
new file mode 100644
index 000000000000..90226ab709f0
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi
@@ -0,0 +1,1729 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/thermal/thermal.h>
+
+#include "tegra30.dtsi"
+#include "tegra30-cpu-opp.dtsi"
+#include "tegra30-cpu-opp-microvolt.dtsi"
+
+/ {
+ chassis-type = "convertible";
+
+ aliases {
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc1; /* uSD slot */
+ mmc2 = &sdmmc3; /* WiFi */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ display0 = &lcd;
+ display1 = &hdmi;
+
+ serial1 = &uartc; /* Bluetooth */
+ serial2 = &uartb; /* GPS */
+ };
+
+ /*
+ * The decompressor and also some bootloaders rely on a
+ * pre-existing /chosen node to be available to insert the
+ * command line and merge other ATAGS info.
+ */
+ chosen {};
+
+ memory@80000000 {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,cma@80000000 {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x80000000 0x30000000>;
+ size = <0x10000000>; /* 256MiB */
+ linux,cma-default;
+ reusable;
+ };
+
+ ramoops@beb00000 {
+ compatible = "ramoops";
+ reg = <0xbeb00000 0x10000>; /* 64kB */
+ console-size = <0x8000>; /* 32kB */
+ record-size = <0x400>; /* 1kB */
+ ecc-size = <16>;
+ };
+
+ trustzone@bfe00000 {
+ reg = <0xbfe00000 0x200000>; /* 2MB */
+ no-map;
+ };
+ };
+
+ host1x@50000000 {
+ hdmi: hdmi@54280000 {
+ status = "okay";
+
+ hdmi-supply = <&hdmi_5v0_sys>;
+ pll-supply = <&vdd_1v8_vio>;
+ vdd-supply = <&vdd_3v3_sys>;
+
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ };
+ };
+
+ gpio@6000d000 {
+ init-lpm-in-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ };
+
+ init-lpm-out-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(K, 7) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+
+ usb-charge-limit-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
+ output-high;
+ };
+ };
+
+ vde@6001a000 {
+ assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
+ assigned-clock-rates = <408000000>;
+ };
+
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* SDMMC1 pinmux */
+ sdmmc1_clk {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_cmd {
+ nvidia,pins = "sdmmc1_dat3_py4",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_cd {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_wp {
+ nvidia,pins = "vi_d11_pt3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC2 pinmux */
+ vi_d1_pd5 {
+ nvidia,pins = "vi_d1_pd5",
+ "vi_d2_pl0",
+ "vi_d3_pl1",
+ "vi_d5_pl3",
+ "vi_d7_pl5";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ vi_d8_pl6 {
+ nvidia,pins = "vi_d8_pl6",
+ "vi_d9_pl7";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+
+ /* SDMMC3 pinmux */
+ sdmmc3_clk {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_cmd {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4",
+ "sdmmc3_dat4_pd1",
+ "sdmmc3_dat5_pd0",
+ "sdmmc3_dat6_pd3",
+ "sdmmc3_dat7_pd4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC4 pinmux */
+ sdmmc4_clk {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_cmd {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_rst_n {
+ nvidia,pins = "sdmmc4_rst_n_pcc3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_mclk {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ drive_sdmmc4 {
+ nvidia,pins = "drive_gma",
+ "drive_gmb",
+ "drive_gmc",
+ "drive_gmd";
+ nvidia,pull-down-strength = <9>;
+ nvidia,pull-up-strength = <9>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+
+ /* I2C pinmux */
+ gen1_i2c {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ gen2_i2c {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ cam_i2c {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ ddc_i2c {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ pwr_i2c {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ hotplug_i2c {
+ nvidia,pins = "pu4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* HDMI pinmux */
+ hdmi_cec {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ hdmi_hpd {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "hdmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-A */
+ ulpi_data0_po1 {
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data1_po2 {
+ nvidia,pins = "ulpi_data1_po2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_data5_po6 {
+ nvidia,pins = "ulpi_data5_po6";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_data7_po0 {
+ nvidia,pins = "ulpi_data7_po0",
+ "ulpi_data2_po3",
+ "ulpi_data3_po4",
+ "ulpi_data4_po5",
+ "ulpi_data6_po7";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-B */
+ uartb_txd_rts {
+ nvidia,pins = "uart2_txd_pc2",
+ "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uartb_rxd_cts {
+ nvidia,pins = "uart2_rxd_pc3",
+ "uart2_cts_n_pj5";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-C */
+ uartc_rxd_cts {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartc_txd_rts {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* UART-D */
+ ulpi_nxt_py2 {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_dir_py1",
+ "ulpi_stp_py3";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* I2S pinmux */
+ dap_i2s0 {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap_i2s1 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_fs {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_dout {
+ nvidia,pins = "dap3_dout_pp2",
+ "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap_i2s3 {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Sensors pinmux */
+ nct_irq {
+ nvidia,pins = "pcc2";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Asus EC pinmux */
+ ec_irqs {
+ nvidia,pins = "kb_row10_ps2",
+ "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ec_reqs {
+ nvidia,pins = "kb_col1_pq1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Memory type bootstrap */
+ mem_boostraps {
+ nvidia,pins = "gmi_ad4_pg4",
+ "gmi_ad5_pg5";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PCI-e pinmux */
+ pex_l2_rst_n {
+ nvidia,pins = "pex_l2_rst_n_pcc6",
+ "pex_l0_rst_n_pdd1",
+ "pex_l1_rst_n_pdd5";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pex_l2_clkreq_n {
+ nvidia,pins = "pex_l2_clkreq_n_pcc7",
+ "pex_l0_prsnt_n_pdd0",
+ "pex_l0_clkreq_n_pdd2",
+ "pex_wake_n_pdd3",
+ "pex_l1_prsnt_n_pdd4",
+ "pex_l1_clkreq_n_pdd6",
+ "pex_l2_prsnt_n_pdd7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SPI pinmux */
+ spi1_mosi_px4 {
+ nvidia,pins = "spi1_mosi_px4",
+ "spi1_sck_px5",
+ "spi1_cs0_n_px6",
+ "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2_cs1_n_pw2 {
+ nvidia,pins = "spi2_cs1_n_pw2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2_sck_px2 {
+ nvidia,pins = "spi2_sck_px2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_a17_pb0 {
+ nvidia,pins = "gmi_a17_pb0",
+ "gmi_a16_pj7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_a18_pb1 {
+ nvidia,pins = "gmi_a18_pb1";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_a19_pk7 {
+ nvidia,pins = "gmi_a19_pk7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Display A pinmux */
+ lcd_pwr0_pb2 {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pclk_pb3",
+ "lcd_pwr1_pc1",
+ "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_de_pj1",
+ "lcd_hsync_pj3",
+ "lcd_vsync_pj4",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7",
+ "lcd_dc0_pn6",
+ "lcd_sdin_pz2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_cs0_n_pn4 {
+ nvidia,pins = "lcd_cs0_n_pn4",
+ "lcd_sdout_pn5",
+ "lcd_wr_n_pz3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ blink {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "blink";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* KBC keys */
+ kb_col0_pq0 {
+ nvidia,pins = "kb_col0_pq0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col1_pq1 {
+ nvidia,pins = "kb_row1_pr1",
+ "kb_row3_pr3",
+ "kb_row8_ps0",
+ "kb_row14_ps6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col4_pq4 {
+ nvidia,pins = "kb_col4_pq4",
+ "kb_col5_pq5",
+ "kb_col7_pq7",
+ "kb_row2_pr2",
+ "kb_row4_pr4",
+ "kb_row5_pr5",
+ "kb_row12_ps4",
+ "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_wp_n_pc7 {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_wait_pi7",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_cs0_n_pj0 {
+ nvidia,pins = "gmi_cs0_n_pj0",
+ "gmi_cs1_n_pj2",
+ "gmi_cs2_n_pk3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ vi_pclk_pt0 {
+ nvidia,pins = "vi_pclk_pt0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+
+ /* GPIO keys pinmux */
+ power_key {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ vol_keys {
+ nvidia,pins = "kb_col2_pq2",
+ "kb_col3_pq3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Bluetooth */
+ bt_shutdown {
+ nvidia,pins = "pu0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ bt_dev_wake {
+ nvidia,pins = "pu1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt_host_wake {
+ nvidia,pins = "pu6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pu2 {
+ nvidia,pins = "pu2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pcc1 {
+ nvidia,pins = "pcc1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pv2 {
+ nvidia,pins = "pv2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pv3 {
+ nvidia,pins = "pv3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ vi_vsync_pd6 {
+ nvidia,pins = "vi_vsync_pd6",
+ "vi_hsync_pd7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+ vi_d10_pt2 {
+ nvidia,pins = "vi_d10_pt2",
+ "vi_d0_pt4", "pbb0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad0_pg0 {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad1_pg1",
+ "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7",
+ "gmi_wr_n_pi0",
+ "gmi_oe_n_pi1",
+ "gmi_dqs_pi2",
+ "gmi_adv_n_pk0",
+ "gmi_clk_pk1";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad13_ph5 {
+ nvidia,pins = "gmi_ad13_ph5";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_ad10_ph2 {
+ nvidia,pins = "gmi_ad10_ph2",
+ "gmi_ad11_ph3",
+ "gmi_ad14_ph6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad12_ph4 {
+ nvidia,pins = "gmi_ad12_ph4",
+ "gmi_rst_n_pi4",
+ "gmi_cs7_n_pi6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Vibrator control */
+ vibrator {
+ nvidia,pins = "gmi_ad15_ph7";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PWM pimnmux */
+ pwm_0 {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pwm_2 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_cs6_n_pi3 {
+ nvidia,pins = "gmi_cs6_n_pi3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Spdif pinmux */
+ spdif_out {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_in {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ vi_d4_pl2 {
+ nvidia,pins = "vi_d4_pl2";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ vi_d6_pl4 {
+ nvidia,pins = "vi_d6_pl4";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+ vi_mclk_pt1 {
+ nvidia,pins = "vi_mclk_pt1";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ jtag_rtck {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ crt_hsync_pv6 {
+ nvidia,pins = "crt_hsync_pv6",
+ "crt_vsync_pv7";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ clk1_out {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_out {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk3_out {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sys_clk_req {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "sysclk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb6 {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk2_req_pcc5 {
+ nvidia,pins = "clk2_req_pcc5",
+ "clk1_req_pee2";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk3_req_pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive_dap1 {
+ nvidia,pins = "drive_dap1",
+ "drive_dap2",
+ "drive_dbg",
+ "drive_at5",
+ "drive_gme",
+ "drive_ddc",
+ "drive_ao1",
+ "drive_uart3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ drive_sdio1 {
+ nvidia,pins = "drive_sdio1",
+ "drive_sdio3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
+ };
+ };
+ };
+
+ uartb: serial@70006040 {
+ compatible = "nvidia,tegra30-hsuart";
+ status = "okay";
+
+ /* Broadcom GPS BCM47511 */
+ };
+
+ uartc: serial@70006200 {
+ compatible = "nvidia,tegra30-hsuart";
+ status = "okay";
+
+ nvidia,adjust-baud-rates = <0 9600 100>,
+ <9600 115200 200>,
+ <1000000 4000000 136>;
+
+ bluetooth {
+ max-speed = <4000000>;
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
+ clock-names = "txco";
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "host-wakeup";
+
+ device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
+
+ vbat-supply = <&vdd_3v3_com>;
+ vddio-supply = <&vdd_1v8_vio>;
+ };
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ lcd_ddc: i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c3: i2c@7000c500 {
+ status = "okay";
+
+ /* Aichi AMI306 digital compass */
+ magnetometer@e {
+ compatible = "asahi-kasei,ak8974";
+ reg = <0x0e>;
+
+ avdd-supply = <&vdd_3v3_sys>;
+ dvdd-supply = <&vdd_1v8_vio>;
+ };
+
+ /* Dynaimage ambient light sensor */
+ light-sensor@1c {
+ compatible = "dynaimage,al3010";
+ reg = <0x1c>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
+
+ vdd-supply = <&vdd_3v3_sys>;
+ };
+
+ gyroscope@68 {
+ compatible = "invensense,mpu3050";
+ reg = <0x68>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&vdd_3v3_sys>;
+ vlogic-supply = <&vdd_1v8_vio>;
+
+ i2c-gate {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@f {
+ compatible = "kionix,kxtf9";
+ reg = <0x0f>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(O, 5) IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&vdd_1v8_vio>;
+ vddio-supply = <&vdd_1v8_vio>;
+ };
+ };
+ };
+ };
+
+ hdmi_ddc: i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <93750>;
+ };
+
+ i2c5: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ nct72: temperature-sensor@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
+
+ vcc-supply = <&vdd_3v3_sys>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ /* Texas Instruments TPS659110 PMIC */
+ pmic: pmic@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ wakeup-source;
+
+ ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
+ ti,system-power-controller;
+ ti,sleep-keep-ck32k;
+ ti,sleep-enable;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ vcc1-supply = <&vdd_5v0_bat>;
+ vcc2-supply = <&vdd_5v0_bat>;
+ vcc3-supply = <&vdd_1v8_vio>;
+ vcc4-supply = <&vdd_5v0_sys>;
+ vcc5-supply = <&vdd_5v0_bat>;
+ vcc6-supply = <&vdd_3v3_sys>;
+ vcc7-supply = <&vdd_5v0_bat>;
+ vccio-supply = <&vdd_5v0_bat>;
+
+ pmic-sleep-hog {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+
+ regulators {
+ /* VDD1 is not used by Transformers */
+
+ vddio_ddr: vdd2 {
+ regulator-name = "vddio_ddr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_cpu: vddctrl {
+ regulator-name = "vdd_cpu,vdd_sys";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-coupled-with = <&vdd_core>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,regulator-ext-sleep-control = <1>;
+
+ nvidia,tegra-cpu-regulator;
+ };
+
+ vdd_1v8_vio: vio {
+ regulator-name = "vdd_1v8_gen";
+ /* FIXME: eMMC won't work, if set to 1.8 V */
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* eMMC VDD */
+ vcore_emmc: ldo1 {
+ regulator-name = "vdd_emmc_core";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ /* uSD slot VDD */
+ vdd_usd: ldo2 {
+ regulator-name = "vdd_usd";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ /* FIXME: Without this, voltage switching fails */
+ regulator-always-on;
+ };
+
+ /* uSD slot VDDIO */
+ vddio_usd: ldo3 {
+ regulator-name = "vddio_usd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3100000>;
+ };
+
+ ldo4 {
+ regulator-name = "vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ /* LDO5 is not used by Transformers */
+
+ ldo6 {
+ regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo7 {
+ regulator-name = "vdd_pllm,x,u,a_p_c_s";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,regulator-ext-sleep-control = <8>;
+ };
+
+ ldo8 {
+ regulator-name = "vdd_ddr_hs";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ ti,regulator-ext-sleep-control = <8>;
+ };
+ };
+ };
+
+ vdd_core: core-regulator@60 {
+ compatible = "ti,tps62361";
+ reg = <0x60>;
+
+ regulator-name = "tps62361-vout";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1770000>;
+ regulator-coupled-with = <&vdd_cpu>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ti,enable-vout-discharge;
+ ti,vsel0-state-high;
+ ti,vsel1-state-high;
+
+ nvidia,tegra-core-regulator;
+ };
+ };
+
+ vdd_5v0_bat: regulator-bat {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_ac_bat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_5v0_cp: regulator-sby {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0_sby";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_bat>;
+ };
+
+ vdd_5v0_sys: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_bat>;
+ };
+
+ vdd_1v5_ddr: regulator-ddr {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_bat>;
+ };
+
+ vdd_3v3_sys: regulator-3v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_bat>;
+ };
+
+ vdd_pnl: regulator-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <20000>;
+ gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ vdd_3v3_com: regulator-com {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3_com";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ vdd_5v0_bl: regulator-bl {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0_bl";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_bat>;
+ };
+
+ hdmi_5v0_sys: regulator-hdmi {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi_5v0_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ pmc@7000e400 {
+ status = "okay";
+ nvidia,invert-interrupt;
+ /* FIXME: LP1 doesn't work at the moment */
+ nvidia,suspend-mode = <2>;
+ nvidia,cpu-pwr-good-time = <2000>;
+ nvidia,cpu-pwr-off-time = <200>;
+ nvidia,core-pwr-good-time = <3845 3845>;
+ nvidia,core-pwr-off-time = <0>;
+ nvidia,core-power-req-active-high;
+ nvidia,sys-clock-req-active-high;
+ core-supply = <&vdd_core>;
+
+ /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */
+ i2c-thermtrip {
+ nvidia,i2c-controller-id = <4>;
+ nvidia,bus-addr = <0x2d>;
+ nvidia,reg-addr = <0x3f>;
+ nvidia,reg-data = <0x81>;
+ };
+ };
+
+ hda@70030000 {
+ status = "okay";
+ };
+
+ ahub@70080000 {
+ i2s@70080400 { /* i2s1 */
+ status = "okay";
+ };
+
+ /* BT SCO */
+ i2s@70080600 { /* i2s3 */
+ status = "okay";
+ };
+ };
+
+ sdmmc1: mmc@78000000 {
+ status = "okay";
+
+ /* FIXME: Full 208Mhz clock rate doesn't work reliably */
+ max-frequency = <104000000>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+
+ vmmc-supply = <&vdd_usd>; /* ldo2 */
+ vqmmc-supply = <&vddio_usd>; /* ldo3 */
+ };
+
+ brcm_wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
+ clock-names = "ext_clock";
+
+ reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <300>;
+ power-off-delay-us = <300>;
+ };
+
+ sdmmc3: mmc@78000400 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
+ assigned-clock-rates = <50000000>;
+
+ max-frequency = <50000000>;
+ keep-power-in-suspend;
+ bus-width = <4>;
+ non-removable;
+
+ mmc-pwrseq = <&brcm_wifi_pwrseq>;
+ vmmc-supply = <&vdd_3v3_com>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+
+ /* Azurewave AW-NH615 BCM4329B1 or AW-NH665 BCM4330B1 */
+ wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+ };
+
+ sdmmc4: mmc@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ mmc-ddr-3_3v;
+ non-removable;
+ };
+
+ /* USB via ASUS connector */
+ usb@7d000000 {
+ compatible = "nvidia,tegra30-udc";
+ status = "okay";
+ dr_mode = "peripheral";
+ };
+
+ usb-phy@7d000000 {
+ status = "okay";
+ dr_mode = "peripheral";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ vbus-supply = <&vdd_5v0_sys>;
+ };
+
+ /* Dock's USB port */
+ usb@7d008000 {
+ status = "okay";
+ };
+
+ usb-phy@7d008000 {
+ status = "okay";
+ vbus-supply = <&vdd_5v0_bat>;
+ };
+
+ mains: ac-adapter-detect {
+ compatible = "gpio-charger";
+ charger-type = "mains";
+ gpios = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_5v0_bl>;
+ pwms = <&pwm 0 4000000>;
+
+ brightness-levels = <1 255>;
+ num-interpolated-steps = <254>;
+ default-brightness-level = <40>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ cpu1: cpu@1 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ cpu2: cpu@2 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ cpu3: cpu@3 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ extcon-keys {
+ compatible = "gpio-keys";
+ interrupt-parent = <&gpio>;
+
+ dock-hall-sensor {
+ label = "Lid sensor";
+ gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ debounce-interval = <500>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ lineout-detect {
+ label = "Audio dock line-out detect";
+ gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LINEOUT_INSERT>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
+
+ firmware {
+ trusted-foundations {
+ compatible = "tlm,trusted-foundations";
+ tlm,version-major = <2>;
+ tlm,version-minor = <8>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ interrupt-parent = <&gpio>;
+
+ power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
+
+ sound {
+ nvidia,i2s-controller = <&tegra_i2s1>;
+
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ nvidia,hp-mute-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>;
+
+ clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+ <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
+ };
+
+ thermal-zones {
+ /*
+ * NCT72 has two sensors:
+ *
+ * 0: internal that monitors ambient/skin temperature
+ * 1: external that is connected to the CPU's diode
+ *
+ * Ideally we should use userspace thermal governor,
+ * but it's a much more complex solution. The "skin"
+ * zone exists as a simpler solution which prevents
+ * Transformers from getting too hot from a user's
+ * tactile perspective. The CPU zone is intended to
+ * protect silicon from damage.
+ */
+
+ skin-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&nct72 0>;
+
+ trips {
+ trip0: skin-alert {
+ /* throttle at 57C until temperature drops to 56.8C */
+ temperature = <57000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+
+ trip1: skin-crit {
+ /* shut down at 65C */
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&trip0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&actmon THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&nct72 1>;
+
+ trips {
+ trip2: cpu-alert {
+ /* throttle at 75C until temperature drops to 74.8C */
+ temperature = <75000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+
+ trip3: cpu-crit {
+ /* shut down at 90C */
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&trip2>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&actmon THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+};
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 07/28] ARM: tegra: Add common device-tree for LVDS display panels of Tegra30 ASUS tablets
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (5 preceding siblings ...)
2021-12-11 21:13 ` [PATCH v6 06/28] ARM: tegra: Add common device-tree base for Tegra30 ASUS Transformers Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 08/28] ARM: tegra: Add device-tree for ASUS Transformer Prime TF201 Dmitry Osipenko
` (20 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Maxim Schwalm <maxim.schwalm@gmail.com>
All Tegra30 ASUS tablets have a similar design pattern in terms of
hardware integration of LVDS display panels, like exactly the same GPIOs
are used for power and reset, etc. Add a common device-tree for LVDS
display panels of Tegra30 ASUS tablets to avoid replicating the
boilerplate panel description.
[digetx@gmail.com: factored out common part into separate patch and wrote commit message]
Co-developed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
.../boot/dts/tegra30-asus-lvds-display.dtsi | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi
diff --git a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi
new file mode 100644
index 000000000000..a047abfa6369
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */
+
+/ {
+ host1x@50000000 {
+ lcd: dc@54200000 {
+ rgb {
+ status = "okay";
+
+ port@0 {
+ dpi_output: endpoint {
+ remote-endpoint = <&bridge_input>;
+ bus-width = <24>;
+ };
+ };
+ };
+ };
+ };
+
+ display-panel {
+ power-supply = <&vdd_pnl>;
+ ddc-i2c-bus = <&lcd_ddc>;
+ backlight = <&backlight>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&bridge_output>;
+ };
+ };
+ };
+
+ /* Texas Instruments SN75LVDS83B LVDS Transmitter */
+ lvds-encoder {
+ compatible = "ti,sn75lvds83", "lvds-encoder";
+
+ powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
+ power-supply = <&vdd_3v3_sys>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ bridge_input: endpoint {
+ remote-endpoint = <&dpi_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ bridge_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+ };
+};
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 08/28] ARM: tegra: Add device-tree for ASUS Transformer Prime TF201
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (6 preceding siblings ...)
2021-12-11 21:13 ` [PATCH v6 07/28] ARM: tegra: Add common device-tree for LVDS display panels of Tegra30 ASUS tablets Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-15 13:28 ` Thierry Reding
2021-12-11 21:13 ` [PATCH v6 09/28] ARM: tegra: Add device-tree for ASUS Transformer Pad TF300T Dmitry Osipenko
` (19 subsequent siblings)
27 siblings, 1 reply; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Svyatoslav Ryhel <clamor95@gmail.com>
Add device-tree for ASUS Transformer Prime TF201, which is a NVIDIA
Tegra30-based 2-in-1 detachable, orignally running Android.
Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Prime_(asus-tf201)
Co-developed-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Ion Agorria <ion@agorria.com>
Co-developed-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/tegra30-asus-tf201.dts | 623 +++++++++++++++++++++++
2 files changed, 624 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra30-asus-tf201.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8fdebf7c1afe..a72aab08e4db 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1321,6 +1321,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-asus-nexus7-grouper-PM269.dtb \
tegra30-asus-nexus7-grouper-E1565.dtb \
tegra30-asus-nexus7-tilapia-E1565.dtb \
+ tegra30-asus-tf201.dtb \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
diff --git a/arch/arm/boot/dts/tegra30-asus-tf201.dts b/arch/arm/boot/dts/tegra30-asus-tf201.dts
new file mode 100644
index 000000000000..76bbb1b67119
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-tf201.dts
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-transformer-common.dtsi"
+#include "tegra30-asus-lvds-display.dtsi"
+
+/ {
+ model = "Asus Transformer Prime TF201";
+ compatible = "asus,tf201", "nvidia,tegra30";
+
+ pinmux@70000868 {
+ state_default: pinmux {
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6",
+ "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_cs4_n_pk2 {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
+ uartc: serial@70006200 {
+ /* Azurewave AW-NH615 BCM4329B1 */
+ bluetooth {
+ compatible = "brcm,bcm4329-bt";
+ };
+ };
+
+ i2c@7000c400 {
+ /* Atmel MXT768E touchscreen */
+ touchscreen@4d {
+ compatible = "atmel,maxtouch";
+ reg = <0x4d>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>;
+
+ vdda-supply = <&vdd_3v3_sys>;
+ vdd-supply = <&vdd_3v3_sys>;
+ };
+ };
+
+ i2c@7000c500 {
+ clock-frequency = <100000>;
+
+ magnetometer@e {
+ mount-matrix = "-1", "0", "0",
+ "0", "-1", "0",
+ "0", "0", "-1";
+ };
+
+ gyroscope@68 {
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "-1";
+
+ /* External I2C interface */
+ i2c-gate {
+ accelerometer@f {
+ mount-matrix = "1", "0", "0",
+ "0", "-1", "0",
+ "0", "0", "1";
+ };
+ };
+ };
+ };
+
+ i2c@7000d000 {
+ /* Realtek ALC5631 audio codec */
+ rt5631: audio-codec@1a {
+ compatible = "realtek,rt5631";
+ reg = <0x1a>;
+ };
+ };
+
+ usb-phy@7d000000 {
+ /delete-property/ nvidia,xcvr-setup-use-fuses;
+ nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */
+ };
+
+ usb-phy@7d008000 {
+ /delete-property/ nvidia,xcvr-setup-use-fuses;
+ nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */
+ };
+
+ display-panel {
+ compatible = "hannstar,hsd101pww2";
+ };
+
+ haptic-feedback {
+ compatible = "gpio-vibrator";
+ enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
+ vcc-supply = <&vdd_3v3_sys>;
+ };
+
+ memory-controller@7000f000 {
+ emc-timings-0 {
+ /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */
+ nvidia,ram-code = <0>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00020001 0x80000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x73e30303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010001 0x80000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x72c30303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000001 0x80000018
+ 0x00000001 0x00000001 0x00000003 0x00000001
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060403 0x72430504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0x80000025
+ 0x00000001 0x00000001 0x00000006 0x00000003
+ 0x00000005 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000003 0x00000002
+ 0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
+ };
+
+ timing-400000000 {
+ clock-frequency = <400000000>;
+
+ nvidia,emem-configuration = < 0x00000006 0x80000048
+ 0x00000002 0x00000003 0x0000000c 0x00000007
+ 0x00000009 0x00000001 0x00000002 0x00000006
+ 0x00000001 0x00000000 0x00000004 0x00000004
+ 0x04040001 0x000d090c 0x71c6120d 0x001f0000 >;
+ };
+ };
+
+ emc-timings-1 {
+ /* TF201 Unknown 1GB LPDDR2 500MHZ */
+ nvidia,ram-code = <1>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00020001 0x80000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x73e30303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010001 0x80000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x72c30303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000001 0x80000018
+ 0x00000001 0x00000001 0x00000003 0x00000001
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060403 0x72430504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0x80000025
+ 0x00000001 0x00000001 0x00000006 0x00000003
+ 0x00000005 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000003 0x00000002
+ 0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
+ };
+
+ timing-500000000 {
+ clock-frequency = <500000000>;
+
+ nvidia,emem-configuration = < 0x00000007 0x8000005a
+ 0x00000003 0x00000004 0x0000000e 0x00000009
+ 0x0000000c 0x00000002 0x00000002 0x00000008
+ 0x00000001 0x00000000 0x00000004 0x00000005
+ 0x05040001 0x00100a0e 0x71c8170f 0x001f0000 >;
+ };
+ };
+ };
+
+ memory-controller@7000f400 {
+ emc-timings-0 {
+ /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */
+ nvidia,ram-code = <0>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000003 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x0000000a 0x00000060 0x00000000 0x00000018
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000004 0x00000004
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x0000006b 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x00780084
+ 0x00008000 0x00098000 0x00098000 0x00098000
+ 0x00098000 0x00000010 0x00000010 0x00000010
+ 0x00000010 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000008 0x00000008 0x00000008
+ 0x00000008 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00000000
+ 0x00000009 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000003
+ 0x00000006 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x0000000a 0x000000c0 0x00000000 0x00000030
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000008 0x00000008
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000000d5 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x00780084
+ 0x00008000 0x00098000 0x00098000 0x00098000
+ 0x00098000 0x00000010 0x00000010 0x00000010
+ 0x00000010 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000018 0x00000018 0x00000018
+ 0x00000018 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00000000
+ 0x00000009 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x0000000a>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000006
+ 0x0000000d 0x00000004 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x0000000a 0x00000181 0x00000000 0x00000060
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x0000000f 0x0000000f
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000001a9 0x00000004 0x00000006
+ 0x00000000 0x00000000 0x00004282 0x00780084
+ 0x00008000 0x000a0000 0x000a0000 0x000a0000
+ 0x000a0000 0x00000010 0x00000010 0x00000010
+ 0x00000010 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000008 0x00000008 0x00000008
+ 0x00000008 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00120220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00000000
+ 0x0000000a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010042>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000013>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000c
+ 0x0000001a 0x00000008 0x00000003 0x00000005
+ 0x00000004 0x00000001 0x00000006 0x00000003
+ 0x00000003 0x00000002 0x00000002 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000c
+ 0x0000000a 0x00000303 0x00000000 0x000000c0
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000007 0x0000001d 0x0000001d
+ 0x00000004 0x0000000b 0x00000005 0x00000004
+ 0x00000002 0x00000351 0x00000004 0x00000006
+ 0x00000000 0x00000000 0x00004282 0x00440084
+ 0x00008000 0x00074000 0x00074000 0x00074000
+ 0x00074000 0x00000010 0x00000010 0x00000010
+ 0x00000010 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000018 0x00000018 0x00000018
+ 0x00000018 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00078000 0x00078000 0x00078000
+ 0x00078000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00000000
+ 0x00000013 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-400000000 {
+ clock-frequency = <400000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010082>;
+ nvidia,emc-mode-2 = <0x00020004>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000024>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000017
+ 0x00000033 0x00000010 0x00000007 0x00000007
+ 0x00000007 0x00000002 0x0000000a 0x00000007
+ 0x00000007 0x00000003 0x00000002 0x00000000
+ 0x00000003 0x00000007 0x00000004 0x0000000d
+ 0x0000000e 0x000005e9 0x00000000 0x0000017a
+ 0x00000002 0x00000002 0x00000007 0x00000000
+ 0x00000001 0x0000000c 0x00000038 0x00000038
+ 0x00000006 0x00000014 0x00000009 0x00000004
+ 0x00000002 0x00000680 0x00000000 0x00000006
+ 0x00000000 0x00000000 0x00006282 0x001d0084
+ 0x00008000 0x0002c000 0x0002c000 0x0002c000
+ 0x0002c000 0x00000010 0x00000010 0x00000010
+ 0x00000010 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000008 0x00000008 0x00000008
+ 0x00000008 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00048000 0x00048000 0x00048000
+ 0x00048000 0x000c0220 0x0800003d 0x00000000
+ 0x77ffc004 0x01f1f408 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00000000
+ 0x00000024 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >;
+ };
+ };
+
+ emc-timings-1 {
+ /* TF201 Unknown 1GB LPDDR2 500MHZ */
+ nvidia,ram-code = <1>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000003 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x00000060 0x00000000 0x00000018
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000004 0x00000004
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x0000006b 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x00780084
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000000a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000003
+ 0x00000006 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x000000c0 0x00000000 0x00000030
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000008 0x00000008
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000000d5 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x00780084
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000013 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x0000000a>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000006
+ 0x0000000d 0x00000004 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x00000181 0x00000000 0x00000060
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x0000000f 0x0000000f
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000001a9 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x00780084
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000025 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010042>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000013>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000c
+ 0x0000001a 0x00000008 0x00000003 0x00000005
+ 0x00000004 0x00000001 0x00000006 0x00000003
+ 0x00000003 0x00000002 0x00000002 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000c
+ 0x0000000a 0x00000303 0x00000000 0x000000c0
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000007 0x0000001d 0x0000001d
+ 0x00000004 0x0000000b 0x00000005 0x00000004
+ 0x00000002 0x00000351 0x00000004 0x00000006
+ 0x00000000 0x00000000 0x00004282 0x00440084
+ 0x00008000 0x00060000 0x00060000 0x00060000
+ 0x00060000 0x00072000 0x00072000 0x00072000
+ 0x00072000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000d0000 0x000d0000 0x000d0000
+ 0x000d0000 0x000e0220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000004a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-500000000 {
+ clock-frequency = <500000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x000100c2>;
+ nvidia,emc-mode-2 = <0x00020005>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x0000002d>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000001d
+ 0x00000040 0x00000014 0x00000008 0x00000007
+ 0x00000009 0x00000003 0x0000000d 0x00000008
+ 0x00000008 0x00000004 0x00000002 0x00000000
+ 0x00000004 0x00000008 0x00000005 0x0000000d
+ 0x0000000f 0x00000763 0x00000000 0x000001d8
+ 0x00000003 0x00000003 0x00000008 0x00000000
+ 0x00000001 0x0000000e 0x00000046 0x00000046
+ 0x00000008 0x00000019 0x0000000b 0x00000004
+ 0x00000002 0x00000820 0x00000000 0x00000006
+ 0x00000000 0x00000000 0x00006282 0xf0140091
+ 0x00008000 0x00000008 0x00000008 0x00000008
+ 0x00000008 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x0000000c 0x0000000c 0x0000000c
+ 0x0000000c 0x00080220 0x0800003d 0x00000000
+ 0x77ffc004 0x01f1f408 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x000000b4 0x000d000d 0xa0f10404 0x00000000
+ 0x00000000 0x80000fde 0xe0000000 0xff00ff88 >;
+ };
+ };
+ };
+};
+
+&emc_icc_dvfs_opp_table {
+ /delete-node/ opp-533000000-1200;
+ /delete-node/ opp-625000000-1200;
+ /delete-node/ opp-625000000-1250;
+ /delete-node/ opp-667000000-1200;
+ /delete-node/ opp-750000000-1300;
+ /delete-node/ opp-800000000-1300;
+ /delete-node/ opp-900000000-1350;
+};
+
+&emc_bw_dfs_opp_table {
+ /delete-node/ opp-533000000;
+ /delete-node/ opp-625000000;
+ /delete-node/ opp-667000000;
+ /delete-node/ opp-750000000;
+ /delete-node/ opp-800000000;
+ /delete-node/ opp-900000000;
+};
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 09/28] ARM: tegra: Add device-tree for ASUS Transformer Pad TF300T
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (7 preceding siblings ...)
2021-12-11 21:13 ` [PATCH v6 08/28] ARM: tegra: Add device-tree for ASUS Transformer Prime TF201 Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 10/28] ARM: tegra: Add device-tree for ASUS Transformer Pad TF300TG Dmitry Osipenko
` (18 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Add device-tree for ASUS Transformer Pad TF300T, which is a NVIDIA
Tegra30-based 2-in-1 detachable, originally running Android.
Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Pad_(asus-tf300t)
Tested-by: Ihor Didenko <tailormoon@rambler.ru>
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com>
Co-developed-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Ion Agorria <ion@agorria.com>
Co-developed-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Co-developed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/tegra30-asus-tf300t.dts | 1030 +++++++++++++++++++++
2 files changed, 1031 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra30-asus-tf300t.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a72aab08e4db..85477066bb2d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1322,6 +1322,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-asus-nexus7-grouper-E1565.dtb \
tegra30-asus-nexus7-tilapia-E1565.dtb \
tegra30-asus-tf201.dtb \
+ tegra30-asus-tf300t.dtb \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
diff --git a/arch/arm/boot/dts/tegra30-asus-tf300t.dts b/arch/arm/boot/dts/tegra30-asus-tf300t.dts
new file mode 100644
index 000000000000..2981b0e15d63
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-tf300t.dts
@@ -0,0 +1,1030 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-transformer-common.dtsi"
+#include "tegra30-asus-lvds-display.dtsi"
+
+/ {
+ model = "Asus Transformer Pad TF300T";
+ compatible = "asus,tf300t", "nvidia,tegra30";
+
+ gpio@6000d000 {
+ tf300t-init-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+
+ pinmux@70000868 {
+ state_default: pinmux {
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6",
+ "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_cs4_n_pk2 {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
+ uartc: serial@70006200 {
+ /* Azurewave AW-NH615 BCM4329B1 */
+ bluetooth {
+ compatible = "brcm,bcm4329-bt";
+ };
+ };
+
+ i2c@7000c400 {
+ /* Elantech EKTH1036 touchscreen */
+ touchscreen@10 {
+ compatible = "elan,ektf3624";
+ reg = <0x10>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>;
+
+ vcc33-supply = <&vdd_3v3_sys>;
+ vccio-supply = <&vdd_3v3_sys>;
+
+ touchscreen-size-x = <2240>;
+ touchscreen-size-y = <1408>;
+ touchscreen-inverted-y;
+ };
+ };
+
+ i2c@7000c500 {
+ clock-frequency = <400000>;
+
+ magnetometer@e {
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "-1";
+ };
+
+ gyroscope@68 {
+ mount-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "-1";
+
+ /* External I2C interface */
+ i2c-gate {
+ accelerometer@f {
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
+ };
+ };
+ };
+ };
+
+ i2c@7000d000 {
+ /* Wolfson Microelectronics WM8903 audio codec */
+ wm8903: audio-codec@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+
+ gpio-cfg = <
+ 0xffffffff /* don't touch */
+ 0xffffffff /* don't touch */
+ 0x00000000 /* Speaker-enable GPIO, output, low */
+ 0xffffffff /* don't touch */
+ 0xffffffff /* don't touch */
+ >;
+
+ AVDD-supply = <&vdd_1v8_vio>;
+ CPVDD-supply = <&vdd_1v8_vio>;
+ DBVDD-supply = <&vdd_1v8_vio>;
+ DCVDD-supply = <&vdd_1v8_vio>;
+ };
+ };
+
+ display-panel {
+ compatible = "innolux,g101ice-l01";
+ };
+
+ sound {
+ compatible = "asus,tegra-audio-wm8903-tf300t",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "Asus Transformer Pad TF300T WM8903";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "IN1L", "Mic Jack",
+ "IN2L", "Mic Jack",
+ "DMICDAT", "Int Mic";
+
+ nvidia,audio-codec = <&wm8903>;
+ nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+ nvidia,headset;
+ };
+
+ memory-controller@7000f000 {
+ emc-timings-0 {
+ /* Elpida 1GB 667MHZ */
+ nvidia,ram-code = <0>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00030003 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x74830303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010003 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x73430303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000030
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0503 0x72830504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000006 0xc0000025
+ 0x00000001 0x00000001 0x00000005 0x00000002
+ 0x00000003 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0505 0x72440a06 0x001f0000 >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emem-configuration = < 0x0000000a 0xc000003d
+ 0x00000001 0x00000002 0x00000008 0x00000004
+ 0x00000004 0x00000001 0x00000002 0x00000007
+ 0x00000002 0x00000002 0x00000003 0x00000006
+ 0x06030202 0x000b0608 0x70850f09 0x001f0000 >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emem-configuration = < 0x00000014 0xc0000079
+ 0x00000003 0x00000004 0x00000010 0x0000000b
+ 0x0000000a 0x00000001 0x00000003 0x0000000b
+ 0x00000002 0x00000002 0x00000004 0x00000008
+ 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >;
+ };
+ };
+
+ emc-timings-1 {
+ /* Hynix 1GB 667MHZ */
+ nvidia,ram-code = <1>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00030003 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x74830303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010003 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x73430303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000030
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0503 0x72830504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000006 0xc0000025
+ 0x00000001 0x00000001 0x00000005 0x00000002
+ 0x00000003 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0605 0x72440a06 0x001f0000 >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emem-configuration = < 0x0000000a 0xc000003d
+ 0x00000001 0x00000002 0x00000008 0x00000005
+ 0x00000004 0x00000001 0x00000002 0x00000007
+ 0x00000002 0x00000002 0x00000003 0x00000006
+ 0x06030202 0x000b0608 0x70850f09 0x001f0000 >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emem-configuration = < 0x00000014 0xc0000079
+ 0x00000003 0x00000004 0x00000011 0x0000000b
+ 0x0000000a 0x00000001 0x00000003 0x0000000b
+ 0x00000002 0x00000002 0x00000004 0x00000008
+ 0x08040202 0x00140b11 0x70ea1f12 0x001f0000 >;
+ };
+ };
+
+ emc-timings-2 {
+ /* Micron 1GB 667MHZ */
+ nvidia,ram-code = <2>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00020001 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x74830303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010001 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x73430303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000001 0xc0000030
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0503 0x72830504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000025
+ 0x00000001 0x00000001 0x00000005 0x00000002
+ 0x00000003 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0505 0x72440a06 0x001f0000 >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emem-configuration = < 0x00000005 0xc000003d
+ 0x00000001 0x00000002 0x00000008 0x00000004
+ 0x00000004 0x00000001 0x00000002 0x00000007
+ 0x00000002 0x00000002 0x00000003 0x00000006
+ 0x06030202 0x000b0608 0x70850f09 0x001f0000 >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emem-configuration = < 0x0000000a 0xc0000079
+ 0x00000003 0x00000004 0x00000010 0x0000000a
+ 0x0000000a 0x00000001 0x00000003 0x0000000b
+ 0x00000002 0x00000002 0x00000004 0x00000008
+ 0x08040202 0x00140b10 0x70ea1f11 0x001f0000 >;
+ };
+ };
+ };
+
+ memory-controller@7000f400 {
+ emc-timings-0 {
+ /* Elpida 1GB 667MHZ */
+ nvidia,ram-code = <0>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000004 0x00000000 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x00000009
+ 0x0000000b 0x000000c0 0x00000000 0x00000030
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000005 0x00000005
+ 0x00000004 0x00000001 0x00000000 0x00000004
+ 0x00000005 0x000000c7 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000002
+ 0x00000008 0x00000001 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x00000009
+ 0x0000000b 0x00000181 0x00000000 0x00000060
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000009 0x00000009
+ 0x00000004 0x00000002 0x00000000 0x00000004
+ 0x00000005 0x0000018e 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000004
+ 0x00000010 0x00000003 0x00000001 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000001
+ 0x00000001 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x00000009
+ 0x0000000b 0x00000303 0x00000000 0x000000c0
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000012 0x00000012
+ 0x00000004 0x00000004 0x00000000 0x00000004
+ 0x00000005 0x0000031c 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000a
+ 0x00000020 0x00000007 0x00000002 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000002
+ 0x00000002 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x00000009
+ 0x0000000b 0x00000607 0x00000000 0x00000181
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000023 0x00000023
+ 0x00000004 0x00000007 0x00000000 0x00000004
+ 0x00000005 0x00000638 0x00000006 0x00000006
+ 0x00000000 0x00000000 0x00004288 0x004400a4
+ 0x00008000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00020000
+ 0x00000100 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200000>;
+ nvidia,emc-mode-reset = <0x80000321>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+
+ nvidia,emc-configuration = < 0x0000000f
+ 0x00000034 0x0000000a 0x00000003 0x00000003
+ 0x00000008 0x00000002 0x00000009 0x00000003
+ 0x00000003 0x00000002 0x00000001 0x00000000
+ 0x00000004 0x00000006 0x00000004 0x0000000a
+ 0x0000000c 0x000009e9 0x00000000 0x0000027a
+ 0x00000001 0x00000008 0x00000001 0x00000000
+ 0x00000007 0x0000000e 0x00000039 0x00000200
+ 0x00000004 0x0000000a 0x00000000 0x00000004
+ 0x00000005 0x00000a2a 0x00000000 0x00000004
+ 0x00000000 0x00000000 0x00007088 0x002600a4
+ 0x00008000 0x0003c000 0x0003c000 0x0003c000
+ 0x0003c000 0x00014000 0x00014000 0x00014000
+ 0x00014000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00048000 0x00048000 0x00048000
+ 0x00048000 0x000002a0 0x0800013d 0x00000000
+ 0x77fff884 0x01f1f508 0x05057404 0x54000007
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x018b000c 0xa0f10000 0x00000000
+ 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200018>;
+ nvidia,emc-mode-reset = <0x80000b71>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000001f
+ 0x00000069 0x00000017 0x00000007 0x00000005
+ 0x0000000c 0x00000003 0x00000011 0x00000007
+ 0x00000007 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000a 0x00000009 0x0000000a
+ 0x00000011 0x00001412 0x00000000 0x00000504
+ 0x00000002 0x0000000e 0x00000001 0x00000000
+ 0x0000000c 0x00000016 0x00000072 0x00000200
+ 0x00000005 0x00000015 0x00000000 0x00000006
+ 0x00000007 0x00001453 0x0000000b 0x00000006
+ 0x00000000 0x00000000 0x00005088 0xf00b0191
+ 0x00008000 0x00000008 0x00000008 0x00000008
+ 0x00000008 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x000002a0 0x0800013d 0x22220000
+ 0x77fff884 0x01f1f501 0x07077404 0x54000000
+ 0x080001e8 0x0f000021 0x00000802 0x00020000
+ 0x00000100 0x0156000c 0xa0f10000 0x00000000
+ 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >;
+ };
+ };
+
+ emc-timings-1 {
+ /* Hynix 1GB 667MHZ */
+ nvidia,ram-code = <1>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000004 0x00000000 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x00000009
+ 0x0000000b 0x000000c0 0x00000000 0x00000030
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000005 0x00000005
+ 0x00000004 0x00000001 0x00000000 0x00000004
+ 0x00000005 0x000000c7 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000002
+ 0x00000008 0x00000001 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x00000009
+ 0x0000000b 0x00000181 0x00000000 0x00000060
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000009 0x00000009
+ 0x00000004 0x00000002 0x00000000 0x00000004
+ 0x00000005 0x0000018e 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000005
+ 0x00000010 0x00000003 0x00000001 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000001
+ 0x00000001 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x00000009
+ 0x0000000b 0x00000303 0x00000000 0x000000c0
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000012 0x00000012
+ 0x00000004 0x00000004 0x00000000 0x00000004
+ 0x00000005 0x0000031c 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000a
+ 0x00000020 0x00000007 0x00000003 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000002
+ 0x00000002 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x00000009
+ 0x0000000b 0x00000607 0x00000000 0x00000181
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000023 0x00000023
+ 0x00000004 0x00000007 0x00000000 0x00000004
+ 0x00000005 0x00000638 0x00000006 0x00000006
+ 0x00000000 0x00000000 0x00004288 0x004400a4
+ 0x00008000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00020000
+ 0x00000100 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200000>;
+ nvidia,emc-mode-reset = <0x80000321>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+
+ nvidia,emc-configuration = < 0x0000000f
+ 0x00000034 0x0000000b 0x00000003 0x00000003
+ 0x00000008 0x00000002 0x00000009 0x00000003
+ 0x00000003 0x00000002 0x00000001 0x00000000
+ 0x00000004 0x00000006 0x00000004 0x0000000a
+ 0x0000000c 0x000009e9 0x00000000 0x0000027a
+ 0x00000001 0x00000008 0x00000001 0x00000000
+ 0x00000007 0x0000000e 0x00000039 0x00000200
+ 0x00000004 0x0000000a 0x00000000 0x00000004
+ 0x00000005 0x00000a2a 0x00000000 0x00000004
+ 0x00000000 0x00000000 0x00007088 0x002600a4
+ 0x00008000 0x0003c000 0x0003c000 0x0003c000
+ 0x0003c000 0x00014000 0x00014000 0x00014000
+ 0x00014000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00048000 0x00048000 0x00048000
+ 0x00048000 0x000002a0 0x0800013d 0x00000000
+ 0x77fff884 0x01f1f508 0x05057404 0x54000007
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x018b000c 0xa0f10000 0x00000000
+ 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200018>;
+ nvidia,emc-mode-reset = <0x80000b71>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000020
+ 0x0000006a 0x00000018 0x00000008 0x00000005
+ 0x0000000c 0x00000003 0x00000011 0x00000007
+ 0x00000007 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000a 0x00000009 0x0000000a
+ 0x00000011 0x00001412 0x00000000 0x00000504
+ 0x00000002 0x0000000e 0x00000001 0x00000000
+ 0x0000000c 0x00000016 0x00000072 0x00000200
+ 0x00000005 0x00000015 0x00000000 0x00000006
+ 0x00000007 0x00001453 0x0000000b 0x00000006
+ 0x00000000 0x00000000 0x00005088 0xf00b0191
+ 0x00008000 0x00000008 0x00000008 0x00000008
+ 0x00000008 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x0000000c 0x0000000c 0x0000000c
+ 0x0000000c 0x000002a0 0x0800013d 0x22220000
+ 0x77fff884 0x01f1f501 0x07077404 0x54000000
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x0155000c 0xa0f10000 0x00000000
+ 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >;
+ };
+ };
+
+ emc-timings-2 {
+ /* Micron 1GB 667MHZ */
+ nvidia,ram-code = <2>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200048>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000004 0x00000000 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x00000009
+ 0x0000000b 0x000000c0 0x00000000 0x00000030
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000005 0x00000005
+ 0x00000004 0x00000001 0x00000000 0x00000004
+ 0x00000005 0x000000c7 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000002
+ 0x00000008 0x00000001 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x00000009
+ 0x0000000b 0x00000181 0x00000000 0x00000060
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000009 0x00000009
+ 0x00000004 0x00000002 0x00000000 0x00000004
+ 0x00000005 0x0000018e 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200048>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000004
+ 0x00000010 0x00000003 0x00000001 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000001
+ 0x00000001 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x00000303 0x00000000 0x000000c0
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000012 0x00000012
+ 0x00000004 0x00000004 0x00000000 0x00000004
+ 0x00000005 0x0000031c 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xd8000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200048>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000009
+ 0x00000020 0x00000007 0x00000002 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000002
+ 0x00000002 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x00000607 0x00000000 0x00000181
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000023 0x00000023
+ 0x00000004 0x00000007 0x00000000 0x00000004
+ 0x00000005 0x00000638 0x00000006 0x00000006
+ 0x00000000 0x00000000 0x00004288 0x004400a4
+ 0x00008000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00020000
+ 0x00000100 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000d22 0xd8000000 0xff00ff00 >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200040>;
+ nvidia,emc-mode-reset = <0x80000321>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+
+ nvidia,emc-configuration = < 0x0000000f
+ 0x00000034 0x0000000a 0x00000003 0x00000003
+ 0x00000008 0x00000002 0x00000009 0x00000003
+ 0x00000003 0x00000002 0x00000001 0x00000000
+ 0x00000004 0x00000006 0x00000004 0x0000000a
+ 0x0000000c 0x000009e9 0x00000000 0x0000027a
+ 0x00000001 0x00000008 0x00000001 0x00000000
+ 0x00000007 0x0000000e 0x00000039 0x00000200
+ 0x00000004 0x0000000a 0x00000000 0x00000004
+ 0x00000005 0x00000a2a 0x00000000 0x00000004
+ 0x00000000 0x00000000 0x00007088 0x002600a4
+ 0x00008000 0x0003c000 0x0003c000 0x0003c000
+ 0x0003c000 0x00014000 0x00014000 0x00014000
+ 0x00014000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00048000 0x00048000 0x00048000
+ 0x00048000 0x000002a0 0x0800013d 0x00000000
+ 0x77fff884 0x01f1f508 0x05057404 0x54000007
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x018b000c 0xa0f10000 0x00000000
+ 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200058>;
+ nvidia,emc-mode-reset = <0x80000b71>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000001f
+ 0x00000069 0x00000016 0x00000007 0x00000005
+ 0x0000000c 0x00000003 0x00000011 0x00000008
+ 0x00000008 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000a 0x00000009 0x0000000b
+ 0x00000011 0x00001412 0x00000000 0x00000504
+ 0x00000002 0x0000000e 0x00000001 0x00000000
+ 0x0000000c 0x00000016 0x00000072 0x00000200
+ 0x00000005 0x00000015 0x00000000 0x00000006
+ 0x00000007 0x00001453 0x0000000b 0x00000006
+ 0x00000000 0x00000000 0x00005088 0xf00b0191
+ 0x00008000 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x0000000c 0x0000000c 0x0000000c
+ 0x0000000c 0x000002a0 0x0800013d 0x22220000
+ 0x77fff884 0x01f1f501 0x07077404 0x54000000
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x0156000c 0xa0f10000 0x00000000
+ 0x00000000 0x800028a5 0xf8000000 0xff00ff49 >;
+ };
+ };
+ };
+};
+
+&emc_icc_dvfs_opp_table {
+ /delete-node/ opp-750000000-1300;
+ /delete-node/ opp-800000000-1300;
+ /delete-node/ opp-900000000-1350;
+};
+
+&emc_bw_dfs_opp_table {
+ /delete-node/ opp-750000000;
+ /delete-node/ opp-800000000;
+ /delete-node/ opp-900000000;
+};
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 10/28] ARM: tegra: Add device-tree for ASUS Transformer Pad TF300TG
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (8 preceding siblings ...)
2021-12-11 21:13 ` [PATCH v6 09/28] ARM: tegra: Add device-tree for ASUS Transformer Pad TF300T Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 11/28] ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T Dmitry Osipenko
` (17 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Svyatoslav Ryhel <clamor95@gmail.com>
Add device-tree for ASUS Transformer Pad TF300TG, which is a NVIDIA
Tegra30-based 2-in-1 detachable, originally running Android. It's a
variant of the TF300T that has a 3G modem.
Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Pad_(asus-tf300t)
Co-developed-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Ion Agorria <ion@agorria.com>
Co-developed-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/tegra30-asus-tf300tg.dts | 1072 ++++++++++++++++++++
2 files changed, 1073 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra30-asus-tf300tg.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 85477066bb2d..fcbcaed0c2da 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1323,6 +1323,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-asus-nexus7-tilapia-E1565.dtb \
tegra30-asus-tf201.dtb \
tegra30-asus-tf300t.dtb \
+ tegra30-asus-tf300tg.dtb \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
diff --git a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts
new file mode 100644
index 000000000000..e1509b48a4fa
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts
@@ -0,0 +1,1072 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-transformer-common.dtsi"
+#include "tegra30-asus-lvds-display.dtsi"
+
+/ {
+ model = "Asus Transformer Pad 3G TF300TG";
+ compatible = "asus,tf300tg", "nvidia,tegra30";
+
+ gpio@6000d000 {
+ tf300tg-init-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(X, 5) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(U, 5) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(Y, 2) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(Y, 3) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(EE, 1) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(U, 3) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+
+ pinmux@70000868 {
+ state_default: pinmux {
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_cs4_n_pk2 {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6",
+ "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi2_cs2_n_pw3 {
+ nvidia,pins = "spi2_cs2_n_pw3";
+ nvidia,function = "spi2";
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ dap3_din_pp1 {
+ nvidia,pins = "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi1_sck_px5 {
+ nvidia,pins = "spi1_sck_px5";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2_mosi_px0 {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi2";
+ };
+ spi1_miso_px7 {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3_req_pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_nxt_py2 {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_stp_py3 {
+ nvidia,pins = "ulpi_stp_py3";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap1_din_pn1 {
+ nvidia,pins = "dap1_din_pn1";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+ };
+
+ uartc: serial@70006200 {
+ /* Azurewave AW-NH615 BCM4329B1 */
+ bluetooth {
+ compatible = "brcm,bcm4329-bt";
+ };
+ };
+
+ i2c2: i2c@7000c400 {
+ /* Elantech EKTH1036 touchscreen */
+ touchscreen@10 {
+ compatible = "elan,ektf3624";
+ reg = <0x10>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>;
+
+ vcc33-supply = <&vdd_3v3_sys>;
+ vccio-supply = <&vdd_3v3_sys>;
+
+ touchscreen-size-x = <2240>;
+ touchscreen-size-y = <1408>;
+ touchscreen-inverted-y;
+ };
+ };
+
+ i2c3: i2c@7000c500 {
+ clock-frequency = <400000>;
+
+ magnetometer@e {
+ mount-matrix = "1", "0", "0",
+ "0", "-1", "0",
+ "0", "0", "-1";
+ };
+
+ gyroscope@68 {
+ mount-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "-1";
+
+ /* External I2C interface */
+ i2c-gate {
+ accelerometer@f {
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
+ };
+ };
+ };
+ };
+
+ i2c5: i2c@7000d000 {
+ /* Realtek ALC5631 audio codec */
+ rt5631: audio-codec@1a {
+ compatible = "realtek,rt5631";
+ reg = <0x1a>;
+ };
+ };
+
+ display-panel {
+ compatible = "innolux,g101ice-l01";
+ };
+
+ memory-controller@7000f000 {
+ emc-timings-0 {
+ /* Elpida 1GB 667MHZ */
+ nvidia,ram-code = <0>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00020001 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x74830303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010001 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x73430303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000001 0xc0000030
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0503 0x72830504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000025
+ 0x00000001 0x00000001 0x00000005 0x00000002
+ 0x00000003 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0505 0x72440a06 0x001f0000 >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emem-configuration = < 0x00000005 0xc000003d
+ 0x00000001 0x00000002 0x00000008 0x00000004
+ 0x00000004 0x00000001 0x00000002 0x00000007
+ 0x00000002 0x00000002 0x00000003 0x00000006
+ 0x06030202 0x000b0608 0x70850f09 0x001f0000 >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emem-configuration = < 0x0000000a 0xc0000079
+ 0x00000003 0x00000004 0x00000010 0x0000000b
+ 0x0000000a 0x00000001 0x00000003 0x0000000b
+ 0x00000002 0x00000002 0x00000004 0x00000008
+ 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >;
+ };
+ };
+
+ emc-timings-1 {
+ /* Hynix 1GB 667MHZ */
+ nvidia,ram-code = <1>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00020001 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x74830303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010001 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x73430303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000001 0xc0000030
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0503 0x72830504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000025
+ 0x00000001 0x00000001 0x00000005 0x00000002
+ 0x00000003 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0505 0x72440a06 0x001f0000 >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emem-configuration = < 0x00000005 0xc000003d
+ 0x00000001 0x00000002 0x00000008 0x00000004
+ 0x00000004 0x00000001 0x00000002 0x00000007
+ 0x00000002 0x00000002 0x00000003 0x00000006
+ 0x06030202 0x000b0608 0x70850f09 0x001f0000 >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emem-configuration = < 0x0000000a 0xc0000079
+ 0x00000003 0x00000004 0x00000010 0x0000000b
+ 0x0000000a 0x00000001 0x00000003 0x0000000b
+ 0x00000002 0x00000002 0x00000004 0x00000008
+ 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >;
+ };
+ };
+
+ emc-timings-2 {
+ /* Micron 1GB 667MHZ */
+ nvidia,ram-code = <2>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00020001 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x74830303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010001 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x73430303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000001 0xc0000030
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0503 0x72830504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000025
+ 0x00000001 0x00000001 0x00000005 0x00000002
+ 0x00000003 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0505 0x72440a06 0x001f0000 >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emem-configuration = < 0x00000005 0x8000003d
+ 0x00000001 0x00000002 0x00000008 0x00000004
+ 0x00000004 0x00000001 0x00000002 0x00000007
+ 0x00000002 0x00000002 0x00000003 0x00000006
+ 0x06030202 0x000b0608 0x70850f09 0x001f0000 >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emem-configuration = < 0x0000000a 0x80000079
+ 0x00000003 0x00000004 0x00000010 0x0000000a
+ 0x0000000a 0x00000001 0x00000003 0x0000000b
+ 0x00000002 0x00000002 0x00000004 0x00000008
+ 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >;
+ };
+ };
+ };
+
+ memory-controller@7000f400 {
+ emc-timings-0 {
+ /* Elpida 1GB 667MHZ */
+ nvidia,ram-code = <0>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200048>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000004 0x00000000 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x000000c0 0x00000000 0x00000030
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000005 0x00000005
+ 0x00000004 0x00000001 0x00000000 0x00000004
+ 0x00000005 0x000000c7 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200048>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000002
+ 0x00000008 0x00000001 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x00000181 0x00000000 0x00000060
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000009 0x00000009
+ 0x00000004 0x00000002 0x00000000 0x00000004
+ 0x00000005 0x0000018e 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200048>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000005
+ 0x00000010 0x00000003 0x00000001 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000001
+ 0x00000001 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x00000303 0x00000000 0x000000c0
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000012 0x00000012
+ 0x00000004 0x00000004 0x00000000 0x00000004
+ 0x00000005 0x0000031c 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200048>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000a
+ 0x00000020 0x00000007 0x00000002 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000002
+ 0x00000002 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000006 0x00000004 0x0000000a
+ 0x0000000b 0x00000607 0x00000000 0x00000181
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000023 0x00000023
+ 0x00000004 0x00000007 0x00000000 0x00000004
+ 0x00000005 0x00000638 0x00000007 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x004400a4
+ 0x00008000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00020000
+ 0x00000100 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200040>;
+ nvidia,emc-mode-reset = <0x80000321>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+
+ nvidia,emc-configuration = < 0x0000000f
+ 0x00000034 0x0000000a 0x00000003 0x00000003
+ 0x00000008 0x00000002 0x00000009 0x00000003
+ 0x00000003 0x00000002 0x00000001 0x00000000
+ 0x00000004 0x00000006 0x00000004 0x0000000a
+ 0x0000000c 0x000009e9 0x00000000 0x0000027a
+ 0x00000001 0x00000008 0x00000001 0x00000000
+ 0x00000007 0x0000000e 0x00000039 0x00000200
+ 0x00000004 0x0000000a 0x00000000 0x00000004
+ 0x00000005 0x00000a2a 0x00000000 0x00000004
+ 0x00000000 0x00000000 0x00007088 0x002600a4
+ 0x00008000 0x0003c000 0x0003c000 0x0003c000
+ 0x0003c000 0x00014000 0x00014000 0x00014000
+ 0x00014000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00050000 0x00050000 0x00050000
+ 0x00050000 0x000002a0 0x0800013d 0x00000000
+ 0x77fff884 0x01f1f508 0x05057404 0x54000007
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x018b000c 0xa0f10000 0x00000000
+ 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200058>;
+ nvidia,emc-mode-reset = <0x80000b71>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000001f
+ 0x00000069 0x00000017 0x00000007 0x00000005
+ 0x0000000c 0x00000003 0x00000011 0x00000007
+ 0x00000007 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000b 0x00000009 0x0000000b
+ 0x00000011 0x00001412 0x00000000 0x00000504
+ 0x00000002 0x0000000e 0x00000001 0x00000000
+ 0x0000000c 0x00000016 0x00000072 0x00000200
+ 0x00000005 0x00000015 0x00000000 0x00000006
+ 0x00000007 0x00001453 0x0000000c 0x00000004
+ 0x00000000 0x00000000 0x00005088 0xf00b0191
+ 0x00008000 0x0000000c 0x0000000c 0x0000000c
+ 0x0000000c 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x00018000 0x00018000 0x00018000
+ 0x00018000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x0000000c 0x0000000c 0x0000000c
+ 0x0000000c 0x000002a0 0x0a00013d 0x22220000
+ 0x77fff884 0x01f1f501 0x07077404 0x54000000
+ 0x080001e8 0x0a000021 0x00000802 0x00020000
+ 0x00000100 0x0156000c 0xa0f10000 0x00000000
+ 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >;
+ };
+ };
+
+ emc-timings-1 {
+ /* Hynix 1GB 667MHZ */
+ nvidia,ram-code = <1>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200048>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000004 0x00000000 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x000000c0 0x00000000 0x00000030
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000005 0x00000005
+ 0x00000004 0x00000001 0x00000000 0x00000004
+ 0x00000005 0x000000c7 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200048>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000002
+ 0x00000008 0x00000001 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x00000181 0x00000000 0x00000060
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000009 0x00000009
+ 0x00000004 0x00000002 0x00000000 0x00000004
+ 0x00000005 0x0000018e 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200048>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000005
+ 0x00000010 0x00000003 0x00000001 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000001
+ 0x00000001 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x00000303 0x00000000 0x000000c0
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000012 0x00000012
+ 0x00000004 0x00000004 0x00000000 0x00000004
+ 0x00000005 0x0000031c 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200048>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000a
+ 0x00000020 0x00000007 0x00000002 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000002
+ 0x00000002 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000006 0x00000004 0x0000000a
+ 0x0000000b 0x00000607 0x00000000 0x00000181
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000023 0x00000023
+ 0x00000004 0x00000007 0x00000000 0x00000004
+ 0x00000005 0x00000638 0x00000007 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x004400a4
+ 0x00008000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00020000
+ 0x00000100 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200040>;
+ nvidia,emc-mode-reset = <0x80000321>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+
+ nvidia,emc-configuration = < 0x0000000f
+ 0x00000034 0x0000000a 0x00000003 0x00000003
+ 0x00000008 0x00000002 0x00000009 0x00000003
+ 0x00000003 0x00000002 0x00000001 0x00000000
+ 0x00000004 0x00000006 0x00000004 0x0000000a
+ 0x0000000c 0x000009e9 0x00000000 0x0000027a
+ 0x00000001 0x00000008 0x00000001 0x00000000
+ 0x00000007 0x0000000e 0x00000039 0x00000200
+ 0x00000004 0x0000000a 0x00000000 0x00000004
+ 0x00000005 0x00000a2a 0x00000000 0x00000004
+ 0x00000000 0x00000000 0x00007088 0x002600a4
+ 0x00008000 0x0003c000 0x0003c000 0x0003c000
+ 0x0003c000 0x00014000 0x00014000 0x00014000
+ 0x00014000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00048000 0x00048000 0x00048000
+ 0x00048000 0x000002a0 0x0800013d 0x00000000
+ 0x77fff884 0x01f1f508 0x05057404 0x54000007
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x018b000c 0xa0f10000 0x00000000
+ 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200058>;
+ nvidia,emc-mode-reset = <0x80000b71>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000020
+ 0x00000069 0x00000017 0x00000007 0x00000005
+ 0x0000000c 0x00000003 0x00000011 0x00000007
+ 0x00000007 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000b 0x00000009 0x0000000b
+ 0x00000011 0x00001412 0x00000000 0x00000504
+ 0x00000002 0x0000000e 0x00000001 0x00000000
+ 0x0000000c 0x00000016 0x00000072 0x00000200
+ 0x00000005 0x00000015 0x00000000 0x00000006
+ 0x00000007 0x00001453 0x0000000c 0x00000004
+ 0x00000000 0x00000000 0x00005088 0xf00b0191
+ 0x00008000 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x00018000 0x00018000 0x00018000
+ 0x00018000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x000002a0 0x0800013d 0x22220000
+ 0x77fff884 0x01f1f501 0x07077404 0x54000000
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x0156000c 0xa0f10000 0x00000000
+ 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >;
+ };
+ };
+
+ emc-timings-2 {
+ /* Micron 1GB 667MHZ */
+ nvidia,ram-code = <2>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000004 0x00000000 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x000000c0 0x00000000 0x00000030
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000005 0x00000005
+ 0x00000004 0x00000001 0x00000000 0x00000004
+ 0x00000005 0x000000c7 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000002
+ 0x00000008 0x00000001 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x00000181 0x00000000 0x00000060
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000009 0x00000009
+ 0x00000004 0x00000002 0x00000000 0x00000004
+ 0x00000005 0x0000018e 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000004
+ 0x00000010 0x00000003 0x00000001 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000001
+ 0x00000001 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x00000303 0x00000000 0x000000c0
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000012 0x00000012
+ 0x00000004 0x00000004 0x00000000 0x00000004
+ 0x00000005 0x0000031c 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000009
+ 0x00000020 0x00000007 0x00000002 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000002
+ 0x00000002 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000006 0x00000004 0x0000000a
+ 0x0000000b 0x00000607 0x00000000 0x00000181
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000023 0x00000023
+ 0x00000004 0x00000007 0x00000000 0x00000004
+ 0x00000005 0x00000638 0x00000007 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x004400a4
+ 0x00008000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00020000
+ 0x00000100 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200000>;
+ nvidia,emc-mode-reset = <0x80000321>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+
+ nvidia,emc-configuration = < 0x0000000f
+ 0x00000034 0x0000000a 0x00000003 0x00000003
+ 0x00000008 0x00000002 0x00000009 0x00000003
+ 0x00000003 0x00000002 0x00000001 0x00000000
+ 0x00000004 0x00000006 0x00000004 0x0000000a
+ 0x0000000c 0x000009e9 0x00000000 0x0000027a
+ 0x00000001 0x00000008 0x00000001 0x00000000
+ 0x00000007 0x0000000e 0x00000039 0x00000200
+ 0x00000004 0x0000000a 0x00000000 0x00000004
+ 0x00000005 0x00000a2a 0x00000000 0x00000004
+ 0x00000000 0x00000000 0x00007088 0x002600a4
+ 0x00008000 0x0003c000 0x0003c000 0x0003c000
+ 0x0003c000 0x00014000 0x00014000 0x00014000
+ 0x00014000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00040000 0x00040000 0x00040000
+ 0x00040000 0x000002a0 0x0800013d 0x00000000
+ 0x77fff884 0x01f1f508 0x05057404 0x54000007
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x018b000c 0xa0f10000 0x00000000
+ 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200018>;
+ nvidia,emc-mode-reset = <0x80000b71>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000001f
+ 0x00000069 0x00000016 0x00000007 0x00000005
+ 0x0000000c 0x00000003 0x00000011 0x00000007
+ 0x00000007 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000b 0x00000009 0x0000000b
+ 0x00000011 0x00001412 0x00000000 0x00000504
+ 0x00000002 0x0000000e 0x00000001 0x00000000
+ 0x0000000c 0x00000016 0x00000072 0x00000200
+ 0x00000005 0x00000015 0x00000000 0x00000006
+ 0x00000007 0x00001453 0x0000000c 0x00000004
+ 0x00000000 0x00000000 0x00005088 0xf00b0191
+ 0x00008000 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x000002a0 0x0600013d 0x22220000
+ 0x77fff884 0x01f1f501 0x07077404 0x54000000
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x0156000c 0xa0f10000 0x00000000
+ 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >;
+ };
+ };
+ };
+};
+
+&emc_icc_dvfs_opp_table {
+ /delete-node/ opp-750000000-1300;
+ /delete-node/ opp-800000000-1300;
+ /delete-node/ opp-900000000-1350;
+};
+
+&emc_bw_dfs_opp_table {
+ /delete-node/ opp-750000000;
+ /delete-node/ opp-800000000;
+ /delete-node/ opp-900000000;
+};
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 11/28] ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (9 preceding siblings ...)
2021-12-11 21:13 ` [PATCH v6 10/28] ARM: tegra: Add device-tree for ASUS Transformer Pad TF300TG Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-15 14:01 ` Thierry Reding
2021-12-11 21:13 ` [PATCH v6 12/28] ARM: tegra: Add device-tree for ASUS Transformer Pad TF701T Dmitry Osipenko
` (16 subsequent siblings)
27 siblings, 1 reply; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Svyatoslav Ryhel <clamor95@gmail.com>
Add device-tree for ASUS Transformer Infinity TF700T, which is a NVIDIA
Tegra30-based 2-in-1 detachable, originally running Android.
Link: https://wiki.postmarketos.org/wiki/Asus_Transformer_Pad_Infinity_TF700T_(asus-tf700t)
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Co-developed-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Ion Agorria <ion@agorria.com>
Co-developed-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Co-developed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/tegra30-asus-tf700t.dts | 818 ++++++++++++++++++++++
2 files changed, 819 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra30-asus-tf700t.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index fcbcaed0c2da..87166d66e0b1 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1324,6 +1324,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-asus-tf201.dtb \
tegra30-asus-tf300t.dtb \
tegra30-asus-tf300tg.dtb \
+ tegra30-asus-tf700t.dtb \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/tegra30-asus-tf700t.dts
new file mode 100644
index 000000000000..49ae8ba89436
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-tf700t.dts
@@ -0,0 +1,818 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-transformer-common.dtsi"
+
+/ {
+ model = "Asus Transformer Infinity TF700T";
+ compatible = "asus,tf700t", "nvidia,tegra30";
+
+ host1x@50000000 {
+ lcd: dc@54200000 {
+ clocks = <&tegra_car TEGRA30_CLK_DISP1>,
+ <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+
+ rgb {
+ status = "okay";
+
+ port@0 {
+ dpi_output: endpoint {
+ remote-endpoint = <&bridge_input>;
+ bus-width = <24>;
+ };
+ };
+ };
+ };
+ };
+
+ pinmux@70000868 {
+ state_default: pinmux {
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6",
+ "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi2_mosi_px0 {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_cs4_n_pk2 {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
+ uartc: serial@70006200 {
+ /* Azurewave AW-NH665 BCM4330B1 */
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ };
+ };
+
+ i2c@7000c400 {
+ /* Elantech ELAN-3024-7053 or 5184N FPC-1 REV: 2/3 touchscreen */
+ touchscreen@10 {
+ compatible = "elan,ektf3624";
+ reg = <0x10>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>;
+
+ vcc33-supply = <&vdd_3v3_sys>;
+ vccio-supply = <&vdd_3v3_sys>;
+
+ touchscreen-size-x = <2944>;
+ touchscreen-size-y = <1856>;
+ touchscreen-inverted-y;
+ };
+ };
+
+ i2c@7000c500 {
+ clock-frequency = <100000>;
+
+ magnetometer@e {
+ mount-matrix = "1", "0", "0",
+ "0", "-1", "0",
+ "0", "0", "-1";
+ };
+
+ gyroscope@68 {
+ mount-matrix = "0", "1", "0",
+ "1", "0", "0",
+ "0", "0", "-1";
+
+ /* External I2C interface */
+ i2c-gate {
+ accelerometer@f {
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
+ };
+ };
+ };
+ };
+
+ i2c@7000d000 {
+ /* Realtek ALC5631 audio codec */
+ rt5631: audio-codec@1a {
+ compatible = "realtek,rt5631";
+ reg = <0x1a>;
+ };
+ };
+
+ haptic-feedback {
+ compatible = "gpio-vibrator";
+ enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
+ vcc-supply = <&vdd_3v3_sys>;
+ };
+
+ i2c-switch-tc358768 {
+ compatible = "i2c-mux-gpio";
+
+ mux-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>;
+ i2c-parent = <&lcd_ddc>;
+ idle-state = <0x0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi-bridge@7 {
+ compatible = "toshiba,tc358768";
+ reg = <0x7>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clocks = <&tc358768_osc>;
+ clock-names = "refclk";
+
+ reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
+
+ vddc-supply = <&vdd_1v2_mipi>;
+ vddio-supply = <&vdd_1v8_vio>;
+ vddmipi-supply = <&vdd_1v2_mipi>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ bridge_input: endpoint {
+ remote-endpoint = <&dpi_output>;
+ data-lines = <24>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ bridge_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+
+ /*
+ * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
+ * LCD SuperIPS+ Full HD panel.
+ */
+ panel@1 {
+ compatible = "panasonic,vvx10f004b00";
+ reg = <1>;
+
+ power-supply = <&vdd_pnl>;
+ backlight = <&backlight>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&bridge_output>;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ vdd_1v2_mipi: regulator-mipi {
+ compatible = "regulator-fixed";
+ regulator-name = "tc358768_1v2_vdd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <10000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ tc358768_refclk: tc358768-refclk {
+ compatible = "fixed-clock";
+ clock-frequency = <23100000>;
+ clock-accuracy = <100>;
+ #clock-cells = <0>;
+ };
+
+ tc358768_osc: tc358768-osc-gate {
+ compatible = "gpio-gate-clock";
+ enable-gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>;
+ clocks = <&tc358768_refclk>;
+ #clock-cells = <0>;
+ };
+
+ memory-controller@7000f000 {
+ emc-timings-0 {
+ /* Micron 1GB 800MHZ */
+ nvidia,ram-code = <0>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00020001 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x75830303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010001 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x74630303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000001 0xc0000030
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000002 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0503 0x73c30504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000025
+ 0x00000001 0x00000001 0x00000005 0x00000002
+ 0x00000004 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0505 0x73840a06 0x001f0000 >;
+ };
+
+ timing-400000000 {
+ clock-frequency = <400000000>;
+
+ nvidia,emem-configuration = < 0x00000006 0xc0000048
+ 0x00000001 0x00000002 0x00000009 0x00000005
+ 0x00000007 0x00000001 0x00000002 0x00000008
+ 0x00000002 0x00000002 0x00000003 0x00000006
+ 0x06030202 0x000d0709 0x7086120a 0x001f0000 >;
+ };
+
+ timing-800000000 {
+ clock-frequency = <800000000>;
+
+ nvidia,emem-configuration = < 0x0000000c 0xc0000090
+ 0x00000004 0x00000005 0x00000013 0x0000000c
+ 0x0000000f 0x00000002 0x00000003 0x0000000c
+ 0x00000002 0x00000002 0x00000004 0x00000008
+ 0x08040202 0x00160d13 0x712c2414 0x001f0000 >;
+ };
+ };
+
+ emc-timings-1 {
+ /* Elpida 1GB 800MHZ */
+ nvidia,ram-code = <1>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00020001 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x75830303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010001 0xc0000020
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0502 0x74630303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000001 0xc0000030
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000002 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0503 0x73c30504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000025
+ 0x00000001 0x00000001 0x00000005 0x00000002
+ 0x00000004 0x00000001 0x00000003 0x00000008
+ 0x00000002 0x00000001 0x00000002 0x00000006
+ 0x06020102 0x000a0505 0x73840a06 0x001f0000 >;
+ };
+
+ timing-400000000 {
+ clock-frequency = <400000000>;
+
+ nvidia,emem-configuration = < 0x00000006 0xc0000048
+ 0x00000001 0x00000002 0x00000009 0x00000005
+ 0x00000007 0x00000001 0x00000002 0x00000008
+ 0x00000002 0x00000002 0x00000003 0x00000006
+ 0x06030202 0x000d0709 0x7086120a 0x001f0000 >;
+ };
+
+ timing-800000000 {
+ clock-frequency = <800000000>;
+
+ nvidia,emem-configuration = < 0x0000000c 0xc0000090
+ 0x00000004 0x00000005 0x00000013 0x0000000c
+ 0x0000000f 0x00000002 0x00000003 0x0000000c
+ 0x00000002 0x00000002 0x00000004 0x00000008
+ 0x08040202 0x00160d13 0x712c2414 0x001f0000 >;
+ };
+ };
+ };
+
+ memory-controller@7000f400 {
+ emc-timings-0 {
+ /* Micron 1GB 800MHZ */
+ nvidia,ram-code = <0>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000006 0x00000000 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x000000c0 0x00000000 0x00000030
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000007 0x00000007
+ 0x00000004 0x00000002 0x00000000 0x00000004
+ 0x00000005 0x000000c7 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000002
+ 0x0000000d 0x00000001 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x00000181 0x00000000 0x00000060
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x0000000e 0x0000000e
+ 0x00000004 0x00000003 0x00000000 0x00000004
+ 0x00000005 0x0000018e 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000004
+ 0x0000001a 0x00000003 0x00000001 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000001
+ 0x00000001 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x00000303 0x00000000 0x000000c0
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x0000001c 0x0000001c
+ 0x00000004 0x00000005 0x00000000 0x00000004
+ 0x00000005 0x0000031c 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000009
+ 0x00000035 0x00000007 0x00000002 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000002
+ 0x00000002 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000006 0x00000004 0x0000000a
+ 0x0000000b 0x00000607 0x00000000 0x00000181
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000038 0x00000038
+ 0x00000004 0x00000009 0x00000000 0x00000004
+ 0x00000005 0x00000638 0x00000007 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x004400a4
+ 0x00008000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00020000
+ 0x00000100 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-400000000 {
+ clock-frequency = <400000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200000>;
+ nvidia,emc-mode-reset = <0x80000521>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+
+ nvidia,emc-configuration = < 0x00000012
+ 0x00000066 0x0000000c 0x00000004 0x00000003
+ 0x00000008 0x00000002 0x0000000a 0x00000004
+ 0x00000004 0x00000002 0x00000001 0x00000000
+ 0x00000004 0x00000006 0x00000004 0x0000000a
+ 0x0000000c 0x00000bf0 0x00000000 0x000002fc
+ 0x00000001 0x00000008 0x00000001 0x00000000
+ 0x00000008 0x0000000f 0x0000006c 0x00000200
+ 0x00000004 0x00000010 0x00000000 0x00000004
+ 0x00000005 0x00000c30 0x00000000 0x00000004
+ 0x00000000 0x00000000 0x00007088 0x001d0084
+ 0x00008000 0x00044000 0x00044000 0x00044000
+ 0x00044000 0x00014000 0x00014000 0x00014000
+ 0x00014000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00048000 0x00048000 0x00048000
+ 0x00048000 0x000002a0 0x0600013d 0x00000000
+ 0x77fff884 0x01f1f508 0x05057404 0x54000007
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x0158000c 0xa0f10000 0x00000000
+ 0x00000000 0x800018c8 0xe8000000 0xff00ff89 >;
+ };
+
+ timing-800000000 {
+ clock-frequency = <800000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200018>;
+ nvidia,emc-mode-reset = <0x80000d71>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000025
+ 0x000000ce 0x0000001a 0x00000009 0x00000005
+ 0x0000000d 0x00000004 0x00000013 0x00000009
+ 0x00000009 0x00000004 0x00000001 0x00000000
+ 0x00000007 0x0000000a 0x00000009 0x0000000a
+ 0x00000011 0x00001820 0x00000000 0x00000608
+ 0x00000003 0x00000012 0x00000001 0x00000000
+ 0x0000000f 0x00000018 0x000000d8 0x00000200
+ 0x00000005 0x00000020 0x00000000 0x00000007
+ 0x00000008 0x00001860 0x0000000b 0x00000006
+ 0x00000000 0x00000000 0x00005088 0xf0070191
+ 0x00008000 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x00018000 0x00018000 0x00018000
+ 0x00018000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x000002a0 0x0800013d 0x22220000
+ 0x77fff884 0x01f1f501 0x07077404 0x54000000
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x00f0000c 0xa0f10000 0x00000000
+ 0x00000000 0x8000308c 0xe8000000 0xff00ff49 >;
+ };
+ };
+
+ emc-timings-1 {
+ /* Elpida 1GB 800MHZ */
+ nvidia,ram-code = <1>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000006 0x00000000 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x000000c0 0x00000000 0x00000030
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000007 0x00000007
+ 0x00000004 0x00000002 0x00000000 0x00000004
+ 0x00000005 0x000000c7 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000002
+ 0x0000000d 0x00000001 0x00000000 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000000
+ 0x00000000 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x00000181 0x00000000 0x00000060
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x0000000e 0x0000000e
+ 0x00000004 0x00000003 0x00000000 0x00000004
+ 0x00000005 0x0000018e 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000004
+ 0x0000001a 0x00000003 0x00000001 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000001
+ 0x00000001 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000005 0x00000004 0x0000000a
+ 0x0000000b 0x00000303 0x00000000 0x000000c0
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x0000001c 0x0000001c
+ 0x00000004 0x00000005 0x00000000 0x00000004
+ 0x00000005 0x0000031c 0x00000006 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00000000
+ 0x00000040 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000009
+ 0x00000035 0x00000007 0x00000002 0x00000002
+ 0x0000000a 0x00000005 0x0000000b 0x00000002
+ 0x00000002 0x00000003 0x00000001 0x00000000
+ 0x00000005 0x00000006 0x00000004 0x0000000a
+ 0x0000000b 0x00000607 0x00000000 0x00000181
+ 0x00000002 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x0000000f 0x00000038 0x00000038
+ 0x00000004 0x00000009 0x00000000 0x00000004
+ 0x00000005 0x00000638 0x00000007 0x00000004
+ 0x00000000 0x00000000 0x00004288 0x004400a4
+ 0x00008000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000002a0 0x0800211c 0x00000000
+ 0x77fff884 0x01f1f108 0x05057404 0x54000007
+ 0x08000168 0x08000000 0x00000802 0x00020000
+ 0x00000100 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >;
+ };
+
+ timing-400000000 {
+ clock-frequency = <400000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200000>;
+ nvidia,emc-mode-reset = <0x80000521>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+
+ nvidia,emc-configuration = < 0x00000012
+ 0x00000066 0x0000000c 0x00000004 0x00000003
+ 0x00000008 0x00000002 0x0000000a 0x00000004
+ 0x00000004 0x00000002 0x00000001 0x00000000
+ 0x00000004 0x00000006 0x00000004 0x0000000a
+ 0x0000000c 0x00000bf0 0x00000000 0x000002fc
+ 0x00000001 0x00000008 0x00000001 0x00000000
+ 0x00000008 0x0000000f 0x0000006c 0x00000200
+ 0x00000004 0x00000010 0x00000000 0x00000004
+ 0x00000005 0x00000c30 0x00000000 0x00000004
+ 0x00000000 0x00000000 0x00007088 0x001d0084
+ 0x00008000 0x00044000 0x00044000 0x00044000
+ 0x00044000 0x00014000 0x00014000 0x00014000
+ 0x00014000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00048000 0x00048000 0x00048000
+ 0x00048000 0x000002a0 0x0600013d 0x00000000
+ 0x77fff884 0x01f1f508 0x05057404 0x54000007
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x0158000c 0xa0f10000 0x00000000
+ 0x00000000 0x800018c8 0xe8000000 0xff00ff89 >;
+ };
+
+ timing-800000000 {
+ clock-frequency = <800000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200018>;
+ nvidia,emc-mode-reset = <0x80000d71>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000025
+ 0x000000ce 0x0000001a 0x00000009 0x00000005
+ 0x0000000d 0x00000004 0x00000013 0x00000009
+ 0x00000009 0x00000004 0x00000001 0x00000000
+ 0x00000007 0x0000000a 0x00000009 0x0000000a
+ 0x00000011 0x00001820 0x00000000 0x00000608
+ 0x00000003 0x00000012 0x00000001 0x00000000
+ 0x0000000f 0x00000018 0x000000d8 0x00000200
+ 0x00000005 0x00000020 0x00000000 0x00000007
+ 0x00000008 0x00001860 0x0000000b 0x00000006
+ 0x00000000 0x00000000 0x00005088 0xf0070191
+ 0x00008000 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x00018000 0x00018000 0x00018000
+ 0x00018000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x000002a0 0x0a00013d 0x22220000
+ 0x77fff884 0x01f1f501 0x07077404 0x54000000
+ 0x080001e8 0x08000021 0x00000802 0x00020000
+ 0x00000100 0x00f0000c 0xa0f10000 0x00000000
+ 0x00000000 0x8000308c 0xe8000000 0xff00ff49 >;
+ };
+ };
+ };
+};
+
+&emc_icc_dvfs_opp_table {
+ /delete-node/ opp-900000000-1350;
+};
+
+&emc_bw_dfs_opp_table {
+ /delete-node/ opp-900000000;
+};
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 12/28] ARM: tegra: Add device-tree for ASUS Transformer Pad TF701T
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (10 preceding siblings ...)
2021-12-11 21:13 ` [PATCH v6 11/28] ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 13/28] ARM: tegra: Add device-tree for Pegatron Chagall Dmitry Osipenko
` (15 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Anton Bambura <jenneron@protonmail.com>
Add device-tree for Tegra114-based ASUS Transformer Pad TF701T (K00C)
tablet.
Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Pad_(TF701T)_(asus-tf701t)
Signed-off-by: Anton Bambura <jenneron@protonmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/tegra114-asus-tf701t.dts | 788 +++++++++++++++++++++
2 files changed, 789 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra114-asus-tf701t.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 87166d66e0b1..e59e7973990d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1331,6 +1331,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-colibri-eval-v3.dtb \
tegra30-ouya.dtb
dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
+ tegra114-asus-tf701t.dtb \
tegra114-dalmore.dtb \
tegra114-roth.dtb \
tegra114-tn7.dtb
diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/tegra114-asus-tf701t.dts
new file mode 100644
index 000000000000..3026a869de63
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114-asus-tf701t.dts
@@ -0,0 +1,788 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+
+#include "tegra114.dtsi"
+
+/ {
+ model = "Asus Transformer Pad TF701T";
+ compatible = "asus,tf701t", "nvidia,tegra114";
+ chassis-type = "convertible";
+
+ aliases {
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc3; /* uSD slot */
+ mmc2 = &sdmmc1; /* WiFi */
+
+ rtc0 = &palmas;
+ rtc1 = &tegra_rtc;
+
+ serial0 = &uartd; /* Console */
+ serial1 = &uartc; /* Bluetooth */
+ serial2 = &uartb; /* GPS */
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,cma@80000000 {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x80000000 0x30000000>;
+ size = <0x10000000>;
+ linux,cma-default;
+ reusable;
+ };
+
+ trustzone@bfe00000 {
+ reg = <0xbfe00000 0x200000>;
+ no-map;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_5v0_sys>;
+ pwms = <&pwm 1 1000000>;
+
+ brightness-levels = <1 255>;
+ num-interpolated-steps = <254>;
+ default-brightness-level = <224>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&backlight_default>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
+ };
+
+ firmware {
+ trusted-foundations {
+ compatible = "tlm,trusted-foundations";
+ tlm,version-major = <2>;
+ tlm,version-minor = <8>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ label = "GPIO Buttons";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_default>;
+
+ power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <10>;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <10>;
+ };
+ };
+
+ gpio-hall-sensor {
+ compatible = "gpio-keys";
+
+ label = "GPIO Hall Effect Sensor";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_hall_sensor_default>;
+
+ hall-sensor {
+ label = "Hall Effect Sensor";
+ gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ sound {
+ compatible = "asus,tegra-audio-rt5639-tf701t",
+ "nvidia,tegra-audio-rt5640";
+ nvidia,model = "Asus Transformer Pad TF701T RT5639";
+
+ nvidia,audio-routing =
+ "Headphones", "HPOR",
+ "Headphones", "HPOL",
+ "Speakers", "SPORP",
+ "Speakers", "SPORN",
+ "Speakers", "SPOLP",
+ "Speakers", "SPOLN",
+ "Mic Jack", "MICBIAS1",
+ "IN2P", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s0>;
+ nvidia,audio-codec = <&rt5639>;
+
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>;
+
+ clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
+ <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA114_CLK_EXTERN1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det_default>;
+ };
+
+ vdd_5v0_sys: regulator-5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_3v3_sys: regulator-3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_lcd: regulator-vdd-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_lcd_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&tps65913_smps8>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_lcd_default>;
+ };
+
+ vdd_usd: regulator-vdd-usd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_sd_slot";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ vin-supply = <&tps65913_smps9>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc3_vdd_default>;
+ };
+};
+
+&dsia {
+ status = "okay";
+
+ avdd-dsi-csi-supply = <&tps65913_ldo2>;
+
+ nvidia,ganged-mode = <&dsib>;
+
+ panel_primary: panel@0 {
+ compatible = "sharp,lq101r1sx03", "sharp,lq101r1sx01";
+ reg = <0>;
+
+ link2 = <&panel_secondary>;
+
+ power-supply = <&vdd_lcd>;
+ backlight = <&backlight>;
+ };
+};
+
+&dsib {
+ status = "okay";
+
+ avdd-dsi-csi-supply = <&tps65913_ldo2>;
+
+ nvidia,ganged-mode;
+
+ panel_secondary: panel@0 {
+ compatible = "sharp,lq101r1sx03", "sharp,lq101r1sx01";
+ reg = <0>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ magnetometer@c {
+ compatible = "asahi-kasei,ak09911";
+ reg = <0xc>;
+
+ vdd-supply = <&vdd_3v3_sys>;
+ };
+
+ rt5639: audio-codec@1c {
+ compatible = "realtek,rt5639";
+ reg = <0x1c>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
+
+ realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&codec_default>;
+ };
+
+ motion-tracker@68 {
+ compatible = "invensense,mpu6500";
+ reg = <0x68>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(R, 3) IRQ_TYPE_LEVEL_HIGH>;
+
+ mount-matrix = "0", "-1", "0",
+ "1", "0", "0",
+ "0", "0", "1";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&imu_default>;
+ };
+
+ temp_sensor: temperature-sensor@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+
+ vcc-supply = <&vdd_3v3_sys>;
+ #thermal-sensor-cells = <1>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ power-sensor@44 {
+ compatible = "ti,ina230";
+ reg = <0x44>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ light-sensor@1c {
+ compatible = "dynaimage,al3320a";
+ reg = <0x1c>;
+
+ vdd-supply = <&vdd_3v3_sys>;
+ };
+};
+
+&i2c4 {
+ /* HDMI DDC */
+};
+
+&i2c5 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ palmas: pmic@58 {
+ compatible = "ti,palmas";
+ reg = <0x58>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ palmas_gpio: gpio {
+ compatible = "ti,palmas-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pmic {
+ compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
+
+ ldo1-in-supply = <&tps65913_smps7>;
+ ldo2-in-supply = <&tps65913_smps7>;
+ ldo4-in-supply = <&tps65913_smps8>;
+ ldo5-in-supply = <&tps65913_smps9>;
+ ldo6-in-supply = <&tps65913_smps9>;
+ ldo7-in-supply = <&tps65913_smps9>;
+ ldo9-in-supply = <&tps65913_smps9>;
+
+ regulators {
+ tps65913_smps123: smps123 {
+ regulator-name = "vdd-cpu";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,roof-floor = <1>;
+ ti,mode-sleep = <3>;
+ };
+
+ tps65913_smps45: smps45 {
+ regulator-name = "vdd-core";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,roof-floor = <3>;
+ };
+
+ smps6 {
+ regulator-name = "va-lcd-hv";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ tps65913_smps7: smps7 {
+ regulator-name = "vdd-ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ tps65913_smps8: smps8 {
+ regulator-name = "vdd-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ tps65913_smps9: smps9 {
+ regulator-name = "vdd-sd";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-always-on;
+ };
+
+ tps65913_smps10_out1: smps10_out1 {
+ regulator-name = "vd-smps10-out1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ tps65913_smps10_out2: smps10_out2 {
+ regulator-name = "vd-smps10-out2";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ tps65913_ldo1: ldo1 {
+ regulator-name = "vdd-hdmi-pll";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ ti,roof-floor = <3>;
+ };
+
+ tps65913_ldo2: ldo2 {
+ regulator-name = "vdd-2v8-dsi-csi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ };
+
+ ldo3 {
+ regulator-name = "vpp-fuse";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo4 {
+ regulator-name = "vdd-1v2-cam";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo5 {
+ regulator-name = "vdd-cam";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo6 {
+ regulator-name = "vdd-dev";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-boot-on;
+ };
+
+ ldo7 {
+ regulator-name = "vdd-2v8-cam";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ tps65913_ldo8: ldo8 {
+ regulator-name = "vdd-rtc";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <950000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,enable-ldo8-tracking;
+ };
+
+ tps65913_ldo9: ldo9 {
+ regulator-name = "vdd-sdmmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ tps65913_ldoln: ldoln {
+ regulator-name = "vdd-hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldousb {
+ regulator-name = "vdd-usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ rtc {
+ compatible = "ti,palmas-rtc";
+ interrupt-parent = <&palmas>;
+ interrupts = <8 0>;
+ };
+
+ pinmux {
+ compatible = "ti,tps65913-pinctrl";
+ ti,palmas-enable-dvfs1;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&palmas_default>;
+
+ palmas_default: pinmux {
+ pin_powergood {
+ pins = "powergood";
+ function = "powergood";
+ };
+
+ pin_vac {
+ pins = "vac";
+ function = "vac";
+ };
+
+ pin_gpio0 {
+ pins = "gpio0";
+ function = "gpio";
+ };
+
+ pin_gpio1 {
+ pins = "gpio1";
+ function = "gpio";
+ };
+
+ pin_gpio2 {
+ pins = "gpio2";
+ function = "gpio";
+ };
+
+ pin_gpio3 {
+ pins = "gpio3";
+ function = "gpio";
+ };
+
+ pin_gpio4 {
+ pins = "gpio4";
+ function = "gpio";
+ };
+
+ pin_gpio5 {
+ pins = "gpio5";
+ function = "gpio";
+ };
+
+ pin_gpio6 {
+ pins = "gpio6";
+ function = "gpio";
+ };
+
+ pin_gpio7 {
+ pins = "gpio7";
+ function = "gpio";
+ };
+ };
+ };
+ };
+};
+
+&pwm {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_default>;
+};
+
+&sdmmc1 {
+ /* WiFi */
+};
+
+/* MicroSD card */
+&sdmmc3 {
+ status = "okay";
+
+ bus-width = <4>;
+ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+
+ nvidia,default-tap = <0x3>;
+ nvidia,default-trim = <0x3>;
+
+ vmmc-supply = <&vdd_usd>;
+ vqmmc-supply = <&tps65913_ldo9>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc3_default>;
+};
+
+&sdmmc4 {
+ /* eMMC */
+};
+
+&tegra_i2s0 {
+ status = "okay";
+};
+
+&uartb {
+ /* GPS */
+};
+
+&uartc {
+ /* Bluetooth */
+};
+
+&uartd {
+ status = "okay";
+};
+
+&usb1 {
+ compatible = "nvidia,tegra114-udc";
+ status = "okay";
+ dr_mode = "peripheral";
+
+ /* Peripheral USB via ASUS connector */
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+
+ /* Host USB via dock */
+};
+
+&usb3_phy {
+ status = "okay";
+ vbus-supply = <&vdd_5v0_sys>;
+};
+
+&pinmux {
+ asus_pad_ec_default: asus-pad-ec-default {
+ ec-interrupt {
+ nvidia,pins = "kb_col5_pq5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ec-request {
+ nvidia,pins = "kb_col2_pq2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+
+ backlight_default: backlight-default {
+ backlight-enable {
+ nvidia,pins = "gmi_ad10_ph2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+
+ codec_default: codec-default {
+ ldo1-en {
+ nvidia,pins = "sdmmc1_wp_n_pv3";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ interrupt {
+ nvidia,pins = "gpio_w2_aud_pw2",
+ "gpio_w3_aud_pw3";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+
+ gpio_keys_default: gpio-keys-default {
+ power {
+ nvidia,pins = "kb_col0_pq0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ volume {
+ nvidia,pins = "kb_row1_pr1",
+ "kb_row2_pr2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+
+ gpio_hall_sensor_default: gpio-hall-sensor-default {
+ ulpi_data4_po5 {
+ nvidia,pins = "ulpi_data4_po5";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+
+ hp_det_default: hp-det-default {
+ gmi_iordy_pi5 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+
+ imu_default: imu-default {
+ kb_row3_pr3 {
+ nvidia,pins = "kb_row3_pr3";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+
+ pwm_default: pwm-default {
+ gmi_ad9_ph1 {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+
+ sdmmc3_default: sdmmc3-default {
+ sdmmc3_clk_pa6 {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_cmd_pa7 {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4",
+ "kb_col4_pq4",
+ "sdmmc3_clk_lb_out_pee4",
+ "sdmmc3_clk_lb_in_pee5",
+ "sdmmc3_cd_n_pv2";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ drive_sdio3 {
+ nvidia,pins = "drive_sdio3";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <22>;
+ nvidia,pull-up-strength = <36>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ };
+
+ sdmmc3_vdd_default: sdmmc3-vdd-default {
+ gmi_clk_pk1 {
+ nvidia,pins = "gmi_clk_pk1";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+
+ vdd_lcd_default: vdd-lcd-default {
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+};
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 13/28] ARM: tegra: Add device-tree for Pegatron Chagall
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (11 preceding siblings ...)
2021-12-11 21:13 ` [PATCH v6 12/28] ARM: tegra: Add device-tree for ASUS Transformer Pad TF701T Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 14/28] ARM: tegra: Add device-tree for 1080p version of Nyan Big Dmitry Osipenko
` (14 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Svyatoslav Ryhel <clamor95@gmail.com>
Add device-tree for Pegatron Chagall, which is a NVIDIA Tegra30-based
Android tablet.
Link: https://wiki.postmarketos.org/wiki/Pegatron_Chagall_(pegatron-chagall)
Co-developed-by: Raffaele Tranquillini <raffaele.tranquillini@gmail.com>
Signed-off-by: Raffaele Tranquillini <raffaele.tranquillini@gmail.com>
Co-developed-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Ion Agorria <ion@agorria.com>
Co-developed-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/Makefile | 3 +-
.../arm/boot/dts/tegra30-pegatron-chagall.dts | 2794 +++++++++++++++++
2 files changed, 2796 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/tegra30-pegatron-chagall.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e59e7973990d..26798673739c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1329,7 +1329,8 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
tegra30-colibri-eval-v3.dtb \
- tegra30-ouya.dtb
+ tegra30-ouya.dtb \
+ tegra30-pegatron-chagall.dtb
dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
tegra114-asus-tf701t.dtb \
tegra114-dalmore.dtb \
diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts
new file mode 100644
index 000000000000..08523f622203
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts
@@ -0,0 +1,2794 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/thermal/thermal.h>
+
+#include "tegra30.dtsi"
+#include "tegra30-cpu-opp.dtsi"
+#include "tegra30-cpu-opp-microvolt.dtsi"
+#include "tegra30-asus-lvds-display.dtsi"
+
+/ {
+ model = "Pegatron Chagall";
+ compatible = "pegatron,chagall", "nvidia,tegra30";
+ chassis-type = "tablet";
+
+ aliases {
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc1; /* uSD slot */
+ mmc2 = &sdmmc3; /* WiFi */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ display0 = &lcd;
+ display1 = &hdmi;
+
+ serial1 = &uartc; /* Bluetooth */
+ serial2 = &uartb; /* GPS */
+ };
+
+ /*
+ * The decompressor and also some bootloaders rely on a
+ * pre-existing /chosen node to be available to insert the
+ * command line and merge other ATAGS info.
+ */
+ chosen {};
+
+ memory@80000000 {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,cma@80000000 {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x80000000 0x30000000>;
+ size = <0x10000000>; /* 256MiB */
+ linux,cma-default;
+ reusable;
+ };
+
+ ramoops@beb00000 {
+ compatible = "ramoops";
+ reg = <0xbeb00000 0x10000>; /* 64kB */
+ console-size = <0x8000>; /* 32kB */
+ record-size = <0x400>; /* 1kB */
+ ecc-size = <16>;
+ };
+
+ trustzone@bfe00000 {
+ reg = <0xbfe00000 0x200000>; /* 2MB */
+ no-map;
+ };
+ };
+
+ host1x@50000000 {
+ hdmi: hdmi@54280000 {
+ status = "okay";
+
+ hdmi-supply = <&hdmi_5v0_sys>;
+ pll-supply = <&vdd_1v8_vio>;
+ vdd-supply = <&vdd_3v3_sys>;
+
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ };
+ };
+
+ vde@6001a000 {
+ assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
+ assigned-clock-rates = <408000000>;
+ };
+
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* SDMMC1 pinmux */
+ sdmmc1_clk_pz0 {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_dat3_py4 {
+ nvidia,pins = "sdmmc1_dat3_py4",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC2 pinmux */
+ vi_d1_pd5 {
+ nvidia,pins = "vi_d1_pd5",
+ "vi_d2_pl0",
+ "vi_d3_pl1",
+ "vi_d5_pl3",
+ "vi_d7_pl5";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ vi_d8_pl6 {
+ nvidia,pins = "vi_d8_pl6",
+ "vi_d9_pl7";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+
+ /* SDMMC3 pinmux */
+ sdmmc3_clk_pa6 {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_cmd_pa7 {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat3_pb4",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat5_pd0",
+ "sdmmc3_dat4_pd1",
+ "sdmmc3_dat6_pd3",
+ "sdmmc3_dat7_pd4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SDMMC4 pinmux */
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_cmd_pt7 {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* I2C pinmux */
+ gen1_i2c_scl_pc4 {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ gen2_i2c_scl_pt5 {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ cam_i2c_scl_pbb1 {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ ddc_scl_pv4 {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+ pwr_i2c_scl_pz6 {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+
+ /* HDMI-CEC pinmux */
+ hdmi_cec_pee3 {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ };
+
+ /* UART-A */
+ ulpi_data0_po1 {
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data1_po2 {
+ nvidia,pins = "ulpi_data1_po2",
+ "ulpi_data2_po3",
+ "ulpi_data3_po4",
+ "ulpi_data4_po5",
+ "ulpi_data5_po6",
+ "ulpi_data6_po7";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_data7_po0 {
+ nvidia,pins = "ulpi_data7_po0";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* UART-B */
+ uart2_txd_pc2 {
+ nvidia,pins = "uart2_txd_pc2",
+ "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart2_rxd_pc3 {
+ nvidia,pins = "uart2_rxd_pc3",
+ "uart2_cts_n_pj5";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* UART-C */
+ uart3_cts_n_pa1 {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart3_rts_n_pc0 {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* UART-D */
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_stp_py3";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_dir_py1 {
+ nvidia,pins = "ulpi_dir_py1",
+ "ulpi_nxt_py2";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* I2S pinmux */
+ dap1_fs_pn0 {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap2_fs_pa2 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_fs_pp0 {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_din_pp1",
+ "dap3_dout_pp2",
+ "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap4_fs_pp4 {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pcc2 {
+ nvidia,pins = "pcc2";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PCI-e pinmux */
+ pex_l2_rst_n_pcc6 {
+ nvidia,pins = "pex_l2_rst_n_pcc6",
+ "pex_l0_rst_n_pdd1",
+ "pex_l1_rst_n_pdd5";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pex_l2_clkreq_n_pcc7 {
+ nvidia,pins = "pex_l2_clkreq_n_pcc7",
+ "pex_l0_prsnt_n_pdd0",
+ "pex_l0_clkreq_n_pdd2",
+ "pex_l2_prsnt_n_pdd7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pex_wake_n_pdd3 {
+ nvidia,pins = "pex_wake_n_pdd3";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* SPI pinmux */
+ spi1_mosi_px4 {
+ nvidia,pins = "spi1_mosi_px4",
+ "spi1_sck_px5",
+ "spi1_cs0_n_px6",
+ "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2_cs1_n_pw2 {
+ nvidia,pins = "spi2_cs1_n_pw2",
+ "spi2_cs2_n_pw3";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2_sck_px2 {
+ nvidia,pins = "spi2_sck_px2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_a16_pj7 {
+ nvidia,pins = "gmi_a16_pj7",
+ "gmi_a19_pk7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_a17_pb0 {
+ nvidia,pins = "gmi_a17_pb0",
+ "gmi_a18_pb1";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi2_mosi_px0 {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_out_pk5 {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_in_pk6 {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Display A pinmux */
+ lcd_pwr0_pb2 {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pclk_pb3",
+ "lcd_pwr1_pc1",
+ "lcd_pwr2_pc6",
+ "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_de_pj1",
+ "lcd_hsync_pj3",
+ "lcd_vsync_pj4",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7",
+ "lcd_cs0_n_pn4",
+ "lcd_sdout_pn5",
+ "lcd_dc0_pn6",
+ "lcd_sdin_pz2",
+ "lcd_wr_n_pz3",
+ "lcd_sck_pz4",
+ "lcd_cs1_n_pw0",
+ "lcd_m1_pw1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_dc1_pd2 {
+ nvidia,pins = "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk_32k_out_pa0 {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "blink";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* KBC keys */
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0",
+ "kb_row1_pr1",
+ "kb_row2_pr2",
+ "kb_row3_pr3",
+ "kb_row8_ps0",
+ "kb_col0_pq0",
+ "kb_col1_pq1",
+ "kb_col2_pq2",
+ "kb_col3_pq3",
+ "kb_col4_pq4",
+ "kb_col5_pq5",
+ "kb_col7_pq7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row4_pr4 {
+ nvidia,pins = "kb_row4_pr4",
+ "kb_row7_pr7",
+ "kb_row10_ps2",
+ "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row11_ps3 {
+ nvidia,pins = "kb_row11_ps3",
+ "kb_row12_ps4",
+ "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row14_ps6 {
+ nvidia,pins = "kb_row14_ps6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_iordy_pi5 {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ vi_pclk_pt0 {
+ nvidia,pins = "vi_pclk_pt0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+ pu1 {
+ nvidia,pins = "pu1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu2 {
+ nvidia,pins = "pu2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pv0 {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pv1 {
+ nvidia,pins = "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pcc1 {
+ nvidia,pins = "pcc1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_rst_n_pcc3 {
+ nvidia,pins = "sdmmc4_rst_n_pcc3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pv3 {
+ nvidia,pins = "pv3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ vi_vsync_pd6 {
+ nvidia,pins = "vi_vsync_pd6",
+ "vi_hsync_pd7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+ vi_d10_pt2 {
+ nvidia,pins = "vi_d10_pt2",
+ "vi_d0_pt4", "pbb0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ vi_d11_pt3 {
+ nvidia,pins = "vi_d11_pt3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pu0 {
+ nvidia,pins = "pu0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu6 {
+ nvidia,pins = "pu6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pex_l1_prsnt_n_pdd4 {
+ nvidia,pins = "pex_l1_prsnt_n_pdd4",
+ "pex_l1_clkreq_n_pdd6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_wait_pi7 {
+ nvidia,pins = "gmi_wait_pi7",
+ "gmi_cs0_n_pj0",
+ "gmi_cs1_n_pj2",
+ "gmi_cs4_n_pk2";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad0_pg0 {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad1_pg1",
+ "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_ad4_pg4",
+ "gmi_ad5_pg5",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7",
+ "gmi_wr_n_pi0",
+ "gmi_oe_n_pi1",
+ "gmi_dqs_pi2",
+ "gmi_adv_n_pk0",
+ "gmi_clk_pk1";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_cs2_n_pk3 {
+ nvidia,pins = "gmi_cs2_n_pk3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_cs3_n_pk4 {
+ nvidia,pins = "gmi_cs3_n_pk4";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad10_ph2 {
+ nvidia,pins = "gmi_ad10_ph2",
+ "gmi_ad11_ph3",
+ "gmi_ad14_ph6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad13_ph5 {
+ nvidia,pins = "gmi_ad13_ph5",
+ "gmi_ad12_ph4",
+ "gmi_cs7_n_pi6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_rst_n_pi4 {
+ nvidia,pins = "gmi_rst_n_pi4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_ad8_ph0 {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad9_ph1 {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_wp_n_pc7 {
+ nvidia,pins = "gmi_wp_n_pc7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_cs6_n_pi3 {
+ nvidia,pins = "gmi_cs6_n_pi3";
+ nvidia,function = "sata";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_d4_pl2 {
+ nvidia,pins = "vi_d4_pl2";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ vi_d6_pl4 {
+ nvidia,pins = "vi_d6_pl4";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,lock = <0>;
+ nvidia,ioreset = <0>;
+ };
+ vi_mclk_pt1 {
+ nvidia,pins = "vi_mclk_pt1";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* HDMI hot-plug-detect */
+ hdmi_int_pn7 {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "hdmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ jtag_rtck_pu7 {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ crt_hsync_pv6 {
+ nvidia,pins = "crt_hsync_pv6",
+ "crt_vsync_pv7";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ clk1_out_pw4 {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_out_pw5 {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3_out_pee0 {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sys_clk_req_pz5 {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "sysclk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb6 {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk1_req_pee2 {
+ nvidia,pins = "clk1_req_pee2";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk2_req_pcc5 {
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ clk3_req_pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pv2 {
+ nvidia,pins = "pv2",
+ "kb_row5_pr5";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_mclk_pcc0 {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive_dap1 {
+ nvidia,pins = "drive_dap1",
+ "drive_dap2",
+ "drive_dbg",
+ "drive_at5",
+ "drive_gme",
+ "drive_ddc",
+ "drive_ao1",
+ "drive_uart3";
+ nvidia,high-speed-mode = <0>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ drive_sdio1 {
+ nvidia,pins = "drive_sdio1";
+ nvidia,high-speed-mode = <0>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <5>;
+ nvidia,pull-up-strength = <5>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
+ };
+ drive_sdio3 {
+ nvidia,pins = "drive_sdio3";
+ nvidia,high-speed-mode = <0>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
+ };
+ drive_gma {
+ nvidia,pins = "drive_gma",
+ "drive_gmb",
+ "drive_gmc",
+ "drive_gmd";
+ nvidia,pull-down-strength = <9>;
+ nvidia,pull-up-strength = <9>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+ drive_lcd2 {
+ nvidia,pins = "drive_lcd2";
+ nvidia,high-speed-mode = <0>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>;
+ nvidia,pull-down-strength = <20>;
+ nvidia,pull-up-strength = <20>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ };
+ };
+
+ uartb: serial@70006040 {
+ compatible = "nvidia,tegra30-hsuart";
+ status = "okay";
+
+ /* Broadcom GPS BCM47511 */
+ };
+
+ uartc: serial@70006200 {
+ compatible = "nvidia,tegra30-hsuart";
+ status = "okay";
+
+ nvidia,adjust-baud-rates = <0 9600 100>,
+ <9600 115200 200>,
+ <1000000 4000000 136>;
+
+ /* Azurewave AW-AH663 BCM4330B1 */
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ max-speed = <4000000>;
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
+ clock-names = "txco";
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "host-wakeup";
+
+ device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
+
+ vbat-supply = <&vdd_3v3_sys>;
+ vddio-supply = <&vdd_1v8_vio>;
+ };
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ lcd_ddc: i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Wolfson Microelectronics WM8903 audio codec */
+ wm8903: audio-codec@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_BOTH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+
+ gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+
+ AVDD-supply = <&vdd_1v8_vio>;
+ CPVDD-supply = <&vdd_1v8_vio>;
+ DBVDD-supply = <&vdd_1v8_vio>;
+ DCVDD-supply = <&vdd_1v8_vio>;
+ };
+
+ };
+
+ i2c2: i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Atmel touchscreen */
+ touchscreen@4d {
+ compatible = "atmel,maxtouch";
+ reg = <0x4d>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>;
+
+ vdda-supply = <&vdd_3v3_sys>;
+ vdd-supply = <&vdd_3v3_sys>;
+ };
+ };
+
+ i2c3: i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ light-sensor@44 {
+ compatible = "isil,isl29023";
+ reg = <0x44>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(Q, 3) IRQ_TYPE_LEVEL_HIGH>;
+
+ vcc-supply = <&vdd_3v3_sen>;
+ };
+
+ /* AsahiKASEI AK8975 magnetometer sensor */
+ magnetometer@c {
+ compatible = "asahi-kasei,ak8975";
+ reg = <0x0c>;
+
+ vdd-supply = <&vdd_3v3_sen>;
+ vid-supply = <&vdd_1v8_vio>;
+
+ mount-matrix = "0", "1", "0",
+ "1", "0", "0",
+ "0", "0", "-1";
+ };
+
+ gyroscope@68 {
+ compatible = "invensense,mpu3050";
+ reg = <0x68>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&vdd_3v3_sen>;
+ vlogic-supply = <&vdd_1v8_vio>;
+
+ mount-matrix = "0", "1", "0",
+ "1", "0", "0",
+ "0", "0", "-1";
+
+ /* External I2C interface */
+ i2c-gate {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@f {
+ compatible = "kionix,kxtf9";
+ reg = <0x0f>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(L, 1) IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&vdd_1v8_vio>;
+ vddio-supply = <&vdd_1v8_vio>;
+
+ mount-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "1";
+ };
+ };
+ };
+ };
+
+ hdmi_ddc: i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <93750>;
+ };
+
+ i2c5: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ nct72: temperature-sensor@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(U, 5) IRQ_TYPE_EDGE_FALLING>;
+
+ vcc-supply = <&vdd_3v3_sys>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ /* Texas Instruments TPS659110 PMIC */
+ pmic: pmic@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ wakeup-source;
+
+ ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
+ ti,system-power-controller;
+ ti,sleep-keep-ck32k;
+ ti,sleep-enable;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ vcc1-supply = <&vdd_5v0_sys>;
+ vcc2-supply = <&vdd_5v0_sys>;
+ vcc3-supply = <&vdd_1v8_vio>;
+ vcc4-supply = <&vdd_1v8_vio>;
+ vcc5-supply = <&vdd_5v0_sys>;
+ vcc6-supply = <&vddio_1v2_ddr>;
+ vcc7-supply = <&vdd_5v0_sys>;
+ vccio-supply = <&vdd_5v0_sys>;
+
+ pmic-sleep-hog {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>,
+ <2 GPIO_ACTIVE_HIGH>,
+ <6 GPIO_ACTIVE_HIGH>,
+ <8 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+
+ regulators {
+ /* VDD1 is not used by Chagall */
+
+ vddio_1v2_ddr: vdd2 {
+ regulator-name = "vddio_1v2_ddr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_cpu: vddctrl {
+ regulator-name = "vdd_cpu,vdd_sys";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-coupled-with = <&vdd_core>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,regulator-ext-sleep-control = <1>;
+
+ nvidia,tegra-cpu-regulator;
+ };
+
+ vdd_1v8_vio: vio {
+ regulator-name = "vdd_1v8_gen";
+ /* FIXME: eMMC won't work, if set to 1.8 V */
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* eMMC VDD */
+ vcore_emmc: ldo1 {
+ regulator-name = "vdd_emmc_core";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ /* uSD slot VDD */
+ vdd_usd: ldo2 {
+ regulator-name = "vdd_usd";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ };
+
+ /* uSD slot VDDIO */
+ vddio_usd: ldo3 {
+ regulator-name = "vddio_usd";
+ regulator-min-microvolt = <1900000>;
+ regulator-max-microvolt = <3200000>;
+ };
+
+ ldo4 {
+ regulator-name = "vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo5 {
+ regulator-name = "vdd_1v3_cam_isp";
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ ldo6 {
+ regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo7 {
+ regulator-name = "vdd_pllm,x,u,a_p_c_s";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,regulator-ext-sleep-control = <8>;
+ };
+
+ ldo8 {
+ regulator-name = "vdd_ddr_hs";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ ti,regulator-ext-sleep-control = <8>;
+ };
+ };
+ };
+
+ vdd_core: core-regulator@60 {
+ compatible = "ti,tps62361";
+ reg = <0x60>;
+
+ regulator-name = "tps62361-vout";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1770000>;
+ regulator-coupled-with = <&vdd_cpu>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ti,enable-vout-discharge;
+ ti,vsel0-state-high;
+ ti,vsel1-state-high;
+
+ nvidia,tegra-core-regulator;
+ };
+ };
+
+ vdd_5v0_sys: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_3v3_sys: regulator-3v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_pnl: regulator-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <300000>;
+ gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ vdd_3v3_sen: regulator-sensors {
+ compatible = "regulator-fixed";
+ regulator-name = "sen_3v3_en";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ vdd_5v0_bl: regulator-bl {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0_bl";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ hdmi_5v0_sys: regulator-hdmi {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi_5v0_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_vbus_usb1: regulator-usb1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_vbus_micro_usb";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_vbus_usb3: regulator-usb3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_vbus_typea_usb";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ pmc@7000e400 {
+ status = "okay";
+ nvidia,invert-interrupt;
+ nvidia,suspend-mode = <2>;
+ nvidia,cpu-pwr-good-time = <2000>;
+ nvidia,cpu-pwr-off-time = <200>;
+ nvidia,core-pwr-good-time = <3845 3845>;
+ nvidia,core-pwr-off-time = <0>;
+ nvidia,core-power-req-active-high;
+ nvidia,sys-clock-req-active-high;
+ core-supply = <&vdd_core>;
+
+ /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */
+ i2c-thermtrip {
+ nvidia,i2c-controller-id = <4>;
+ nvidia,bus-addr = <0x2d>;
+ nvidia,reg-addr = <0x3f>;
+ nvidia,reg-data = <0x81>;
+ };
+ };
+
+ hda@70030000 {
+ status = "okay";
+ };
+
+ ahub@70080000 {
+ i2s@70080400 { /* i2s1 */
+ status = "okay";
+ };
+
+ /* BT SCO */
+ i2s@70080600 { /* i2s3 */
+ status = "okay";
+ };
+ };
+
+ sdmmc1: mmc@78000000 {
+ status = "okay";
+
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+
+ vmmc-supply = <&vdd_usd>; /* ldo2 */
+ vqmmc-supply = <&vddio_usd>; /* ldo3 */
+ };
+
+ brcm_wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
+ clock-names = "ext_clock";
+
+ reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <300>;
+ power-off-delay-us = <300>;
+ };
+
+ sdmmc3: mmc@78000400 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
+ assigned-clock-rates = <50000000>;
+
+ max-frequency = <50000000>;
+ keep-power-in-suspend;
+ bus-width = <4>;
+ non-removable;
+
+ mmc-pwrseq = <&brcm_wifi_pwrseq>;
+ vmmc-supply = <&vdd_3v3_sys>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+
+ /* Azurewave AW-AH663 BCM4330B1 */
+ wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+ };
+
+ sdmmc4: mmc@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ non-removable;
+ };
+
+ usb@7d000000 {
+ compatible = "nvidia,tegra30-udc";
+ status = "okay";
+ dr_mode = "otg";
+ vbus-supply = <&vdd_vbus_usb1>;
+ };
+
+ usb-phy@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
+ usb@7d008000 {
+ status = "okay";
+ };
+
+ usb-phy@7d008000 {
+ status = "okay";
+ vbus-supply = <&vdd_vbus_usb3>;
+ };
+
+ mains: ac-adapter-detect {
+ compatible = "gpio-charger";
+ charger-type = "mains";
+ gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_5v0_bl>;
+ pwms = <&pwm 0 5000000>;
+
+ brightness-levels = <1 255>;
+ num-interpolated-steps = <254>;
+ default-brightness-level = <15>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ cpu1: cpu@1 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ cpu2: cpu@2 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ cpu3: cpu@3 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ display-panel {
+ compatible = "panel-lvds";
+
+ width-mm = <217>;
+ height-mm = <136>;
+
+ data-mapping = "jeida-24";
+
+ panel-timing {
+ /* 1280x800@60Hz */
+ clock-frequency = <68000000>;
+ hactive = <1280>;
+ vactive = <800>;
+ hfront-porch = <48>;
+ hback-porch = <18>;
+ hsync-len = <30>;
+ vsync-len = <5>;
+ vfront-porch = <3>;
+ vback-porch = <12>;
+ };
+ };
+
+ extcon-keys {
+ compatible = "gpio-keys";
+ interrupt-parent = <&gpio>;
+
+ dock-insert {
+ label = "Chagall Dock";
+ gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_DOCK>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ lineout-detect {
+ label = "Audio dock line-out detect";
+ gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LINEOUT_INSERT>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
+
+ firmware {
+ trusted-foundations {
+ compatible = "tlm,trusted-foundations";
+ tlm,version-major = <2>;
+ tlm,version-minor = <8>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ interrupt-parent = <&gpio>;
+
+ power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
+
+ haptic-feedback {
+ compatible = "gpio-vibrator";
+ enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
+ vcc-supply = <&vdd_3v3_sys>;
+ };
+
+ sound {
+ compatible = "pegatron,tegra-audio-wm8903-chagall",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "Pegatron Chagall WM8903";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "ROP",
+ "Int Spk", "RON",
+ "Int Spk", "LOP",
+ "Int Spk", "LON",
+ "IN1R", "Mic Jack",
+ "DMICDAT", "Int Mic";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ nvidia,headset;
+
+ clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+ <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
+ };
+
+ thermal-zones {
+ /*
+ * NCT72 has two sensors:
+ *
+ * 0: internal that monitors ambient/skin temperature
+ * 1: external that is connected to the CPU's diode
+ *
+ * Ideally we should use userspace thermal governor,
+ * but it's a much more complex solution. The "skin"
+ * zone exists as a simpler solution which prevents
+ * Chagall from getting too hot from a user's tactile
+ * perspective. The CPU zone is intended to protect
+ * silicon from damage.
+ */
+
+ skin-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&nct72 0>;
+
+ trips {
+ trip0: skin-alert {
+ /* throttle at 57C until temperature drops to 56.8C */
+ temperature = <57000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+
+ trip1: skin-crit {
+ /* shut down at 65C */
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&trip0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&actmon THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&nct72 1>;
+
+ trips {
+ trip2: cpu-alert {
+ /* throttle at 85C until temperature drops to 84.8C */
+ temperature = <85000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+
+ trip3: cpu-crit {
+ /* shut down at 90C */
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&trip2>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&actmon THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ memory-controller@7000f000 {
+ emc-timings-0 {
+ /* SAMSUNG K4P8G304EB FGC1 */
+ nvidia,ram-code = <0>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00020001 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x73e30303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010001 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x72c30303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000001 0xc0000018
+ 0x00000001 0x00000001 0x00000003 0x00000001
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060403 0x72430504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000025
+ 0x00000001 0x00000001 0x00000006 0x00000003
+ 0x00000005 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000003 0x00000002
+ 0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
+ };
+
+ timing-400000000 {
+ clock-frequency = <400000000>;
+
+ nvidia,emem-configuration = < 0x00000006 0xc0000048
+ 0x00000002 0x00000003 0x0000000c 0x00000007
+ 0x00000009 0x00000001 0x00000002 0x00000006
+ 0x00000001 0x00000000 0x00000004 0x00000004
+ 0x04040001 0x000d090c 0x7026120d 0x001f0000 >;
+ };
+ };
+
+ emc-timings-1 {
+ /* ELPIDA EDB8132B2MA 8D_F */
+ nvidia,ram-code = <1>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00020001 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x73e30303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010001 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x72c30303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000001 0xc0000018
+ 0x00000001 0x00000001 0x00000003 0x00000001
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060403 0x72430504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000025
+ 0x00000001 0x00000001 0x00000006 0x00000003
+ 0x00000005 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000003 0x00000002
+ 0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
+ };
+
+ timing-400000000 {
+ clock-frequency = <400000000>;
+
+ nvidia,emem-configuration = < 0x00000006 0xc0000048
+ 0x00000002 0x00000003 0x0000000c 0x00000007
+ 0x00000009 0x00000001 0x00000002 0x00000006
+ 0x00000001 0x00000000 0x00000004 0x00000004
+ 0x04040001 0x000d090c 0x7026120d 0x001f0000 >;
+ };
+ };
+
+ emc-timings-2 {
+ /* SAMSUNG K4P8G304EB FGC2 */
+ nvidia,ram-code = <2>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00020001 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x73e30303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010001 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x72c30303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000001 0xc0000018
+ 0x00000001 0x00000001 0x00000003 0x00000001
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060403 0x72430504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000025
+ 0x00000001 0x00000001 0x00000006 0x00000003
+ 0x00000005 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000003 0x00000002
+ 0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
+ };
+
+ timing-533000000 {
+ clock-frequency = <533000000>;
+
+ nvidia,emem-configuration = < 0x00000008 0xc0000060
+ 0x00000003 0x00000004 0x00000010 0x0000000a
+ 0x0000000d 0x00000002 0x00000002 0x00000008
+ 0x00000002 0x00000000 0x00000004 0x00000005
+ 0x05040002 0x00110b10 0x70281811 0x001f0000 >;
+ };
+ };
+
+ emc-timings-3 {
+ /* HYNIX H9TCNNN8JDMMPR NGM */
+ nvidia,ram-code = <3>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00020001 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x73e30303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010001 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x72c30303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000001 0xc0000018
+ 0x00000001 0x00000001 0x00000003 0x00000001
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060403 0x72430504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000025
+ 0x00000001 0x00000001 0x00000006 0x00000003
+ 0x00000005 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000003 0x00000002
+ 0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
+ };
+
+ timing-533000000 {
+ clock-frequency = <533000000>;
+
+ nvidia,emem-configuration = < 0x00000008 0xc0000060
+ 0x00000003 0x00000004 0x00000010 0x0000000a
+ 0x0000000d 0x00000002 0x00000002 0x00000008
+ 0x00000002 0x00000000 0x00000004 0x00000005
+ 0x05040002 0x00110b10 0x70281811 0x001f0000 >;
+ };
+ };
+ };
+
+ memory-controller@7000f400 {
+ emc-timings-0 {
+ /* SAMSUNG K4P8G304EB FGC1 */
+ nvidia,ram-code = <0>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000003 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x00000060 0x00000000 0x00000018
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000004 0x00000004
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x0000006b 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000000a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000003
+ 0x00000006 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x000000c0 0x00000000 0x00000030
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000008 0x00000008
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000000d5 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000013 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x0000000a>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000006
+ 0x0000000d 0x00000004 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x00000181 0x00000000 0x00000060
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x0000000f 0x0000000f
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000001a9 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000025 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010042>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000013>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000c
+ 0x0000001a 0x00000008 0x00000003 0x00000005
+ 0x00000004 0x00000001 0x00000006 0x00000003
+ 0x00000003 0x00000002 0x00000002 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000c
+ 0x0000000a 0x00000303 0x00000000 0x000000c0
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000007 0x0000001d 0x0000001d
+ 0x00000004 0x0000000b 0x00000005 0x00000004
+ 0x00000002 0x00000351 0x00000004 0x00000006
+ 0x00000000 0x00000000 0x00004282 0x004400a4
+ 0x00008000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000e0220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000004a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-400000000 {
+ clock-frequency = <400000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010082>;
+ nvidia,emc-mode-2 = <0x00020004>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000024>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000017
+ 0x00000033 0x00000010 0x00000007 0x00000007
+ 0x00000007 0x00000002 0x0000000a 0x00000007
+ 0x00000007 0x00000003 0x00000002 0x00000000
+ 0x00000003 0x00000007 0x00000004 0x0000000d
+ 0x0000000e 0x000005e9 0x00000000 0x0000017a
+ 0x00000002 0x00000002 0x00000007 0x00000000
+ 0x00000001 0x0000000c 0x00000038 0x00000038
+ 0x00000006 0x00000014 0x00000009 0x00000004
+ 0x00000002 0x00000680 0x00000000 0x00000006
+ 0x00000000 0x00000000 0x00006282 0x001d0084
+ 0x00008000 0x00034000 0x00034000 0x00034000
+ 0x00034000 0x00034000 0x00034000 0x00034000
+ 0x00034000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00038000 0x00038000 0x00038000
+ 0x00038000 0x00080220 0x0800003d 0x00000000
+ 0x77ffc004 0x01f1f408 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000090 0x000c000c 0xa0f10404 0x00000000
+ 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >;
+ };
+ };
+
+ emc-timings-1 {
+ /* ELPIDA EDB8132B2MA 8D_F */
+ nvidia,ram-code = <1>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000003 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x0000000a 0x00000060 0x00000000 0x00000018
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000004 0x00000004
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x0000006b 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000000a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000003
+ 0x00000006 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x0000000a 0x000000c0 0x00000000 0x00000030
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000008 0x00000008
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000000d5 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000013 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x0000000a>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000006
+ 0x0000000d 0x00000004 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x0000000a 0x00000181 0x00000000 0x00000060
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x0000000f 0x0000000f
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000001a9 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000025 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010042>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000013>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000c
+ 0x0000001a 0x00000008 0x00000003 0x00000005
+ 0x00000004 0x00000001 0x00000006 0x00000003
+ 0x00000003 0x00000002 0x00000002 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000c
+ 0x0000000a 0x00000303 0x00000000 0x000000c0
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000007 0x0000001d 0x0000001d
+ 0x00000004 0x0000000b 0x00000005 0x00000004
+ 0x00000002 0x00000351 0x00000004 0x00000006
+ 0x00000000 0x00000000 0x00004282 0x004400a4
+ 0x00008000 0x00070000 0x00070000 0x00070000
+ 0x00070000 0x00070000 0x00070000 0x00070000
+ 0x00070000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000e0220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000004a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-400000000 {
+ clock-frequency = <400000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010082>;
+ nvidia,emc-mode-2 = <0x00020004>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000024>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000017
+ 0x00000033 0x00000010 0x00000007 0x00000007
+ 0x00000007 0x00000002 0x0000000a 0x00000007
+ 0x00000007 0x00000003 0x00000002 0x00000000
+ 0x00000003 0x00000007 0x00000004 0x0000000d
+ 0x0000000e 0x000005e9 0x00000000 0x0000017a
+ 0x00000002 0x00000002 0x00000007 0x00000000
+ 0x00000001 0x0000000c 0x00000038 0x00000038
+ 0x00000006 0x00000014 0x00000009 0x00000004
+ 0x00000002 0x00000680 0x00000000 0x00000004
+ 0x00000000 0x00000000 0x00006282 0x001d0084
+ 0x00008000 0x00034000 0x00034000 0x00034000
+ 0x00034000 0x00034000 0x00034000 0x00034000
+ 0x00034000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00048000 0x00048000 0x00048000
+ 0x00048000 0x00060220 0x0800003d 0x00000000
+ 0x77ffc004 0x01f1f408 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000090 0x000c000c 0xa0f10000 0x00000000
+ 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >;
+ };
+ };
+
+ emc-timings-2 {
+ /* SAMSUNG K4P8G304EB FGC2 */
+ nvidia,ram-code = <2>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000003 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x0000000a 0x00000060 0x00000000 0x00000018
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000004 0x00000004
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x0000006b 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000000a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000003
+ 0x00000006 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x0000000a 0x000000c0 0x00000000 0x00000030
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000008 0x00000008
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000000d5 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000013 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x0000000a>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000006
+ 0x0000000d 0x00000004 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x00000181 0x00000000 0x00000060
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x0000000f 0x0000000f
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000001a9 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000025 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010042>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000013>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000c
+ 0x0000001a 0x00000008 0x00000003 0x00000005
+ 0x00000004 0x00000001 0x00000006 0x00000003
+ 0x00000003 0x00000002 0x00000002 0x00000000
+ 0x00000001 0x00000004 0x00000001 0x0000000c
+ 0x0000000a 0x00000303 0x00000000 0x000000c0
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000007 0x0000001d 0x0000001d
+ 0x00000004 0x0000000b 0x00000005 0x00000004
+ 0x00000002 0x00000351 0x00000005 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x004400a4
+ 0x00008000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000e0220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000004a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-533000000 {
+ clock-frequency = <533000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x000100c2>;
+ nvidia,emc-mode-2 = <0x00020006>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000030>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000001f
+ 0x00000045 0x00000016 0x00000009 0x00000008
+ 0x00000009 0x00000003 0x0000000d 0x00000009
+ 0x00000009 0x00000005 0x00000003 0x00000000
+ 0x00000004 0x0000000a 0x00000006 0x0000000d
+ 0x00000010 0x000007df 0x00000000 0x000001f7
+ 0x00000003 0x00000003 0x00000009 0x00000000
+ 0x00000001 0x0000000f 0x0000004b 0x0000004b
+ 0x00000008 0x0000001b 0x0000000c 0x00000004
+ 0x00000002 0x000008aa 0x00000000 0x00000004
+ 0x00000000 0x00000000 0x00006282 0xf0120091
+ 0x00008000 0x007f8008 0x007f8008 0x007f8008
+ 0x007f8008 0x007f8008 0x007f8008 0x007f8008
+ 0x007f8008 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x0000000c 0x0000000c 0x0000000c
+ 0x0000000c 0x00080220 0x0200003d 0x00000000
+ 0x77ffc004 0x01f1f408 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x000000c0 0x000e000e 0xa0f10000 0x00000000
+ 0x00000000 0x800010d9 0xf0000000 0xff00ff88 >;
+ };
+ };
+
+ emc-timings-3 {
+ /* HYNIX H9TCNNN8JDMMPR NGM */
+ nvidia,ram-code = <3>;
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000003 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x0000000a 0x00000060 0x00000000 0x00000018
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000004 0x00000004
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x0000006b 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000000a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000003
+ 0x00000006 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x0000000a 0x000000c0 0x00000000 0x00000030
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000008 0x00000008
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000000d5 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000013 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x0000000a>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000006
+ 0x0000000d 0x00000004 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x0000000a 0x00000181 0x00000000 0x00000060
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x0000000f 0x0000000f
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000001a9 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000025 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010042>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000013>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000c
+ 0x0000001a 0x00000008 0x00000003 0x00000005
+ 0x00000004 0x00000001 0x00000006 0x00000003
+ 0x00000003 0x00000002 0x00000002 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000c
+ 0x0000000b 0x00000303 0x00000000 0x000000c0
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000007 0x0000001d 0x0000001d
+ 0x00000004 0x0000000b 0x00000005 0x00000004
+ 0x00000002 0x00000351 0x00000004 0x00000006
+ 0x00000000 0x00000000 0x00004282 0x004400a4
+ 0x00008000 0x00072000 0x00072000 0x00072000
+ 0x00072000 0x00072000 0x00072000 0x00072000
+ 0x00072000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000e0220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000004a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xd0000000 0xff00ff00 >;
+ };
+
+ timing-533000000 {
+ clock-frequency = <533000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x000100c2>;
+ nvidia,emc-mode-2 = <0x00020006>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000030>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000001f
+ 0x00000045 0x00000016 0x00000009 0x00000008
+ 0x00000009 0x00000003 0x0000000d 0x00000009
+ 0x00000009 0x00000005 0x00000003 0x00000000
+ 0x00000004 0x00000009 0x00000006 0x0000000d
+ 0x00000010 0x000007df 0x00000000 0x000001f7
+ 0x00000003 0x00000003 0x00000009 0x00000000
+ 0x00000001 0x0000000f 0x0000004b 0x0000004b
+ 0x00000008 0x0000001b 0x0000000c 0x00000004
+ 0x00000002 0x000008aa 0x00000000 0x00000006
+ 0x00000000 0x00000000 0x00006282 0xf0120091
+ 0x00008000 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x0000000c 0x0000000c 0x0000000c
+ 0x0000000c 0x000a0220 0x0800003d 0x00000000
+ 0x77ffc004 0x01f1f408 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x000000c0 0x000e000e 0xa0f10000 0x00000000
+ 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >;
+ };
+ };
+ };
+};
+
+&emc_icc_dvfs_opp_table {
+ /delete-node/ opp-625000000-1200;
+ /delete-node/ opp-625000000-1250;
+ /delete-node/ opp-667000000-1200;
+ /delete-node/ opp-750000000-1300;
+ /delete-node/ opp-800000000-1300;
+ /delete-node/ opp-900000000-1350;
+};
+
+&emc_bw_dfs_opp_table {
+ /delete-node/ opp-625000000;
+ /delete-node/ opp-667000000;
+ /delete-node/ opp-750000000;
+ /delete-node/ opp-800000000;
+ /delete-node/ opp-900000000;
+};
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 14/28] ARM: tegra: Add device-tree for 1080p version of Nyan Big
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (12 preceding siblings ...)
2021-12-11 21:13 ` [PATCH v6 13/28] ARM: tegra: Add device-tree for Pegatron Chagall Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 15/28] ARM: tegra: Add usb-role-switch property to USB OTG ports Dmitry Osipenko
` (13 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
Add dedicated device-tree for 1080p version of Nyan Big in order to
describe display panel properly. FHD panel doesn't support modes other
than 1080p, hence it's wrong to use incompatible lower resolution panel
in device-tree.
Tested-by: Thomas Graichen <thomas.graichen@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/tegra124-nyan-big-fhd.dts | 11 +++++++++++
2 files changed, 12 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra124-nyan-big-fhd.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 26798673739c..561e0eae05a9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1341,6 +1341,7 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
tegra124-apalis-v1.2-eval.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
+ tegra124-nyan-big-fhd.dtb \
tegra124-nyan-blaze.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ARCH_U8500) += \
diff --git a/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts b/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts
new file mode 100644
index 000000000000..d35fb79d2f51
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra124-nyan-big.dts"
+
+/ {
+ /* Version of Nyan Big with 1080p panel */
+ panel {
+ compatible = "auo,b133htn01";
+ };
+};
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 15/28] ARM: tegra: Add usb-role-switch property to USB OTG ports
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (13 preceding siblings ...)
2021-12-11 21:13 ` [PATCH v6 14/28] ARM: tegra: Add device-tree for 1080p version of Nyan Big Dmitry Osipenko
@ 2021-12-11 21:13 ` Dmitry Osipenko
2021-12-15 13:14 ` Thierry Reding
2021-12-11 21:14 ` [PATCH v6 16/28] ARM: tegra: Enable HDMI CEC on Nyan Dmitry Osipenko
` (12 subsequent siblings)
27 siblings, 1 reply; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:13 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
If an USB port is an OTG port, then we should add the usb-role-switch
property. Otherwise XUSB setup fails and therefore padctl is unable to
set up the ports. This leads to broken USB and PCIe ports. Add the
usb-role-switch properties to Tegra124 device-trees to fix the problem.
The error message shown without this patch is e.g:
usb2-0: usb-role-switch not found for otg mode
[digetx@gmail.com: improved commit message]
Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 1 +
arch/arm/boot/dts/tegra124-apalis.dtsi | 1 +
arch/arm/boot/dts/tegra124-nyan.dtsi | 1 +
arch/arm/boot/dts/tegra124-venice2.dts | 2 +-
4 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
index cde9ae8fa04b..b9198f842a34 100644
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -1885,6 +1885,7 @@ ports {
usb2-0 {
status = "okay";
mode = "otg";
+ usb-role-switch;
vbus-supply = <®_usbo1_vbus>;
};
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index a46d9ba9bb7a..1a996fb78ee2 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -1877,6 +1877,7 @@ ports {
usb2-0 {
status = "okay";
mode = "otg";
+ usb-role-switch;
vbus-supply = <®_usbo1_vbus>;
};
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index 63a81270300a..93a40a84b792 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -466,6 +466,7 @@ usb2-0 {
vbus-supply = <&vdd_usb1_vbus>;
status = "okay";
mode = "otg";
+ usb-role-switch;
};
usb2-1 {
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index e6b54ac1ebd1..de8c18e6b7e6 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -972,7 +972,7 @@ ports {
usb2-0 {
status = "okay";
mode = "otg";
-
+ usb-role-switch;
vbus-supply = <&vdd_usb1_vbus>;
};
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 16/28] ARM: tegra: Enable HDMI CEC on Nyan
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (14 preceding siblings ...)
2021-12-11 21:13 ` [PATCH v6 15/28] ARM: tegra: Add usb-role-switch property to USB OTG ports Dmitry Osipenko
@ 2021-12-11 21:14 ` Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 17/28] ARM: tegra: Enable CPU DFLL " Dmitry Osipenko
` (11 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:14 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
Enable HDMI CEC on Nyan Chromebooks. It allows to control TV over HDMI.
Suggested-by: Thomas Graichen <thomas.graichen@gmail.com>
Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra124-nyan.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index 93a40a84b792..a5dff226831b 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -390,6 +390,10 @@ pmc@7000e400 {
nvidia,sys-clock-req-active-high;
};
+ cec@70015000 {
+ status = "okay";
+ };
+
hda@70030000 {
status = "okay";
};
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 17/28] ARM: tegra: Enable CPU DFLL on Nyan
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (15 preceding siblings ...)
2021-12-11 21:14 ` [PATCH v6 16/28] ARM: tegra: Enable HDMI CEC on Nyan Dmitry Osipenko
@ 2021-12-11 21:14 ` Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 18/28] ARM: tegra: Add CPU thermal zones to Nyan device-tree Dmitry Osipenko
` (10 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:14 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
Enable CPU DFLL node on Nyan Chromebooks. DFLL was previously disabled due
to Linux kernel CPUFreq driver which didn't support suspend-resume. That
problem was fixed years ago, but DFLL was never re-enabled.
Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index a5dff226831b..ec01a23d4d47 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -532,7 +532,7 @@ mmc@700b0600 { /* eMMC on this bus */
/* CPU DFLL clock */
clock@70110000 {
- status = "disabled";
+ status = "okay";
vdd-cpu-supply = <&vdd_cpu>;
nvidia,i2c-fs-rate = <400000>;
};
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 18/28] ARM: tegra: Add CPU thermal zones to Nyan device-tree
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (16 preceding siblings ...)
2021-12-11 21:14 ` [PATCH v6 17/28] ARM: tegra: Enable CPU DFLL " Dmitry Osipenko
@ 2021-12-11 21:14 ` Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 19/28] ARM: tegra: Rename top-level clocks Dmitry Osipenko
` (9 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:14 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
CPU of Nyan Chromebooks is overheating badly because apparently hardware
soctherm controller doesn't work well. Add CPU thermal zones to enable
software thermal control over CPU and fix the overheat trouble.
Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra124-nyan.dtsi | 49 +++++++++++++++++++++++++++-
1 file changed, 48 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index ec01a23d4d47..b16cce7476ef 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
+#include <dt-bindings/thermal/thermal.h>
#include "tegra124.dtsi"
/ {
@@ -87,7 +88,7 @@ acodec: audio-codec@10 {
interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
};
- temperature-sensor@4c {
+ tmp451: temperature-sensor@4c {
compatible = "ti,tmp451";
reg = <0x4c>;
interrupt-parent = <&gpio>;
@@ -789,6 +790,52 @@ gpio-restart {
gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
priority = <200>;
};
+
+ cpus {
+ cpu0: cpu@0 {
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@1 {
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@2 {
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@3 {
+ #cooling-cells = <2>;
+ };
+ };
+
+ thermal-zones {
+ cpu-skin-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tmp451 0>;
+
+ trips {
+ cpu_passive_trip: cpu-alert0 {
+ /* throttle at 70C until temperature drops to 69.8C */
+ temperature = <70000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_passive_trip>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
};
#include "cros-ec-keyboard.dtsi"
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 19/28] ARM: tegra: Rename top-level clocks
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (17 preceding siblings ...)
2021-12-11 21:14 ` [PATCH v6 18/28] ARM: tegra: Add CPU thermal zones to Nyan device-tree Dmitry Osipenko
@ 2021-12-11 21:14 ` Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 20/28] ARM: tegra: Rename top-level regulators Dmitry Osipenko
` (8 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:14 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: David Heidelberg <david@ixit.cz>
Clocks defined at the top level in device tree are no longer part of a
simple bus and therefore don't have a reg property. Nodes without a reg
property shouldn't have a unit-address either, so drop the unit address
from the node names. To ensure nodes aren't duplicated (in which case
they would end up merged in the final DTB), append the name of the clock
to the node name.
[treding@nvidia.com: factored out patch and wrote commit message]
Signed-off-by: David Heidelberg <david@ixit.cz>
Co-developed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra114-dalmore.dts | 2 +-
arch/arm/boot/dts/tegra114-roth.dts | 2 +-
arch/arm/boot/dts/tegra114-tn7.dts | 2 +-
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +-
arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +-
arch/arm/boot/dts/tegra124-venice2.dts | 2 +-
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++--
arch/arm/boot/dts/tegra20-harmony.dts | 2 +-
arch/arm/boot/dts/tegra20-paz00.dts | 2 +-
arch/arm/boot/dts/tegra20-seaboard.dts | 2 +-
arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +-
arch/arm/boot/dts/tegra20-trimslice.dts | 2 +-
arch/arm/boot/dts/tegra20-ventana.dts | 2 +-
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 2 +-
arch/arm/boot/dts/tegra30-beaver.dts | 2 +-
arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +-
16 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 7fd901f8d39a..4bf35d947d9b 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1151,7 +1151,7 @@ backlight: backlight {
default-brightness-level = <6>;
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts
index 07960171fabe..24ac84f81b19 100644
--- a/arch/arm/boot/dts/tegra114-roth.dts
+++ b/arch/arm/boot/dts/tegra114-roth.dts
@@ -1016,7 +1016,7 @@ backlight: backlight {
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts
index 745d234b105b..73c949d90345 100644
--- a/arch/arm/boot/dts/tegra114-tn7.dts
+++ b/arch/arm/boot/dts/tegra114-tn7.dts
@@ -273,7 +273,7 @@ backlight: backlight {
power-supply = <&lcd_bl_en>;
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 35ab296408e1..7339373c3e64 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1868,7 +1868,7 @@ usb-phy@7d008000 {
vbus-supply = <&vdd_usb3_vbus>;
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index b16cce7476ef..ccd3d81a3531 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -588,7 +588,7 @@ backlight: backlight {
256>;
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index de8c18e6b7e6..2fdcb8bf0bc5 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -1061,7 +1061,7 @@ backlight: backlight {
default-brightness-level = <6>;
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
index 23d3f8daab23..1aaee6f09fd8 100644
--- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
+++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
@@ -827,7 +827,7 @@ bat1010: battery-2s1p {
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k-in {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@@ -839,7 +839,7 @@ clk32k_in: clock@0 {
* oscillator is used as a reference clock-source by the
* Azurewave WiFi/BT module.
*/
- rtc_32k_wifi: clock@1 {
+ rtc_32k_wifi: clock-32k-wifi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index ae4312eedcbd..4d137461f3c4 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -640,7 +640,7 @@ backlight: backlight {
default-brightness-level = <6>;
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 5b38b0606f99..d3d24523553e 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -575,7 +575,7 @@ backlight: backlight {
default-brightness-level = <10>;
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 92d494b8c3d2..ffeae5da22e7 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -792,7 +792,7 @@ backlight: backlight {
default-brightness-level = <6>;
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index dd4d506683de..d5f1a46da0bc 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -502,7 +502,7 @@ mmc@c8000600 {
status = "okay";
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 4bc87bc0c2a4..7bda2d30a748 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -379,7 +379,7 @@ mmc@c8000600 {
bus-width = <4>;
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 5a2578b3707f..ef97457f1334 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -606,7 +606,7 @@ backlight: backlight {
default-brightness-level = <6>;
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
index 07d4ea130964..72159eb55a3d 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
@@ -1069,7 +1069,7 @@ battery_cell: battery-cell {
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index e159feeedef7..3184a9d6227e 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1966,7 +1966,7 @@ usb-phy@7d008000 {
status = "okay";
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 448f1397e64a..3a7621a2efde 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -433,7 +433,7 @@ backlight: backlight {
default-brightness-level = <6>;
};
- clk32k_in: clock@0 {
+ clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 20/28] ARM: tegra: Rename top-level regulators
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (18 preceding siblings ...)
2021-12-11 21:14 ` [PATCH v6 19/28] ARM: tegra: Rename top-level clocks Dmitry Osipenko
@ 2021-12-11 21:14 ` Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 21/28] ARM: tegra: nexus7: Drop clock-frequency from NFC node Dmitry Osipenko
` (7 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:14 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
Regulators defined at the top level in device tree are no longer part of
a simple bus and therefore don't have a reg property. Nodes without a
reg property shouldn't have a unit-address either, so drop the unit
address from the node names. To ensure nodes aren't duplicated (in which
case they would end up merged in the final DTB), append the name of the
regulator to the node name.
[treding@nvidia.com: factored out patch and wrote commit message]
Signed-off-by: David Heidelberg <david@ixit.cz>
Co-developed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra114-dalmore.dts | 14 +++++-----
arch/arm/boot/dts/tegra114-roth.dts | 12 ++++-----
arch/arm/boot/dts/tegra114-tn7.dts | 6 ++---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 24 ++++++++---------
arch/arm/boot/dts/tegra124-nyan.dtsi | 26 +++++++++----------
arch/arm/boot/dts/tegra124-venice2.dts | 26 +++++++++----------
.../boot/dts/tegra20-acer-a500-picasso.dts | 8 +++---
arch/arm/boot/dts/tegra20-harmony.dts | 14 +++++-----
arch/arm/boot/dts/tegra20-medcom-wide.dts | 8 +++---
arch/arm/boot/dts/tegra20-paz00.dts | 4 +--
arch/arm/boot/dts/tegra20-plutux.dts | 8 +++---
arch/arm/boot/dts/tegra20-seaboard.dts | 14 +++++-----
arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +-
arch/arm/boot/dts/tegra20-tec.dts | 8 +++---
arch/arm/boot/dts/tegra20-trimslice.dts | 10 +++----
arch/arm/boot/dts/tegra20-ventana.dts | 10 +++----
.../tegra30-asus-nexus7-grouper-common.dtsi | 8 +++---
...egra30-asus-nexus7-grouper-maxim-pmic.dtsi | 4 +--
.../tegra30-asus-nexus7-grouper-ti-pmic.dtsi | 2 +-
arch/arm/boot/dts/tegra30-beaver.dts | 18 ++++++-------
arch/arm/boot/dts/tegra30-cardhu-a02.dts | 12 ++++-----
arch/arm/boot/dts/tegra30-cardhu-a04.dts | 14 +++++-----
arch/arm/boot/dts/tegra30-cardhu.dtsi | 26 +++++++++----------
23 files changed, 139 insertions(+), 139 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 4bf35d947d9b..d23050bfaba6 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1186,7 +1186,7 @@ volume_up {
};
};
- vdd_ac_bat_reg: regulator@0 {
+ vdd_ac_bat_reg: regulator-acbat {
compatible = "regulator-fixed";
regulator-name = "vdd_ac_bat";
regulator-min-microvolt = <5000000>;
@@ -1194,7 +1194,7 @@ vdd_ac_bat_reg: regulator@0 {
regulator-always-on;
};
- dvdd_ts_reg: regulator@1 {
+ dvdd_ts_reg: regulator-ts {
compatible = "regulator-fixed";
regulator-name = "dvdd_ts";
regulator-min-microvolt = <1800000>;
@@ -1203,7 +1203,7 @@ dvdd_ts_reg: regulator@1 {
gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
};
- usb1_vbus_reg: regulator@3 {
+ usb1_vbus_reg: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
@@ -1214,7 +1214,7 @@ usb1_vbus_reg: regulator@3 {
vin-supply = <&tps65090_dcdc1_reg>;
};
- usb3_vbus_reg: regulator@4 {
+ usb3_vbus_reg: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "usb2_vbus";
regulator-min-microvolt = <5000000>;
@@ -1225,7 +1225,7 @@ usb3_vbus_reg: regulator@4 {
vin-supply = <&tps65090_dcdc1_reg>;
};
- vdd_hdmi_reg: regulator@5 {
+ vdd_hdmi_reg: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "vdd_hdmi_5v0";
regulator-min-microvolt = <5000000>;
@@ -1233,7 +1233,7 @@ vdd_hdmi_reg: regulator@5 {
vin-supply = <&tps65090_dcdc1_reg>;
};
- vdd_cam_1v8_reg: regulator@6 {
+ vdd_cam_1v8_reg: regulator-cam {
compatible = "regulator-fixed";
regulator-name = "vdd_cam_1v8_reg";
regulator-min-microvolt = <1800000>;
@@ -1242,7 +1242,7 @@ vdd_cam_1v8_reg: regulator@6 {
gpio = <&palmas_gpio 6 0>;
};
- vdd_5v0_hdmi: regulator@7 {
+ vdd_5v0_hdmi: regulator-hdmicon {
compatible = "regulator-fixed";
regulator-name = "VDD_5V0_HDMI_CON";
regulator-min-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts
index 24ac84f81b19..18521707ff5b 100644
--- a/arch/arm/boot/dts/tegra114-roth.dts
+++ b/arch/arm/boot/dts/tegra114-roth.dts
@@ -1045,7 +1045,7 @@ power {
};
};
- lcd_bl_en: regulator@0 {
+ lcd_bl_en: regulator-lcden {
compatible = "regulator-fixed";
regulator-name = "lcd_bl_en";
regulator-min-microvolt = <5000000>;
@@ -1053,7 +1053,7 @@ lcd_bl_en: regulator@0 {
regulator-boot-on;
};
- vdd_lcd: regulator@1 {
+ vdd_lcd: regulator-lcd {
compatible = "regulator-fixed";
regulator-name = "vdd_lcd_1v8";
regulator-min-microvolt = <1800000>;
@@ -1064,7 +1064,7 @@ vdd_lcd: regulator@1 {
regulator-boot-on;
};
- regulator@2 {
+ regulator-1v8ts {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8_ts";
regulator-min-microvolt = <1800000>;
@@ -1073,7 +1073,7 @@ regulator@2 {
regulator-boot-on;
};
- regulator@3 {
+ regulator-3v3ts {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3_ts";
regulator-min-microvolt = <3300000>;
@@ -1083,7 +1083,7 @@ regulator@3 {
regulator-boot-on;
};
- regulator@4 {
+ regulator-1v8com {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8_com";
regulator-min-microvolt = <1800000>;
@@ -1094,7 +1094,7 @@ regulator@4 {
regulator-boot-on;
};
- regulator@5 {
+ regulator-3v3com {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3_com";
regulator-min-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts
index 73c949d90345..0534247458f0 100644
--- a/arch/arm/boot/dts/tegra114-tn7.dts
+++ b/arch/arm/boot/dts/tegra114-tn7.dts
@@ -303,7 +303,7 @@ volume_up {
};
/* FIXME: output of BQ24192 */
- vs_sys: regulator@0 {
+ vs_sys: regulator-vs {
compatible = "regulator-fixed";
regulator-name = "VS_SYS";
regulator-min-microvolt = <4200000>;
@@ -312,7 +312,7 @@ vs_sys: regulator@0 {
regulator-boot-on;
};
- lcd_bl_en: regulator@1 {
+ lcd_bl_en: regulator-lcden {
compatible = "regulator-fixed";
regulator-name = "VDD_LCD_BL";
regulator-min-microvolt = <16500000>;
@@ -323,7 +323,7 @@ lcd_bl_en: regulator@1 {
regulator-boot-on;
};
- vdd_lcd: regulator@2 {
+ vdd_lcd: regulator-lcd {
compatible = "regulator-fixed";
regulator-name = "VD_LCD_1V8";
regulator-min-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 7339373c3e64..094f94a627b2 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1892,7 +1892,7 @@ power {
};
};
- vdd_mux: regulator@0 {
+ vdd_mux: regulator-mux {
compatible = "regulator-fixed";
regulator-name = "+VDD_MUX";
regulator-min-microvolt = <12000000>;
@@ -1901,7 +1901,7 @@ vdd_mux: regulator@0 {
regulator-boot-on;
};
- vdd_5v0_sys: regulator@1 {
+ vdd_5v0_sys: regulator-5v0sys {
compatible = "regulator-fixed";
regulator-name = "+5V_SYS";
regulator-min-microvolt = <5000000>;
@@ -1911,7 +1911,7 @@ vdd_5v0_sys: regulator@1 {
vin-supply = <&vdd_mux>;
};
- vdd_3v3_sys: regulator@2 {
+ vdd_3v3_sys: regulator-3v3sys {
compatible = "regulator-fixed";
regulator-name = "+3.3V_SYS";
regulator-min-microvolt = <3300000>;
@@ -1921,7 +1921,7 @@ vdd_3v3_sys: regulator@2 {
vin-supply = <&vdd_mux>;
};
- vdd_3v3_run: regulator@3 {
+ vdd_3v3_run: regulator-3v3run {
compatible = "regulator-fixed";
regulator-name = "+3.3V_RUN";
regulator-min-microvolt = <3300000>;
@@ -1933,7 +1933,7 @@ vdd_3v3_run: regulator@3 {
vin-supply = <&vdd_3v3_sys>;
};
- vdd_3v3_hdmi: regulator@4 {
+ vdd_3v3_hdmi: regulator-3v3hdmi {
compatible = "regulator-fixed";
regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
regulator-min-microvolt = <3300000>;
@@ -1941,7 +1941,7 @@ vdd_3v3_hdmi: regulator@4 {
vin-supply = <&vdd_3v3_run>;
};
- vdd_usb1_vbus: regulator@5 {
+ vdd_usb1_vbus: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "+USB0_VBUS_SW";
regulator-min-microvolt = <5000000>;
@@ -1952,7 +1952,7 @@ vdd_usb1_vbus: regulator@5 {
vin-supply = <&vdd_5v0_sys>;
};
- vdd_usb3_vbus: regulator@6 {
+ vdd_usb3_vbus: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "+5V_USB_HS";
regulator-min-microvolt = <5000000>;
@@ -1963,7 +1963,7 @@ vdd_usb3_vbus: regulator@6 {
vin-supply = <&vdd_5v0_sys>;
};
- vdd_3v3_lp0: regulator@7 {
+ vdd_3v3_lp0: regulator-lp0 {
compatible = "regulator-fixed";
regulator-name = "+3.3V_LP0";
regulator-min-microvolt = <3300000>;
@@ -1975,7 +1975,7 @@ vdd_3v3_lp0: regulator@7 {
vin-supply = <&vdd_3v3_sys>;
};
- vdd_hdmi_pll: regulator@8 {
+ vdd_hdmi_pll: regulator-hdmipll {
compatible = "regulator-fixed";
regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
regulator-min-microvolt = <1050000>;
@@ -1984,7 +1984,7 @@ vdd_hdmi_pll: regulator@8 {
vin-supply = <&vdd_1v05_run>;
};
- vdd_5v0_hdmi: regulator@9 {
+ vdd_5v0_hdmi: regulator-hdmicon {
compatible = "regulator-fixed";
regulator-name = "+5V_HDMI_CON";
regulator-min-microvolt = <5000000>;
@@ -1995,7 +1995,7 @@ vdd_5v0_hdmi: regulator@9 {
};
/* Molex power connector */
- vdd_5v0_sata: regulator@10 {
+ vdd_5v0_sata: regulator-5v0sata {
compatible = "regulator-fixed";
regulator-name = "+5V_SATA";
regulator-min-microvolt = <5000000>;
@@ -2005,7 +2005,7 @@ vdd_5v0_sata: regulator@10 {
vin-supply = <&vdd_5v0_sys>;
};
- vdd_12v0_sata: regulator@11 {
+ vdd_12v0_sata: regulator-12v0sata {
compatible = "regulator-fixed";
regulator-name = "+12V_SATA";
regulator-min-microvolt = <12000000>;
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index ccd3d81a3531..d62f57b392ec 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -621,7 +621,7 @@ power {
};
};
- vdd_mux: regulator@0 {
+ vdd_mux: regulator-mux {
compatible = "regulator-fixed";
regulator-name = "+VDD_MUX";
regulator-min-microvolt = <12000000>;
@@ -630,7 +630,7 @@ vdd_mux: regulator@0 {
regulator-boot-on;
};
- vdd_5v0_sys: regulator@1 {
+ vdd_5v0_sys: regulator-5v0sys {
compatible = "regulator-fixed";
regulator-name = "+5V_SYS";
regulator-min-microvolt = <5000000>;
@@ -640,7 +640,7 @@ vdd_5v0_sys: regulator@1 {
vin-supply = <&vdd_mux>;
};
- vdd_3v3_sys: regulator@2 {
+ vdd_3v3_sys: regulator-3v3sys {
compatible = "regulator-fixed";
regulator-name = "+3.3V_SYS";
regulator-min-microvolt = <3300000>;
@@ -650,7 +650,7 @@ vdd_3v3_sys: regulator@2 {
vin-supply = <&vdd_mux>;
};
- vdd_3v3_run: regulator@3 {
+ vdd_3v3_run: regulator-3v3run {
compatible = "regulator-fixed";
regulator-name = "+3.3V_RUN";
regulator-min-microvolt = <3300000>;
@@ -662,7 +662,7 @@ vdd_3v3_run: regulator@3 {
vin-supply = <&vdd_3v3_sys>;
};
- vdd_3v3_hdmi: regulator@4 {
+ vdd_3v3_hdmi: regulator-3v3hdmi {
compatible = "regulator-fixed";
regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
regulator-min-microvolt = <3300000>;
@@ -670,7 +670,7 @@ vdd_3v3_hdmi: regulator@4 {
vin-supply = <&vdd_3v3_run>;
};
- vdd_led: regulator@5 {
+ vdd_led: regulator-led {
compatible = "regulator-fixed";
regulator-name = "+VDD_LED";
gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
@@ -678,7 +678,7 @@ vdd_led: regulator@5 {
vin-supply = <&vdd_mux>;
};
- vdd_5v0_ts: regulator@6 {
+ vdd_5v0_ts: regulator-ts {
compatible = "regulator-fixed";
regulator-name = "+5V_VDD_TS_SW";
regulator-min-microvolt = <5000000>;
@@ -689,7 +689,7 @@ vdd_5v0_ts: regulator@6 {
vin-supply = <&vdd_5v0_sys>;
};
- vdd_usb1_vbus: regulator@7 {
+ vdd_usb1_vbus: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "+5V_USB_HS";
regulator-min-microvolt = <5000000>;
@@ -700,7 +700,7 @@ vdd_usb1_vbus: regulator@7 {
vin-supply = <&vdd_5v0_sys>;
};
- vdd_usb3_vbus: regulator@8 {
+ vdd_usb3_vbus: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "+5V_USB_SS";
regulator-min-microvolt = <5000000>;
@@ -711,7 +711,7 @@ vdd_usb3_vbus: regulator@8 {
vin-supply = <&vdd_5v0_sys>;
};
- vdd_3v3_panel: regulator@9 {
+ vdd_3v3_panel: regulator-panel {
compatible = "regulator-fixed";
regulator-name = "+3.3V_PANEL";
regulator-min-microvolt = <3300000>;
@@ -721,7 +721,7 @@ vdd_3v3_panel: regulator@9 {
vin-supply = <&vdd_3v3_run>;
};
- vdd_3v3_lp0: regulator@10 {
+ vdd_3v3_lp0: regulator-lp0 {
compatible = "regulator-fixed";
regulator-name = "+3.3V_LP0";
regulator-min-microvolt = <3300000>;
@@ -736,7 +736,7 @@ vdd_3v3_lp0: regulator@10 {
vin-supply = <&vdd_3v3_sys>;
};
- vdd_hdmi_pll: regulator@11 {
+ vdd_hdmi_pll: regulator-hdmipll {
compatible = "regulator-fixed";
regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
regulator-min-microvolt = <1050000>;
@@ -745,7 +745,7 @@ vdd_hdmi_pll: regulator@11 {
vin-supply = <&vdd_1v05_run>;
};
- vdd_5v0_hdmi: regulator@12 {
+ vdd_5v0_hdmi: regulator-hdmicon {
compatible = "regulator-fixed";
regulator-name = "+5V_HDMI_CON";
regulator-min-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 2fdcb8bf0bc5..2f2932be01c6 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -1086,7 +1086,7 @@ panel: panel {
ddc-i2c-bus = <&dpaux>;
};
- vdd_mux: regulator@0 {
+ vdd_mux: regulator-mux {
compatible = "regulator-fixed";
regulator-name = "+VDD_MUX";
regulator-min-microvolt = <12000000>;
@@ -1095,7 +1095,7 @@ vdd_mux: regulator@0 {
regulator-boot-on;
};
- vdd_5v0_sys: regulator@1 {
+ vdd_5v0_sys: regulator-5v0sys {
compatible = "regulator-fixed";
regulator-name = "+5V_SYS";
regulator-min-microvolt = <5000000>;
@@ -1105,7 +1105,7 @@ vdd_5v0_sys: regulator@1 {
vin-supply = <&vdd_mux>;
};
- vdd_3v3_sys: regulator@2 {
+ vdd_3v3_sys: regulator-3v3sys {
compatible = "regulator-fixed";
regulator-name = "+3.3V_SYS";
regulator-min-microvolt = <3300000>;
@@ -1115,7 +1115,7 @@ vdd_3v3_sys: regulator@2 {
vin-supply = <&vdd_mux>;
};
- vdd_3v3_run: regulator@3 {
+ vdd_3v3_run: regulator-3v3run {
compatible = "regulator-fixed";
regulator-name = "+3.3V_RUN";
regulator-min-microvolt = <3300000>;
@@ -1127,7 +1127,7 @@ vdd_3v3_run: regulator@3 {
vin-supply = <&vdd_3v3_sys>;
};
- vdd_3v3_hdmi: regulator@4 {
+ vdd_3v3_hdmi: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
regulator-min-microvolt = <3300000>;
@@ -1135,7 +1135,7 @@ vdd_3v3_hdmi: regulator@4 {
vin-supply = <&vdd_3v3_run>;
};
- vdd_led: regulator@5 {
+ vdd_led: regulator-led {
compatible = "regulator-fixed";
regulator-name = "+VDD_LED";
regulator-min-microvolt = <3300000>;
@@ -1145,7 +1145,7 @@ vdd_led: regulator@5 {
vin-supply = <&vdd_mux>;
};
- vdd_5v0_ts: regulator@6 {
+ vdd_5v0_ts: regulator-ts {
compatible = "regulator-fixed";
regulator-name = "+5V_VDD_TS_SW";
regulator-min-microvolt = <5000000>;
@@ -1156,7 +1156,7 @@ vdd_5v0_ts: regulator@6 {
vin-supply = <&vdd_5v0_sys>;
};
- vdd_usb1_vbus: regulator@7 {
+ vdd_usb1_vbus: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "+5V_USB_HS";
regulator-min-microvolt = <5000000>;
@@ -1167,7 +1167,7 @@ vdd_usb1_vbus: regulator@7 {
vin-supply = <&vdd_5v0_sys>;
};
- vdd_usb3_vbus: regulator@8 {
+ vdd_usb3_vbus: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "+5V_USB_SS";
regulator-min-microvolt = <5000000>;
@@ -1178,7 +1178,7 @@ vdd_usb3_vbus: regulator@8 {
vin-supply = <&vdd_5v0_sys>;
};
- vdd_3v3_panel: regulator@9 {
+ vdd_3v3_panel: regulator-panel {
compatible = "regulator-fixed";
regulator-name = "+3.3V_PANEL";
regulator-min-microvolt = <3300000>;
@@ -1188,7 +1188,7 @@ vdd_3v3_panel: regulator@9 {
vin-supply = <&vdd_3v3_run>;
};
- vdd_3v3_lp0: regulator@10 {
+ vdd_3v3_lp0: regulator-lp0 {
compatible = "regulator-fixed";
regulator-name = "+3.3V_LP0";
regulator-min-microvolt = <3300000>;
@@ -1203,7 +1203,7 @@ vdd_3v3_lp0: regulator@10 {
vin-supply = <&vdd_3v3_sys>;
};
- vdd_hdmi_pll: regulator@11 {
+ vdd_hdmi_pll: regulator-hdmipll {
compatible = "regulator-fixed";
regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
regulator-min-microvolt = <1050000>;
@@ -1212,7 +1212,7 @@ vdd_hdmi_pll: regulator@11 {
vin-supply = <&vdd_1v05_run>;
};
- vdd_5v0_hdmi: regulator@12 {
+ vdd_5v0_hdmi: regulator-hdmicon {
compatible = "regulator-fixed";
regulator-name = "+5V_HDMI_CON";
regulator-min-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
index 1aaee6f09fd8..2e6340e92fe1 100644
--- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
+++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
@@ -964,7 +964,7 @@ lvds_encoder_output: endpoint {
};
};
- vdd_5v0_sys: regulator@0 {
+ vdd_5v0_sys: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
@@ -972,7 +972,7 @@ vdd_5v0_sys: regulator@0 {
regulator-always-on;
};
- vdd_3v3_sys: regulator@1 {
+ vdd_3v3_sys: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3_vs";
regulator-min-microvolt = <3300000>;
@@ -981,7 +981,7 @@ vdd_3v3_sys: regulator@1 {
vin-supply = <&vdd_5v0_sys>;
};
- vdd_1v8_sys: regulator@2 {
+ vdd_1v8_sys: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8_vs";
regulator-min-microvolt = <1800000>;
@@ -990,7 +990,7 @@ vdd_1v8_sys: regulator@2 {
vin-supply = <&vdd_5v0_sys>;
};
- vdd_pnl: regulator@3 {
+ vdd_pnl: regulator-panel {
compatible = "regulator-fixed";
regulator-name = "vdd_panel";
regulator-min-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 4d137461f3c4..a8494378c382 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -666,7 +666,7 @@ panel: panel {
backlight = <&backlight>;
};
- vdd_5v0_reg: regulator@0 {
+ vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
@@ -674,7 +674,7 @@ vdd_5v0_reg: regulator@0 {
regulator-always-on;
};
- regulator@1 {
+ regulator-1v5 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v5";
regulator-min-microvolt = <1500000>;
@@ -682,7 +682,7 @@ regulator@1 {
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
- regulator@2 {
+ regulator-1v2 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v2";
regulator-min-microvolt = <1200000>;
@@ -691,7 +691,7 @@ regulator@2 {
enable-active-high;
};
- pci_vdd_reg: regulator@3 {
+ pci_vdd_reg: regulator-1v05 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v05";
regulator-min-microvolt = <1050000>;
@@ -700,7 +700,7 @@ pci_vdd_reg: regulator@3 {
enable-active-high;
};
- vdd_pnl_reg: regulator@4 {
+ vdd_pnl_reg: regulator-pn1 {
compatible = "regulator-fixed";
regulator-name = "vdd_pnl";
regulator-min-microvolt = <2800000>;
@@ -709,7 +709,7 @@ vdd_pnl_reg: regulator@4 {
enable-active-high;
};
- vdd_bl_reg: regulator@5 {
+ vdd_bl_reg: regulator-bl {
compatible = "regulator-fixed";
regulator-name = "vdd_bl";
regulator-min-microvolt = <2800000>;
@@ -718,7 +718,7 @@ vdd_bl_reg: regulator@5 {
enable-active-high;
};
- vdd_5v0_hdmi: regulator@6 {
+ vdd_5v0_hdmi: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "VDDIO_HDMI";
regulator-min-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index b31c9bca16e6..cb6199d7d224 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -92,7 +92,7 @@ sound {
clock-names = "pll_a", "pll_a_out0", "mclk";
};
- vcc_24v_reg: regulator@100 {
+ vcc_24v_reg: regulator-24v0 {
compatible = "regulator-fixed";
regulator-name = "vcc_24v";
regulator-min-microvolt = <24000000>;
@@ -100,7 +100,7 @@ vcc_24v_reg: regulator@100 {
regulator-always-on;
};
- vdd_5v0_reg: regulator@101 {
+ vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
vin-supply = <&vcc_24v_reg>;
@@ -109,7 +109,7 @@ vdd_5v0_reg: regulator@101 {
regulator-always-on;
};
- vdd_3v3_reg: regulator@102 {
+ vdd_3v3_reg: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
vin-supply = <&vcc_24v_reg>;
@@ -118,7 +118,7 @@ vdd_3v3_reg: regulator@102 {
regulator-always-on;
};
- vdd_1v8_reg: regulator@103 {
+ vdd_1v8_reg: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8";
vin-supply = <&vdd_3v3_reg>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index d3d24523553e..46d81d703548 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -612,7 +612,7 @@ panel: panel {
backlight = <&backlight>;
};
- p5valw_reg: regulator@0 {
+ p5valw_reg: regulator-5v0alw {
compatible = "regulator-fixed";
regulator-name = "+5valw";
regulator-min-microvolt = <5000000>;
@@ -620,7 +620,7 @@ p5valw_reg: regulator@0 {
regulator-always-on;
};
- vdd_pnl_reg: regulator@1 {
+ vdd_pnl_reg: regulator-3v0 {
compatible = "regulator-fixed";
regulator-name = "+3VS,vdd_pnl";
regulator-min-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 5811b7006a9b..71a8236491df 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -60,7 +60,7 @@ sound {
clock-names = "pll_a", "pll_a_out0", "mclk";
};
- vcc_24v_reg: regulator@100 {
+ vcc_24v_reg: regulator-24v0 {
compatible = "regulator-fixed";
regulator-name = "vcc_24v";
regulator-min-microvolt = <24000000>;
@@ -68,7 +68,7 @@ vcc_24v_reg: regulator@100 {
regulator-always-on;
};
- vdd_5v0_reg: regulator@101 {
+ vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
vin-supply = <&vcc_24v_reg>;
@@ -77,7 +77,7 @@ vdd_5v0_reg: regulator@101 {
regulator-always-on;
};
- vdd_3v3_reg: regulator@102 {
+ vdd_3v3_reg: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
vin-supply = <&vcc_24v_reg>;
@@ -86,7 +86,7 @@ vdd_3v3_reg: regulator@102 {
regulator-always-on;
};
- vdd_1v8_reg: regulator@103 {
+ vdd_1v8_reg: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8";
vin-supply = <&vdd_3v3_reg>;
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index ffeae5da22e7..ca7adeb1fdd9 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -828,7 +828,7 @@ panel: panel {
ddc-i2c-bus = <&lvds_ddc>;
};
- vdd_5v0_reg: regulator@0 {
+ vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
@@ -836,7 +836,7 @@ vdd_5v0_reg: regulator@0 {
regulator-always-on;
};
- regulator@1 {
+ regulator-1v5 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v5";
regulator-min-microvolt = <1500000>;
@@ -844,7 +844,7 @@ regulator@1 {
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
- regulator@2 {
+ regulator-1v2 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v2";
regulator-min-microvolt = <1200000>;
@@ -853,7 +853,7 @@ regulator@2 {
enable-active-high;
};
- vbus_reg: regulator@3 {
+ vbus_reg: regulator-vbus {
compatible = "regulator-fixed";
regulator-name = "vdd_vbus_wup1";
regulator-min-microvolt = <5000000>;
@@ -864,7 +864,7 @@ vbus_reg: regulator@3 {
regulator-boot-on;
};
- vdd_pnl_reg: regulator@4 {
+ vdd_pnl_reg: regulator-pnl {
compatible = "regulator-fixed";
regulator-name = "vdd_pnl";
regulator-min-microvolt = <2800000>;
@@ -873,7 +873,7 @@ vdd_pnl_reg: regulator@4 {
enable-active-high;
};
- vdd_bl_reg: regulator@5 {
+ vdd_bl_reg: regulator-bl {
compatible = "regulator-fixed";
regulator-name = "vdd_bl";
regulator-min-microvolt = <2800000>;
@@ -882,7 +882,7 @@ vdd_bl_reg: regulator@5 {
enable-active-high;
};
- vdd_hdmi: regulator@6 {
+ vdd_hdmi: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "VDDIO_HDMI";
regulator-min-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index d5f1a46da0bc..2ad56f84bb62 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -508,7 +508,7 @@ clk32k_in: clock-32k {
#clock-cells = <0>;
};
- pci_vdd_reg: regulator@1 {
+ pci_vdd_reg: regulator-1v05 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v05";
regulator-min-microvolt = <1050000>;
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 10ff09d86efa..4f41c74384b2 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -69,7 +69,7 @@ sound {
clock-names = "pll_a", "pll_a_out0", "mclk";
};
- vcc_24v_reg: regulator@100 {
+ vcc_24v_reg: regulator-24v {
compatible = "regulator-fixed";
regulator-name = "vcc_24v";
regulator-min-microvolt = <24000000>;
@@ -77,7 +77,7 @@ vcc_24v_reg: regulator@100 {
regulator-always-on;
};
- vdd_5v0_reg: regulator@101 {
+ vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
vin-supply = <&vcc_24v_reg>;
@@ -86,7 +86,7 @@ vdd_5v0_reg: regulator@101 {
regulator-always-on;
};
- vdd_3v3_reg: regulator@102 {
+ vdd_3v3_reg: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
vin-supply = <&vcc_24v_reg>;
@@ -95,7 +95,7 @@ vdd_3v3_reg: regulator@102 {
regulator-always-on;
};
- vdd_1v8_reg: regulator@103 {
+ vdd_1v8_reg: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v8";
vin-supply = <&vdd_3v3_reg>;
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 7bda2d30a748..1f4893699614 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -401,7 +401,7 @@ poweroff {
gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
};
- hdmi_vdd_reg: regulator@0 {
+ hdmi_vdd_reg: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "avdd_hdmi";
regulator-min-microvolt = <3300000>;
@@ -409,7 +409,7 @@ hdmi_vdd_reg: regulator@0 {
regulator-always-on;
};
- hdmi_pll_reg: regulator@1 {
+ hdmi_pll_reg: regulator-hdmipll {
compatible = "regulator-fixed";
regulator-name = "avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
@@ -417,7 +417,7 @@ hdmi_pll_reg: regulator@1 {
regulator-always-on;
};
- vbus_reg: regulator@2 {
+ vbus_reg: regulator-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
@@ -428,7 +428,7 @@ vbus_reg: regulator@2 {
regulator-boot-on;
};
- pci_clk_reg: regulator@3 {
+ pci_clk_reg: regulator-pciclk {
compatible = "regulator-fixed";
regulator-name = "pci_clk";
regulator-min-microvolt = <3300000>;
@@ -436,7 +436,7 @@ pci_clk_reg: regulator@3 {
regulator-always-on;
};
- pci_vdd_reg: regulator@4 {
+ pci_vdd_reg: regulator-pcivdd {
compatible = "regulator-fixed";
regulator-name = "pci_vdd";
regulator-min-microvolt = <1050000>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index ef97457f1334..4284054ebd2c 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -647,7 +647,7 @@ panel: panel {
ddc-i2c-bus = <&lvds_ddc>;
};
- vdd_5v0_reg: regulator@0 {
+ vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
@@ -655,7 +655,7 @@ vdd_5v0_reg: regulator@0 {
regulator-always-on;
};
- regulator@1 {
+ regulator-1v5 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v5";
regulator-min-microvolt = <1500000>;
@@ -663,7 +663,7 @@ regulator@1 {
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
- regulator@2 {
+ regulator-1v2 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v2";
regulator-min-microvolt = <1200000>;
@@ -672,7 +672,7 @@ regulator@2 {
enable-active-high;
};
- vdd_pnl_reg: regulator@3 {
+ vdd_pnl_reg: regulator-pnl {
compatible = "regulator-fixed";
regulator-name = "vdd_pnl";
regulator-min-microvolt = <2800000>;
@@ -681,7 +681,7 @@ vdd_pnl_reg: regulator@3 {
enable-active-high;
};
- vdd_bl_reg: regulator@4 {
+ vdd_bl_reg: regulator-bl {
compatible = "regulator-fixed";
regulator-name = "vdd_bl";
regulator-min-microvolt = <2800000>;
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
index 72159eb55a3d..e6aed19a5f3b 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
@@ -1207,7 +1207,7 @@ lvds_encoder_output: endpoint {
};
};
- vdd_5v0_sys: regulator@0 {
+ vdd_5v0_sys: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
@@ -1216,7 +1216,7 @@ vdd_5v0_sys: regulator@0 {
regulator-boot-on;
};
- vdd_3v3_sys: regulator@1 {
+ vdd_3v3_sys: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
regulator-min-microvolt = <3300000>;
@@ -1226,7 +1226,7 @@ vdd_3v3_sys: regulator@1 {
vin-supply = <&vdd_5v0_sys>;
};
- vdd_pnl: regulator@2 {
+ vdd_pnl: regulator-panel {
compatible = "regulator-fixed";
regulator-name = "vdd_panel";
regulator-min-microvolt = <3300000>;
@@ -1237,7 +1237,7 @@ vdd_pnl: regulator@2 {
vin-supply = <&vdd_3v3_sys>;
};
- vcc_3v3_ts: regulator@3 {
+ vcc_3v3_ts: regulator-ts {
compatible = "regulator-fixed";
regulator-name = "ldo_s-1167_3v3";
regulator-min-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
index 53966fa4eef2..cd28e8782f7d 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
@@ -166,12 +166,12 @@ ldo8 {
};
};
- vdd_3v3_sys: regulator@1 {
+ vdd_3v3_sys: regulator-3v3 {
gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
- regulator@4 {
+ regulator-usb {
compatible = "regulator-fixed";
regulator-name = "avdd_usb";
regulator-min-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi
index 9365ae607239..ee4a3f482769 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi
@@ -143,7 +143,7 @@ vdd_core: core-regulator@60 {
};
};
- vdd_3v3_sys: regulator@1 {
+ vdd_3v3_sys: regulator-3v3 {
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 3184a9d6227e..2ec5e47d9623 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1985,7 +1985,7 @@ gpled2 {
};
};
- vdd_5v_in_reg: regulator@0 {
+ vdd_5v_in_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v_in";
regulator-min-microvolt = <5000000>;
@@ -1993,7 +1993,7 @@ vdd_5v_in_reg: regulator@0 {
regulator-always-on;
};
- chargepump_5v_reg: regulator@1 {
+ chargepump_5v_reg: regulator-chargepump {
compatible = "regulator-fixed";
regulator-name = "chargepump_5v";
regulator-min-microvolt = <5000000>;
@@ -2004,7 +2004,7 @@ chargepump_5v_reg: regulator@1 {
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
- ddr_reg: regulator@2 {
+ ddr_reg: regulator-ddr {
compatible = "regulator-fixed";
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1500000>;
@@ -2016,7 +2016,7 @@ ddr_reg: regulator@2 {
vin-supply = <&vdd_5v_in_reg>;
};
- vdd_5v_sata_reg: regulator@3 {
+ vdd_5v_sata_reg: regulator-sata {
compatible = "regulator-fixed";
regulator-name = "vdd_5v_sata";
regulator-min-microvolt = <5000000>;
@@ -2028,7 +2028,7 @@ vdd_5v_sata_reg: regulator@3 {
vin-supply = <&vdd_5v_in_reg>;
};
- usb1_vbus_reg: regulator@4 {
+ usb1_vbus_reg: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
@@ -2039,7 +2039,7 @@ usb1_vbus_reg: regulator@4 {
vin-supply = <&vdd_5v_in_reg>;
};
- usb3_vbus_reg: regulator@5 {
+ usb3_vbus_reg: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "usb3_vbus";
regulator-min-microvolt = <5000000>;
@@ -2050,7 +2050,7 @@ usb3_vbus_reg: regulator@5 {
vin-supply = <&vdd_5v_in_reg>;
};
- sys_3v3_reg: regulator@6 {
+ sys_3v3_reg: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "sys_3v3,vdd_3v3_alw";
regulator-min-microvolt = <3300000>;
@@ -2062,7 +2062,7 @@ sys_3v3_reg: regulator@6 {
vin-supply = <&vdd_5v_in_reg>;
};
- sys_3v3_pexs_reg: regulator@7 {
+ sys_3v3_pexs_reg: regulator-pexs {
compatible = "regulator-fixed";
regulator-name = "sys_3v3_pexs";
regulator-min-microvolt = <3300000>;
@@ -2074,7 +2074,7 @@ sys_3v3_pexs_reg: regulator@7 {
vin-supply = <&sys_3v3_reg>;
};
- vdd_5v0_hdmi: regulator@8 {
+ vdd_5v0_hdmi: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "+VDD_5V_HDMI";
regulator-min-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index 4899e05a0d9c..247185314f46 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -16,7 +16,7 @@ mmc@78000400 {
keep-power-in-suspend;
};
- ddr_reg: regulator@100 {
+ ddr_reg: regulator-ddr {
compatible = "regulator-fixed";
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1500000>;
@@ -27,7 +27,7 @@ ddr_reg: regulator@100 {
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
};
- sys_3v3_reg: regulator@101 {
+ sys_3v3_reg: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "sys_3v3";
regulator-min-microvolt = <3300000>;
@@ -38,7 +38,7 @@ sys_3v3_reg: regulator@101 {
gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
};
- usb1_vbus_reg: regulator@102 {
+ usb1_vbus_reg: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
@@ -49,7 +49,7 @@ usb1_vbus_reg: regulator@102 {
vin-supply = <&vdd_5v0_reg>;
};
- usb3_vbus_reg: regulator@103 {
+ usb3_vbus_reg: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "usb3_vbus";
regulator-min-microvolt = <5000000>;
@@ -60,7 +60,7 @@ usb3_vbus_reg: regulator@103 {
vin-supply = <&vdd_5v0_reg>;
};
- vdd_5v0_reg: regulator@104 {
+ vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5v0";
regulator-min-microvolt = <5000000>;
@@ -69,7 +69,7 @@ vdd_5v0_reg: regulator@104 {
gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
};
- vdd_bl_reg: regulator@105 {
+ vdd_bl_reg: regulator-bl {
compatible = "regulator-fixed";
regulator-name = "vdd_bl";
regulator-min-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index a11028b8b67b..2911f08863a0 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -16,7 +16,7 @@ mmc@78000400 {
keep-power-in-suspend;
};
- ddr_reg: regulator@100 {
+ ddr_reg: regulator-ddr {
compatible = "regulator-fixed";
regulator-name = "ddr";
regulator-min-microvolt = <1500000>;
@@ -27,7 +27,7 @@ ddr_reg: regulator@100 {
gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
};
- sys_3v3_reg: regulator@101 {
+ sys_3v3_reg: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "sys_3v3";
regulator-min-microvolt = <3300000>;
@@ -38,7 +38,7 @@ sys_3v3_reg: regulator@101 {
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
};
- usb1_vbus_reg: regulator@102 {
+ usb1_vbus_reg: regulator-usb1 {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
@@ -49,7 +49,7 @@ usb1_vbus_reg: regulator@102 {
vin-supply = <&vdd_5v0_reg>;
};
- usb3_vbus_reg: regulator@103 {
+ usb3_vbus_reg: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "usb3_vbus";
regulator-min-microvolt = <5000000>;
@@ -60,7 +60,7 @@ usb3_vbus_reg: regulator@103 {
vin-supply = <&vdd_5v0_reg>;
};
- vdd_5v0_reg: regulator@104 {
+ vdd_5v0_reg: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5v0";
regulator-min-microvolt = <5000000>;
@@ -69,7 +69,7 @@ vdd_5v0_reg: regulator@104 {
gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
};
- vdd_bl_reg: regulator@105 {
+ vdd_bl_reg: regulator-bl {
compatible = "regulator-fixed";
regulator-name = "vdd_bl";
regulator-min-microvolt = <5000000>;
@@ -80,7 +80,7 @@ vdd_bl_reg: regulator@105 {
gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
};
- vdd_bl2_reg: regulator@106 {
+ vdd_bl2_reg: regulator-bl2 {
compatible = "regulator-fixed";
regulator-name = "vdd_bl2";
regulator-min-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 3a7621a2efde..d2f6121049a4 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -475,7 +475,7 @@ panel: panel {
backlight = <&backlight>;
};
- vdd_ac_bat_reg: regulator@0 {
+ vdd_ac_bat_reg: regulator-acbat {
compatible = "regulator-fixed";
regulator-name = "vdd_ac_bat";
regulator-min-microvolt = <5000000>;
@@ -483,7 +483,7 @@ vdd_ac_bat_reg: regulator@0 {
regulator-always-on;
};
- cam_1v8_reg: regulator@1 {
+ cam_1v8_reg: regulator-cam {
compatible = "regulator-fixed";
regulator-name = "cam_1v8";
regulator-min-microvolt = <1800000>;
@@ -493,7 +493,7 @@ cam_1v8_reg: regulator@1 {
vin-supply = <&vio_reg>;
};
- cp_5v_reg: regulator@2 {
+ cp_5v_reg: regulator-5v0cp {
compatible = "regulator-fixed";
regulator-name = "cp_5v";
regulator-min-microvolt = <5000000>;
@@ -504,7 +504,7 @@ cp_5v_reg: regulator@2 {
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
- emmc_3v3_reg: regulator@3 {
+ emmc_3v3_reg: regulator-emmc {
compatible = "regulator-fixed";
regulator-name = "emmc_3v3";
regulator-min-microvolt = <3300000>;
@@ -516,7 +516,7 @@ emmc_3v3_reg: regulator@3 {
vin-supply = <&sys_3v3_reg>;
};
- modem_3v3_reg: regulator@4 {
+ modem_3v3_reg: regulator-modem {
compatible = "regulator-fixed";
regulator-name = "modem_3v3";
regulator-min-microvolt = <3300000>;
@@ -525,7 +525,7 @@ modem_3v3_reg: regulator@4 {
gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
};
- pex_hvdd_3v3_reg: regulator@5 {
+ pex_hvdd_3v3_reg: regulator-pex {
compatible = "regulator-fixed";
regulator-name = "pex_hvdd_3v3";
regulator-min-microvolt = <3300000>;
@@ -535,7 +535,7 @@ pex_hvdd_3v3_reg: regulator@5 {
vin-supply = <&sys_3v3_reg>;
};
- vdd_cam1_ldo_reg: regulator@6 {
+ vdd_cam1_ldo_reg: regulator-cam1 {
compatible = "regulator-fixed";
regulator-name = "vdd_cam1_ldo";
regulator-min-microvolt = <2800000>;
@@ -545,7 +545,7 @@ vdd_cam1_ldo_reg: regulator@6 {
vin-supply = <&sys_3v3_reg>;
};
- vdd_cam2_ldo_reg: regulator@7 {
+ vdd_cam2_ldo_reg: regulator-cam2 {
compatible = "regulator-fixed";
regulator-name = "vdd_cam2_ldo";
regulator-min-microvolt = <2800000>;
@@ -555,7 +555,7 @@ vdd_cam2_ldo_reg: regulator@7 {
vin-supply = <&sys_3v3_reg>;
};
- vdd_cam3_ldo_reg: regulator@8 {
+ vdd_cam3_ldo_reg: regulator-cam3 {
compatible = "regulator-fixed";
regulator-name = "vdd_cam3_ldo";
regulator-min-microvolt = <3300000>;
@@ -565,7 +565,7 @@ vdd_cam3_ldo_reg: regulator@8 {
vin-supply = <&sys_3v3_reg>;
};
- vdd_com_reg: regulator@9 {
+ vdd_com_reg: regulator-com {
compatible = "regulator-fixed";
regulator-name = "vdd_com";
regulator-min-microvolt = <3300000>;
@@ -577,7 +577,7 @@ vdd_com_reg: regulator@9 {
vin-supply = <&sys_3v3_reg>;
};
- vdd_fuse_3v3_reg: regulator@10 {
+ vdd_fuse_3v3_reg: regulator-fuse {
compatible = "regulator-fixed";
regulator-name = "vdd_fuse_3v3";
regulator-min-microvolt = <3300000>;
@@ -587,7 +587,7 @@ vdd_fuse_3v3_reg: regulator@10 {
vin-supply = <&sys_3v3_reg>;
};
- vdd_pnl1_reg: regulator@11 {
+ vdd_pnl1_reg: regulator-pnl1 {
compatible = "regulator-fixed";
regulator-name = "vdd_pnl1";
regulator-min-microvolt = <3300000>;
@@ -599,7 +599,7 @@ vdd_pnl1_reg: regulator@11 {
vin-supply = <&sys_3v3_reg>;
};
- vdd_vid_reg: regulator@12 {
+ vdd_vid_reg: regulator-vid {
compatible = "regulator-fixed";
regulator-name = "vddio_vid";
regulator-min-microvolt = <5000000>;
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 21/28] ARM: tegra: nexus7: Drop clock-frequency from NFC node
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (19 preceding siblings ...)
2021-12-11 21:14 ` [PATCH v6 20/28] ARM: tegra: Rename top-level regulators Dmitry Osipenko
@ 2021-12-11 21:14 ` Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 22/28] ARM: tegra: nexus7: Use common LVDS display device-tree Dmitry Osipenko
` (6 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:14 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: David Heidelberg <david@ixit.cz>
The clock-frequency property was never used and is deprecated now.
Remove it from Nexus 7 device-tree.
Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi | 1 -
arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi | 2 --
2 files changed, 3 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi
index a044dbd200a9..564cfcde21a9 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi
@@ -137,7 +137,6 @@ i2c@7000c500 {
nfc@28 {
compatible = "nxp,pn544-i2c";
reg = <0x28>;
- clock-frequency = <100000>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_EDGE_RISING>;
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi
index a681ad51fddd..cd63e0ef7445 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi
@@ -223,8 +223,6 @@ nfc@2a {
compatible = "nxp,pn544-i2c";
reg = <0x2a>;
- clock-frequency = <100000>;
-
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 22/28] ARM: tegra: nexus7: Use common LVDS display device-tree
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (20 preceding siblings ...)
2021-12-11 21:14 ` [PATCH v6 21/28] ARM: tegra: nexus7: Drop clock-frequency from NFC node Dmitry Osipenko
@ 2021-12-11 21:14 ` Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 23/28] ARM: tegra: Add #reset-cells for Tegra114 MC Dmitry Osipenko
` (5 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:14 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Maxim Schwalm <maxim.schwalm@gmail.com>
Make Nexus 7 device-tree to use common LVDS bridge description. This makes
device-trees more consistent.
[digetx@gmail.com: factored Nexus7 change into separate patch and wrote commit message]
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
.../tegra30-asus-nexus7-grouper-common.dtsi | 54 ++-----------------
1 file changed, 3 insertions(+), 51 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
index e6aed19a5f3b..861ac96bd806 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
@@ -8,6 +8,7 @@
#include "tegra30.dtsi"
#include "tegra30-cpu-opp.dtsi"
#include "tegra30-cpu-opp-microvolt.dtsi"
+#include "tegra30-asus-lvds-display.dtsi"
/ {
aliases {
@@ -59,21 +60,6 @@ trustzone@bfe00000 {
};
};
- host1x@50000000 {
- dc@54200000 {
- rgb {
- status = "okay";
-
- port@0 {
- lcd_output: endpoint {
- remote-endpoint = <&lvds_encoder_input>;
- bus-width = <24>;
- };
- };
- };
- };
- };
-
gpio@6000d000 {
init-mode-hog {
gpio-hog;
@@ -1114,20 +1100,14 @@ display-panel {
*/
compatible = "panel-lvds";
- power-supply = <&vdd_pnl>;
- backlight = <&backlight>;
-
width-mm = <94>;
height-mm = <150>;
rotation = <180>;
data-mapping = "jeida-24";
- port {
- panel_input: endpoint {
- remote-endpoint = <&lvds_encoder_output>;
- };
- };
+ /* DDC unconnected on Nexus 7 */
+ /delete-property/ ddc-i2c-bus;
};
firmware {
@@ -1179,34 +1159,6 @@ volume-down {
};
};
- lvds-encoder {
- compatible = "ti,sn75lvds83", "lvds-encoder";
-
- powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
- power-supply = <&vdd_3v3_sys>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- lvds_encoder_input: endpoint {
- remote-endpoint = <&lcd_output>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- lvds_encoder_output: endpoint {
- remote-endpoint = <&panel_input>;
- };
- };
- };
- };
-
vdd_5v0_sys: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 23/28] ARM: tegra: Add #reset-cells for Tegra114 MC
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (21 preceding siblings ...)
2021-12-11 21:14 ` [PATCH v6 22/28] ARM: tegra: nexus7: Use common LVDS display device-tree Dmitry Osipenko
@ 2021-12-11 21:14 ` Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 24/28] ARM: tegra: Enable video decoder on Tegra114 Dmitry Osipenko
` (4 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:14 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Thierry Reding <treding@nvidia.com>
The Tegra memory controller provides reset controls for hotflush reset,
so the #reset-cells property must be specified.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra114.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 563ee262f41d..d487bc180f09 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -543,6 +543,7 @@ mc: memory-controller@70019000 {
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
+ #reset-cells = <1>;
};
ahub@70080000 {
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 24/28] ARM: tegra: Enable video decoder on Tegra114
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (22 preceding siblings ...)
2021-12-11 21:14 ` [PATCH v6 23/28] ARM: tegra: Add #reset-cells for Tegra114 MC Dmitry Osipenko
@ 2021-12-11 21:14 ` Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 25/28] ARM: tegra: Remove stray #reset-cells property Dmitry Osipenko
` (3 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:14 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Anton Bambura <jenneron@protonmail.com>
Add Video Decoder Engine node to Tegra114 device-tree.
Signed-off-by: Anton Bambura <jenneron@protonmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra114.dtsi | 37 +++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index d487bc180f09..3d08764401ce 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -17,6 +17,19 @@ memory@80000000 {
reg = <0x80000000 0x0>;
};
+ sram@40000000 {
+ compatible = "mmio-sram";
+ reg = <0x40000000 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x40000000 0x40000>;
+
+ vde_pool: sram@400 {
+ reg = <0x400 0x3fc00>;
+ pool;
+ };
+ };
+
host1x@50000000 {
compatible = "nvidia,tegra114-host1x";
reg = <0x50000000 0x00028000>;
@@ -253,6 +266,30 @@ gpio: gpio@6000d000 {
*/
};
+ vde@6001a000 {
+ compatible = "nvidia,tegra114-vde";
+ reg = <0x6001a000 0x1000>, /* Syntax Engine */
+ <0x6001b000 0x1000>, /* Video Bitstream Engine */
+ <0x6001c000 0x100>, /* Macroblock Engine */
+ <0x6001c200 0x100>, /* Post-processing Engine */
+ <0x6001c400 0x100>, /* Motion Compensation Engine */
+ <0x6001c600 0x100>, /* Transform Engine */
+ <0x6001c800 0x100>, /* Pixel prediction block */
+ <0x6001ca00 0x100>, /* Video DMA */
+ <0x6001d800 0x400>; /* Video frame controls */
+ reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
+ "tfe", "ppb", "vdma", "frameid";
+ iram = <&vde_pool>; /* IRAM region */
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
+ interrupt-names = "sync-token", "bsev", "sxe";
+ clocks = <&tegra_car TEGRA114_CLK_VDE>;
+ reset-names = "vde", "mc";
+ resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>;
+ iommus = <&mc TEGRA_SWGROUP_VDE>;
+ };
+
apbmisc@70000800 {
compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
reg = <0x70000800 0x64>, /* Chip revision */
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 25/28] ARM: tegra: Remove stray #reset-cells property
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (23 preceding siblings ...)
2021-12-11 21:14 ` [PATCH v6 24/28] ARM: tegra: Enable video decoder on Tegra114 Dmitry Osipenko
@ 2021-12-11 21:14 ` Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 26/28] ARM: tegra: Re-add gpio-ranges properties Dmitry Osipenko
` (2 subsequent siblings)
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:14 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Thierry Reding <treding@nvidia.com>
The Ouya board specifies the #reset-cells property for the GPIO
controller. Since the GPIO controller doesn't provide reset controls
this is not needed, so they can be dropped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra30-ouya.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts
index 4259871b76c9..fd64aadc472a 100644
--- a/arch/arm/boot/dts/tegra30-ouya.dts
+++ b/arch/arm/boot/dts/tegra30-ouya.dts
@@ -70,7 +70,6 @@ hdmi@54280000 {
gpio: gpio@6000d000 {
gpio-ranges = <&pinmux 0 0 248>;
- #reset-cells = <1>;
};
pinmux@70000868 {
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 26/28] ARM: tegra: Re-add gpio-ranges properties
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (24 preceding siblings ...)
2021-12-11 21:14 ` [PATCH v6 25/28] ARM: tegra: Remove stray #reset-cells property Dmitry Osipenko
@ 2021-12-11 21:14 ` Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 27/28] ARM: tegra_defconfig: Enable drivers wanted by Acer Chromebooks and ASUS tablets Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 28/28] ARM: config: multi v7: Enable display drivers used by Tegra devices Dmitry Osipenko
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:14 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
From: Stefan Agner <stefan@agner.ch>
The properties have been commented out to prevent a regression a
while ago. The first regression should be resolved by
commit 44af7927316e ("spi: Map SPI OF client IRQ at probe time").
The second regression is probably addressed by
commit 494fd7b7ad10 ("PM / core: fix deferred probe breaking suspend resume order")
and/or maybe others. Re-add the gpio-ranges properties to see whether
regressions still get reported.
This reverts commit 4f1d841475e1f6e9e32496dda11215db56f4ea73
("ARM: tegra: Comment out gpio-ranges properties").
[digetx@gmail.com: removed gpio-ranges from tegra30-ouya.dtsi]
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra114.dtsi | 2 --
arch/arm/boot/dts/tegra124.dtsi | 2 --
arch/arm/boot/dts/tegra20.dtsi | 2 --
arch/arm/boot/dts/tegra30-ouya.dts | 4 ----
arch/arm/boot/dts/tegra30.dtsi | 2 --
5 files changed, 12 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 3d08764401ce..ea5ba6e19a32 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -261,9 +261,7 @@ gpio: gpio@6000d000 {
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
- /*
gpio-ranges = <&pinmux 0 0 246>;
- */
};
vde@6001a000 {
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 63a64171b422..fbc9bc6e5bd7 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -313,9 +313,7 @@ gpio: gpio@6000d000 {
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
- /*
gpio-ranges = <&pinmux 0 0 251>;
- */
};
apbdma: dma@60020000 {
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 9508248fd166..f9ad0780587f 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -293,9 +293,7 @@ gpio: gpio@6000d000 {
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
- /*
gpio-ranges = <&pinmux 0 0 224>;
- */
};
vde@6001a000 {
diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts
index fd64aadc472a..e40043546a0b 100644
--- a/arch/arm/boot/dts/tegra30-ouya.dts
+++ b/arch/arm/boot/dts/tegra30-ouya.dts
@@ -68,10 +68,6 @@ hdmi@54280000 {
};
};
- gpio: gpio@6000d000 {
- gpio-ranges = <&pinmux 0 0 248>;
- };
-
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index a6772171c910..b7a48758d930 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -441,9 +441,7 @@ gpio: gpio@6000d000 {
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
- /*
gpio-ranges = <&pinmux 0 0 248>;
- */
};
vde@6001a000 {
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 27/28] ARM: tegra_defconfig: Enable drivers wanted by Acer Chromebooks and ASUS tablets
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (25 preceding siblings ...)
2021-12-11 21:14 ` [PATCH v6 26/28] ARM: tegra: Re-add gpio-ranges properties Dmitry Osipenko
@ 2021-12-11 21:14 ` Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 28/28] ARM: config: multi v7: Enable display drivers used by Tegra devices Dmitry Osipenko
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:14 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
Enable charger, touchpad and EC drivers found on Acer Tegra124 (Nyan)
Chromebooks, display bridge found on ASUS TF700T and audio codecs
found on ASUS tablets.
Suggested-by: Thomas Graichen <thomas.graichen@gmail.com> # Nyan options
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/configs/tegra_defconfig | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 8a8f12b3e6dd..a8093b222551 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -104,6 +104,8 @@ CONFIG_USB_USBNET=y
CONFIG_USB_NET_SMSC75XX=y
CONFIG_USB_NET_SMSC95XX=y
CONFIG_BRCMFMAC=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
CONFIG_RT2X00=y
CONFIG_RT2800USB=m
CONFIG_INPUT_JOYDEV=y
@@ -112,6 +114,8 @@ CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_TEGRA=y
CONFIG_KEYBOARD_CROS_EC=y
CONFIG_KEYBOARD_CAP11XX=y
+CONFIG_MOUSE_ELAN_I2C=m
+CONFIG_MOUSE_ELAN_I2C_SMBUS=y
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
@@ -131,6 +135,7 @@ CONFIG_SERIAL_DEV_BUS=y
# CONFIG_HW_RANDOM is not set
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_TEGRA=y
@@ -151,7 +156,9 @@ CONFIG_GPIO_TPS65910=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_AS3722=y
CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_BATTERY_SBS=y
+CONFIG_CHARGER_BQ24735=y
CONFIG_BATTERY_BQ27XXX=y
CONFIG_CHARGER_GPIO=y
CONFIG_CHARGER_SMB347=y
@@ -200,7 +207,9 @@ CONFIG_DRM_TEGRA_STAGING=y
CONFIG_DRM_PANEL_LVDS=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_EDP=y
+CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=y
CONFIG_DRM_LVDS_CODEC=y
+CONFIG_DRM_TOSHIBA_TC358768=y
CONFIG_FB=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
@@ -279,6 +288,9 @@ CONFIG_STAGING_MEDIA=y
CONFIG_TEGRA_VDE=y
CONFIG_CHROME_PLATFORMS=y
CONFIG_CROS_EC=y
+CONFIG_CROS_EC_I2C=m
+CONFIG_CROS_EC_SPI=m
+CONFIG_I2C_CROS_EC_TUNNEL=m
CONFIG_TEGRA_IOMMU_GART=y
CONFIG_TEGRA_IOMMU_SMMU=y
CONFIG_ARCH_TEGRA_2x_SOC=y
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v6 28/28] ARM: config: multi v7: Enable display drivers used by Tegra devices
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
` (26 preceding siblings ...)
2021-12-11 21:14 ` [PATCH v6 27/28] ARM: tegra_defconfig: Enable drivers wanted by Acer Chromebooks and ASUS tablets Dmitry Osipenko
@ 2021-12-11 21:14 ` Dmitry Osipenko
27 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-11 21:14 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, David Heidelberg,
Svyatoslav Ryhel, Anton Bambura, Antoni Aloy Torrens,
Nikola Milosavljevic, Ion Agorria, Michał Mirosław,
Ihor Didenko, Andreas Westman Dorcsak, Maxim Schwalm,
Raffaele Tranquillini, Jasper Korten, Thomas Graichen,
Stefan Eichenberger, Stefan Agner, Peter Geis
Cc: devicetree, linux-tegra, linux-kernel
Enable display-related drivers used by various Tegra-based tablets.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/configs/multi_v7_defconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index c951aeed2138..3d509bc13444 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -382,6 +382,7 @@ CONFIG_TCG_TPM=m
CONFIG_TCG_TIS_I2C_INFINEON=m
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=m
+CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_DEMUX_PINCTRL=y
@@ -680,19 +681,23 @@ CONFIG_DRM_FSL_DCU=m
CONFIG_DRM_TEGRA=y
CONFIG_DRM_STM=m
CONFIG_DRM_STM_DSI=m
+CONFIG_DRM_PANEL_LVDS=m
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_EDP=y
CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
+CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
+CONFIG_DRM_LVDS_CODEC=m
CONFIG_DRM_NXP_PTN3460=m
CONFIG_DRM_PARADE_PS8622=m
CONFIG_DRM_SII902X=m
CONFIG_DRM_SII9234=m
CONFIG_DRM_SIMPLE_BRIDGE=m
CONFIG_DRM_TOSHIBA_TC358764=m
+CONFIG_DRM_TOSHIBA_TC358768=m
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_I2C_ADV7511_AUDIO=y
CONFIG_DRM_STI=m
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [PATCH v6 15/28] ARM: tegra: Add usb-role-switch property to USB OTG ports
2021-12-11 21:13 ` [PATCH v6 15/28] ARM: tegra: Add usb-role-switch property to USB OTG ports Dmitry Osipenko
@ 2021-12-15 13:14 ` Thierry Reding
2021-12-15 15:04 ` Dmitry Osipenko
0 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-12-15 13:14 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Jonathan Hunter, David Heidelberg, Svyatoslav Ryhel,
Anton Bambura, Antoni Aloy Torrens, Nikola Milosavljevic,
Ion Agorria, Michał Mirosław, Ihor Didenko,
Andreas Westman Dorcsak, Maxim Schwalm, Raffaele Tranquillini,
Jasper Korten, Thomas Graichen, Stefan Eichenberger,
Stefan Agner, Peter Geis, devicetree, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1393 bytes --]
On Sun, Dec 12, 2021 at 12:13:59AM +0300, Dmitry Osipenko wrote:
> From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
>
> If an USB port is an OTG port, then we should add the usb-role-switch
> property. Otherwise XUSB setup fails and therefore padctl is unable to
> set up the ports. This leads to broken USB and PCIe ports. Add the
> usb-role-switch properties to Tegra124 device-trees to fix the problem.
>
> The error message shown without this patch is e.g:
> usb2-0: usb-role-switch not found for otg mode
>
> [digetx@gmail.com: improved commit message]
> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
> Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
> arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 1 +
> arch/arm/boot/dts/tegra124-apalis.dtsi | 1 +
> arch/arm/boot/dts/tegra124-nyan.dtsi | 1 +
> arch/arm/boot/dts/tegra124-venice2.dts | 2 +-
> 4 files changed, 4 insertions(+), 1 deletion(-)
The device tree bindings for the XUSB pad controller say that when this
property is set, then the "connector" subnode should also exist.
Any chance we can add that? I was planning on making that a dependency
in the json-schema conversion of the binding, in which case it would be
more of a "must" than a "should".
Thierry
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 08/28] ARM: tegra: Add device-tree for ASUS Transformer Prime TF201
2021-12-11 21:13 ` [PATCH v6 08/28] ARM: tegra: Add device-tree for ASUS Transformer Prime TF201 Dmitry Osipenko
@ 2021-12-15 13:28 ` Thierry Reding
2021-12-15 14:19 ` Dmitry Osipenko
0 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-12-15 13:28 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Jonathan Hunter, David Heidelberg, Svyatoslav Ryhel,
Anton Bambura, Antoni Aloy Torrens, Nikola Milosavljevic,
Ion Agorria, Michał Mirosław, Ihor Didenko,
Andreas Westman Dorcsak, Maxim Schwalm, Raffaele Tranquillini,
Jasper Korten, Thomas Graichen, Stefan Eichenberger,
Stefan Agner, Peter Geis, devicetree, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 284 bytes --]
On Sun, Dec 12, 2021 at 12:13:52AM +0300, Dmitry Osipenko wrote:
[...]
> + display-panel {
> + compatible = "hannstar,hsd101pww2";
There doesn't seem to be a DT binding for this and I can't find any
patches where this would be added. Is there a patch somewhere to do
this?
Thierry
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 11/28] ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T
2021-12-11 21:13 ` [PATCH v6 11/28] ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T Dmitry Osipenko
@ 2021-12-15 14:01 ` Thierry Reding
2021-12-15 14:52 ` Dmitry Osipenko
0 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-12-15 14:01 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Jonathan Hunter, David Heidelberg, Svyatoslav Ryhel,
Anton Bambura, Antoni Aloy Torrens, Nikola Milosavljevic,
Ion Agorria, Michał Mirosław, Ihor Didenko,
Andreas Westman Dorcsak, Maxim Schwalm, Raffaele Tranquillini,
Jasper Korten, Thomas Graichen, Stefan Eichenberger,
Stefan Agner, Peter Geis, devicetree, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1856 bytes --]
On Sun, Dec 12, 2021 at 12:13:55AM +0300, Dmitry Osipenko wrote:
[...]
> + i2c@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dsi-bridge@7 {
> + compatible = "toshiba,tc358768";
> + reg = <0x7>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + clocks = <&tc358768_osc>;
> + clock-names = "refclk";
> +
> + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
> +
> + vddc-supply = <&vdd_1v2_mipi>;
> + vddio-supply = <&vdd_1v8_vio>;
> + vddmipi-supply = <&vdd_1v2_mipi>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + bridge_input: endpoint {
> + remote-endpoint = <&dpi_output>;
> + data-lines = <24>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + bridge_output: endpoint {
> + remote-endpoint = <&panel_input>;
> + };
> + };
> + };
> +
> + /*
> + * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
> + * LCD SuperIPS+ Full HD panel.
> + */
> + panel@1 {
> + compatible = "panasonic,vvx10f004b00";
> + reg = <1>;
> +
> + power-supply = <&vdd_pnl>;
> + backlight = <&backlight>;
> +
> + port {
> + panel_input: endpoint {
> + remote-endpoint = <&bridge_output>;
> + };
> + };
> + };
make dtbs_check complains about this and says that panel@1 (as well as
#address-cells and #size-cells) are not allowed here. And indeed the
binding for the Toshiba bridge doesn't mention them here.
Do we need this here or should this be moved to the top level to fix
those warnings? I guess what you're doing above is describe a DSI bus
created by the DSI bridge, which also makes sense, so another
alternative would be to fix up the binding and let it accept those
properties.
Thierry
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 08/28] ARM: tegra: Add device-tree for ASUS Transformer Prime TF201
2021-12-15 13:28 ` Thierry Reding
@ 2021-12-15 14:19 ` Dmitry Osipenko
2021-12-15 15:09 ` Thierry Reding
0 siblings, 1 reply; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-15 14:19 UTC (permalink / raw)
To: Thierry Reding
Cc: Jonathan Hunter, David Heidelberg, Svyatoslav Ryhel,
Anton Bambura, Antoni Aloy Torrens, Nikola Milosavljevic,
Ion Agorria, Michał Mirosław, Ihor Didenko,
Andreas Westman Dorcsak, Maxim Schwalm, Raffaele Tranquillini,
Jasper Korten, Thomas Graichen, Stefan Eichenberger,
Stefan Agner, Peter Geis, devicetree, linux-tegra, linux-kernel
15.12.2021 16:28, Thierry Reding пишет:
> On Sun, Dec 12, 2021 at 12:13:52AM +0300, Dmitry Osipenko wrote:
> [...]
>> + display-panel {
>> + compatible = "hannstar,hsd101pww2";
>
> There doesn't seem to be a DT binding for this and I can't find any
> patches where this would be added. Is there a patch somewhere to do
> this?
Are you trolling me? :/ Please search the "Tegra kernel patches for
5.17" email in your inbox, it must be there. Please read and answer to it.
All patches are in the Tegra patchwork. Who marked them "Not Applicable"?
https://patchwork.ozlabs.org/project/linux-tegra/patch/20211211213653.17700-3-digetx@gmail.com/
https://patchwork.ozlabs.org/project/linux-tegra/list/?series=276358
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 11/28] ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T
2021-12-15 14:01 ` Thierry Reding
@ 2021-12-15 14:52 ` Dmitry Osipenko
2021-12-15 15:19 ` Thierry Reding
0 siblings, 1 reply; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-15 14:52 UTC (permalink / raw)
To: Thierry Reding
Cc: Jonathan Hunter, David Heidelberg, Svyatoslav Ryhel,
Anton Bambura, Antoni Aloy Torrens, Nikola Milosavljevic,
Ion Agorria, Michał Mirosław, Ihor Didenko,
Andreas Westman Dorcsak, Maxim Schwalm, Raffaele Tranquillini,
Jasper Korten, Thomas Graichen, Stefan Eichenberger,
Stefan Agner, Peter Geis, devicetree, linux-tegra, linux-kernel
15.12.2021 17:01, Thierry Reding пишет:
> On Sun, Dec 12, 2021 at 12:13:55AM +0300, Dmitry Osipenko wrote:
> [...]
>> + i2c@1 {
>> + reg = <1>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + dsi-bridge@7 {
>> + compatible = "toshiba,tc358768";
>> + reg = <0x7>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + clocks = <&tc358768_osc>;
>> + clock-names = "refclk";
>> +
>> + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
>> +
>> + vddc-supply = <&vdd_1v2_mipi>;
>> + vddio-supply = <&vdd_1v8_vio>;
>> + vddmipi-supply = <&vdd_1v2_mipi>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> +
>> + bridge_input: endpoint {
>> + remote-endpoint = <&dpi_output>;
>> + data-lines = <24>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> +
>> + bridge_output: endpoint {
>> + remote-endpoint = <&panel_input>;
>> + };
>> + };
>> + };
>> +
>> + /*
>> + * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
>> + * LCD SuperIPS+ Full HD panel.
>> + */
>> + panel@1 {
>> + compatible = "panasonic,vvx10f004b00";
>> + reg = <1>;
>> +
>> + power-supply = <&vdd_pnl>;
>> + backlight = <&backlight>;
>> +
>> + port {
>> + panel_input: endpoint {
>> + remote-endpoint = <&bridge_output>;
>> + };
>> + };
>> + };
>
> make dtbs_check complains about this and says that panel@1 (as well as
> #address-cells and #size-cells) are not allowed here. And indeed the
> binding for the Toshiba bridge doesn't mention them here.
>
> Do we need this here or should this be moved to the top level to fix
> those warnings? I guess what you're doing above is describe a DSI bus
> created by the DSI bridge, which also makes sense, so another
> alternative would be to fix up the binding and let it accept those
> properties.
Toshiba bridge binding is incomplete. David has patch for that [1], I
don't think that it was sent out yet.
[1]
https://github.com/okias/linux/commit/0875230062294b6db17f395ced0a8384a4c1cfc7
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 15/28] ARM: tegra: Add usb-role-switch property to USB OTG ports
2021-12-15 13:14 ` Thierry Reding
@ 2021-12-15 15:04 ` Dmitry Osipenko
2021-12-15 15:16 ` Thierry Reding
0 siblings, 1 reply; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-15 15:04 UTC (permalink / raw)
To: Thierry Reding
Cc: Jonathan Hunter, David Heidelberg, Svyatoslav Ryhel,
Anton Bambura, Antoni Aloy Torrens, Nikola Milosavljevic,
Ion Agorria, Michał Mirosław, Ihor Didenko,
Andreas Westman Dorcsak, Maxim Schwalm, Raffaele Tranquillini,
Jasper Korten, Thomas Graichen, Stefan Eichenberger,
Stefan Agner, Peter Geis, devicetree, linux-tegra, linux-kernel
15.12.2021 16:14, Thierry Reding пишет:
> On Sun, Dec 12, 2021 at 12:13:59AM +0300, Dmitry Osipenko wrote:
>> From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
>>
>> If an USB port is an OTG port, then we should add the usb-role-switch
>> property. Otherwise XUSB setup fails and therefore padctl is unable to
>> set up the ports. This leads to broken USB and PCIe ports. Add the
>> usb-role-switch properties to Tegra124 device-trees to fix the problem.
>>
>> The error message shown without this patch is e.g:
>> usb2-0: usb-role-switch not found for otg mode
>>
>> [digetx@gmail.com: improved commit message]
>> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
>> Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>> ---
>> arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 1 +
>> arch/arm/boot/dts/tegra124-apalis.dtsi | 1 +
>> arch/arm/boot/dts/tegra124-nyan.dtsi | 1 +
>> arch/arm/boot/dts/tegra124-venice2.dts | 2 +-
>> 4 files changed, 4 insertions(+), 1 deletion(-)
>
> The device tree bindings for the XUSB pad controller say that when this
> property is set, then the "connector" subnode should also exist.
>
> Any chance we can add that? I was planning on making that a dependency
> in the json-schema conversion of the binding, in which case it would be
> more of a "must" than a "should".
I guess it will be harmless if you'll add the connector subnodes. Will
you be able to create a separate patch that will add the subnodes on top
of this patch?
Thomas Graichen says that one USB port on Nyan Big doesn't work without
this patch. This is why this patch is needed essentially.
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 08/28] ARM: tegra: Add device-tree for ASUS Transformer Prime TF201
2021-12-15 14:19 ` Dmitry Osipenko
@ 2021-12-15 15:09 ` Thierry Reding
0 siblings, 0 replies; 42+ messages in thread
From: Thierry Reding @ 2021-12-15 15:09 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Jonathan Hunter, David Heidelberg, Svyatoslav Ryhel,
Anton Bambura, Antoni Aloy Torrens, Nikola Milosavljevic,
Ion Agorria, Michał Mirosław, Ihor Didenko,
Andreas Westman Dorcsak, Maxim Schwalm, Raffaele Tranquillini,
Jasper Korten, Thomas Graichen, Stefan Eichenberger,
Stefan Agner, Peter Geis, devicetree, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1128 bytes --]
On Wed, Dec 15, 2021 at 05:19:09PM +0300, Dmitry Osipenko wrote:
> 15.12.2021 16:28, Thierry Reding пишет:
> > On Sun, Dec 12, 2021 at 12:13:52AM +0300, Dmitry Osipenko wrote:
> > [...]
> >> + display-panel {
> >> + compatible = "hannstar,hsd101pww2";
> >
> > There doesn't seem to be a DT binding for this and I can't find any
> > patches where this would be added. Is there a patch somewhere to do
> > this?
>
> Are you trolling me? :/ Please search the "Tegra kernel patches for
> 5.17" email in your inbox, it must be there. Please read and answer to it.
Hmm... I searched for this in my inbox and couldn't find it. Odd.
> All patches are in the Tegra patchwork. Who marked them "Not Applicable"?
>
> https://patchwork.ozlabs.org/project/linux-tegra/patch/20211211213653.17700-3-digetx@gmail.com/
>
> https://patchwork.ozlabs.org/project/linux-tegra/list/?series=276358
I will regularly go over patchwork and mark things "Not Applicable" if
they don't go in via the Tegra tree. These would have to go in via DRM
and so are not relevant on the linux-tegra patchwork instance.
Thierry
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 15/28] ARM: tegra: Add usb-role-switch property to USB OTG ports
2021-12-15 15:04 ` Dmitry Osipenko
@ 2021-12-15 15:16 ` Thierry Reding
2021-12-15 15:45 ` Dmitry Osipenko
0 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-12-15 15:16 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Jonathan Hunter, David Heidelberg, Svyatoslav Ryhel,
Anton Bambura, Antoni Aloy Torrens, Nikola Milosavljevic,
Ion Agorria, Michał Mirosław, Ihor Didenko,
Andreas Westman Dorcsak, Maxim Schwalm, Raffaele Tranquillini,
Jasper Korten, Thomas Graichen, Stefan Eichenberger,
Stefan Agner, Peter Geis, devicetree, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2889 bytes --]
On Wed, Dec 15, 2021 at 06:04:54PM +0300, Dmitry Osipenko wrote:
> 15.12.2021 16:14, Thierry Reding пишет:
> > On Sun, Dec 12, 2021 at 12:13:59AM +0300, Dmitry Osipenko wrote:
> >> From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
> >>
> >> If an USB port is an OTG port, then we should add the usb-role-switch
> >> property. Otherwise XUSB setup fails and therefore padctl is unable to
> >> set up the ports. This leads to broken USB and PCIe ports. Add the
> >> usb-role-switch properties to Tegra124 device-trees to fix the problem.
> >>
> >> The error message shown without this patch is e.g:
> >> usb2-0: usb-role-switch not found for otg mode
> >>
> >> [digetx@gmail.com: improved commit message]
> >> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
> >> Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
> >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> >> ---
> >> arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 1 +
> >> arch/arm/boot/dts/tegra124-apalis.dtsi | 1 +
> >> arch/arm/boot/dts/tegra124-nyan.dtsi | 1 +
> >> arch/arm/boot/dts/tegra124-venice2.dts | 2 +-
> >> 4 files changed, 4 insertions(+), 1 deletion(-)
> >
> > The device tree bindings for the XUSB pad controller say that when this
> > property is set, then the "connector" subnode should also exist.
> >
> > Any chance we can add that? I was planning on making that a dependency
> > in the json-schema conversion of the binding, in which case it would be
> > more of a "must" than a "should".
>
> I guess it will be harmless if you'll add the connector subnodes. Will
> you be able to create a separate patch that will add the subnodes on top
> of this patch?
>
> Thomas Graichen says that one USB port on Nyan Big doesn't work without
> this patch. This is why this patch is needed essentially.
Okay, I can add "dummy" connector nodes for now. I don't see how we can
properly set this up because as far as I can tell there's USB ID GPIO on
Tegra124 (seems like it's a fixed function pin) and the VBUS GPIO is
already used to enable the VBUS supply. The gpio-usb-b-connector binding
required at least one of the ID and VBUS GPIOs to be specified.
On the other hand, at least Venice2 has a USB type A connector for this,
so I'm not even sure how that would work. I vaguely recall that the
Tegra20 Seaboard also had a USB type A and that it was possible to use
it in device mode, but I don't how that would. Nor would it be correct
to use the gpio-usb-b-connector compatible for that since, well, it's
not USB type B.
I suspect that Apalis has a micro-B port, much like the Jetson TK1. My
understanding is that OTG doesn't work on Jetson TK1 (which is why it's
configured in "host" mode), so it'd be interesting to see if this can be
made to work on Apalis.
Thierry
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 11/28] ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T
2021-12-15 14:52 ` Dmitry Osipenko
@ 2021-12-15 15:19 ` Thierry Reding
2021-12-15 15:28 ` David Heidelberg
0 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-12-15 15:19 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Jonathan Hunter, David Heidelberg, Svyatoslav Ryhel,
Anton Bambura, Antoni Aloy Torrens, Nikola Milosavljevic,
Ion Agorria, Michał Mirosław, Ihor Didenko,
Andreas Westman Dorcsak, Maxim Schwalm, Raffaele Tranquillini,
Jasper Korten, Thomas Graichen, Stefan Eichenberger,
Stefan Agner, Peter Geis, devicetree, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2627 bytes --]
On Wed, Dec 15, 2021 at 05:52:24PM +0300, Dmitry Osipenko wrote:
> 15.12.2021 17:01, Thierry Reding пишет:
> > On Sun, Dec 12, 2021 at 12:13:55AM +0300, Dmitry Osipenko wrote:
> > [...]
> >> + i2c@1 {
> >> + reg = <1>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + dsi-bridge@7 {
> >> + compatible = "toshiba,tc358768";
> >> + reg = <0x7>;
> >> +
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + clocks = <&tc358768_osc>;
> >> + clock-names = "refclk";
> >> +
> >> + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
> >> +
> >> + vddc-supply = <&vdd_1v2_mipi>;
> >> + vddio-supply = <&vdd_1v8_vio>;
> >> + vddmipi-supply = <&vdd_1v2_mipi>;
> >> +
> >> + ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port@0 {
> >> + reg = <0>;
> >> +
> >> + bridge_input: endpoint {
> >> + remote-endpoint = <&dpi_output>;
> >> + data-lines = <24>;
> >> + };
> >> + };
> >> +
> >> + port@1 {
> >> + reg = <1>;
> >> +
> >> + bridge_output: endpoint {
> >> + remote-endpoint = <&panel_input>;
> >> + };
> >> + };
> >> + };
> >> +
> >> + /*
> >> + * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
> >> + * LCD SuperIPS+ Full HD panel.
> >> + */
> >> + panel@1 {
> >> + compatible = "panasonic,vvx10f004b00";
> >> + reg = <1>;
> >> +
> >> + power-supply = <&vdd_pnl>;
> >> + backlight = <&backlight>;
> >> +
> >> + port {
> >> + panel_input: endpoint {
> >> + remote-endpoint = <&bridge_output>;
> >> + };
> >> + };
> >> + };
> >
> > make dtbs_check complains about this and says that panel@1 (as well as
> > #address-cells and #size-cells) are not allowed here. And indeed the
> > binding for the Toshiba bridge doesn't mention them here.
> >
> > Do we need this here or should this be moved to the top level to fix
> > those warnings? I guess what you're doing above is describe a DSI bus
> > created by the DSI bridge, which also makes sense, so another
> > alternative would be to fix up the binding and let it accept those
> > properties.
>
> Toshiba bridge binding is incomplete. David has patch for that [1], I
> don't think that it was sent out yet.
>
> [1]
> https://github.com/okias/linux/commit/0875230062294b6db17f395ced0a8384a4c1cfc7
Okay, please make sure this finds its way upstream eventually. That
patch looks quite similar to what I tried to do to fix this up locally.
Thierry
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 11/28] ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T
2021-12-15 15:19 ` Thierry Reding
@ 2021-12-15 15:28 ` David Heidelberg
0 siblings, 0 replies; 42+ messages in thread
From: David Heidelberg @ 2021-12-15 15:28 UTC (permalink / raw)
To: Thierry Reding
Cc: Dmitry Osipenko, Jonathan Hunter, Svyatoslav Ryhel,
Anton Bambura, Antoni Aloy Torrens, Nikola Milosavljevic,
Ion Agorria, Michał Mirosław, Ihor Didenko,
Andreas Westman Dorcsak, Maxim Schwalm, Raffaele Tranquillini,
Jasper Korten, Thomas Graichen, Stefan Eichenberger,
Stefan Agner, Peter Geis, devicetree, linux-tegra, linux-kernel
Hello Dmitry and Thierry!
Sent as "[PATCH] dt-bindings: display: bridge: document Toshiba
TC358768 cells and panel node",
I'll try to not keep these patches for myself for so long.
David
On Wed, Dec 15 2021 at 16:19:19 +0100, Thierry Reding
<thierry.reding@gmail.com> wrote:
> On Wed, Dec 15, 2021 at 05:52:24PM +0300, Dmitry Osipenko wrote:
>> 15.12.2021 17:01, Thierry Reding пишет:
>> > On Sun, Dec 12, 2021 at 12:13:55AM +0300, Dmitry Osipenko wrote:
>> > [...]
>> >> + i2c@1 {
>> >> + reg = <1>;
>> >> + #address-cells = <1>;
>> >> + #size-cells = <0>;
>> >> +
>> >> + dsi-bridge@7 {
>> >> + compatible = "toshiba,tc358768";
>> >> + reg = <0x7>;
>> >> +
>> >> + #address-cells = <1>;
>> >> + #size-cells = <0>;
>> >> +
>> >> + clocks = <&tc358768_osc>;
>> >> + clock-names = "refclk";
>> >> +
>> >> + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
>> >> +
>> >> + vddc-supply = <&vdd_1v2_mipi>;
>> >> + vddio-supply = <&vdd_1v8_vio>;
>> >> + vddmipi-supply = <&vdd_1v2_mipi>;
>> >> +
>> >> + ports {
>> >> + #address-cells = <1>;
>> >> + #size-cells = <0>;
>> >> +
>> >> + port@0 {
>> >> + reg = <0>;
>> >> +
>> >> + bridge_input: endpoint {
>> >> + remote-endpoint = <&dpi_output>;
>> >> + data-lines = <24>;
>> >> + };
>> >> + };
>> >> +
>> >> + port@1 {
>> >> + reg = <1>;
>> >> +
>> >> + bridge_output: endpoint {
>> >> + remote-endpoint = <&panel_input>;
>> >> + };
>> >> + };
>> >> + };
>> >> +
>> >> + /*
>> >> + * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
>> >> + * LCD SuperIPS+ Full HD panel.
>> >> + */
>> >> + panel@1 {
>> >> + compatible = "panasonic,vvx10f004b00";
>> >> + reg = <1>;
>> >> +
>> >> + power-supply = <&vdd_pnl>;
>> >> + backlight = <&backlight>;
>> >> +
>> >> + port {
>> >> + panel_input: endpoint {
>> >> + remote-endpoint = <&bridge_output>;
>> >> + };
>> >> + };
>> >> + };
>> >
>> > make dtbs_check complains about this and says that panel@1 (as
>> well as
>> > #address-cells and #size-cells) are not allowed here. And indeed
>> the
>> > binding for the Toshiba bridge doesn't mention them here.
>> >
>> > Do we need this here or should this be moved to the top level to
>> fix
>> > those warnings? I guess what you're doing above is describe a DSI
>> bus
>> > created by the DSI bridge, which also makes sense, so another
>> > alternative would be to fix up the binding and let it accept those
>> > properties.
>>
>> Toshiba bridge binding is incomplete. David has patch for that [1],
>> I
>> don't think that it was sent out yet.
>>
>> [1]
>>
>> https://github.com/okias/linux/commit/0875230062294b6db17f395ced0a8384a4c1cfc7
>
> Okay, please make sure this finds its way upstream eventually. That
> patch looks quite similar to what I tried to do to fix this up
> locally.
>
> Thierry
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 15/28] ARM: tegra: Add usb-role-switch property to USB OTG ports
2021-12-15 15:16 ` Thierry Reding
@ 2021-12-15 15:45 ` Dmitry Osipenko
2021-12-15 15:52 ` Thierry Reding
0 siblings, 1 reply; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-15 15:45 UTC (permalink / raw)
To: Thierry Reding
Cc: Jonathan Hunter, David Heidelberg, Svyatoslav Ryhel,
Anton Bambura, Antoni Aloy Torrens, Nikola Milosavljevic,
Ion Agorria, Michał Mirosław, Ihor Didenko,
Andreas Westman Dorcsak, Maxim Schwalm, Raffaele Tranquillini,
Jasper Korten, Thomas Graichen, Stefan Eichenberger,
Stefan Agner, Peter Geis, devicetree, linux-tegra, linux-kernel
15.12.2021 18:16, Thierry Reding пишет:
> On Wed, Dec 15, 2021 at 06:04:54PM +0300, Dmitry Osipenko wrote:
>> 15.12.2021 16:14, Thierry Reding пишет:
>>> On Sun, Dec 12, 2021 at 12:13:59AM +0300, Dmitry Osipenko wrote:
>>>> From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
>>>>
>>>> If an USB port is an OTG port, then we should add the usb-role-switch
>>>> property. Otherwise XUSB setup fails and therefore padctl is unable to
>>>> set up the ports. This leads to broken USB and PCIe ports. Add the
>>>> usb-role-switch properties to Tegra124 device-trees to fix the problem.
>>>>
>>>> The error message shown without this patch is e.g:
>>>> usb2-0: usb-role-switch not found for otg mode
>>>>
>>>> [digetx@gmail.com: improved commit message]
>>>> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
>>>> Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>>> ---
>>>> arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 1 +
>>>> arch/arm/boot/dts/tegra124-apalis.dtsi | 1 +
>>>> arch/arm/boot/dts/tegra124-nyan.dtsi | 1 +
>>>> arch/arm/boot/dts/tegra124-venice2.dts | 2 +-
>>>> 4 files changed, 4 insertions(+), 1 deletion(-)
>>>
>>> The device tree bindings for the XUSB pad controller say that when this
>>> property is set, then the "connector" subnode should also exist.
>>>
>>> Any chance we can add that? I was planning on making that a dependency
>>> in the json-schema conversion of the binding, in which case it would be
>>> more of a "must" than a "should".
>>
>> I guess it will be harmless if you'll add the connector subnodes. Will
>> you be able to create a separate patch that will add the subnodes on top
>> of this patch?
>>
>> Thomas Graichen says that one USB port on Nyan Big doesn't work without
>> this patch. This is why this patch is needed essentially.
>
> Okay, I can add "dummy" connector nodes for now. I don't see how we can
> properly set this up because as far as I can tell there's USB ID GPIO on
> Tegra124 (seems like it's a fixed function pin) and the VBUS GPIO is
> already used to enable the VBUS supply. The gpio-usb-b-connector binding
> required at least one of the ID and VBUS GPIOs to be specified.
The ID and VBUS hardware configurations are very board-specific. There
are multiple ways of how it could implemented on Tegra.
> On the other hand, at least Venice2 has a USB type A connector for this,
> so I'm not even sure how that would work. I vaguely recall that the
> Tegra20 Seaboard also had a USB type A and that it was possible to use
> it in device mode, but I don't how that would. Nor would it be correct
> to use the gpio-usb-b-connector compatible for that since, well, it's
> not USB type B.
I'm not sure whether it makes much sense to use OTG for USB type A
connectors, normally they should be fixed to host mode.
> I suspect that Apalis has a micro-B port, much like the Jetson TK1. My
> understanding is that OTG doesn't work on Jetson TK1 (which is why it's
> configured in "host" mode), so it'd be interesting to see if this can be
> made to work on Apalis.
Looks like the default Apalis carrier board has three type A connectors.
https://www.toradex.com/products/carrier-board/ixora-carrier-board
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 15/28] ARM: tegra: Add usb-role-switch property to USB OTG ports
2021-12-15 15:45 ` Dmitry Osipenko
@ 2021-12-15 15:52 ` Thierry Reding
2021-12-15 17:16 ` Dmitry Osipenko
0 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-12-15 15:52 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Jonathan Hunter, David Heidelberg, Svyatoslav Ryhel,
Anton Bambura, Antoni Aloy Torrens, Nikola Milosavljevic,
Ion Agorria, Michał Mirosław, Ihor Didenko,
Andreas Westman Dorcsak, Maxim Schwalm, Raffaele Tranquillini,
Jasper Korten, Thomas Graichen, Stefan Eichenberger,
Stefan Agner, Peter Geis, devicetree, linux-tegra, linux-kernel
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On Wed, Dec 15, 2021 at 06:45:32PM +0300, Dmitry Osipenko wrote:
> 15.12.2021 18:16, Thierry Reding пишет:
> > On Wed, Dec 15, 2021 at 06:04:54PM +0300, Dmitry Osipenko wrote:
> >> 15.12.2021 16:14, Thierry Reding пишет:
> >>> On Sun, Dec 12, 2021 at 12:13:59AM +0300, Dmitry Osipenko wrote:
> >>>> From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
> >>>>
> >>>> If an USB port is an OTG port, then we should add the usb-role-switch
> >>>> property. Otherwise XUSB setup fails and therefore padctl is unable to
> >>>> set up the ports. This leads to broken USB and PCIe ports. Add the
> >>>> usb-role-switch properties to Tegra124 device-trees to fix the problem.
> >>>>
> >>>> The error message shown without this patch is e.g:
> >>>> usb2-0: usb-role-switch not found for otg mode
> >>>>
> >>>> [digetx@gmail.com: improved commit message]
> >>>> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
> >>>> Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
> >>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> >>>> ---
> >>>> arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 1 +
> >>>> arch/arm/boot/dts/tegra124-apalis.dtsi | 1 +
> >>>> arch/arm/boot/dts/tegra124-nyan.dtsi | 1 +
> >>>> arch/arm/boot/dts/tegra124-venice2.dts | 2 +-
> >>>> 4 files changed, 4 insertions(+), 1 deletion(-)
> >>>
> >>> The device tree bindings for the XUSB pad controller say that when this
> >>> property is set, then the "connector" subnode should also exist.
> >>>
> >>> Any chance we can add that? I was planning on making that a dependency
> >>> in the json-schema conversion of the binding, in which case it would be
> >>> more of a "must" than a "should".
> >>
> >> I guess it will be harmless if you'll add the connector subnodes. Will
> >> you be able to create a separate patch that will add the subnodes on top
> >> of this patch?
> >>
> >> Thomas Graichen says that one USB port on Nyan Big doesn't work without
> >> this patch. This is why this patch is needed essentially.
> >
> > Okay, I can add "dummy" connector nodes for now. I don't see how we can
> > properly set this up because as far as I can tell there's USB ID GPIO on
> > Tegra124 (seems like it's a fixed function pin) and the VBUS GPIO is
> > already used to enable the VBUS supply. The gpio-usb-b-connector binding
> > required at least one of the ID and VBUS GPIOs to be specified.
>
> The ID and VBUS hardware configurations are very board-specific. There
> are multiple ways of how it could implemented on Tegra.
>
> > On the other hand, at least Venice2 has a USB type A connector for this,
> > so I'm not even sure how that would work. I vaguely recall that the
> > Tegra20 Seaboard also had a USB type A and that it was possible to use
> > it in device mode, but I don't how that would. Nor would it be correct
> > to use the gpio-usb-b-connector compatible for that since, well, it's
> > not USB type B.
>
> I'm not sure whether it makes much sense to use OTG for USB type A
> connectors, normally they should be fixed to host mode.
My recollection is that those can be used in device mode as well. For
example that USB type A port on Venice2 (same as for Seaboard) can be
used for RCM, IIRC. It's possible that there's no way to detect what is
connected, though, so this may not be proper OTG.
>
> > I suspect that Apalis has a micro-B port, much like the Jetson TK1. My
> > understanding is that OTG doesn't work on Jetson TK1 (which is why it's
> > configured in "host" mode), so it'd be interesting to see if this can be
> > made to work on Apalis.
>
> Looks like the default Apalis carrier board has three type A connectors.
>
> https://www.toradex.com/products/carrier-board/ixora-carrier-board
I'm wondering if the best thing would be to mark all of these as "host"
for now and avoid making this look like something that it isn't. I don't
think we've ever made OTG work on these boards, so perhaps we shouldn't
assume that it works.
Thierry
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v6 15/28] ARM: tegra: Add usb-role-switch property to USB OTG ports
2021-12-15 15:52 ` Thierry Reding
@ 2021-12-15 17:16 ` Dmitry Osipenko
0 siblings, 0 replies; 42+ messages in thread
From: Dmitry Osipenko @ 2021-12-15 17:16 UTC (permalink / raw)
To: Thierry Reding
Cc: Jonathan Hunter, David Heidelberg, Svyatoslav Ryhel,
Anton Bambura, Antoni Aloy Torrens, Nikola Milosavljevic,
Ion Agorria, Michał Mirosław, Ihor Didenko,
Andreas Westman Dorcsak, Maxim Schwalm, Raffaele Tranquillini,
Jasper Korten, Thomas Graichen, Stefan Eichenberger,
Stefan Agner, Peter Geis, devicetree, linux-tegra, linux-kernel
15.12.2021 18:52, Thierry Reding пишет:
>>> On the other hand, at least Venice2 has a USB type A connector for this,
>>> so I'm not even sure how that would work. I vaguely recall that the
>>> Tegra20 Seaboard also had a USB type A and that it was possible to use
>>> it in device mode, but I don't how that would. Nor would it be correct
>>> to use the gpio-usb-b-connector compatible for that since, well, it's
>>> not USB type B.
>> I'm not sure whether it makes much sense to use OTG for USB type A
>> connectors, normally they should be fixed to host mode.
> My recollection is that those can be used in device mode as well. For
> example that USB type A port on Venice2 (same as for Seaboard) can be
> used for RCM, IIRC. It's possible that there's no way to detect what is
> connected, though, so this may not be proper OTG.
Sounds correct.
>>> I suspect that Apalis has a micro-B port, much like the Jetson TK1. My
>>> understanding is that OTG doesn't work on Jetson TK1 (which is why it's
>>> configured in "host" mode), so it'd be interesting to see if this can be
>>> made to work on Apalis.
>> Looks like the default Apalis carrier board has three type A connectors.
>>
>> https://www.toradex.com/products/carrier-board/ixora-carrier-board
> I'm wondering if the best thing would be to mark all of these as "host"
> for now and avoid making this look like something that it isn't. I don't
> think we've ever made OTG work on these boards, so perhaps we shouldn't
> assume that it works.
Marking them "host" should be correct, but that wasn't tested.
I assume that those "OTG" ports may default to the host mode.
^ permalink raw reply [flat|nested] 42+ messages in thread
end of thread, other threads:[~2021-12-17 3:43 UTC | newest]
Thread overview: 42+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-11 21:13 [PATCH v6 00/28] NVIDIA Tegra ARM32 device-tree patches for 5.17 (new devices and more) Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 01/28] dt-bindings: ARM: tegra: Document ASUS Transformers Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 02/28] dt-bindings: ARM: tegra: Document Pegatron Chagall Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 03/28] ARM: tegra: Add labels to tegra30.dtsi Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 04/28] ARM: tegra: Add labels to tegra114.dtsi Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 05/28] ARM: tegra: Add device-tree for ASUS Transformer EeePad TF101 Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 06/28] ARM: tegra: Add common device-tree base for Tegra30 ASUS Transformers Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 07/28] ARM: tegra: Add common device-tree for LVDS display panels of Tegra30 ASUS tablets Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 08/28] ARM: tegra: Add device-tree for ASUS Transformer Prime TF201 Dmitry Osipenko
2021-12-15 13:28 ` Thierry Reding
2021-12-15 14:19 ` Dmitry Osipenko
2021-12-15 15:09 ` Thierry Reding
2021-12-11 21:13 ` [PATCH v6 09/28] ARM: tegra: Add device-tree for ASUS Transformer Pad TF300T Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 10/28] ARM: tegra: Add device-tree for ASUS Transformer Pad TF300TG Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 11/28] ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T Dmitry Osipenko
2021-12-15 14:01 ` Thierry Reding
2021-12-15 14:52 ` Dmitry Osipenko
2021-12-15 15:19 ` Thierry Reding
2021-12-15 15:28 ` David Heidelberg
2021-12-11 21:13 ` [PATCH v6 12/28] ARM: tegra: Add device-tree for ASUS Transformer Pad TF701T Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 13/28] ARM: tegra: Add device-tree for Pegatron Chagall Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 14/28] ARM: tegra: Add device-tree for 1080p version of Nyan Big Dmitry Osipenko
2021-12-11 21:13 ` [PATCH v6 15/28] ARM: tegra: Add usb-role-switch property to USB OTG ports Dmitry Osipenko
2021-12-15 13:14 ` Thierry Reding
2021-12-15 15:04 ` Dmitry Osipenko
2021-12-15 15:16 ` Thierry Reding
2021-12-15 15:45 ` Dmitry Osipenko
2021-12-15 15:52 ` Thierry Reding
2021-12-15 17:16 ` Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 16/28] ARM: tegra: Enable HDMI CEC on Nyan Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 17/28] ARM: tegra: Enable CPU DFLL " Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 18/28] ARM: tegra: Add CPU thermal zones to Nyan device-tree Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 19/28] ARM: tegra: Rename top-level clocks Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 20/28] ARM: tegra: Rename top-level regulators Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 21/28] ARM: tegra: nexus7: Drop clock-frequency from NFC node Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 22/28] ARM: tegra: nexus7: Use common LVDS display device-tree Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 23/28] ARM: tegra: Add #reset-cells for Tegra114 MC Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 24/28] ARM: tegra: Enable video decoder on Tegra114 Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 25/28] ARM: tegra: Remove stray #reset-cells property Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 26/28] ARM: tegra: Re-add gpio-ranges properties Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 27/28] ARM: tegra_defconfig: Enable drivers wanted by Acer Chromebooks and ASUS tablets Dmitry Osipenko
2021-12-11 21:14 ` [PATCH v6 28/28] ARM: config: multi v7: Enable display drivers used by Tegra devices Dmitry Osipenko
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