* [boot-wrapper PATCH 1/2] aarch64: Document what we're doing when setting ZCR_EL3.LEN
@ 2022-02-01 17:21 broonie
2022-02-01 17:21 ` [boot-wrapper PATCH 2/2] aarch64: Enable use of SME by EL2 and below broonie
0 siblings, 1 reply; 6+ messages in thread
From: broonie @ 2022-02-01 17:21 UTC (permalink / raw)
To: Mark Rutland; +Cc: linux-arm-kernel, Mark Brown
From: Mark Brown <broonie@kernel.org>
The enumeration and configuration algorithm for SVE vector lengths is not
100% obvious so add a comment explaining what's going on in case someone
looks at this code as a reference. If this is ever used on hardware with
asymmetric vector lengths we will need to handle this differently to meet
Linux's boot requirements but this is not a present issue and such hardware
would be fairly surprising.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/aarch64/init.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index aa58567..8bb0524 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -88,6 +88,10 @@ void cpu_init_el3(void)
cptr |= CPTR_EL3_EZ;
msr(CPTR_EL3, cptr);
isb();
+ /*
+ * Write the maximum possible vector length, hardware
+ * will constrain to the actual limit.
+ */
msr(ZCR_EL3, ZCR_EL3_LEN_MAX);
}
--
2.30.2
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [boot-wrapper PATCH 2/2] aarch64: Enable use of SME by EL2 and below
2022-02-01 17:21 [boot-wrapper PATCH 1/2] aarch64: Document what we're doing when setting ZCR_EL3.LEN broonie
@ 2022-02-01 17:21 ` broonie
2022-02-01 18:16 ` Mark Rutland
0 siblings, 1 reply; 6+ messages in thread
From: broonie @ 2022-02-01 17:21 UTC (permalink / raw)
To: Mark Rutland; +Cc: linux-arm-kernel, Mark Brown
From: Mark Brown <broonie@kernel.org>
Allow lower ELs to use SME when booted on a system that support it. This
requires us to set two new bits, one in each of SCR_EL3 and CPTR_EL3, set
the maximum vector length in a similar fashion to SVE and if the optional
FA64 feature is present then set another feature bit in the new SMCR
register.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/aarch64/include/asm/cpu.h | 10 ++++++++++
arch/aarch64/init.c | 22 ++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index ce80b6e..49f5a71 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -49,6 +49,7 @@
#define SCR_EL3_FGTEN BIT(27)
#define SCR_EL3_ECVEN BIT(28)
#define SCR_EL3_TME BIT(34)
+#define SCR_EL3_EnTP2 BIT(41)
#define HCR_EL2_RES1 BIT(1)
@@ -69,9 +70,13 @@
#define ID_AA64MMFR0_EL1_FGT BITS(59, 56)
#define ID_AA64MMFR0_EL1_ECV BITS(63, 60)
+#define ID_AA64PFR1_EL1_SME BITS(27, 24)
#define ID_AA64PFR1_EL1_MTE BITS(11, 8)
#define ID_AA64PFR0_EL1_SVE BITS(35, 32)
+#define ID_AA64SMFR0_EL1 s3_0_c0_c4_5
+#define ID_AA64SMFR0_EL1_FA64 (1UL << 63)
+
/*
* Initial register values required for the boot-wrapper to run out-of-reset.
*/
@@ -96,6 +101,7 @@
#define SPSR_EL2H (9 << 0) /* EL2 Handler mode */
#define SPSR_HYP (0x1a << 0) /* M[3:0] = hyp, M[4] = AArch32 */
+#define CPTR_EL3_ESM (1 << 12)
#define CPTR_EL3_EZ (1 << 8)
#define ICC_SRE_EL2 S3_4_C12_C9_5
@@ -107,6 +113,10 @@
#define ZCR_EL3 s3_6_c1_c2_0
#define ZCR_EL3_LEN_MAX 0xf
+#define SMCR_EL3 s3_6_c1_c2_6
+#define SMCR_EL3_FA64 (1 << 31)
+#define SMCR_EL3_LEN_MAX 0xf
+
#define ID_AA64ISAR2_EL1 s3_0_c0_c6_2
#define SCTLR_EL1_CP15BEN (1 << 5)
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index 8bb0524..db73b58 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -47,6 +47,7 @@ void cpu_init_el3(void)
unsigned long scr = SCR_EL3_RES1 | SCR_EL3_NS | SCR_EL3_HCE;
unsigned long mdcr = 0;
unsigned long cptr = 0;
+ unsigned long smcr = 0;
if (cpu_has_pauth())
scr |= SCR_EL3_APK | SCR_EL3_API;
@@ -95,6 +96,27 @@ void cpu_init_el3(void)
msr(ZCR_EL3, ZCR_EL3_LEN_MAX);
}
+ if (mrs_field(ID_AA64PFR1_EL1, SME)) {
+ cptr |= CPTR_EL3_ESM;
+ msr(CPTR_EL3, cptr);
+ isb();
+
+ scr |= SCR_EL3_EnTP2;
+ msr(SCR_EL3, scr);
+ isb();
+
+ /*
+ * Write the maximum possible vector length, hardware
+ * will constrain to the actual limit.
+ */
+ smcr = SMCR_EL3_LEN_MAX;
+
+ if (mrs_field(ID_AA64SMFR0_EL1, FA64))
+ smcr |= SMCR_EL3_FA64;
+
+ msr(SMCR_EL3, smcr);
+ }
+
msr(CNTFRQ_EL0, COUNTER_FREQ);
}
--
2.30.2
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [boot-wrapper PATCH 2/2] aarch64: Enable use of SME by EL2 and below
2022-02-01 17:21 ` [boot-wrapper PATCH 2/2] aarch64: Enable use of SME by EL2 and below broonie
@ 2022-02-01 18:16 ` Mark Rutland
2022-02-01 18:22 ` Mark Brown
2022-02-04 10:59 ` Mark Rutland
0 siblings, 2 replies; 6+ messages in thread
From: Mark Rutland @ 2022-02-01 18:16 UTC (permalink / raw)
To: broonie; +Cc: linux-arm-kernel
Hi Mark,
On Tue, Feb 01, 2022 at 05:21:32PM +0000, broonie@kernel.org wrote:
> From: Mark Brown <broonie@kernel.org>
>
> Allow lower ELs to use SME when booted on a system that support it. This
> requires us to set two new bits, one in each of SCR_EL3 and CPTR_EL3, set
> the maximum vector length in a similar fashion to SVE and if the optional
> FA64 feature is present then set another feature bit in the new SMCR
> register.
This looks good to me. I'll wait a day or so to allow others to review, but if
no-one shouts I'll apply this (along with patch 1) before the end of the week.
There's one trivial fixup I intend to make when applying (noted below), but
regardless this looks good structurally and value-wise, so no need to respin
unless someone shouts.
I checked the register encodings and bit definitions against developer.arm.com:
* CPTR_EL3
https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/CPTR-EL3--Architectural-Feature-Trap-Register--EL3-?lang=en
* ID_AA64PFR1_EL1
https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/ID-AA64PFR1-EL1--AArch64-Processor-Feature-Register-1?lang=en
* ID_AA64SMFR0_EL1
https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/ID-AA64SMFR0-EL1--SME-Feature-ID-register-0?lang=en
* SCR_EL3
https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/SCR-EL3--Secure-Configuration-Register?lang=en
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/aarch64/include/asm/cpu.h | 10 ++++++++++
> arch/aarch64/init.c | 22 ++++++++++++++++++++++
> 2 files changed, 32 insertions(+)
>
> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
> index ce80b6e..49f5a71 100644
> --- a/arch/aarch64/include/asm/cpu.h
> +++ b/arch/aarch64/include/asm/cpu.h
> @@ -49,6 +49,7 @@
> #define SCR_EL3_FGTEN BIT(27)
> #define SCR_EL3_ECVEN BIT(28)
> #define SCR_EL3_TME BIT(34)
> +#define SCR_EL3_EnTP2 BIT(41)
>
> #define HCR_EL2_RES1 BIT(1)
>
> @@ -69,9 +70,13 @@
> #define ID_AA64MMFR0_EL1_FGT BITS(59, 56)
> #define ID_AA64MMFR0_EL1_ECV BITS(63, 60)
>
> +#define ID_AA64PFR1_EL1_SME BITS(27, 24)
> #define ID_AA64PFR1_EL1_MTE BITS(11, 8)
> #define ID_AA64PFR0_EL1_SVE BITS(35, 32)
>
> +#define ID_AA64SMFR0_EL1 s3_0_c0_c4_5
> +#define ID_AA64SMFR0_EL1_FA64 (1UL << 63)
For consistency with the other ID fields, I'm going to make this:
#define ID_AA64SMFR0_EL1_FA64 BIT(63)
In future I'd like to split the remaining definitions using shifted bits into
separate <register>_<field> and <register>_<field>_<value> definitions (or
something of that rought shape) so that field boundaries are always explicit,
but those can stay as-is for now.
> +
> /*
> * Initial register values required for the boot-wrapper to run out-of-reset.
> */
> @@ -96,6 +101,7 @@
> #define SPSR_EL2H (9 << 0) /* EL2 Handler mode */
> #define SPSR_HYP (0x1a << 0) /* M[3:0] = hyp, M[4] = AArch32 */
>
> +#define CPTR_EL3_ESM (1 << 12)
> #define CPTR_EL3_EZ (1 << 8)
>
> #define ICC_SRE_EL2 S3_4_C12_C9_5
> @@ -107,6 +113,10 @@
> #define ZCR_EL3 s3_6_c1_c2_0
> #define ZCR_EL3_LEN_MAX 0xf
>
> +#define SMCR_EL3 s3_6_c1_c2_6
> +#define SMCR_EL3_FA64 (1 << 31)
> +#define SMCR_EL3_LEN_MAX 0xf
> +
> #define ID_AA64ISAR2_EL1 s3_0_c0_c6_2
>
> #define SCTLR_EL1_CP15BEN (1 << 5)
> diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
> index 8bb0524..db73b58 100644
> --- a/arch/aarch64/init.c
> +++ b/arch/aarch64/init.c
> @@ -47,6 +47,7 @@ void cpu_init_el3(void)
> unsigned long scr = SCR_EL3_RES1 | SCR_EL3_NS | SCR_EL3_HCE;
> unsigned long mdcr = 0;
> unsigned long cptr = 0;
> + unsigned long smcr = 0;
>
> if (cpu_has_pauth())
> scr |= SCR_EL3_APK | SCR_EL3_API;
> @@ -95,6 +96,27 @@ void cpu_init_el3(void)
> msr(ZCR_EL3, ZCR_EL3_LEN_MAX);
> }
>
> + if (mrs_field(ID_AA64PFR1_EL1, SME)) {
> + cptr |= CPTR_EL3_ESM;
> + msr(CPTR_EL3, cptr);
> + isb();
> +
> + scr |= SCR_EL3_EnTP2;
> + msr(SCR_EL3, scr);
> + isb();
> +
> + /*
> + * Write the maximum possible vector length, hardware
> + * will constrain to the actual limit.
> + */
> + smcr = SMCR_EL3_LEN_MAX;
> +
> + if (mrs_field(ID_AA64SMFR0_EL1, FA64))
> + smcr |= SMCR_EL3_FA64;
> +
> + msr(SMCR_EL3, smcr);
> + }
> +
> msr(CNTFRQ_EL0, COUNTER_FREQ);
> }
>
> --
> 2.30.2
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [boot-wrapper PATCH 2/2] aarch64: Enable use of SME by EL2 and below
2022-02-01 18:16 ` Mark Rutland
@ 2022-02-01 18:22 ` Mark Brown
2022-02-02 10:30 ` Mark Rutland
2022-02-04 10:59 ` Mark Rutland
1 sibling, 1 reply; 6+ messages in thread
From: Mark Brown @ 2022-02-01 18:22 UTC (permalink / raw)
To: Mark Rutland; +Cc: linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 867 bytes --]
On Tue, Feb 01, 2022 at 06:16:58PM +0000, Mark Rutland wrote:
> On Tue, Feb 01, 2022 at 05:21:32PM +0000, broonie@kernel.org wrote:
> > +#define ID_AA64SMFR0_EL1 s3_0_c0_c4_5
> > +#define ID_AA64SMFR0_EL1_FA64 (1UL << 63)
> For consistency with the other ID fields, I'm going to make this:
> #define ID_AA64SMFR0_EL1_FA64 BIT(63)
> In future I'd like to split the remaining definitions using shifted bits into
> separate <register>_<field> and <register>_<field>_<value> definitions (or
> something of that rought shape) so that field boundaries are always explicit,
> but those can stay as-is for now.
Sure. I was quite confused about the idioms for the use of BIT() in
this header since it's used for for example both ID registers and SCR
but things like the various SPSR and CPTR defines use shifts, it'd
probably be good to just use BIT() throughout.
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [boot-wrapper PATCH 2/2] aarch64: Enable use of SME by EL2 and below
2022-02-01 18:22 ` Mark Brown
@ 2022-02-02 10:30 ` Mark Rutland
0 siblings, 0 replies; 6+ messages in thread
From: Mark Rutland @ 2022-02-02 10:30 UTC (permalink / raw)
To: Mark Brown; +Cc: linux-arm-kernel
On Tue, Feb 01, 2022 at 06:22:59PM +0000, Mark Brown wrote:
> On Tue, Feb 01, 2022 at 06:16:58PM +0000, Mark Rutland wrote:
> > On Tue, Feb 01, 2022 at 05:21:32PM +0000, broonie@kernel.org wrote:
>
> > > +#define ID_AA64SMFR0_EL1 s3_0_c0_c4_5
> > > +#define ID_AA64SMFR0_EL1_FA64 (1UL << 63)
>
> > For consistency with the other ID fields, I'm going to make this:
>
> > #define ID_AA64SMFR0_EL1_FA64 BIT(63)
>
> > In future I'd like to split the remaining definitions using shifted bits into
> > separate <register>_<field> and <register>_<field>_<value> definitions (or
> > something of that rought shape) so that field boundaries are always explicit,
> > but those can stay as-is for now.
>
> Sure. I was quite confused about the idioms for the use of BIT() in
> this header since it's used for for example both ID registers and SCR
> but things like the various SPSR and CPTR defines use shifts, it'd
> probably be good to just use BIT() throughout.
I generally agree, and sorry that this is a bit of a mess at present!
I'd held off converting everything to BIT() because I had planned to convert
multi-bit fields at the same time with some helper macros that I've dropped for
now to clearly separate the concept of a field of bits from the values that
field may contain.
For example, CURRENTEL_EL2 is (1 << 2), and shouldn't be converted to BIT(2),
because it is a 2-bit value 0b10 in the field bits[3:2].
That said, I'd be happy to convert all the true single-bit fields to BIT() now.
Thanks,
Mark.
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [boot-wrapper PATCH 2/2] aarch64: Enable use of SME by EL2 and below
2022-02-01 18:16 ` Mark Rutland
2022-02-01 18:22 ` Mark Brown
@ 2022-02-04 10:59 ` Mark Rutland
1 sibling, 0 replies; 6+ messages in thread
From: Mark Rutland @ 2022-02-04 10:59 UTC (permalink / raw)
To: broonie; +Cc: linux-arm-kernel
On Tue, Feb 01, 2022 at 06:16:58PM +0000, Mark Rutland wrote:
> Hi Mark,
>
> On Tue, Feb 01, 2022 at 05:21:32PM +0000, broonie@kernel.org wrote:
> > From: Mark Brown <broonie@kernel.org>
> >
> > Allow lower ELs to use SME when booted on a system that support it. This
> > requires us to set two new bits, one in each of SCR_EL3 and CPTR_EL3, set
> > the maximum vector length in a similar fashion to SVE and if the optional
> > FA64 feature is present then set another feature bit in the new SMCR
> > register.
>
> This looks good to me. I'll wait a day or so to allow others to review, but if
> no-one shouts I'll apply this (along with patch 1) before the end of the week.
I've applied both patches now.
Thanks,
Mark.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-02-04 11:00 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-01 17:21 [boot-wrapper PATCH 1/2] aarch64: Document what we're doing when setting ZCR_EL3.LEN broonie
2022-02-01 17:21 ` [boot-wrapper PATCH 2/2] aarch64: Enable use of SME by EL2 and below broonie
2022-02-01 18:16 ` Mark Rutland
2022-02-01 18:22 ` Mark Brown
2022-02-02 10:30 ` Mark Rutland
2022-02-04 10:59 ` Mark Rutland
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