* [PULL] u-boot-riscv/master
@ 2022-02-10 15:16 Leo Liang
2022-02-11 0:35 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2022-02-10 15:16 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick, ycliang
Hi Tom,
The following changes since commit 531c00894577a0a852431adf61ade76925f8b162:
Merge branch '2022-02-08-TI-platform-updates' (2022-02-08 12:28:04 -0500)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 7c08680aa32db12e5a7e2765cfc8b7e8ce8895ff:
doc: qemu-riscv: Update documentation for QEMU spike machine (2022-02-10 11:19:15 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/10941
----------------------------------------------------------------
Anup Patel (4):
serial: Add RISC-V HTIF console driver
riscv: qemu: Enable HTIF console support
riscv: qemu: Implement is_flash_available() for MTD NOR
doc: qemu-riscv: Update documentation for QEMU spike machine
board/emulation/qemu-riscv/Kconfig | 1 +
board/emulation/qemu-riscv/qemu-riscv.c | 12 +++
doc/board/emulation/qemu-riscv.rst | 48 ++++++---
drivers/serial/Kconfig | 8 ++
drivers/serial/Makefile | 1 +
drivers/serial/serial_htif.c | 178 ++++++++++++++++++++++++++++++++
6 files changed, 232 insertions(+), 16 deletions(-)
create mode 100644 drivers/serial/serial_htif.c
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2023-10-19 11:41 Leo Liang
2023-10-19 14:57 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2023-10-19 11:41 UTC (permalink / raw)
To: trini; +Cc: ycliang, rick, u-boot
Hi Tom,
The following changes since commit 9a0cf3993f71043ba08c315572c54622de42d447:
Merge branch '2023-10-17-spl-test-some-load-methods' (2023-10-18 08:28:00 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to bc5a50452bd42029d6587e1596b44ff235655e90:
riscv: Add Zbb support for building U-Boot (2023-10-19 17:29:50 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18215
----------------------------------------------------------------
+ riscv: Add Zbb support
+ riscv: Add preliminary RISC-V falcon mode support
+ riscv: Remove dram_init_banksize()
+ andes: rearrange PLICSW scheme
+ visionfive2: enable bootstage configs
----------------------------------------------------------------
Chanho Park (1):
configs: visionfive2: enable bootstage configs
Heinrich Schuchardt (1):
riscv: remove dram_init_banksize()
Mayuresh Chitale (1):
riscv: binman: Fix compilation error
Randolph (8):
riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy
spl: riscv: opensbi: change the default os_type as varible
riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol
riscv: dts: binman: add condition for opensbi os boot
Makefile: delete file *.itb when make clean
spl: riscv: add os type for next booting stage
andes: config: add riscv falcon mode for ae350 platform
riscv: spl: andes: Move the DTB in front of kernel
Yu Chien Peter Lin (1):
riscv: Add Zbb support for building U-Boot
Makefile | 2 +-
arch/riscv/Kconfig | 99 +++++++++++++++++++++++++++++++
arch/riscv/Makefile | 5 +-
arch/riscv/cpu/generic/dram.c | 16 -----
arch/riscv/dts/binman.dtsi | 38 ++++++++++--
arch/riscv/include/asm/string.h | 18 ++++++
arch/riscv/lib/Makefile | 3 +
arch/riscv/lib/andes_plicsw.c | 24 ++++----
arch/riscv/lib/strcmp_zbb.S | 81 +++++++++++++++++++++++++
arch/riscv/lib/strlen_zbb.S | 101 ++++++++++++++++++++++++++++++++
arch/riscv/lib/strncmp_zbb.S | 94 +++++++++++++++++++++++++++++
board/AndesTech/ae350/ae350.c | 25 ++++++++
common/spl/spl_fit.c | 3 +-
common/spl/spl_opensbi.c | 31 ++++++----
configs/ae350_rv32_falcon_defconfig | 60 +++++++++++++++++++
configs/ae350_rv32_falcon_xip_defconfig | 61 +++++++++++++++++++
configs/ae350_rv64_falcon_defconfig | 60 +++++++++++++++++++
configs/ae350_rv64_falcon_xip_defconfig | 61 +++++++++++++++++++
configs/starfive_visionfive2_defconfig | 2 +
19 files changed, 738 insertions(+), 46 deletions(-)
create mode 100644 arch/riscv/lib/strcmp_zbb.S
create mode 100644 arch/riscv/lib/strlen_zbb.S
create mode 100644 arch/riscv/lib/strncmp_zbb.S
create mode 100644 configs/ae350_rv32_falcon_defconfig
create mode 100644 configs/ae350_rv32_falcon_xip_defconfig
create mode 100644 configs/ae350_rv64_falcon_defconfig
create mode 100644 configs/ae350_rv64_falcon_xip_defconfig
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2023-10-05 8:10 Leo Liang
2023-10-05 17:46 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2023-10-05 8:10 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick, ycliang
Hi Tom,
The following changes since commit 65b9b3462bec2966911658836983819ab4e4823e:
Merge branch 'next_pinctrl_sync' of https://source.denx.de/u-boot/custodians/u-boot-sh (2023-10-02 15:19:02 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 7cfdacbe8020292845bd5eba63b576b8586c433c:
configs: sifive: enable poweroff command on Unmatched (2023-10-04 18:23:59 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18005
----------------------------------------------------------------
+ ae350: modify memory layout and target name
+ ae350: use generic RISC-V timer driver in S-mode
+ Support bootstage report for RISC-V
+ Support C extension exception command for RISC-V
+ Add Starfive timer support
----------------------------------------------------------------
Chanho Park (3):
riscv: bootstage: correct bootstage_report guard
riscv: timer: add timer_get_boot_us for BOOTSTAGE
timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE
Heinrich Schuchardt (4):
cmd/exception: support RISC-V compressed instruction
cmd/exception: test RISC-V 16 bit aligned instruction
riscv: enable CONFIG_DEBUG_UART by default
configs: sifive: enable poweroff command on Unmatched
Kuan Lim Lee (1):
timer: starfive: Add Starfive timer support
Randolph (2):
configs: andes: add vender prefix for target name
configs: andes: rearrange SPL mode memory layout
Yu Chien Peter Lin (1):
riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode
arch/riscv/Kconfig | 5 +-
arch/riscv/cpu/andesv5/Kconfig | 3 +-
arch/riscv/dts/Makefile | 2 +-
arch/riscv/lib/bootm.c | 2 +-
board/AndesTech/ae350/Kconfig | 2 +-
cmd/riscv/exception.c | 34 +++++++++++--
configs/ae350_rv32_defconfig | 3 +-
configs/ae350_rv32_spl_defconfig | 10 ++--
configs/ae350_rv32_spl_xip_defconfig | 7 +--
configs/ae350_rv32_xip_defconfig | 2 +-
configs/ae350_rv64_defconfig | 2 +-
configs/ae350_rv64_spl_defconfig | 11 +++--
configs/ae350_rv64_spl_xip_defconfig | 8 +--
configs/ae350_rv64_xip_defconfig | 2 +-
configs/sifive_unmatched_defconfig | 1 +
drivers/timer/Kconfig | 16 +++++-
drivers/timer/Makefile | 3 +-
drivers/timer/riscv_aclint_timer.c | 23 +++++++++
drivers/timer/riscv_timer.c | 22 +++++++++
drivers/timer/starfive-timer.c | 94 ++++++++++++++++++++++++++++++++++++
20 files changed, 223 insertions(+), 29 deletions(-)
create mode 100644 drivers/timer/starfive-timer.c
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2023-09-26 5:21 Leo Liang
2023-09-26 14:05 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2023-09-26 5:21 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick, ycliang
Hi Tom,
The following changes since commit 15155ab0a3d1f839509bcac620bfb38f950bead6:
Merge tag 'u-boot-imx-20230923' of https://source.denx.de/u-boot/custodians/u-boot-imx (2023-09-24 17:15:31 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 16dbe3d9d45527f67d479535a22dc4054ae93e99:
riscv: set fdtfile on VisionFive 2 (2023-09-26 10:43:02 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17879
However, this patch has landed in the "next" branch.
Could we cherry-pick this commit to have this patch on master branch ?
----------------------------------------------------------------
+ Fix VisionFive2 booting issue by providing the correct FDT.
----------------------------------------------------------------
Heinrich Schuchardt (1):
riscv: set fdtfile on VisionFive 2
arch/riscv/Kconfig | 1 +
board/starfive/visionfive2/starfive_visionfive2.c | 43 +++++++++++++++++++++++++++++++++++++++++--
2 files changed, 42 insertions(+), 2 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* Re: [PULL] u-boot-riscv/master
2023-09-26 5:21 Leo Liang
@ 2023-09-26 14:05 ` Tom Rini
0 siblings, 0 replies; 99+ messages in thread
From: Tom Rini @ 2023-09-26 14:05 UTC (permalink / raw)
To: Leo Liang; +Cc: u-boot, rick
[-- Attachment #1: Type: text/plain, Size: 840 bytes --]
On Tue, Sep 26, 2023 at 01:21:50PM +0800, Leo Liang wrote:
> Hi Tom,
>
> The following changes since commit 15155ab0a3d1f839509bcac620bfb38f950bead6:
>
> Merge tag 'u-boot-imx-20230923' of https://source.denx.de/u-boot/custodians/u-boot-imx (2023-09-24 17:15:31 -0400)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to 16dbe3d9d45527f67d479535a22dc4054ae93e99:
>
> riscv: set fdtfile on VisionFive 2 (2023-09-26 10:43:02 +0800)
>
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17879
>
> However, this patch has landed in the "next" branch.
> Could we cherry-pick this commit to have this patch on master branch ?
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
@ 2023-09-21 1:36 Leo Liang
2023-09-21 19:57 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2023-09-21 1:36 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick, ycliang
Hi Tom,
The following changes since commit b9b83a86f0e84e837191db120c279a9cc0e3434b:
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh (2023-09-17 09:25:42 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 43177705ab29ed1ccca970096de1ef3c6095e7e6:
board: visionfive2: Fixup memory size passed to kernel (2023-09-20 20:30:30 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17777
----------------------------------------------------------------
+ Fixup memory size passed to kernel
----------------------------------------------------------------
Shengyu Qu (2):
configs: visionfive2: Enable CONFIG_OF_BOARD_SETUP
board: visionfive2: Fixup memory size passed to kernel
board/starfive/visionfive2/starfive_visionfive2.c | 7 +++++++
configs/starfive_visionfive2_defconfig | 1 +
2 files changed, 8 insertions(+)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2023-09-05 3:30 Leo Liang
2023-09-05 18:43 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2023-09-05 3:30 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick, ycliang
Hi Tom,
The following changes since commit 493fd3363f6da6a784514657d689c7cda0f390d5:
nokia_rx51: Remove platform (2023-09-04 21:14:32 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to dfe08374943c0e898fcfaf7327f69e0fb56b7d23:
risc-v: implement DBCN based debug console (2023-09-05 10:53:55 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17650
----------------------------------------------------------------
+ Implement OpenSBI DBCN extension for early debug console
+ Fixes for VisionFive2 board
+ Fix timer missing
+ Fix L2 LIM issue
+ Enable PCIE auto enumeration to support USB and NVMe by default
+ Set eth0 mac address properly
+ Add __noreturn attribute to spl_invoke_opensbi
----------------------------------------------------------------
Chanho Park (1):
spl: add __noreturn attribute to spl_invoke_opensbi function
Heinrich Schuchardt (2):
risc-v: implement DBCN write byte
risc-v: implement DBCN based debug console
Seung-Woo Kim (1):
eeprom: starfive: set eth0 mac address properly
Shengyu Qu (6):
configs: starfive: Enable PCIE auto enum and NVME/USB stuff for Starfive Visionfive 2
doc: board: starfive: Add more info about supported driver
Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT
dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT
riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT
configs: starfive: Disable SYS_MALLOC_CLEAR_ON_INIT by default
Torsten Duwe (2):
riscv: allow riscv timer to be instantiated via device tree
riscv: jh7110: enable riscv,timer in the device tree
Kconfig | 11 +++++++++
arch/riscv/cpu/jh7110/Kconfig | 1 +
arch/riscv/dts/jh7110.dtsi | 9 +++++++
arch/riscv/include/asm/sbi.h | 1 +
arch/riscv/lib/sbi.c | 16 +++++++++++++
.../starfive/visionfive2/visionfive2-i2c-eeprom.c | 2 +-
common/dlmalloc.c | 6 ++---
common/spl/spl_opensbi.c | 7 +++---
configs/starfive_visionfive2_defconfig | 10 +++++++-
doc/board/starfive/visionfive2.rst | 2 ++
drivers/serial/Kconfig | 5 +++-
drivers/serial/serial_sbi.c | 20 ++++++++++++++++
drivers/timer/riscv_timer.c | 28 ++++++++++++++++++++--
include/spl.h | 2 +-
14 files changed, 108 insertions(+), 12 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2023-08-10 10:32 Leo Liang
2023-08-10 16:22 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2023-08-10 10:32 UTC (permalink / raw)
To: trini; +Cc: rick, ycliang, u-boot
Hi Tom,
The following changes since commit ec58228830a1f68e8e65099387cf12c5a91c9e72:
Merge tag 'x86-pull-20230809' of https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-09 13:17:34 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 47ed15125cccd98e041cdff3b6bbe675a2418ec2:
riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE (2023-08-10 10:58:55 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17276
----------------------------------------------------------------
+ Add USB host support on VisionFive2 board
+ Enable SPI flash support on VisionFive2 board
+ Enable Random Number Generator in RISC-V QEMU board
+ Display new SBI extension
+ Add SPL_ZERO_MEM_BEFORE_USE Kconfig for jh7110 L2 LIM (Loosely-Integrated Memory)
----------------------------------------------------------------
Heinrich Schuchardt (2):
riscv: qemu: imply CONFIG_DM_RNG
cmd/sbi: display new extensions
Minda Chen (4):
pci: plda: Get correct ECAM offset in multiple PCIe RC case
riscv: dts: starfive: Enable pcie0 dts node
riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE
configs: riscv: starfive: Add VF2 PCIe USB3 XHCI support
Shengyu Qu (4):
configs: starfive: Enable environment in SPI flash support
riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE
riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation
riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE
arch/riscv/Kconfig | 8 ++++++++
arch/riscv/cpu/jh7110/Kconfig | 2 ++
arch/riscv/cpu/jh7110/spl.c | 25 -------------------------
arch/riscv/cpu/start.S | 12 ++++++++++++
arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +-
arch/riscv/include/asm/sbi.h | 2 ++
board/emulation/qemu-riscv/Kconfig | 1 +
cmd/riscv/sbi.c | 4 ++++
common/init/board_init.c | 3 +++
configs/starfive_visionfive2_defconfig | 14 ++++++++++++++
drivers/pci/pcie_plda_common.c | 5 +++--
11 files changed, 50 insertions(+), 28 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2023-08-02 5:48 Leo Liang
2023-08-02 6:27 ` Bin Meng
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2023-08-02 5:48 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick, ycliang
Hi Tom,
The following changes since commit 7755b2200777f72dca87dd169138e95f011bbcb9:
Merge tag 'x86-pull-20230801' of https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 093bd0354e5b947b0bd634bf5ed4041ba075b57d:
acpi: Add missing RISC-V acpi_table header (2023-08-02 11:02:33 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17177
----------------------------------------------------------------
+ Fix compilation error for CI when enabling RTL8169 driver
+ Fix compilation error for pci_mmc.c by adding acpi_table header file
+ Support StarFive JH7110 PCIe driver
+ Enable PCI on Unmatched board
----------------------------------------------------------------
Heinrich Schuchardt (2):
riscv: sifive: initialize PCI on Unmatched
acpi: Add missing RISC-V acpi_table header
Mason Huo (3):
starfive: pci: Add StarFive JH7110 pcie driver
configs: starfive-jh7110: Add support for PCIe host driver
riscv: dts: starfive: Enable PCIe host controller
Minda Chen (5):
i2c: designware: Add Kconfig for designware_i2c_pci.c
net: rtl8169: Fix compile warning in rtl8169
net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V
net: rtl8169: Add one device ID 0x8161
configs: starfive-jh7110: Add CONFIG_RTL8169
arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 11 +++++++
arch/riscv/dts/jh7110.dtsi | 74 +++++++++++++++++++++++++++++++++++++++++
arch/riscv/include/asm/acpi_table.h | 11 +++++++
configs/sifive_unmatched_defconfig | 1 +
configs/starfive_visionfive2_defconfig | 8 +++++
drivers/i2c/Kconfig | 9 +++++
drivers/i2c/Makefile | 4 +--
drivers/net/rtl8169.c | 22 ++++++++-----
drivers/pci/Kconfig | 13 ++++++++
drivers/pci/Makefile | 2 ++
drivers/pci/pcie_plda_common.c | 116 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/pci/pcie_plda_common.h | 118 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/pci/pcie_starfive_jh7110.c | 317 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
13 files changed, 694 insertions(+), 12 deletions(-)
create mode 100644 arch/riscv/include/asm/acpi_table.h
create mode 100644 drivers/pci/pcie_plda_common.c
create mode 100644 drivers/pci/pcie_plda_common.h
create mode 100644 drivers/pci/pcie_starfive_jh7110.c
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* Re: [PULL] u-boot-riscv/master
2023-08-02 5:48 Leo Liang
@ 2023-08-02 6:27 ` Bin Meng
2023-08-02 9:31 ` Leo Liang
0 siblings, 1 reply; 99+ messages in thread
From: Bin Meng @ 2023-08-02 6:27 UTC (permalink / raw)
To: Leo Liang; +Cc: trini, u-boot, rick
Hi Leo,
On Wed, Aug 2, 2023 at 1:49 PM Leo Liang <ycliang@andestech.com> wrote:
>
> Hi Tom,
>
> The following changes since commit 7755b2200777f72dca87dd169138e95f011bbcb9:
>
> Merge tag 'x86-pull-20230801' of https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 -0400)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to 093bd0354e5b947b0bd634bf5ed4041ba075b57d:
>
> acpi: Add missing RISC-V acpi_table header (2023-08-02 11:02:33 +0800)
>
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17177
>
> ----------------------------------------------------------------
>
> + Fix compilation error for CI when enabling RTL8169 driver
> + Fix compilation error for pci_mmc.c by adding acpi_table header file
> + Support StarFive JH7110 PCIe driver
> + Enable PCI on Unmatched board
>
> ----------------------------------------------------------------
>
> Heinrich Schuchardt (2):
> riscv: sifive: initialize PCI on Unmatched
> acpi: Add missing RISC-V acpi_table header
>
> Mason Huo (3):
> starfive: pci: Add StarFive JH7110 pcie driver
> configs: starfive-jh7110: Add support for PCIe host driver
> riscv: dts: starfive: Enable PCIe host controller
>
> Minda Chen (5):
> i2c: designware: Add Kconfig for designware_i2c_pci.c
> net: rtl8169: Fix compile warning in rtl8169
> net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V
> net: rtl8169: Add one device ID 0x8161
> configs: starfive-jh7110: Add CONFIG_RTL8169
>
Looks the second half of this series is missed?
https://patchwork.ozlabs.org/project/uboot/list/?series=365237
Regards,
Bin
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PULL] u-boot-riscv/master
2023-08-02 6:27 ` Bin Meng
@ 2023-08-02 9:31 ` Leo Liang
2023-08-03 0:59 ` Minda Chen
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2023-08-02 9:31 UTC (permalink / raw)
To: Bin Meng; +Cc: trini, u-boot, rick
Hi Bin,
On Wed, Aug 02, 2023 at 02:27:29PM +0800, Bin Meng wrote:
> Hi Leo,
>
> On Wed, Aug 2, 2023 at 1:49 PM Leo Liang <ycliang@andestech.com> wrote:
> >
> > Hi Tom,
> >
> > The following changes since commit 7755b2200777f72dca87dd169138e95f011bbcb9:
> >
> > Merge tag 'x86-pull-20230801' of https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 -0400)
> >
> > are available in the Git repository at:
> >
> > https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> >
> > for you to fetch changes up to 093bd0354e5b947b0bd634bf5ed4041ba075b57d:
> >
> > acpi: Add missing RISC-V acpi_table header (2023-08-02 11:02:33 +0800)
> >
> > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17177
> >
> > ----------------------------------------------------------------
> >
> > + Fix compilation error for CI when enabling RTL8169 driver
> > + Fix compilation error for pci_mmc.c by adding acpi_table header file
> > + Support StarFive JH7110 PCIe driver
> > + Enable PCI on Unmatched board
> >
> > ----------------------------------------------------------------
> >
> > Heinrich Schuchardt (2):
> > riscv: sifive: initialize PCI on Unmatched
> > acpi: Add missing RISC-V acpi_table header
> >
> > Mason Huo (3):
> > starfive: pci: Add StarFive JH7110 pcie driver
> > configs: starfive-jh7110: Add support for PCIe host driver
> > riscv: dts: starfive: Enable PCIe host controller
> >
> > Minda Chen (5):
> > i2c: designware: Add Kconfig for designware_i2c_pci.c
> > net: rtl8169: Fix compile warning in rtl8169
> > net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V
> > net: rtl8169: Add one device ID 0x8161
> > configs: starfive-jh7110: Add CONFIG_RTL8169
> >
>
> Looks the second half of this series is missed?
> https://patchwork.ozlabs.org/project/uboot/list/?series=365237
>
> Regards,
> Bin
Thanks for the reminder!
I did omit this second half of the series by accident!
I will re-send the PR again ASAP!
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PULL] u-boot-riscv/master
2023-08-02 9:31 ` Leo Liang
@ 2023-08-03 0:59 ` Minda Chen
0 siblings, 0 replies; 99+ messages in thread
From: Minda Chen @ 2023-08-03 0:59 UTC (permalink / raw)
To: Leo Liang, Bin Meng; +Cc: trini, u-boot, rick
On 2023/8/2 17:31, Leo Liang wrote:
> Hi Bin,
>
> On Wed, Aug 02, 2023 at 02:27:29PM +0800, Bin Meng wrote:
>> Hi Leo,
>>
>> On Wed, Aug 2, 2023 at 1:49 PM Leo Liang <ycliang@andestech.com> wrote:
>> >
>> > Hi Tom,
>> >
>> > The following changes since commit 7755b2200777f72dca87dd169138e95f011bbcb9:
>> >
>> > Merge tag 'x86-pull-20230801' of https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 -0400)
>> >
>> > are available in the Git repository at:
>> >
>> > https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>> >
>> > for you to fetch changes up to 093bd0354e5b947b0bd634bf5ed4041ba075b57d:
>> >
>> > acpi: Add missing RISC-V acpi_table header (2023-08-02 11:02:33 +0800)
>> >
>> > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17177
>> >
>> > ----------------------------------------------------------------
>> >
>> > + Fix compilation error for CI when enabling RTL8169 driver
>> > + Fix compilation error for pci_mmc.c by adding acpi_table header file
>> > + Support StarFive JH7110 PCIe driver
>> > + Enable PCI on Unmatched board
>> >
>> > ----------------------------------------------------------------
>> >
>> > Heinrich Schuchardt (2):
>> > riscv: sifive: initialize PCI on Unmatched
>> > acpi: Add missing RISC-V acpi_table header
>> >
>> > Mason Huo (3):
>> > starfive: pci: Add StarFive JH7110 pcie driver
>> > configs: starfive-jh7110: Add support for PCIe host driver
>> > riscv: dts: starfive: Enable PCIe host controller
>> >
>> > Minda Chen (5):
>> > i2c: designware: Add Kconfig for designware_i2c_pci.c
>> > net: rtl8169: Fix compile warning in rtl8169
>> > net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V
>> > net: rtl8169: Add one device ID 0x8161
>> > configs: starfive-jh7110: Add CONFIG_RTL8169
>> >
>>
>> Looks the second half of this series is missed?
>> https://patchwork.ozlabs.org/project/uboot/list/?series=365237
>>
>> Regards,
>> Bin
>
> Thanks for the reminder!
> I did omit this second half of the series by accident!
> I will re-send the PR again ASAP!
>
> Best regards,
> Leo
Hi Leo and Bin
Thanks!
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
@ 2023-07-24 8:01 Leo Liang
2023-07-24 16:41 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2023-07-24 8:01 UTC (permalink / raw)
To: trini; +Cc: u-boot, ycliang, rick
Hi Tom,
The following changes since commit 247aa5a191159ea7e03bf1918e22fbbb784cd410:
Merge branch '2023-07-21-assorted-TI-platform-updates' (2023-07-21 19:33:05 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 6aabe229f8440c4960b904baf3aa33f692eea9a1:
riscv: define a cache line size for the generic CPU (2023-07-24 13:22:24 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17015
----------------------------------------------------------------
- Set up per-hart stack before any function call
- Sync visionfive2 board DTS with Linux
- Define cache line size for USB 3.0 driver for RISC-V CPU
----------------------------------------------------------------
Bo Gan (1):
riscv: setup per-hart stack earlier
Chanho Park (2):
configs: visionfive2: add a trailing space to prompt
doc: visionfive2: apply a trailing space to the prompt
Heinrich Schuchardt (1):
riscv: define a cache line size for the generic CPU
Xingyu Wu (5):
clk: starfive: jh7110: Separate the PLL driver
riscv: dts: jh7110: Add PLL clock controller node
riscv: dts: jh7110: Add clock source from PLL
dt-bindings: clock: jh7110: Modify clock id to be same with Linux
clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversion
arch/riscv/cpu/generic/Kconfig | 1 +
arch/riscv/cpu/start.S | 37 ++++++++++++++--------
arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 6 ++--
arch/riscv/dts/jh7110-u-boot.dtsi | 1 -
arch/riscv/dts/jh7110.dtsi | 16 ++++++++--
configs/starfive_visionfive2_defconfig | 2 +-
doc/board/starfive/visionfive2.rst | 18 +++++------
drivers/clk/starfive/clk-jh7110-pll.c | 103 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++--
drivers/clk/starfive/clk-jh7110.c | 306 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------------------------------------------------------------
drivers/clk/starfive/clk.h | 58 ++++++++-------------------------
include/dt-bindings/clock/starfive,jh7110-crg.h | 101 +++++++++++++++++++++++++++++-----------------------------
11 files changed, 400 insertions(+), 249 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2023-07-12 6:58 Leo Liang
2023-07-12 19:43 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2023-07-12 6:58 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick, ycliang
Hi Tom,
The following changes since commit 8e21064cb3452950b09301baec06d86e37342471:
Merge tag 'efi-2023-07-rc7' of https://source.denx.de/u-boot/custodians/u-boot-efi (2023-07-11 13:27:32 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git master
for you to fetch changes up to 478fedfda42ea2a444991de1696fa0adc8bb16d4:
doc: t-head: lpi4a: document Lichee PI 4A board (2023-07-12 13:21:41 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/16856
----------------------------------------------------------------
- Add ethernet driver for StarFive JH7110 SoC
- Add ACLINT mtimer and mswi devices support
- Add Lichee PI 4A board
----------------------------------------------------------------
Bin Meng (3):
riscv: timer: Update the sifive clint timer driver to support aclint
riscv: clint: Update the sifive clint ipi driver to support aclint
riscv: Rename SiFive CLINT to RISC-V ALINT
Yanhong Wang (11):
net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
net: dwc_eth_qos: Add StarFive ethernet driver glue layer
riscv: dts: jh7110: Add ethernet device tree nodes
riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B
doc: board: starfive: Reword the make defconfig information
configs: starfive: Enable ethernet configuration for StarFive VisionFive2
eeprom: starfive: Enable ID EEPROM configuration
riscv: dts: starfive: Add support eeprom device tree node
configs: starfive: Enable ID EEPROM configuration
ram: starfive: Read memory size information from EEPROM
board: starfive: Dynamic configuration of DT for 1.2A and 1.3B
Yixun Lan (4):
riscv: t-head: licheepi4a: initial support added
riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board
configs: th1520_lpi4a_defconfig: Add initial config
doc: t-head: lpi4a: document Lichee PI 4A board
MAINTAINERS | 2 +-
arch/riscv/Kconfig | 17 +++--
arch/riscv/cpu/fu540/Kconfig | 2 +-
arch/riscv/cpu/fu740/Kconfig | 2 +-
arch/riscv/cpu/generic/Kconfig | 4 +-
arch/riscv/cpu/jh7110/Kconfig | 2 +-
arch/riscv/cpu/jh7110/spl.c | 32 ++++++++-
arch/riscv/dts/Makefile | 4 +-
arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi => jh7110-starfive-visionfive-2-u-boot.dtsi} | 39 ++++++++++-
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts | 12 ----
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 -------------------
arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts => jh7110-starfive-visionfive-2.dts} | 3 +-
arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 40 +++++++++++
arch/riscv/dts/jh7110.dtsi | 69 +++++++++++++++++++
arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 +++++++++
arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 +++++++++
arch/riscv/dts/th1520.dtsi | 406 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/riscv/include/asm/arch-jh7110/eeprom.h | 13 ++++
arch/riscv/include/asm/global_data.h | 4 +-
arch/riscv/include/asm/syscon.h | 2 +-
arch/riscv/lib/Makefile | 2 +-
arch/riscv/lib/{sifive_clint.c => aclint_ipi.c} | 31 +++++++--
board/openpiton/riscv64/Kconfig | 2 +-
board/sipeed/maix/Kconfig | 2 +-
board/starfive/visionfive2/Makefile | 1 +
board/starfive/visionfive2/spl.c | 157 ++++++++++++++++++++++++++++++++++++++++++
board/starfive/visionfive2/starfive_visionfive2.c | 13 ++++
board/starfive/visionfive2/visionfive2-i2c-eeprom.c | 561 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
board/thead/th1520_lpi4a/Kconfig | 42 ++++++++++++
board/thead/th1520_lpi4a/MAINTAINERS | 7 ++
board/thead/th1520_lpi4a/Makefile | 5 ++
board/thead/th1520_lpi4a/board.c | 15 ++++
configs/starfive_visionfive2_defconfig | 32 ++++++++-
configs/th1520_lpi4a_defconfig | 82 ++++++++++++++++++++++
doc/board/index.rst | 1 +
doc/board/starfive/visionfive2.rst | 6 +-
doc/board/thead/index.rst | 9 +++
doc/board/thead/lpi4a.rst | 129 +++++++++++++++++++++++++++++++++++
drivers/net/Kconfig | 7 ++
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 ++
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c | 249 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/net/phy/Kconfig | 6 ++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/motorcomm.c | 437 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/ram/starfive/starfive_ddr.c | 2 -
drivers/timer/Makefile | 2 +-
drivers/timer/riscv_aclint_timer.c | 74 ++++++++++++++++++++
drivers/timer/sifive_clint_timer.c | 68 ------------------
include/configs/qemu-riscv.h | 2 +-
include/configs/sifive-unleashed.h | 2 +-
include/configs/starfive-visionfive2.h | 1 +
include/configs/th1520_lpi4a.h | 22 ++++++
54 files changed, 2578 insertions(+), 188 deletions(-)
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi => jh7110-starfive-visionfive-2-u-boot.dtsi} (58%)
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts => jh7110-starfive-visionfive-2.dts} (65%)
create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi
create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts
create mode 100644 arch/riscv/dts/th1520.dtsi
create mode 100644 arch/riscv/include/asm/arch-jh7110/eeprom.h
rename arch/riscv/lib/{sifive_clint.c => aclint_ipi.c} (53%)
create mode 100644 board/starfive/visionfive2/visionfive2-i2c-eeprom.c
create mode 100644 board/thead/th1520_lpi4a/Kconfig
create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS
create mode 100644 board/thead/th1520_lpi4a/Makefile
create mode 100644 board/thead/th1520_lpi4a/board.c
create mode 100644 configs/th1520_lpi4a_defconfig
create mode 100644 doc/board/thead/index.rst
create mode 100644 doc/board/thead/lpi4a.rst
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
create mode 100644 drivers/net/phy/motorcomm.c
create mode 100644 drivers/timer/riscv_aclint_timer.c
delete mode 100644 drivers/timer/sifive_clint_timer.c
create mode 100644 include/configs/th1520_lpi4a.h
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2023-04-21 0:41 Leo Liang
2023-04-23 16:15 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2023-04-21 0:41 UTC (permalink / raw)
To: trini; +Cc: rick, ycliang, u-boot
Hi Tom,
The following changes since commit 5db4972a5bbdbf9e3af48ffc9bc4fec73b7b6a79:
Merge tag 'u-boot-nand-20230417' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash (2023-04-17 10:47:33 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 04d16be55404ee07134b4171dea37eff9ad8fa5a:
riscv: Support CONFIG_REMAKE_ELF (2023-04-20 20:45:08 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/16065
----------------------------------------------------------------
* Add StarFive VisionFive v2 Board support
* Support CONFIG_REMAKE_ELF
* Code cleanups for RISC-V architecture
----------------------------------------------------------------
Bin Meng (11):
riscv: Correct a comment in io.h
riscv: Enforce DWARF4 output
riscv: Optimize source end address calculation in start.S
riscv: Optimize loading relocation type
tools: prelink-riscv: Cosmetic style fixes
tools: prelink-riscv: Unmap the ELF image when done
makefile: riscv: Drop useless argument of prelink-riscv
riscv: Change to use positive offset to access relocation entries
riscv: Avoid updating the link register
riscv: spl: Remove relocation sections
riscv: Update alignment for some sections in linker scripts
Jianlong Huang (1):
dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions
Kuan Lim Lee (1):
pinctrl: starfive: Add StarFive JH7110 driver
Samuel Holland (1):
riscv: Support CONFIG_REMAKE_ELF
Yanhong Wang (15):
riscv: cpu: jh7110: Add support for jh7110 SoC
cache: starfive: Add StarFive JH7110 support
dt-bindings: reset: Add StarFive JH7110 reset definitions
reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC
dt-bindings: clock: Add StarFive JH7110 clock definitions
clk: starfive: Add StarFive JH7110 clock driver
ram: starfive: add ddr driver
board: starfive: add StarFive VisionFive v2 board support
riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC
board: starfive: Add Kconfig for StarFive VisionFive v2 Board
board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig
riscv: dts: jh7110: Add initial StarFive JH7110 device tree
riscv: dts: jh7110: Add initial u-boot device tree
riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree
configs: starfive: add starfive_visionfive2_defconfig
Makefile | 2 +-
arch/riscv/Kconfig | 5 +
arch/riscv/config.mk | 5 +-
arch/riscv/cpu/jh7110/Kconfig | 28 ++
arch/riscv/cpu/jh7110/Makefile | 10 +
arch/riscv/cpu/jh7110/cpu.c | 23 ++
arch/riscv/cpu/jh7110/dram.c | 38 +++
arch/riscv/cpu/jh7110/spl.c | 64 ++++
arch/riscv/cpu/start.S | 28 +-
arch/riscv/cpu/u-boot-spl.lds | 27 +-
arch/riscv/cpu/u-boot.lds | 6 +-
arch/riscv/dts/Makefile | 3 +-
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi | 69 ++++
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts | 12 +
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 ++++
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts | 12 +
arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 319 +++++++++++++++++++
arch/riscv/dts/jh7110-u-boot.dtsi | 99 ++++++
arch/riscv/dts/jh7110.dtsi | 573 +++++++++++++++++++++++++++++++++
arch/riscv/include/asm/arch-jh7110/regs.h | 19 ++
arch/riscv/include/asm/arch-jh7110/spl.h | 12 +
arch/riscv/include/asm/io.h | 2 +-
board/starfive/visionfive2/Kconfig | 53 ++++
board/starfive/visionfive2/MAINTAINERS | 7 +
board/starfive/visionfive2/Makefile | 7 +
board/starfive/visionfive2/spl.c | 87 +++++
board/starfive/visionfive2/starfive_visionfive2.c | 40 +++
configs/starfive_visionfive2_defconfig | 79 +++++
doc/board/index.rst | 1 +
doc/board/starfive/index.rst | 9 +
doc/board/starfive/visionfive2.rst | 492 +++++++++++++++++++++++++++++
drivers/cache/cache-sifive-ccache.c | 1 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/starfive/Kconfig | 17 +
drivers/clk/starfive/Makefile | 4 +
drivers/clk/starfive/clk-jh7110-pll.c | 321 +++++++++++++++++++
drivers/clk/starfive/clk-jh7110.c | 603 +++++++++++++++++++++++++++++++++++
drivers/clk/starfive/clk.h | 57 ++++
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/starfive/Kconfig | 28 ++
drivers/pinctrl/starfive/Makefile | 6 +
drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 113 +++++++
drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 399 +++++++++++++++++++++++
drivers/pinctrl/starfive/pinctrl-starfive.c | 398 +++++++++++++++++++++++
drivers/pinctrl/starfive/pinctrl-starfive.h | 55 ++++
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile | 4 +-
drivers/ram/starfive/Kconfig | 5 +
drivers/ram/starfive/Makefile | 11 +
drivers/ram/starfive/ddrcsr_boot.c | 339 ++++++++++++++++++++
drivers/ram/starfive/ddrphy_start.c | 279 ++++++++++++++++
drivers/ram/starfive/ddrphy_train.c | 383 ++++++++++++++++++++++
drivers/ram/starfive/ddrphy_utils.c | 1955 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/ram/starfive/starfive_ddr.c | 161 ++++++++++
drivers/ram/starfive/starfive_ddr.h | 65 ++++
drivers/reset/Kconfig | 16 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-jh7110.c | 158 ++++++++++
include/configs/starfive-visionfive2.h | 49 +++
include/dt-bindings/clock/starfive,jh7110-crg.h | 257 +++++++++++++++
include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h | 427 +++++++++++++++++++++++++
include/dt-bindings/reset/starfive,jh7110-crg.h | 183 +++++++++++
tools/prelink-riscv.c | 2 +
tools/prelink-riscv.inc | 12 +-
66 files changed, 8456 insertions(+), 58 deletions(-)
create mode 100644 arch/riscv/cpu/jh7110/Kconfig
create mode 100644 arch/riscv/cpu/jh7110/Makefile
create mode 100644 arch/riscv/cpu/jh7110/cpu.c
create mode 100644 arch/riscv/cpu/jh7110/dram.c
create mode 100644 arch/riscv/cpu/jh7110/spl.c
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi
create mode 100644 arch/riscv/dts/jh7110.dtsi
create mode 100644 arch/riscv/include/asm/arch-jh7110/regs.h
create mode 100644 arch/riscv/include/asm/arch-jh7110/spl.h
create mode 100644 board/starfive/visionfive2/Kconfig
create mode 100644 board/starfive/visionfive2/MAINTAINERS
create mode 100644 board/starfive/visionfive2/Makefile
create mode 100644 board/starfive/visionfive2/spl.c
create mode 100644 board/starfive/visionfive2/starfive_visionfive2.c
create mode 100644 configs/starfive_visionfive2_defconfig
create mode 100644 doc/board/starfive/index.rst
create mode 100644 doc/board/starfive/visionfive2.rst
create mode 100644 drivers/clk/starfive/Kconfig
create mode 100644 drivers/clk/starfive/Makefile
create mode 100644 drivers/clk/starfive/clk-jh7110-pll.c
create mode 100644 drivers/clk/starfive/clk-jh7110.c
create mode 100644 drivers/clk/starfive/clk.h
create mode 100644 drivers/pinctrl/starfive/Kconfig
create mode 100644 drivers/pinctrl/starfive/Makefile
create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h
create mode 100644 drivers/ram/starfive/Kconfig
create mode 100644 drivers/ram/starfive/Makefile
create mode 100644 drivers/ram/starfive/ddrcsr_boot.c
create mode 100644 drivers/ram/starfive/ddrphy_start.c
create mode 100644 drivers/ram/starfive/ddrphy_train.c
create mode 100644 drivers/ram/starfive/ddrphy_utils.c
create mode 100644 drivers/ram/starfive/starfive_ddr.c
create mode 100644 drivers/ram/starfive/starfive_ddr.h
create mode 100644 drivers/reset/reset-jh7110.c
create mode 100644 include/configs/starfive-visionfive2.h
create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h
create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2023-02-17 12:12 Leo Liang
2023-02-17 15:01 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2023-02-17 12:12 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick, ycliang
Hi Tom,
The following changes since commit faac9dee8e0629326dc122f4624fc4897e3f38b0:
Prepare v2023.04-rc2 (2023-02-13 18:39:15 -0500)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 7574b6476afc1fd76816be6567458f6ca4f44234:
riscv: binman: Add help message for missing blobs (2023-02-17 19:07:48 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15225
----------------------------------------------------------------
- binman: Add help message if opensbi is absent when building u-boot SPL
- AndesTech: rename cpu and board name to 'andesv5' and 'ae350'
- Clean up cache operation for Andes ae350 platform
----------------------------------------------------------------
Leo Yu-Chi Liang (3):
riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"
riscv: Rename Andes cpu and board names
riscv: ae350: Adjust the memory layout of ae350
Rick Chen (1):
riscv: binman: Add help message for missing blobs
Yu Chien Peter Lin (10):
riscv: global_data.h: Correct the comment for PLICSW
board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()
driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform
riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()
riscv: ae350: dts: Update L2 cache compatible string
riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL
configs: ae350: Enable v5l2 cache for AE350 platforms in SPL
configs: ae350: Increase maximum retry count for AE350 platforms
configs: ae350: Display CPU and board info for AE350 platforms
driver: cache-v5l2: Fix type casting warning on RV32
arch/riscv/Kconfig | 8 ++++----
arch/riscv/cpu/{ax25 => andesv5}/Kconfig | 11 +----------
arch/riscv/cpu/{ax25 => andesv5}/Makefile | 0
arch/riscv/cpu/andesv5/cache.c | 130 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/riscv/cpu/andesv5/cpu.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++
arch/riscv/cpu/{ax25 => andesv5}/spl.c | 0
arch/riscv/cpu/ax25/cache.c | 172 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------
arch/riscv/cpu/ax25/cpu.c | 75 ------------------------------------------------------------------------
arch/riscv/dts/Makefile | 2 +-
arch/riscv/dts/ae350_32.dts | 2 +-
arch/riscv/dts/ae350_64.dts | 2 +-
arch/riscv/dts/binman.dtsi | 1 +
arch/riscv/include/asm/arch-andes/csr.h | 31 ++++++++++++++++++++++++++++++
arch/riscv/include/asm/global_data.h | 2 +-
board/AndesTech/{ax25-ae350 => ae350}/Kconfig | 8 ++++----
board/AndesTech/{ax25-ae350 => ae350}/MAINTAINERS | 6 +++---
board/AndesTech/{ax25-ae350 => ae350}/Makefile | 2 +-
board/AndesTech/{ax25-ae350/ax25-ae350.c => ae350/ae350.c} | 17 +++++++++--------
configs/ae350_rv32_defconfig | 5 ++++-
configs/ae350_rv32_spl_defconfig | 13 +++++++++----
configs/ae350_rv32_spl_xip_defconfig | 13 +++++++++----
configs/ae350_rv32_xip_defconfig | 5 ++++-
configs/ae350_rv64_defconfig | 5 ++++-
configs/ae350_rv64_spl_defconfig | 13 +++++++++----
configs/ae350_rv64_spl_xip_defconfig | 13 +++++++++----
configs/ae350_rv64_xip_defconfig | 5 ++++-
doc/board/AndesTech/{ax25-ae350.rst => ae350.rst} | 16 ++++++++--------
doc/board/AndesTech/index.rst | 2 +-
drivers/cache/Kconfig | 1 -
drivers/cache/cache-v5l2.c | 36 +++++++++++++++++++++++++----------
include/configs/{ax25-ae350.h => ae350.h} | 0
tools/binman/missing-blob-help | 6 ++++++
32 files changed, 331 insertions(+), 321 deletions(-)
rename arch/riscv/cpu/{ax25 => andesv5}/Kconfig (66%)
rename arch/riscv/cpu/{ax25 => andesv5}/Makefile (100%)
create mode 100644 arch/riscv/cpu/andesv5/cache.c
create mode 100644 arch/riscv/cpu/andesv5/cpu.c
rename arch/riscv/cpu/{ax25 => andesv5}/spl.c (100%)
delete mode 100644 arch/riscv/cpu/ax25/cache.c
delete mode 100644 arch/riscv/cpu/ax25/cpu.c
create mode 100644 arch/riscv/include/asm/arch-andes/csr.h
rename board/AndesTech/{ax25-ae350 => ae350}/Kconfig (88%)
rename board/AndesTech/{ax25-ae350 => ae350}/MAINTAINERS (80%)
rename board/AndesTech/{ax25-ae350 => ae350}/Makefile (87%)
rename board/AndesTech/{ax25-ae350/ax25-ae350.c => ae350/ae350.c} (95%)
rename doc/board/AndesTech/{ax25-ae350.rst => ae350.rst} (98%)
rename include/configs/{ax25-ae350.h => ae350.h} (100%)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* Re: [PULL] u-boot-riscv/master
2023-02-17 12:12 Leo Liang
@ 2023-02-17 15:01 ` Tom Rini
2023-02-19 6:09 ` Leo Liang
0 siblings, 1 reply; 99+ messages in thread
From: Tom Rini @ 2023-02-17 15:01 UTC (permalink / raw)
To: Leo Liang; +Cc: u-boot, rick
[-- Attachment #1: Type: text/plain, Size: 794 bytes --]
On Fri, Feb 17, 2023 at 12:12:18PM +0000, Leo Liang wrote:
> Hi Tom,
>
> The following changes since commit faac9dee8e0629326dc122f4624fc4897e3f38b0:
>
> Prepare v2023.04-rc2 (2023-02-13 18:39:15 -0500)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to 7574b6476afc1fd76816be6567458f6ca4f44234:
>
> riscv: binman: Add help message for missing blobs (2023-02-17 19:07:48 +0800)
>
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15225
>
I've taken this to u-boot/master, but for the rest of the cycle please
make sure any changes for master are clearly bug fixes, and otherwise
apply to next instead. Thanks!
--
Tom
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PULL] u-boot-riscv/master
2023-02-17 15:01 ` Tom Rini
@ 2023-02-19 6:09 ` Leo Liang
0 siblings, 0 replies; 99+ messages in thread
From: Leo Liang @ 2023-02-19 6:09 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot, rick
On Fri, Feb 17, 2023 at 10:01:54AM -0500, Tom Rini wrote:
> On Fri, Feb 17, 2023 at 12:12:18PM +0000, Leo Liang wrote:
>
> > Hi Tom,
> >
> > The following changes since commit faac9dee8e0629326dc122f4624fc4897e3f38b0:
> >
> > Prepare v2023.04-rc2 (2023-02-13 18:39:15 -0500)
> >
> > are available in the Git repository at:
> >
> > https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> >
> > for you to fetch changes up to 7574b6476afc1fd76816be6567458f6ca4f44234:
> >
> > riscv: binman: Add help message for missing blobs (2023-02-17 19:07:48 +0800)
> >
> > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15225
> >
>
> I've taken this to u-boot/master, but for the rest of the cycle please
> make sure any changes for master are clearly bug fixes, and otherwise
> apply to next instead. Thanks!
Hi Tom,
Understood!
Thanks for merging this!
Best regards,
Leo
>
> --
> Tom
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
@ 2023-02-02 6:30 Leo Liang
2023-02-02 19:18 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2023-02-02 6:30 UTC (permalink / raw)
To: trini; +Cc: ycliang, rick, u-boot
Hi Tom,
The following changes since commit 73a3f5139182a0389d505bf29b0ad4bc29424cf8:
Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-01-31 18:28:07 -0500)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 2b0af9feb594b68a75e4f111bde7f55ddb14995d:
board: sifive: unmatched: enable booting on a second NVME device (2023-02-01 16:17:59 +0800)
CI result show no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15011
----------------------------------------------------------------
+ riscv lib:
+ optimize memcpy for "dst == src" case
+ check if u-mode exists before writing mcounteren register
+ unmatched board config: enable second NVME device on unmatched board
+ ae350 board:
+ Adjust memory layout and some CSR setting
----------------------------------------------------------------
Aurelien Jarno (1):
board: sifive: unmatched: enable booting on a second NVME device
Nikita Shubin (1):
riscv: cpu: check U-Mode before counteren write
Rick Chen (4):
riscv: ae350: Enable CCTL_SUEN
riscv: ax25: bypass malloc when spl fit boots from ram
riscv: memcpy: check src and dst before copy
riscv: ae350: support OpenSBI 1.0+ which enable FW_PIC
arch/riscv/cpu/ax25/Makefile | 1 +
arch/riscv/cpu/ax25/cpu.c | 18 +++++++++++-------
arch/riscv/cpu/ax25/spl.c | 27 +++++++++++++++++++++++++++
arch/riscv/cpu/cpu.c | 16 ++++++++--------
arch/riscv/lib/memcpy.S | 2 ++
board/AndesTech/ax25-ae350/Kconfig | 2 +-
include/configs/sifive-unmatched.h | 1 +
7 files changed, 51 insertions(+), 16 deletions(-)
create mode 100644 arch/riscv/cpu/ax25/spl.c
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2022-12-08 11:23 Leo Liang
2022-12-08 16:24 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2022-12-08 11:23 UTC (permalink / raw)
To: trini; +Cc: u-boot, ycliang, rick
Hi Tom,
The following changes since commit 14f2d087a3d6347ba0ff7a7e9aaff6955e53e7a8:
Merge tag 'sound-2023-01-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi (2022-12-06 10:07:01 -0500)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 57b9900cd59ad492f74390515901788459f1e8aa:
riscv: use imply instead of select for SPL_SEPARATE_BSS (2022-12-08 15:50:22 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14369
----------------------------------------------------------------
- Kautuk's semihosting patch:
move semihosting library from arm directory to common place and add RISC-V support
- Zong's Kconfig patch:
use "imply" instead of "select" to allow user to decide if SPL_SEPARATE_BSS should be selected
----------------------------------------------------------------
Kautuk Consul (3):
lib: Add common semihosting library
arch/riscv: add semihosting support for RISC-V
common/spl/Kconfig: add dependency on SPL_SEMIHOSTING for SPL payload
Zong Li (1):
riscv: use imply instead of select for SPL_SEPARATE_BSS
arch/Kconfig | 2 +-
arch/arm/Kconfig | 46 ----------------------------------------------
arch/arm/lib/semihosting.c | 181 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
arch/riscv/include/asm/spl.h | 1 +
arch/riscv/lib/Makefile | 2 ++
arch/riscv/lib/interrupts.c | 25 +++++++++++++++++++++++++
arch/riscv/lib/semihosting.c | 24 ++++++++++++++++++++++++
common/spl/Kconfig | 2 +-
include/semihosting.h | 11 +++++++++++
lib/Kconfig | 47 +++++++++++++++++++++++++++++++++++++++++++++++
lib/Makefile | 2 ++
lib/semihosting.c | 186 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
12 files changed, 301 insertions(+), 228 deletions(-)
create mode 100644 arch/riscv/lib/semihosting.c
create mode 100644 lib/semihosting.c
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2022-11-16 6:16 Leo Liang
2022-11-16 18:01 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2022-11-16 6:16 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick, ycliang
Hi Tom,
The following changes since commit c4ee4fe92e9be120be6d12718273dec6b63cc7d9:
Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2022-11-14 09:33:36 -0500)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 591e0f878083925e7afff82e1774ba295a7767aa:
riscv: enable reset via SBI on PolarFire Icicle Kit (2022-11-15 15:37:17 +0800)
CI shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14105
----------------------------------------------------------------
- Fix and improve microchip's clock driver to allow sync'ing DTS with linux
- Improve the help message in "SBI_V02" Kconfig
- Improve DTS property "isa-string" parsing rule
----------------------------------------------------------------
Conor Dooley (6):
dt-bindings: clk: add missing clk ids for microchip mpfs
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()
clk: microchip: mpfs: fix reference clock handling
clk: microchip: mpfs: fix periph clk parentage
clk: microchip: mpfs: fix criticality of peripheral clocks
riscv: dts: fix the mpfs's reference clock frequency
Heinrich Schuchardt (2):
riscv: clarify meaning of CONFIG_SBI_V02
riscv: enable reset via SBI on PolarFire Icicle Kit
Yu Chien Peter Lin (1):
riscv: Fix detecting FPU support in standard extension
arch/riscv/Kconfig | 14 +++++++-------
arch/riscv/cpu/cpu.c | 14 +++++++++++---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 4 ++++
arch/riscv/dts/microchip-mpfs.dtsi | 14 ++++++--------
configs/microchip_mpfs_icicle_defconfig | 2 ++
drivers/clk/microchip/Makefile | 2 +-
drivers/clk/microchip/mpfs_clk.c | 37 +++++++++++++++++++++++++++----------
drivers/clk/microchip/mpfs_clk.h | 20 ++++++++++++--------
drivers/clk/microchip/mpfs_clk_cfg.c | 7 +++----
drivers/clk/microchip/mpfs_clk_msspll.c | 119 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/microchip/mpfs_clk_periph.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------------------------------
include/dt-bindings/clock/microchip-mpfs-clock.h | 3 +++
12 files changed, 249 insertions(+), 83 deletions(-)
create mode 100644 drivers/clk/microchip/mpfs_clk_msspll.c
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2022-11-03 7:04 Leo Liang
2022-11-03 16:57 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2022-11-03 7:04 UTC (permalink / raw)
To: trini; +Cc: ycliang, rick, u-boot
Hi Tom,
The following changes since commit c8d9ff634fc429db5acf2f5386ea937f0fef1ae7:
Merge branch '2022-10-31-FWU-add-FWU-multi-bank-update-feature-support' (2022-11-01 09:32:21 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 7321bad25f18684b53cff4346543fb2da2a2c0d0:
riscv: Update Microchip MPFS Icicle Kit support (2022-11-03 13:27:56 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13999
----------------------------------------------------------------
Padmarao Begari (4):
riscv: dts: Update memory configuration
riscv: dts: Add QSPI NAND device node
spi: Add Microchip PolarFire SoC QSPI driver
riscv: Update Microchip MPFS Icicle Kit support
Yu Chien Peter Lin (1):
riscv: Rename Andes PLIC to PLICSW
arch/riscv/Kconfig | 6 +--
arch/riscv/cpu/ax25/Kconfig | 2 +-
arch/riscv/dts/ae350-u-boot.dtsi | 2 +-
arch/riscv/dts/ae350_32.dts | 6 +--
arch/riscv/dts/ae350_64.dts | 6 +--
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 91 ++++++++++++--------------------
arch/riscv/include/asm/global_data.h | 4 +-
arch/riscv/include/asm/syscon.h | 2 +-
arch/riscv/lib/Makefile | 2 +-
arch/riscv/lib/{andes_plic.c => andes_plicsw.c} | 26 +++++-----
board/microchip/mpfs_icicle/Kconfig | 7 +++
configs/microchip_mpfs_icicle_defconfig | 1 +
drivers/spi/Kconfig | 6 +++
drivers/spi/Makefile | 1 +
drivers/spi/microchip_coreqspi.c | 505 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/timer/andes_plmt_timer.c | 2 +-
16 files changed, 582 insertions(+), 87 deletions(-)
rename arch/riscv/lib/{andes_plic.c => andes_plicsw.c} (76%)
create mode 100644 drivers/spi/microchip_coreqspi.c
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* Re: [PULL] u-boot-riscv/master
2022-11-03 7:04 Leo Liang
@ 2022-11-03 16:57 ` Tom Rini
2022-11-04 0:28 ` Leo Liang
0 siblings, 1 reply; 99+ messages in thread
From: Tom Rini @ 2022-11-03 16:57 UTC (permalink / raw)
To: Leo Liang; +Cc: rick, u-boot
[-- Attachment #1: Type: text/plain, Size: 798 bytes --]
On Thu, Nov 03, 2022 at 07:04:33AM +0000, Leo Liang wrote:
> Hi Tom,
>
> The following changes since commit c8d9ff634fc429db5acf2f5386ea937f0fef1ae7:
>
> Merge branch '2022-10-31-FWU-add-FWU-multi-bank-update-feature-support' (2022-11-01 09:32:21 -0400)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
Can you please start including a few line summary of the changes in your
pull requests?
>
> for you to fetch changes up to 7321bad25f18684b53cff4346543fb2da2a2c0d0:
>
> riscv: Update Microchip MPFS Icicle Kit support (2022-11-03 13:27:56 +0800)
>
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13999
>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PULL] u-boot-riscv/master
2022-11-03 16:57 ` Tom Rini
@ 2022-11-04 0:28 ` Leo Liang
0 siblings, 0 replies; 99+ messages in thread
From: Leo Liang @ 2022-11-04 0:28 UTC (permalink / raw)
To: Tom Rini; +Cc: rick, u-boot, ycliang
Hi Tom,
On Thu, Nov 03, 2022 at 12:57:05PM -0400, Tom Rini wrote:
> On Thu, Nov 03, 2022 at 07:04:33AM +0000, Leo Liang wrote:
>
> > Hi Tom,
> >
> > The following changes since commit c8d9ff634fc429db5acf2f5386ea937f0fef1ae7:
> >
> > Merge branch '2022-10-31-FWU-add-FWU-multi-bank-update-feature-support' (2022-11-01 09:32:21 -0400)
> >
> > are available in the Git repository at:
> >
> > https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>
> Can you please start including a few line summary of the changes in your
> pull requests?
>
Sorry for not including any summary before,
will for sure summarize the PRs in the pull requests.
> >
> > for you to fetch changes up to 7321bad25f18684b53cff4346543fb2da2a2c0d0:
> >
> > riscv: Update Microchip MPFS Icicle Kit support (2022-11-03 13:27:56 +0800)
> >
> > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13999
> >
>
> Applied to u-boot/master, thanks!
>
> --
> Tom
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
@ 2022-10-20 12:36 Leo Liang
2022-10-20 19:03 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2022-10-20 12:36 UTC (permalink / raw)
To: trini; +Cc: u-boot, ycliang, rick
Hi Tom,
The following changes since commit 3724ddf157aab3bd009c1da234b9a1af1621b544:
Merge branch '2022-10-18-TI-platform-updates' (2022-10-18 18:13:39 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to b3b44c674a473bdd3d53cf5196fae897107af619:
riscv: ae350: Check firmware_fdt_addr header (2022-10-20 15:26:31 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13866
----------------------------------------------------------------
Bin Meng (1):
riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+
Heinrich Schuchardt (5):
cmd/sbi: format RustSBI version number
cmd/sbi: error message for failure to get spec version
cmd/sbi: user friendly short texts
riscv: support building double-float modules
k210: fix k210_pll_calc_config()
Rick Chen (1):
riscv: ae350: Check firmware_fdt_addr header
Yu Chien Peter Lin (1):
riscv: andes_plic.c: use modified IPI scheme
arch/riscv/Kconfig | 15 +++++++++++++++
arch/riscv/Makefile | 15 ++++++++++++---
arch/riscv/lib/andes_plic.c | 7 ++++---
board/AndesTech/ax25-ae350/ax25-ae350.c | 2 +-
board/emulation/qemu-riscv/Kconfig | 2 +-
cmd/riscv/sbi.c | 26 +++++++++++++++-----------
drivers/clk/clk_k210.c | 2 +-
test/dm/k210_pll.c | 2 +-
8 files changed, 50 insertions(+), 21 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2022-09-06 6:07 Leo Liang
2022-09-06 15:50 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2022-09-06 6:07 UTC (permalink / raw)
To: trini; +Cc: rick, ycliang, u-boot
Hi Tom,
The following changes since commit 427aa3c9b72b6672f714389a6f71b6cc2841d559:
Merge tag 'tpm-03092022' of https://source.denx.de/u-boot/custodians/u-boot-tpm (2022-09-03 14:55:37 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 4a98207b2335b7108e964b831dc92f0333346c87:
RISC-V: enable CONFIG_SYSRESET_SBI by default (2022-09-06 13:00:58 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13361
----------------------------------------------------------------
Heinrich Schuchardt (2):
cmd/sbi: format KVM version
RISC-V: enable CONFIG_SYSRESET_SBI by default
Icenowy Zheng (2):
dt-bindings: clock: sifive: sync FU740 PRCI clock binding header
riscv: dts: sifive: Synchronize FU740 and Unmatched DT
Jessica Clarke (1):
riscv: dts: Sync important Unmatched pmic and qspi0 changes from Linux
arch/riscv/dts/fu740-c000-u-boot.dtsi | 16 ++---
arch/riscv/dts/fu740-c000.dtsi | 91 +++++++++++++------------
arch/riscv/dts/hifive-unmatched-a00.dts | 95 ++++++++++++---------------
cmd/riscv/sbi.c | 14 +++-
drivers/clk/sifive/fu740-prci.c | 18 ++---
drivers/clk/sifive/sifive-prci.c | 4 +-
drivers/sysreset/Kconfig | 1 +
include/dt-bindings/clock/sifive-fu740-prci.h | 25 ++++---
8 files changed, 129 insertions(+), 135 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2022-08-11 21:38 Leo Liang
2022-08-12 12:17 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2022-08-11 21:38 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick, ycliang
Hi Tom,
The following changes since commit cdebee1fd9fa04cc4c972f826bae19b28c253eb0:
Merge branch '2022-08-10-assorted-updates' (2022-08-10 17:49:20 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to aa0eda17cf98448c3ef826204f38c76bf48b3345:
spl: opensbi: convert scratch options to config (2022-08-11 18:46:41 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13119
----------------------------------------------------------------
Leo Yu-Chi Liang (1):
riscv: ae350: Fix XIP config boot failure
Nikita Shubin (3):
riscv: cpu: set gp before board_init_f_init_reserve
spl: opensbi: fix typo
spl: opensbi: convert scratch options to config
arch/riscv/cpu/start.S | 5 ++++-
board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +++++++++++------
common/spl/Kconfig | 8 ++++++++
common/spl/spl_opensbi.c | 4 ++--
4 files changed, 25 insertions(+), 9 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2022-05-27 2:36 Leo Liang
2022-05-27 13:30 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2022-05-27 2:36 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick, ycliang
Hi Tom,
The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5:
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd:
riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 18:42:34 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131
----------------------------------------------------------------
Bin Meng (3):
riscv: sifive: unmatched: Adjust for big ramdisk image
riscv: sifive: unleashed: Set kernel_comp_addr_r for compressed kernel
riscv: qemu: Set kernel_comp_addr_r for compressed kernel
Heinrich Schuchardt (1):
cmd/sbi: add implementation ID 6 - Coffer
Leo Yu-Chi Liang (1):
riscv: Clean up asm/io.h
Michal Simek (1):
riscv: remove CONFIG_ARCH_MAP_SYSMEM from io.h
Rick Chen (2):
riscv: ae350: Fix OF_BOARD boot failure
riscv: ae350: Fix OF_BOARD boot failure
arch/riscv/include/asm/io.h | 138 -----------------------------------
board/AndesTech/ax25-ae350/Kconfig | 1 +
cmd/riscv/sbi.c | 1 +
configs/ae350_rv32_spl_defconfig | 1 +
configs/ae350_rv32_spl_xip_defconfig | 1 +
configs/ae350_rv64_spl_defconfig | 1 +
configs/ae350_rv64_spl_xip_defconfig | 1 +
doc/board/sifive/unleashed.rst | 2 -
include/configs/qemu-riscv.h | 10 ++-
include/configs/sifive-unleashed.h | 10 ++-
include/configs/sifive-unmatched.h | 10 +--
11 files changed, 23 insertions(+), 153 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* Re: [PULL] u-boot-riscv/master
2022-05-27 2:36 Leo Liang
@ 2022-05-27 13:30 ` Tom Rini
2022-05-28 9:02 ` Leo Liang
0 siblings, 1 reply; 99+ messages in thread
From: Tom Rini @ 2022-05-27 13:30 UTC (permalink / raw)
To: Leo Liang; +Cc: u-boot, rick
[-- Attachment #1: Type: text/plain, Size: 900 bytes --]
On Fri, May 27, 2022 at 02:36:29AM +0000, Leo Liang wrote:
> Hi Tom,
>
> The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5:
>
> Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 -0400)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd:
>
> riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 18:42:34 +0800)
>
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131
First, I've applied this to u-boot/master now. Second, will
https://patchwork.ozlabs.org/project/uboot/patch/PH7PR14MB5594FD11D1BE74284F554BEBCED49@PH7PR14MB5594.namprd14.prod.outlook.com/
be coming soon? Thanks!
--
Tom
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PULL] u-boot-riscv/master
2022-05-27 13:30 ` Tom Rini
@ 2022-05-28 9:02 ` Leo Liang
2022-05-30 15:05 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2022-05-28 9:02 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot, rick
On Fri, May 27, 2022 at 09:30:49AM -0400, Tom Rini wrote:
> On Fri, May 27, 2022 at 02:36:29AM +0000, Leo Liang wrote:
>
> > Hi Tom,
> >
> > The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5:
> >
> > Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 -0400)
> >
> > are available in the Git repository at:
> >
> > https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> >
> > for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd:
> >
> > riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 18:42:34 +0800)
> >
> > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131
>
> First, I've applied this to u-boot/master now. Second, will
> https://patchwork.ozlabs.org/project/uboot/patch/PH7PR14MB5594FD11D1BE74284F554BEBCED49@PH7PR14MB5594.namprd14.prod.outlook.com/
> be coming soon? Thanks!
Hi Tom,
This patch you mentioned will not pass CI, and the reason for that
is the toolchain used for RISC-V in CI does not have corresponding
settings for zifencei and zicsr.
(detailed disscussion: https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.ghiti@canonical.com/)
(CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/440735)
The patch looks valid, but will fail CI on 32-bit configs.
If we use 32-bit toolchain to test 32-bit configs, then
problems solved.
Do you have any comments?
Best regards.
Leo
> --
> Tom
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PULL] u-boot-riscv/master
2022-05-28 9:02 ` Leo Liang
@ 2022-05-30 15:05 ` Tom Rini
2022-08-11 22:22 ` Leo Liang
0 siblings, 1 reply; 99+ messages in thread
From: Tom Rini @ 2022-05-30 15:05 UTC (permalink / raw)
To: Leo Liang; +Cc: u-boot, rick
[-- Attachment #1: Type: text/plain, Size: 1853 bytes --]
On Sat, May 28, 2022 at 09:02:09AM +0000, Leo Liang wrote:
> On Fri, May 27, 2022 at 09:30:49AM -0400, Tom Rini wrote:
> > On Fri, May 27, 2022 at 02:36:29AM +0000, Leo Liang wrote:
> >
> > > Hi Tom,
> > >
> > > The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5:
> > >
> > > Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 -0400)
> > >
> > > are available in the Git repository at:
> > >
> > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> > >
> > > for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd:
> > >
> > > riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 18:42:34 +0800)
> > >
> > > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131
> >
> > First, I've applied this to u-boot/master now. Second, will
> > https://patchwork.ozlabs.org/project/uboot/patch/PH7PR14MB5594FD11D1BE74284F554BEBCED49@PH7PR14MB5594.namprd14.prod.outlook.com/
> > be coming soon? Thanks!
>
> Hi Tom,
>
> This patch you mentioned will not pass CI, and the reason for that
> is the toolchain used for RISC-V in CI does not have corresponding
> settings for zifencei and zicsr.
> (detailed disscussion: https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.ghiti@canonical.com/)
> (CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/440735)
>
> The patch looks valid, but will fail CI on 32-bit configs.
> If we use 32-bit toolchain to test 32-bit configs, then
> problems solved.
>
> Do you have any comments?
I guess I'm OK with saying we should use a 32bit toolchain for 32bit
riscv, if that's how things should be handled moving forward for
everyone else.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PULL] u-boot-riscv/master
2022-05-30 15:05 ` Tom Rini
@ 2022-08-11 22:22 ` Leo Liang
0 siblings, 0 replies; 99+ messages in thread
From: Leo Liang @ 2022-08-11 22:22 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot, rick, ycliang
On Mon, May 30, 2022 at 11:05:54AM -0400, Tom Rini wrote:
> On Sat, May 28, 2022 at 09:02:09AM +0000, Leo Liang wrote:
> > On Fri, May 27, 2022 at 09:30:49AM -0400, Tom Rini wrote:
> > > On Fri, May 27, 2022 at 02:36:29AM +0000, Leo Liang wrote:
> > >
> > > > Hi Tom,
> > > >
> > > > The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5:
> > > >
> > > > Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 -0400)
> > > >
> > > > are available in the Git repository at:
> > > >
> > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> > > >
> > > > for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd:
> > > >
> > > > riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 18:42:34 +0800)
> > > >
> > > > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131
> > >
> > > First, I've applied this to u-boot/master now. Second, will
> > > https://patchwork.ozlabs.org/project/uboot/patch/PH7PR14MB5594FD11D1BE74284F554BEBCED49@PH7PR14MB5594.namprd14.prod.outlook.com/
> > > be coming soon? Thanks!
> >
> > Hi Tom,
> >
> > This patch you mentioned will not pass CI, and the reason for that
> > is the toolchain used for RISC-V in CI does not have corresponding
> > settings for zifencei and zicsr.
> > (detailed disscussion: https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.ghiti@canonical.com/)
> > (CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/440735)
> >
> > The patch looks valid, but will fail CI on 32-bit configs.
> > If we use 32-bit toolchain to test 32-bit configs, then
> > problems solved.
> >
> > Do you have any comments?
>
> I guess I'm OK with saying we should use a 32bit toolchain for 32bit
> riscv, if that's how things should be handled moving forward for
> everyone else.
>
> --
> Tom
Hi Tom,
Sorry for taking such a long time to reply.
Recap:
All the "riscv: fix compitible with binutils 2.38" patches that
try to support new RISC-V ISA extension will cause U-Boot CI to fail
because the toolchain used in U-Boot CI do not support the new multilib settings.
(original discussion:
https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.ghiti@canonical.com/)
We found that current RISC-V toolchains from kernel.org do not
support zifencei and zicsr extensions' multilib settings,
regardless of the toolchain version.
(Both gcc 11.1.0, 12.1.0 do not support the needed settings.
https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/
https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.1.0/)
But we also found that if we use recent upstream riscv-gnu-toolchain,
we could build an gcc-12.1.0 toolchain that does support multilib
settings and could fix this issue.
We have provided a Dockerfile as a reference build script[1] and
a prebuilt toolchain[2] for U-Boot CI to use.
We have also verified the CI process could execute successfully
with your base image and the provided riscv64-linux toolchain[3].
I guess the coming update of the toolchain in kernel.org should
contain the new multilib settings, so I was wondering if we could
replace the riscv64-linux toolchain from kernel.org with this prebuilt
toolchain we've provided on github[2] temporarily?
After studying a bit of the buildman tool, the earlier idea that
"use different toolchains for different board configs" would require
an amount of modification, thus we think its best to replace the toolchain
temporarily to fix this issue, then the patch could be applied without CI failure.
[1] https://github.com/ycliang-andes/riscv-toolchain/blob/master/Dockerfile
[2] https://github.com/ycliang-andes/riscv-toolchain/releases/download/v1.0/x86_64-gcc-12.1.0-nolibc-riscv64-linux.tar.xz
[3] https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13129
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
@ 2022-04-06 4:43 Leo Liang
2022-04-06 15:55 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2022-04-06 4:43 UTC (permalink / raw)
To: trini; +Cc: rick, ycliang, u-boot
Hi Tom,
The following changes since commit 59bffec43a657598b194b9eb30dc01eec06078c7:
Merge branch '2022-04-04-platform-updates' (2022-04-05 13:45:22 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 776e8aca0bad2900dc9c12b87dedb732a9f8e39b:
riscv: alloc space exhausted (2022-04-06 10:58:13 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/11595
----------------------------------------------------------------
Heinrich Schuchardt (5):
cmd: sbi: add Performance Monitoring Unit Extension
riscv: provide missing base extension functions
cmd/sbi: add missing SBI information
riscv: enable CONFIG_CMD_SBI for QEMU boards
riscv: alloc space exhausted
Kconfig | 2 +-
arch/riscv/Kconfig | 3 ---
arch/riscv/include/asm/sbi.h | 4 ++++
arch/riscv/lib/sbi.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
board/emulation/qemu-riscv/Kconfig | 1 +
cmd/riscv/sbi.c | 14 +++++++++++++-
6 files changed, 84 insertions(+), 5 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2022-03-16 2:56 Leo Liang
2022-03-16 14:48 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2022-03-16 2:56 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick, ycliang
Hi Tom,
The following changes since commit c149bf41404e34014e37de32fac332892b11bd4a:
Prepare v2022.04-rc4 (2022-03-14 16:39:08 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to aa34e13346cf727197981c599f688b406005049a:
pinctrl: k210: Fix bias-pull-up (2022-03-15 17:43:11 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/11297
----------------------------------------------------------------
Damien Le Moal (4):
k210: use the board vendor name rather than the marketing name
k210: dts: add missing power bus clocks
k210: dts: align fpioa node with Linux
spi: dw: Force set K210 fifo length to 31
Niklas Cassel (3):
k210: dts: align plic node with Linux
pinctrl: k210: Fix loop in k210_pc_get_drive()
pinctrl: k210: Fix bias-pull-up
Sean Anderson (1):
spi: dw: Actually mask interrupts
MAINTAINERS | 12 +-
arch/riscv/dts/k210-maix-bit.dts | 3 +-
arch/riscv/dts/k210.dtsi | 177 ++++++++++++---------
board/sipeed/maix/maix.c | 2 +-
doc/board/sipeed/maix.rst | 20 +--
...ryte,k210-sysctl.txt => canaan,k210-sysctl.txt} | 8 +-
...ndryte,k210-fpioa.txt => canaan,k210-fpioa.txt} | 12 +-
doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt | 4 +-
drivers/clk/Makefile | 2 +-
drivers/clk/{clk_kendryte.c => clk_k210.c} | 4 +-
drivers/pinctrl/Makefile | 2 +-
.../pinctrl/{pinctrl-kendryte.c => pinctrl-k210.c} | 25 ++-
drivers/spi/designware_spi.c | 20 ++-
include/configs/sipeed-maix.h | 2 +-
include/{kendryte => k210}/pll.h | 0
test/dm/k210_pll.c | 2 +-
16 files changed, 174 insertions(+), 121 deletions(-)
rename doc/device-tree-bindings/mfd/{kendryte,k210-sysctl.txt => canaan,k210-sysctl.txt} (78%)
rename doc/device-tree-bindings/pinctrl/{kendryte,k210-fpioa.txt => canaan,k210-fpioa.txt} (91%)
rename drivers/clk/{clk_kendryte.c => clk_k210.c} (99%)
rename drivers/pinctrl/{pinctrl-kendryte.c => pinctrl-k210.c} (97%)
rename include/{kendryte => k210}/pll.h (100%)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2021-12-03 6:19 Leo Liang
2021-12-04 17:50 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-12-03 6:19 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick
Hi Tom,
The following changes since commit 4a14bfffd42f968ed9d72a780a8d44a9053c5b95:
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2021-11-30 08:59:22 -0500)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to c0ffc12a701621dc72dfc896965cbfe5b0dbf9b4:
riscv: Enable SPI flash env for SiFive Unmatched. (2021-12-02 16:43:56 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/10128
----------------------------------------------------------------
Leo Yu-Chi Liang (1):
board: ae350: Support autoboot from RAM
Padmarao Begari (5):
net: macb: Remove Microchip compatible string
i2c: Add Microchip PolarFire SoC I2C driver
riscv: dts: Split Microchip device tree
riscv: Update Microchip MPFS Icicle Kit support
doc: board: Update Microchip MPFS Icicle Kit doc
Thomas Skibo (2):
riscv: Support booting SiFive Unmatched from SPI.
riscv: Enable SPI flash env for SiFive Unmatched.
arch/riscv/cpu/fu740/Kconfig | 13 +
arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi | 11 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 518 +++++--------------
arch/riscv/dts/microchip-mpfs.dtsi | 571 +++++++++++++++++++++
board/microchip/mpfs_icicle/Kconfig | 5 +
board/microchip/mpfs_icicle/mpfs_icicle.c | 17 +-
board/sifive/unmatched/Kconfig | 1 +
board/sifive/unmatched/spl.c | 3 +
configs/microchip_mpfs_icicle_defconfig | 1 -
configs/sifive_unmatched_defconfig | 6 +
doc/board/microchip/mpfs_icicle.rst | 7 +-
doc/board/sifive/unmatched.rst | 31 ++
drivers/i2c/Kconfig | 6 +
drivers/i2c/Makefile | 1 +
drivers/i2c/i2c-microchip.c | 482 +++++++++++++++++
drivers/net/macb.c | 18 +-
include/configs/ax25-ae350.h | 13 +-
.../interrupt-controller/microchip-mpfs-plic.h | 196 +++++++
.../dt-bindings/interrupt-controller/riscv-hart.h | 17 +
19 files changed, 1512 insertions(+), 405 deletions(-)
create mode 100644 arch/riscv/dts/microchip-mpfs.dtsi
create mode 100644 drivers/i2c/i2c-microchip.c
create mode 100644 include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h
create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2021-11-09 2:40 Leo Liang
2021-11-09 13:45 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-11-09 2:40 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick
Hi Tom,
The following changes since commit 52207514ba419a69a8105d16997b025f966c8879:
Merge branch '2021-11-05-Kconfig-syncs' (2021-11-05 15:38:46 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 990e1e4beae546ddc9c50854c0588d1bea494cd2:
Fix syntax error (2021-11-08 15:35:55 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9775
----------------------------------------------------------------
Heinrich Schuchardt (2):
riscv: function to retrieve SBI implementation version
cmd: sbi: show SBI implementation version
Leo Yu-Chi Liang (2):
riscv: ae350: Use #if defined instead of CONFIG_IS_ENABLED
Fix syntax error
Wei Fu (1):
riscv: add #define in asm/io.h for some device drivers
arch/riscv/include/asm/io.h | 4 ++++
arch/riscv/include/asm/sbi.h | 1 +
arch/riscv/lib/sbi.c | 19 +++++++++++++++++++
board/AndesTech/ax25-ae350/ax25-ae350.c | 4 ++--
cmd/riscv/sbi.c | 26 ++++++++++++++++++--------
common/image-board.c | 2 +-
6 files changed, 45 insertions(+), 11 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2021-10-20 7:14 Leo Liang
2021-10-21 11:51 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-10-20 7:14 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick
Hi Tom,
The following changes since commit fb1018106a7bbb1a0d723029f6760b1b1b4d306d:
Merge branch '2021-10-19-assorted-changes' (2021-10-19 20:45:12 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to ddf4972834fdf33f0a3360ff4a68fde333995113:
riscv: Avoid io read/write cause wrong result (2021-10-20 10:59:17 +0800)
SI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9532
----------------------------------------------------------------
Bin Meng (10):
board: sifive: Fix a potential build warning in board_fdt_blob_setup()
cache: sifive: Fix -Wint-to-pointer-cast warning
clk: sifive: Fix -Wint-to-pointer-cast warning
gpio: sifive: Fix -Wint-to-pointer-cast warning
i2c: ocores: Fix -Wint-to-pointer-cast warning
dm: core: Add a new API devfdt_get_addr_index_ptr()
dm: Provide dev_read_addr_index_ptr() wrapper
net: macb: Fix -Wint-to-pointer-cast warnings
ram: sifive: Fix -Wint-to-pointer-cast warnings
board: sifive: Fix -Wint-to-pointer-cast warning
Nick Hu (1):
riscv: Avoid io read/write cause wrong result
arch/riscv/include/asm/io.h | 18 +++++++++---------
board/sifive/unleashed/unleashed.c | 6 +++---
board/sifive/unmatched/unmatched.c | 6 +++---
drivers/cache/cache-sifive-ccache.c | 2 +-
drivers/clk/sifive/sifive-prci.c | 6 +++---
drivers/core/fdtaddr.c | 11 ++++++++---
drivers/gpio/sifive-gpio.c | 6 ++----
drivers/i2c/ocores_i2c.c | 2 +-
drivers/net/macb.c | 11 +++--------
drivers/ram/sifive/sifive_ddr.c | 8 ++++----
include/dm/fdtaddr.h | 12 ++++++++++++
include/dm/read.h | 18 ++++++++++++++++++
12 files changed, 67 insertions(+), 39 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2021-10-07 11:51 Leo Liang
2021-10-07 15:43 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-10-07 11:51 UTC (permalink / raw)
To: trini; +Cc: rick, u-boot
Hi Tom,
The following changes since commit ea67f467a43e4c8852bd1ce1bb75f5dc6c3788d1:
Merge branch '2021-10-06-assorted-improvements' (2021-10-06 13:46:31 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 1b2b52f29402b5aaccccadfe4ba11bd3f29bd414:
riscv: ae350: enable Coherence Manager for ae350 (2021-10-07 16:08:23 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9388
----------------------------------------------------------------
Heinrich Schuchardt (4):
riscv: add missing SBI extension definitions
cmd/sbi: use constants instead of numerical values
sysreset: provide SBI based sysreset driver
configs: enable SYSRESET_SBI on qemu-riscvXX_smode_defconfig
Leo Yu-Chi Liang (1):
riscv: ae350: enable Coherence Manager for ae350
Samuel Holland (3):
serial: Add a debug console using the RISC-V SBI interface
riscv: Fix setting no-map in reserved memory nodes
riscv: image: Use the first DRAM bank for bootm_low
Sean Anderson (4):
clk: k210: Fix checking if ulongs are less than 0
k210: clk: Refactor out_of_spec tests
test: dm: k210: Reduce duplication in test cases
clk: k210: Try harder to get the best config
MAINTAINERS | 1 +
arch/riscv/cpu/ax25/cpu.c | 42 +++++++++++
arch/riscv/cpu/cpu.c | 13 +++-
arch/riscv/include/asm/sbi.h | 40 ++++++++++-
arch/riscv/lib/fdt_fixup.c | 5 +-
arch/riscv/lib/sbi.c | 12 ++++
cmd/riscv/sbi.c | 30 ++++----
common/image.c | 2 +-
configs/qemu-riscv32_smode_defconfig | 1 +
configs/qemu-riscv32_spl_defconfig | 1 +
configs/qemu-riscv64_smode_defconfig | 1 +
configs/qemu-riscv64_spl_defconfig | 1 +
drivers/clk/clk_kendryte.c | 134 +++++++++++++++++++++--------------
drivers/serial/Kconfig | 10 +++
drivers/serial/Makefile | 1 +
drivers/serial/serial_sbi.c | 16 +++++
drivers/sysreset/Kconfig | 12 ++++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_sbi.c | 51 +++++++++++++
test/dm/k210_pll.c | 36 +++++-----
20 files changed, 313 insertions(+), 97 deletions(-)
create mode 100644 drivers/serial/serial_sbi.c
create mode 100644 drivers/sysreset/sysreset_sbi.c
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2021-09-07 8:20 Leo Liang
2021-09-07 15:33 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-09-07 8:20 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick
Hi Tom,
The following changes since commit ad320c237bea7ece659efaf6c1d43475e0e5db6a:
Merge tag 'u-boot-stm32-20210906' of https://source.denx.de/u-boot/custodians/u-boot-stm (2021-09-06 10:31:56 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 30fa33dc808b8f28185bca9c812225cbc1ec6e8f:
riscv: lib: modify the indent (2021-09-07 10:34:29 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9018
----------------------------------------------------------------
Heinrich Schuchardt (3):
riscv: enable booting HiFive Unmatched from SATA
configs: qemu-riscvXX_spl_defconfig enable CMD_SBI
riscv: show code leading to exception
Thomas Skibo (1):
riscv: Add missing sentinel in ocores_i2c.c
Zong Li (5):
cache: add sifive composable cache driver
common: board_r: support enable_caches for RISC-V
riscv: lib: implement enable_caches for sifive cache
board: sifive: use ccache driver instead of helper function
riscv: lib: modify the indent
arch/riscv/Kconfig | 5 +++
arch/riscv/cpu/fu540/Kconfig | 2 +
arch/riscv/cpu/fu540/Makefile | 1 -
arch/riscv/cpu/fu540/cache.c | 55 -----------------------
arch/riscv/cpu/fu740/Kconfig | 2 +
arch/riscv/cpu/fu740/Makefile | 1 -
arch/riscv/cpu/fu740/cache.c | 55 -----------------------
arch/riscv/include/asm/arch-fu540/cache.h | 14 ------
arch/riscv/include/asm/arch-fu740/cache.h | 14 ------
arch/riscv/include/asm/cache.h | 2 +-
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/cache.c | 4 ++
arch/riscv/lib/interrupts.c | 33 ++++++++++++++
arch/riscv/lib/sifive_cache.c | 27 +++++++++++
board/sifive/unleashed/unleashed.c | 10 +----
board/sifive/unmatched/unmatched.c | 11 ++---
common/board_r.c | 4 +-
configs/qemu-riscv32_spl_defconfig | 1 +
configs/qemu-riscv64_spl_defconfig | 1 +
configs/sifive_unmatched_defconfig | 5 +++
drivers/cache/Kconfig | 7 +++
drivers/cache/Makefile | 1 +
drivers/cache/cache-sifive-ccache.c | 75 +++++++++++++++++++++++++++++++
drivers/i2c/ocores_i2c.c | 1 +
include/configs/sifive-unmatched.h | 3 ++
25 files changed, 176 insertions(+), 159 deletions(-)
delete mode 100644 arch/riscv/cpu/fu540/cache.c
delete mode 100644 arch/riscv/cpu/fu740/cache.c
delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
create mode 100644 arch/riscv/lib/sifive_cache.c
create mode 100644 drivers/cache/cache-sifive-ccache.c
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2021-08-19 8:56 Leo Liang
2021-08-19 14:13 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-08-19 8:56 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick
Hi Tom,
The following changes since commit a0da2dda4ed9d0aee5265e9cd8876734f9f80e09:
Prepare v2021.10-rc2 (2021-08-16 14:18:45 -0400)
are available in the Git repository at:
git@source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 47d73ba4f4a40f17622d93f96b48e285b73c3061:
board: sifive: overwrite board_fdt_blob_setup in u-boot proper (2021-08-17 19:28:37 +0800)
CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8749
----------------------------------------------------------------
Dimitri John Ledkov (1):
qemu-riscv64_smode: fix extlinux (define preboot)
Zong Li (3):
riscv: cpu: fu740: Fix typo of date
board: sifive: compile stuff only related to SPL in SPL build
board: sifive: overwrite board_fdt_blob_setup in u-boot proper
arch/riscv/cpu/fu740/spl.c | 2 +-
board/sifive/unleashed/Makefile | 4 ++--
board/sifive/unleashed/unleashed.c | 11 +++++++++++
board/sifive/unmatched/Makefile | 3 ++-
board/sifive/unmatched/unmatched.c | 11 +++++++++++
configs/qemu-riscv64_smode_defconfig | 2 ++
6 files changed, 29 insertions(+), 4 deletions(-)
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2021-07-22 2:15 Leo Liang
2021-07-22 12:15 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-07-22 2:15 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick
Hi Tom,
The following changes since commit c9204859bbdb924cda811813c545032971656480:
Merge branch 'master' of git://source.denx.de/u-boot-sh (2021-07-20 19:31:40 -0400)
are available in the Git repository at:
git@source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 219cb173114c9cfaf1dc7fed21281f2c43c88c9f:
board: sifive: unmatched: reset USB hub, PCIe-USB bridge, and ULPI device in SPL (2021-07-21 22:25:15 +0800)
CI result show no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8344
----------------------------------------------------------------
Vincent Chen (2):
board: sifive: unmatched: refine GEMGXL initialized function in SPL
board: sifive: unmatched: reset USB hub, PCIe-USB bridge, and ULPI device in SPL
Vitaly Wool (1):
riscv: booti: do not force relocation if force_reloc is not set
Zong Li (2):
board: sifive: remove the command for setting serial number
board: sifive: drop stuff related to unmatched revision 1
arch/riscv/dts/Makefile | 2 +-
.../dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi | 1489 --------------------
.../dts/hifive-unmatched-a00-rev1-u-boot.dtsi | 7 -
arch/riscv/dts/hifive-unmatched-a00-rev1.dts | 4 -
arch/riscv/lib/image.c | 7 +-
.../sifive/unmatched/hifive-platform-i2c-eeprom.c | 23 +-
board/sifive/unmatched/spl.c | 114 +-
configs/sifive_unmatched_defconfig | 4 -
8 files changed, 81 insertions(+), 1569 deletions(-)
delete mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi
delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1.dts
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* Re: [PULL] u-boot-riscv/master
2021-07-22 2:15 Leo Liang
@ 2021-07-22 12:15 ` Tom Rini
0 siblings, 0 replies; 99+ messages in thread
From: Tom Rini @ 2021-07-22 12:15 UTC (permalink / raw)
To: Leo Liang; +Cc: u-boot, rick
[-- Attachment #1: Type: text/plain, Size: 715 bytes --]
On Thu, Jul 22, 2021 at 10:15:10AM +0800, Leo Liang wrote:
> Hi Tom,
>
> The following changes since commit c9204859bbdb924cda811813c545032971656480:
>
> Merge branch 'master' of git://source.denx.de/u-boot-sh (2021-07-20 19:31:40 -0400)
>
> are available in the Git repository at:
>
> git@source.denx.de:u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to 219cb173114c9cfaf1dc7fed21281f2c43c88c9f:
>
> board: sifive: unmatched: reset USB hub, PCIe-USB bridge, and ULPI device in SPL (2021-07-21 22:25:15 +0800)
>
> CI result show no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8344
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
@ 2021-07-07 15:21 Leo Liang
2021-07-07 17:33 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-07-07 15:21 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick, tianrui-wei
Hi Tom,
This is a follow up PR for OpenPiton's dts.
Thanks for the catch.
The following changes since commit 5617efd2c882562b716a61bc0dc0edda46b045df:
Merge branch '2021-07-06-platform-updates' (2021-07-06 18:10:10 -0400)
are available in the Git repository at:
git@source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to c9135d5a7af2df0e273e0f7e2f6c8132b34aba82:
riscv: dts: add OpenPiton RISC-V board dts support (2021-07-07 20:34:02 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8100
----------------------------------------------------------------
Tianrui Wei (1):
riscv: dts: add OpenPiton RISC-V board dts support
arch/riscv/dts/openpiton-riscv64.dts | 4 ++--
board/openpiton/riscv64/MAINTAINERS | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* Re: [PULL] u-boot-riscv/master
2021-07-07 15:21 Leo Liang
@ 2021-07-07 17:33 ` Tom Rini
0 siblings, 0 replies; 99+ messages in thread
From: Tom Rini @ 2021-07-07 17:33 UTC (permalink / raw)
To: Leo Liang; +Cc: u-boot, rick, tianrui-wei
[-- Attachment #1: Type: text/plain, Size: 753 bytes --]
On Wed, Jul 07, 2021 at 11:21:13PM +0800, Leo Liang wrote:
> Hi Tom,
>
> This is a follow up PR for OpenPiton's dts.
>
> Thanks for the catch.
>
> The following changes since commit 5617efd2c882562b716a61bc0dc0edda46b045df:
>
> Merge branch '2021-07-06-platform-updates' (2021-07-06 18:10:10 -0400)
>
> are available in the Git repository at:
>
> git@source.denx.de:u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to c9135d5a7af2df0e273e0f7e2f6c8132b34aba82:
>
> riscv: dts: add OpenPiton RISC-V board dts support (2021-07-07 20:34:02 +0800)
>
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8100
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
@ 2021-07-06 16:02 Leo Liang
2021-07-06 19:52 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-07-06 16:02 UTC (permalink / raw)
To: trini; +Cc: u-boot, rick
Hi Tom,
The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de:
Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400)
are available in the Git repository at:
git@source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 4b4159d0f31ca3e0174ccfdce9a24a1fe3671829:
board: sifive: support spl multi-dtb on unmatched board (2021-07-06 20:24:26 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8081
----------------------------------------------------------------
Dimitri John Ledkov (1):
riscv: sifive: Set default fdtfile names
Green Wan (1):
drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'
Tianrui Wei (2):
board: riscv: add openpiton-riscv64 SoC support
mmc: openpiton: add piton_mmc driver
Zong Li (6):
board: sifive: unmatched: add initial support for a platform ID EEPROM
riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller
riscv: sifive: fu740: Support i2c in spl
board: sifive: Add an interface to get PCB revision
riscv: dts: add dts for unmatched rev1
board: sifive: support spl multi-dtb on unmatched board
arch/riscv/Kconfig | 4 +
arch/riscv/cpu/fu740/Kconfig | 3 +
arch/riscv/dts/Makefile | 3 +-
arch/riscv/dts/fu740-c000-u-boot.dtsi | 4 +
.../dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi | 1489 ++++++++++++++++++++
.../dts/hifive-unmatched-a00-rev1-u-boot.dtsi | 7 +
arch/riscv/dts/hifive-unmatched-a00-rev1.dts | 4 +
arch/riscv/dts/openpiton-riscv64.dts | 153 ++
arch/riscv/include/asm/arch-fu740/eeprom.h | 15 +
board/openpiton/riscv64/Kconfig | 40 +
board/openpiton/riscv64/MAINTAINERS | 8 +
board/openpiton/riscv64/Makefile | 5 +
board/openpiton/riscv64/openpiton-riscv64.c | 33 +
board/sifive/unmatched/Kconfig | 1 +
board/sifive/unmatched/Makefile | 1 +
.../sifive/unmatched/hifive-platform-i2c-eeprom.c | 574 ++++++++
board/sifive/unmatched/spl.c | 28 +-
configs/openpiton_riscv64_defconfig | 76 +
configs/openpiton_riscv64_spl_defconfig | 87 ++
configs/sifive_unleashed_defconfig | 1 +
configs/sifive_unmatched_defconfig | 5 +
doc/board/index.rst | 1 +
doc/board/openpiton/index.rst | 9 +
doc/board/openpiton/riscv64.rst | 376 +++++
drivers/clk/sifive/fu740-prci.c | 6 +-
drivers/mmc/Kconfig | 9 +
drivers/mmc/Makefile | 1 +
drivers/mmc/piton_mmc.c | 161 +++
include/configs/openpiton-riscv64.h | 61 +
include/configs/sifive-unleashed.h | 1 +
include/configs/sifive-unmatched.h | 7 +
31 files changed, 3167 insertions(+), 6 deletions(-)
create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
create mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi
create mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1.dts
create mode 100644 arch/riscv/dts/openpiton-riscv64.dts
create mode 100644 arch/riscv/include/asm/arch-fu740/eeprom.h
create mode 100644 board/openpiton/riscv64/Kconfig
create mode 100644 board/openpiton/riscv64/MAINTAINERS
create mode 100644 board/openpiton/riscv64/Makefile
create mode 100644 board/openpiton/riscv64/openpiton-riscv64.c
create mode 100644 board/sifive/unmatched/hifive-platform-i2c-eeprom.c
create mode 100644 configs/openpiton_riscv64_defconfig
create mode 100644 configs/openpiton_riscv64_spl_defconfig
create mode 100644 doc/board/openpiton/index.rst
create mode 100644 doc/board/openpiton/riscv64.rst
create mode 100644 drivers/mmc/piton_mmc.c
create mode 100644 include/configs/openpiton-riscv64.h
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* Re: [PULL] u-boot-riscv/master
2021-07-06 16:02 Leo Liang
@ 2021-07-06 19:52 ` Tom Rini
2021-07-07 4:05 ` Tianrui Wei
0 siblings, 1 reply; 99+ messages in thread
From: Tom Rini @ 2021-07-06 19:52 UTC (permalink / raw)
To: Leo Liang; +Cc: u-boot, rick, Tianrui Wei
[-- Attachment #1: Type: text/plain, Size: 1205 bytes --]
On Wed, Jul 07, 2021 at 12:02:05AM +0800, Leo Liang wrote:
> Hi Tom,
>
> The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de:
>
> Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400)
>
> are available in the Git repository at:
>
> git@source.denx.de:u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to 4b4159d0f31ca3e0174ccfdce9a24a1fe3671829:
>
> board: sifive: support spl multi-dtb on unmatched board (2021-07-06 20:24:26 +0800)
>
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8081
>
Please note:
w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #address-cells (1) differs from / (2)
w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #size-cells (1) differs from / (2)
need to be fixed in a follow up PR (and the relevant dts files should be
added to the board MAINTAINER file too). That said, applied to
u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PULL] u-boot-riscv/master
2021-07-06 19:52 ` Tom Rini
@ 2021-07-07 4:05 ` Tianrui Wei
0 siblings, 0 replies; 99+ messages in thread
From: Tianrui Wei @ 2021-07-07 4:05 UTC (permalink / raw)
To: Tom Rini, Leo Liang; +Cc: u-boot, rick
Hi Tom, Leo,
Apologies for making that mistake, and many many thanks for merging our patches! We’ve already fixed the problem with another patch.
Many thanks,
Tianrui
-----Original Message-----
From: Tom Rini <trini@konsulko.com>
Date: Wednesday, July 7, 2021 at 3:52 AM
To: Leo Liang <ycliang@andestech.com>
Cc: u-boot@lists.denx.de <u-boot@lists.denx.de>, rick@andestech.com <rick@andestech.com>, Tianrui Wei <tianrui-wei@outlook.com>
Subject: Re: [PULL] u-boot-riscv/master
On Wed, Jul 07, 2021 at 12:02:05AM +0800, Leo Liang wrote:
> Hi Tom,
>
> The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de:
>
> Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400)
>
> are available in the Git repository at:
>
> git@source.denx.de<mailto:git@source.denx.de>:u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to 4b4159d0f31ca3e0174ccfdce9a24a1fe3671829:
>
> board: sifive: support spl multi-dtb on unmatched board (2021-07-06 20:24:26 +0800)
>
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8081
>
Please note:
w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #address-cells (1) differs from / (2)
w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #size-cells (1) differs from / (2)
need to be fixed in a follow up PR (and the relevant dts files should be
added to the board MAINTAINER file too). That said, applied to
u-boot/master, thanks!
--
Tom
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
@ 2021-06-17 3:31 Leo Liang
2021-06-17 14:51 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-06-17 3:31 UTC (permalink / raw)
To: trini; +Cc: u-boot, Jian-Zhi Chen, bmeng.cn
Hi Tom,
The following changes since commit 9301a5cc99dd0c298e2f7fe2fa98a7287fcda772:
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2021-06-15 08:23:04 -0400)
are available in the Git repository at:
git@source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 62ce0a02f9e5bda51a05c5f735e5a75f6c4bbb54:
riscv: andes_plic: Fix riscv_get_ipi() mask (2021-06-17 09:39:46 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7864
----------------------------------------------------------------
Bin Meng (7):
riscv: ae350: dts: Add SPDX license header
riscv: ae350: dts: Remove the unnecessary space in bootargs
riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config
riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT
riscv: andes_plic: Fix riscv_get_ipi() mask
arch/riscv/dts/ae350-u-boot.dtsi | 52 ++++++++++++++++++++++++++++++++++++++
arch/riscv/dts/ae350_32.dts | 9 ++++---
arch/riscv/dts/ae350_64.dts | 7 ++---
arch/riscv/lib/andes_plic.c | 4 ++-
doc/board/AndesTech/ax25-ae350.rst | 19 +++-----------
5 files changed, 68 insertions(+), 23 deletions(-)
create mode 100644 arch/riscv/dts/ae350-u-boot.dtsi
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* Re: [PULL] u-boot-riscv/master
2021-06-17 3:31 Leo Liang
@ 2021-06-17 14:51 ` Tom Rini
0 siblings, 0 replies; 99+ messages in thread
From: Tom Rini @ 2021-06-17 14:51 UTC (permalink / raw)
To: Leo Liang; +Cc: u-boot, Jian-Zhi Chen, bmeng.cn
[-- Attachment #1: Type: text/plain, Size: 685 bytes --]
On Thu, Jun 17, 2021 at 11:31:12AM +0800, Leo Liang wrote:
> Hi Tom,
>
> The following changes since commit 9301a5cc99dd0c298e2f7fe2fa98a7287fcda772:
>
> Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2021-06-15 08:23:04 -0400)
>
> are available in the Git repository at:
>
> git@source.denx.de:u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to 62ce0a02f9e5bda51a05c5f735e5a75f6c4bbb54:
>
> riscv: andes_plic: Fix riscv_get_ipi() mask (2021-06-17 09:39:46 +0800)
>
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7864
>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
@ 2021-05-31 10:16 Leo Liang
2021-05-31 18:59 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-05-31 10:16 UTC (permalink / raw)
To: trini; +Cc: rick, u-boot
Hi Tom,
The following changes since commit ffd810487ec2ff6095edf3f3d058d7ed6eb85ff3:
Merge tag 'u-boot-stm32-20210528' of https://source.denx.de/u-boot/custodians/u-boot-stm (2021-05-28 14:11:06 -0400)
are available in the Git repository at:
git@source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to d7da718bd94943309a7f25f14e694226a45b2aef:
drivers: pci: pcie_dw_common: fix Werror compilation error (2021-05-31 16:35:55 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/
----------------------------------------------------------------
Green Wan (9):
riscv: cpu: fu740: Add support for cpu fu740
drivers: clk: add fu740 support
drivers: ram: sifive: rename fu540_ddr and add fu740 support
drivers: pci: add pcie support for fu740
riscv: dts: add fu740 support
riscv: dts: add SiFive Unmatched board support
board: sifive: add HiFive Unmatched board support
riscv: cpu: fu740: clear feature disable CSR
drivers: pci: pcie_dw_common: fix Werror compilation error
arch/riscv/Kconfig | 5 +
arch/riscv/cpu/fu540/Kconfig | 2 +-
arch/riscv/cpu/fu740/Kconfig | 37 +
arch/riscv/cpu/fu740/Makefile | 12 +
arch/riscv/cpu/fu740/cache.c | 55 +
arch/riscv/cpu/fu740/cpu.c | 22 +
arch/riscv/cpu/fu740/dram.c | 38 +
arch/riscv/cpu/fu740/spl.c | 38 +
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 ++
arch/riscv/dts/fu740-c000.dtsi | 329 +++++
arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 ++++++++++++++++++++
arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi | 41 +
arch/riscv/dts/hifive-unmatched-a00.dts | 259 ++++
arch/riscv/include/asm/arch-fu740/cache.h | 14 +
arch/riscv/include/asm/arch-fu740/clk.h | 14 +
arch/riscv/include/asm/arch-fu740/gpio.h | 38 +
arch/riscv/include/asm/arch-fu740/reset.h | 13 +
arch/riscv/include/asm/arch-fu740/spl.h | 14 +
board/sifive/unleashed/Kconfig | 1 +
board/sifive/unmatched/Kconfig | 51 +
board/sifive/unmatched/MAINTAINERS | 9 +
board/sifive/unmatched/Makefile | 9 +
board/sifive/unmatched/spl.c | 85 ++
board/sifive/unmatched/unmatched.c | 24 +
common/spl/Kconfig | 4 +-
configs/sifive_unmatched_defconfig | 54 +
doc/board/sifive/index.rst | 1 +
doc/board/sifive/unmatched.rst | 536 +++++++
drivers/clk/sifive/Kconfig | 8 +-
drivers/clk/sifive/Makefile | 4 +-
drivers/clk/sifive/fu540-prci.c | 769 +---------
drivers/clk/sifive/fu540-prci.h | 22 +
drivers/clk/sifive/fu740-prci.c | 158 +++
drivers/clk/sifive/fu740-prci.h | 22 +
drivers/clk/sifive/sifive-prci.c | 733 ++++++++++
drivers/clk/sifive/sifive-prci.h | 323 +++++
drivers/pci/Kconfig | 10 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_dw_common.c | 54 +-
drivers/pci/pcie_dw_sifive.c | 507 +++++++
drivers/ram/sifive/Kconfig | 8 +-
drivers/ram/sifive/Makefile | 2 +-
drivers/ram/sifive/{fu540_ddr.c => sifive_ddr.c} | 89 +-
drivers/reset/Kconfig | 2 +-
include/configs/sifive-unmatched.h | 83 ++
include/dt-bindings/clock/sifive-fu740-prci.h | 25 +
include/dt-bindings/reset/sifive-fu740-prci.h | 19 +
48 files changed, 5308 insertions(+), 831 deletions(-)
create mode 100644 arch/riscv/cpu/fu740/Kconfig
create mode 100644 arch/riscv/cpu/fu740/Makefile
create mode 100644 arch/riscv/cpu/fu740/cache.c
create mode 100644 arch/riscv/cpu/fu740/cpu.c
create mode 100644 arch/riscv/cpu/fu740/dram.c
create mode 100644 arch/riscv/cpu/fu740/spl.c
create mode 100644 arch/riscv/dts/fu740-c000-u-boot.dtsi
create mode 100644 arch/riscv/dts/fu740-c000.dtsi
create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts
create mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
create mode 100644 arch/riscv/include/asm/arch-fu740/clk.h
create mode 100644 arch/riscv/include/asm/arch-fu740/gpio.h
create mode 100644 arch/riscv/include/asm/arch-fu740/reset.h
create mode 100644 arch/riscv/include/asm/arch-fu740/spl.h
create mode 100644 board/sifive/unmatched/Kconfig
create mode 100644 board/sifive/unmatched/MAINTAINERS
create mode 100644 board/sifive/unmatched/Makefile
create mode 100644 board/sifive/unmatched/spl.c
create mode 100644 board/sifive/unmatched/unmatched.c
create mode 100644 configs/sifive_unmatched_defconfig
create mode 100644 doc/board/sifive/unmatched.rst
create mode 100644 drivers/clk/sifive/fu540-prci.h
create mode 100644 drivers/clk/sifive/fu740-prci.c
create mode 100644 drivers/clk/sifive/fu740-prci.h
create mode 100644 drivers/clk/sifive/sifive-prci.c
create mode 100644 drivers/clk/sifive/sifive-prci.h
create mode 100644 drivers/pci/pcie_dw_sifive.c
rename drivers/ram/sifive/{fu540_ddr.c => sifive_ddr.c} (81%)
create mode 100644 include/configs/sifive-unmatched.h
create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h
create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2021-05-26 8:12 Leo Liang
2021-05-26 15:24 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-05-26 8:12 UTC (permalink / raw)
To: trini; +Cc: rick, u-boot
Hi Tom,
The following changes since commit eb53b943be2949ca111140a8e05532cd74cda058:
Merge https://source.denx.de/u-boot/custodians/u-boot-sh (2021-05-23 10:15:15 -0400)
are available in the Git repository at:
git@source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 9358576a281ab5e3b7348685bbd5f713833a5048:
drivers: pci: pcie_dw_common: fix Werror compilation error (2021-05-24 23:54:54 +0800)
Gitlab CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7620
----------------------------------------------------------------
Green Wan (9):
riscv: cpu: fu740: Add support for cpu fu740
drivers: clk: add fu740 support
drivers: ram: sifive: rename fu540_ddr and add fu740 support
drivers: pci: add pcie support for fu740
riscv: dts: add fu740 support
riscv: dts: add SiFive Unmatched board support
board: sifive: add HiFive Unmatched board support
riscv: cpu: fu740: clear feature disable CSR
drivers: pci: pcie_dw_common: fix Werror compilation error
arch/riscv/Kconfig | 5 +
arch/riscv/cpu/fu540/Kconfig | 2 +-
arch/riscv/cpu/fu740/Kconfig | 37 +
arch/riscv/cpu/fu740/Makefile | 12 +
arch/riscv/cpu/fu740/cache.c | 55 +
arch/riscv/cpu/fu740/cpu.c | 22 +
arch/riscv/cpu/fu740/dram.c | 38 +
arch/riscv/cpu/fu740/spl.c | 38 +
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 ++
arch/riscv/dts/fu740-c000.dtsi | 329 +++++
arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 ++++++++++++++++++++
arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi | 41 +
arch/riscv/dts/hifive-unmatched-a00.dts | 259 ++++
arch/riscv/include/asm/arch-fu740/cache.h | 14 +
arch/riscv/include/asm/arch-fu740/clk.h | 14 +
arch/riscv/include/asm/arch-fu740/gpio.h | 38 +
arch/riscv/include/asm/arch-fu740/reset.h | 13 +
arch/riscv/include/asm/arch-fu740/spl.h | 14 +
board/sifive/unleashed/Kconfig | 1 +
board/sifive/unmatched/Kconfig | 51 +
board/sifive/unmatched/MAINTAINERS | 9 +
board/sifive/unmatched/Makefile | 9 +
board/sifive/unmatched/spl.c | 85 ++
board/sifive/unmatched/unmatched.c | 24 +
common/spl/Kconfig | 4 +-
configs/sifive_unmatched_defconfig | 54 +
doc/board/sifive/index.rst | 1 +
doc/board/sifive/unmatched.rst | 536 +++++++
drivers/clk/sifive/Kconfig | 8 +-
drivers/clk/sifive/Makefile | 4 +-
drivers/clk/sifive/fu540-prci.c | 769 +---------
drivers/clk/sifive/fu540-prci.h | 22 +
drivers/clk/sifive/fu740-prci.c | 158 +++
drivers/clk/sifive/fu740-prci.h | 22 +
drivers/clk/sifive/sifive-prci.c | 733 ++++++++++
drivers/clk/sifive/sifive-prci.h | 323 +++++
drivers/pci/Kconfig | 10 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_dw_common.c | 54 +-
drivers/pci/pcie_dw_sifive.c | 507 +++++++
drivers/ram/sifive/Kconfig | 8 +-
drivers/ram/sifive/Makefile | 2 +-
drivers/ram/sifive/{fu540_ddr.c => sifive_ddr.c} | 89 +-
drivers/reset/Kconfig | 2 +-
include/configs/sifive-unmatched.h | 85 ++
include/dt-bindings/clock/sifive-fu740-prci.h | 25 +
include/dt-bindings/reset/sifive-fu740-prci.h | 19 +
48 files changed, 5310 insertions(+), 831 deletions(-)
create mode 100644 arch/riscv/cpu/fu740/Kconfig
create mode 100644 arch/riscv/cpu/fu740/Makefile
create mode 100644 arch/riscv/cpu/fu740/cache.c
create mode 100644 arch/riscv/cpu/fu740/cpu.c
create mode 100644 arch/riscv/cpu/fu740/dram.c
create mode 100644 arch/riscv/cpu/fu740/spl.c
create mode 100644 arch/riscv/dts/fu740-c000-u-boot.dtsi
create mode 100644 arch/riscv/dts/fu740-c000.dtsi
create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts
create mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
create mode 100644 arch/riscv/include/asm/arch-fu740/clk.h
create mode 100644 arch/riscv/include/asm/arch-fu740/gpio.h
create mode 100644 arch/riscv/include/asm/arch-fu740/reset.h
create mode 100644 arch/riscv/include/asm/arch-fu740/spl.h
create mode 100644 board/sifive/unmatched/Kconfig
create mode 100644 board/sifive/unmatched/MAINTAINERS
create mode 100644 board/sifive/unmatched/Makefile
create mode 100644 board/sifive/unmatched/spl.c
create mode 100644 board/sifive/unmatched/unmatched.c
create mode 100644 configs/sifive_unmatched_defconfig
create mode 100644 doc/board/sifive/unmatched.rst
create mode 100644 drivers/clk/sifive/fu540-prci.h
create mode 100644 drivers/clk/sifive/fu740-prci.c
create mode 100644 drivers/clk/sifive/fu740-prci.h
create mode 100644 drivers/clk/sifive/sifive-prci.c
create mode 100644 drivers/clk/sifive/sifive-prci.h
create mode 100644 drivers/pci/pcie_dw_sifive.c
rename drivers/ram/sifive/{fu540_ddr.c => sifive_ddr.c} (81%)
create mode 100644 include/configs/sifive-unmatched.h
create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h
create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* Re: [PULL] u-boot-riscv/master
2021-05-26 8:12 Leo Liang
@ 2021-05-26 15:24 ` Tom Rini
2021-05-27 8:57 ` Green Wan
0 siblings, 1 reply; 99+ messages in thread
From: Tom Rini @ 2021-05-26 15:24 UTC (permalink / raw)
To: Leo Liang, Green Wan; +Cc: rick, u-boot
[-- Attachment #1: Type: text/plain, Size: 1246 bytes --]
On Wed, May 26, 2021 at 04:12:50PM +0800, Leo Liang wrote:
> Hi Tom,
>
> The following changes since commit eb53b943be2949ca111140a8e05532cd74cda058:
>
> Merge https://source.denx.de/u-boot/custodians/u-boot-sh (2021-05-23 10:15:15 -0400)
>
> are available in the Git repository at:
>
> git@source.denx.de:u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to 9358576a281ab5e3b7348685bbd5f713833a5048:
>
> drivers: pci: pcie_dw_common: fix Werror compilation error (2021-05-24 23:54:54 +0800)
>
> Gitlab CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7620
>
NAK.
ERROR: fdt or initrd relocation disabled at boot time
#993: FILE: include/configs/sifive-unmatched.h:65:
+ "fdt_high=0xffffffffffffffff\0" \
ERROR: fdt or initrd relocation disabled at boot time
#994: FILE: include/configs/sifive-unmatched.h:66:
+ "initrd_high=0xffffffffffffffff\0" \
You can, but shouldn't disable initrd relocation. You cannot disable
device tree relocation as that leads to too many issues due to
misalignment later. Make use of bootm_size or similar to make sure
everything is within an appropriate area of memory. Thanks.
--
Tom
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PULL] u-boot-riscv/master
2021-05-26 15:24 ` Tom Rini
@ 2021-05-27 8:57 ` Green Wan
2021-05-27 10:41 ` Leo Liang
0 siblings, 1 reply; 99+ messages in thread
From: Green Wan @ 2021-05-27 8:57 UTC (permalink / raw)
To: Tom Rini; +Cc: Leo Liang, Rick Chen, U-Boot Mailing List
Hi Tom,
Thanks for the comments.
Not sure whether it catches different concerns, I plan to remove fdt_high
and initrd_high since the bootm_* settings should be sufficient to
calculate the values related to fdt_high and initrd_high. And I checked the
bootm_* settings as below, the system can boot without fdt_high and
initrd_high.
- bootm_low is set to CONFIG_SYS_SDRAM_BASE
- bootm_size is set to gd->ram_size (which comes from DT)
- bootm_mapsize is now equal to bootm_size
- boot log without fdt_high and initrd_high
"## Flattened Device Tree blob at 88000000
Booting using the fdt blob at 0x88000000
Loading Device Tree to 00000000ffffa000, end 00000000fffff64d ... OK"
Hi Leo/Rick,
Should I create v12 for fu740 series patchset based on u-boot-riscv.git ?
or revert [PATCH v11 7/8] plus a patch? Thanks a lot!
Regards,
Green
On Wed, May 26, 2021 at 11:24 PM Tom Rini <trini@konsulko.com> wrote:
> On Wed, May 26, 2021 at 04:12:50PM +0800, Leo Liang wrote:
>
> > Hi Tom,
> >
> > The following changes since commit
> eb53b943be2949ca111140a8e05532cd74cda058:
> >
> > Merge https://source.denx.de/u-boot/custodians/u-boot-sh (2021-05-23
> 10:15:15 -0400)
> >
> > are available in the Git repository at:
> >
> > git@source.denx.de:u-boot/custodians/u-boot-riscv.git
> >
> > for you to fetch changes up to 9358576a281ab5e3b7348685bbd5f713833a5048:
> >
> > drivers: pci: pcie_dw_common: fix Werror compilation error (2021-05-24
> 23:54:54 +0800)
> >
> > Gitlab CI result shows no issue:
> https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7620
> >
>
> NAK.
> ERROR: fdt or initrd relocation disabled at boot time
> #993: FILE: include/configs/sifive-unmatched.h:65:
> + "fdt_high=0xffffffffffffffff\0" \
>
> ERROR: fdt or initrd relocation disabled at boot time
> #994: FILE: include/configs/sifive-unmatched.h:66:
> + "initrd_high=0xffffffffffffffff\0" \
>
> You can, but shouldn't disable initrd relocation. You cannot disable
> device tree relocation as that leads to too many issues due to
> misalignment later. Make use of bootm_size or similar to make sure
> everything is within an appropriate area of memory. Thanks.
>
> --
> Tom
>
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PULL] u-boot-riscv/master
2021-05-27 8:57 ` Green Wan
@ 2021-05-27 10:41 ` Leo Liang
2021-05-27 11:20 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-05-27 10:41 UTC (permalink / raw)
To: Green Wan
Cc: Tom Rini, Rick Jian-Zhi Chen(陳建志),
U-Boot Mailing List
On Thu, May 27, 2021 at 04:57:17PM +0800, Green Wan wrote:
> Hi Tom,
>
> Thanks for the comments.
>
> Not sure whether it catches different concerns, I plan to remove fdt_high and initrd_high since the bootm_* settings should be sufficient to calculate the values related to fdt_high and initrd_high. And I checked the bootm_* settings as below, the system can
> boot without fdt_high and initrd_high.
>
> - bootm_low is set to CONFIG_SYS_SDRAM_BASE
> - bootm_size is set to gd->ram_size (which comes from DT)
> - bootm_mapsize is now equal to bootm_size
> - boot log without fdt_high and initrd_high
> "## Flattened Device Tree blob at 88000000
> Booting using the fdt blob at 0x88000000
> Loading Device Tree to 00000000ffffa000, end 00000000fffff64d ... OK"
>
> Hi Leo/Rick,
>
> Should I create v12 for fu740 series patchset based on u-boot-riscv.git ? or revert [PATCH v11 7/8] plus a patch? Thanks a lot!
>
> Regards,
> Green
Hi Green,
I think you could just create v12 patch.
I will do the revert, thanks!
Best regards,
Leo
>
>
> > On Wed, May 26, 2021 at 11:24 PM Tom Rini <trini@konsulko.com> wrote:
> >
> >
> > On Wed, May 26, 2021 at 04:12:50PM +0800, Leo Liang wrote:
> >
> > Hi Tom,
> >
> > The following changes since commit eb53b943be2949ca111140a8e05532cd74cda058:
> >
> > Merge https://source.denx.de/u-boot/custodians/u-boot-sh (2021-05-23 10:15:15 -0400)
> >
> > are available in the Git repository at:
> >
> >
> > git@source.denx.de:u-boot/custodians/u-boot-riscv.git
> >
> > for you to fetch changes up to 9358576a281ab5e3b7348685bbd5f713833a5048:
> >
> > drivers: pci: pcie_dw_common: fix Werror compilation error (2021-05-24 23:54:54 +0800)
> >
> > Gitlab CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7620
>
> NAK.
> ERROR: fdt or initrd relocation disabled at boot time
> #993: FILE: include/configs/sifive-unmatched.h:65:
> + "fdt_high=0xffffffffffffffff\0" \
>
> ERROR: fdt or initrd relocation disabled at boot time
> #994: FILE: include/configs/sifive-unmatched.h:66:
> + "initrd_high=0xffffffffffffffff\0" \
>
> You can, but shouldn't disable initrd relocation. You cannot disable
> device tree relocation as that leads to too many issues due to
> misalignment later. Make use of bootm_size or similar to make sure
> everything is within an appropriate area of memory. Thanks.
>
> --
> Tom
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PULL] u-boot-riscv/master
2021-05-27 10:41 ` Leo Liang
@ 2021-05-27 11:20 ` Tom Rini
2021-05-27 13:56 ` Green Wan
0 siblings, 1 reply; 99+ messages in thread
From: Tom Rini @ 2021-05-27 11:20 UTC (permalink / raw)
To: Leo Liang
Cc: Green Wan, Rick Jian-Zhi Chen(陳建志),
U-Boot Mailing List
[-- Attachment #1: Type: text/plain, Size: 1234 bytes --]
On Thu, May 27, 2021 at 06:41:35PM +0800, Leo Liang wrote:
> On Thu, May 27, 2021 at 04:57:17PM +0800, Green Wan wrote:
> > Hi Tom,
> >
> > Thanks for the comments.
> >
> > Not sure whether it catches different concerns, I plan to remove fdt_high and initrd_high since the bootm_* settings should be sufficient to calculate the values related to fdt_high and initrd_high. And I checked the bootm_* settings as below, the system can
> > boot without fdt_high and initrd_high.
> >
> > - bootm_low is set to CONFIG_SYS_SDRAM_BASE
> > - bootm_size is set to gd->ram_size (which comes from DT)
> > - bootm_mapsize is now equal to bootm_size
> > - boot log without fdt_high and initrd_high
> > "## Flattened Device Tree blob at 88000000
> > Booting using the fdt blob at 0x88000000
> > Loading Device Tree to 00000000ffffa000, end 00000000fffff64d ... OK"
> >
> > Hi Leo/Rick,
> >
> > Should I create v12 for fu740 series patchset based on u-boot-riscv.git ? or revert [PATCH v11 7/8] plus a patch? Thanks a lot!
> >
> > Regards,
> > Green
>
> Hi Green,
>
> I think you could just create v12 patch.
> I will do the revert, thanks!
Thanks for sorting this out quickly!
--
Tom
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^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [PULL] u-boot-riscv/master
2021-05-27 11:20 ` Tom Rini
@ 2021-05-27 13:56 ` Green Wan
0 siblings, 0 replies; 99+ messages in thread
From: Green Wan @ 2021-05-27 13:56 UTC (permalink / raw)
To: Tom Rini
Cc: Leo Liang, Rick Jian-Zhi Chen(陳建志),
U-Boot Mailing List
On Thu, May 27, 2021 at 7:20 PM Tom Rini <trini@konsulko.com> wrote:
> On Thu, May 27, 2021 at 06:41:35PM +0800, Leo Liang wrote:
> > On Thu, May 27, 2021 at 04:57:17PM +0800, Green Wan wrote:
> > > Hi Tom,
> > >
> > > Thanks for the comments.
> > >
> > > Not sure whether it catches different concerns, I plan to remove
> fdt_high and initrd_high since the bootm_* settings should be
> sufficient to calculate the values related to fdt_high and initrd_high. And
> I checked the bootm_* settings as below, the system can
> > > boot without fdt_high and initrd_high.
> > >
> > > - bootm_low is set to CONFIG_SYS_SDRAM_BASE
> > > - bootm_size is set to gd->ram_size (which comes from DT)
> > > - bootm_mapsize is now equal to bootm_size
> > > - boot log without fdt_high and initrd_high
> > > "## Flattened Device Tree blob at 88000000
> > > Booting using the fdt blob at 0x88000000
> > > Loading Device Tree to 00000000ffffa000, end 00000000fffff64d ...
> OK"
> > >
> > > Hi Leo/Rick,
> > >
> > > Should I create v12 for fu740 series patchset based on
> u-boot-riscv.git ? or revert [PATCH v11 7/8] plus a patch? Thanks a lot!
> > >
> > > Regards,
> > > Green
> >
> > Hi Green,
> >
> > I think you could just create v12 patch.
> > I will do the revert, thanks!
>
Hi Leo,
Thanks for the help. I just posted the v12 patchset.
--
Green
>
> Thanks for sorting this out quickly!
>
> --
> Tom
>
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
@ 2021-05-20 2:19 Leo Liang
2021-05-21 14:07 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-05-20 2:19 UTC (permalink / raw)
To: u-boot
Hi Tom,
The following changes since commit 428bec7cf956c3558bbdfda4d2ba23beb73a68ba:
Merge branch '2021-05-17-assorted-fixes' (2021-05-18 14:17:54 -0400)
are available in the Git repository at:
git at source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to a4691f363ef75783bee626bb8337c3a34d8c0e96:
riscv: ae350: Increase malloc size for binman spl flow (2021-05-19 17:01:52 +0800)
Gitlab CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7583
----------------------------------------------------------------
Bin Meng (13):
common: kconfig: Correct a typo in SPL_LOAD_FIT
binman: Correct '-a' description in the doc
binman: Correct the comment for ATF entry type
binman: test: Rename 172_fit_fdt.dts to 170_fit_fdt.dts
binman: Add support for RISC-V OpenSBI fw_dynamic blob
makefile: Pass OpenSBI blob to binman make rules
riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb
lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED
binman: Support packaging U-Boot for scenarios like OF_BOARD or OF_PRIOR_STAGE
riscv: dts: Sort build targets in alphabetical order
riscv: qemu: Switch to use binman to generate u-boot.itb
riscv: ae350: Switch to use binman to generate u-boot.itb
riscv: Drop USE_SPL_FIT_GENERATOR
Rick Chen (1):
riscv: ae350: Increase malloc size for binman spl flow
Makefile | 4 +-
arch/riscv/cpu/generic/Kconfig | 1 +
arch/riscv/dts/Makefile | 3 +-
arch/riscv/dts/ae350_32.dts | 2 +
arch/riscv/dts/ae350_64.dts | 2 +
arch/riscv/dts/binman.dtsi | 78 ++++++++++++++++
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 1 +
arch/riscv/dts/qemu-virt.dts | 8 ++
arch/riscv/lib/mkimage_fit_opensbi.sh | 100 ---------------------
board/AndesTech/ax25-ae350/Kconfig | 1 +
board/sifive/unleashed/Kconfig | 1 +
common/Kconfig.boot | 5 +-
configs/ae350_rv32_spl_defconfig | 2 +
configs/ae350_rv32_spl_xip_defconfig | 2 +
configs/ae350_rv64_spl_defconfig | 2 +
configs/ae350_rv64_spl_xip_defconfig | 2 +
configs/qemu-riscv32_spl_defconfig | 1 +
configs/qemu-riscv64_spl_defconfig | 1 +
dts/Kconfig | 18 ++++
lib/Kconfig | 2 +-
tools/binman/binman.rst | 28 +++++-
tools/binman/entries.rst | 13 +++
tools/binman/etype/atf_bl31.py | 2 +-
tools/binman/etype/opensbi.py | 23 +++++
tools/binman/ftest.py | 17 ++--
.../test/{172_fit_fdt.dts => 170_fit_fdt.dts} | 0
tools/binman/test/201_opensbi.dts | 14 +++
27 files changed, 219 insertions(+), 114 deletions(-)
create mode 100644 arch/riscv/dts/binman.dtsi
create mode 100644 arch/riscv/dts/qemu-virt.dts
delete mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh
create mode 100644 tools/binman/etype/opensbi.py
rename tools/binman/test/{172_fit_fdt.dts => 170_fit_fdt.dts} (100%)
create mode 100644 tools/binman/test/201_opensbi.dts
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2021-05-18 1:48 Leo Liang
2021-05-18 18:17 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-05-18 1:48 UTC (permalink / raw)
To: u-boot
Hi Tom,
CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7572
The following changes since commit e644dfbb1786a4a3308b068e1f61cd9e2dfac237:
configs: Resync with savedefconfig (2021-05-15 08:10:13 -0400)
are available in the Git repository at:
git at source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 89419279f4fe6bfd68dd518059ef2007295f1cb4:
riscv: Group assembly optimized implementation of memory routines into a submenu (2021-05-17 16:47:33 +0800)
----------------------------------------------------------------
Bin Meng (4):
riscv: ax25-ae350: doc: Fix minor format issues
riscv: Split SiFive CLINT support between SPL and U-Boot proper
riscv: Fix memmove and optimise memcpy when misalign
riscv: Group assembly optimized implementation of memory routines into a submenu
Sean Anderson (1):
riscv: Fix arch_fixup_fdt always failing without /chosen
arch/riscv/Kconfig | 13 ++-
arch/riscv/cpu/fu540/Kconfig | 2 +-
arch/riscv/cpu/generic/Kconfig | 3 +-
arch/riscv/include/asm/global_data.h | 2 +-
arch/riscv/lib/Makefile | 2 +-
arch/riscv/lib/fdt_fixup.c | 11 ++-
arch/riscv/lib/memcpy.S | 223 +++++++++++++++++++++++++++++------------------
arch/riscv/lib/memmove.S | 176 +++++++++++++++++++++++++------------
doc/board/AndesTech/ax25-ae350.rst | 4 +-
drivers/timer/Makefile | 2 +-
10 files changed, 284 insertions(+), 154 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
@ 2021-05-14 11:10 Leo Liang
2021-05-14 12:23 ` Bin Meng
2021-05-15 12:09 ` Tom Rini
0 siblings, 2 replies; 99+ messages in thread
From: Leo Liang @ 2021-05-14 11:10 UTC (permalink / raw)
To: u-boot
Hi Tom,
CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7504
The following changes since commit 530c8d4af2e18c6142ab7cac6f11dd92c02b2bc9:
Merge branch '2021-05-13-extension-board-detection-and-DT-overlay-application' (2021-05-13 13:09:14 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to ffdc71bc0977c1e6b7b6e6a5a005e1f77213bf21:
Revert "riscv: cpu: fu740: clear feature disable CSR" (2021-05-14 16:26:20 +0800)
----------------------------------------------------------------
Bin Meng (1):
Revert "riscv: cpu: fu740: clear feature disable CSR"
Rick Chen (1):
MAINTAINERS: Add a co-maintainer for RISC-V
Sean Anderson (11):
clk: Warn on failure to assign rate
clk: k210: Fix PLLs not being enabled
clk: k210: Fix PLL enable always getting taken
clk: k210: Remove k210_register_pll
clk: k210: Move the clint clock to under aclk
clk: Add support for the k210 clock driver pre-relocation
riscv: Enable some devices pre-relocation
riscv: Enable AI ram on K210
riscv: k210: Rename airam to aisram
riscv: k210: Use AI as the parent clock of aisram, not PLL1
riscv: Don't reserve AI ram in k210 dts
Vincent Chen (1):
pwm: sifive: make set_config() and set_enable() work properly
MAINTAINERS | 1 +
arch/riscv/cpu/fu540/spl.c | 15 ---------------
arch/riscv/dts/k210.dtsi | 22 +++++++---------------
board/sipeed/maix/maix.c | 14 ++++++++++++--
configs/sipeed_maix_bitm_defconfig | 2 ++
drivers/clk/clk-uclass.c | 11 +++++++----
drivers/clk/kendryte/clk.c | 26 ++++++++++++++------------
drivers/clk/kendryte/pll.c | 26 ++++----------------------
drivers/pwm/pwm-sifive.c | 21 +++++++++++----------
include/configs/sipeed-maix.h | 3 +--
include/kendryte/pll.h | 4 ----
11 files changed, 59 insertions(+), 86 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
2021-05-14 11:10 Leo Liang
@ 2021-05-14 12:23 ` Bin Meng
2021-05-15 12:09 ` Tom Rini
1 sibling, 0 replies; 99+ messages in thread
From: Bin Meng @ 2021-05-14 12:23 UTC (permalink / raw)
To: u-boot
Hi Leo,
On Fri, May 14, 2021 at 7:10 PM Leo Liang <ycliang@andestech.com> wrote:
>
> Hi Tom,
>
> CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7504
>
> The following changes since commit 530c8d4af2e18c6142ab7cac6f11dd92c02b2bc9:
>
> Merge branch '2021-05-13-extension-board-detection-and-DT-overlay-application' (2021-05-13 13:09:14 -0400)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to ffdc71bc0977c1e6b7b6e6a5a005e1f77213bf21:
>
> Revert "riscv: cpu: fu740: clear feature disable CSR" (2021-05-14 16:26:20 +0800)
>
> ----------------------------------------------------------------
> Bin Meng (1):
> Revert "riscv: cpu: fu740: clear feature disable CSR"
The following patches are not applied. Without them, SiFive Unleashed
is still not bootable.
http://patchwork.ozlabs.org/project/uboot/patch/20210511120412.25065-1-bmeng.cn at gmail.com/
http://patchwork.ozlabs.org/project/uboot/list/?series=243574
Could you please apply ASAP?
Regards,
Bin
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
2021-05-14 11:10 Leo Liang
2021-05-14 12:23 ` Bin Meng
@ 2021-05-15 12:09 ` Tom Rini
1 sibling, 0 replies; 99+ messages in thread
From: Tom Rini @ 2021-05-15 12:09 UTC (permalink / raw)
To: u-boot
On Fri, May 14, 2021 at 07:10:10PM +0800, Leo Liang wrote:
> Hi Tom,
>
> CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7504
>
> The following changes since commit 530c8d4af2e18c6142ab7cac6f11dd92c02b2bc9:
>
> Merge branch '2021-05-13-extension-board-detection-and-DT-overlay-application' (2021-05-13 13:09:14 -0400)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to ffdc71bc0977c1e6b7b6e6a5a005e1f77213bf21:
>
> Revert "riscv: cpu: fu740: clear feature disable CSR" (2021-05-14 16:26:20 +0800)
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
@ 2021-05-07 1:06 Leo Liang
2021-05-07 1:09 ` Tom Rini
` (2 more replies)
0 siblings, 3 replies; 99+ messages in thread
From: Leo Liang @ 2021-05-07 1:06 UTC (permalink / raw)
To: u-boot
Hi Tom,
CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
----------------------------------------------------------------
Dylan Jhong (1):
atcspi200: Add timeout mechanism in spi_xfer()
Green Wan (2):
riscv: cpu: Add callback to init each core
riscv: cpu: fu740: clear feature disable CSR
Heinrich Schuchardt (1):
cmd/exception: support ebreak exception on RISC-V
arch/riscv/cpu/cpu.c | 11 +++++++++++
arch/riscv/cpu/fu540/spl.c | 15 +++++++++++++++
arch/riscv/cpu/start.S | 4 ++++
cmd/riscv/exception.c | 10 ++++++++++
doc/usage/exception.rst | 3 +++
drivers/spi/atcspi200_spi.c | 10 ++++++++--
6 files changed, 51 insertions(+), 2 deletions(-)
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread* [PULL] u-boot-riscv/master
2021-05-07 1:06 Leo Liang
@ 2021-05-07 1:09 ` Tom Rini
2021-05-07 1:41 ` Leo Liang
2021-05-07 1:49 ` Sean Anderson
2021-05-07 15:37 ` Tom Rini
2 siblings, 1 reply; 99+ messages in thread
From: Tom Rini @ 2021-05-07 1:09 UTC (permalink / raw)
To: u-boot
On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:
> Hi Tom,
>
> CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
>
> The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
>
> Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
>
> cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
>
> ----------------------------------------------------------------
> Dylan Jhong (1):
> atcspi200: Add timeout mechanism in spi_xfer()
>
> Green Wan (2):
> riscv: cpu: Add callback to init each core
> riscv: cpu: fu740: clear feature disable CSR
>
> Heinrich Schuchardt (1):
> cmd/exception: support ebreak exception on RISC-V
>
> arch/riscv/cpu/cpu.c | 11 +++++++++++
> arch/riscv/cpu/fu540/spl.c | 15 +++++++++++++++
> arch/riscv/cpu/start.S | 4 ++++
> cmd/riscv/exception.c | 10 ++++++++++
> doc/usage/exception.rst | 3 +++
> drivers/spi/atcspi200_spi.c | 10 ++++++++--
> 6 files changed, 51 insertions(+), 2 deletions(-)
Please note that currently
https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=&state=&q=&archive=&delegate=20174
shows 55 patches. Most of them have been posted long enough that I
would expect them to be applied if there's no further feedback. Can you
please take a look? Thanks!
--
Tom
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^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
2021-05-07 1:09 ` Tom Rini
@ 2021-05-07 1:41 ` Leo Liang
2021-05-07 1:55 ` Sean Anderson
2021-05-07 14:21 ` Dimitri John Ledkov
0 siblings, 2 replies; 99+ messages in thread
From: Leo Liang @ 2021-05-07 1:41 UTC (permalink / raw)
To: u-boot
On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote:
> On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:
>
> > Hi Tom,
> >
> > CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> >
> > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
> >
> > Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
> >
> > are available in the Git repository at:
> >
> > https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> >
> > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
> >
> > cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
> >
> > ----------------------------------------------------------------
> > Dylan Jhong (1):
> > atcspi200: Add timeout mechanism in spi_xfer()
> >
> > Green Wan (2):
> > riscv: cpu: Add callback to init each core
> > riscv: cpu: fu740: clear feature disable CSR
> >
> > Heinrich Schuchardt (1):
> > cmd/exception: support ebreak exception on RISC-V
> >
> > arch/riscv/cpu/cpu.c | 11 +++++++++++
> > arch/riscv/cpu/fu540/spl.c | 15 +++++++++++++++
> > arch/riscv/cpu/start.S | 4 ++++
> > cmd/riscv/exception.c | 10 ++++++++++
> > doc/usage/exception.rst | 3 +++
> > drivers/spi/atcspi200_spi.c | 10 ++++++++--
> > 6 files changed, 51 insertions(+), 2 deletions(-)
>
> Please note that currently
> https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=&state=&q=&archive=&delegate=20174
> shows 55 patches. Most of them have been posted long enough that I
> would expect them to be applied if there's no further feedback. Can you
> please take a look? Thanks!
>
No problem, sorry for the delay!
Two quick questions.
Some of the patches delegated to Andes do not own a RISC-V tag but rather clk or driver etc.
Do you mind if we pull them through RISC-V tree?
And for these patches,
do you prefer them pulled into this release or for-next branch?
Best regards,
Leo
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
2021-05-07 1:41 ` Leo Liang
@ 2021-05-07 1:55 ` Sean Anderson
2021-05-07 16:15 ` Tom Rini
2021-05-07 14:21 ` Dimitri John Ledkov
1 sibling, 1 reply; 99+ messages in thread
From: Sean Anderson @ 2021-05-07 1:55 UTC (permalink / raw)
To: u-boot
On 5/6/21 9:41 PM, Leo Liang wrote:
> On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote:
>> On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:
>>
>>> Hi Tom,
>>>
>>> CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
>>>
>>> The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
>>>
>>> Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
>>>
>>> are available in the Git repository at:
>>>
>>> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>>>
>>> for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
>>>
>>> cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
>>>
>>> ----------------------------------------------------------------
>>> Dylan Jhong (1):
>>> atcspi200: Add timeout mechanism in spi_xfer()
>>>
>>> Green Wan (2):
>>> riscv: cpu: Add callback to init each core
>>> riscv: cpu: fu740: clear feature disable CSR
>>>
>>> Heinrich Schuchardt (1):
>>> cmd/exception: support ebreak exception on RISC-V
>>>
>>> arch/riscv/cpu/cpu.c | 11 +++++++++++
>>> arch/riscv/cpu/fu540/spl.c | 15 +++++++++++++++
>>> arch/riscv/cpu/start.S | 4 ++++
>>> cmd/riscv/exception.c | 10 ++++++++++
>>> doc/usage/exception.rst | 3 +++
>>> drivers/spi/atcspi200_spi.c | 10 ++++++++--
>>> 6 files changed, 51 insertions(+), 2 deletions(-)
>>
>> Please note that currently
>> https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=&state=&q=&archive=&delegate=20174
>> shows 55 patches. Most of them have been posted long enough that I
>> would expect them to be applied if there's no further feedback. Can you
>> please take a look? Thanks!
>>
>
> No problem, sorry for the delay!
>
> Two quick questions.
>
> Some of the patches delegated to Andes do not own a RISC-V tag but rather clk or driver etc.
> Do you mind if we pull them through RISC-V tree?
Clock patches should go though Lukasz's tree, but given the scope of the
patches I think it is OK for them to be in RISC-V. I would like to get an
Acked-by from him, but unfortunately he hasn't commented on them at all.
--Sean
> And for these patches,
> do you prefer them pulled into this release or for-next branch?
>
> Best regards,
> Leo
>
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
2021-05-07 1:55 ` Sean Anderson
@ 2021-05-07 16:15 ` Tom Rini
0 siblings, 0 replies; 99+ messages in thread
From: Tom Rini @ 2021-05-07 16:15 UTC (permalink / raw)
To: u-boot
On Thu, May 06, 2021 at 09:55:17PM -0400, Sean Anderson wrote:
> On 5/6/21 9:41 PM, Leo Liang wrote:
> > On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote:
> > > On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:
> > >
> > > > Hi Tom,
> > > >
> > > > CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> > > >
> > > > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
> > > >
> > > > Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
> > > >
> > > > are available in the Git repository at:
> > > >
> > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> > > >
> > > > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
> > > >
> > > > cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
> > > >
> > > > ----------------------------------------------------------------
> > > > Dylan Jhong (1):
> > > > atcspi200: Add timeout mechanism in spi_xfer()
> > > >
> > > > Green Wan (2):
> > > > riscv: cpu: Add callback to init each core
> > > > riscv: cpu: fu740: clear feature disable CSR
> > > >
> > > > Heinrich Schuchardt (1):
> > > > cmd/exception: support ebreak exception on RISC-V
> > > >
> > > > arch/riscv/cpu/cpu.c | 11 +++++++++++
> > > > arch/riscv/cpu/fu540/spl.c | 15 +++++++++++++++
> > > > arch/riscv/cpu/start.S | 4 ++++
> > > > cmd/riscv/exception.c | 10 ++++++++++
> > > > doc/usage/exception.rst | 3 +++
> > > > drivers/spi/atcspi200_spi.c | 10 ++++++++--
> > > > 6 files changed, 51 insertions(+), 2 deletions(-)
> > >
> > > Please note that currently
> > > https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=&state=&q=&archive=&delegate=20174
> > > shows 55 patches. Most of them have been posted long enough that I
> > > would expect them to be applied if there's no further feedback. Can you
> > > please take a look? Thanks!
> > >
> >
> > No problem, sorry for the delay!
> >
> > Two quick questions.
> >
> > Some of the patches delegated to Andes do not own a RISC-V tag but rather clk or driver etc.
> > Do you mind if we pull them through RISC-V tree?
>
> Clock patches should go though Lukasz's tree, but given the scope of the
> patches I think it is OK for them to be in RISC-V. I would like to get an
> Acked-by from him, but unfortunately he hasn't commented on them at all.
In general, I believe it is OK for non-subsystem-core changes to go via
the architecture / SoC tree.
--
Tom
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^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
2021-05-07 1:41 ` Leo Liang
2021-05-07 1:55 ` Sean Anderson
@ 2021-05-07 14:21 ` Dimitri John Ledkov
2021-05-07 14:35 ` Tom Rini
1 sibling, 1 reply; 99+ messages in thread
From: Dimitri John Ledkov @ 2021-05-07 14:21 UTC (permalink / raw)
To: u-boot
Hi,
On Fri, May 7, 2021 at 2:42 AM Leo Liang <ycliang@andestech.com> wrote:
>
> On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote:
> > On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:
> >
> > > Hi Tom,
> > >
> > > CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> > >
> > > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
> > >
> > > Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
> > >
> > > are available in the Git repository at:
> > >
> > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> > >
> > > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
> > >
> > > cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
> > >
> > > ----------------------------------------------------------------
> > > Dylan Jhong (1):
> > > atcspi200: Add timeout mechanism in spi_xfer()
> > >
> > > Green Wan (2):
> > > riscv: cpu: Add callback to init each core
> > > riscv: cpu: fu740: clear feature disable CSR
> > >
> > > Heinrich Schuchardt (1):
> > > cmd/exception: support ebreak exception on RISC-V
> > >
> > > arch/riscv/cpu/cpu.c | 11 +++++++++++
> > > arch/riscv/cpu/fu540/spl.c | 15 +++++++++++++++
> > > arch/riscv/cpu/start.S | 4 ++++
> > > cmd/riscv/exception.c | 10 ++++++++++
> > > doc/usage/exception.rst | 3 +++
> > > drivers/spi/atcspi200_spi.c | 10 ++++++++--
> > > 6 files changed, 51 insertions(+), 2 deletions(-)
> >
> > Please note that currently
> > https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=&state=&q=&archive=&delegate=20174
> > shows 55 patches. Most of them have been posted long enough that I
> > would expect them to be applied if there's no further feedback. Can you
> > please take a look? Thanks!
> >
>
> No problem, sorry for the delay!
>
> Two quick questions.
>
> Some of the patches delegated to Andes do not own a RISC-V tag but rather clk or driver etc.
> Do you mind if we pull them through RISC-V tree?
>
> And for these patches,
> do you prefer them pulled into this release or for-next branch?
Although https://patchwork.ozlabs.org/project/uboot/patch/20210421114201.57994-1-xnox at ubuntu.com/
is not strictly for riscv64 it does prevent me from using the same
Ubuntu rootfs for riscv boards or qemu. I would appreciate it if it
could be pulled in via qemu or riscv maintainers.
--
Regards,
Dimitri.
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
2021-05-07 14:21 ` Dimitri John Ledkov
@ 2021-05-07 14:35 ` Tom Rini
0 siblings, 0 replies; 99+ messages in thread
From: Tom Rini @ 2021-05-07 14:35 UTC (permalink / raw)
To: u-boot
On Fri, May 07, 2021 at 03:21:13PM +0100, Dimitri John Ledkov wrote:
> Hi,
>
> On Fri, May 7, 2021 at 2:42 AM Leo Liang <ycliang@andestech.com> wrote:
> >
> > On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote:
> > > On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:
> > >
> > > > Hi Tom,
> > > >
> > > > CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> > > >
> > > > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
> > > >
> > > > Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
> > > >
> > > > are available in the Git repository at:
> > > >
> > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> > > >
> > > > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
> > > >
> > > > cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
> > > >
> > > > ----------------------------------------------------------------
> > > > Dylan Jhong (1):
> > > > atcspi200: Add timeout mechanism in spi_xfer()
> > > >
> > > > Green Wan (2):
> > > > riscv: cpu: Add callback to init each core
> > > > riscv: cpu: fu740: clear feature disable CSR
> > > >
> > > > Heinrich Schuchardt (1):
> > > > cmd/exception: support ebreak exception on RISC-V
> > > >
> > > > arch/riscv/cpu/cpu.c | 11 +++++++++++
> > > > arch/riscv/cpu/fu540/spl.c | 15 +++++++++++++++
> > > > arch/riscv/cpu/start.S | 4 ++++
> > > > cmd/riscv/exception.c | 10 ++++++++++
> > > > doc/usage/exception.rst | 3 +++
> > > > drivers/spi/atcspi200_spi.c | 10 ++++++++--
> > > > 6 files changed, 51 insertions(+), 2 deletions(-)
> > >
> > > Please note that currently
> > > https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=&state=&q=&archive=&delegate=20174
> > > shows 55 patches. Most of them have been posted long enough that I
> > > would expect them to be applied if there's no further feedback. Can you
> > > please take a look? Thanks!
> > >
> >
> > No problem, sorry for the delay!
> >
> > Two quick questions.
> >
> > Some of the patches delegated to Andes do not own a RISC-V tag but rather clk or driver etc.
> > Do you mind if we pull them through RISC-V tree?
> >
> > And for these patches,
> > do you prefer them pulled into this release or for-next branch?
>
>
> Although https://patchwork.ozlabs.org/project/uboot/patch/20210421114201.57994-1-xnox at ubuntu.com/
> is not strictly for riscv64 it does prevent me from using the same
> Ubuntu rootfs for riscv boards or qemu. I would appreciate it if it
> could be pulled in via qemu or riscv maintainers.
As that's a PXE change I've assigned it to the network maintainer, and
I've cc'd him here. Thanks.
--
Tom
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^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
2021-05-07 1:06 Leo Liang
2021-05-07 1:09 ` Tom Rini
@ 2021-05-07 1:49 ` Sean Anderson
2021-05-10 6:57 ` Leo Liang
2021-05-07 15:37 ` Tom Rini
2 siblings, 1 reply; 99+ messages in thread
From: Sean Anderson @ 2021-05-07 1:49 UTC (permalink / raw)
To: u-boot
Hi Leo,
Are you maintaining RISC-V now? Should I be CC-ing you on my series?
Can you update MAINTAINERS with this information? Thanks.
--Sean
On 5/6/21 9:06 PM, Leo Liang wrote:
> Hi Tom,
>
> CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
>
> The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
>
> Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
>
> cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
>
> ----------------------------------------------------------------
> Dylan Jhong (1):
> atcspi200: Add timeout mechanism in spi_xfer()
>
> Green Wan (2):
> riscv: cpu: Add callback to init each core
> riscv: cpu: fu740: clear feature disable CSR
>
> Heinrich Schuchardt (1):
> cmd/exception: support ebreak exception on RISC-V
>
> arch/riscv/cpu/cpu.c | 11 +++++++++++
> arch/riscv/cpu/fu540/spl.c | 15 +++++++++++++++
> arch/riscv/cpu/start.S | 4 ++++
> cmd/riscv/exception.c | 10 ++++++++++
> doc/usage/exception.rst | 3 +++
> drivers/spi/atcspi200_spi.c | 10 ++++++++--
> 6 files changed, 51 insertions(+), 2 deletions(-)
>
> Best regards,
> Leo
>
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
2021-05-07 1:49 ` Sean Anderson
@ 2021-05-10 6:57 ` Leo Liang
0 siblings, 0 replies; 99+ messages in thread
From: Leo Liang @ 2021-05-10 6:57 UTC (permalink / raw)
To: u-boot
On Fri, May 07, 2021 at 09:49:08AM +0800, Sean Anderson wrote:
> Hi Leo,
>
> Are you maintaining RISC-V now? Should I be CC-ing you on my series?
> Can you update MAINTAINERS with this information? Thanks.
>
> --Sean
>
Hi Sean,
Yes, I am now co-maintaining RISC-V tree with Rick.
I will update the information as soon as possible, thanks for the reminder.
And yes, please do CC your work to me, thanks again!
Best regards,
Leo
> On 5/6/21 9:06 PM, Leo Liang wrote:
> > Hi Tom,
> >
> > CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> >
> > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
> >
> > Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
> >
> > are available in the Git repository at:
> >
> > https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> >
> > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
> >
> > cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
> >
> > ----------------------------------------------------------------
> > Dylan Jhong (1):
> > atcspi200: Add timeout mechanism in spi_xfer()
> >
> > Green Wan (2):
> > riscv: cpu: Add callback to init each core
> > riscv: cpu: fu740: clear feature disable CSR
> >
> > Heinrich Schuchardt (1):
> > cmd/exception: support ebreak exception on RISC-V
> >
> > arch/riscv/cpu/cpu.c | 11 +++++++++++
> > arch/riscv/cpu/fu540/spl.c | 15 +++++++++++++++
> > arch/riscv/cpu/start.S | 4 ++++
> > cmd/riscv/exception.c | 10 ++++++++++
> > doc/usage/exception.rst | 3 +++
> > drivers/spi/atcspi200_spi.c | 10 ++++++++--
> > 6 files changed, 51 insertions(+), 2 deletions(-)
> >
> > Best regards,
> > Leo
> >
^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
2021-05-07 1:06 Leo Liang
2021-05-07 1:09 ` Tom Rini
2021-05-07 1:49 ` Sean Anderson
@ 2021-05-07 15:37 ` Tom Rini
2 siblings, 0 replies; 99+ messages in thread
From: Tom Rini @ 2021-05-07 15:37 UTC (permalink / raw)
To: u-boot
On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:
> Hi Tom,
>
> CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
>
> The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
>
> Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
>
> cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 99+ messages in thread
* [PULL] u-boot-riscv/master
@ 2021-04-08 10:44 Leo Liang
2021-04-08 19:36 ` Tom Rini
0 siblings, 1 reply; 99+ messages in thread
From: Leo Liang @ 2021-04-08 10:44 UTC (permalink / raw)
To: u-boot
Hi Tom,
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7078
The following changes since commit e9c99db7787e3b5c2ef05701177c43ed1c023c27:
Merge branch '2021-04-07-CI-improvements' (2021-04-07 15:54:07 -0400)
are available in the Git repository at:
git at source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to e7bb113cc4d03aeb573ff938a1d897d4b3ca99df:
riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodes (2021-04-08 15:37:30 +0800)
----------------------------------------------------------------
Bin Meng (5):
riscv: sifive: Rename fu540 board to unleashed
timer: sifive_clint: Support the official clint DT bindings
riscv: mpfs-icicle-kit: Increase SYS_MALLOC_F_LEN
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag
riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodes
Heinrich Schuchardt (4):
configs: EXT4, FAT, hush shell, env on S-mode MAIX
riscv: simplify longjmp
test: unit test for longjmp
riscv: assembler versions of memcpy, memmove, memset
Sean Anderson (7):
wdt: dw: Switch to using fls for log2
wdt: dw: Switch to if(CONFIG()) instead of using #if
wdt: dw: Enable the clock before using it
wdt: dw: Free the clock on error
riscv: Add watchdog bindings for the k210
riscv: Enable watchdog for the k210
riscv: Remove unused define in maix header
arch/riscv/Kconfig | 84 ++++++++++++++-
arch/riscv/dts/Makefile | 2 +-
arch/riscv/dts/k210.dtsi | 1 -
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 4 -
arch/riscv/include/asm/string.h | 36 +++----
arch/riscv/lib/Makefile | 4 +
arch/riscv/lib/memcpy.S | 108 ++++++++++++++++++++
arch/riscv/lib/memmove.S | 64 ++++++++++++
arch/riscv/lib/memset.S | 113 +++++++++++++++++++++
arch/riscv/lib/setjmp.S | 8 +-
board/sifive/{fu540 => unleashed}/Kconfig | 6 +-
board/sifive/{fu540 => unleashed}/MAINTAINERS | 10 +-
board/sifive/{fu540 => unleashed}/Makefile | 2 +-
board/sifive/{fu540 => unleashed}/spl.c | 0
.../{fu540/fu540.c => unleashed/unleashed.c} | 0
board/sipeed/maix/Kconfig | 2 +
common/spl/Kconfig | 5 +-
configs/microchip_mpfs_icicle_defconfig | 1 +
..._fu540_defconfig => sifive_unleashed_defconfig} | 2 +-
configs/sipeed_maix_smode_defconfig | 11 ++
doc/board/sifive/index.rst | 2 +-
doc/board/sifive/{fu540.rst => unleashed.rst} | 0
drivers/clk/microchip/mpfs_clk.c | 1 +
drivers/ram/sifive/Kconfig | 2 +-
drivers/reset/Kconfig | 2 +-
drivers/timer/sifive_clint_timer.c | 1 +
drivers/watchdog/designware_wdt.c | 37 ++++---
.../configs/{sifive-fu540.h => sifive-unleashed.h} | 0
include/configs/sipeed-maix.h | 3 -
test/lib/Makefile | 1 +
test/lib/longjmp.c | 73 +++++++++++++
31 files changed, 518 insertions(+), 67 deletions(-)
create mode 100644 arch/riscv/lib/memcpy.S
create mode 100644 arch/riscv/lib/memmove.S
create mode 100644 arch/riscv/lib/memset.S
rename board/sifive/{fu540 => unleashed}/Kconfig (91%)
rename board/sifive/{fu540 => unleashed}/MAINTAINERS (50%)
rename board/sifive/{fu540 => unleashed}/Makefile (87%)
rename board/sifive/{fu540 => unleashed}/spl.c (100%)
rename board/sifive/{fu540/fu540.c => unleashed/unleashed.c} (100%)
rename configs/{sifive_fu540_defconfig => sifive_unleashed_defconfig} (95%)
rename doc/board/sifive/{fu540.rst => unleashed.rst} (100%)
rename include/configs/{sifive-fu540.h => sifive-unleashed.h} (100%)
create mode 100644 test/lib/longjmp.c
Best regards,
Leo
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