* [PATCH v7 00/11] Update the Icicle Kit device tree
@ 2022-02-14 13:58 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
This series updates the Microchip Icicle Kit device tree by adding a
host of peripherals, and some updates to the memory map. In addition,
the device tree has been split into a third part, which contains "soft"
peripherals that are in the fpga fabric.
Several of the entries are for peripherals that have not get had their
drivers upstreamed, so in those cases the dt bindings are included where
appropriate in order to avoid the many "DT compatible string <x> appears
un-documented" errors.
Depends on mpfs clock driver binding (on clk/next) to provide
dt-bindings/clock/microchip,mpfs-clock.h for the device tree
and on the other changes to the icicle/mpfs device tree from geert
that are already in linux/riscv/for-next.
Additionally, the interrupt-extended warnings on the plic/clint are
cleared by [1] & [2].
[1] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/
[2] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/
Changes from v6:
- Dropped i2c patch, as its in i2c-next
- Added ack on gpio, reviewed-by on rtc
- Dropped child nodes from sysctrl binding entirely, added a link to
the online documenation for the services the system controller can
provide
- Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's
series
Changes from v5:
- reworded the descriptions in the pwm binding to (hopefully) add
clarity
- added -mask to the custom properties and made them 32 bit
- renamed the i2c binding to corei2c, since it is not mpfs specific
- removed the child nodes of the system controller in example/dts &
will create them in the driver.
@Rob, I assume keeping them documented is the correct thing to do?
- removed the dependancy on the clock binding from the examples
- reformatted rtc interrupts as per Rob's suggestion
Changes from v4:
- dont include icicle_kit_defconfig, accidentally added in v3
- drop prescaler from mpfs-rtc & calculate the value instead
- use corei2c as a fallback device for mpfs-i2c
- drop spi dt-binding (on spi-next)
commit 2da187304e556ac59cf2dacb323cc78ded988169
- drop usb dt-binding (on usb-next)
Changes from v3:
- drop "mailbox: change mailbox-mpfs compatible string", already upstream:
commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
- fix copy paste error in microchip,mpfs-mailbox dt-binding
- remove whitespace in syscontroller dt entry
Changes from v2:
- dropped plic int header & corresponding defines in dts{,i}
- use $ref to drmode in mpfs-musb binding
- split changes to dts{,i} again: functional changes to existing
elements now are in a new patch
- drop num-cs property in mpfs-spi binding
- dont make the system controller a simple-mfd
- move the separate bindings for rng/generic system services into the
system controller binding
- added an instance corei2c as i2c2 in the fabric dtsi
- add version numbering to corepwm and corei2c compat string (-rtl-vN)
Conor Dooley (11):
dt-bindings: soc/microchip: update syscontroller compatibles
dt-bindings: soc/microchip: add info about services to mpfs sysctrl
dt-bindings: rtc: add bindings for microchip mpfs rtc
dt-bindings: gpio: add bindings for microchip mpfs gpio
dt-bindings: pwm: add microchip corepwm binding
riscv: dts: microchip: use clk defines for icicle kit
riscv: dts: microchip: add fpga fabric section to icicle kit
riscv: dts: microchip: refactor icicle kit device tree
riscv: dts: microchip: update peripherals in icicle kit device tree
riscv: dts: microchip: add new peripherals to icicle kit device tree
MAINTAINERS: update riscv/microchip entry
.../bindings/gpio/microchip,mpfs-gpio.yaml | 79 ++++++
...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +-
.../bindings/pwm/microchip,corepwm.yaml | 81 ++++++
.../bindings/rtc/microchip,mfps-rtc.yaml | 58 ++++
.../microchip,mpfs-sys-controller.yaml | 40 +++
...icrochip,polarfire-soc-sys-controller.yaml | 35 ---
MAINTAINERS | 2 +
.../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++
.../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++--
.../boot/dts/microchip/microchip-mpfs.dtsi | 254 ++++++++++++++----
10 files changed, 591 insertions(+), 104 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
--
2.35.1
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v7 00/11] Update the Icicle Kit device tree
@ 2022-02-14 13:58 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
This series updates the Microchip Icicle Kit device tree by adding a
host of peripherals, and some updates to the memory map. In addition,
the device tree has been split into a third part, which contains "soft"
peripherals that are in the fpga fabric.
Several of the entries are for peripherals that have not get had their
drivers upstreamed, so in those cases the dt bindings are included where
appropriate in order to avoid the many "DT compatible string <x> appears
un-documented" errors.
Depends on mpfs clock driver binding (on clk/next) to provide
dt-bindings/clock/microchip,mpfs-clock.h for the device tree
and on the other changes to the icicle/mpfs device tree from geert
that are already in linux/riscv/for-next.
Additionally, the interrupt-extended warnings on the plic/clint are
cleared by [1] & [2].
[1] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/
[2] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/
Changes from v6:
- Dropped i2c patch, as its in i2c-next
- Added ack on gpio, reviewed-by on rtc
- Dropped child nodes from sysctrl binding entirely, added a link to
the online documenation for the services the system controller can
provide
- Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's
series
Changes from v5:
- reworded the descriptions in the pwm binding to (hopefully) add
clarity
- added -mask to the custom properties and made them 32 bit
- renamed the i2c binding to corei2c, since it is not mpfs specific
- removed the child nodes of the system controller in example/dts &
will create them in the driver.
@Rob, I assume keeping them documented is the correct thing to do?
- removed the dependancy on the clock binding from the examples
- reformatted rtc interrupts as per Rob's suggestion
Changes from v4:
- dont include icicle_kit_defconfig, accidentally added in v3
- drop prescaler from mpfs-rtc & calculate the value instead
- use corei2c as a fallback device for mpfs-i2c
- drop spi dt-binding (on spi-next)
commit 2da187304e556ac59cf2dacb323cc78ded988169
- drop usb dt-binding (on usb-next)
Changes from v3:
- drop "mailbox: change mailbox-mpfs compatible string", already upstream:
commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
- fix copy paste error in microchip,mpfs-mailbox dt-binding
- remove whitespace in syscontroller dt entry
Changes from v2:
- dropped plic int header & corresponding defines in dts{,i}
- use $ref to drmode in mpfs-musb binding
- split changes to dts{,i} again: functional changes to existing
elements now are in a new patch
- drop num-cs property in mpfs-spi binding
- dont make the system controller a simple-mfd
- move the separate bindings for rng/generic system services into the
system controller binding
- added an instance corei2c as i2c2 in the fabric dtsi
- add version numbering to corepwm and corei2c compat string (-rtl-vN)
Conor Dooley (11):
dt-bindings: soc/microchip: update syscontroller compatibles
dt-bindings: soc/microchip: add info about services to mpfs sysctrl
dt-bindings: rtc: add bindings for microchip mpfs rtc
dt-bindings: gpio: add bindings for microchip mpfs gpio
dt-bindings: pwm: add microchip corepwm binding
riscv: dts: microchip: use clk defines for icicle kit
riscv: dts: microchip: add fpga fabric section to icicle kit
riscv: dts: microchip: refactor icicle kit device tree
riscv: dts: microchip: update peripherals in icicle kit device tree
riscv: dts: microchip: add new peripherals to icicle kit device tree
MAINTAINERS: update riscv/microchip entry
.../bindings/gpio/microchip,mpfs-gpio.yaml | 79 ++++++
...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +-
.../bindings/pwm/microchip,corepwm.yaml | 81 ++++++
.../bindings/rtc/microchip,mfps-rtc.yaml | 58 ++++
.../microchip,mpfs-sys-controller.yaml | 40 +++
...icrochip,polarfire-soc-sys-controller.yaml | 35 ---
MAINTAINERS | 2 +
.../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++
.../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++--
.../boot/dts/microchip/microchip-mpfs.dtsi | 254 ++++++++++++++----
10 files changed, 591 insertions(+), 104 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v7 01/11] dt-bindings: soc/microchip: update syscontroller compatibles
2022-02-14 13:58 ` conor.dooley
@ 2022-02-14 13:58 ` conor.dooley
-1 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Rob Herring, Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
The Polarfire SoC is currently using two different compatible string
prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in
its system controller in order to match the compatible string used in
the soc binding and device tree
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
...larfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +++---
...s-controller.yaml => microchip,mpfs-sys-controller.yaml} | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
rename Documentation/devicetree/bindings/soc/microchip/{microchip,polarfire-soc-sys-controller.yaml => microchip,mpfs-sys-controller.yaml} (75%)
diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
similarity index 82%
rename from Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
rename to Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
index bbb173ea483c..082d397d3e89 100644
--- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#"
+$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
@@ -11,7 +11,7 @@ maintainers:
properties:
compatible:
- const: microchip,polarfire-soc-mailbox
+ const: microchip,mpfs-mailbox
reg:
items:
@@ -38,7 +38,7 @@ examples:
#address-cells = <2>;
#size-cells = <2>;
mbox: mailbox@37020000 {
- compatible = "microchip,polarfire-soc-mailbox";
+ compatible = "microchip,mpfs-mailbox";
reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;
interrupt-parent = <&L1>;
interrupts = <96>;
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
similarity index 75%
rename from Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
rename to Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
index 2cd3bc6bd8d6..f699772fedf3 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/soc/microchip/microchip,polarfire-soc-sys-controller.yaml#"
+$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
@@ -19,7 +19,7 @@ properties:
maxItems: 1
compatible:
- const: microchip,polarfire-soc-sys-controller
+ const: microchip,mpfs-sys-controller
required:
- compatible
@@ -30,6 +30,6 @@ additionalProperties: false
examples:
- |
syscontroller: syscontroller {
- compatible = "microchip,polarfire-soc-sys-controller";
+ compatible = "microchip,mpfs-sys-controller";
mboxes = <&mbox 0>;
};
--
2.35.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 01/11] dt-bindings: soc/microchip: update syscontroller compatibles
@ 2022-02-14 13:58 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Rob Herring, Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
The Polarfire SoC is currently using two different compatible string
prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in
its system controller in order to match the compatible string used in
the soc binding and device tree
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
...larfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +++---
...s-controller.yaml => microchip,mpfs-sys-controller.yaml} | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
rename Documentation/devicetree/bindings/soc/microchip/{microchip,polarfire-soc-sys-controller.yaml => microchip,mpfs-sys-controller.yaml} (75%)
diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
similarity index 82%
rename from Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
rename to Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
index bbb173ea483c..082d397d3e89 100644
--- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#"
+$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
@@ -11,7 +11,7 @@ maintainers:
properties:
compatible:
- const: microchip,polarfire-soc-mailbox
+ const: microchip,mpfs-mailbox
reg:
items:
@@ -38,7 +38,7 @@ examples:
#address-cells = <2>;
#size-cells = <2>;
mbox: mailbox@37020000 {
- compatible = "microchip,polarfire-soc-mailbox";
+ compatible = "microchip,mpfs-mailbox";
reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;
interrupt-parent = <&L1>;
interrupts = <96>;
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
similarity index 75%
rename from Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
rename to Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
index 2cd3bc6bd8d6..f699772fedf3 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/soc/microchip/microchip,polarfire-soc-sys-controller.yaml#"
+$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
@@ -19,7 +19,7 @@ properties:
maxItems: 1
compatible:
- const: microchip,polarfire-soc-sys-controller
+ const: microchip,mpfs-sys-controller
required:
- compatible
@@ -30,6 +30,6 @@ additionalProperties: false
examples:
- |
syscontroller: syscontroller {
- compatible = "microchip,polarfire-soc-sys-controller";
+ compatible = "microchip,mpfs-sys-controller";
mboxes = <&mbox 0>;
};
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 02/11] dt-bindings: soc/microchip: add info about services to mpfs sysctrl
2022-02-14 13:58 ` conor.dooley
@ 2022-02-14 13:58 ` conor.dooley
-1 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
The services actually provided by the system controller are not
documented so add some words about what the system controller can
actually do. Add a link to the oneline documentation with the specific
details of each individual service.
Also, drop the unneeded label from the example.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../soc/microchip/microchip,mpfs-sys-controller.yaml | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
index f699772fedf3..b0dae51e1d42 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
@@ -10,9 +10,14 @@ maintainers:
- Conor Dooley <conor.dooley@microchip.com>
description: |
- The PolarFire SoC system controller is communicated with via a mailbox.
- This document describes the bindings for the client portion of that mailbox.
+ PolarFire SoC devices include a microcontroller acting as the system controller,
+ which provides "services" to the main processor and to the FPGA fabric. These
+ services include hardware rng, reprogramming of the FPGA and verfification of the
+ eNVM contents etc. More information on these services can be found online, at
+ https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
+ Communication with the system controller is done via a mailbox, of which the client
+ portion is documented here.
properties:
mboxes:
@@ -29,7 +34,7 @@ additionalProperties: false
examples:
- |
- syscontroller: syscontroller {
+ syscontroller {
compatible = "microchip,mpfs-sys-controller";
mboxes = <&mbox 0>;
};
--
2.35.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 02/11] dt-bindings: soc/microchip: add info about services to mpfs sysctrl
@ 2022-02-14 13:58 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
The services actually provided by the system controller are not
documented so add some words about what the system controller can
actually do. Add a link to the oneline documentation with the specific
details of each individual service.
Also, drop the unneeded label from the example.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../soc/microchip/microchip,mpfs-sys-controller.yaml | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
index f699772fedf3..b0dae51e1d42 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
@@ -10,9 +10,14 @@ maintainers:
- Conor Dooley <conor.dooley@microchip.com>
description: |
- The PolarFire SoC system controller is communicated with via a mailbox.
- This document describes the bindings for the client portion of that mailbox.
+ PolarFire SoC devices include a microcontroller acting as the system controller,
+ which provides "services" to the main processor and to the FPGA fabric. These
+ services include hardware rng, reprogramming of the FPGA and verfification of the
+ eNVM contents etc. More information on these services can be found online, at
+ https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
+ Communication with the system controller is done via a mailbox, of which the client
+ portion is documented here.
properties:
mboxes:
@@ -29,7 +34,7 @@ additionalProperties: false
examples:
- |
- syscontroller: syscontroller {
+ syscontroller {
compatible = "microchip,mpfs-sys-controller";
mboxes = <&mbox 0>;
};
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc
2022-02-14 13:58 ` conor.dooley
@ 2022-02-14 13:58 ` conor.dooley
-1 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt, Rob Herring
From: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the real time clock on
the Microchip PolarFire SoC.
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
new file mode 100644
index 000000000000..a2e984ea3553
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
+
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
+
+allOf:
+ - $ref: rtc.yaml#
+
+maintainers:
+ - Daire McNamara <daire.mcnamara@microchip.com>
+ - Lewis Hanly <lewis.hanly@microchip.com>
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: |
+ RTC_WAKEUP interrupt
+ - description: |
+ RTC_MATCH, asserted when the content of the Alarm register is equal
+ to that of the RTC's count register.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: rtc
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ rtc@20124000 {
+ compatible = "microchip,mpfs-rtc";
+ reg = <0x20124000 0x1000>;
+ clocks = <&clkcfg 21>;
+ clock-names = "rtc";
+ interrupts = <80>, <81>;
+ };
+...
--
2.35.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc
@ 2022-02-14 13:58 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt, Rob Herring
From: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the real time clock on
the Microchip PolarFire SoC.
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
new file mode 100644
index 000000000000..a2e984ea3553
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
+
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
+
+allOf:
+ - $ref: rtc.yaml#
+
+maintainers:
+ - Daire McNamara <daire.mcnamara@microchip.com>
+ - Lewis Hanly <lewis.hanly@microchip.com>
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: |
+ RTC_WAKEUP interrupt
+ - description: |
+ RTC_MATCH, asserted when the content of the Alarm register is equal
+ to that of the RTC's count register.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: rtc
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ rtc@20124000 {
+ compatible = "microchip,mpfs-rtc";
+ reg = <0x20124000 0x1000>;
+ clocks = <&clkcfg 21>;
+ clock-names = "rtc";
+ interrupts = <80>, <81>;
+ };
+...
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 04/11] dt-bindings: gpio: add bindings for microchip mpfs gpio
2022-02-14 13:58 ` conor.dooley
@ 2022-02-14 13:58 ` conor.dooley
-1 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Rob Herring, Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the gpio controller on
the Microchip PolarFire SoC.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
.../bindings/gpio/microchip,mpfs-gpio.yaml | 79 +++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
new file mode 100644
index 000000000000..110651eafa70
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS GPIO Controller Device Tree Bindings
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - microchip,mpfs-gpio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
+ minItems: 1
+ maxItems: 32
+
+ interrupt-controller: true
+
+ clocks:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ "#interrupt-cells":
+ const: 1
+
+ ngpios:
+ description:
+ The number of GPIOs available.
+ minimum: 1
+ maximum: 32
+ default: 32
+
+ gpio-controller: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#interrupt-cells"
+ - interrupt-controller
+ - "#gpio-cells"
+ - gpio-controller
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x20122000 0x1000>;
+ clocks = <&clkcfg 25>;
+ interrupt-parent = <&plic>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ };
+...
--
2.35.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 04/11] dt-bindings: gpio: add bindings for microchip mpfs gpio
@ 2022-02-14 13:58 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Rob Herring, Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the gpio controller on
the Microchip PolarFire SoC.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
.../bindings/gpio/microchip,mpfs-gpio.yaml | 79 +++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
new file mode 100644
index 000000000000..110651eafa70
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS GPIO Controller Device Tree Bindings
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - microchip,mpfs-gpio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
+ minItems: 1
+ maxItems: 32
+
+ interrupt-controller: true
+
+ clocks:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ "#interrupt-cells":
+ const: 1
+
+ ngpios:
+ description:
+ The number of GPIOs available.
+ minimum: 1
+ maximum: 32
+ default: 32
+
+ gpio-controller: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#interrupt-cells"
+ - interrupt-controller
+ - "#gpio-cells"
+ - gpio-controller
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x20122000 0x1000>;
+ clocks = <&clkcfg 25>;
+ interrupt-parent = <&plic>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ };
+...
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
2022-02-14 13:58 ` conor.dooley
@ 2022-02-14 13:58 ` conor.dooley
-1 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Rob Herring, Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the Microchip fpga fabric based "core" PWM
controller.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../bindings/pwm/microchip,corepwm.yaml | 81 +++++++++++++++++++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
new file mode 100644
index 000000000000..a7fae1772a81
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip IP corePWM controller bindings
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+description: |
+ corePWM is an 16 channel pulse width modulator FPGA IP
+
+ https://www.microsemi.com/existing-parts/parts/152118
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: microchip,corepwm-rtl-v4
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+ microchip,sync-update-mask:
+ description: |
+ Depending on how the IP is instantiated, there are two modes of operation.
+ In synchronous mode, all channels are updated at the beginning of the PWM period,
+ and in asynchronous mode updates happen as the control registers are written.
+ A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
+ mode is possible for each channel, and is set by the bitstream programmed to the
+ FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
+ control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
+ At runtime a bit wide register exposed to APB can be used to toggle on/off
+ synchronised mode for all channels it has been synthesised for.
+ Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
+ whether synchronous mode is possible for the PWM channel.
+
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+ microchip,dac-mode-mask:
+ description: |
+ Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
+ a minimum period pulse train whose High/Low average is that of the chosen duty
+ cycle. This "DAC" will have far better bandwidth and ripple performance than the
+ standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
+ core, set at instantiation and by the bitstream programmed to the FPGA, determines
+ whether a given channel operates in regular PWM or DAC mode.
+ Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
+ for that channel.
+
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ pwm@41000000 {
+ compatible = "microchip,corepwm-rtl-v4";
+ microchip,sync-update-mask = /bits/ 32 <0>;
+ clocks = <&clkcfg 30>;
+ reg = <0x41000000 0xF0>;
+ #pwm-cells = <2>;
+ };
--
2.35.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
@ 2022-02-14 13:58 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Rob Herring, Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the Microchip fpga fabric based "core" PWM
controller.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../bindings/pwm/microchip,corepwm.yaml | 81 +++++++++++++++++++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
new file mode 100644
index 000000000000..a7fae1772a81
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip IP corePWM controller bindings
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+description: |
+ corePWM is an 16 channel pulse width modulator FPGA IP
+
+ https://www.microsemi.com/existing-parts/parts/152118
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: microchip,corepwm-rtl-v4
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+ microchip,sync-update-mask:
+ description: |
+ Depending on how the IP is instantiated, there are two modes of operation.
+ In synchronous mode, all channels are updated at the beginning of the PWM period,
+ and in asynchronous mode updates happen as the control registers are written.
+ A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
+ mode is possible for each channel, and is set by the bitstream programmed to the
+ FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
+ control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
+ At runtime a bit wide register exposed to APB can be used to toggle on/off
+ synchronised mode for all channels it has been synthesised for.
+ Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
+ whether synchronous mode is possible for the PWM channel.
+
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+ microchip,dac-mode-mask:
+ description: |
+ Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
+ a minimum period pulse train whose High/Low average is that of the chosen duty
+ cycle. This "DAC" will have far better bandwidth and ripple performance than the
+ standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
+ core, set at instantiation and by the bitstream programmed to the FPGA, determines
+ whether a given channel operates in regular PWM or DAC mode.
+ Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
+ for that channel.
+
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ pwm@41000000 {
+ compatible = "microchip,corepwm-rtl-v4";
+ microchip,sync-update-mask = /bits/ 32 <0>;
+ clocks = <&clkcfg 30>;
+ reg = <0x41000000 0xF0>;
+ #pwm-cells = <2>;
+ };
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 06/11] riscv: dts: microchip: use clk defines for icicle kit
2022-02-14 13:58 ` conor.dooley
@ 2022-02-14 13:58 ` conor.dooley
-1 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Update the Microchip Icicle kit device tree by replacing clock
related magic numbers with their defined counterparts.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 2 +-
.../boot/dts/microchip/microchip-mpfs.dtsi | 25 ++++++++++---------
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 0c748ae1b006..6d19ba196f12 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -31,7 +31,7 @@ cpus {
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
- clocks = <&clkcfg 26>;
+ clocks = <&clkcfg CLK_DDRC>;
};
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 869aaf0d5c06..717e39b30a15 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -2,6 +2,7 @@
/* Copyright (c) 2020 Microchip Technology Inc */
/dts-v1/;
+#include "dt-bindings/clock/microchip,mpfs-clock.h"
/ {
#address-cells = <2>;
@@ -14,7 +15,6 @@ cpus {
#size-cells = <0>;
cpu@0 {
- clock-frequency = <0>;
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
@@ -22,6 +22,7 @@ cpu@0 {
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&clkcfg CLK_CPU>;
status = "disabled";
cpu0_intc: interrupt-controller {
@@ -32,7 +33,6 @@ cpu0_intc: interrupt-controller {
};
cpu@1 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -48,6 +48,7 @@ cpu@1 {
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -59,7 +60,6 @@ cpu1_intc: interrupt-controller {
};
cpu@2 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -75,6 +75,7 @@ cpu@2 {
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -86,7 +87,6 @@ cpu2_intc: interrupt-controller {
};
cpu@3 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -102,6 +102,7 @@ cpu@3 {
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -113,7 +114,6 @@ cpu3_intc: interrupt-controller {
};
cpu@4 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -129,6 +129,7 @@ cpu@4 {
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
cpu4_intc: interrupt-controller {
@@ -210,7 +211,7 @@ serial0: serial@20000000 {
interrupt-parent = <&plic>;
interrupts = <90>;
current-speed = <115200>;
- clocks = <&clkcfg 8>;
+ clocks = <&clkcfg CLK_MMUART0>;
status = "disabled";
};
@@ -222,7 +223,7 @@ serial1: serial@20100000 {
interrupt-parent = <&plic>;
interrupts = <91>;
current-speed = <115200>;
- clocks = <&clkcfg 9>;
+ clocks = <&clkcfg CLK_MMUART1>;
status = "disabled";
};
@@ -234,7 +235,7 @@ serial2: serial@20102000 {
interrupt-parent = <&plic>;
interrupts = <92>;
current-speed = <115200>;
- clocks = <&clkcfg 10>;
+ clocks = <&clkcfg CLK_MMUART2>;
status = "disabled";
};
@@ -246,7 +247,7 @@ serial3: serial@20104000 {
interrupt-parent = <&plic>;
interrupts = <93>;
current-speed = <115200>;
- clocks = <&clkcfg 11>;
+ clocks = <&clkcfg CLK_MMUART3>;
status = "disabled";
};
@@ -256,7 +257,7 @@ mmc: mmc@20008000 {
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <88>, <89>;
- clocks = <&clkcfg 6>;
+ clocks = <&clkcfg CLK_MMC>;
max-frequency = <200000000>;
status = "disabled";
};
@@ -267,7 +268,7 @@ emac0: ethernet@20110000 {
interrupt-parent = <&plic>;
interrupts = <64>, <65>, <66>, <67>;
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg 4>, <&clkcfg 2>;
+ clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
status = "disabled";
#address-cells = <1>;
@@ -280,7 +281,7 @@ emac1: ethernet@20112000 {
interrupt-parent = <&plic>;
interrupts = <70>, <71>, <72>, <73>;
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg 5>, <&clkcfg 2>;
+ clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
status = "disabled";
clock-names = "pclk", "hclk";
#address-cells = <1>;
--
2.35.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 06/11] riscv: dts: microchip: use clk defines for icicle kit
@ 2022-02-14 13:58 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Update the Microchip Icicle kit device tree by replacing clock
related magic numbers with their defined counterparts.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 2 +-
.../boot/dts/microchip/microchip-mpfs.dtsi | 25 ++++++++++---------
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 0c748ae1b006..6d19ba196f12 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -31,7 +31,7 @@ cpus {
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
- clocks = <&clkcfg 26>;
+ clocks = <&clkcfg CLK_DDRC>;
};
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 869aaf0d5c06..717e39b30a15 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -2,6 +2,7 @@
/* Copyright (c) 2020 Microchip Technology Inc */
/dts-v1/;
+#include "dt-bindings/clock/microchip,mpfs-clock.h"
/ {
#address-cells = <2>;
@@ -14,7 +15,6 @@ cpus {
#size-cells = <0>;
cpu@0 {
- clock-frequency = <0>;
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
@@ -22,6 +22,7 @@ cpu@0 {
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&clkcfg CLK_CPU>;
status = "disabled";
cpu0_intc: interrupt-controller {
@@ -32,7 +33,6 @@ cpu0_intc: interrupt-controller {
};
cpu@1 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -48,6 +48,7 @@ cpu@1 {
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -59,7 +60,6 @@ cpu1_intc: interrupt-controller {
};
cpu@2 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -75,6 +75,7 @@ cpu@2 {
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -86,7 +87,6 @@ cpu2_intc: interrupt-controller {
};
cpu@3 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -102,6 +102,7 @@ cpu@3 {
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -113,7 +114,6 @@ cpu3_intc: interrupt-controller {
};
cpu@4 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -129,6 +129,7 @@ cpu@4 {
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
cpu4_intc: interrupt-controller {
@@ -210,7 +211,7 @@ serial0: serial@20000000 {
interrupt-parent = <&plic>;
interrupts = <90>;
current-speed = <115200>;
- clocks = <&clkcfg 8>;
+ clocks = <&clkcfg CLK_MMUART0>;
status = "disabled";
};
@@ -222,7 +223,7 @@ serial1: serial@20100000 {
interrupt-parent = <&plic>;
interrupts = <91>;
current-speed = <115200>;
- clocks = <&clkcfg 9>;
+ clocks = <&clkcfg CLK_MMUART1>;
status = "disabled";
};
@@ -234,7 +235,7 @@ serial2: serial@20102000 {
interrupt-parent = <&plic>;
interrupts = <92>;
current-speed = <115200>;
- clocks = <&clkcfg 10>;
+ clocks = <&clkcfg CLK_MMUART2>;
status = "disabled";
};
@@ -246,7 +247,7 @@ serial3: serial@20104000 {
interrupt-parent = <&plic>;
interrupts = <93>;
current-speed = <115200>;
- clocks = <&clkcfg 11>;
+ clocks = <&clkcfg CLK_MMUART3>;
status = "disabled";
};
@@ -256,7 +257,7 @@ mmc: mmc@20008000 {
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <88>, <89>;
- clocks = <&clkcfg 6>;
+ clocks = <&clkcfg CLK_MMC>;
max-frequency = <200000000>;
status = "disabled";
};
@@ -267,7 +268,7 @@ emac0: ethernet@20110000 {
interrupt-parent = <&plic>;
interrupts = <64>, <65>, <66>, <67>;
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg 4>, <&clkcfg 2>;
+ clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
status = "disabled";
#address-cells = <1>;
@@ -280,7 +281,7 @@ emac1: ethernet@20112000 {
interrupt-parent = <&plic>;
interrupts = <70>, <71>, <72>, <73>;
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg 5>, <&clkcfg 2>;
+ clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
status = "disabled";
clock-names = "pclk", "hclk";
#address-cells = <1>;
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 07/11] riscv: dts: microchip: add fpga fabric section to icicle kit
2022-02-14 13:58 ` conor.dooley
@ 2022-02-14 13:58 ` conor.dooley
-1 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Split the device tree for the Microchip MPFS into two sections by adding
microchip-mpfs-fabric.dtsi, which contains peripherals contained in the
FPGA fabric.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../dts/microchip/microchip-mpfs-fabric.dtsi | 25 +++++++++++++++++++
.../microchip/microchip-mpfs-icicle-kit.dts | 8 ++++++
.../boot/dts/microchip/microchip-mpfs.dtsi | 1 +
3 files changed, 34 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
new file mode 100644
index 000000000000..854320e17b28
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/ {
+ core_pwm0: pwm@41000000 {
+ compatible = "microchip,corepwm-rtl-v4";
+ reg = <0x0 0x41000000 0x0 0xF0>;
+ microchip,sync-update-mask = /bits/ 32 <0>;
+ #pwm-cells = <2>;
+ clocks = <&clkcfg CLK_FIC3>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@44000000 {
+ compatible = "microchip,corei2c-rtl-v7";
+ reg = <0x0 0x44000000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkcfg CLK_FIC3>;
+ interrupt-parent = <&plic>;
+ interrupts = <122>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 6d19ba196f12..ab803f71626a 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -68,6 +68,10 @@ &mmc {
sd-uhs-sdr104;
};
+&i2c2 {
+ status = "okay";
+};
+
&emac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
@@ -86,3 +90,7 @@ phy1: ethernet-phy@9 {
ti,fifo-depth = <0x01>;
};
};
+
+&core_pwm0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 717e39b30a15..c7d73756c9b8 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -3,6 +3,7 @@
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
+#include "microchip-mpfs-fabric.dtsi"
/ {
#address-cells = <2>;
--
2.35.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 07/11] riscv: dts: microchip: add fpga fabric section to icicle kit
@ 2022-02-14 13:58 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Split the device tree for the Microchip MPFS into two sections by adding
microchip-mpfs-fabric.dtsi, which contains peripherals contained in the
FPGA fabric.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../dts/microchip/microchip-mpfs-fabric.dtsi | 25 +++++++++++++++++++
.../microchip/microchip-mpfs-icicle-kit.dts | 8 ++++++
.../boot/dts/microchip/microchip-mpfs.dtsi | 1 +
3 files changed, 34 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
new file mode 100644
index 000000000000..854320e17b28
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/ {
+ core_pwm0: pwm@41000000 {
+ compatible = "microchip,corepwm-rtl-v4";
+ reg = <0x0 0x41000000 0x0 0xF0>;
+ microchip,sync-update-mask = /bits/ 32 <0>;
+ #pwm-cells = <2>;
+ clocks = <&clkcfg CLK_FIC3>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@44000000 {
+ compatible = "microchip,corei2c-rtl-v7";
+ reg = <0x0 0x44000000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkcfg CLK_FIC3>;
+ interrupt-parent = <&plic>;
+ interrupts = <122>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 6d19ba196f12..ab803f71626a 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -68,6 +68,10 @@ &mmc {
sd-uhs-sdr104;
};
+&i2c2 {
+ status = "okay";
+};
+
&emac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
@@ -86,3 +90,7 @@ phy1: ethernet-phy@9 {
ti,fifo-depth = <0x01>;
};
};
+
+&core_pwm0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 717e39b30a15..c7d73756c9b8 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -3,6 +3,7 @@
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
+#include "microchip-mpfs-fabric.dtsi"
/ {
#address-cells = <2>;
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 08/11] riscv: dts: microchip: refactor icicle kit device tree
2022-02-14 13:58 ` conor.dooley
@ 2022-02-14 13:58 ` conor.dooley
-1 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Assorted minor changes to the MPFS/Icicle kit device tree:
- rename serial to mmuart to match microchip documentation
- move phy0 inside mac1 node to match phy configuration
- add labels where missing (cpus, cache controller)
- add missing address cells & interrupts to MACs
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 37 ++++++-----
.../boot/dts/microchip/microchip-mpfs.dtsi | 65 +++++++++----------
2 files changed, 52 insertions(+), 50 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index ab803f71626a..c51bd7cf500f 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
@@ -13,11 +13,11 @@ / {
compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
- ethernet0 = &emac1;
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
+ ethernet0 = &mac1;
+ serial0 = &mmuart0;
+ serial1 = &mmuart1;
+ serial2 = &mmuart2;
+ serial3 = &mmuart3;
};
chosen {
@@ -39,19 +39,19 @@ &refclk {
clock-frequency = <600000000>;
};
-&serial0 {
+&mmuart0 {
status = "okay";
};
-&serial1 {
+&mmuart1 {
status = "okay";
};
-&serial2 {
+&mmuart2 {
status = "okay";
};
-&serial3 {
+&mmuart3 {
status = "okay";
};
@@ -61,7 +61,10 @@ &mmc {
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
+ cap-mmc-highspeed;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
@@ -72,22 +75,22 @@ &i2c2 {
status = "okay";
};
-&emac0 {
+&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
- phy0: ethernet-phy@8 {
- reg = <8>;
- ti,fifo-depth = <0x01>;
- };
};
-&emac1 {
+&mac1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
phy1: ethernet-phy@9 {
reg = <9>;
- ti,fifo-depth = <0x01>;
+ ti,fifo-depth = <0x1>;
+ };
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ ti,fifo-depth = <0x1>;
};
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index c7d73756c9b8..62bd00092bcc 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
@@ -15,7 +15,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
@@ -33,7 +33,7 @@ cpu0_intc: interrupt-controller {
};
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -60,7 +60,7 @@ cpu1_intc: interrupt-controller {
};
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -87,7 +87,7 @@ cpu2_intc: interrupt-controller {
};
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -114,7 +114,7 @@ cpu3_intc: interrupt-controller {
};
};
- cpu@4 {
+ cpu4: cpu@4 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -152,8 +152,9 @@ soc {
compatible = "simple-bus";
ranges;
- cache-controller@2010000 {
+ cctrllr: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
+ reg = <0x0 0x2010000 0x0 0x1000>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
@@ -161,10 +162,9 @@ cache-controller@2010000 {
cache-unified;
interrupt-parent = <&plic>;
interrupts = <1>, <2>, <3>;
- reg = <0x0 0x2010000 0x0 0x1000>;
};
- clint@2000000 {
+ clint: clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
@@ -174,6 +174,15 @@ clint@2000000 {
<&cpu4_intc 3>, <&cpu4_intc 7>;
};
+ dma@3000000 {
+ compatible = "sifive,fu540-c000-pdma";
+ reg = <0x0 0x3000000 0x0 0x8000>;
+ interrupt-parent = <&plic>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>;
+ #dma-cells = <1>;
+ };
+
plic: interrupt-controller@c000000 {
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
@@ -188,15 +197,6 @@ plic: interrupt-controller@c000000 {
riscv,ndev = <186>;
};
- dma@3000000 {
- compatible = "sifive,fu540-c000-pdma";
- reg = <0x0 0x3000000 0x0 0x8000>;
- interrupt-parent = <&plic>;
- interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
- <30>;
- #dma-cells = <1>;
- };
-
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
@@ -204,7 +204,7 @@ clkcfg: clkcfg@20002000 {
#clock-cells = <1>;
};
- serial0: serial@20000000 {
+ mmuart0: serial@20000000 {
compatible = "ns16550a";
reg = <0x0 0x20000000 0x0 0x400>;
reg-io-width = <4>;
@@ -216,7 +216,7 @@ serial0: serial@20000000 {
status = "disabled";
};
- serial1: serial@20100000 {
+ mmuart1: serial@20100000 {
compatible = "ns16550a";
reg = <0x0 0x20100000 0x0 0x400>;
reg-io-width = <4>;
@@ -228,7 +228,7 @@ serial1: serial@20100000 {
status = "disabled";
};
- serial2: serial@20102000 {
+ mmuart2: serial@20102000 {
compatible = "ns16550a";
reg = <0x0 0x20102000 0x0 0x400>;
reg-io-width = <4>;
@@ -240,7 +240,7 @@ serial2: serial@20102000 {
status = "disabled";
};
- serial3: serial@20104000 {
+ mmuart3: serial@20104000 {
compatible = "ns16550a";
reg = <0x0 0x20104000 0x0 0x400>;
reg-io-width = <4>;
@@ -257,37 +257,36 @@ mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
- interrupts = <88>, <89>;
+ interrupts = <88>;
clocks = <&clkcfg CLK_MMC>;
max-frequency = <200000000>;
status = "disabled";
};
- emac0: ethernet@20110000 {
+ mac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupt-parent = <&plic>;
- interrupts = <64>, <65>, <66>, <67>;
+ interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
};
- emac1: ethernet@20112000 {
+ mac1: ethernet@20112000 {
compatible = "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupt-parent = <&plic>;
- interrupts = <70>, <71>, <72>, <73>;
+ interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
- status = "disabled";
clock-names = "pclk", "hclk";
- #address-cells = <1>;
- #size-cells = <0>;
+ status = "disabled";
};
-
};
};
--
2.35.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 08/11] riscv: dts: microchip: refactor icicle kit device tree
@ 2022-02-14 13:58 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Assorted minor changes to the MPFS/Icicle kit device tree:
- rename serial to mmuart to match microchip documentation
- move phy0 inside mac1 node to match phy configuration
- add labels where missing (cpus, cache controller)
- add missing address cells & interrupts to MACs
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 37 ++++++-----
.../boot/dts/microchip/microchip-mpfs.dtsi | 65 +++++++++----------
2 files changed, 52 insertions(+), 50 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index ab803f71626a..c51bd7cf500f 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
@@ -13,11 +13,11 @@ / {
compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
- ethernet0 = &emac1;
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
+ ethernet0 = &mac1;
+ serial0 = &mmuart0;
+ serial1 = &mmuart1;
+ serial2 = &mmuart2;
+ serial3 = &mmuart3;
};
chosen {
@@ -39,19 +39,19 @@ &refclk {
clock-frequency = <600000000>;
};
-&serial0 {
+&mmuart0 {
status = "okay";
};
-&serial1 {
+&mmuart1 {
status = "okay";
};
-&serial2 {
+&mmuart2 {
status = "okay";
};
-&serial3 {
+&mmuart3 {
status = "okay";
};
@@ -61,7 +61,10 @@ &mmc {
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
+ cap-mmc-highspeed;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
@@ -72,22 +75,22 @@ &i2c2 {
status = "okay";
};
-&emac0 {
+&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
- phy0: ethernet-phy@8 {
- reg = <8>;
- ti,fifo-depth = <0x01>;
- };
};
-&emac1 {
+&mac1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
phy1: ethernet-phy@9 {
reg = <9>;
- ti,fifo-depth = <0x01>;
+ ti,fifo-depth = <0x1>;
+ };
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ ti,fifo-depth = <0x1>;
};
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index c7d73756c9b8..62bd00092bcc 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
@@ -15,7 +15,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
@@ -33,7 +33,7 @@ cpu0_intc: interrupt-controller {
};
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -60,7 +60,7 @@ cpu1_intc: interrupt-controller {
};
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -87,7 +87,7 @@ cpu2_intc: interrupt-controller {
};
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -114,7 +114,7 @@ cpu3_intc: interrupt-controller {
};
};
- cpu@4 {
+ cpu4: cpu@4 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -152,8 +152,9 @@ soc {
compatible = "simple-bus";
ranges;
- cache-controller@2010000 {
+ cctrllr: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
+ reg = <0x0 0x2010000 0x0 0x1000>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
@@ -161,10 +162,9 @@ cache-controller@2010000 {
cache-unified;
interrupt-parent = <&plic>;
interrupts = <1>, <2>, <3>;
- reg = <0x0 0x2010000 0x0 0x1000>;
};
- clint@2000000 {
+ clint: clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
@@ -174,6 +174,15 @@ clint@2000000 {
<&cpu4_intc 3>, <&cpu4_intc 7>;
};
+ dma@3000000 {
+ compatible = "sifive,fu540-c000-pdma";
+ reg = <0x0 0x3000000 0x0 0x8000>;
+ interrupt-parent = <&plic>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>;
+ #dma-cells = <1>;
+ };
+
plic: interrupt-controller@c000000 {
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
@@ -188,15 +197,6 @@ plic: interrupt-controller@c000000 {
riscv,ndev = <186>;
};
- dma@3000000 {
- compatible = "sifive,fu540-c000-pdma";
- reg = <0x0 0x3000000 0x0 0x8000>;
- interrupt-parent = <&plic>;
- interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
- <30>;
- #dma-cells = <1>;
- };
-
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
@@ -204,7 +204,7 @@ clkcfg: clkcfg@20002000 {
#clock-cells = <1>;
};
- serial0: serial@20000000 {
+ mmuart0: serial@20000000 {
compatible = "ns16550a";
reg = <0x0 0x20000000 0x0 0x400>;
reg-io-width = <4>;
@@ -216,7 +216,7 @@ serial0: serial@20000000 {
status = "disabled";
};
- serial1: serial@20100000 {
+ mmuart1: serial@20100000 {
compatible = "ns16550a";
reg = <0x0 0x20100000 0x0 0x400>;
reg-io-width = <4>;
@@ -228,7 +228,7 @@ serial1: serial@20100000 {
status = "disabled";
};
- serial2: serial@20102000 {
+ mmuart2: serial@20102000 {
compatible = "ns16550a";
reg = <0x0 0x20102000 0x0 0x400>;
reg-io-width = <4>;
@@ -240,7 +240,7 @@ serial2: serial@20102000 {
status = "disabled";
};
- serial3: serial@20104000 {
+ mmuart3: serial@20104000 {
compatible = "ns16550a";
reg = <0x0 0x20104000 0x0 0x400>;
reg-io-width = <4>;
@@ -257,37 +257,36 @@ mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
- interrupts = <88>, <89>;
+ interrupts = <88>;
clocks = <&clkcfg CLK_MMC>;
max-frequency = <200000000>;
status = "disabled";
};
- emac0: ethernet@20110000 {
+ mac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupt-parent = <&plic>;
- interrupts = <64>, <65>, <66>, <67>;
+ interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
};
- emac1: ethernet@20112000 {
+ mac1: ethernet@20112000 {
compatible = "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupt-parent = <&plic>;
- interrupts = <70>, <71>, <72>, <73>;
+ interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
- status = "disabled";
clock-names = "pclk", "hclk";
- #address-cells = <1>;
- #size-cells = <0>;
+ status = "disabled";
};
-
};
};
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 09/11] riscv: dts: microchip: update peripherals in icicle kit device tree
2022-02-14 13:58 ` conor.dooley
@ 2022-02-14 13:58 ` conor.dooley
-1 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Assorted minor changes to the MPFS/Icicle kit device tree:
- enable mmuart4 instead of mmuart0
- remove sifive pdma
- split memory node to match updated fpga design
- move stdout path to serial1 to avoid collision with
bootloader running on the e51
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 23 +++++++++++++------
.../boot/dts/microchip/microchip-mpfs.dtsi | 23 +++++++++++--------
2 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index c51bd7cf500f..dc5f351b10c4 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -18,20 +18,29 @@ aliases {
serial1 = &mmuart1;
serial2 = &mmuart2;
serial3 = &mmuart3;
+ serial4 = &mmuart4;
};
chosen {
- stdout-path = "serial0:115200n8";
+ stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
- memory@80000000 {
+ ddrc_cache_lo: memory@80000000 {
device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x40000000>;
+ reg = <0x0 0x80000000 0x0 0x2e000000>;
clocks = <&clkcfg CLK_DDRC>;
+ status = "okay";
+ };
+
+ ddrc_cache_hi: memory@1000000000 {
+ device_type = "memory";
+ reg = <0x10 0x0 0x0 0x40000000>;
+ clocks = <&clkcfg CLK_DDRC>;
+ status = "okay";
};
};
@@ -39,10 +48,6 @@ &refclk {
clock-frequency = <600000000>;
};
-&mmuart0 {
- status = "okay";
-};
-
&mmuart1 {
status = "okay";
};
@@ -55,6 +60,10 @@ &mmuart3 {
status = "okay";
};
+&mmuart4 {
+ status = "okay";
+};
+
&mmc {
status = "okay";
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 62bd00092bcc..5e7aaaf42cde 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -174,15 +174,6 @@ clint: clint@2000000 {
<&cpu4_intc 3>, <&cpu4_intc 7>;
};
- dma@3000000 {
- compatible = "sifive,fu540-c000-pdma";
- reg = <0x0 0x3000000 0x0 0x8000>;
- interrupt-parent = <&plic>;
- interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
- <30>;
- #dma-cells = <1>;
- };
-
plic: interrupt-controller@c000000 {
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
@@ -213,7 +204,7 @@ mmuart0: serial@20000000 {
interrupts = <90>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART0>;
- status = "disabled";
+ status = "disabled"; /* Reserved for the HSS */
};
mmuart1: serial@20100000 {
@@ -252,6 +243,18 @@ mmuart3: serial@20104000 {
status = "disabled";
};
+ mmuart4: serial@20106000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20106000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <94>;
+ clocks = <&clkcfg CLK_MMUART4>;
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
/* Common node entry for emmc/sd */
mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
--
2.35.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 09/11] riscv: dts: microchip: update peripherals in icicle kit device tree
@ 2022-02-14 13:58 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Assorted minor changes to the MPFS/Icicle kit device tree:
- enable mmuart4 instead of mmuart0
- remove sifive pdma
- split memory node to match updated fpga design
- move stdout path to serial1 to avoid collision with
bootloader running on the e51
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 23 +++++++++++++------
.../boot/dts/microchip/microchip-mpfs.dtsi | 23 +++++++++++--------
2 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index c51bd7cf500f..dc5f351b10c4 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -18,20 +18,29 @@ aliases {
serial1 = &mmuart1;
serial2 = &mmuart2;
serial3 = &mmuart3;
+ serial4 = &mmuart4;
};
chosen {
- stdout-path = "serial0:115200n8";
+ stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
- memory@80000000 {
+ ddrc_cache_lo: memory@80000000 {
device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x40000000>;
+ reg = <0x0 0x80000000 0x0 0x2e000000>;
clocks = <&clkcfg CLK_DDRC>;
+ status = "okay";
+ };
+
+ ddrc_cache_hi: memory@1000000000 {
+ device_type = "memory";
+ reg = <0x10 0x0 0x0 0x40000000>;
+ clocks = <&clkcfg CLK_DDRC>;
+ status = "okay";
};
};
@@ -39,10 +48,6 @@ &refclk {
clock-frequency = <600000000>;
};
-&mmuart0 {
- status = "okay";
-};
-
&mmuart1 {
status = "okay";
};
@@ -55,6 +60,10 @@ &mmuart3 {
status = "okay";
};
+&mmuart4 {
+ status = "okay";
+};
+
&mmc {
status = "okay";
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 62bd00092bcc..5e7aaaf42cde 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -174,15 +174,6 @@ clint: clint@2000000 {
<&cpu4_intc 3>, <&cpu4_intc 7>;
};
- dma@3000000 {
- compatible = "sifive,fu540-c000-pdma";
- reg = <0x0 0x3000000 0x0 0x8000>;
- interrupt-parent = <&plic>;
- interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
- <30>;
- #dma-cells = <1>;
- };
-
plic: interrupt-controller@c000000 {
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
@@ -213,7 +204,7 @@ mmuart0: serial@20000000 {
interrupts = <90>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART0>;
- status = "disabled";
+ status = "disabled"; /* Reserved for the HSS */
};
mmuart1: serial@20100000 {
@@ -252,6 +243,18 @@ mmuart3: serial@20104000 {
status = "disabled";
};
+ mmuart4: serial@20106000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20106000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <94>;
+ clocks = <&clkcfg CLK_MMUART4>;
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
/* Common node entry for emmc/sd */
mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 10/11] riscv: dts: microchip: add new peripherals to icicle kit device tree
2022-02-14 13:58 ` conor.dooley
@ 2022-02-14 13:58 ` conor.dooley
-1 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Add new peripherals to the MPFS, and enable them in the Icicle kit
device tree:
2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller,
USB host & system controller.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 53 ++++++
.../boot/dts/microchip/microchip-mpfs.dtsi | 160 ++++++++++++++++++
2 files changed, 213 insertions(+)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index dc5f351b10c4..cd2fe80fa81a 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -80,6 +80,26 @@ &mmc {
sd-uhs-sdr104;
};
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
&i2c2 {
status = "okay";
};
@@ -103,6 +123,39 @@ phy0: ethernet-phy@8 {
};
};
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&mbox {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
&core_pwm0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 5e7aaaf42cde..c5c9d1360de0 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -266,6 +266,66 @@ mmc: mmc@20008000 {
status = "disabled";
};
+ spi0: spi@20108000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20108000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <54>;
+ clocks = <&clkcfg CLK_SPI0>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ spi1: spi@20109000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20109000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <55>;
+ clocks = <&clkcfg CLK_SPI1>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ qspi: spi@21000000 {
+ compatible = "microchip,mpfs-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21000000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <85>;
+ clocks = <&clkcfg CLK_QSPI>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2010a000 {
+ compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
+ reg = <0x0 0x2010a000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <58>;
+ clocks = <&clkcfg CLK_I2C0>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010b000 {
+ compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
+ reg = <0x0 0x2010b000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <61>;
+ clocks = <&clkcfg CLK_I2C1>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
mac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
@@ -291,5 +351,105 @@ mac1: ethernet@20112000 {
clock-names = "pclk", "hclk";
status = "disabled";
};
+
+ gpio0: gpio@20120000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20120000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@20121000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <000 0x20121000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20122000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ rtc: rtc@20124000 {
+ compatible = "microchip,mpfs-rtc";
+ reg = <0x0 0x20124000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <80>, <81>;
+ clocks = <&clkcfg CLK_RTC>;
+ clock-names = "rtc";
+ status = "disabled";
+ };
+
+ usb: usb@20201000 {
+ compatible = "microchip,mpfs-musb";
+ reg = <0x0 0x20201000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <86>, <87>;
+ clocks = <&clkcfg CLK_USB>;
+ interrupt-names = "dma","mc";
+ status = "disabled";
+ };
+
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
+ clock-names = "fic0", "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ microchip,axi-m-atr0 = <0x10 0x0>;
+ status = "disabled";
+ pcie_intc: legacy-interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ mbox: mailbox@37020000 {
+ compatible = "microchip,mpfs-mailbox";
+ reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
+ interrupt-parent = <&plic>;
+ interrupts = <96>;
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ syscontroller: syscontroller {
+ compatible = "microchip,mpfs-sys-controller";
+ mboxes = <&mbox 0>;
+ };
};
};
--
2.35.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 10/11] riscv: dts: microchip: add new peripherals to icicle kit device tree
@ 2022-02-14 13:58 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Add new peripherals to the MPFS, and enable them in the Icicle kit
device tree:
2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller,
USB host & system controller.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 53 ++++++
.../boot/dts/microchip/microchip-mpfs.dtsi | 160 ++++++++++++++++++
2 files changed, 213 insertions(+)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index dc5f351b10c4..cd2fe80fa81a 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -80,6 +80,26 @@ &mmc {
sd-uhs-sdr104;
};
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
&i2c2 {
status = "okay";
};
@@ -103,6 +123,39 @@ phy0: ethernet-phy@8 {
};
};
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&mbox {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
&core_pwm0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 5e7aaaf42cde..c5c9d1360de0 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -266,6 +266,66 @@ mmc: mmc@20008000 {
status = "disabled";
};
+ spi0: spi@20108000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20108000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <54>;
+ clocks = <&clkcfg CLK_SPI0>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ spi1: spi@20109000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20109000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <55>;
+ clocks = <&clkcfg CLK_SPI1>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ qspi: spi@21000000 {
+ compatible = "microchip,mpfs-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21000000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <85>;
+ clocks = <&clkcfg CLK_QSPI>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2010a000 {
+ compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
+ reg = <0x0 0x2010a000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <58>;
+ clocks = <&clkcfg CLK_I2C0>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010b000 {
+ compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
+ reg = <0x0 0x2010b000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <61>;
+ clocks = <&clkcfg CLK_I2C1>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
mac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
@@ -291,5 +351,105 @@ mac1: ethernet@20112000 {
clock-names = "pclk", "hclk";
status = "disabled";
};
+
+ gpio0: gpio@20120000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20120000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@20121000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <000 0x20121000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20122000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ rtc: rtc@20124000 {
+ compatible = "microchip,mpfs-rtc";
+ reg = <0x0 0x20124000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <80>, <81>;
+ clocks = <&clkcfg CLK_RTC>;
+ clock-names = "rtc";
+ status = "disabled";
+ };
+
+ usb: usb@20201000 {
+ compatible = "microchip,mpfs-musb";
+ reg = <0x0 0x20201000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <86>, <87>;
+ clocks = <&clkcfg CLK_USB>;
+ interrupt-names = "dma","mc";
+ status = "disabled";
+ };
+
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
+ clock-names = "fic0", "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ microchip,axi-m-atr0 = <0x10 0x0>;
+ status = "disabled";
+ pcie_intc: legacy-interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ mbox: mailbox@37020000 {
+ compatible = "microchip,mpfs-mailbox";
+ reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
+ interrupt-parent = <&plic>;
+ interrupts = <96>;
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ syscontroller: syscontroller {
+ compatible = "microchip,mpfs-sys-controller";
+ mboxes = <&mbox 0>;
+ };
};
};
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 11/11] MAINTAINERS: update riscv/microchip entry
2022-02-14 13:58 ` conor.dooley
@ 2022-02-14 13:58 ` conor.dooley
-1 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Update the RISC-V/Microchip entry by adding the microchip dts
directory and myself as maintainer
Reviewed-by: Lewis Hanly <lewis.hanly@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ea3e6c914384..779a550dc95b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16575,8 +16575,10 @@ K: riscv
RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
M: Lewis Hanly <lewis.hanly@microchip.com>
+M: Conor Dooley <conor.dooley@microchip.com>
L: linux-riscv@lists.infradead.org
S: Supported
+F: arch/riscv/boot/dts/microchip/
F: drivers/mailbox/mailbox-mpfs.c
F: drivers/soc/microchip/
F: include/soc/microchip/mpfs.h
--
2.35.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v7 11/11] MAINTAINERS: update riscv/microchip entry
@ 2022-02-14 13:58 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-14 13:58 UTC (permalink / raw)
To: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, krzysztof.kozlowski,
linux-gpio, devicetree, linux-kernel, linux-pwm, linux-rtc,
linux-riscv
Cc: lewis.hanly, conor.dooley, daire.mcnamara, ivan.griffin, atishp,
Palmer Dabbelt
From: Conor Dooley <conor.dooley@microchip.com>
Update the RISC-V/Microchip entry by adding the microchip dts
directory and myself as maintainer
Reviewed-by: Lewis Hanly <lewis.hanly@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ea3e6c914384..779a550dc95b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16575,8 +16575,10 @@ K: riscv
RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
M: Lewis Hanly <lewis.hanly@microchip.com>
+M: Conor Dooley <conor.dooley@microchip.com>
L: linux-riscv@lists.infradead.org
S: Supported
+F: arch/riscv/boot/dts/microchip/
F: drivers/mailbox/mailbox-mpfs.c
F: drivers/soc/microchip/
F: include/soc/microchip/mpfs.h
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 64+ messages in thread
* Re: [PATCH v7 02/11] dt-bindings: soc/microchip: add info about services to mpfs sysctrl
2022-02-14 13:58 ` conor.dooley
@ 2022-02-21 7:40 ` Conor.Dooley
-1 siblings, 0 replies; 64+ messages in thread
From: Conor.Dooley @ 2022-02-21 7:40 UTC (permalink / raw)
To: robh+dt
Cc: linus.walleij, Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp,
brgl, jassisinghbrar, thierry.reding, u.kleine-koenig, lee.jones,
a.zummo, alexandre.belloni, paul.walmsley, palmer, aou, geert,
krzysztof.kozlowski, linux-gpio, devicetree, linux-kernel,
linux-pwm, linux-rtc, linux-riscv
Hey Rob,
I removed the children and added a link to the documentation for the
services. Could you take a look and see if this version meets your approval?
Thanks.
Conor
On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The services actually provided by the system controller are not
> documented so add some words about what the system controller can
> actually do. Add a link to the oneline documentation with the specific
> details of each individual service.
> Also, drop the unneeded label from the example.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../soc/microchip/microchip,mpfs-sys-controller.yaml | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> index f699772fedf3..b0dae51e1d42 100644
> --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> @@ -10,9 +10,14 @@ maintainers:
> - Conor Dooley <conor.dooley@microchip.com>
>
> description: |
> - The PolarFire SoC system controller is communicated with via a mailbox.
> - This document describes the bindings for the client portion of that mailbox.
> + PolarFire SoC devices include a microcontroller acting as the system controller,
> + which provides "services" to the main processor and to the FPGA fabric. These
> + services include hardware rng, reprogramming of the FPGA and verfification of the
> + eNVM contents etc. More information on these services can be found online, at
> + https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
>
> + Communication with the system controller is done via a mailbox, of which the client
> + portion is documented here.
>
> properties:
> mboxes:
> @@ -29,7 +34,7 @@ additionalProperties: false
>
> examples:
> - |
> - syscontroller: syscontroller {
> + syscontroller {
> compatible = "microchip,mpfs-sys-controller";
> mboxes = <&mbox 0>;
> };
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 02/11] dt-bindings: soc/microchip: add info about services to mpfs sysctrl
@ 2022-02-21 7:40 ` Conor.Dooley
0 siblings, 0 replies; 64+ messages in thread
From: Conor.Dooley @ 2022-02-21 7:40 UTC (permalink / raw)
To: robh+dt
Cc: linus.walleij, Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp,
brgl, jassisinghbrar, thierry.reding, u.kleine-koenig, lee.jones,
a.zummo, alexandre.belloni, paul.walmsley, palmer, aou, geert,
krzysztof.kozlowski, linux-gpio, devicetree, linux-kernel,
linux-pwm, linux-rtc, linux-riscv
Hey Rob,
I removed the children and added a link to the documentation for the
services. Could you take a look and see if this version meets your approval?
Thanks.
Conor
On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The services actually provided by the system controller are not
> documented so add some words about what the system controller can
> actually do. Add a link to the oneline documentation with the specific
> details of each individual service.
> Also, drop the unneeded label from the example.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../soc/microchip/microchip,mpfs-sys-controller.yaml | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> index f699772fedf3..b0dae51e1d42 100644
> --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> @@ -10,9 +10,14 @@ maintainers:
> - Conor Dooley <conor.dooley@microchip.com>
>
> description: |
> - The PolarFire SoC system controller is communicated with via a mailbox.
> - This document describes the bindings for the client portion of that mailbox.
> + PolarFire SoC devices include a microcontroller acting as the system controller,
> + which provides "services" to the main processor and to the FPGA fabric. These
> + services include hardware rng, reprogramming of the FPGA and verfification of the
> + eNVM contents etc. More information on these services can be found online, at
> + https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
>
> + Communication with the system controller is done via a mailbox, of which the client
> + portion is documented here.
>
> properties:
> mboxes:
> @@ -29,7 +34,7 @@ additionalProperties: false
>
> examples:
> - |
> - syscontroller: syscontroller {
> + syscontroller {
> compatible = "microchip,mpfs-sys-controller";
> mboxes = <&mbox 0>;
> };
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
2022-02-14 13:58 ` conor.dooley
@ 2022-02-21 7:55 ` Conor.Dooley
-1 siblings, 0 replies; 64+ messages in thread
From: Conor.Dooley @ 2022-02-21 7:55 UTC (permalink / raw)
To: u.kleine-koenig
Cc: Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp, robh, palmer,
linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
lee.jones, a.zummo, alexandre.belloni, paul.walmsley, palmer,
aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv
Hey Uwe,
Could you take a look at this version & see if the descriptions are
easier to understand?
Thanks,
Conor
On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the Microchip fpga fabric based "core" PWM
> controller.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> .../bindings/pwm/microchip,corepwm.yaml | 81 +++++++++++++++++++
> 1 file changed, 81 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
> new file mode 100644
> index 000000000000..a7fae1772a81
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip IP corePWM controller bindings
> +
> +maintainers:
> + - Conor Dooley <conor.dooley@microchip.com>
> +
> +description: |
> + corePWM is an 16 channel pulse width modulator FPGA IP
> +
> + https://www.microsemi.com/existing-parts/parts/152118
> +
> +allOf:
> + - $ref: pwm.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: microchip,corepwm-rtl-v4
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + "#pwm-cells":
> + const: 2
> +
> + microchip,sync-update-mask:
> + description: |
> + Depending on how the IP is instantiated, there are two modes of operation.
> + In synchronous mode, all channels are updated at the beginning of the PWM period,
> + and in asynchronous mode updates happen as the control registers are written.
> + A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
> + mode is possible for each channel, and is set by the bitstream programmed to the
> + FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
> + control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
> + At runtime a bit wide register exposed to APB can be used to toggle on/off
> + synchronised mode for all channels it has been synthesised for.
> + Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
> + whether synchronous mode is possible for the PWM channel.
> +
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> +
> + microchip,dac-mode-mask:
> + description: |
> + Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
> + a minimum period pulse train whose High/Low average is that of the chosen duty
> + cycle. This "DAC" will have far better bandwidth and ripple performance than the
> + standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
> + core, set at instantiation and by the bitstream programmed to the FPGA, determines
> + whether a given channel operates in regular PWM or DAC mode.
> + Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
> + for that channel.
> +
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pwm@41000000 {
> + compatible = "microchip,corepwm-rtl-v4";
> + microchip,sync-update-mask = /bits/ 32 <0>;
> + clocks = <&clkcfg 30>;
> + reg = <0x41000000 0xF0>;
> + #pwm-cells = <2>;
> + };
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
@ 2022-02-21 7:55 ` Conor.Dooley
0 siblings, 0 replies; 64+ messages in thread
From: Conor.Dooley @ 2022-02-21 7:55 UTC (permalink / raw)
To: u.kleine-koenig
Cc: Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp, robh, palmer,
linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
lee.jones, a.zummo, alexandre.belloni, paul.walmsley, palmer,
aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv
Hey Uwe,
Could you take a look at this version & see if the descriptions are
easier to understand?
Thanks,
Conor
On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the Microchip fpga fabric based "core" PWM
> controller.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> .../bindings/pwm/microchip,corepwm.yaml | 81 +++++++++++++++++++
> 1 file changed, 81 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
> new file mode 100644
> index 000000000000..a7fae1772a81
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip IP corePWM controller bindings
> +
> +maintainers:
> + - Conor Dooley <conor.dooley@microchip.com>
> +
> +description: |
> + corePWM is an 16 channel pulse width modulator FPGA IP
> +
> + https://www.microsemi.com/existing-parts/parts/152118
> +
> +allOf:
> + - $ref: pwm.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: microchip,corepwm-rtl-v4
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + "#pwm-cells":
> + const: 2
> +
> + microchip,sync-update-mask:
> + description: |
> + Depending on how the IP is instantiated, there are two modes of operation.
> + In synchronous mode, all channels are updated at the beginning of the PWM period,
> + and in asynchronous mode updates happen as the control registers are written.
> + A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
> + mode is possible for each channel, and is set by the bitstream programmed to the
> + FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
> + control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
> + At runtime a bit wide register exposed to APB can be used to toggle on/off
> + synchronised mode for all channels it has been synthesised for.
> + Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
> + whether synchronous mode is possible for the PWM channel.
> +
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> +
> + microchip,dac-mode-mask:
> + description: |
> + Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
> + a minimum period pulse train whose High/Low average is that of the chosen duty
> + cycle. This "DAC" will have far better bandwidth and ripple performance than the
> + standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
> + core, set at instantiation and by the bitstream programmed to the FPGA, determines
> + whether a given channel operates in regular PWM or DAC mode.
> + Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
> + for that channel.
> +
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pwm@41000000 {
> + compatible = "microchip,corepwm-rtl-v4";
> + microchip,sync-update-mask = /bits/ 32 <0>;
> + clocks = <&clkcfg 30>;
> + reg = <0x41000000 0xF0>;
> + #pwm-cells = <2>;
> + };
_______________________________________________
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 02/11] dt-bindings: soc/microchip: add info about services to mpfs sysctrl
2022-02-14 13:58 ` conor.dooley
@ 2022-02-22 21:39 ` Rob Herring
-1 siblings, 0 replies; 64+ messages in thread
From: Rob Herring @ 2022-02-22 21:39 UTC (permalink / raw)
To: conor.dooley
Cc: linux-gpio, atishp, a.zummo, devicetree, robh+dt, paul.walmsley,
lee.jones, u.kleine-koenig, linux-pwm, ivan.griffin,
linus.walleij, brgl, daire.mcnamara, jassisinghbrar, linux-rtc,
linux-kernel, linux-riscv, aou, krzysztof.kozlowski, palmer,
geert, lewis.hanly, thierry.reding, alexandre.belloni
On Mon, 14 Feb 2022 13:58:32 +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The services actually provided by the system controller are not
> documented so add some words about what the system controller can
> actually do. Add a link to the oneline documentation with the specific
> details of each individual service.
> Also, drop the unneeded label from the example.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../soc/microchip/microchip,mpfs-sys-controller.yaml | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 02/11] dt-bindings: soc/microchip: add info about services to mpfs sysctrl
@ 2022-02-22 21:39 ` Rob Herring
0 siblings, 0 replies; 64+ messages in thread
From: Rob Herring @ 2022-02-22 21:39 UTC (permalink / raw)
To: conor.dooley
Cc: linux-gpio, atishp, a.zummo, devicetree, robh+dt, paul.walmsley,
lee.jones, u.kleine-koenig, linux-pwm, ivan.griffin,
linus.walleij, brgl, daire.mcnamara, jassisinghbrar, linux-rtc,
linux-kernel, linux-riscv, aou, krzysztof.kozlowski, palmer,
geert, lewis.hanly, thierry.reding, alexandre.belloni
On Mon, 14 Feb 2022 13:58:32 +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The services actually provided by the system controller are not
> documented so add some words about what the system controller can
> actually do. Add a link to the oneline documentation with the specific
> details of each individual service.
> Also, drop the unneeded label from the example.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../soc/microchip/microchip,mpfs-sys-controller.yaml | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
2022-02-14 13:58 ` conor.dooley
@ 2022-02-23 6:20 ` Uwe Kleine-König
-1 siblings, 0 replies; 64+ messages in thread
From: Uwe Kleine-König @ 2022-02-23 6:20 UTC (permalink / raw)
To: conor.dooley
Cc: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
lee.jones, a.zummo, alexandre.belloni, paul.walmsley, palmer,
aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv, lewis.hanly,
daire.mcnamara, ivan.griffin, atishp, Rob Herring,
Palmer Dabbelt
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On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the Microchip fpga fabric based "core" PWM
> controller.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
I like it:
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
nitpick: Put your S-o-b last in the commit log. (This doesn't justify a
resend IMHO)
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
@ 2022-02-23 6:20 ` Uwe Kleine-König
0 siblings, 0 replies; 64+ messages in thread
From: Uwe Kleine-König @ 2022-02-23 6:20 UTC (permalink / raw)
To: conor.dooley
Cc: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
lee.jones, a.zummo, alexandre.belloni, paul.walmsley, palmer,
aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv, lewis.hanly,
daire.mcnamara, ivan.griffin, atishp, Rob Herring,
Palmer Dabbelt
[-- Attachment #1.1: Type: text/plain, Size: 728 bytes --]
On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the Microchip fpga fabric based "core" PWM
> controller.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
I like it:
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
nitpick: Put your S-o-b last in the commit log. (This doesn't justify a
resend IMHO)
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
2022-02-23 6:20 ` Uwe Kleine-König
@ 2022-02-23 7:12 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 64+ messages in thread
From: Krzysztof Kozlowski @ 2022-02-23 7:12 UTC (permalink / raw)
To: Uwe Kleine-König, conor.dooley
Cc: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
lee.jones, a.zummo, alexandre.belloni, paul.walmsley, palmer,
aou, geert, linux-gpio, devicetree, linux-kernel, linux-pwm,
linux-rtc, linux-riscv, lewis.hanly, daire.mcnamara,
ivan.griffin, atishp, Rob Herring, Palmer Dabbelt
On 23/02/2022 07:20, Uwe Kleine-König wrote:
> On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> Add device tree bindings for the Microchip fpga fabric based "core" PWM
>> controller.
>>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> I like it:
>
> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
>
> nitpick: Put your S-o-b last in the commit log. (This doesn't justify a
> resend IMHO)
It should be the opposite - the first. First author signs the patch,
then comes review and finally an ack. Putting SoB at then suggests that
tags were accumulated before sending patch, out of mailing list.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
@ 2022-02-23 7:12 ` Krzysztof Kozlowski
0 siblings, 0 replies; 64+ messages in thread
From: Krzysztof Kozlowski @ 2022-02-23 7:12 UTC (permalink / raw)
To: Uwe Kleine-König, conor.dooley
Cc: linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
lee.jones, a.zummo, alexandre.belloni, paul.walmsley, palmer,
aou, geert, linux-gpio, devicetree, linux-kernel, linux-pwm,
linux-rtc, linux-riscv, lewis.hanly, daire.mcnamara,
ivan.griffin, atishp, Rob Herring, Palmer Dabbelt
On 23/02/2022 07:20, Uwe Kleine-König wrote:
> On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> Add device tree bindings for the Microchip fpga fabric based "core" PWM
>> controller.
>>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> I like it:
>
> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
>
> nitpick: Put your S-o-b last in the commit log. (This doesn't justify a
> resend IMHO)
It should be the opposite - the first. First author signs the patch,
then comes review and finally an ack. Putting SoB at then suggests that
tags were accumulated before sending patch, out of mailing list.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc
2022-02-14 13:58 ` conor.dooley
@ 2022-02-23 7:41 ` Conor.Dooley
-1 siblings, 0 replies; 64+ messages in thread
From: Conor.Dooley @ 2022-02-23 7:41 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp, palmer, robh,
linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, paul.walmsley, palmer, aou, geert,
krzysztof.kozlowski, linux-gpio, devicetree, linux-kernel,
linux-pwm, linux-rtc, linux-riscv
Hi Alessandro, Alexandre,
If one of you could take a look at this, that'd be great.
Thanks,
Conor.
On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the real time clock on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++
> 1 file changed, 58 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>
> diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> new file mode 100644
> index 000000000000..a2e984ea3553
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
> +
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
> +
> +allOf:
> + - $ref: rtc.yaml#
> +
> +maintainers:
> + - Daire McNamara <daire.mcnamara@microchip.com>
> + - Lewis Hanly <lewis.hanly@microchip.com>
> +
> +properties:
> + compatible:
> + enum:
> + - microchip,mpfs-rtc
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + items:
> + - description: |
> + RTC_WAKEUP interrupt
> + - description: |
> + RTC_MATCH, asserted when the content of the Alarm register is equal
> + to that of the RTC's count register.
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: rtc
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + rtc@20124000 {
> + compatible = "microchip,mpfs-rtc";
> + reg = <0x20124000 0x1000>;
> + clocks = <&clkcfg 21>;
> + clock-names = "rtc";
> + interrupts = <80>, <81>;
> + };
> +...
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc
@ 2022-02-23 7:41 ` Conor.Dooley
0 siblings, 0 replies; 64+ messages in thread
From: Conor.Dooley @ 2022-02-23 7:41 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp, palmer, robh,
linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, paul.walmsley, palmer, aou, geert,
krzysztof.kozlowski, linux-gpio, devicetree, linux-kernel,
linux-pwm, linux-rtc, linux-riscv
Hi Alessandro, Alexandre,
If one of you could take a look at this, that'd be great.
Thanks,
Conor.
On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the real time clock on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++
> 1 file changed, 58 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>
> diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> new file mode 100644
> index 000000000000..a2e984ea3553
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
> +
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
> +
> +allOf:
> + - $ref: rtc.yaml#
> +
> +maintainers:
> + - Daire McNamara <daire.mcnamara@microchip.com>
> + - Lewis Hanly <lewis.hanly@microchip.com>
> +
> +properties:
> + compatible:
> + enum:
> + - microchip,mpfs-rtc
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + items:
> + - description: |
> + RTC_WAKEUP interrupt
> + - description: |
> + RTC_MATCH, asserted when the content of the Alarm register is equal
> + to that of the RTC's count register.
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: rtc
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + rtc@20124000 {
> + compatible = "microchip,mpfs-rtc";
> + reg = <0x20124000 0x1000>;
> + clocks = <&clkcfg 21>;
> + clock-names = "rtc";
> + interrupts = <80>, <81>;
> + };
> +...
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
2022-02-23 7:12 ` Krzysztof Kozlowski
@ 2022-02-23 8:20 ` Uwe Kleine-König
-1 siblings, 0 replies; 64+ messages in thread
From: Uwe Kleine-König @ 2022-02-23 8:20 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: conor.dooley, linus.walleij, brgl, robh+dt, jassisinghbrar,
thierry.reding, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv, lewis.hanly,
daire.mcnamara, ivan.griffin, atishp, Rob Herring,
Palmer Dabbelt
[-- Attachment #1: Type: text/plain, Size: 1685 bytes --]
On Wed, Feb 23, 2022 at 08:12:49AM +0100, Krzysztof Kozlowski wrote:
> On 23/02/2022 07:20, Uwe Kleine-König wrote:
> > On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> Add device tree bindings for the Microchip fpga fabric based "core" PWM
> >> controller.
> >>
> >> Reviewed-by: Rob Herring <robh@kernel.org>
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> >
> > I like it:
> >
> > Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> >
> > nitpick: Put your S-o-b last in the commit log. (This doesn't justify a
> > resend IMHO)
>
> It should be the opposite - the first. First author signs the patch,
> then comes review and finally an ack. Putting SoB at then suggests that
> tags were accumulated before sending patch, out of mailing list.
well, or in an earlier revision of this patch as is the case here. One
of the ideas of S-o-b is that the order shows the flow of the patch
states and if this patch ends in git with:
Referred-by: Rob Herring <robh@kernel.org>
Singed-off-by: Conor Dooley <conor.dooley@microchip.com>
Backed-by: Palmer Dabbelt <palmer@rivosinc.com>
Singed-off-by: Peter Maintainer <pm@example.com>
I'd expect that Backed-by was added by Peter, not Conor.
(Modified the tags on purpose to not interfere with b4's tag pickup, I
guess you humans still get the point.)
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
@ 2022-02-23 8:20 ` Uwe Kleine-König
0 siblings, 0 replies; 64+ messages in thread
From: Uwe Kleine-König @ 2022-02-23 8:20 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: conor.dooley, linus.walleij, brgl, robh+dt, jassisinghbrar,
thierry.reding, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv, lewis.hanly,
daire.mcnamara, ivan.griffin, atishp, Rob Herring,
Palmer Dabbelt
[-- Attachment #1.1: Type: text/plain, Size: 1685 bytes --]
On Wed, Feb 23, 2022 at 08:12:49AM +0100, Krzysztof Kozlowski wrote:
> On 23/02/2022 07:20, Uwe Kleine-König wrote:
> > On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> Add device tree bindings for the Microchip fpga fabric based "core" PWM
> >> controller.
> >>
> >> Reviewed-by: Rob Herring <robh@kernel.org>
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> >
> > I like it:
> >
> > Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> >
> > nitpick: Put your S-o-b last in the commit log. (This doesn't justify a
> > resend IMHO)
>
> It should be the opposite - the first. First author signs the patch,
> then comes review and finally an ack. Putting SoB at then suggests that
> tags were accumulated before sending patch, out of mailing list.
well, or in an earlier revision of this patch as is the case here. One
of the ideas of S-o-b is that the order shows the flow of the patch
states and if this patch ends in git with:
Referred-by: Rob Herring <robh@kernel.org>
Singed-off-by: Conor Dooley <conor.dooley@microchip.com>
Backed-by: Palmer Dabbelt <palmer@rivosinc.com>
Singed-off-by: Peter Maintainer <pm@example.com>
I'd expect that Backed-by was added by Peter, not Conor.
(Modified the tags on purpose to not interfere with b4's tag pickup, I
guess you humans still get the point.)
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
2022-02-23 8:20 ` Uwe Kleine-König
@ 2022-02-23 8:55 ` conor.dooley
-1 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-23 8:55 UTC (permalink / raw)
To: u.kleine-koenig, krzysztof.kozlowski
Cc: a.zummo, alexandre.belloni, aou, atishp, brgl, conor.dooley,
daire.mcnamara, devicetree, geert, ivan.griffin, jassisinghbrar,
lee.jones, lewis.hanly, linus.walleij, linux-gpio, linux-kernel,
linux-pwm, linux-riscv, linux-rtc, palmer, palmer, paul.walmsley,
robh+dt, robh, thierry.reding
On 23/02/2022 08:20, Uwe Kleine-König wrote:
> On Wed, Feb 23, 2022 at 08:12:49AM +0100, Krzysztof Kozlowski wrote:
> > On 23/02/2022 07:20, Uwe Kleine-König wrote:
> > > On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote:
> > >> From: Conor Dooley <conor.dooley@microchip.com>
> > >>
> > >> Add device tree bindings for the Microchip fpga fabric based "core" PWM
> > >> controller.
> > >>
> > >> Reviewed-by: Rob Herring <robh@kernel.org>
> > >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > >> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> > >
> > > I like it:
> > >
> > > Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> > >
> > > nitpick: Put your S-o-b last in the commit log. (This doesn't justify a
> > > resend IMHO)
> >
> > It should be the opposite - the first. First author signs the patch,
> > then comes review and finally an ack. Putting SoB at then suggests that
> > tags were accumulated before sending patch, out of mailing list.
>
> well, or in an earlier revision of this patch as is the case here. One
> of the ideas of S-o-b is that the order shows the flow of the patch
> states and if this patch ends in git with:
>
> Referred-by: Rob Herring <robh@kernel.org>
> Singed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Backed-by: Palmer Dabbelt <palmer@rivosinc.com>
> Singed-off-by: Peter Maintainer <pm@example.com>
>
> I'd expect that Backed-by was added by Peter, not Conor.
> (Modified the tags on purpose to not interfere with b4's tag pickup, I
> guess you humans still get the point.)
I had put the acks after the S-o-B for patches I hadn't changed since the ack,
but I think that may have been a misinterpretation of what was meant by Rob
when he said tags should be in chronological order. Won't do it this way in
the future.
If the remaining patch gets a maintainer ack, the order will be fine I guess
since it'll be Palmer taking it anyway. If there's a v8, I will fix the order.
Thanks,
Conor
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
@ 2022-02-23 8:55 ` conor.dooley
0 siblings, 0 replies; 64+ messages in thread
From: conor.dooley @ 2022-02-23 8:55 UTC (permalink / raw)
To: u.kleine-koenig, krzysztof.kozlowski
Cc: a.zummo, alexandre.belloni, aou, atishp, brgl, conor.dooley,
daire.mcnamara, devicetree, geert, ivan.griffin, jassisinghbrar,
lee.jones, lewis.hanly, linus.walleij, linux-gpio, linux-kernel,
linux-pwm, linux-riscv, linux-rtc, palmer, palmer, paul.walmsley,
robh+dt, robh, thierry.reding
On 23/02/2022 08:20, Uwe Kleine-König wrote:
> On Wed, Feb 23, 2022 at 08:12:49AM +0100, Krzysztof Kozlowski wrote:
> > On 23/02/2022 07:20, Uwe Kleine-König wrote:
> > > On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote:
> > >> From: Conor Dooley <conor.dooley@microchip.com>
> > >>
> > >> Add device tree bindings for the Microchip fpga fabric based "core" PWM
> > >> controller.
> > >>
> > >> Reviewed-by: Rob Herring <robh@kernel.org>
> > >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > >> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> > >
> > > I like it:
> > >
> > > Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> > >
> > > nitpick: Put your S-o-b last in the commit log. (This doesn't justify a
> > > resend IMHO)
> >
> > It should be the opposite - the first. First author signs the patch,
> > then comes review and finally an ack. Putting SoB at then suggests that
> > tags were accumulated before sending patch, out of mailing list.
>
> well, or in an earlier revision of this patch as is the case here. One
> of the ideas of S-o-b is that the order shows the flow of the patch
> states and if this patch ends in git with:
>
> Referred-by: Rob Herring <robh@kernel.org>
> Singed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Backed-by: Palmer Dabbelt <palmer@rivosinc.com>
> Singed-off-by: Peter Maintainer <pm@example.com>
>
> I'd expect that Backed-by was added by Peter, not Conor.
> (Modified the tags on purpose to not interfere with b4's tag pickup, I
> guess you humans still get the point.)
I had put the acks after the S-o-B for patches I hadn't changed since the ack,
but I think that may have been a misinterpretation of what was meant by Rob
when he said tags should be in chronological order. Won't do it this way in
the future.
If the remaining patch gets a maintainer ack, the order will be fine I guess
since it'll be Palmer taking it anyway. If there's a v8, I will fix the order.
Thanks,
Conor
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
2022-02-23 8:20 ` Uwe Kleine-König
@ 2022-02-23 9:09 ` Lee Jones
-1 siblings, 0 replies; 64+ messages in thread
From: Lee Jones @ 2022-02-23 9:09 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Krzysztof Kozlowski, conor.dooley, linus.walleij, brgl, robh+dt,
jassisinghbrar, thierry.reding, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv, lewis.hanly,
daire.mcnamara, ivan.griffin, atishp, Rob Herring,
Palmer Dabbelt
On Wed, 23 Feb 2022, Uwe Kleine-König wrote:
> On Wed, Feb 23, 2022 at 08:12:49AM +0100, Krzysztof Kozlowski wrote:
> > On 23/02/2022 07:20, Uwe Kleine-König wrote:
> > > On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote:
> > >> From: Conor Dooley <conor.dooley@microchip.com>
> > >>
> > >> Add device tree bindings for the Microchip fpga fabric based "core" PWM
> > >> controller.
> > >>
> > >> Reviewed-by: Rob Herring <robh@kernel.org>
> > >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > >> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> > >
> > > I like it:
> > >
> > > Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> > >
> > > nitpick: Put your S-o-b last in the commit log. (This doesn't justify a
> > > resend IMHO)
> >
> > It should be the opposite - the first. First author signs the patch,
> > then comes review and finally an ack. Putting SoB at then suggests that
> > tags were accumulated before sending patch, out of mailing list.
>
> well, or in an earlier revision of this patch as is the case here. One
> of the ideas of S-o-b is that the order shows the flow of the patch
> states and if this patch ends in git with:
>
> Referred-by: Rob Herring <robh@kernel.org>
> Singed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Backed-by: Palmer Dabbelt <palmer@rivosinc.com>
> Singed-off-by: Peter Maintainer <pm@example.com>
>
> I'd expect that Backed-by was added by Peter, not Conor.
> (Modified the tags on purpose to not interfere with b4's tag pickup, I
> guess you humans still get the point.)
I tend to like *-by tags to appear chronologically.
Suggested (suggested-by)
Authored (signed-off-by)
Co-Authored (signed-off-by/co-developed-by)
Reviewed/Acked/Tested (reviewed-by/acked-by/tested-by)
Committed (signed-off-by)
--
Lee Jones [李琼斯]
Principal Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
@ 2022-02-23 9:09 ` Lee Jones
0 siblings, 0 replies; 64+ messages in thread
From: Lee Jones @ 2022-02-23 9:09 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Krzysztof Kozlowski, conor.dooley, linus.walleij, brgl, robh+dt,
jassisinghbrar, thierry.reding, a.zummo, alexandre.belloni,
paul.walmsley, palmer, aou, geert, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv, lewis.hanly,
daire.mcnamara, ivan.griffin, atishp, Rob Herring,
Palmer Dabbelt
On Wed, 23 Feb 2022, Uwe Kleine-König wrote:
> On Wed, Feb 23, 2022 at 08:12:49AM +0100, Krzysztof Kozlowski wrote:
> > On 23/02/2022 07:20, Uwe Kleine-König wrote:
> > > On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote:
> > >> From: Conor Dooley <conor.dooley@microchip.com>
> > >>
> > >> Add device tree bindings for the Microchip fpga fabric based "core" PWM
> > >> controller.
> > >>
> > >> Reviewed-by: Rob Herring <robh@kernel.org>
> > >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > >> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> > >
> > > I like it:
> > >
> > > Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> > >
> > > nitpick: Put your S-o-b last in the commit log. (This doesn't justify a
> > > resend IMHO)
> >
> > It should be the opposite - the first. First author signs the patch,
> > then comes review and finally an ack. Putting SoB at then suggests that
> > tags were accumulated before sending patch, out of mailing list.
>
> well, or in an earlier revision of this patch as is the case here. One
> of the ideas of S-o-b is that the order shows the flow of the patch
> states and if this patch ends in git with:
>
> Referred-by: Rob Herring <robh@kernel.org>
> Singed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Backed-by: Palmer Dabbelt <palmer@rivosinc.com>
> Singed-off-by: Peter Maintainer <pm@example.com>
>
> I'd expect that Backed-by was added by Peter, not Conor.
> (Modified the tags on purpose to not interfere with b4's tag pickup, I
> guess you humans still get the point.)
I tend to like *-by tags to appear chronologically.
Suggested (suggested-by)
Authored (signed-off-by)
Co-Authored (signed-off-by/co-developed-by)
Reviewed/Acked/Tested (reviewed-by/acked-by/tested-by)
Committed (signed-off-by)
--
Lee Jones [李琼斯]
Principal Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc
2022-02-23 7:41 ` Conor.Dooley
@ 2022-02-23 15:18 ` Alexandre Belloni
-1 siblings, 0 replies; 64+ messages in thread
From: Alexandre Belloni @ 2022-02-23 15:18 UTC (permalink / raw)
To: Conor.Dooley
Cc: a.zummo, Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp,
palmer, robh, linus.walleij, brgl, robh+dt, jassisinghbrar,
thierry.reding, u.kleine-koenig, lee.jones, paul.walmsley,
palmer, aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv
On 23/02/2022 07:41:27+0000, Conor.Dooley@microchip.com wrote:
> Hi Alessandro, Alexandre,
> If one of you could take a look at this, that'd be great.
I actually expected someone else to apply this, what is your plan?
> Thanks,
> Conor.
>
> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > Add device tree bindings for the real time clock on
> > the Microchip PolarFire SoC.
> >
> > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > ---
> > .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++
> > 1 file changed, 58 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> > new file mode 100644
> > index 000000000000..a2e984ea3553
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> > @@ -0,0 +1,58 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
> > +
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
> > +
> > +allOf:
> > + - $ref: rtc.yaml#
> > +
> > +maintainers:
> > + - Daire McNamara <daire.mcnamara@microchip.com>
> > + - Lewis Hanly <lewis.hanly@microchip.com>
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - microchip,mpfs-rtc
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + items:
> > + - description: |
> > + RTC_WAKEUP interrupt
> > + - description: |
> > + RTC_MATCH, asserted when the content of the Alarm register is equal
> > + to that of the RTC's count register.
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + clock-names:
> > + items:
> > + - const: rtc
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + rtc@20124000 {
> > + compatible = "microchip,mpfs-rtc";
> > + reg = <0x20124000 0x1000>;
> > + clocks = <&clkcfg 21>;
> > + clock-names = "rtc";
> > + interrupts = <80>, <81>;
> > + };
> > +...
>
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc
@ 2022-02-23 15:18 ` Alexandre Belloni
0 siblings, 0 replies; 64+ messages in thread
From: Alexandre Belloni @ 2022-02-23 15:18 UTC (permalink / raw)
To: Conor.Dooley
Cc: a.zummo, Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp,
palmer, robh, linus.walleij, brgl, robh+dt, jassisinghbrar,
thierry.reding, u.kleine-koenig, lee.jones, paul.walmsley,
palmer, aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv
On 23/02/2022 07:41:27+0000, Conor.Dooley@microchip.com wrote:
> Hi Alessandro, Alexandre,
> If one of you could take a look at this, that'd be great.
I actually expected someone else to apply this, what is your plan?
> Thanks,
> Conor.
>
> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > Add device tree bindings for the real time clock on
> > the Microchip PolarFire SoC.
> >
> > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > ---
> > .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++
> > 1 file changed, 58 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> > new file mode 100644
> > index 000000000000..a2e984ea3553
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> > @@ -0,0 +1,58 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
> > +
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
> > +
> > +allOf:
> > + - $ref: rtc.yaml#
> > +
> > +maintainers:
> > + - Daire McNamara <daire.mcnamara@microchip.com>
> > + - Lewis Hanly <lewis.hanly@microchip.com>
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - microchip,mpfs-rtc
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + items:
> > + - description: |
> > + RTC_WAKEUP interrupt
> > + - description: |
> > + RTC_MATCH, asserted when the content of the Alarm register is equal
> > + to that of the RTC's count register.
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + clock-names:
> > + items:
> > + - const: rtc
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + rtc@20124000 {
> > + compatible = "microchip,mpfs-rtc";
> > + reg = <0x20124000 0x1000>;
> > + clocks = <&clkcfg 21>;
> > + clock-names = "rtc";
> > + interrupts = <80>, <81>;
> > + };
> > +...
>
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc
2022-02-23 15:18 ` Alexandre Belloni
@ 2022-02-23 15:25 ` Conor.Dooley
-1 siblings, 0 replies; 64+ messages in thread
From: Conor.Dooley @ 2022-02-23 15:25 UTC (permalink / raw)
To: alexandre.belloni
Cc: a.zummo, Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp,
palmer, robh, linus.walleij, brgl, robh+dt, jassisinghbrar,
thierry.reding, u.kleine-koenig, lee.jones, paul.walmsley,
palmer, aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv
On 23/02/2022 15:18, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 23/02/2022 07:41:27+0000, Conor.Dooley@microchip.com wrote:
>> Hi Alessandro, Alexandre,
>> If one of you could take a look at this, that'd be great.
>
> I actually expected someone else to apply this, what is your plan?
I was going to ask Palmer to take the series via riscv. Since I have
Rob's R-b, I was just looking for a subsystem maintainer ack/R-b before
actually asking him.
Thanks,
Conor.
>
>> Thanks,
>> Conor.
>>
>> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> Add device tree bindings for the real time clock on
>>> the Microchip PolarFire SoC.
>>>
>>> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>> ---
>>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++
>>> 1 file changed, 58 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>> new file mode 100644
>>> index 000000000000..a2e984ea3553
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>> @@ -0,0 +1,58 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
>>> +
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
>>> +
>>> +allOf:
>>> + - $ref: rtc.yaml#
>>> +
>>> +maintainers:
>>> + - Daire McNamara <daire.mcnamara@microchip.com>
>>> + - Lewis Hanly <lewis.hanly@microchip.com>
>>> +
>>> +properties:
>>> + compatible:
>>> + enum:
>>> + - microchip,mpfs-rtc
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> + interrupts:
>>> + items:
>>> + - description: |
>>> + RTC_WAKEUP interrupt
>>> + - description: |
>>> + RTC_MATCH, asserted when the content of the Alarm register is equal
>>> + to that of the RTC's count register.
>>> +
>>> + clocks:
>>> + maxItems: 1
>>> +
>>> + clock-names:
>>> + items:
>>> + - const: rtc
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - interrupts
>>> + - clocks
>>> + - clock-names
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + rtc@20124000 {
>>> + compatible = "microchip,mpfs-rtc";
>>> + reg = <0x20124000 0x1000>;
>>> + clocks = <&clkcfg 21>;
>>> + clock-names = "rtc";
>>> + interrupts = <80>, <81>;
>>> + };
>>> +...
>>
>
> --
> Alexandre Belloni, co-owner and COO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc
@ 2022-02-23 15:25 ` Conor.Dooley
0 siblings, 0 replies; 64+ messages in thread
From: Conor.Dooley @ 2022-02-23 15:25 UTC (permalink / raw)
To: alexandre.belloni
Cc: a.zummo, Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp,
palmer, robh, linus.walleij, brgl, robh+dt, jassisinghbrar,
thierry.reding, u.kleine-koenig, lee.jones, paul.walmsley,
palmer, aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv
On 23/02/2022 15:18, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 23/02/2022 07:41:27+0000, Conor.Dooley@microchip.com wrote:
>> Hi Alessandro, Alexandre,
>> If one of you could take a look at this, that'd be great.
>
> I actually expected someone else to apply this, what is your plan?
I was going to ask Palmer to take the series via riscv. Since I have
Rob's R-b, I was just looking for a subsystem maintainer ack/R-b before
actually asking him.
Thanks,
Conor.
>
>> Thanks,
>> Conor.
>>
>> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> Add device tree bindings for the real time clock on
>>> the Microchip PolarFire SoC.
>>>
>>> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>> ---
>>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++
>>> 1 file changed, 58 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>> new file mode 100644
>>> index 000000000000..a2e984ea3553
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>> @@ -0,0 +1,58 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
>>> +
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
>>> +
>>> +allOf:
>>> + - $ref: rtc.yaml#
>>> +
>>> +maintainers:
>>> + - Daire McNamara <daire.mcnamara@microchip.com>
>>> + - Lewis Hanly <lewis.hanly@microchip.com>
>>> +
>>> +properties:
>>> + compatible:
>>> + enum:
>>> + - microchip,mpfs-rtc
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> + interrupts:
>>> + items:
>>> + - description: |
>>> + RTC_WAKEUP interrupt
>>> + - description: |
>>> + RTC_MATCH, asserted when the content of the Alarm register is equal
>>> + to that of the RTC's count register.
>>> +
>>> + clocks:
>>> + maxItems: 1
>>> +
>>> + clock-names:
>>> + items:
>>> + - const: rtc
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - interrupts
>>> + - clocks
>>> + - clock-names
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + rtc@20124000 {
>>> + compatible = "microchip,mpfs-rtc";
>>> + reg = <0x20124000 0x1000>;
>>> + clocks = <&clkcfg 21>;
>>> + clock-names = "rtc";
>>> + interrupts = <80>, <81>;
>>> + };
>>> +...
>>
>
> --
> Alexandre Belloni, co-owner and COO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc
2022-02-23 15:25 ` Conor.Dooley
@ 2022-02-23 20:20 ` Alexandre Belloni
-1 siblings, 0 replies; 64+ messages in thread
From: Alexandre Belloni @ 2022-02-23 20:20 UTC (permalink / raw)
To: Conor.Dooley
Cc: a.zummo, Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp,
palmer, robh, linus.walleij, brgl, robh+dt, jassisinghbrar,
thierry.reding, u.kleine-koenig, lee.jones, paul.walmsley,
palmer, aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv
On 23/02/2022 15:25:00+0000, Conor.Dooley@microchip.com wrote:
> On 23/02/2022 15:18, Alexandre Belloni wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On 23/02/2022 07:41:27+0000, Conor.Dooley@microchip.com wrote:
> >> Hi Alessandro, Alexandre,
> >> If one of you could take a look at this, that'd be great.
> >
> > I actually expected someone else to apply this, what is your plan?
>
> I was going to ask Palmer to take the series via riscv. Since I have
> Rob's R-b, I was just looking for a subsystem maintainer ack/R-b before
> actually asking him.
>
Rob's review is enough for a DT binding, no need to wait for me. but
FWIW:
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Thanks,
> Conor.
>
> >
> >> Thanks,
> >> Conor.
> >>
> >> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> >>> From: Conor Dooley <conor.dooley@microchip.com>
> >>>
> >>> Add device tree bindings for the real time clock on
> >>> the Microchip PolarFire SoC.
> >>>
> >>> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> >>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> >>> Reviewed-by: Rob Herring <robh@kernel.org>
> >>> ---
> >>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++
> >>> 1 file changed, 58 insertions(+)
> >>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> >>> new file mode 100644
> >>> index 000000000000..a2e984ea3553
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> >>> @@ -0,0 +1,58 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
> >>> +
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
> >>> +
> >>> +allOf:
> >>> + - $ref: rtc.yaml#
> >>> +
> >>> +maintainers:
> >>> + - Daire McNamara <daire.mcnamara@microchip.com>
> >>> + - Lewis Hanly <lewis.hanly@microchip.com>
> >>> +
> >>> +properties:
> >>> + compatible:
> >>> + enum:
> >>> + - microchip,mpfs-rtc
> >>> +
> >>> + reg:
> >>> + maxItems: 1
> >>> +
> >>> + interrupts:
> >>> + items:
> >>> + - description: |
> >>> + RTC_WAKEUP interrupt
> >>> + - description: |
> >>> + RTC_MATCH, asserted when the content of the Alarm register is equal
> >>> + to that of the RTC's count register.
> >>> +
> >>> + clocks:
> >>> + maxItems: 1
> >>> +
> >>> + clock-names:
> >>> + items:
> >>> + - const: rtc
> >>> +
> >>> +required:
> >>> + - compatible
> >>> + - reg
> >>> + - interrupts
> >>> + - clocks
> >>> + - clock-names
> >>> +
> >>> +additionalProperties: false
> >>> +
> >>> +examples:
> >>> + - |
> >>> + rtc@20124000 {
> >>> + compatible = "microchip,mpfs-rtc";
> >>> + reg = <0x20124000 0x1000>;
> >>> + clocks = <&clkcfg 21>;
> >>> + clock-names = "rtc";
> >>> + interrupts = <80>, <81>;
> >>> + };
> >>> +...
> >>
> >
> > --
> > Alexandre Belloni, co-owner and COO, Bootlin
> > Embedded Linux and Kernel engineering
> > https://bootlin.com
>
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc
@ 2022-02-23 20:20 ` Alexandre Belloni
0 siblings, 0 replies; 64+ messages in thread
From: Alexandre Belloni @ 2022-02-23 20:20 UTC (permalink / raw)
To: Conor.Dooley
Cc: a.zummo, Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp,
palmer, robh, linus.walleij, brgl, robh+dt, jassisinghbrar,
thierry.reding, u.kleine-koenig, lee.jones, paul.walmsley,
palmer, aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv
On 23/02/2022 15:25:00+0000, Conor.Dooley@microchip.com wrote:
> On 23/02/2022 15:18, Alexandre Belloni wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On 23/02/2022 07:41:27+0000, Conor.Dooley@microchip.com wrote:
> >> Hi Alessandro, Alexandre,
> >> If one of you could take a look at this, that'd be great.
> >
> > I actually expected someone else to apply this, what is your plan?
>
> I was going to ask Palmer to take the series via riscv. Since I have
> Rob's R-b, I was just looking for a subsystem maintainer ack/R-b before
> actually asking him.
>
Rob's review is enough for a DT binding, no need to wait for me. but
FWIW:
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Thanks,
> Conor.
>
> >
> >> Thanks,
> >> Conor.
> >>
> >> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> >>> From: Conor Dooley <conor.dooley@microchip.com>
> >>>
> >>> Add device tree bindings for the real time clock on
> >>> the Microchip PolarFire SoC.
> >>>
> >>> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> >>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> >>> Reviewed-by: Rob Herring <robh@kernel.org>
> >>> ---
> >>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++
> >>> 1 file changed, 58 insertions(+)
> >>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> >>> new file mode 100644
> >>> index 000000000000..a2e984ea3553
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> >>> @@ -0,0 +1,58 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
> >>> +
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
> >>> +
> >>> +allOf:
> >>> + - $ref: rtc.yaml#
> >>> +
> >>> +maintainers:
> >>> + - Daire McNamara <daire.mcnamara@microchip.com>
> >>> + - Lewis Hanly <lewis.hanly@microchip.com>
> >>> +
> >>> +properties:
> >>> + compatible:
> >>> + enum:
> >>> + - microchip,mpfs-rtc
> >>> +
> >>> + reg:
> >>> + maxItems: 1
> >>> +
> >>> + interrupts:
> >>> + items:
> >>> + - description: |
> >>> + RTC_WAKEUP interrupt
> >>> + - description: |
> >>> + RTC_MATCH, asserted when the content of the Alarm register is equal
> >>> + to that of the RTC's count register.
> >>> +
> >>> + clocks:
> >>> + maxItems: 1
> >>> +
> >>> + clock-names:
> >>> + items:
> >>> + - const: rtc
> >>> +
> >>> +required:
> >>> + - compatible
> >>> + - reg
> >>> + - interrupts
> >>> + - clocks
> >>> + - clock-names
> >>> +
> >>> +additionalProperties: false
> >>> +
> >>> +examples:
> >>> + - |
> >>> + rtc@20124000 {
> >>> + compatible = "microchip,mpfs-rtc";
> >>> + reg = <0x20124000 0x1000>;
> >>> + clocks = <&clkcfg 21>;
> >>> + clock-names = "rtc";
> >>> + interrupts = <80>, <81>;
> >>> + };
> >>> +...
> >>
> >
> > --
> > Alexandre Belloni, co-owner and COO, Bootlin
> > Embedded Linux and Kernel engineering
> > https://bootlin.com
>
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc
2022-02-23 20:20 ` Alexandre Belloni
@ 2022-02-23 20:26 ` Conor Dooley
-1 siblings, 0 replies; 64+ messages in thread
From: Conor Dooley @ 2022-02-23 20:26 UTC (permalink / raw)
To: Alexandre Belloni, Conor.Dooley
Cc: a.zummo, Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp,
palmer, robh, linus.walleij, brgl, robh+dt, jassisinghbrar,
thierry.reding, u.kleine-koenig, lee.jones, paul.walmsley,
palmer, aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv
On 23/02/2022 20:20, Alexandre Belloni wrote:
> On 23/02/2022 15:25:00+0000, Conor.Dooley@microchip.com wrote:
>> On 23/02/2022 15:18, Alexandre Belloni wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 23/02/2022 07:41:27+0000, Conor.Dooley@microchip.com wrote:
>>>> Hi Alessandro, Alexandre,
>>>> If one of you could take a look at this, that'd be great.
>>>
>>> I actually expected someone else to apply this, what is your plan?
>>
>> I was going to ask Palmer to take the series via riscv. Since I have
>> Rob's R-b, I was just looking for a subsystem maintainer ack/R-b before
>> actually asking him.
>>
>
> Rob's review is enough for a DT binding, no need to wait for me. but
> FWIW:
>
> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Great, thanks.
>
>
>> Thanks,
>> Conor.
>>
>>>
>>>> Thanks,
>>>> Conor.
>>>>
>>>> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>
>>>>> Add device tree bindings for the real time clock on
>>>>> the Microchip PolarFire SoC.
>>>>>
>>>>> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>>>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>>>> ---
>>>>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++
>>>>> 1 file changed, 58 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..a2e984ea3553
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>>>> @@ -0,0 +1,58 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
>>>>> +
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
>>>>> +
>>>>> +allOf:
>>>>> + - $ref: rtc.yaml#
>>>>> +
>>>>> +maintainers:
>>>>> + - Daire McNamara <daire.mcnamara@microchip.com>
>>>>> + - Lewis Hanly <lewis.hanly@microchip.com>
>>>>> +
>>>>> +properties:
>>>>> + compatible:
>>>>> + enum:
>>>>> + - microchip,mpfs-rtc
>>>>> +
>>>>> + reg:
>>>>> + maxItems: 1
>>>>> +
>>>>> + interrupts:
>>>>> + items:
>>>>> + - description: |
>>>>> + RTC_WAKEUP interrupt
>>>>> + - description: |
>>>>> + RTC_MATCH, asserted when the content of the Alarm register is equal
>>>>> + to that of the RTC's count register.
>>>>> +
>>>>> + clocks:
>>>>> + maxItems: 1
>>>>> +
>>>>> + clock-names:
>>>>> + items:
>>>>> + - const: rtc
>>>>> +
>>>>> +required:
>>>>> + - compatible
>>>>> + - reg
>>>>> + - interrupts
>>>>> + - clocks
>>>>> + - clock-names
>>>>> +
>>>>> +additionalProperties: false
>>>>> +
>>>>> +examples:
>>>>> + - |
>>>>> + rtc@20124000 {
>>>>> + compatible = "microchip,mpfs-rtc";
>>>>> + reg = <0x20124000 0x1000>;
>>>>> + clocks = <&clkcfg 21>;
>>>>> + clock-names = "rtc";
>>>>> + interrupts = <80>, <81>;
>>>>> + };
>>>>> +...
>>>>
>>>
>>> --
>>> Alexandre Belloni, co-owner and COO, Bootlin
>>> Embedded Linux and Kernel engineering
>>> https://bootlin.com
>>
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc
@ 2022-02-23 20:26 ` Conor Dooley
0 siblings, 0 replies; 64+ messages in thread
From: Conor Dooley @ 2022-02-23 20:26 UTC (permalink / raw)
To: Alexandre Belloni, Conor.Dooley
Cc: a.zummo, Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp,
palmer, robh, linus.walleij, brgl, robh+dt, jassisinghbrar,
thierry.reding, u.kleine-koenig, lee.jones, paul.walmsley,
palmer, aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv
On 23/02/2022 20:20, Alexandre Belloni wrote:
> On 23/02/2022 15:25:00+0000, Conor.Dooley@microchip.com wrote:
>> On 23/02/2022 15:18, Alexandre Belloni wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 23/02/2022 07:41:27+0000, Conor.Dooley@microchip.com wrote:
>>>> Hi Alessandro, Alexandre,
>>>> If one of you could take a look at this, that'd be great.
>>>
>>> I actually expected someone else to apply this, what is your plan?
>>
>> I was going to ask Palmer to take the series via riscv. Since I have
>> Rob's R-b, I was just looking for a subsystem maintainer ack/R-b before
>> actually asking him.
>>
>
> Rob's review is enough for a DT binding, no need to wait for me. but
> FWIW:
>
> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Great, thanks.
>
>
>> Thanks,
>> Conor.
>>
>>>
>>>> Thanks,
>>>> Conor.
>>>>
>>>> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>
>>>>> Add device tree bindings for the real time clock on
>>>>> the Microchip PolarFire SoC.
>>>>>
>>>>> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>>>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>>>> ---
>>>>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++
>>>>> 1 file changed, 58 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..a2e984ea3553
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>>>> @@ -0,0 +1,58 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
>>>>> +
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
>>>>> +
>>>>> +allOf:
>>>>> + - $ref: rtc.yaml#
>>>>> +
>>>>> +maintainers:
>>>>> + - Daire McNamara <daire.mcnamara@microchip.com>
>>>>> + - Lewis Hanly <lewis.hanly@microchip.com>
>>>>> +
>>>>> +properties:
>>>>> + compatible:
>>>>> + enum:
>>>>> + - microchip,mpfs-rtc
>>>>> +
>>>>> + reg:
>>>>> + maxItems: 1
>>>>> +
>>>>> + interrupts:
>>>>> + items:
>>>>> + - description: |
>>>>> + RTC_WAKEUP interrupt
>>>>> + - description: |
>>>>> + RTC_MATCH, asserted when the content of the Alarm register is equal
>>>>> + to that of the RTC's count register.
>>>>> +
>>>>> + clocks:
>>>>> + maxItems: 1
>>>>> +
>>>>> + clock-names:
>>>>> + items:
>>>>> + - const: rtc
>>>>> +
>>>>> +required:
>>>>> + - compatible
>>>>> + - reg
>>>>> + - interrupts
>>>>> + - clocks
>>>>> + - clock-names
>>>>> +
>>>>> +additionalProperties: false
>>>>> +
>>>>> +examples:
>>>>> + - |
>>>>> + rtc@20124000 {
>>>>> + compatible = "microchip,mpfs-rtc";
>>>>> + reg = <0x20124000 0x1000>;
>>>>> + clocks = <&clkcfg 21>;
>>>>> + clock-names = "rtc";
>>>>> + interrupts = <80>, <81>;
>>>>> + };
>>>>> +...
>>>>
>>>
>>> --
>>> Alexandre Belloni, co-owner and COO, Bootlin
>>> Embedded Linux and Kernel engineering
>>> https://bootlin.com
>>
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 00/11] Update the Icicle Kit device tree
2022-02-14 13:58 ` conor.dooley
@ 2022-02-23 20:48 ` Conor Dooley
-1 siblings, 0 replies; 64+ messages in thread
From: Conor Dooley @ 2022-02-23 20:48 UTC (permalink / raw)
To: palmer
Cc: lewis.hanly, daire.mcnamara, ivan.griffin, atishp, conor.dooley,
linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, aou, geert, krzysztof.kozlowski, linux-gpio,
devicetree, linux-kernel, linux-pwm, linux-rtc, linux-riscv
On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> This series updates the Microchip Icicle Kit device tree by adding a
> host of peripherals, and some updates to the memory map. In addition,
> the device tree has been split into a third part, which contains "soft"
> peripherals that are in the fpga fabric.
>
> Several of the entries are for peripherals that have not get had their
> drivers upstreamed, so in those cases the dt bindings are included where
> appropriate in order to avoid the many "DT compatible string <x> appears
> un-documented" errors.
>
> Depends on mpfs clock driver binding (on clk/next) to provide
> dt-bindings/clock/microchip,mpfs-clock.h for the device tree
> and on the other changes to the icicle/mpfs device tree from geert
> that are already in linux/riscv/for-next.
>
> Additionally, the interrupt-extended warnings on the plic/clint are
> cleared by [1] & [2].
>
> [1] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/
> [2] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/
Hey Palmer,
dt-bindings should be set now, so if you're still happy to take the
series via riscv, that'd be great. i2c, spi & usb patches ended going
via the sub-system trees (and have been dropped from the series), in
case those generate warnings for you.
Thanks,
Conor.
>
> Changes from v6:
> - Dropped i2c patch, as its in i2c-next
> - Added ack on gpio, reviewed-by on rtc
> - Dropped child nodes from sysctrl binding entirely, added a link to
> the online documenation for the services the system controller can
> provide
> - Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's
> series
>
> Changes from v5:
> - reworded the descriptions in the pwm binding to (hopefully) add
> clarity
> - added -mask to the custom properties and made them 32 bit
> - renamed the i2c binding to corei2c, since it is not mpfs specific
> - removed the child nodes of the system controller in example/dts &
> will create them in the driver.
> @Rob, I assume keeping them documented is the correct thing to do?
> - removed the dependancy on the clock binding from the examples
> - reformatted rtc interrupts as per Rob's suggestion
>
> Changes from v4:
> - dont include icicle_kit_defconfig, accidentally added in v3
> - drop prescaler from mpfs-rtc & calculate the value instead
> - use corei2c as a fallback device for mpfs-i2c
> - drop spi dt-binding (on spi-next)
> commit 2da187304e556ac59cf2dacb323cc78ded988169
> - drop usb dt-binding (on usb-next)
>
> Changes from v3:
> - drop "mailbox: change mailbox-mpfs compatible string", already upstream:
> commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
> - fix copy paste error in microchip,mpfs-mailbox dt-binding
> - remove whitespace in syscontroller dt entry
>
> Changes from v2:
> - dropped plic int header & corresponding defines in dts{,i}
> - use $ref to drmode in mpfs-musb binding
> - split changes to dts{,i} again: functional changes to existing
> elements now are in a new patch
> - drop num-cs property in mpfs-spi binding
> - dont make the system controller a simple-mfd
> - move the separate bindings for rng/generic system services into the
> system controller binding
> - added an instance corei2c as i2c2 in the fabric dtsi
> - add version numbering to corepwm and corei2c compat string (-rtl-vN)
>
> Conor Dooley (11):
> dt-bindings: soc/microchip: update syscontroller compatibles
> dt-bindings: soc/microchip: add info about services to mpfs sysctrl
> dt-bindings: rtc: add bindings for microchip mpfs rtc
> dt-bindings: gpio: add bindings for microchip mpfs gpio
> dt-bindings: pwm: add microchip corepwm binding
> riscv: dts: microchip: use clk defines for icicle kit
> riscv: dts: microchip: add fpga fabric section to icicle kit
> riscv: dts: microchip: refactor icicle kit device tree
> riscv: dts: microchip: update peripherals in icicle kit device tree
> riscv: dts: microchip: add new peripherals to icicle kit device tree
> MAINTAINERS: update riscv/microchip entry
>
> .../bindings/gpio/microchip,mpfs-gpio.yaml | 79 ++++++
> ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +-
> .../bindings/pwm/microchip,corepwm.yaml | 81 ++++++
> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 ++++
> .../microchip,mpfs-sys-controller.yaml | 40 +++
> ...icrochip,polarfire-soc-sys-controller.yaml | 35 ---
> MAINTAINERS | 2 +
> .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++
> .../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++--
> .../boot/dts/microchip/microchip-mpfs.dtsi | 254 ++++++++++++++----
> 10 files changed, 591 insertions(+), 104 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
> rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 00/11] Update the Icicle Kit device tree
@ 2022-02-23 20:48 ` Conor Dooley
0 siblings, 0 replies; 64+ messages in thread
From: Conor Dooley @ 2022-02-23 20:48 UTC (permalink / raw)
To: palmer
Cc: lewis.hanly, daire.mcnamara, ivan.griffin, atishp, conor.dooley,
linus.walleij, brgl, robh+dt, jassisinghbrar, thierry.reding,
u.kleine-koenig, lee.jones, a.zummo, alexandre.belloni,
paul.walmsley, aou, geert, krzysztof.kozlowski, linux-gpio,
devicetree, linux-kernel, linux-pwm, linux-rtc, linux-riscv
On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> This series updates the Microchip Icicle Kit device tree by adding a
> host of peripherals, and some updates to the memory map. In addition,
> the device tree has been split into a third part, which contains "soft"
> peripherals that are in the fpga fabric.
>
> Several of the entries are for peripherals that have not get had their
> drivers upstreamed, so in those cases the dt bindings are included where
> appropriate in order to avoid the many "DT compatible string <x> appears
> un-documented" errors.
>
> Depends on mpfs clock driver binding (on clk/next) to provide
> dt-bindings/clock/microchip,mpfs-clock.h for the device tree
> and on the other changes to the icicle/mpfs device tree from geert
> that are already in linux/riscv/for-next.
>
> Additionally, the interrupt-extended warnings on the plic/clint are
> cleared by [1] & [2].
>
> [1] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/
> [2] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/
Hey Palmer,
dt-bindings should be set now, so if you're still happy to take the
series via riscv, that'd be great. i2c, spi & usb patches ended going
via the sub-system trees (and have been dropped from the series), in
case those generate warnings for you.
Thanks,
Conor.
>
> Changes from v6:
> - Dropped i2c patch, as its in i2c-next
> - Added ack on gpio, reviewed-by on rtc
> - Dropped child nodes from sysctrl binding entirely, added a link to
> the online documenation for the services the system controller can
> provide
> - Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's
> series
>
> Changes from v5:
> - reworded the descriptions in the pwm binding to (hopefully) add
> clarity
> - added -mask to the custom properties and made them 32 bit
> - renamed the i2c binding to corei2c, since it is not mpfs specific
> - removed the child nodes of the system controller in example/dts &
> will create them in the driver.
> @Rob, I assume keeping them documented is the correct thing to do?
> - removed the dependancy on the clock binding from the examples
> - reformatted rtc interrupts as per Rob's suggestion
>
> Changes from v4:
> - dont include icicle_kit_defconfig, accidentally added in v3
> - drop prescaler from mpfs-rtc & calculate the value instead
> - use corei2c as a fallback device for mpfs-i2c
> - drop spi dt-binding (on spi-next)
> commit 2da187304e556ac59cf2dacb323cc78ded988169
> - drop usb dt-binding (on usb-next)
>
> Changes from v3:
> - drop "mailbox: change mailbox-mpfs compatible string", already upstream:
> commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
> - fix copy paste error in microchip,mpfs-mailbox dt-binding
> - remove whitespace in syscontroller dt entry
>
> Changes from v2:
> - dropped plic int header & corresponding defines in dts{,i}
> - use $ref to drmode in mpfs-musb binding
> - split changes to dts{,i} again: functional changes to existing
> elements now are in a new patch
> - drop num-cs property in mpfs-spi binding
> - dont make the system controller a simple-mfd
> - move the separate bindings for rng/generic system services into the
> system controller binding
> - added an instance corei2c as i2c2 in the fabric dtsi
> - add version numbering to corepwm and corei2c compat string (-rtl-vN)
>
> Conor Dooley (11):
> dt-bindings: soc/microchip: update syscontroller compatibles
> dt-bindings: soc/microchip: add info about services to mpfs sysctrl
> dt-bindings: rtc: add bindings for microchip mpfs rtc
> dt-bindings: gpio: add bindings for microchip mpfs gpio
> dt-bindings: pwm: add microchip corepwm binding
> riscv: dts: microchip: use clk defines for icicle kit
> riscv: dts: microchip: add fpga fabric section to icicle kit
> riscv: dts: microchip: refactor icicle kit device tree
> riscv: dts: microchip: update peripherals in icicle kit device tree
> riscv: dts: microchip: add new peripherals to icicle kit device tree
> MAINTAINERS: update riscv/microchip entry
>
> .../bindings/gpio/microchip,mpfs-gpio.yaml | 79 ++++++
> ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +-
> .../bindings/pwm/microchip,corepwm.yaml | 81 ++++++
> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 ++++
> .../microchip,mpfs-sys-controller.yaml | 40 +++
> ...icrochip,polarfire-soc-sys-controller.yaml | 35 ---
> MAINTAINERS | 2 +
> .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++
> .../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++--
> .../boot/dts/microchip/microchip-mpfs.dtsi | 254 ++++++++++++++----
> 10 files changed, 591 insertions(+), 104 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
> rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
2022-02-14 13:58 ` conor.dooley
@ 2022-02-24 13:19 ` Thierry Reding
-1 siblings, 0 replies; 64+ messages in thread
From: Thierry Reding @ 2022-02-24 13:19 UTC (permalink / raw)
To: conor.dooley
Cc: linus.walleij, brgl, robh+dt, jassisinghbrar, u.kleine-koenig,
lee.jones, a.zummo, alexandre.belloni, paul.walmsley, palmer,
aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv, lewis.hanly,
daire.mcnamara, ivan.griffin, atishp, Rob Herring,
Palmer Dabbelt
[-- Attachment #1: Type: text/plain, Size: 687 bytes --]
On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the Microchip fpga fabric based "core" PWM
> controller.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> .../bindings/pwm/microchip,corepwm.yaml | 81 +++++++++++++++++++
> 1 file changed, 81 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
Fine with me to go through the RISC-V tree:
Acked-by: Thierry Reding <thierry.reding@gmail.com>
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding
@ 2022-02-24 13:19 ` Thierry Reding
0 siblings, 0 replies; 64+ messages in thread
From: Thierry Reding @ 2022-02-24 13:19 UTC (permalink / raw)
To: conor.dooley
Cc: linus.walleij, brgl, robh+dt, jassisinghbrar, u.kleine-koenig,
lee.jones, a.zummo, alexandre.belloni, paul.walmsley, palmer,
aou, geert, krzysztof.kozlowski, linux-gpio, devicetree,
linux-kernel, linux-pwm, linux-rtc, linux-riscv, lewis.hanly,
daire.mcnamara, ivan.griffin, atishp, Rob Herring,
Palmer Dabbelt
[-- Attachment #1.1: Type: text/plain, Size: 687 bytes --]
On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the Microchip fpga fabric based "core" PWM
> controller.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> .../bindings/pwm/microchip,corepwm.yaml | 81 +++++++++++++++++++
> 1 file changed, 81 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
Fine with me to go through the RISC-V tree:
Acked-by: Thierry Reding <thierry.reding@gmail.com>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 00/11] Update the Icicle Kit device tree
2022-02-23 20:48 ` Conor Dooley
@ 2022-03-10 7:07 ` Palmer Dabbelt
-1 siblings, 0 replies; 64+ messages in thread
From: Palmer Dabbelt @ 2022-03-10 7:07 UTC (permalink / raw)
To: mail, sboyd
Cc: lewis.hanly, daire.mcnamara, ivan.griffin, Atish Patra,
conor.dooley, linus.walleij, brgl, robh+dt, jassisinghbrar,
thierry.reding, u.kleine-koenig, lee.jones, a.zummo,
alexandre.belloni, Paul Walmsley, aou, geert,
krzysztof.kozlowski, linux-gpio, devicetree, linux-kernel,
linux-pwm, linux-rtc, linux-riscv
On Wed, 23 Feb 2022 12:48:16 PST (-0800), mail@conchuod.ie wrote:
> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> This series updates the Microchip Icicle Kit device tree by adding a
>> host of peripherals, and some updates to the memory map. In addition,
>> the device tree has been split into a third part, which contains "soft"
>> peripherals that are in the fpga fabric.
>>
>> Several of the entries are for peripherals that have not get had their
>> drivers upstreamed, so in those cases the dt bindings are included where
>> appropriate in order to avoid the many "DT compatible string <x> appears
>> un-documented" errors.
>>
>> Depends on mpfs clock driver binding (on clk/next) to provide
>> dt-bindings/clock/microchip,mpfs-clock.h for the device tree
>> and on the other changes to the icicle/mpfs device tree from geert
>> that are already in linux/riscv/for-next.
So that's causing this to not build, as I can't build without the
header. I went ahead and put these on top of that patch, resulting in
* 48e8641c2bf0 - (HEAD -> riscv-microchip, palmer/riscv-microchip) MAINTAINERS: update riscv/microchip entry (2 minutes ago) <Conor Dooley>
* 528a5b1f2556 - riscv: dts: microchip: add new peripherals to icicle kit device tree (2 minutes ago) <Conor Dooley>
* 5b28df37d311 - riscv: dts: microchip: update peripherals in icicle kit device tree (2 minutes ago) <Conor Dooley>
* c5094f371008 - riscv: dts: microchip: refactor icicle kit device tree (2 minutes ago) <Conor Dooley>
* 72560c6559b8 - riscv: dts: microchip: add fpga fabric section to icicle kit (2 minutes ago) <Conor Dooley>
* 6546f920868e - riscv: dts: microchip: use clk defines for icicle kit (2 minutes ago) <Conor Dooley>
* df77f7735786 - dt-bindings: pwm: add microchip corepwm binding (2 minutes ago) <Conor Dooley>
* 735806d8a68e - dt-bindings: gpio: add bindings for microchip mpfs gpio (2 minutes ago) <Conor Dooley>
* 4cbcc0d7b397 - dt-bindings: rtc: add bindings for microchip mpfs rtc (2 minutes ago) <Conor Dooley>
* b435a1728c9f - dt-bindings: soc/microchip: add info about services to mpfs sysctrl (2 minutes ago) <Conor Dooley>
* 213556235526 - dt-bindings: soc/microchip: update syscontroller compatibles (2 minutes ago) <Conor Dooley>
* 2145bb687e3f - (clk/clk-microchip) dt-bindings: clk: microchip: Add Microchip PolarFire host binding (6 weeks ago) <Daire McNamara>
* e783362eb54c - (tag: v5.17-rc1) Linux 5.17-rc1 (7 weeks ago) <Linus Torvalds>
sboyd: IIRC it's OK to consider clk-microchip as a stable branch? If
not I can just wait until you send your PR to Linus and send this later
in the merge window, no big deal on my end.
I've put this on for-next. If that's a problem let me know and I'll
delay it.
Thanks!
>>
>> Additionally, the interrupt-extended warnings on the plic/clint are
>> cleared by [1] & [2].
>>
>> [1] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/
>> [2] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/
>
> Hey Palmer,
>
> dt-bindings should be set now, so if you're still happy to take the
> series via riscv, that'd be great. i2c, spi & usb patches ended going
> via the sub-system trees (and have been dropped from the series), in
> case those generate warnings for you.
Something went off the rails in email land and #0 and #2 didn't end up
in my patch queue but the rest did. Luckily enough made it through that
it didn't get lost, and lore's pretty great so this sort of thing isn't
that big of a deal these days. That said, email is a bit of a black box
so figured I'd give you a heads up.
>
> Thanks,
> Conor.
>>
>> Changes from v6:
>> - Dropped i2c patch, as its in i2c-next
>> - Added ack on gpio, reviewed-by on rtc
>> - Dropped child nodes from sysctrl binding entirely, added a link to
>> the online documenation for the services the system controller can
>> provide
>> - Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's
>> series
>>
>> Changes from v5:
>> - reworded the descriptions in the pwm binding to (hopefully) add
>> clarity
>> - added -mask to the custom properties and made them 32 bit
>> - renamed the i2c binding to corei2c, since it is not mpfs specific
>> - removed the child nodes of the system controller in example/dts &
>> will create them in the driver.
>> @Rob, I assume keeping them documented is the correct thing to do?
>> - removed the dependancy on the clock binding from the examples
>> - reformatted rtc interrupts as per Rob's suggestion
>>
>> Changes from v4:
>> - dont include icicle_kit_defconfig, accidentally added in v3
>> - drop prescaler from mpfs-rtc & calculate the value instead
>> - use corei2c as a fallback device for mpfs-i2c
>> - drop spi dt-binding (on spi-next)
>> commit 2da187304e556ac59cf2dacb323cc78ded988169
>> - drop usb dt-binding (on usb-next)
>>
>> Changes from v3:
>> - drop "mailbox: change mailbox-mpfs compatible string", already upstream:
>> commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
>> - fix copy paste error in microchip,mpfs-mailbox dt-binding
>> - remove whitespace in syscontroller dt entry
>>
>> Changes from v2:
>> - dropped plic int header & corresponding defines in dts{,i}
>> - use $ref to drmode in mpfs-musb binding
>> - split changes to dts{,i} again: functional changes to existing
>> elements now are in a new patch
>> - drop num-cs property in mpfs-spi binding
>> - dont make the system controller a simple-mfd
>> - move the separate bindings for rng/generic system services into the
>> system controller binding
>> - added an instance corei2c as i2c2 in the fabric dtsi
>> - add version numbering to corepwm and corei2c compat string (-rtl-vN)
>>
>> Conor Dooley (11):
>> dt-bindings: soc/microchip: update syscontroller compatibles
>> dt-bindings: soc/microchip: add info about services to mpfs sysctrl
>> dt-bindings: rtc: add bindings for microchip mpfs rtc
>> dt-bindings: gpio: add bindings for microchip mpfs gpio
>> dt-bindings: pwm: add microchip corepwm binding
>> riscv: dts: microchip: use clk defines for icicle kit
>> riscv: dts: microchip: add fpga fabric section to icicle kit
>> riscv: dts: microchip: refactor icicle kit device tree
>> riscv: dts: microchip: update peripherals in icicle kit device tree
>> riscv: dts: microchip: add new peripherals to icicle kit device tree
>> MAINTAINERS: update riscv/microchip entry
>>
>> .../bindings/gpio/microchip,mpfs-gpio.yaml | 79 ++++++
>> ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +-
>> .../bindings/pwm/microchip,corepwm.yaml | 81 ++++++
>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 ++++
>> .../microchip,mpfs-sys-controller.yaml | 40 +++
>> ...icrochip,polarfire-soc-sys-controller.yaml | 35 ---
>> MAINTAINERS | 2 +
>> .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++
>> .../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++--
>> .../boot/dts/microchip/microchip-mpfs.dtsi | 254 ++++++++++++++----
>> 10 files changed, 591 insertions(+), 104 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
>> rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
>> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>> create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
>> delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 00/11] Update the Icicle Kit device tree
@ 2022-03-10 7:07 ` Palmer Dabbelt
0 siblings, 0 replies; 64+ messages in thread
From: Palmer Dabbelt @ 2022-03-10 7:07 UTC (permalink / raw)
To: mail, sboyd
Cc: lewis.hanly, daire.mcnamara, ivan.griffin, Atish Patra,
conor.dooley, linus.walleij, brgl, robh+dt, jassisinghbrar,
thierry.reding, u.kleine-koenig, lee.jones, a.zummo,
alexandre.belloni, Paul Walmsley, aou, geert,
krzysztof.kozlowski, linux-gpio, devicetree, linux-kernel,
linux-pwm, linux-rtc, linux-riscv
On Wed, 23 Feb 2022 12:48:16 PST (-0800), mail@conchuod.ie wrote:
> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> This series updates the Microchip Icicle Kit device tree by adding a
>> host of peripherals, and some updates to the memory map. In addition,
>> the device tree has been split into a third part, which contains "soft"
>> peripherals that are in the fpga fabric.
>>
>> Several of the entries are for peripherals that have not get had their
>> drivers upstreamed, so in those cases the dt bindings are included where
>> appropriate in order to avoid the many "DT compatible string <x> appears
>> un-documented" errors.
>>
>> Depends on mpfs clock driver binding (on clk/next) to provide
>> dt-bindings/clock/microchip,mpfs-clock.h for the device tree
>> and on the other changes to the icicle/mpfs device tree from geert
>> that are already in linux/riscv/for-next.
So that's causing this to not build, as I can't build without the
header. I went ahead and put these on top of that patch, resulting in
* 48e8641c2bf0 - (HEAD -> riscv-microchip, palmer/riscv-microchip) MAINTAINERS: update riscv/microchip entry (2 minutes ago) <Conor Dooley>
* 528a5b1f2556 - riscv: dts: microchip: add new peripherals to icicle kit device tree (2 minutes ago) <Conor Dooley>
* 5b28df37d311 - riscv: dts: microchip: update peripherals in icicle kit device tree (2 minutes ago) <Conor Dooley>
* c5094f371008 - riscv: dts: microchip: refactor icicle kit device tree (2 minutes ago) <Conor Dooley>
* 72560c6559b8 - riscv: dts: microchip: add fpga fabric section to icicle kit (2 minutes ago) <Conor Dooley>
* 6546f920868e - riscv: dts: microchip: use clk defines for icicle kit (2 minutes ago) <Conor Dooley>
* df77f7735786 - dt-bindings: pwm: add microchip corepwm binding (2 minutes ago) <Conor Dooley>
* 735806d8a68e - dt-bindings: gpio: add bindings for microchip mpfs gpio (2 minutes ago) <Conor Dooley>
* 4cbcc0d7b397 - dt-bindings: rtc: add bindings for microchip mpfs rtc (2 minutes ago) <Conor Dooley>
* b435a1728c9f - dt-bindings: soc/microchip: add info about services to mpfs sysctrl (2 minutes ago) <Conor Dooley>
* 213556235526 - dt-bindings: soc/microchip: update syscontroller compatibles (2 minutes ago) <Conor Dooley>
* 2145bb687e3f - (clk/clk-microchip) dt-bindings: clk: microchip: Add Microchip PolarFire host binding (6 weeks ago) <Daire McNamara>
* e783362eb54c - (tag: v5.17-rc1) Linux 5.17-rc1 (7 weeks ago) <Linus Torvalds>
sboyd: IIRC it's OK to consider clk-microchip as a stable branch? If
not I can just wait until you send your PR to Linus and send this later
in the merge window, no big deal on my end.
I've put this on for-next. If that's a problem let me know and I'll
delay it.
Thanks!
>>
>> Additionally, the interrupt-extended warnings on the plic/clint are
>> cleared by [1] & [2].
>>
>> [1] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/
>> [2] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/
>
> Hey Palmer,
>
> dt-bindings should be set now, so if you're still happy to take the
> series via riscv, that'd be great. i2c, spi & usb patches ended going
> via the sub-system trees (and have been dropped from the series), in
> case those generate warnings for you.
Something went off the rails in email land and #0 and #2 didn't end up
in my patch queue but the rest did. Luckily enough made it through that
it didn't get lost, and lore's pretty great so this sort of thing isn't
that big of a deal these days. That said, email is a bit of a black box
so figured I'd give you a heads up.
>
> Thanks,
> Conor.
>>
>> Changes from v6:
>> - Dropped i2c patch, as its in i2c-next
>> - Added ack on gpio, reviewed-by on rtc
>> - Dropped child nodes from sysctrl binding entirely, added a link to
>> the online documenation for the services the system controller can
>> provide
>> - Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's
>> series
>>
>> Changes from v5:
>> - reworded the descriptions in the pwm binding to (hopefully) add
>> clarity
>> - added -mask to the custom properties and made them 32 bit
>> - renamed the i2c binding to corei2c, since it is not mpfs specific
>> - removed the child nodes of the system controller in example/dts &
>> will create them in the driver.
>> @Rob, I assume keeping them documented is the correct thing to do?
>> - removed the dependancy on the clock binding from the examples
>> - reformatted rtc interrupts as per Rob's suggestion
>>
>> Changes from v4:
>> - dont include icicle_kit_defconfig, accidentally added in v3
>> - drop prescaler from mpfs-rtc & calculate the value instead
>> - use corei2c as a fallback device for mpfs-i2c
>> - drop spi dt-binding (on spi-next)
>> commit 2da187304e556ac59cf2dacb323cc78ded988169
>> - drop usb dt-binding (on usb-next)
>>
>> Changes from v3:
>> - drop "mailbox: change mailbox-mpfs compatible string", already upstream:
>> commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
>> - fix copy paste error in microchip,mpfs-mailbox dt-binding
>> - remove whitespace in syscontroller dt entry
>>
>> Changes from v2:
>> - dropped plic int header & corresponding defines in dts{,i}
>> - use $ref to drmode in mpfs-musb binding
>> - split changes to dts{,i} again: functional changes to existing
>> elements now are in a new patch
>> - drop num-cs property in mpfs-spi binding
>> - dont make the system controller a simple-mfd
>> - move the separate bindings for rng/generic system services into the
>> system controller binding
>> - added an instance corei2c as i2c2 in the fabric dtsi
>> - add version numbering to corepwm and corei2c compat string (-rtl-vN)
>>
>> Conor Dooley (11):
>> dt-bindings: soc/microchip: update syscontroller compatibles
>> dt-bindings: soc/microchip: add info about services to mpfs sysctrl
>> dt-bindings: rtc: add bindings for microchip mpfs rtc
>> dt-bindings: gpio: add bindings for microchip mpfs gpio
>> dt-bindings: pwm: add microchip corepwm binding
>> riscv: dts: microchip: use clk defines for icicle kit
>> riscv: dts: microchip: add fpga fabric section to icicle kit
>> riscv: dts: microchip: refactor icicle kit device tree
>> riscv: dts: microchip: update peripherals in icicle kit device tree
>> riscv: dts: microchip: add new peripherals to icicle kit device tree
>> MAINTAINERS: update riscv/microchip entry
>>
>> .../bindings/gpio/microchip,mpfs-gpio.yaml | 79 ++++++
>> ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +-
>> .../bindings/pwm/microchip,corepwm.yaml | 81 ++++++
>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 ++++
>> .../microchip,mpfs-sys-controller.yaml | 40 +++
>> ...icrochip,polarfire-soc-sys-controller.yaml | 35 ---
>> MAINTAINERS | 2 +
>> .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++
>> .../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++--
>> .../boot/dts/microchip/microchip-mpfs.dtsi | 254 ++++++++++++++----
>> 10 files changed, 591 insertions(+), 104 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
>> rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
>> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>> create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
>> delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 00/11] Update the Icicle Kit device tree
2022-03-10 7:07 ` Palmer Dabbelt
@ 2022-03-10 7:35 ` Conor.Dooley
-1 siblings, 0 replies; 64+ messages in thread
From: Conor.Dooley @ 2022-03-10 7:35 UTC (permalink / raw)
To: palmer, sboyd, zong.li
Cc: Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp, linus.walleij,
brgl, robh+dt, jassisinghbrar, thierry.reding, u.kleine-koenig,
lee.jones, a.zummo, alexandre.belloni, paul.walmsley, aou, geert,
krzysztof.kozlowski, linux-gpio, devicetree, linux-kernel,
linux-pwm, linux-rtc, linux-riscv
On 10/03/2022 07:07, Palmer Dabbelt wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Wed, 23 Feb 2022 12:48:16 PST (-0800), mail@conchuod.ie wrote:
>> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> This series updates the Microchip Icicle Kit device tree by adding a
>>> host of peripherals, and some updates to the memory map. In addition,
>>> the device tree has been split into a third part, which contains "soft"
>>> peripherals that are in the fpga fabric.
>>>
>>> Several of the entries are for peripherals that have not get had their
>>> drivers upstreamed, so in those cases the dt bindings are included where
>>> appropriate in order to avoid the many "DT compatible string <x> appears
>>> un-documented" errors.
>>>
>>> Depends on mpfs clock driver binding (on clk/next) to provide
>>> dt-bindings/clock/microchip,mpfs-clock.h for the device tree
>>> and on the other changes to the icicle/mpfs device tree from geert
>>> that are already in linux/riscv/for-next.
>
> So that's causing this to not build, as I can't build without the
> header. I went ahead and put these on top of that patch, resulting in
>
> * 48e8641c2bf0 - (HEAD -> riscv-microchip, palmer/riscv-microchip) MAINTAINERS: update riscv/microchip entry (2 minutes ago) <Conor Dooley>
> * 528a5b1f2556 - riscv: dts: microchip: add new peripherals to icicle kit device tree (2 minutes ago) <Conor Dooley>
> * 5b28df37d311 - riscv: dts: microchip: update peripherals in icicle kit device tree (2 minutes ago) <Conor Dooley>
> * c5094f371008 - riscv: dts: microchip: refactor icicle kit device tree (2 minutes ago) <Conor Dooley>
> * 72560c6559b8 - riscv: dts: microchip: add fpga fabric section to icicle kit (2 minutes ago) <Conor Dooley>
> * 6546f920868e - riscv: dts: microchip: use clk defines for icicle kit (2 minutes ago) <Conor Dooley>
> * df77f7735786 - dt-bindings: pwm: add microchip corepwm binding (2 minutes ago) <Conor Dooley>
> * 735806d8a68e - dt-bindings: gpio: add bindings for microchip mpfs gpio (2 minutes ago) <Conor Dooley>
> * 4cbcc0d7b397 - dt-bindings: rtc: add bindings for microchip mpfs rtc (2 minutes ago) <Conor Dooley>
> * b435a1728c9f - dt-bindings: soc/microchip: add info about services to mpfs sysctrl (2 minutes ago) <Conor Dooley>
> * 213556235526 - dt-bindings: soc/microchip: update syscontroller compatibles (2 minutes ago) <Conor Dooley>
> * 2145bb687e3f - (clk/clk-microchip) dt-bindings: clk: microchip: Add Microchip PolarFire host binding (6 weeks ago) <Daire McNamara>
> * e783362eb54c - (tag: v5.17-rc1) Linux 5.17-rc1 (7 weeks ago) <Linus Torvalds>
>
> sboyd: IIRC it's OK to consider clk-microchip as a stable branch? If
> not I can just wait until you send your PR to Linus and send this later
> in the merge window, no big deal on my end.
>
> I've put this on for-next. If that's a problem let me know and I'll
> delay it.
Great, thanks! Probably worth mentioning that I've deleted the dma node
that Zong Li is modifying in his pdma patchset.
>
> Thanks!
>
>>>
>>> Additionally, the interrupt-extended warnings on the plic/clint are
>>> cleared by [1] & [2].
>>>
>>> [1] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/
>>> [2] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/
>>
>> Hey Palmer,
>>
>> dt-bindings should be set now, so if you're still happy to take the
>> series via riscv, that'd be great. i2c, spi & usb patches ended going
>> via the sub-system trees (and have been dropped from the series), in
>> case those generate warnings for you.
>
> Something went off the rails in email land and #0 and #2 didn't end up
> in my patch queue but the rest did. Luckily enough made it through that
> it didn't get lost, and lore's pretty great so this sort of thing isn't
> that big of a deal these days. That said, email is a bit of a black box
> so figured I'd give you a heads up.
Huh, interesting. I do check after sending that I can see the mails in my
other email's inbox & they're there. Guess good thing that I sent the follow up.
Thanks,
Conor.
>
>>
>> Thanks,
>> Conor.
>>>
>>> Changes from v6:
>>> - Dropped i2c patch, as its in i2c-next
>>> - Added ack on gpio, reviewed-by on rtc
>>> - Dropped child nodes from sysctrl binding entirely, added a link to
>>> the online documenation for the services the system controller can
>>> provide
>>> - Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's
>>> series
>>>
>>> Changes from v5:
>>> - reworded the descriptions in the pwm binding to (hopefully) add
>>> clarity
>>> - added -mask to the custom properties and made them 32 bit
>>> - renamed the i2c binding to corei2c, since it is not mpfs specific
>>> - removed the child nodes of the system controller in example/dts &
>>> will create them in the driver.
>>> @Rob, I assume keeping them documented is the correct thing to do?
>>> - removed the dependancy on the clock binding from the examples
>>> - reformatted rtc interrupts as per Rob's suggestion
>>>
>>> Changes from v4:
>>> - dont include icicle_kit_defconfig, accidentally added in v3
>>> - drop prescaler from mpfs-rtc & calculate the value instead
>>> - use corei2c as a fallback device for mpfs-i2c
>>> - drop spi dt-binding (on spi-next)
>>> commit 2da187304e556ac59cf2dacb323cc78ded988169
>>> - drop usb dt-binding (on usb-next)
>>>
>>> Changes from v3:
>>> - drop "mailbox: change mailbox-mpfs compatible string", already upstream:
>>> commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
>>> - fix copy paste error in microchip,mpfs-mailbox dt-binding
>>> - remove whitespace in syscontroller dt entry
>>>
>>> Changes from v2:
>>> - dropped plic int header & corresponding defines in dts{,i}
>>> - use $ref to drmode in mpfs-musb binding
>>> - split changes to dts{,i} again: functional changes to existing
>>> elements now are in a new patch
>>> - drop num-cs property in mpfs-spi binding
>>> - dont make the system controller a simple-mfd
>>> - move the separate bindings for rng/generic system services into the
>>> system controller binding
>>> - added an instance corei2c as i2c2 in the fabric dtsi
>>> - add version numbering to corepwm and corei2c compat string (-rtl-vN)
>>>
>>> Conor Dooley (11):
>>> dt-bindings: soc/microchip: update syscontroller compatibles
>>> dt-bindings: soc/microchip: add info about services to mpfs sysctrl
>>> dt-bindings: rtc: add bindings for microchip mpfs rtc
>>> dt-bindings: gpio: add bindings for microchip mpfs gpio
>>> dt-bindings: pwm: add microchip corepwm binding
>>> riscv: dts: microchip: use clk defines for icicle kit
>>> riscv: dts: microchip: add fpga fabric section to icicle kit
>>> riscv: dts: microchip: refactor icicle kit device tree
>>> riscv: dts: microchip: update peripherals in icicle kit device tree
>>> riscv: dts: microchip: add new peripherals to icicle kit device tree
>>> MAINTAINERS: update riscv/microchip entry
>>>
>>> .../bindings/gpio/microchip,mpfs-gpio.yaml | 79 ++++++
>>> ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +-
>>> .../bindings/pwm/microchip,corepwm.yaml | 81 ++++++
>>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 ++++
>>> .../microchip,mpfs-sys-controller.yaml | 40 +++
>>> ...icrochip,polarfire-soc-sys-controller.yaml | 35 ---
>>> MAINTAINERS | 2 +
>>> .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++
>>> .../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++--
>>> .../boot/dts/microchip/microchip-mpfs.dtsi | 254 ++++++++++++++----
>>> 10 files changed, 591 insertions(+), 104 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
>>> rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
>>> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
>>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>> create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
>>> delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
>>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>>>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 00/11] Update the Icicle Kit device tree
@ 2022-03-10 7:35 ` Conor.Dooley
0 siblings, 0 replies; 64+ messages in thread
From: Conor.Dooley @ 2022-03-10 7:35 UTC (permalink / raw)
To: palmer, sboyd, zong.li
Cc: Lewis.Hanly, Daire.McNamara, Ivan.Griffin, atishp, linus.walleij,
brgl, robh+dt, jassisinghbrar, thierry.reding, u.kleine-koenig,
lee.jones, a.zummo, alexandre.belloni, paul.walmsley, aou, geert,
krzysztof.kozlowski, linux-gpio, devicetree, linux-kernel,
linux-pwm, linux-rtc, linux-riscv
On 10/03/2022 07:07, Palmer Dabbelt wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Wed, 23 Feb 2022 12:48:16 PST (-0800), mail@conchuod.ie wrote:
>> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> This series updates the Microchip Icicle Kit device tree by adding a
>>> host of peripherals, and some updates to the memory map. In addition,
>>> the device tree has been split into a third part, which contains "soft"
>>> peripherals that are in the fpga fabric.
>>>
>>> Several of the entries are for peripherals that have not get had their
>>> drivers upstreamed, so in those cases the dt bindings are included where
>>> appropriate in order to avoid the many "DT compatible string <x> appears
>>> un-documented" errors.
>>>
>>> Depends on mpfs clock driver binding (on clk/next) to provide
>>> dt-bindings/clock/microchip,mpfs-clock.h for the device tree
>>> and on the other changes to the icicle/mpfs device tree from geert
>>> that are already in linux/riscv/for-next.
>
> So that's causing this to not build, as I can't build without the
> header. I went ahead and put these on top of that patch, resulting in
>
> * 48e8641c2bf0 - (HEAD -> riscv-microchip, palmer/riscv-microchip) MAINTAINERS: update riscv/microchip entry (2 minutes ago) <Conor Dooley>
> * 528a5b1f2556 - riscv: dts: microchip: add new peripherals to icicle kit device tree (2 minutes ago) <Conor Dooley>
> * 5b28df37d311 - riscv: dts: microchip: update peripherals in icicle kit device tree (2 minutes ago) <Conor Dooley>
> * c5094f371008 - riscv: dts: microchip: refactor icicle kit device tree (2 minutes ago) <Conor Dooley>
> * 72560c6559b8 - riscv: dts: microchip: add fpga fabric section to icicle kit (2 minutes ago) <Conor Dooley>
> * 6546f920868e - riscv: dts: microchip: use clk defines for icicle kit (2 minutes ago) <Conor Dooley>
> * df77f7735786 - dt-bindings: pwm: add microchip corepwm binding (2 minutes ago) <Conor Dooley>
> * 735806d8a68e - dt-bindings: gpio: add bindings for microchip mpfs gpio (2 minutes ago) <Conor Dooley>
> * 4cbcc0d7b397 - dt-bindings: rtc: add bindings for microchip mpfs rtc (2 minutes ago) <Conor Dooley>
> * b435a1728c9f - dt-bindings: soc/microchip: add info about services to mpfs sysctrl (2 minutes ago) <Conor Dooley>
> * 213556235526 - dt-bindings: soc/microchip: update syscontroller compatibles (2 minutes ago) <Conor Dooley>
> * 2145bb687e3f - (clk/clk-microchip) dt-bindings: clk: microchip: Add Microchip PolarFire host binding (6 weeks ago) <Daire McNamara>
> * e783362eb54c - (tag: v5.17-rc1) Linux 5.17-rc1 (7 weeks ago) <Linus Torvalds>
>
> sboyd: IIRC it's OK to consider clk-microchip as a stable branch? If
> not I can just wait until you send your PR to Linus and send this later
> in the merge window, no big deal on my end.
>
> I've put this on for-next. If that's a problem let me know and I'll
> delay it.
Great, thanks! Probably worth mentioning that I've deleted the dma node
that Zong Li is modifying in his pdma patchset.
>
> Thanks!
>
>>>
>>> Additionally, the interrupt-extended warnings on the plic/clint are
>>> cleared by [1] & [2].
>>>
>>> [1] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/
>>> [2] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/
>>
>> Hey Palmer,
>>
>> dt-bindings should be set now, so if you're still happy to take the
>> series via riscv, that'd be great. i2c, spi & usb patches ended going
>> via the sub-system trees (and have been dropped from the series), in
>> case those generate warnings for you.
>
> Something went off the rails in email land and #0 and #2 didn't end up
> in my patch queue but the rest did. Luckily enough made it through that
> it didn't get lost, and lore's pretty great so this sort of thing isn't
> that big of a deal these days. That said, email is a bit of a black box
> so figured I'd give you a heads up.
Huh, interesting. I do check after sending that I can see the mails in my
other email's inbox & they're there. Guess good thing that I sent the follow up.
Thanks,
Conor.
>
>>
>> Thanks,
>> Conor.
>>>
>>> Changes from v6:
>>> - Dropped i2c patch, as its in i2c-next
>>> - Added ack on gpio, reviewed-by on rtc
>>> - Dropped child nodes from sysctrl binding entirely, added a link to
>>> the online documenation for the services the system controller can
>>> provide
>>> - Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's
>>> series
>>>
>>> Changes from v5:
>>> - reworded the descriptions in the pwm binding to (hopefully) add
>>> clarity
>>> - added -mask to the custom properties and made them 32 bit
>>> - renamed the i2c binding to corei2c, since it is not mpfs specific
>>> - removed the child nodes of the system controller in example/dts &
>>> will create them in the driver.
>>> @Rob, I assume keeping them documented is the correct thing to do?
>>> - removed the dependancy on the clock binding from the examples
>>> - reformatted rtc interrupts as per Rob's suggestion
>>>
>>> Changes from v4:
>>> - dont include icicle_kit_defconfig, accidentally added in v3
>>> - drop prescaler from mpfs-rtc & calculate the value instead
>>> - use corei2c as a fallback device for mpfs-i2c
>>> - drop spi dt-binding (on spi-next)
>>> commit 2da187304e556ac59cf2dacb323cc78ded988169
>>> - drop usb dt-binding (on usb-next)
>>>
>>> Changes from v3:
>>> - drop "mailbox: change mailbox-mpfs compatible string", already upstream:
>>> commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
>>> - fix copy paste error in microchip,mpfs-mailbox dt-binding
>>> - remove whitespace in syscontroller dt entry
>>>
>>> Changes from v2:
>>> - dropped plic int header & corresponding defines in dts{,i}
>>> - use $ref to drmode in mpfs-musb binding
>>> - split changes to dts{,i} again: functional changes to existing
>>> elements now are in a new patch
>>> - drop num-cs property in mpfs-spi binding
>>> - dont make the system controller a simple-mfd
>>> - move the separate bindings for rng/generic system services into the
>>> system controller binding
>>> - added an instance corei2c as i2c2 in the fabric dtsi
>>> - add version numbering to corepwm and corei2c compat string (-rtl-vN)
>>>
>>> Conor Dooley (11):
>>> dt-bindings: soc/microchip: update syscontroller compatibles
>>> dt-bindings: soc/microchip: add info about services to mpfs sysctrl
>>> dt-bindings: rtc: add bindings for microchip mpfs rtc
>>> dt-bindings: gpio: add bindings for microchip mpfs gpio
>>> dt-bindings: pwm: add microchip corepwm binding
>>> riscv: dts: microchip: use clk defines for icicle kit
>>> riscv: dts: microchip: add fpga fabric section to icicle kit
>>> riscv: dts: microchip: refactor icicle kit device tree
>>> riscv: dts: microchip: update peripherals in icicle kit device tree
>>> riscv: dts: microchip: add new peripherals to icicle kit device tree
>>> MAINTAINERS: update riscv/microchip entry
>>>
>>> .../bindings/gpio/microchip,mpfs-gpio.yaml | 79 ++++++
>>> ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +-
>>> .../bindings/pwm/microchip,corepwm.yaml | 81 ++++++
>>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 ++++
>>> .../microchip,mpfs-sys-controller.yaml | 40 +++
>>> ...icrochip,polarfire-soc-sys-controller.yaml | 35 ---
>>> MAINTAINERS | 2 +
>>> .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++
>>> .../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++--
>>> .../boot/dts/microchip/microchip-mpfs.dtsi | 254 ++++++++++++++----
>>> 10 files changed, 591 insertions(+), 104 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
>>> rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
>>> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
>>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>> create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
>>> delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
>>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>>>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 00/11] Update the Icicle Kit device tree
2022-03-10 7:35 ` Conor.Dooley
@ 2022-03-11 7:59 ` Zong Li
-1 siblings, 0 replies; 64+ messages in thread
From: Zong Li @ 2022-03-11 7:59 UTC (permalink / raw)
To: Conor Dooley
Cc: Palmer Dabbelt, Stephen Boyd, Lewis.Hanly, Daire.McNamara,
Ivan.Griffin, atishp, linus.walleij, brgl, Rob Herring,
jassisinghbrar, thierry.reding, u.kleine-koenig, Lee Jones,
a.zummo, alexandre.belloni, Paul Walmsley, Albert Ou,
Geert Uytterhoeven, Krzysztof Kozlowski, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org List, linux-pwm, linux-rtc,
linux-riscv
On Thu, Mar 10, 2022 at 3:35 PM <Conor.Dooley@microchip.com> wrote:
>
> On 10/03/2022 07:07, Palmer Dabbelt wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Wed, 23 Feb 2022 12:48:16 PST (-0800), mail@conchuod.ie wrote:
> >> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> >>> From: Conor Dooley <conor.dooley@microchip.com>
> >>>
> >>> This series updates the Microchip Icicle Kit device tree by adding a
> >>> host of peripherals, and some updates to the memory map. In addition,
> >>> the device tree has been split into a third part, which contains "soft"
> >>> peripherals that are in the fpga fabric.
> >>>
> >>> Several of the entries are for peripherals that have not get had their
> >>> drivers upstreamed, so in those cases the dt bindings are included where
> >>> appropriate in order to avoid the many "DT compatible string <x> appears
> >>> un-documented" errors.
> >>>
> >>> Depends on mpfs clock driver binding (on clk/next) to provide
> >>> dt-bindings/clock/microchip,mpfs-clock.h for the device tree
> >>> and on the other changes to the icicle/mpfs device tree from geert
> >>> that are already in linux/riscv/for-next.
> >
> > So that's causing this to not build, as I can't build without the
> > header. I went ahead and put these on top of that patch, resulting in
> >
> > * 48e8641c2bf0 - (HEAD -> riscv-microchip, palmer/riscv-microchip) MAINTAINERS: update riscv/microchip entry (2 minutes ago) <Conor Dooley>
> > * 528a5b1f2556 - riscv: dts: microchip: add new peripherals to icicle kit device tree (2 minutes ago) <Conor Dooley>
> > * 5b28df37d311 - riscv: dts: microchip: update peripherals in icicle kit device tree (2 minutes ago) <Conor Dooley>
> > * c5094f371008 - riscv: dts: microchip: refactor icicle kit device tree (2 minutes ago) <Conor Dooley>
> > * 72560c6559b8 - riscv: dts: microchip: add fpga fabric section to icicle kit (2 minutes ago) <Conor Dooley>
> > * 6546f920868e - riscv: dts: microchip: use clk defines for icicle kit (2 minutes ago) <Conor Dooley>
> > * df77f7735786 - dt-bindings: pwm: add microchip corepwm binding (2 minutes ago) <Conor Dooley>
> > * 735806d8a68e - dt-bindings: gpio: add bindings for microchip mpfs gpio (2 minutes ago) <Conor Dooley>
> > * 4cbcc0d7b397 - dt-bindings: rtc: add bindings for microchip mpfs rtc (2 minutes ago) <Conor Dooley>
> > * b435a1728c9f - dt-bindings: soc/microchip: add info about services to mpfs sysctrl (2 minutes ago) <Conor Dooley>
> > * 213556235526 - dt-bindings: soc/microchip: update syscontroller compatibles (2 minutes ago) <Conor Dooley>
> > * 2145bb687e3f - (clk/clk-microchip) dt-bindings: clk: microchip: Add Microchip PolarFire host binding (6 weeks ago) <Daire McNamara>
> > * e783362eb54c - (tag: v5.17-rc1) Linux 5.17-rc1 (7 weeks ago) <Linus Torvalds>
> >
> > sboyd: IIRC it's OK to consider clk-microchip as a stable branch? If
> > not I can just wait until you send your PR to Linus and send this later
> > in the merge window, no big deal on my end.
> >
> > I've put this on for-next. If that's a problem let me know and I'll
> > delay it.
> Great, thanks! Probably worth mentioning that I've deleted the dma node
> that Zong Li is modifying in his pdma patchset.
>
I guess I could re-sent the next version based on top of for-next, or
delay my patch set until the next tag. What is your perspective?
> >
> > Thanks!
> >
> >>>
> >>> Additionally, the interrupt-extended warnings on the plic/clint are
> >>> cleared by [1] & [2].
> >>>
> >>> [1] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/
> >>> [2] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/
> >>
> >> Hey Palmer,
> >>
> >> dt-bindings should be set now, so if you're still happy to take the
> >> series via riscv, that'd be great. i2c, spi & usb patches ended going
> >> via the sub-system trees (and have been dropped from the series), in
> >> case those generate warnings for you.
> >
> > Something went off the rails in email land and #0 and #2 didn't end up
> > in my patch queue but the rest did. Luckily enough made it through that
> > it didn't get lost, and lore's pretty great so this sort of thing isn't
> > that big of a deal these days. That said, email is a bit of a black box
> > so figured I'd give you a heads up.
>
> Huh, interesting. I do check after sending that I can see the mails in my
> other email's inbox & they're there. Guess good thing that I sent the follow up.
> Thanks,
> Conor.
>
> >
> >>
> >> Thanks,
> >> Conor.
> >>>
> >>> Changes from v6:
> >>> - Dropped i2c patch, as its in i2c-next
> >>> - Added ack on gpio, reviewed-by on rtc
> >>> - Dropped child nodes from sysctrl binding entirely, added a link to
> >>> the online documenation for the services the system controller can
> >>> provide
> >>> - Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's
> >>> series
> >>>
> >>> Changes from v5:
> >>> - reworded the descriptions in the pwm binding to (hopefully) add
> >>> clarity
> >>> - added -mask to the custom properties and made them 32 bit
> >>> - renamed the i2c binding to corei2c, since it is not mpfs specific
> >>> - removed the child nodes of the system controller in example/dts &
> >>> will create them in the driver.
> >>> @Rob, I assume keeping them documented is the correct thing to do?
> >>> - removed the dependancy on the clock binding from the examples
> >>> - reformatted rtc interrupts as per Rob's suggestion
> >>>
> >>> Changes from v4:
> >>> - dont include icicle_kit_defconfig, accidentally added in v3
> >>> - drop prescaler from mpfs-rtc & calculate the value instead
> >>> - use corei2c as a fallback device for mpfs-i2c
> >>> - drop spi dt-binding (on spi-next)
> >>> commit 2da187304e556ac59cf2dacb323cc78ded988169
> >>> - drop usb dt-binding (on usb-next)
> >>>
> >>> Changes from v3:
> >>> - drop "mailbox: change mailbox-mpfs compatible string", already upstream:
> >>> commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
> >>> - fix copy paste error in microchip,mpfs-mailbox dt-binding
> >>> - remove whitespace in syscontroller dt entry
> >>>
> >>> Changes from v2:
> >>> - dropped plic int header & corresponding defines in dts{,i}
> >>> - use $ref to drmode in mpfs-musb binding
> >>> - split changes to dts{,i} again: functional changes to existing
> >>> elements now are in a new patch
> >>> - drop num-cs property in mpfs-spi binding
> >>> - dont make the system controller a simple-mfd
> >>> - move the separate bindings for rng/generic system services into the
> >>> system controller binding
> >>> - added an instance corei2c as i2c2 in the fabric dtsi
> >>> - add version numbering to corepwm and corei2c compat string (-rtl-vN)
> >>>
> >>> Conor Dooley (11):
> >>> dt-bindings: soc/microchip: update syscontroller compatibles
> >>> dt-bindings: soc/microchip: add info about services to mpfs sysctrl
> >>> dt-bindings: rtc: add bindings for microchip mpfs rtc
> >>> dt-bindings: gpio: add bindings for microchip mpfs gpio
> >>> dt-bindings: pwm: add microchip corepwm binding
> >>> riscv: dts: microchip: use clk defines for icicle kit
> >>> riscv: dts: microchip: add fpga fabric section to icicle kit
> >>> riscv: dts: microchip: refactor icicle kit device tree
> >>> riscv: dts: microchip: update peripherals in icicle kit device tree
> >>> riscv: dts: microchip: add new peripherals to icicle kit device tree
> >>> MAINTAINERS: update riscv/microchip entry
> >>>
> >>> .../bindings/gpio/microchip,mpfs-gpio.yaml | 79 ++++++
> >>> ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +-
> >>> .../bindings/pwm/microchip,corepwm.yaml | 81 ++++++
> >>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 ++++
> >>> .../microchip,mpfs-sys-controller.yaml | 40 +++
> >>> ...icrochip,polarfire-soc-sys-controller.yaml | 35 ---
> >>> MAINTAINERS | 2 +
> >>> .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++
> >>> .../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++--
> >>> .../boot/dts/microchip/microchip-mpfs.dtsi | 254 ++++++++++++++----
> >>> 10 files changed, 591 insertions(+), 104 deletions(-)
> >>> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
> >>> rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
> >>> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
> >>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> >>> create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> >>> delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> >>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
> >>>
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 00/11] Update the Icicle Kit device tree
@ 2022-03-11 7:59 ` Zong Li
0 siblings, 0 replies; 64+ messages in thread
From: Zong Li @ 2022-03-11 7:59 UTC (permalink / raw)
To: Conor Dooley
Cc: Palmer Dabbelt, Stephen Boyd, Lewis.Hanly, Daire.McNamara,
Ivan.Griffin, atishp, linus.walleij, brgl, Rob Herring,
jassisinghbrar, thierry.reding, u.kleine-koenig, Lee Jones,
a.zummo, alexandre.belloni, Paul Walmsley, Albert Ou,
Geert Uytterhoeven, Krzysztof Kozlowski, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org List, linux-pwm, linux-rtc,
linux-riscv
On Thu, Mar 10, 2022 at 3:35 PM <Conor.Dooley@microchip.com> wrote:
>
> On 10/03/2022 07:07, Palmer Dabbelt wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Wed, 23 Feb 2022 12:48:16 PST (-0800), mail@conchuod.ie wrote:
> >> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
> >>> From: Conor Dooley <conor.dooley@microchip.com>
> >>>
> >>> This series updates the Microchip Icicle Kit device tree by adding a
> >>> host of peripherals, and some updates to the memory map. In addition,
> >>> the device tree has been split into a third part, which contains "soft"
> >>> peripherals that are in the fpga fabric.
> >>>
> >>> Several of the entries are for peripherals that have not get had their
> >>> drivers upstreamed, so in those cases the dt bindings are included where
> >>> appropriate in order to avoid the many "DT compatible string <x> appears
> >>> un-documented" errors.
> >>>
> >>> Depends on mpfs clock driver binding (on clk/next) to provide
> >>> dt-bindings/clock/microchip,mpfs-clock.h for the device tree
> >>> and on the other changes to the icicle/mpfs device tree from geert
> >>> that are already in linux/riscv/for-next.
> >
> > So that's causing this to not build, as I can't build without the
> > header. I went ahead and put these on top of that patch, resulting in
> >
> > * 48e8641c2bf0 - (HEAD -> riscv-microchip, palmer/riscv-microchip) MAINTAINERS: update riscv/microchip entry (2 minutes ago) <Conor Dooley>
> > * 528a5b1f2556 - riscv: dts: microchip: add new peripherals to icicle kit device tree (2 minutes ago) <Conor Dooley>
> > * 5b28df37d311 - riscv: dts: microchip: update peripherals in icicle kit device tree (2 minutes ago) <Conor Dooley>
> > * c5094f371008 - riscv: dts: microchip: refactor icicle kit device tree (2 minutes ago) <Conor Dooley>
> > * 72560c6559b8 - riscv: dts: microchip: add fpga fabric section to icicle kit (2 minutes ago) <Conor Dooley>
> > * 6546f920868e - riscv: dts: microchip: use clk defines for icicle kit (2 minutes ago) <Conor Dooley>
> > * df77f7735786 - dt-bindings: pwm: add microchip corepwm binding (2 minutes ago) <Conor Dooley>
> > * 735806d8a68e - dt-bindings: gpio: add bindings for microchip mpfs gpio (2 minutes ago) <Conor Dooley>
> > * 4cbcc0d7b397 - dt-bindings: rtc: add bindings for microchip mpfs rtc (2 minutes ago) <Conor Dooley>
> > * b435a1728c9f - dt-bindings: soc/microchip: add info about services to mpfs sysctrl (2 minutes ago) <Conor Dooley>
> > * 213556235526 - dt-bindings: soc/microchip: update syscontroller compatibles (2 minutes ago) <Conor Dooley>
> > * 2145bb687e3f - (clk/clk-microchip) dt-bindings: clk: microchip: Add Microchip PolarFire host binding (6 weeks ago) <Daire McNamara>
> > * e783362eb54c - (tag: v5.17-rc1) Linux 5.17-rc1 (7 weeks ago) <Linus Torvalds>
> >
> > sboyd: IIRC it's OK to consider clk-microchip as a stable branch? If
> > not I can just wait until you send your PR to Linus and send this later
> > in the merge window, no big deal on my end.
> >
> > I've put this on for-next. If that's a problem let me know and I'll
> > delay it.
> Great, thanks! Probably worth mentioning that I've deleted the dma node
> that Zong Li is modifying in his pdma patchset.
>
I guess I could re-sent the next version based on top of for-next, or
delay my patch set until the next tag. What is your perspective?
> >
> > Thanks!
> >
> >>>
> >>> Additionally, the interrupt-extended warnings on the plic/clint are
> >>> cleared by [1] & [2].
> >>>
> >>> [1] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/
> >>> [2] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/
> >>
> >> Hey Palmer,
> >>
> >> dt-bindings should be set now, so if you're still happy to take the
> >> series via riscv, that'd be great. i2c, spi & usb patches ended going
> >> via the sub-system trees (and have been dropped from the series), in
> >> case those generate warnings for you.
> >
> > Something went off the rails in email land and #0 and #2 didn't end up
> > in my patch queue but the rest did. Luckily enough made it through that
> > it didn't get lost, and lore's pretty great so this sort of thing isn't
> > that big of a deal these days. That said, email is a bit of a black box
> > so figured I'd give you a heads up.
>
> Huh, interesting. I do check after sending that I can see the mails in my
> other email's inbox & they're there. Guess good thing that I sent the follow up.
> Thanks,
> Conor.
>
> >
> >>
> >> Thanks,
> >> Conor.
> >>>
> >>> Changes from v6:
> >>> - Dropped i2c patch, as its in i2c-next
> >>> - Added ack on gpio, reviewed-by on rtc
> >>> - Dropped child nodes from sysctrl binding entirely, added a link to
> >>> the online documenation for the services the system controller can
> >>> provide
> >>> - Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's
> >>> series
> >>>
> >>> Changes from v5:
> >>> - reworded the descriptions in the pwm binding to (hopefully) add
> >>> clarity
> >>> - added -mask to the custom properties and made them 32 bit
> >>> - renamed the i2c binding to corei2c, since it is not mpfs specific
> >>> - removed the child nodes of the system controller in example/dts &
> >>> will create them in the driver.
> >>> @Rob, I assume keeping them documented is the correct thing to do?
> >>> - removed the dependancy on the clock binding from the examples
> >>> - reformatted rtc interrupts as per Rob's suggestion
> >>>
> >>> Changes from v4:
> >>> - dont include icicle_kit_defconfig, accidentally added in v3
> >>> - drop prescaler from mpfs-rtc & calculate the value instead
> >>> - use corei2c as a fallback device for mpfs-i2c
> >>> - drop spi dt-binding (on spi-next)
> >>> commit 2da187304e556ac59cf2dacb323cc78ded988169
> >>> - drop usb dt-binding (on usb-next)
> >>>
> >>> Changes from v3:
> >>> - drop "mailbox: change mailbox-mpfs compatible string", already upstream:
> >>> commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
> >>> - fix copy paste error in microchip,mpfs-mailbox dt-binding
> >>> - remove whitespace in syscontroller dt entry
> >>>
> >>> Changes from v2:
> >>> - dropped plic int header & corresponding defines in dts{,i}
> >>> - use $ref to drmode in mpfs-musb binding
> >>> - split changes to dts{,i} again: functional changes to existing
> >>> elements now are in a new patch
> >>> - drop num-cs property in mpfs-spi binding
> >>> - dont make the system controller a simple-mfd
> >>> - move the separate bindings for rng/generic system services into the
> >>> system controller binding
> >>> - added an instance corei2c as i2c2 in the fabric dtsi
> >>> - add version numbering to corepwm and corei2c compat string (-rtl-vN)
> >>>
> >>> Conor Dooley (11):
> >>> dt-bindings: soc/microchip: update syscontroller compatibles
> >>> dt-bindings: soc/microchip: add info about services to mpfs sysctrl
> >>> dt-bindings: rtc: add bindings for microchip mpfs rtc
> >>> dt-bindings: gpio: add bindings for microchip mpfs gpio
> >>> dt-bindings: pwm: add microchip corepwm binding
> >>> riscv: dts: microchip: use clk defines for icicle kit
> >>> riscv: dts: microchip: add fpga fabric section to icicle kit
> >>> riscv: dts: microchip: refactor icicle kit device tree
> >>> riscv: dts: microchip: update peripherals in icicle kit device tree
> >>> riscv: dts: microchip: add new peripherals to icicle kit device tree
> >>> MAINTAINERS: update riscv/microchip entry
> >>>
> >>> .../bindings/gpio/microchip,mpfs-gpio.yaml | 79 ++++++
> >>> ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +-
> >>> .../bindings/pwm/microchip,corepwm.yaml | 81 ++++++
> >>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 ++++
> >>> .../microchip,mpfs-sys-controller.yaml | 40 +++
> >>> ...icrochip,polarfire-soc-sys-controller.yaml | 35 ---
> >>> MAINTAINERS | 2 +
> >>> .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++
> >>> .../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++--
> >>> .../boot/dts/microchip/microchip-mpfs.dtsi | 254 ++++++++++++++----
> >>> 10 files changed, 591 insertions(+), 104 deletions(-)
> >>> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
> >>> rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
> >>> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
> >>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> >>> create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> >>> delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> >>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
> >>>
>
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 00/11] Update the Icicle Kit device tree
2022-03-11 7:59 ` Zong Li
@ 2022-03-11 19:56 ` Conor Dooley
-1 siblings, 0 replies; 64+ messages in thread
From: Conor Dooley @ 2022-03-11 19:56 UTC (permalink / raw)
To: Zong Li, Palmer Dabbelt
Cc: Stephen Boyd, Conor Dooley, Lewis.Hanly, Daire.McNamara,
Ivan.Griffin, atishp, linus.walleij, brgl, Rob Herring,
jassisinghbrar, thierry.reding, u.kleine-koenig, Lee Jones,
a.zummo, alexandre.belloni, Paul Walmsley, Albert Ou,
Geert Uytterhoeven, Krzysztof Kozlowski, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org List, linux-pwm, linux-rtc,
linux-riscv
On 11/03/2022 07:59, Zong Li wrote:
> On Thu, Mar 10, 2022 at 3:35 PM <Conor.Dooley@microchip.com> wrote:
>>
>> On 10/03/2022 07:07, Palmer Dabbelt wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Wed, 23 Feb 2022 12:48:16 PST (-0800), mail@conchuod.ie wrote:
>>>> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>
>>>>> This series updates the Microchip Icicle Kit device tree by adding a
>>>>> host of peripherals, and some updates to the memory map. In addition,
>>>>> the device tree has been split into a third part, which contains "soft"
>>>>> peripherals that are in the fpga fabric.
>>>>>
>>>>> Several of the entries are for peripherals that have not get had their
>>>>> drivers upstreamed, so in those cases the dt bindings are included where
>>>>> appropriate in order to avoid the many "DT compatible string <x> appears
>>>>> un-documented" errors.
>>>>>
>>>>> Depends on mpfs clock driver binding (on clk/next) to provide
>>>>> dt-bindings/clock/microchip,mpfs-clock.h for the device tree
>>>>> and on the other changes to the icicle/mpfs device tree from geert
>>>>> that are already in linux/riscv/for-next.
>>>
>>> So that's causing this to not build, as I can't build without the
>>> header. I went ahead and put these on top of that patch, resulting in
>>>
>>> * 48e8641c2bf0 - (HEAD -> riscv-microchip, palmer/riscv-microchip) MAINTAINERS: update riscv/microchip entry (2 minutes ago) <Conor Dooley>
>>> * 528a5b1f2556 - riscv: dts: microchip: add new peripherals to icicle kit device tree (2 minutes ago) <Conor Dooley>
>>> * 5b28df37d311 - riscv: dts: microchip: update peripherals in icicle kit device tree (2 minutes ago) <Conor Dooley>
>>> * c5094f371008 - riscv: dts: microchip: refactor icicle kit device tree (2 minutes ago) <Conor Dooley>
>>> * 72560c6559b8 - riscv: dts: microchip: add fpga fabric section to icicle kit (2 minutes ago) <Conor Dooley>
>>> * 6546f920868e - riscv: dts: microchip: use clk defines for icicle kit (2 minutes ago) <Conor Dooley>
>>> * df77f7735786 - dt-bindings: pwm: add microchip corepwm binding (2 minutes ago) <Conor Dooley>
>>> * 735806d8a68e - dt-bindings: gpio: add bindings for microchip mpfs gpio (2 minutes ago) <Conor Dooley>
>>> * 4cbcc0d7b397 - dt-bindings: rtc: add bindings for microchip mpfs rtc (2 minutes ago) <Conor Dooley>
>>> * b435a1728c9f - dt-bindings: soc/microchip: add info about services to mpfs sysctrl (2 minutes ago) <Conor Dooley>
>>> * 213556235526 - dt-bindings: soc/microchip: update syscontroller compatibles (2 minutes ago) <Conor Dooley>
>>> * 2145bb687e3f - (clk/clk-microchip) dt-bindings: clk: microchip: Add Microchip PolarFire host binding (6 weeks ago) <Daire McNamara>
>>> * e783362eb54c - (tag: v5.17-rc1) Linux 5.17-rc1 (7 weeks ago) <Linus Torvalds>
>>>
>>> sboyd: IIRC it's OK to consider clk-microchip as a stable branch? If
>>> not I can just wait until you send your PR to Linus and send this later
>>> in the merge window, no big deal on my end.
>>>
>>> I've put this on for-next. If that's a problem let me know and I'll
>>> delay it.
>> Great, thanks! Probably worth mentioning that I've deleted the dma node
>> that Zong Li is modifying in his pdma patchset.
>>
>
> I guess I could re-sent the next version based on top of for-next, or
> delay my patch set until the next tag. What is your perspective?
I'll be honest and say that I have no idea what one is supposed to do here.
Palmer?
>
>>>
>>> Thanks!
>>>
>>>>>
>>>>> Additionally, the interrupt-extended warnings on the plic/clint are
>>>>> cleared by [1] & [2].
>>>>>
>>>>> [1] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/
>>>>> [2] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/
>>>>
>>>> Hey Palmer,
>>>>
>>>> dt-bindings should be set now, so if you're still happy to take the
>>>> series via riscv, that'd be great. i2c, spi & usb patches ended going
>>>> via the sub-system trees (and have been dropped from the series), in
>>>> case those generate warnings for you.
>>>
>>> Something went off the rails in email land and #0 and #2 didn't end up
>>> in my patch queue but the rest did. Luckily enough made it through that
>>> it didn't get lost, and lore's pretty great so this sort of thing isn't
>>> that big of a deal these days. That said, email is a bit of a black box
>>> so figured I'd give you a heads up.
>>
>> Huh, interesting. I do check after sending that I can see the mails in my
>> other email's inbox & they're there. Guess good thing that I sent the follow up.
>> Thanks,
>> Conor.
>>
>>>
>>>>
>>>> Thanks,
>>>> Conor.
>>>>>
>>>>> Changes from v6:
>>>>> - Dropped i2c patch, as its in i2c-next
>>>>> - Added ack on gpio, reviewed-by on rtc
>>>>> - Dropped child nodes from sysctrl binding entirely, added a link to
>>>>> the online documenation for the services the system controller can
>>>>> provide
>>>>> - Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's
>>>>> series
>>>>>
>>>>> Changes from v5:
>>>>> - reworded the descriptions in the pwm binding to (hopefully) add
>>>>> clarity
>>>>> - added -mask to the custom properties and made them 32 bit
>>>>> - renamed the i2c binding to corei2c, since it is not mpfs specific
>>>>> - removed the child nodes of the system controller in example/dts &
>>>>> will create them in the driver.
>>>>> @Rob, I assume keeping them documented is the correct thing to do?
>>>>> - removed the dependancy on the clock binding from the examples
>>>>> - reformatted rtc interrupts as per Rob's suggestion
>>>>>
>>>>> Changes from v4:
>>>>> - dont include icicle_kit_defconfig, accidentally added in v3
>>>>> - drop prescaler from mpfs-rtc & calculate the value instead
>>>>> - use corei2c as a fallback device for mpfs-i2c
>>>>> - drop spi dt-binding (on spi-next)
>>>>> commit 2da187304e556ac59cf2dacb323cc78ded988169
>>>>> - drop usb dt-binding (on usb-next)
>>>>>
>>>>> Changes from v3:
>>>>> - drop "mailbox: change mailbox-mpfs compatible string", already upstream:
>>>>> commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
>>>>> - fix copy paste error in microchip,mpfs-mailbox dt-binding
>>>>> - remove whitespace in syscontroller dt entry
>>>>>
>>>>> Changes from v2:
>>>>> - dropped plic int header & corresponding defines in dts{,i}
>>>>> - use $ref to drmode in mpfs-musb binding
>>>>> - split changes to dts{,i} again: functional changes to existing
>>>>> elements now are in a new patch
>>>>> - drop num-cs property in mpfs-spi binding
>>>>> - dont make the system controller a simple-mfd
>>>>> - move the separate bindings for rng/generic system services into the
>>>>> system controller binding
>>>>> - added an instance corei2c as i2c2 in the fabric dtsi
>>>>> - add version numbering to corepwm and corei2c compat string (-rtl-vN)
>>>>>
>>>>> Conor Dooley (11):
>>>>> dt-bindings: soc/microchip: update syscontroller compatibles
>>>>> dt-bindings: soc/microchip: add info about services to mpfs sysctrl
>>>>> dt-bindings: rtc: add bindings for microchip mpfs rtc
>>>>> dt-bindings: gpio: add bindings for microchip mpfs gpio
>>>>> dt-bindings: pwm: add microchip corepwm binding
>>>>> riscv: dts: microchip: use clk defines for icicle kit
>>>>> riscv: dts: microchip: add fpga fabric section to icicle kit
>>>>> riscv: dts: microchip: refactor icicle kit device tree
>>>>> riscv: dts: microchip: update peripherals in icicle kit device tree
>>>>> riscv: dts: microchip: add new peripherals to icicle kit device tree
>>>>> MAINTAINERS: update riscv/microchip entry
>>>>>
>>>>> .../bindings/gpio/microchip,mpfs-gpio.yaml | 79 ++++++
>>>>> ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +-
>>>>> .../bindings/pwm/microchip,corepwm.yaml | 81 ++++++
>>>>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 ++++
>>>>> .../microchip,mpfs-sys-controller.yaml | 40 +++
>>>>> ...icrochip,polarfire-soc-sys-controller.yaml | 35 ---
>>>>> MAINTAINERS | 2 +
>>>>> .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++
>>>>> .../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++--
>>>>> .../boot/dts/microchip/microchip-mpfs.dtsi | 254 ++++++++++++++----
>>>>> 10 files changed, 591 insertions(+), 104 deletions(-)
>>>>> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
>>>>> rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
>>>>> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
>>>>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>>>> create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
>>>>> delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
>>>>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>>>>>
>>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 00/11] Update the Icicle Kit device tree
@ 2022-03-11 19:56 ` Conor Dooley
0 siblings, 0 replies; 64+ messages in thread
From: Conor Dooley @ 2022-03-11 19:56 UTC (permalink / raw)
To: Zong Li, Palmer Dabbelt
Cc: Stephen Boyd, Conor Dooley, Lewis.Hanly, Daire.McNamara,
Ivan.Griffin, atishp, linus.walleij, brgl, Rob Herring,
jassisinghbrar, thierry.reding, u.kleine-koenig, Lee Jones,
a.zummo, alexandre.belloni, Paul Walmsley, Albert Ou,
Geert Uytterhoeven, Krzysztof Kozlowski, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org List, linux-pwm, linux-rtc,
linux-riscv
On 11/03/2022 07:59, Zong Li wrote:
> On Thu, Mar 10, 2022 at 3:35 PM <Conor.Dooley@microchip.com> wrote:
>>
>> On 10/03/2022 07:07, Palmer Dabbelt wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Wed, 23 Feb 2022 12:48:16 PST (-0800), mail@conchuod.ie wrote:
>>>> On 14/02/2022 13:58, conor.dooley@microchip.com wrote:
>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>
>>>>> This series updates the Microchip Icicle Kit device tree by adding a
>>>>> host of peripherals, and some updates to the memory map. In addition,
>>>>> the device tree has been split into a third part, which contains "soft"
>>>>> peripherals that are in the fpga fabric.
>>>>>
>>>>> Several of the entries are for peripherals that have not get had their
>>>>> drivers upstreamed, so in those cases the dt bindings are included where
>>>>> appropriate in order to avoid the many "DT compatible string <x> appears
>>>>> un-documented" errors.
>>>>>
>>>>> Depends on mpfs clock driver binding (on clk/next) to provide
>>>>> dt-bindings/clock/microchip,mpfs-clock.h for the device tree
>>>>> and on the other changes to the icicle/mpfs device tree from geert
>>>>> that are already in linux/riscv/for-next.
>>>
>>> So that's causing this to not build, as I can't build without the
>>> header. I went ahead and put these on top of that patch, resulting in
>>>
>>> * 48e8641c2bf0 - (HEAD -> riscv-microchip, palmer/riscv-microchip) MAINTAINERS: update riscv/microchip entry (2 minutes ago) <Conor Dooley>
>>> * 528a5b1f2556 - riscv: dts: microchip: add new peripherals to icicle kit device tree (2 minutes ago) <Conor Dooley>
>>> * 5b28df37d311 - riscv: dts: microchip: update peripherals in icicle kit device tree (2 minutes ago) <Conor Dooley>
>>> * c5094f371008 - riscv: dts: microchip: refactor icicle kit device tree (2 minutes ago) <Conor Dooley>
>>> * 72560c6559b8 - riscv: dts: microchip: add fpga fabric section to icicle kit (2 minutes ago) <Conor Dooley>
>>> * 6546f920868e - riscv: dts: microchip: use clk defines for icicle kit (2 minutes ago) <Conor Dooley>
>>> * df77f7735786 - dt-bindings: pwm: add microchip corepwm binding (2 minutes ago) <Conor Dooley>
>>> * 735806d8a68e - dt-bindings: gpio: add bindings for microchip mpfs gpio (2 minutes ago) <Conor Dooley>
>>> * 4cbcc0d7b397 - dt-bindings: rtc: add bindings for microchip mpfs rtc (2 minutes ago) <Conor Dooley>
>>> * b435a1728c9f - dt-bindings: soc/microchip: add info about services to mpfs sysctrl (2 minutes ago) <Conor Dooley>
>>> * 213556235526 - dt-bindings: soc/microchip: update syscontroller compatibles (2 minutes ago) <Conor Dooley>
>>> * 2145bb687e3f - (clk/clk-microchip) dt-bindings: clk: microchip: Add Microchip PolarFire host binding (6 weeks ago) <Daire McNamara>
>>> * e783362eb54c - (tag: v5.17-rc1) Linux 5.17-rc1 (7 weeks ago) <Linus Torvalds>
>>>
>>> sboyd: IIRC it's OK to consider clk-microchip as a stable branch? If
>>> not I can just wait until you send your PR to Linus and send this later
>>> in the merge window, no big deal on my end.
>>>
>>> I've put this on for-next. If that's a problem let me know and I'll
>>> delay it.
>> Great, thanks! Probably worth mentioning that I've deleted the dma node
>> that Zong Li is modifying in his pdma patchset.
>>
>
> I guess I could re-sent the next version based on top of for-next, or
> delay my patch set until the next tag. What is your perspective?
I'll be honest and say that I have no idea what one is supposed to do here.
Palmer?
>
>>>
>>> Thanks!
>>>
>>>>>
>>>>> Additionally, the interrupt-extended warnings on the plic/clint are
>>>>> cleared by [1] & [2].
>>>>>
>>>>> [1] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/
>>>>> [2] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/
>>>>
>>>> Hey Palmer,
>>>>
>>>> dt-bindings should be set now, so if you're still happy to take the
>>>> series via riscv, that'd be great. i2c, spi & usb patches ended going
>>>> via the sub-system trees (and have been dropped from the series), in
>>>> case those generate warnings for you.
>>>
>>> Something went off the rails in email land and #0 and #2 didn't end up
>>> in my patch queue but the rest did. Luckily enough made it through that
>>> it didn't get lost, and lore's pretty great so this sort of thing isn't
>>> that big of a deal these days. That said, email is a bit of a black box
>>> so figured I'd give you a heads up.
>>
>> Huh, interesting. I do check after sending that I can see the mails in my
>> other email's inbox & they're there. Guess good thing that I sent the follow up.
>> Thanks,
>> Conor.
>>
>>>
>>>>
>>>> Thanks,
>>>> Conor.
>>>>>
>>>>> Changes from v6:
>>>>> - Dropped i2c patch, as its in i2c-next
>>>>> - Added ack on gpio, reviewed-by on rtc
>>>>> - Dropped child nodes from sysctrl binding entirely, added a link to
>>>>> the online documenation for the services the system controller can
>>>>> provide
>>>>> - Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's
>>>>> series
>>>>>
>>>>> Changes from v5:
>>>>> - reworded the descriptions in the pwm binding to (hopefully) add
>>>>> clarity
>>>>> - added -mask to the custom properties and made them 32 bit
>>>>> - renamed the i2c binding to corei2c, since it is not mpfs specific
>>>>> - removed the child nodes of the system controller in example/dts &
>>>>> will create them in the driver.
>>>>> @Rob, I assume keeping them documented is the correct thing to do?
>>>>> - removed the dependancy on the clock binding from the examples
>>>>> - reformatted rtc interrupts as per Rob's suggestion
>>>>>
>>>>> Changes from v4:
>>>>> - dont include icicle_kit_defconfig, accidentally added in v3
>>>>> - drop prescaler from mpfs-rtc & calculate the value instead
>>>>> - use corei2c as a fallback device for mpfs-i2c
>>>>> - drop spi dt-binding (on spi-next)
>>>>> commit 2da187304e556ac59cf2dacb323cc78ded988169
>>>>> - drop usb dt-binding (on usb-next)
>>>>>
>>>>> Changes from v3:
>>>>> - drop "mailbox: change mailbox-mpfs compatible string", already upstream:
>>>>> commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string")
>>>>> - fix copy paste error in microchip,mpfs-mailbox dt-binding
>>>>> - remove whitespace in syscontroller dt entry
>>>>>
>>>>> Changes from v2:
>>>>> - dropped plic int header & corresponding defines in dts{,i}
>>>>> - use $ref to drmode in mpfs-musb binding
>>>>> - split changes to dts{,i} again: functional changes to existing
>>>>> elements now are in a new patch
>>>>> - drop num-cs property in mpfs-spi binding
>>>>> - dont make the system controller a simple-mfd
>>>>> - move the separate bindings for rng/generic system services into the
>>>>> system controller binding
>>>>> - added an instance corei2c as i2c2 in the fabric dtsi
>>>>> - add version numbering to corepwm and corei2c compat string (-rtl-vN)
>>>>>
>>>>> Conor Dooley (11):
>>>>> dt-bindings: soc/microchip: update syscontroller compatibles
>>>>> dt-bindings: soc/microchip: add info about services to mpfs sysctrl
>>>>> dt-bindings: rtc: add bindings for microchip mpfs rtc
>>>>> dt-bindings: gpio: add bindings for microchip mpfs gpio
>>>>> dt-bindings: pwm: add microchip corepwm binding
>>>>> riscv: dts: microchip: use clk defines for icicle kit
>>>>> riscv: dts: microchip: add fpga fabric section to icicle kit
>>>>> riscv: dts: microchip: refactor icicle kit device tree
>>>>> riscv: dts: microchip: update peripherals in icicle kit device tree
>>>>> riscv: dts: microchip: add new peripherals to icicle kit device tree
>>>>> MAINTAINERS: update riscv/microchip entry
>>>>>
>>>>> .../bindings/gpio/microchip,mpfs-gpio.yaml | 79 ++++++
>>>>> ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +-
>>>>> .../bindings/pwm/microchip,corepwm.yaml | 81 ++++++
>>>>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 ++++
>>>>> .../microchip,mpfs-sys-controller.yaml | 40 +++
>>>>> ...icrochip,polarfire-soc-sys-controller.yaml | 35 ---
>>>>> MAINTAINERS | 2 +
>>>>> .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++
>>>>> .../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++--
>>>>> .../boot/dts/microchip/microchip-mpfs.dtsi | 254 ++++++++++++++----
>>>>> 10 files changed, 591 insertions(+), 104 deletions(-)
>>>>> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
>>>>> rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
>>>>> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
>>>>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>>>>> create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
>>>>> delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
>>>>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>>>>>
>>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 00/11] Update the Icicle Kit device tree
2022-03-10 7:07 ` Palmer Dabbelt
@ 2022-03-16 6:51 ` Uwe Kleine-König
-1 siblings, 0 replies; 64+ messages in thread
From: Uwe Kleine-König @ 2022-03-16 6:51 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: mail, sboyd, lewis.hanly, daire.mcnamara, ivan.griffin,
Atish Patra, conor.dooley, linus.walleij, brgl, robh+dt,
jassisinghbrar, thierry.reding, lee.jones, a.zummo,
alexandre.belloni, Paul Walmsley, aou, geert,
krzysztof.kozlowski, linux-gpio, devicetree, linux-kernel,
linux-pwm, linux-rtc, linux-riscv
[-- Attachment #1: Type: text/plain, Size: 1204 bytes --]
On Wed, Mar 09, 2022 at 11:07:03PM -0800, Palmer Dabbelt wrote:
> On Wed, 23 Feb 2022 12:48:16 PST (-0800), mail@conchuod.ie wrote:
> > dt-bindings should be set now, so if you're still happy to take the
> > series via riscv, that'd be great. i2c, spi & usb patches ended going
> > via the sub-system trees (and have been dropped from the series), in
> > case those generate warnings for you.
>
> Something went off the rails in email land and #0 and #2 didn't end up in my
> patch queue but the rest did. Luckily enough made it through that it didn't
> get lost, and lore's pretty great so this sort of thing isn't that big of a
> deal these days. That said, email is a bit of a black box so figured I'd
> give you a heads up.
One of the patches in next now is
df77f7735786ece2fcd8875b036a511ffcadfab6. It would be great if you could
fix your patch application setup to not mangle names. Here it's
Acked-by: Uwe Kleine-K=F6nig <u.kleine-koenig@pengutronix.de>
where my ö was recorded as =F6. :-\
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v7 00/11] Update the Icicle Kit device tree
@ 2022-03-16 6:51 ` Uwe Kleine-König
0 siblings, 0 replies; 64+ messages in thread
From: Uwe Kleine-König @ 2022-03-16 6:51 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: mail, sboyd, lewis.hanly, daire.mcnamara, ivan.griffin,
Atish Patra, conor.dooley, linus.walleij, brgl, robh+dt,
jassisinghbrar, thierry.reding, lee.jones, a.zummo,
alexandre.belloni, Paul Walmsley, aou, geert,
krzysztof.kozlowski, linux-gpio, devicetree, linux-kernel,
linux-pwm, linux-rtc, linux-riscv
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On Wed, Mar 09, 2022 at 11:07:03PM -0800, Palmer Dabbelt wrote:
> On Wed, 23 Feb 2022 12:48:16 PST (-0800), mail@conchuod.ie wrote:
> > dt-bindings should be set now, so if you're still happy to take the
> > series via riscv, that'd be great. i2c, spi & usb patches ended going
> > via the sub-system trees (and have been dropped from the series), in
> > case those generate warnings for you.
>
> Something went off the rails in email land and #0 and #2 didn't end up in my
> patch queue but the rest did. Luckily enough made it through that it didn't
> get lost, and lore's pretty great so this sort of thing isn't that big of a
> deal these days. That said, email is a bit of a black box so figured I'd
> give you a heads up.
One of the patches in next now is
df77f7735786ece2fcd8875b036a511ffcadfab6. It would be great if you could
fix your patch application setup to not mangle names. Here it's
Acked-by: Uwe Kleine-K=F6nig <u.kleine-koenig@pengutronix.de>
where my ö was recorded as =F6. :-\
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 64+ messages in thread
end of thread, other threads:[~2022-03-16 6:52 UTC | newest]
Thread overview: 64+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-14 13:58 [PATCH v7 00/11] Update the Icicle Kit device tree conor.dooley
2022-02-14 13:58 ` conor.dooley
2022-02-14 13:58 ` [PATCH v7 01/11] dt-bindings: soc/microchip: update syscontroller compatibles conor.dooley
2022-02-14 13:58 ` conor.dooley
2022-02-14 13:58 ` [PATCH v7 02/11] dt-bindings: soc/microchip: add info about services to mpfs sysctrl conor.dooley
2022-02-14 13:58 ` conor.dooley
2022-02-21 7:40 ` Conor.Dooley
2022-02-21 7:40 ` Conor.Dooley
2022-02-22 21:39 ` Rob Herring
2022-02-22 21:39 ` Rob Herring
2022-02-14 13:58 ` [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc conor.dooley
2022-02-14 13:58 ` conor.dooley
2022-02-23 7:41 ` Conor.Dooley
2022-02-23 7:41 ` Conor.Dooley
2022-02-23 15:18 ` Alexandre Belloni
2022-02-23 15:18 ` Alexandre Belloni
2022-02-23 15:25 ` Conor.Dooley
2022-02-23 15:25 ` Conor.Dooley
2022-02-23 20:20 ` Alexandre Belloni
2022-02-23 20:20 ` Alexandre Belloni
2022-02-23 20:26 ` Conor Dooley
2022-02-23 20:26 ` Conor Dooley
2022-02-14 13:58 ` [PATCH v7 04/11] dt-bindings: gpio: add bindings for microchip mpfs gpio conor.dooley
2022-02-14 13:58 ` conor.dooley
2022-02-14 13:58 ` [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding conor.dooley
2022-02-14 13:58 ` conor.dooley
2022-02-21 7:55 ` Conor.Dooley
2022-02-21 7:55 ` Conor.Dooley
2022-02-23 6:20 ` Uwe Kleine-König
2022-02-23 6:20 ` Uwe Kleine-König
2022-02-23 7:12 ` Krzysztof Kozlowski
2022-02-23 7:12 ` Krzysztof Kozlowski
2022-02-23 8:20 ` Uwe Kleine-König
2022-02-23 8:20 ` Uwe Kleine-König
2022-02-23 8:55 ` conor.dooley
2022-02-23 8:55 ` conor.dooley
2022-02-23 9:09 ` Lee Jones
2022-02-23 9:09 ` Lee Jones
2022-02-24 13:19 ` Thierry Reding
2022-02-24 13:19 ` Thierry Reding
2022-02-14 13:58 ` [PATCH v7 06/11] riscv: dts: microchip: use clk defines for icicle kit conor.dooley
2022-02-14 13:58 ` conor.dooley
2022-02-14 13:58 ` [PATCH v7 07/11] riscv: dts: microchip: add fpga fabric section to " conor.dooley
2022-02-14 13:58 ` conor.dooley
2022-02-14 13:58 ` [PATCH v7 08/11] riscv: dts: microchip: refactor icicle kit device tree conor.dooley
2022-02-14 13:58 ` conor.dooley
2022-02-14 13:58 ` [PATCH v7 09/11] riscv: dts: microchip: update peripherals in " conor.dooley
2022-02-14 13:58 ` conor.dooley
2022-02-14 13:58 ` [PATCH v7 10/11] riscv: dts: microchip: add new peripherals to " conor.dooley
2022-02-14 13:58 ` conor.dooley
2022-02-14 13:58 ` [PATCH v7 11/11] MAINTAINERS: update riscv/microchip entry conor.dooley
2022-02-14 13:58 ` conor.dooley
2022-02-23 20:48 ` [PATCH v7 00/11] Update the Icicle Kit device tree Conor Dooley
2022-02-23 20:48 ` Conor Dooley
2022-03-10 7:07 ` Palmer Dabbelt
2022-03-10 7:07 ` Palmer Dabbelt
2022-03-10 7:35 ` Conor.Dooley
2022-03-10 7:35 ` Conor.Dooley
2022-03-11 7:59 ` Zong Li
2022-03-11 7:59 ` Zong Li
2022-03-11 19:56 ` Conor Dooley
2022-03-11 19:56 ` Conor Dooley
2022-03-16 6:51 ` Uwe Kleine-König
2022-03-16 6:51 ` Uwe Kleine-König
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