* [PATCH 01/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M SoC and EVK board
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
2022-03-23 10:29 ` Krzysztof Kozlowski
2022-03-21 15:42 ` [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration Phil Edworthy
` (12 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski
Cc: Phil Edworthy, linux-renesas-soc, devicetree, Biju Das
Details of the SoC can be found here:
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output
The RZ/V2M Evaluation Kit (V2MEVK) consists of the RZ/V2M Main Board,
RZ/V2M Base Board, and CIS IMX415 Board (CIS).
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/renesas.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index fa435d6fda77..9a9f16a58359 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -430,6 +430,12 @@ properties:
- renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
- const: renesas,r9a07g054
+ - description: RZ/V2M (R9A09G011)
+ items:
+ - enum:
+ - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
+ - const: renesas,r9a09g011
+
additionalProperties: true
...
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 01/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M SoC and EVK board
2022-03-21 15:42 ` [PATCH 01/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M SoC and EVK board Phil Edworthy
@ 2022-03-23 10:29 ` Krzysztof Kozlowski
0 siblings, 0 replies; 33+ messages in thread
From: Krzysztof Kozlowski @ 2022-03-23 10:29 UTC (permalink / raw)
To: Phil Edworthy, Geert Uytterhoeven, Magnus Damm, Rob Herring
Cc: linux-renesas-soc, devicetree, Biju Das
On 21/03/2022 16:42, Phil Edworthy wrote:
> Details of the SoC can be found here:
> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output
>
> The RZ/V2M Evaluation Kit (V2MEVK) consists of the RZ/V2M Main Board,
> RZ/V2M Base Board, and CIS IMX415 Board (CIS).
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/arm/renesas.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
2022-03-21 15:42 ` [PATCH 01/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M SoC and EVK board Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
2022-03-23 10:41 ` Krzysztof Kozlowski
2022-03-21 15:42 ` [PATCH 03/14] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings Phil Edworthy
` (11 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Krzysztof Kozlowski
Cc: Phil Edworthy, linux-renesas-soc, devicetree, Biju Das
Add DT binding documentation for System Configuration (SYS) found on
RZ/V2M SoC's.
SYS block contains the SYS_VERSION register which can be used to retrieve
SoC version information.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../bindings/arm/renesas,rzv2m-sys.yaml | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
diff --git a/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml b/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
new file mode 100644
index 000000000000..1a58906336b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/renesas,rzv2m-sys.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas RZ/V2M System Configuration (SYS)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The RZ/V2M System Configuration (SYS) performs system control of the LSI
+ and supports the following functions,
+ - LSI version
+ - 34-bit address space access function
+ - PCIe related settings
+ - WDT stop control
+ - Temperature sensor (TSU) monitor
+
+properties:
+ compatible:
+ const: renesas,r9a09g011-sys
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ sysc: system-configuration@a3f03000 {
+ compatible = "renesas,r9a09g011-sys";
+ reg = <0 0xa3f03000 0 0x400>;
+ };
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration
2022-03-21 15:42 ` [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration Phil Edworthy
@ 2022-03-23 10:41 ` Krzysztof Kozlowski
2022-03-23 14:44 ` Phil Edworthy
0 siblings, 1 reply; 33+ messages in thread
From: Krzysztof Kozlowski @ 2022-03-23 10:41 UTC (permalink / raw)
To: Phil Edworthy, Geert Uytterhoeven, Rob Herring
Cc: linux-renesas-soc, devicetree, Biju Das
On 21/03/2022 16:42, Phil Edworthy wrote:
> Add DT binding documentation for System Configuration (SYS) found on
> RZ/V2M SoC's.
>
> SYS block contains the SYS_VERSION register which can be used to retrieve
> SoC version information.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Could you send reviewed-by tags publicly? Maybe there was internal
review, maybe not and it was just copy-pasted to all submissions...
> ---
> .../bindings/arm/renesas,rzv2m-sys.yaml | 39 +++++++++++++++++++
> 1 file changed, 39 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml b/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
> new file mode 100644
> index 000000000000..1a58906336b8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
> @@ -0,0 +1,39 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/renesas,rzv2m-sys.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Renesas RZ/V2M System Configuration (SYS)
> +
> +maintainers:
> + - Geert Uytterhoeven <geert+renesas@glider.be>
> +
> +description:
> + The RZ/V2M System Configuration (SYS) performs system control of the LSI
> + and supports the following functions,
> + - LSI version
> + - 34-bit address space access function
> + - PCIe related settings
> + - WDT stop control
> + - Temperature sensor (TSU) monitor
Usually all these are separate devices, so what does it mean that SYS is
supporting these functions? Is it related to other Renesas System
Controllers? For example
Documentation/devicetree/bindings/power/renesas,apmu.yaml
?
Why one is in power and one in arm subdirectory? Maybe you should extend
existing one?
> +
> +properties:
> + compatible:
> + const: renesas,r9a09g011-sys
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + sysc: system-configuration@a3f03000 {
> + compatible = "renesas,r9a09g011-sys";
> + reg = <0 0xa3f03000 0 0x400>;
Did you actually test it (make dt_binding_check)? This looks wrong.
> + };
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 33+ messages in thread* RE: [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration
2022-03-23 10:41 ` Krzysztof Kozlowski
@ 2022-03-23 14:44 ` Phil Edworthy
2022-03-23 14:54 ` Krzysztof Kozlowski
0 siblings, 1 reply; 33+ messages in thread
From: Phil Edworthy @ 2022-03-23 14:44 UTC (permalink / raw)
To: Krzysztof Kozlowski, Geert Uytterhoeven, Rob Herring
Cc: linux-renesas-soc, devicetree, Biju Das
Hi Krzysztof,
Thanks for the review.
On 23 March 2022 10:42, Krzysztof Kozlowski wrote:
> On 21/03/2022 16:42, Phil Edworthy wrote:
> > Add DT binding documentation for System Configuration (SYS) found on
> > RZ/V2M SoC's.
> >
> > SYS block contains the SYS_VERSION register which can be used to
> retrieve
> > SoC version information.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> Could you send reviewed-by tags publicly? Maybe there was internal
> review, maybe not and it was just copy-pasted to all submissions...
Yes, it was reviewed internally.
We've done it like this for a while, I'll see what we can do to change
the way we do it. Would just copying the person who reviewed it be
enough?
> > ---
> > .../bindings/arm/renesas,rzv2m-sys.yaml | 39 +++++++++++++++++++
> > 1 file changed, 39 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/arm/renesas,rzv2m-
> sys.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/arm/renesas,rzv2m-
> sys.yaml b/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
> > new file mode 100644
> > index 000000000000..1a58906336b8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
> > @@ -0,0 +1,39 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/arm/renesas,rzv2m-sys.yaml#"
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > +
> > +title: Renesas RZ/V2M System Configuration (SYS)
> > +
> > +maintainers:
> > + - Geert Uytterhoeven <geert+renesas@glider.be>
> > +
> > +description:
> > + The RZ/V2M System Configuration (SYS) performs system control of the
> LSI
> > + and supports the following functions,
> > + - LSI version
> > + - 34-bit address space access function
> > + - PCIe related settings
> > + - WDT stop control
> > + - Temperature sensor (TSU) monitor
>
> Usually all these are separate devices, so what does it mean that SYS is
> supporting these functions? Is it related to other Renesas System
> Controllers? For example
> Documentation/devicetree/bindings/power/renesas,apmu.yaml
> ?
> Why one is in power and one in arm subdirectory? Maybe you should extend
> existing one?
SYS looks like somewhere to put registers that don't have a logical home.
There are lots of little bits, I just listed the main functions.
On other Renesas SoCs, it's similar but they include power related
registers. Actually, I originally put it in the power directory, then
moved it.
> > +
> > +properties:
> > + compatible:
> > + const: renesas,r9a09g011-sys
> > +
> > + reg:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + sysc: system-configuration@a3f03000 {
> > + compatible = "renesas,r9a09g011-sys";
> > + reg = <0 0xa3f03000 0 0x400>;
>
> Did you actually test it (make dt_binding_check)? This looks wrong.
Sorry, I missed that.
I just tried, but it's failing on some unrelated bindings for a
different SoC. It may be because I'm basing it off next-20220321
at the moment.
> > + };
>
>
> Best regards,
> Krzysztof
Thanks
Phil
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration
2022-03-23 14:44 ` Phil Edworthy
@ 2022-03-23 14:54 ` Krzysztof Kozlowski
2022-03-29 1:03 ` Rob Herring
0 siblings, 1 reply; 33+ messages in thread
From: Krzysztof Kozlowski @ 2022-03-23 14:54 UTC (permalink / raw)
To: Phil Edworthy, Geert Uytterhoeven, Rob Herring
Cc: linux-renesas-soc, devicetree, Biju Das
On 23/03/2022 15:44, Phil Edworthy wrote:
> Hi Krzysztof,
>
> Thanks for the review.
>
> On 23 March 2022 10:42, Krzysztof Kozlowski wrote:
>> On 21/03/2022 16:42, Phil Edworthy wrote:
>>> Add DT binding documentation for System Configuration (SYS) found on
>>> RZ/V2M SoC's.
>>>
>>> SYS block contains the SYS_VERSION register which can be used to
>> retrieve
>>> SoC version information.
>>>
>>> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
>>> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
>>
>> Could you send reviewed-by tags publicly? Maybe there was internal
>> review, maybe not and it was just copy-pasted to all submissions...
> Yes, it was reviewed internally.
> We've done it like this for a while, I'll see what we can do to change
> the way we do it. Would just copying the person who reviewed it be
> enough?
>
>>> ---
>>> .../bindings/arm/renesas,rzv2m-sys.yaml | 39 +++++++++++++++++++
>>> 1 file changed, 39 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/arm/renesas,rzv2m-
>> sys.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/renesas,rzv2m-
>> sys.yaml b/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
>>> new file mode 100644
>>> index 000000000000..1a58906336b8
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
>>> @@ -0,0 +1,39 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: "http://devicetree.org/schemas/arm/renesas,rzv2m-sys.yaml#"
>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>>> +
>>> +title: Renesas RZ/V2M System Configuration (SYS)
>>> +
>>> +maintainers:
>>> + - Geert Uytterhoeven <geert+renesas@glider.be>
>>> +
>>> +description:
>>> + The RZ/V2M System Configuration (SYS) performs system control of the
>> LSI
>>> + and supports the following functions,
>>> + - LSI version
>>> + - 34-bit address space access function
>>> + - PCIe related settings
>>> + - WDT stop control
>>> + - Temperature sensor (TSU) monitor
>>
>> Usually all these are separate devices, so what does it mean that SYS is
>> supporting these functions? Is it related to other Renesas System
>> Controllers? For example
>> Documentation/devicetree/bindings/power/renesas,apmu.yaml
>> ?
>> Why one is in power and one in arm subdirectory? Maybe you should extend
>> existing one?
>
> SYS looks like somewhere to put registers that don't have a logical home.
> There are lots of little bits, I just listed the main functions.
> On other Renesas SoCs, it's similar but they include power related
> registers. Actually, I originally put it in the power directory, then
> moved it.
The existing rzg2l-sysc looks similar and is in power. If arm location
is conscious choice (not just placeholder), fine with me. :)
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration
2022-03-23 14:54 ` Krzysztof Kozlowski
@ 2022-03-29 1:03 ` Rob Herring
2022-04-26 14:10 ` Geert Uytterhoeven
0 siblings, 1 reply; 33+ messages in thread
From: Rob Herring @ 2022-03-29 1:03 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Phil Edworthy, Geert Uytterhoeven, linux-renesas-soc, devicetree,
Biju Das
On Wed, Mar 23, 2022 at 03:54:42PM +0100, Krzysztof Kozlowski wrote:
> On 23/03/2022 15:44, Phil Edworthy wrote:
> > Hi Krzysztof,
> >
> > Thanks for the review.
> >
> > On 23 March 2022 10:42, Krzysztof Kozlowski wrote:
> >> On 21/03/2022 16:42, Phil Edworthy wrote:
> >>> Add DT binding documentation for System Configuration (SYS) found on
> >>> RZ/V2M SoC's.
> >>>
> >>> SYS block contains the SYS_VERSION register which can be used to
> >> retrieve
> >>> SoC version information.
> >>>
> >>> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> >>> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> >>
> >> Could you send reviewed-by tags publicly? Maybe there was internal
> >> review, maybe not and it was just copy-pasted to all submissions...
> > Yes, it was reviewed internally.
> > We've done it like this for a while, I'll see what we can do to change
> > the way we do it. Would just copying the person who reviewed it be
> > enough?
> >
> >>> ---
> >>> .../bindings/arm/renesas,rzv2m-sys.yaml | 39 +++++++++++++++++++
> >>> 1 file changed, 39 insertions(+)
> >>> create mode 100644 Documentation/devicetree/bindings/arm/renesas,rzv2m-
> >> sys.yaml
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/arm/renesas,rzv2m-
> >> sys.yaml b/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
> >>> new file mode 100644
> >>> index 000000000000..1a58906336b8
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
> >>> @@ -0,0 +1,39 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: "http://devicetree.org/schemas/arm/renesas,rzv2m-sys.yaml#"
> >>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> >>> +
> >>> +title: Renesas RZ/V2M System Configuration (SYS)
> >>> +
> >>> +maintainers:
> >>> + - Geert Uytterhoeven <geert+renesas@glider.be>
> >>> +
> >>> +description:
> >>> + The RZ/V2M System Configuration (SYS) performs system control of the
> >> LSI
> >>> + and supports the following functions,
> >>> + - LSI version
> >>> + - 34-bit address space access function
> >>> + - PCIe related settings
> >>> + - WDT stop control
> >>> + - Temperature sensor (TSU) monitor
> >>
> >> Usually all these are separate devices, so what does it mean that SYS is
> >> supporting these functions? Is it related to other Renesas System
> >> Controllers? For example
> >> Documentation/devicetree/bindings/power/renesas,apmu.yaml
> >> ?
> >> Why one is in power and one in arm subdirectory? Maybe you should extend
> >> existing one?
> >
> > SYS looks like somewhere to put registers that don't have a logical home.
> > There are lots of little bits, I just listed the main functions.
> > On other Renesas SoCs, it's similar but they include power related
> > registers. Actually, I originally put it in the power directory, then
> > moved it.
>
> The existing rzg2l-sysc looks similar and is in power. If arm location
> is conscious choice (not just placeholder), fine with me. :)
The preference is:
1) subsystem/class
2) soc/ dir
And arm/ for just top-level bindings.
Rob
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration
2022-03-29 1:03 ` Rob Herring
@ 2022-04-26 14:10 ` Geert Uytterhoeven
0 siblings, 0 replies; 33+ messages in thread
From: Geert Uytterhoeven @ 2022-04-26 14:10 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, Phil Edworthy, linux-renesas-soc,
devicetree, Biju Das
On Tue, Mar 29, 2022 at 3:03 AM Rob Herring <robh@kernel.org> wrote:
> On Wed, Mar 23, 2022 at 03:54:42PM +0100, Krzysztof Kozlowski wrote:
> > On 23/03/2022 15:44, Phil Edworthy wrote:
> > > On 23 March 2022 10:42, Krzysztof Kozlowski wrote:
> > >> On 21/03/2022 16:42, Phil Edworthy wrote:
> > >>> Add DT binding documentation for System Configuration (SYS) found on
> > >>> RZ/V2M SoC's.
> > >>>
> > >>> SYS block contains the SYS_VERSION register which can be used to
> > >> retrieve
> > >>> SoC version information.
> > >>>
> > >>> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > >>> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > >>
> > >> Could you send reviewed-by tags publicly? Maybe there was internal
> > >> review, maybe not and it was just copy-pasted to all submissions...
> > > Yes, it was reviewed internally.
> > > We've done it like this for a while, I'll see what we can do to change
> > > the way we do it. Would just copying the person who reviewed it be
> > > enough?
> > >
> > >>> ---
> > >>> .../bindings/arm/renesas,rzv2m-sys.yaml | 39 +++++++++++++++++++
> > >>> 1 file changed, 39 insertions(+)
> > >>> create mode 100644 Documentation/devicetree/bindings/arm/renesas,rzv2m-
> > >> sys.yaml
> > >>>
> > >>> diff --git a/Documentation/devicetree/bindings/arm/renesas,rzv2m-
> > >> sys.yaml b/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
> > >>> new file mode 100644
> > >>> index 000000000000..1a58906336b8
> > >>> --- /dev/null
> > >>> +++ b/Documentation/devicetree/bindings/arm/renesas,rzv2m-sys.yaml
> > >>> @@ -0,0 +1,39 @@
> > >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > >>> +%YAML 1.2
> > >>> +---
> > >>> +$id: "http://devicetree.org/schemas/arm/renesas,rzv2m-sys.yaml#"
> > >>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > >>> +
> > >>> +title: Renesas RZ/V2M System Configuration (SYS)
> > >>> +
> > >>> +maintainers:
> > >>> + - Geert Uytterhoeven <geert+renesas@glider.be>
> > >>> +
> > >>> +description:
> > >>> + The RZ/V2M System Configuration (SYS) performs system control of the
> > >> LSI
> > >>> + and supports the following functions,
> > >>> + - LSI version
> > >>> + - 34-bit address space access function
> > >>> + - PCIe related settings
> > >>> + - WDT stop control
> > >>> + - Temperature sensor (TSU) monitor
> > >>
> > >> Usually all these are separate devices, so what does it mean that SYS is
> > >> supporting these functions? Is it related to other Renesas System
> > >> Controllers? For example
> > >> Documentation/devicetree/bindings/power/renesas,apmu.yaml
> > >> ?
> > >> Why one is in power and one in arm subdirectory? Maybe you should extend
> > >> existing one?
> > >
> > > SYS looks like somewhere to put registers that don't have a logical home.
> > > There are lots of little bits, I just listed the main functions.
> > > On other Renesas SoCs, it's similar but they include power related
> > > registers. Actually, I originally put it in the power directory, then
> > > moved it.
> >
> > The existing rzg2l-sysc looks similar and is in power. If arm location
> > is conscious choice (not just placeholder), fine with me. :)
>
> The preference is:
>
> 1) subsystem/class
> 2) soc/ dir
>
> And arm/ for just top-level bindings.
Documentation/devicetree/bindings/soc/renesas/ sounds good to me!
I'll send patches to move .../arm/renesas,prr.yaml and
.../power/renesas,rzg2l-sysc.yaml to .../soc/renesas/, too.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 03/14] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
2022-03-21 15:42 ` [PATCH 01/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M SoC and EVK board Phil Edworthy
2022-03-21 15:42 ` [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
2022-03-23 10:42 ` Krzysztof Kozlowski
2022-03-21 15:42 ` [PATCH 04/14] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions Phil Edworthy
` (10 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Geert Uytterhoeven, Greg Kroah-Hartman, Magnus Damm, Rob Herring,
Krzysztof Kozlowski
Cc: Phil Edworthy, linux-renesas-soc, linux-serial, devicetree, Biju Das
The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with the
EMMA Mobile SoC.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../devicetree/bindings/serial/renesas,em-uart.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
index e98ec48fee46..42733eaa0ece 100644
--- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
@@ -14,7 +14,11 @@ allOf:
properties:
compatible:
- const: renesas,em-uart
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a09g011-uart # RZ/V2M
+ - const: renesas,em-uart # generic EMMA Mobile compatible UART
reg:
maxItems: 1
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 03/14] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings
2022-03-21 15:42 ` [PATCH 03/14] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings Phil Edworthy
@ 2022-03-23 10:42 ` Krzysztof Kozlowski
2022-03-23 14:49 ` Phil Edworthy
0 siblings, 1 reply; 33+ messages in thread
From: Krzysztof Kozlowski @ 2022-03-23 10:42 UTC (permalink / raw)
To: Phil Edworthy, Geert Uytterhoeven, Greg Kroah-Hartman,
Magnus Damm, Rob Herring
Cc: linux-renesas-soc, linux-serial, devicetree, Biju Das
On 21/03/2022 16:42, Phil Edworthy wrote:
> The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with the
> EMMA Mobile SoC.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../devicetree/bindings/serial/renesas,em-uart.yaml | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> index e98ec48fee46..42733eaa0ece 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> @@ -14,7 +14,11 @@ allOf:
>
> properties:
> compatible:
> - const: renesas,em-uart
> + oneOf:
No need for oneOf, you have just one element below.
> + - items:
> + - enum:
> + - renesas,r9a09g011-uart # RZ/V2M
> + - const: renesas,em-uart # generic EMMA Mobile compatible UART
>
Does not look like you tested it...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH 03/14] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings
2022-03-23 10:42 ` Krzysztof Kozlowski
@ 2022-03-23 14:49 ` Phil Edworthy
0 siblings, 0 replies; 33+ messages in thread
From: Phil Edworthy @ 2022-03-23 14:49 UTC (permalink / raw)
To: Krzysztof Kozlowski, Geert Uytterhoeven, Greg Kroah-Hartman,
Magnus Damm, Rob Herring
Cc: linux-renesas-soc, linux-serial, devicetree, Biju Das
Hi Krzysztof,
On 23 March 2022 10:42, Krzysztof Kozlowski wrote:
> On 21/03/2022 16:42, Phil Edworthy wrote:
> > The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with
> the
> > EMMA Mobile SoC.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > .../devicetree/bindings/serial/renesas,em-uart.yaml | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/serial/renesas,em-
> uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > index e98ec48fee46..42733eaa0ece 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > @@ -14,7 +14,11 @@ allOf:
> >
> > properties:
> > compatible:
> > - const: renesas,em-uart
> > + oneOf:
>
> No need for oneOf, you have just one element below.
Ok
> > + - items:
> > + - enum:
> > + - renesas,r9a09g011-uart # RZ/V2M
> > + - const: renesas,em-uart # generic EMMA Mobile
> compatible UART
> >
>
> Does not look like you tested it...
Sorry about that.
>
> Best regards,
> Krzysztof
Thanks
Phil
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 04/14] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
` (2 preceding siblings ...)
2022-03-21 15:42 ` [PATCH 03/14] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
2022-03-23 10:44 ` Krzysztof Kozlowski
2022-03-21 15:42 ` [PATCH 05/14] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC Phil Edworthy
` (9 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Krzysztof Kozlowski
Cc: Phil Edworthy, linux-renesas-soc, devicetree, Biju Das
Define RZ/V2M (R9A09G011) Clock Pulse Generator core clocks, module clock
outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_*
registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware
User's Manual (Rev. 1.10, Sep. 2021).
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
include/dt-bindings/clock/r9a09g011-cpg.h | 337 ++++++++++++++++++++++
1 file changed, 337 insertions(+)
create mode 100644 include/dt-bindings/clock/r9a09g011-cpg.h
diff --git a/include/dt-bindings/clock/r9a09g011-cpg.h b/include/dt-bindings/clock/r9a09g011-cpg.h
new file mode 100644
index 000000000000..b88dbb0d8c49
--- /dev/null
+++ b/include/dt-bindings/clock/r9a09g011-cpg.h
@@ -0,0 +1,337 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* Module Clocks */
+#define R9A09G011_SYS_CLK 0
+#define R9A09G011_PFC_PCLK 1
+#define R9A09G011_PMC_CORE_CLOCK 2
+#define R9A09G011_GIC_CLK 3
+#define R9A09G011_RAMA_ACLK 4
+
+#define R9A09G011_SEC_ACLK 5
+#define R9A09G011_SEC_PCLK 6
+#define R9A09G011_SEC_TCLK 7
+#define R9A09G011_DMAA_ACLK 8
+#define R9A09G011_TSU0_PCLK 9
+#define R9A09G011_TSU1_PCLK 10
+
+#define R9A09G011_CST_TRACECLK 11
+#define R9A09G011_CST_SB_CLK 12
+#define R9A09G011_CST_AHB_CLK 13
+#define R9A09G011_CST_ATB_SB_CLK 14
+
+#define R9A09G011_SDI0_ACLK 15
+#define R9A09G011_SDI0_IMCLK 16
+#define R9A09G011_SDI0_IMCLK2 17
+#define R9A09G011_SDI0_CLK_HS 18
+#define R9A09G011_SDI1_ACLK 19
+#define R9A09G011_SDI1_IMCLK 20
+#define R9A09G011_SDI1_IMCLK2 21
+#define R9A09G011_SDI1_CLK_HS 22
+#define R9A09G011_EMM_ACLK 23
+#define R9A09G011_EMM_IMCLK 24
+#define R9A09G011_EMM_IMCLK2 25
+#define R9A09G011_EMM_CLK_HS 26
+#define R9A09G011_NFI_ACLK 27
+#define R9A09G011_NFI_NF_CLK 28
+
+#define R9A09G011_PCI_ACLK 29
+#define R9A09G011_PCI_CLK_PMU 30
+#define R9A09G011_PCI_APB_CLK 31
+#define R9A09G011_USB_ACLK_H 32
+#define R9A09G011_USB_ACLK_P 33
+#define R9A09G011_USB_PCLK 34
+#define R9A09G011_ETH_CLK_AXI 35
+#define R9A09G011_ETH_CLK_CHI 36
+#define R9A09G011_ETH_GPTP_EXT 37
+
+#define R9A09G011_SDT_CLK 38
+#define R9A09G011_SDT_CLKAPB 39
+#define R9A09G011_SDT_CLK48 40
+#define R9A09G011_GRP_CLK 41
+#define R9A09G011_CIF_P0_CLK 42
+#define R9A09G011_CIF_P1_CLK 43
+#define R9A09G011_CIF_APB_CLK 44
+#define R9A09G011_DCI_CLKAXI 45
+#define R9A09G011_DCI_CLKAPB 46
+#define R9A09G011_DCI_CLKDCI2 47
+
+#define R9A09G011_HMI_PCLK 48
+#define R9A09G011_LCI_PCLK 49
+#define R9A09G011_LCI_ACLK 50
+#define R9A09G011_LCI_VCLK 51
+#define R9A09G011_LCI_LPCLK 52
+
+#define R9A09G011_AUI_CLK 53
+#define R9A09G011_AUI_CLKAXI 54
+#define R9A09G011_AUI_CLKAPB 55
+#define R9A09G011_AUMCLK 56
+#define R9A09G011_GMCLK0 57
+#define R9A09G011_GMCLK1 58
+#define R9A09G011_MTR_CLK0 59
+#define R9A09G011_MTR_CLK1 60
+#define R9A09G011_MTR_CLKAPB 61
+#define R9A09G011_GFT_CLK 62
+#define R9A09G011_GFT_CLKAPB 63
+#define R9A09G011_GFT_MCLK 64
+
+#define R9A09G011_ATGA_CLK 65
+#define R9A09G011_ATGA_CLKAPB 66
+#define R9A09G011_ATGB_CLK 67
+#define R9A09G011_ATGB_CLKAPB 68
+#define R9A09G011_SYC_CNT_CLK 69
+
+#define R9A09G011_GRPA_PCLK 70
+#define R9A09G011_TIM0_CLK 71
+#define R9A09G011_TIM1_CLK 72
+#define R9A09G011_TIM2_CLK 73
+#define R9A09G011_TIM3_CLK 74
+#define R9A09G011_TIM4_CLK 75
+#define R9A09G011_TIM5_CLK 76
+#define R9A09G011_TIM6_CLK 77
+#define R9A09G011_TIM7_CLK 78
+#define R9A09G011_IIC01_PCLK 79
+
+#define R9A09G011_GRPB_PCLK 80
+#define R9A09G011_TIM8_CLK 81
+#define R9A09G011_TIM9_CLK 82
+#define R9A09G011_TIM10_CLK 83
+#define R9A09G011_TIM11_CLK 84
+#define R9A09G011_TIM12_CLK 85
+#define R9A09G011_TIM13_CLK 86
+#define R9A09G011_TIM14_CLK 87
+#define R9A09G011_TIM15_CLK 88
+#define R9A09G011_IIC23_PCLK 89
+
+#define R9A09G011_GRPC_PCLK 90
+#define R9A09G011_TIM16_CLK 91
+#define R9A09G011_TIM17_CLK 92
+#define R9A09G011_TIM18_CLK 93
+#define R9A09G011_TIM19_CLK 94
+#define R9A09G011_TIM20_CLK 95
+#define R9A09G011_TIM21_CLK 96
+#define R9A09G011_TIM22_CLK 97
+#define R9A09G011_TIM23_CLK 98
+#define R9A09G011_WDT0_PCLK 99
+#define R9A09G011_WDT0_CLK 100
+#define R9A09G011_WDT1_PCLK 101
+#define R9A09G011_WDT1_CLK 102
+
+#define R9A09G011_GRPD_PCLK 103
+#define R9A09G011_TIM24_CLK 104
+#define R9A09G011_TIM25_CLK 105
+#define R9A09G011_TIM26_CLK 106
+#define R9A09G011_TIM27_CLK 107
+#define R9A09G011_TIM28_CLK 108
+#define R9A09G011_TIM29_CLK 109
+#define R9A09G011_TIM30_CLK 110
+#define R9A09G011_TIM31_CLK 111
+
+#define R9A09G011_GRPE_PCLK 112
+#define R9A09G011_PWM0_CLK 113
+#define R9A09G011_PWM1_CLK 114
+#define R9A09G011_PWM2_CLK 115
+#define R9A09G011_PWM3_CLK 116
+#define R9A09G011_PWM4_CLK 117
+#define R9A09G011_PWM5_CLK 118
+#define R9A09G011_PWM6_CLK 119
+#define R9A09G011_PWM7_CLK 120
+
+#define R9A09G011_GRPF_PCLK 121
+#define R9A09G011_PWM8_CLK 122
+#define R9A09G011_PWM9_CLK 123
+#define R9A09G011_PWM10_CLK 124
+#define R9A09G011_PWM11_CLK 125
+#define R9A09G011_PWM12_CLK 126
+#define R9A09G011_PWM13_CLK 127
+#define R9A09G011_PWM14_CLK 128
+#define R9A09G011_PWM15_CLK 129
+
+#define R9A09G011_GRPG_PCLK 130
+#define R9A09G011_GRPH_PCLK 131
+#define R9A09G011_URT_PCLK 132
+#define R9A09G011_URT0_CLK 133
+#define R9A09G011_URT1_CLK 134
+#define R9A09G011_CSI0_CLK 135
+#define R9A09G011_CSI1_CLK 136
+#define R9A09G011_CSI2_CLK 137
+#define R9A09G011_CSI3_CLK 138
+#define R9A09G011_CSI4_CLK 139
+#define R9A09G011_CSI5_CLK 140
+
+#define R9A09G011_ICB_ACLK1 141
+#define R9A09G011_ICB_MPCLK1 142
+#define R9A09G011_ICB_SPCLK1 143
+#define R9A09G011_ICB_CLK48 144
+#define R9A09G011_ICB_CLK48_2 145
+#define R9A09G011_ICB_CLK48_3 146
+#define R9A09G011_ICB_CLK48_4L 147
+#define R9A09G011_ICB_CLK48_5 148
+#define R9A09G011_ICB_CST_ATB_SB_CLK 149
+#define R9A09G011_ICB_CST_CS_CLK 150
+#define R9A09G011_ICB_CLK100_1 151
+#define R9A09G011_ICB_ETH0_CLK_AXI 152
+#define R9A09G011_ICB_DCI_CLKAXI 153
+#define R9A09G011_ICB_SYC_CNT_CLK 154
+
+#define R9A09G011_ICB_DRPA_ACLK 155
+#define R9A09G011_ICB_RFX_ACLK 156
+#define R9A09G011_ICB_MMC_ACLK 157
+
+#define R9A09G011_ICB_MPCLK3 158
+#define R9A09G011_ICB_CIMA_CLK 159
+#define R9A09G011_ICB_CIMB_CLK 160
+#define R9A09G011_ICB_BIMA_CLK 161
+#define R9A09G011_ICB_FCD_CLKAXI 162
+#define R9A09G011_ICB_VD_ACLK4 163
+#define R9A09G011_ICB_MPCLK4 164
+#define R9A09G011_ICB_VCD_PCLK4 165
+
+#define R9A09G011_CA53_CLK 166
+#define R9A09G011_CA53_ACLK 167
+#define R9A09G011_CA53_APCLK_DBG 168
+#define R9A09G011_CA53_ATCLK 169
+#define R9A09G011_CA53_TSCLK 170
+#define R9A09G011_CA53_APCLK_REG 171
+
+#define R9A09G011_DRPA_ACLK 172
+#define R9A09G011_DRPA_DCLK 173
+#define R9A09G011_DRPA_INITCLK 174
+
+#define R9A09G011_RAMB_ACLK 175
+
+#define R9A09G011_CIMA_CLKAPB 176
+#define R9A09G011_CIMA_CLK 177
+#define R9A09G011_CIMB_CLK 178
+#define R9A09G011_FAFA_CLK 179
+#define R9A09G011_STG_CLKAXI 180
+#define R9A09G011_STG_CLK0 181
+
+#define R9A09G011_BIMA_CLKAPB 182
+#define R9A09G011_BIMA_CLK 183
+#define R9A09G011_FAFB_CLK 184
+#define R9A09G011_FCD_CLK 185
+#define R9A09G011_FCD_CLKAXI 186
+
+#define R9A09G011_RIM_CLK 187
+#define R9A09G011_VCD_ACLK 188
+#define R9A09G011_JPG0_CLK 189
+#define R9A09G011_JPG0_ACLK 190
+
+#define R9A09G011_MMC_CORE_DDRC_CLK 191
+#define R9A09G011_MMC_ACLK 192
+#define R9A09G011_MMC_PCLK 193
+#define R9A09G011_DDI_APBCLK 194
+
+/* Resets */
+#define R9A09G011_SYS_RST_N 0
+#define R9A09G011_PFC_PRESETN 1
+#define R9A09G011_RAMA_ARESETN 2
+#define R9A09G011_ROM_ARESETN 3
+#define R9A09G011_DMAA_ARESETN 4
+#define R9A09G011_SEC_ARESETN 5
+#define R9A09G011_SEC_PRESETN 6
+#define R9A09G011_SEC_RSTB 7
+#define R9A09G011_TSU0_RESETN 8
+#define R9A09G011_TSU1_RESETN 9
+#define R9A09G011_PMC_RESET_N 10
+
+#define R9A09G011_CST_NTRST 11
+#define R9A09G011_CST_NPOTRST 12
+#define R9A09G011_CST_CS_RESETN 13
+#define R9A09G011_CST_TS_RESETN 14
+#define R9A09G011_CST_TRESETN 15
+#define R9A09G011_CST_SB_RESETN 16
+#define R9A09G011_CST_AHB_RESETN 17
+#define R9A09G011_CST_TS_SB_RESETN 18
+#define R9A09G011_CST_APB_CA53_RESETN 19
+#define R9A09G011_CST_ATB_SB_RESETN 20
+
+#define R9A09G011_SDI0_IXRST 21
+#define R9A09G011_SDI1_IXRST 22
+#define R9A09G011_EMM_IXRST 23
+#define R9A09G011_NFI_MARESETN 24
+#define R9A09G011_NFI_REG_RST_N 25
+#define R9A09G011_USB_PRESET_N 26
+#define R9A09G011_USB_DRD_RESET 27
+#define R9A09G011_USB_ARESETN_P 28
+#define R9A09G011_USB_ARESETN_H 29
+#define R9A09G011_ETH0_RST_HW_N 30
+#define R9A09G011_PCI_ARESETN 31
+
+#define R9A09G011_SDT_RSTSYSAX 32
+#define R9A09G011_GRP_RESETN 33
+#define R9A09G011_CIF_RST_N 34
+#define R9A09G011_DCU_RSTSYSAX 35
+#define R9A09G011_HMI_RST_N 36
+#define R9A09G011_HMI_PRESETN 37
+#define R9A09G011_LCI_PRESETN 38
+#define R9A09G011_LCI_ARESETN 39
+
+#define R9A09G011_AUI_RSTSYSAX 40
+#define R9A09G011_MTR_RSTSYSAX 41
+#define R9A09G011_GFT_RSTSYSAX 42
+#define R9A09G011_ATGA_RSTSYSAX 43
+#define R9A09G011_ATGB_RSTSYSAX 44
+#define R9A09G011_SYC_RST_N 45
+
+#define R9A09G011_TIM_GPA_PRESETN 46
+#define R9A09G011_TIM_GPB_PRESETN 47
+#define R9A09G011_TIM_GPC_PRESETN 48
+#define R9A09G011_TIM_GPD_PRESETN 49
+#define R9A09G011_PWM_GPE_PRESETN 50
+#define R9A09G011_PWM_GPF_PRESETN 51
+#define R9A09G011_CSI_GPG_PRESETN 52
+#define R9A09G011_CSI_GPH_PRESETN 53
+#define R9A09G011_IIC_GPA_PRESETN 54
+#define R9A09G011_IIC_GPB_PRESETN 55
+#define R9A09G011_URT_PRESETN 56
+#define R9A09G011_WDT0_PRESETN 57
+#define R9A09G011_WDT1_PRESETN 58
+
+#define R9A09G011_ICB_PD_AWO_RST_N 59
+#define R9A09G011_ICB_PD_MMC_RST_N 60
+#define R9A09G011_ICB_PD_VD0_RST_N 61
+#define R9A09G011_ICB_PD_VD1_RST_N 62
+#define R9A09G011_ICB_PD_RFX_RST_N 63
+
+#define R9A09G011_CA53_NCPUPORESET0 64
+#define R9A09G011_CA53_NCPUPORESET1 65
+#define R9A09G011_CA53_NCORERESET0 66
+#define R9A09G011_CA53_NCORERESET1 67
+#define R9A09G011_CA53_NPRESETDBG 68
+#define R9A09G011_CA53_L2RESET 69
+#define R9A09G011_CA53_NMISCRESET_HM 70
+#define R9A09G011_CA53_NMISCRESET_SM 71
+#define R9A09G011_CA53_NARESET 72
+
+#define R9A09G011_DRPA_ARESETN 73
+
+#define R9A09G011_RAMB_ARESETN 74
+
+#define R9A09G011_CIMA_RSTSYSAX 75
+#define R9A09G011_CIMB_RSTSYSAX 76
+#define R9A09G011_FAFA_RSTSYSAX 77
+#define R9A09G011_STG_RSTSYSAX 78
+
+#define R9A09G011_BIMA_RSTSYSAX 79
+#define R9A09G011_FAFB_RSTSYSAX 80
+#define R9A09G011_FCD_RSTSYSAX 81
+#define R9A09G011_RIM_RSTSYSAX 82
+#define R9A09G011_VCD_RESETN 83
+#define R9A09G011_JPG_XRESET 84
+
+#define R9A09G011_MMC_CORE_DDRC_RSTN 85
+#define R9A09G011_MMC_ARESETN_N 86
+#define R9A09G011_MMC_PRESETN 87
+#define R9A09G011_DDI_PWROK 88
+#define R9A09G011_DDI_RESET 89
+#define R9A09G011_DDI_RESETN_APB 90
+
+#endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 04/14] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions
2022-03-21 15:42 ` [PATCH 04/14] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions Phil Edworthy
@ 2022-03-23 10:44 ` Krzysztof Kozlowski
2022-03-23 14:07 ` Phil Edworthy
2022-03-23 14:29 ` Geert Uytterhoeven
0 siblings, 2 replies; 33+ messages in thread
From: Krzysztof Kozlowski @ 2022-03-23 10:44 UTC (permalink / raw)
To: Phil Edworthy, Geert Uytterhoeven, Rob Herring
Cc: linux-renesas-soc, devicetree, Biju Das
On 21/03/2022 16:42, Phil Edworthy wrote:
> Define RZ/V2M (R9A09G011) Clock Pulse Generator core clocks, module clock
> outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_*
> registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware
> User's Manual (Rev. 1.10, Sep. 2021).
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> include/dt-bindings/clock/r9a09g011-cpg.h | 337 ++++++++++++++++++++++
> 1 file changed, 337 insertions(+)
> create mode 100644 include/dt-bindings/clock/r9a09g011-cpg.h
>
> diff --git a/include/dt-bindings/clock/r9a09g011-cpg.h b/include/dt-bindings/clock/r9a09g011-cpg.h
> new file mode 100644
> index 000000000000..b88dbb0d8c49
> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a09g011-cpg.h
> @@ -0,0 +1,337 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
> +#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
Include only headers which you use here. Do you use it directly here?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 33+ messages in thread* RE: [PATCH 04/14] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions
2022-03-23 10:44 ` Krzysztof Kozlowski
@ 2022-03-23 14:07 ` Phil Edworthy
2022-03-23 14:29 ` Geert Uytterhoeven
1 sibling, 0 replies; 33+ messages in thread
From: Phil Edworthy @ 2022-03-23 14:07 UTC (permalink / raw)
To: Krzysztof Kozlowski, Geert Uytterhoeven, Rob Herring
Cc: linux-renesas-soc, devicetree, Biju Das
Hi Krzysztof,
Thanks for the review.
On 23 March 2022 10:44, Krzysztof Kozlowski wrote:
> On 21/03/2022 16:42, Phil Edworthy wrote:
> > Define RZ/V2M (R9A09G011) Clock Pulse Generator core clocks, module
> clock
> > outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_*
> > registers) in Section 48.5 ("Register Description") of the RZ/V2M
> Hardware
> > User's Manual (Rev. 1.10, Sep. 2021).
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > include/dt-bindings/clock/r9a09g011-cpg.h | 337 ++++++++++++++++++++++
> > 1 file changed, 337 insertions(+)
> > create mode 100644 include/dt-bindings/clock/r9a09g011-cpg.h
> >
> > diff --git a/include/dt-bindings/clock/r9a09g011-cpg.h b/include/dt-
> bindings/clock/r9a09g011-cpg.h
> > new file mode 100644
> > index 000000000000..b88dbb0d8c49
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r9a09g011-cpg.h
> > @@ -0,0 +1,337 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
> > +#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
>
> Include only headers which you use here. Do you use it directly here?
Ah, it was just used by my dtsi for CPG_CORE and CPG_MOD definitions.
I'll moved the include to the dtsi.
Thanks
Phil
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH 04/14] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions
2022-03-23 10:44 ` Krzysztof Kozlowski
2022-03-23 14:07 ` Phil Edworthy
@ 2022-03-23 14:29 ` Geert Uytterhoeven
2022-03-23 14:36 ` Krzysztof Kozlowski
1 sibling, 1 reply; 33+ messages in thread
From: Geert Uytterhoeven @ 2022-03-23 14:29 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Phil Edworthy, Geert Uytterhoeven, Rob Herring,
linux-renesas-soc, devicetree, Biju Das
Hi Krzysztof,
On Wed, Mar 23, 2022 at 11:44 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On 21/03/2022 16:42, Phil Edworthy wrote:
> > Define RZ/V2M (R9A09G011) Clock Pulse Generator core clocks, module clock
> > outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_*
> > registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware
> > User's Manual (Rev. 1.10, Sep. 2021).
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r9a09g011-cpg.h
> > @@ -0,0 +1,337 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
> > +#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
>
> Include only headers which you use here. Do you use it directly here?
Technically, it is part of the clock bindings for the SoC.
That's why it's included here, and in several other *-cpg-mssr.h files.
So I prefer to keep it that way.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH 04/14] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions
2022-03-23 14:29 ` Geert Uytterhoeven
@ 2022-03-23 14:36 ` Krzysztof Kozlowski
0 siblings, 0 replies; 33+ messages in thread
From: Krzysztof Kozlowski @ 2022-03-23 14:36 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Phil Edworthy, Geert Uytterhoeven, Rob Herring,
linux-renesas-soc, devicetree, Biju Das
On 23/03/2022 15:29, Geert Uytterhoeven wrote:
> Hi Krzysztof,
>
> On Wed, Mar 23, 2022 at 11:44 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>> On 21/03/2022 16:42, Phil Edworthy wrote:
>>> Define RZ/V2M (R9A09G011) Clock Pulse Generator core clocks, module clock
>>> outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_*
>>> registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware
>>> User's Manual (Rev. 1.10, Sep. 2021).
>>>
>>> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
>>> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
>
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/r9a09g011-cpg.h
>>> @@ -0,0 +1,337 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> + *
>>> + * Copyright (C) 2022 Renesas Electronics Corp.
>>> + */
>>> +#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
>>> +#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
>>> +
>>> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
>>
>> Include only headers which you use here. Do you use it directly here?
>
> Technically, it is part of the clock bindings for the SoC.
> That's why it's included here, and in several other *-cpg-mssr.h files.
>
> So I prefer to keep it that way.
Sure, thanks for the explanation. It sill makes header decoupling more
difficult if ever needed, but it's ok.
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 05/14] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
` (3 preceding siblings ...)
2022-03-21 15:42 ` [PATCH 04/14] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
2022-03-23 10:44 ` Krzysztof Kozlowski
2022-03-21 15:42 ` [PATCH 06/14] serial: 8250: Make SERIAL_8250_EM available for arm64 systems Phil Edworthy
` (8 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski
Cc: Phil Edworthy, linux-renesas-soc, linux-clk, devicetree, Biju Das
Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../bindings/clock/renesas,rzg2l-cpg.yaml | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index bd3af8fc616b..b1145f9139d2 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -4,14 +4,15 @@
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
-title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
+title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description: |
On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
- Standby Mode share the same register block.
+ Standby Mode share the same register block. On RZ/V2M, the functionality is
+ similar, but does not have Clock Monitor Registers.
They provide the following functionalities:
- The CPG block generates various core clocks,
@@ -25,6 +26,7 @@ properties:
enum:
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
- renesas,r9a07g054-cpg # RZ/V2L
+ - renesas,r9a09g011-cpg # RZ/V2M
reg:
maxItems: 1
@@ -42,9 +44,10 @@ properties:
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
- <dt-bindings/clock/r9a07g*-cpg.h>
+ <dt-bindings/clock/r9a07g*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
- a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
+ a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or
+ <dt-bindings/clock/r9a09g011-cpg.h>.
const: 2
'#power-domain-cells':
@@ -58,7 +61,7 @@ properties:
'#reset-cells':
description:
The single reset specifier cell must be the module number, as defined in
- the <dt-bindings/clock/r9a07g0*-cpg.h>.
+ the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.
const: 1
required:
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 05/14] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC
2022-03-21 15:42 ` [PATCH 05/14] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC Phil Edworthy
@ 2022-03-23 10:44 ` Krzysztof Kozlowski
0 siblings, 0 replies; 33+ messages in thread
From: Krzysztof Kozlowski @ 2022-03-23 10:44 UTC (permalink / raw)
To: Phil Edworthy, Geert Uytterhoeven, Michael Turquette,
Stephen Boyd, Rob Herring
Cc: linux-renesas-soc, linux-clk, devicetree, Biju Das
On 21/03/2022 16:42, Phil Edworthy wrote:
> Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../bindings/clock/renesas,rzg2l-cpg.yaml | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 06/14] serial: 8250: Make SERIAL_8250_EM available for arm64 systems
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
` (4 preceding siblings ...)
2022-03-21 15:42 ` [PATCH 05/14] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
2022-03-21 16:14 ` Andy Shevchenko
2022-03-21 15:42 ` [PATCH 07/14] soc: renesas: Identify RZ/V2M SoC Phil Edworthy
` (7 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Greg Kroah-Hartman, Geert Uytterhoeven
Cc: Phil Edworthy, Jiri Slaby, Johan Hovold, Andy Shevchenko,
Maciej W. Rozycki, Al Cooper, linux-renesas-soc, linux-serial,
Biju Das
This is needed for the Renesas RZ/V2M (r9a09g011) SoC.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/tty/serial/8250/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig
index cd93ea6eed65..fdb6c4188695 100644
--- a/drivers/tty/serial/8250/Kconfig
+++ b/drivers/tty/serial/8250/Kconfig
@@ -380,7 +380,7 @@ config SERIAL_8250_DW
config SERIAL_8250_EM
tristate "Support for Emma Mobile integrated serial port"
depends on SERIAL_8250 && HAVE_CLK
- depends on (ARM && ARCH_RENESAS) || COMPILE_TEST
+ depends on ARCH_RENESAS || COMPILE_TEST
help
Selecting this option will add support for the integrated serial
port hardware found on the Emma Mobile line of processors.
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 06/14] serial: 8250: Make SERIAL_8250_EM available for arm64 systems
2022-03-21 15:42 ` [PATCH 06/14] serial: 8250: Make SERIAL_8250_EM available for arm64 systems Phil Edworthy
@ 2022-03-21 16:14 ` Andy Shevchenko
0 siblings, 0 replies; 33+ messages in thread
From: Andy Shevchenko @ 2022-03-21 16:14 UTC (permalink / raw)
To: Phil Edworthy
Cc: Greg Kroah-Hartman, Geert Uytterhoeven, Jiri Slaby, Johan Hovold,
Maciej W. Rozycki, Al Cooper, linux-renesas-soc, linux-serial,
Biju Das
On Mon, Mar 21, 2022 at 03:42:24PM +0000, Phil Edworthy wrote:
> This is needed for the Renesas RZ/V2M (r9a09g011) SoC.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> drivers/tty/serial/8250/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig
> index cd93ea6eed65..fdb6c4188695 100644
> --- a/drivers/tty/serial/8250/Kconfig
> +++ b/drivers/tty/serial/8250/Kconfig
> @@ -380,7 +380,7 @@ config SERIAL_8250_DW
> config SERIAL_8250_EM
> tristate "Support for Emma Mobile integrated serial port"
> depends on SERIAL_8250 && HAVE_CLK
> - depends on (ARM && ARCH_RENESAS) || COMPILE_TEST
> + depends on ARCH_RENESAS || COMPILE_TEST
> help
> Selecting this option will add support for the integrated serial
> port hardware found on the Emma Mobile line of processors.
> --
> 2.32.0
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 07/14] soc: renesas: Identify RZ/V2M SoC
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
` (5 preceding siblings ...)
2022-03-21 15:42 ` [PATCH 06/14] serial: 8250: Make SERIAL_8250_EM available for arm64 systems Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
2022-04-26 14:16 ` Geert Uytterhoeven
2022-03-21 15:42 ` [PATCH 08/14] clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers Phil Edworthy
` (6 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Phil Edworthy, Magnus Damm, linux-renesas-soc, Biju Das
Add support for identifying the RZ/V2M (R9A09G011) SoC.
Note that the SoC does not have a identification register.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/soc/renesas/Kconfig | 5 +++++
drivers/soc/renesas/renesas-soc.c | 22 ++++++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index fdc99a05a7e0..19a4423490f0 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -308,6 +308,11 @@ config ARCH_R9A07G054
help
This enables support for the Renesas RZ/V2L SoC variants.
+config ARCH_R9A09G011
+ bool "ARM64 Platform support for RZ/V2M"
+ help
+ This enables support for the Renesas RZ/V2M SoC.
+
endif # ARM64
config RST_RCAR
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 92c7b42250ee..9df7bbe86381 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -68,6 +68,10 @@ static const struct renesas_family fam_rzv2l __initconst __maybe_unused = {
.name = "RZ/V2L",
};
+static const struct renesas_family fam_rzv2m __initconst __maybe_unused = {
+ .name = "RZ/V2M",
+};
+
static const struct renesas_family fam_shmobile __initconst __maybe_unused = {
.name = "SH-Mobile",
.reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
@@ -153,6 +157,10 @@ static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = {
.id = 0x8447447,
};
+static const struct renesas_soc soc_rz_v2m __initconst __maybe_unused = {
+ .family = &fam_rzv2m,
+};
+
static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
.family = &fam_rcar_gen1,
};
@@ -346,6 +354,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
#if defined(CONFIG_ARCH_R9A07G054)
{ .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l },
#endif
+#if defined(CONFIG_ARCH_R9A09G011)
+ { .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m },
+#endif
#ifdef CONFIG_ARCH_SH73A0
{ .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 },
#endif
@@ -371,6 +382,11 @@ static const struct renesas_id id_rzg2l __initconst = {
.mask = 0xfffffff,
};
+static const struct renesas_id id_rzv2m __initconst = {
+ .offset = 0x104,
+ .mask = 0xff,
+};
+
static const struct renesas_id id_prr __initconst = {
.offset = 0,
.mask = 0xff00,
@@ -380,6 +396,7 @@ static const struct of_device_id renesas_ids[] __initconst = {
{ .compatible = "renesas,bsid", .data = &id_bsid },
{ .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l },
+ { .compatible = "renesas,r9a09g011-sys", .data = &id_rzv2m },
{ .compatible = "renesas,prr", .data = &id_prr },
{ /* sentinel */ }
};
@@ -450,6 +467,11 @@ static int __init renesas_soc_init(void)
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u",
eshi);
rev_prefix = "Rev ";
+ } else if (id == &id_rzv2m) {
+ eshi = ((product >> 4) & 0x0f);
+ eslo = product & 0xf;
+ soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u.%u",
+ eshi, eslo);
}
if (soc->id &&
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 07/14] soc: renesas: Identify RZ/V2M SoC
2022-03-21 15:42 ` [PATCH 07/14] soc: renesas: Identify RZ/V2M SoC Phil Edworthy
@ 2022-04-26 14:16 ` Geert Uytterhoeven
0 siblings, 0 replies; 33+ messages in thread
From: Geert Uytterhoeven @ 2022-04-26 14:16 UTC (permalink / raw)
To: Phil Edworthy; +Cc: Magnus Damm, Linux-Renesas, Biju Das
Hi Phil,
On Mon, Mar 21, 2022 at 4:44 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> Add support for identifying the RZ/V2M (R9A09G011) SoC.
> Note that the SoC does not have a identification register.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -308,6 +308,11 @@ config ARCH_R9A07G054
> help
> This enables support for the Renesas RZ/V2L SoC variants.
>
> +config ARCH_R9A09G011
> + bool "ARM64 Platform support for RZ/V2M"
> + help
> + This enables support for the Renesas RZ/V2M SoC.
> +
> endif # ARM64
This part is superseded by "[PATCH v2 06/13] soc: renesas: Add RZ/V2M
(R9A09G011) config option".
The rest looks good to me (pending acceptance of the "sys" DT
bindings).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 08/14] clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
` (6 preceding siblings ...)
2022-03-21 15:42 ` [PATCH 07/14] soc: renesas: Identify RZ/V2M SoC Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
2022-03-21 15:42 ` [PATCH 09/14] clk: renesas: rzg2l: Make use of CLK_MON registers optional Phil Edworthy
` (5 subsequent siblings)
13 siblings, 0 replies; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: Phil Edworthy, linux-renesas-soc, linux-clk, Biju Das
All of the muxes and dividers that can be modified require the HIWORD
flags, so make the macros set them. It won't affect read only muxes and
dividers.
This will make the clock tables a little easier to read, particularly for
new SoCs coming.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 16 +++++++---------
drivers/clk/renesas/rzg2l-cpg.h | 5 +++--
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index bdfabb992a20..b187d9ac47aa 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -121,7 +121,7 @@ static const struct {
DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
- DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DIVPL3C, dtable_1_32, 0),
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
@@ -129,21 +129,20 @@ static const struct {
sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),
/* Core output clk */
- DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
- CLK_DIVIDER_HIWORD_MASK),
+ DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, 0),
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
- dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ dtable_1_32, 0),
DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
- DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DIVPL3B, dtable_1_32, 0),
DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
- DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DIVPL3A, dtable_1_32, 0),
DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,
- sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
+ sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, 0),
DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0,
@@ -152,8 +151,7 @@ static const struct {
sel_shdi, ARRAY_SIZE(sel_shdi)),
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
- DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
- CLK_DIVIDER_HIWORD_MASK),
+ DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8, 0),
},
#ifdef CONFIG_CLK_R9A07G054
.drp = {
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index ce657beaf160..592dd9515cfc 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -100,12 +100,13 @@ enum clk_types {
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
#define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \
DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
- .parent = _parent, .dtable = _dtable, .flag = _flag)
+ .parent = _parent, .dtable = _dtable, \
+ .flag = CLK_DIVIDER_HIWORD_MASK | _flag)
#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \
_mux_flags) \
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
.parent_names = _parent_names, .num_parents = _num_parents, \
- .flag = _flag, .mux_flags = _mux_flags)
+ .flag = _flag, .mux_flags = CLK_MUX_HIWORD_MASK | _mux_flags)
#define DEF_SD_MUX(_name, _id, _conf, _parent_names, _num_parents) \
DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \
.parent_names = _parent_names, .num_parents = _num_parents)
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 09/14] clk: renesas: rzg2l: Make use of CLK_MON registers optional
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
` (7 preceding siblings ...)
2022-03-21 15:42 ` [PATCH 08/14] clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
2022-03-21 15:42 ` [PATCH 10/14] clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg Phil Edworthy
` (4 subsequent siblings)
13 siblings, 0 replies; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: Phil Edworthy, linux-renesas-soc, linux-clk, Biju Das
The rz/v2m SoC doesn't use CLK_MON registers, so make it optional.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 4 ++++
drivers/clk/renesas/rzg2l-cpg.c | 25 +++++++++++++++----------
drivers/clk/renesas/rzg2l-cpg.h | 3 +++
3 files changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index b187d9ac47aa..3393754ffb5e 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -374,6 +374,8 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
/* Resets */
.resets = r9a07g044_resets,
.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
+
+ .has_clk_mon_regs = true,
};
#ifdef CONFIG_CLK_R9A07G054
@@ -396,5 +398,7 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = {
/* Resets */
.resets = r9a07g044_resets,
.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
+
+ .has_clk_mon_regs = true,
};
#endif
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 486d0656c58a..c357b0bfa119 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -498,16 +498,18 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
if (!enable)
return 0;
- for (i = 1000; i > 0; --i) {
- if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
- break;
- cpu_relax();
- }
+ if (priv->info->has_clk_mon_regs) {
+ for (i = 1000; i > 0; --i) {
+ if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
+ break;
+ cpu_relax();
+ }
- if (!i) {
- dev_err(dev, "Failed to enable CLK_ON %p\n",
- priv->base + CLK_ON_R(reg));
- return -ETIMEDOUT;
+ if (!i) {
+ dev_err(dev, "Failed to enable CLK_ON %p\n",
+ priv->base + CLK_ON_R(reg));
+ return -ETIMEDOUT;
+ }
}
return 0;
@@ -568,7 +570,10 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
if (clock->sibling)
return clock->enabled;
- value = readl(priv->base + CLK_MON_R(clock->off));
+ if (priv->info->has_clk_mon_regs)
+ value = readl(priv->base + CLK_MON_R(clock->off));
+ else
+ value = readl(priv->base + clock->off);
return value & bitmask;
}
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 592dd9515cfc..f04671376af5 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -181,6 +181,7 @@ struct rzg2l_reset {
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
* should not be disabled without a knowledgeable driver
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
+ * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
*/
struct rzg2l_cpg_info {
/* Core Clocks */
@@ -201,6 +202,8 @@ struct rzg2l_cpg_info {
/* Critical Module Clocks that should not be disabled */
const unsigned int *crit_mod_clks;
unsigned int num_crit_mod_clks;
+
+ bool has_clk_mon_regs;
};
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 10/14] clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
` (8 preceding siblings ...)
2022-03-21 15:42 ` [PATCH 09/14] clk: renesas: rzg2l: Make use of CLK_MON registers optional Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
2022-03-21 15:42 ` [PATCH 11/14] clk: renesas: Add RZ/V2M support using the rzg2l driver Phil Edworthy
` (3 subsequent siblings)
13 siblings, 0 replies; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: Phil Edworthy, linux-renesas-soc, linux-clk, Biju Das
The RZ/V2M doesn't have a matching set of reset monitor regs for each reset
reg like the RZ/G2L. Instead, it has a single CPG_RST_MON reg which has a
single bit per module.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/rzg2l-cpg.c | 6 +++++-
drivers/clk/renesas/rzg2l-cpg.h | 10 ++++++++--
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index c357b0bfa119..220955366538 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -748,8 +748,12 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->resets[id].off;
u32 bitmask = BIT(info->resets[id].bit);
+ u32 monbitmask = BIT(info->resets[id].monbit);
- return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
+ if (info->has_clk_mon_regs)
+ return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
+ else
+ return !!(readl(priv->base + CPG_RST_MON) & monbitmask);
}
static const struct reset_control_ops rzg2l_cpg_reset_ops = {
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index f04671376af5..d1d08669066b 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -18,6 +18,7 @@
#define CPG_PL3_SSEL (0x408)
#define CPG_PL6_SSEL (0x414)
#define CPG_PL6_ETH_SSEL (0x418)
+#define CPG_RST_MON (0x680)
#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)
#define CPG_CLKSTATUS_SELSDHI1_STS BIT(29)
@@ -151,17 +152,22 @@ struct rzg2l_mod_clk {
*
* @off: register offset
* @bit: reset bit
+ * @monbit: monitor bit in CPG_RST_MON register, -1 if none
*/
struct rzg2l_reset {
u16 off;
u8 bit;
+ s8 monbit;
};
-#define DEF_RST(_id, _off, _bit) \
+#define DEF_RST_MON(_id, _off, _bit, _monbit) \
[_id] = { \
.off = (_off), \
- .bit = (_bit) \
+ .bit = (_bit), \
+ .monbit = (_monbit) \
}
+#define DEF_RST(_id, _off, _bit) \
+ DEF_RST_MON(_id, _off, _bit, -1)
/**
* struct rzg2l_cpg_info - SoC-specific CPG Description
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 11/14] clk: renesas: Add RZ/V2M support using the rzg2l driver
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
` (9 preceding siblings ...)
2022-03-21 15:42 ` [PATCH 10/14] clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
2022-03-21 15:42 ` Phil Edworthy
` (2 subsequent siblings)
13 siblings, 0 replies; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: Phil Edworthy, linux-renesas-soc, linux-clk, Biju Das
The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have
any CLK_MON registers.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/Kconfig | 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a09g011-cpg.c | 164 ++++++++++++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.c | 6 +
drivers/clk/renesas/rzg2l-cpg.h | 7 ++
5 files changed, 183 insertions(+)
create mode 100644 drivers/clk/renesas/r9a09g011-cpg.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index c281f3af5716..83c5a9929936 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -35,6 +35,7 @@ config CLK_RENESAS
select CLK_R9A06G032 if ARCH_R9A06G032
select CLK_R9A07G044 if ARCH_R9A07G044
select CLK_R9A07G054 if ARCH_R9A07G054
+ select CLK_R9A09G011 if ARCH_R9A09G011
select CLK_SH73A0 if ARCH_SH73A0
if CLK_RENESAS
@@ -168,6 +169,10 @@ config CLK_R9A07G054
bool "RZ/V2L clock support" if COMPILE_TEST
select CLK_RZG2L
+config CLK_R9A09G011
+ bool "RZ/V2M clock support" if COMPILE_TEST
+ select CLK_RZG2L
+
config CLK_SH73A0
bool "SH-Mobile AG5 clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index d5e571699a30..650dbe2bb5c6 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
+obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
# Family
diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c
new file mode 100644
index 000000000000..47b93c1dec11
--- /dev/null
+++ b/drivers/clk/renesas/r9a09g011-cpg.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/V2M Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ * Based on r9a07g044-cpg.c
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/clock/r9a09g011-cpg.h>
+
+#include "rzg2l-cpg.h"
+
+#define RZV2M_SAMPLL4_CLK1 0x104
+#define RZV2M_SAMPLL4_CLK2 0x108
+
+#define PLL4_CONF (RZV2M_SAMPLL4_CLK1 << 22 | RZV2M_SAMPLL4_CLK2 << 12)
+
+#define DIV_A DDIV_PACK(0x200, 0, 3)
+#define DIV_B DDIV_PACK(0x204, 0, 2)
+#define DIV_E DDIV_PACK(0x204, 8, 1)
+#define DIV_W DDIV_PACK(0x328, 0, 3)
+
+#define SEL_B SEL_PLL_PACK(0x214, 0, 1)
+#define SEL_E SEL_PLL_PACK(0x214, 2, 1)
+#define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1)
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = 0,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_MAIN_24,
+ CLK_MAIN_2,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL2_800,
+ CLK_PLL2_400,
+ CLK_PLL2_200,
+ CLK_PLL2_100,
+ CLK_PLL4,
+ CLK_DIV_A,
+ CLK_DIV_B,
+ CLK_DIV_E,
+ CLK_DIV_W,
+ CLK_SEL_B,
+ CLK_SEL_B_D2,
+ CLK_SEL_E,
+ CLK_SEL_W0,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+/* Divider tables */
+static const struct clk_div_table dtable_diva[] = {
+ {0, 1},
+ {1, 2},
+ {2, 3},
+ {3, 4},
+ {4, 6},
+ {5, 12},
+ {6, 24},
+ {0, 0},
+};
+
+static const struct clk_div_table dtable_divb[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {0, 0},
+};
+
+static const struct clk_div_table dtable_divw[] = {
+ {0, 6},
+ {1, 7},
+ {2, 8},
+ {3, 9},
+ {4, 10},
+ {5, 11},
+ {6, 12},
+ {0, 0},
+};
+
+/* Mux clock tables */
+static const char * const sel_b[] = { ".main", ".divb" };
+static const char * const sel_e[] = { ".main", ".dive" };
+static const char * const sel_w[] = { ".main", ".divw" };
+
+static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_FIXED(".main", CLK_MAIN, CLK_EXTAL, 1, 1),
+ DEF_FIXED(".main_24", CLK_MAIN_24, CLK_MAIN, 1, 2),
+ DEF_FIXED(".main_2", CLK_MAIN_2, CLK_MAIN, 1, 24),
+ DEF_FIXED(".pll1", CLK_PLL1, CLK_MAIN_2, 498, 1),
+ DEF_FIXED(".pll2", CLK_PLL2, CLK_MAIN_2, 800, 1),
+ DEF_FIXED(".pll2_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
+ DEF_FIXED(".pll2_400", CLK_PLL2_400, CLK_PLL2_800, 1, 2),
+ DEF_FIXED(".pll2_200", CLK_PLL2_200, CLK_PLL2_800, 1, 4),
+ DEF_FIXED(".pll2_100", CLK_PLL2_100, CLK_PLL2_800, 1, 8),
+ DEF_SAMPLL(".pll4", CLK_PLL4, CLK_MAIN_2, PLL4_CONF),
+
+ DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva),
+ DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb),
+ DEF_DIV_RO(".divw", CLK_DIV_W, CLK_PLL4, DIV_W, dtable_divw),
+
+ DEF_MUX2_RO(".selb", CLK_SEL_B, SEL_B, sel_b, 0),
+ DEF_MUX2(".selw0", CLK_SEL_W0, SEL_W0, sel_w, 0, 0),
+
+ DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2),
+};
+
+static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
+ DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5),
+ DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12),
+ DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5),
+ DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0),
+};
+
+static const struct rzg2l_reset r9a09g011_resets[] = {
+ DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13),
+};
+
+static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {
+ MOD_CLK_BASE + R9A09G011_CA53_CLK,
+ MOD_CLK_BASE + R9A09G011_GIC_CLK,
+ MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK,
+};
+
+const struct rzg2l_cpg_info r9a09g011_cpg_info = {
+ /* Core Clocks */
+ .core_clks = r9a09g011_core_clks,
+ .num_core_clks = ARRAY_SIZE(r9a09g011_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r9a09g011_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r9a09g011_crit_mod_clks),
+
+ /* Module Clocks */
+ .mod_clks = r9a09g011_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r9a09g011_mod_clks),
+ .num_hw_mod_clks = R9A09G011_CA53_CLK + 1,
+
+ /* Resets */
+ .resets = r9a09g011_resets,
+ .num_resets = ARRAY_SIZE(r9a09g011_resets),
+
+ .has_clk_mon_regs = false,
+};
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 220955366538..04f2cfafe6b3 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -967,6 +967,12 @@ static const struct of_device_id rzg2l_cpg_match[] = {
.compatible = "renesas,r9a07g054-cpg",
.data = &r9a07g054_cpg_info,
},
+#endif
+#ifdef CONFIG_CLK_R9A09G011
+ {
+ .compatible = "renesas,r9a09g011-cpg",
+ .data = &r9a09g011_cpg_info,
+ },
#endif
{ /* sentinel */ }
};
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index d1d08669066b..b571d1f1c5f3 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -103,11 +103,17 @@ enum clk_types {
DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
.parent = _parent, .dtable = _dtable, \
.flag = CLK_DIVIDER_HIWORD_MASK | _flag)
+#define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \
+ DEF_DIV(_name, _id, _parent, _conf, _dtable, CLK_DIVIDER_READ_ONLY)
#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \
_mux_flags) \
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
.parent_names = _parent_names, .num_parents = _num_parents, \
.flag = _flag, .mux_flags = CLK_MUX_HIWORD_MASK | _mux_flags)
+#define DEF_MUX2(_name, _id, _conf, _parent_names, _flag, _mux_flags) \
+ DEF_MUX(_name, _id, _conf, _parent_names, 2, _flag, _mux_flags)
+#define DEF_MUX2_RO(_name, _id, _conf, _parent_names, _flag) \
+ DEF_MUX2(_name, _id, _conf, _parent_names, _flag, CLK_MUX_READ_ONLY)
#define DEF_SD_MUX(_name, _id, _conf, _parent_names, _num_parents) \
DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \
.parent_names = _parent_names, .num_parents = _num_parents)
@@ -214,5 +220,6 @@ struct rzg2l_cpg_info {
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
+extern const struct rzg2l_cpg_info r9a09g011_cpg_info;
#endif
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 12/14] arm64: defconfig: Enable Renesas RZ/V2M SoC
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
2022-03-21 15:42 ` [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration Phil Edworthy
` (12 subsequent siblings)
13 siblings, 0 replies; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Geert Uytterhoeven
Cc: Phil Edworthy, Bjorn Andersson, Shawn Guo, Krzysztof Kozlowski,
Marcel Ziswiler, Vinod Koul, Enric Balletbo i Serra,
Dmitry Baryshkov, linux-renesas-soc, linux-arm-kernel, Biju Das
Enable the Renesas RZ/V2M SoC and the uart it uses.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 813e644b6af1..cc8196c48029 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -428,6 +428,7 @@ CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_OMAP=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_UNIPHIER=y
+CONFIG_SERIAL_8250_EM=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
@@ -1106,6 +1107,7 @@ CONFIG_ARCH_R8A774E1=y
CONFIG_ARCH_R8A774A1=y
CONFIG_ARCH_R8A774B1=y
CONFIG_ARCH_R9A07G044=y
+CONFIG_ARCH_R9A09G011=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ARCH_TEGRA_132_SOC=y
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 12/14] arm64: defconfig: Enable Renesas RZ/V2M SoC
@ 2022-03-21 15:42 ` Phil Edworthy
0 siblings, 0 replies; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Geert Uytterhoeven
Cc: Phil Edworthy, Bjorn Andersson, Shawn Guo, Krzysztof Kozlowski,
Marcel Ziswiler, Vinod Koul, Enric Balletbo i Serra,
Dmitry Baryshkov, linux-renesas-soc, linux-arm-kernel, Biju Das
Enable the Renesas RZ/V2M SoC and the uart it uses.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 813e644b6af1..cc8196c48029 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -428,6 +428,7 @@ CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_OMAP=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_UNIPHIER=y
+CONFIG_SERIAL_8250_EM=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
@@ -1106,6 +1107,7 @@ CONFIG_ARCH_R8A774E1=y
CONFIG_ARCH_R8A774A1=y
CONFIG_ARCH_R8A774B1=y
CONFIG_ARCH_R9A07G044=y
+CONFIG_ARCH_R9A09G011=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ARCH_TEGRA_132_SOC=y
--
2.32.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH 12/14] arm64: defconfig: Enable Renesas RZ/V2M SoC
2022-03-21 15:42 ` Phil Edworthy
@ 2022-03-21 15:57 ` Marcel Ziswiler
-1 siblings, 0 replies; 33+ messages in thread
From: Marcel Ziswiler @ 2022-03-21 15:57 UTC (permalink / raw)
To: will, catalin.marinas, phil.edworthy, geert+renesas
Cc: vkoul, enric.balletbo, dmitry.baryshkov, krzk, biju.das.jz,
linux-renesas-soc, shawnguo, linux-arm-kernel, bjorn.andersson
On Mon, 2022-03-21 at 15:42 +0000, Phil Edworthy wrote:
> Enable the Renesas RZ/V2M SoC and the uart it uses.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
> arch/arm64/configs/defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 813e644b6af1..cc8196c48029 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -428,6 +428,7 @@ CONFIG_SERIAL_8250_DW=y
> CONFIG_SERIAL_8250_OMAP=y
> CONFIG_SERIAL_8250_MT6577=y
> CONFIG_SERIAL_8250_UNIPHIER=y
> +CONFIG_SERIAL_8250_EM=y
> CONFIG_SERIAL_OF_PLATFORM=y
> CONFIG_SERIAL_AMBA_PL011=y
> CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
> @@ -1106,6 +1107,7 @@ CONFIG_ARCH_R8A774E1=y
> CONFIG_ARCH_R8A774A1=y
> CONFIG_ARCH_R8A774B1=y
> CONFIG_ARCH_R9A07G044=y
> +CONFIG_ARCH_R9A09G011=y
> CONFIG_ROCKCHIP_IODOMAIN=y
> CONFIG_ROCKCHIP_PM_DOMAINS=y
> CONFIG_ARCH_TEGRA_132_SOC=y
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 12/14] arm64: defconfig: Enable Renesas RZ/V2M SoC
@ 2022-03-21 15:57 ` Marcel Ziswiler
0 siblings, 0 replies; 33+ messages in thread
From: Marcel Ziswiler @ 2022-03-21 15:57 UTC (permalink / raw)
To: will, catalin.marinas, phil.edworthy, geert+renesas
Cc: vkoul, enric.balletbo, dmitry.baryshkov, krzk, biju.das.jz,
linux-renesas-soc, shawnguo, linux-arm-kernel, bjorn.andersson
On Mon, 2022-03-21 at 15:42 +0000, Phil Edworthy wrote:
> Enable the Renesas RZ/V2M SoC and the uart it uses.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
> arch/arm64/configs/defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 813e644b6af1..cc8196c48029 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -428,6 +428,7 @@ CONFIG_SERIAL_8250_DW=y
> CONFIG_SERIAL_8250_OMAP=y
> CONFIG_SERIAL_8250_MT6577=y
> CONFIG_SERIAL_8250_UNIPHIER=y
> +CONFIG_SERIAL_8250_EM=y
> CONFIG_SERIAL_OF_PLATFORM=y
> CONFIG_SERIAL_AMBA_PL011=y
> CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
> @@ -1106,6 +1107,7 @@ CONFIG_ARCH_R8A774E1=y
> CONFIG_ARCH_R8A774A1=y
> CONFIG_ARCH_R8A774B1=y
> CONFIG_ARCH_R9A07G044=y
> +CONFIG_ARCH_R9A09G011=y
> CONFIG_ROCKCHIP_IODOMAIN=y
> CONFIG_ROCKCHIP_PM_DOMAINS=y
> CONFIG_ARCH_TEGRA_132_SOC=y
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 13/14] arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
` (11 preceding siblings ...)
2022-03-21 15:42 ` Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
2022-03-21 15:42 ` [PATCH 14/14] arm64: dts: renesas: Add initial device tree for RZ/V2M EVK Phil Edworthy
13 siblings, 0 replies; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski
Cc: Phil Edworthy, linux-renesas-soc, devicetree, Biju Das
Details of the SoC can be found here:
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 99 ++++++++++++++++++++++
1 file changed, 99 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a09g011.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
new file mode 100644
index 000000000000..fe1f5107351f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2M SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a09g011-cpg.h>
+
+/ {
+ compatible = "renesas,r9a09g011";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0>;
+ device_type = "cpu";
+ clocks = <&cpg CPG_CORE R9A09G011_CA53_CLK>;
+ };
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@82000000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x82010000 0 0x1000>,
+ <0x0 0x82020000 0 0x20000>,
+ <0x0 0x82040000 0 0x20000>,
+ <0x0 0x82060000 0 0x20000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ cpg: clock-controller@a3500000 {
+ compatible = "renesas,r9a09g011-cpg";
+ reg = <0 0xa3500000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sys: system-configuration@a3f03000 {
+ compatible = "renesas,r9a09g011-sys";
+ reg = <0 0xa3f03000 0 0x400>;
+ status = "disabled";
+ };
+
+ uart0: serial@a4040000 {
+ compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
+ reg = <0 0xa4040000 0 0x38>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>;
+ clock-names = "sclk";
+ status = "disabled";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ clocks = <&cpg CPG_MOD R9A09G011_SYC_CNT_CLK>;
+ clock-names = "clk";
+ resets = <&cpg R9A09G011_SYC_RST_N>;
+ };
+};
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 14/14] arm64: dts: renesas: Add initial device tree for RZ/V2M EVK
2022-03-21 15:42 [PATCH 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
` (12 preceding siblings ...)
2022-03-21 15:42 ` [PATCH 13/14] arm64: dts: renesas: Add initial DTSI for " Phil Edworthy
@ 2022-03-21 15:42 ` Phil Edworthy
13 siblings, 0 replies; 33+ messages in thread
From: Phil Edworthy @ 2022-03-21 15:42 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski
Cc: Phil Edworthy, linux-renesas-soc, devicetree, Biju Das
Add basic support for RZ/V2M EVK (based on R9A09G011):
- memory
- External input clock
- UART
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/Makefile | 2 +
.../boot/dts/renesas/r9a09g011-v2mevk2.dts | 45 +++++++++++++++++++
2 files changed, 47 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index d000f6b131dc..06ba849d3db3 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -79,3 +79,5 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
+
+dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
new file mode 100644
index 000000000000..90172de7851f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g011.dtsi"
+
+/ {
+ model = "RZ/V2M Evaluation Kit 2.0";
+ compatible = "renesas,rzv2mevk2", "renesas,r9a09g011";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@58000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x58000000 0x0 0x28000000>;
+ };
+
+ memory@180000000 {
+ device_type = "memory";
+ reg = <0x1 0x80000000 0x0 0x80000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <48000000>;
+};
+
+&sys {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.32.0
^ permalink raw reply related [flat|nested] 33+ messages in thread