[PATCH 0/3] spi: tegra quad: Add Tegra Grace features

[PATCH 0/3] spi: tegra quad: Add Tegra Grace features

[Krishna Yarlagadda]

Add multiple chip selects and hardware wait state polling supported
by Tegra Grace.

Krishna Yarlagadda (3):
  spi: tegra210-quad: Multi-cs support
  spi: tegra210-quad: Add wait polling support
  spi: dt-bindings: Add wait state polling flag

 .../bindings/spi/nvidia,tegra210-quad.yaml    |  6 ++
 drivers/spi/spi-tegra210-quad.c               | 64 ++++++++++++++++++-
 2 files changed, 68 insertions(+), 2 deletions(-)

-- 
2.17.1

[PATCH 1/3] spi: tegra210-quad: Multi-cs support

[Krishna Yarlagadda]

Tegra Grace and later chips can support upto 4 chip select lines
for QUAD SPI. Added new compatible for Tegra Grace.

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
 drivers/spi/spi-tegra210-quad.c | 33 +++++++++++++++++++++++++++++++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
index 66f647f32876..a2e225e8f7f0 100644
--- a/drivers/spi/spi-tegra210-quad.c
+++ b/drivers/spi/spi-tegra210-quad.c
@@ -37,6 +37,16 @@
 #define QSPI_RX_EN				BIT(12)
 #define QSPI_CS_SW_VAL				BIT(20)
 #define QSPI_CS_SW_HW				BIT(21)
+
+#define QSPI_CS_POL_INACTIVE(n)			(1 << (22 + (n)))
+#define QSPI_CS_POL_INACTIVE_MASK		(0xF << 22)
+#define QSPI_CS_SEL_0				(0 << 26)
+#define QSPI_CS_SEL_1				(1 << 26)
+#define QSPI_CS_SEL_2				(2 << 26)
+#define QSPI_CS_SEL_3				(3 << 26)
+#define QSPI_CS_SEL_MASK			(3 << 26)
+#define QSPI_CS_SEL(x)				(((x) & 0x3) << 26)
+
 #define QSPI_CONTROL_MODE_0			(0 << 28)
 #define QSPI_CONTROL_MODE_3			(3 << 28)
 #define QSPI_CONTROL_MODE_MASK			(3 << 28)
@@ -154,6 +164,7 @@
 struct tegra_qspi_soc_data {
 	bool has_dma;
 	bool cmb_xfer_capable;
+	bool cs_count;
 };
 
 struct tegra_qspi_client_data {
@@ -812,6 +823,7 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran
 		tegra_qspi_mask_clear_irq(tqspi);
 
 		command1 = tqspi->def_command1_reg;
+		command1 |= QSPI_CS_SEL(spi->chip_select);
 		command1 |= QSPI_BIT_LENGTH(bits_per_word - 1);
 
 		command1 &= ~QSPI_CONTROL_MODE_MASK;
@@ -941,10 +953,11 @@ static int tegra_qspi_setup(struct spi_device *spi)
 
 	/* keep default cs state to inactive */
 	val = tqspi->def_command1_reg;
+	val |= QSPI_CS_SEL(spi->chip_select);
 	if (spi->mode & SPI_CS_HIGH)
-		val &= ~QSPI_CS_SW_VAL;
+		val &= ~QSPI_CS_POL_INACTIVE(spi->chip_select);
 	else
-		val |= QSPI_CS_SW_VAL;
+		val |= QSPI_CS_POL_INACTIVE(spi->chip_select);
 
 	tqspi->def_command1_reg = val;
 	tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
@@ -1425,16 +1438,25 @@ static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data)
 static struct tegra_qspi_soc_data tegra210_qspi_soc_data = {
 	.has_dma = true,
 	.cmb_xfer_capable = false,
+	.cs_count = 1,
 };
 
 static struct tegra_qspi_soc_data tegra186_qspi_soc_data = {
 	.has_dma = true,
 	.cmb_xfer_capable = true,
+	.cs_count = 1,
 };
 
 static struct tegra_qspi_soc_data tegra234_qspi_soc_data = {
 	.has_dma = false,
 	.cmb_xfer_capable = true,
+	.cs_count = 1,
+};
+
+static struct tegra_qspi_soc_data tegra_grace_qspi_soc_data = {
+	.has_dma = false,
+	.cmb_xfer_capable = true,
+	.cs_count = 4,
 };
 
 static const struct of_device_id tegra_qspi_of_match[] = {
@@ -1450,6 +1472,9 @@ static const struct of_device_id tegra_qspi_of_match[] = {
 	}, {
 		.compatible = "nvidia,tegra234-qspi",
 		.data	    = &tegra234_qspi_soc_data,
+	}, {
+		.compatible = "nvidia,tegra-grace-qspi",
+		.data	    = &tegra_grace_qspi_soc_data,
 	},
 	{}
 };
@@ -1467,6 +1492,9 @@ static const struct acpi_device_id tegra_qspi_acpi_match[] = {
 	}, {
 		.id = "NVDA1413",
 		.driver_data = (kernel_ulong_t)&tegra234_qspi_soc_data,
+	}, {
+		.id = "NVDA1513",
+		.driver_data = (kernel_ulong_t)&th500_qspi_soc_data,
 	},
 	{}
 };
@@ -1506,6 +1534,7 @@ static int tegra_qspi_probe(struct platform_device *pdev)
 	spin_lock_init(&tqspi->lock);
 
 	tqspi->soc_data = device_get_match_data(&pdev->dev);
+	master->num_chipselect = tqspi->soc_data->cs_count;
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	tqspi->base = devm_ioremap_resource(&pdev->dev, r);
 	if (IS_ERR(tqspi->base))
-- 
2.17.1

[PATCH 2/3] spi: tegra210-quad: Add wait polling support

[Krishna Yarlagadda]

Controller can poll for wait state inserted by TPM device and
handle it.

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
 drivers/spi/spi-tegra210-quad.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
index a2e225e8f7f0..ecf171bfcdce 100644
--- a/drivers/spi/spi-tegra210-quad.c
+++ b/drivers/spi/spi-tegra210-quad.c
@@ -142,6 +142,7 @@
 
 #define QSPI_GLOBAL_CONFIG			0X1a4
 #define QSPI_CMB_SEQ_EN				BIT(0)
+#define QSPI_TPM_WAIT_POLL_EN			BIT(1)
 
 #define QSPI_CMB_SEQ_ADDR			0x1a8
 #define QSPI_ADDRESS_VALUE_SET(X)		(((x) & 0xFFFF) << 0)
@@ -165,11 +166,13 @@ struct tegra_qspi_soc_data {
 	bool has_dma;
 	bool cmb_xfer_capable;
 	bool cs_count;
+	bool has_wait_polling;
 };
 
 struct tegra_qspi_client_data {
 	int tx_clk_tap_delay;
 	int rx_clk_tap_delay;
+	bool wait_polling;
 };
 
 struct tegra_qspi {
@@ -833,6 +836,11 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran
 		else
 			command1 |= QSPI_CONTROL_MODE_0;
 
+		if (tqspi->soc_data->cmb_xfer_capable)
+			command1 &= ~QSPI_CS_SW_HW;
+		else
+			command1 |= QSPI_CS_SW_HW;
+
 		if (spi->mode & SPI_CS_HIGH)
 			command1 |= QSPI_CS_SW_VAL;
 		else
@@ -917,6 +925,7 @@ static int tegra_qspi_start_transfer_one(struct spi_device *spi,
 
 static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_device *spi)
 {
+	struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
 	struct tegra_qspi_client_data *cdata;
 
 	cdata = devm_kzalloc(&spi->dev, sizeof(*cdata), GFP_KERNEL);
@@ -927,6 +936,11 @@ static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_devic
 				 &cdata->tx_clk_tap_delay);
 	device_property_read_u32(&spi->dev, "nvidia,rx-clk-tap-delay",
 				 &cdata->rx_clk_tap_delay);
+	if (tqspi->soc_data->has_wait_polling)
+		cdata->wait_polling = device_property_read_bool
+					(&spi->dev,
+					 "nvidia,wait-polling");
+
 
 	return cdata;
 }
@@ -1049,6 +1063,7 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
 	bool is_first_msg = true;
 	struct spi_transfer *xfer;
 	struct spi_device *spi = msg->spi;
+	struct tegra_qspi_client_data *cdata = spi->controller_data;
 	u8 transfer_phase = 0;
 	u32 cmd1 = 0, dma_ctl = 0;
 	int ret = 0;
@@ -1059,6 +1074,10 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
 	/* Enable Combined sequence mode */
 	val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
 	val |= QSPI_CMB_SEQ_EN;
+	if (cdata->wait_polling)
+		val |= QSPI_TPM_WAIT_POLL_EN;
+	else
+		val &= ~QSPI_TPM_WAIT_POLL_EN;
 	tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
 	/* Process individual transfer list */
 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
@@ -1158,6 +1177,8 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
 		transfer_phase++;
 	}
 
+	ret = 0;
+
 exit:
 	msg->status = ret;
 
@@ -1180,6 +1201,7 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi,
 	/* Disable Combined sequence mode */
 	val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
 	val &= ~QSPI_CMB_SEQ_EN;
+	val &= ~QSPI_TPM_WAIT_POLL_EN;
 	tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
 	list_for_each_entry(transfer, &msg->transfers, transfer_list) {
 		struct spi_transfer *xfer = transfer;
@@ -1439,24 +1461,28 @@ static struct tegra_qspi_soc_data tegra210_qspi_soc_data = {
 	.has_dma = true,
 	.cmb_xfer_capable = false,
 	.cs_count = 1,
+	.has_wait_polling = false,
 };
 
 static struct tegra_qspi_soc_data tegra186_qspi_soc_data = {
 	.has_dma = true,
 	.cmb_xfer_capable = true,
 	.cs_count = 1,
+	.has_wait_polling = false,
 };
 
 static struct tegra_qspi_soc_data tegra234_qspi_soc_data = {
 	.has_dma = false,
 	.cmb_xfer_capable = true,
 	.cs_count = 1,
+	.has_wait_polling = true,
 };
 
 static struct tegra_qspi_soc_data tegra_grace_qspi_soc_data = {
 	.has_dma = false,
 	.cmb_xfer_capable = true,
 	.cs_count = 4,
+	.has_wait_polling = true,
 };
 
 static const struct of_device_id tegra_qspi_of_match[] = {
@@ -1509,6 +1535,7 @@ static int tegra_qspi_probe(struct platform_device *pdev)
 	struct resource		*r;
 	int ret, qspi_irq;
 	int bus_num;
+	u8 val = 0;
 
 	master = devm_spi_alloc_master(&pdev->dev, sizeof(*tqspi));
 	if (!master)
@@ -1585,6 +1612,10 @@ static int tegra_qspi_probe(struct platform_device *pdev)
 	tqspi->spi_cs_timing1 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING1);
 	tqspi->spi_cs_timing2 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING2);
 	tqspi->def_command2_reg = tegra_qspi_readl(tqspi, QSPI_COMMAND2);
+	val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
+	val &= ~QSPI_CMB_SEQ_EN;
+	val &= ~QSPI_TPM_WAIT_POLL_EN;
+	tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
 
 	pm_runtime_put(&pdev->dev);
 
-- 
2.17.1

[PATCH 3/3] spi: dt-bindings: Add wait state polling flag

[Krishna Yarlagadda]

Add flag to enable tpm wait state polling and Tegra Grace binding.

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
 .../devicetree/bindings/spi/nvidia,tegra210-quad.yaml       | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
index 0296edd1de22..88b00fcad210 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
@@ -20,6 +20,7 @@ properties:
       - nvidia,tegra186-qspi
       - nvidia,tegra194-qspi
       - nvidia,tegra234-qspi
+      - nvidia,tegra-grace-qspi
 
   reg:
     maxItems: 1
@@ -57,6 +58,11 @@ patternProperties:
       spi-tx-bus-width:
         enum: [1, 2, 4]
 
+      nvidia,wait-polling:
+        description:
+          Enable TPM wait state polling on supported chips.
+	type: boolean
+
       nvidia,tx-clk-tap-delay:
         description:
           Delays the clock going out to device with this tap value.
-- 
2.17.1

Re: [PATCH 3/3] spi: dt-bindings: Add wait state polling flag

[Mikko Perttunen]

On 3/17/22 03:20, Krishna Yarlagadda wrote:
> Add flag to enable tpm wait state polling and Tegra Grace binding.
> 
> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> ---
>   .../devicetree/bindings/spi/nvidia,tegra210-quad.yaml       | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> index 0296edd1de22..88b00fcad210 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> @@ -20,6 +20,7 @@ properties:
>         - nvidia,tegra186-qspi
>         - nvidia,tegra194-qspi
>         - nvidia,tegra234-qspi
> +      - nvidia,tegra-grace-qspi

nvidia,tegra241-qspi. Similarly in other places that refer to the chip name.

Mikko

>   
>     reg:
>       maxItems: 1
> @@ -57,6 +58,11 @@ patternProperties:
>         spi-tx-bus-width:
>           enum: [1, 2, 4]
>   
> +      nvidia,wait-polling:
> +        description:
> +          Enable TPM wait state polling on supported chips.
> +	type: boolean
> +
>         nvidia,tx-clk-tap-delay:
>           description:
>             Delays the clock going out to device with this tap value.

Re: [PATCH 2/3] spi: tegra210-quad: Add wait polling support

[Jon Hunter]

On 17/03/2022 01:20, Krishna Yarlagadda wrote:
> Controller can poll for wait state inserted by TPM device and
> handle it.
> 
> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> ---
>   drivers/spi/spi-tegra210-quad.c | 31 +++++++++++++++++++++++++++++++
>   1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
> index a2e225e8f7f0..ecf171bfcdce 100644
> --- a/drivers/spi/spi-tegra210-quad.c
> +++ b/drivers/spi/spi-tegra210-quad.c
> @@ -142,6 +142,7 @@
>   
>   #define QSPI_GLOBAL_CONFIG			0X1a4
>   #define QSPI_CMB_SEQ_EN				BIT(0)
> +#define QSPI_TPM_WAIT_POLL_EN			BIT(1)
>   
>   #define QSPI_CMB_SEQ_ADDR			0x1a8
>   #define QSPI_ADDRESS_VALUE_SET(X)		(((x) & 0xFFFF) << 0)
> @@ -165,11 +166,13 @@ struct tegra_qspi_soc_data {
>   	bool has_dma;
>   	bool cmb_xfer_capable;
>   	bool cs_count;
> +	bool has_wait_polling;
>   };
>   
>   struct tegra_qspi_client_data {
>   	int tx_clk_tap_delay;
>   	int rx_clk_tap_delay;
> +	bool wait_polling;
>   };
>   
>   struct tegra_qspi {
> @@ -833,6 +836,11 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran
>   		else
>   			command1 |= QSPI_CONTROL_MODE_0;
>   
> +		if (tqspi->soc_data->cmb_xfer_capable)
> +			command1 &= ~QSPI_CS_SW_HW;
> +		else
> +			command1 |= QSPI_CS_SW_HW;
> +
>   		if (spi->mode & SPI_CS_HIGH)
>   			command1 |= QSPI_CS_SW_VAL;
>   		else
> @@ -917,6 +925,7 @@ static int tegra_qspi_start_transfer_one(struct spi_device *spi,
>   
>   static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_device *spi)
>   {
> +	struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
>   	struct tegra_qspi_client_data *cdata;
>   
>   	cdata = devm_kzalloc(&spi->dev, sizeof(*cdata), GFP_KERNEL);
> @@ -927,6 +936,11 @@ static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_devic
>   				 &cdata->tx_clk_tap_delay);
>   	device_property_read_u32(&spi->dev, "nvidia,rx-clk-tap-delay",
>   				 &cdata->rx_clk_tap_delay);
> +	if (tqspi->soc_data->has_wait_polling)
> +		cdata->wait_polling = device_property_read_bool
> +					(&spi->dev,
> +					 "nvidia,wait-polling");
> +


This looks odd. Why do we need this device-tree property if it is 
already specified in the SoC data?

Jon

-- 
nvpublic

RE: [PATCH 2/3] spi: tegra210-quad: Add wait polling support

[Krishna Yarlagadda]

> -----Original Message-----
> From: Jonathan Hunter <jonathanh@nvidia.com>
> Sent: 17 March 2022 14:25
> To: Krishna Yarlagadda <kyarlagadda@nvidia.com>; broonie@kernel.org; thierry.reding@gmail.com; linux-spi@vger.kernel.org; linux-
> tegra@vger.kernel.org; Ashish Singhal <ashishsingha@nvidia.com>
> Cc: Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan <ldewangan@nvidia.com>; robh+dt@kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 2/3] spi: tegra210-quad: Add wait polling support
> 
> 
> On 17/03/2022 01:20, Krishna Yarlagadda wrote:
> > Controller can poll for wait state inserted by TPM device and
> > handle it.
> >
> > Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> > ---
> >   drivers/spi/spi-tegra210-quad.c | 31 +++++++++++++++++++++++++++++++
> >   1 file changed, 31 insertions(+)
> >
> > diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
> > index a2e225e8f7f0..ecf171bfcdce 100644
> > --- a/drivers/spi/spi-tegra210-quad.c
> > +++ b/drivers/spi/spi-tegra210-quad.c
> > @@ -142,6 +142,7 @@
> >
> >   #define QSPI_GLOBAL_CONFIG			0X1a4
> >   #define QSPI_CMB_SEQ_EN				BIT(0)
> > +#define QSPI_TPM_WAIT_POLL_EN			BIT(1)
> >
> >   #define QSPI_CMB_SEQ_ADDR			0x1a8
> >   #define QSPI_ADDRESS_VALUE_SET(X)		(((x) & 0xFFFF) << 0)
> > @@ -165,11 +166,13 @@ struct tegra_qspi_soc_data {
> >   	bool has_dma;
> >   	bool cmb_xfer_capable;
> >   	bool cs_count;
> > +	bool has_wait_polling;
> >   };
> >
> >   struct tegra_qspi_client_data {
> >   	int tx_clk_tap_delay;
> >   	int rx_clk_tap_delay;
> > +	bool wait_polling;
> >   };
> >
> >   struct tegra_qspi {
> > @@ -833,6 +836,11 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran
> >   		else
> >   			command1 |= QSPI_CONTROL_MODE_0;
> >
> > +		if (tqspi->soc_data->cmb_xfer_capable)
> > +			command1 &= ~QSPI_CS_SW_HW;
> > +		else
> > +			command1 |= QSPI_CS_SW_HW;
> > +
> >   		if (spi->mode & SPI_CS_HIGH)
> >   			command1 |= QSPI_CS_SW_VAL;
> >   		else
> > @@ -917,6 +925,7 @@ static int tegra_qspi_start_transfer_one(struct spi_device *spi,
> >
> >   static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_device *spi)
> >   {
> > +	struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
> >   	struct tegra_qspi_client_data *cdata;
> >
> >   	cdata = devm_kzalloc(&spi->dev, sizeof(*cdata), GFP_KERNEL);
> > @@ -927,6 +936,11 @@ static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_devic
> >   				 &cdata->tx_clk_tap_delay);
> >   	device_property_read_u32(&spi->dev, "nvidia,rx-clk-tap-delay",
> >   				 &cdata->rx_clk_tap_delay);
> > +	if (tqspi->soc_data->has_wait_polling)
> > +		cdata->wait_polling = device_property_read_bool
> > +					(&spi->dev,
> > +					 "nvidia,wait-polling");
> > +
> 
> 
> This looks odd. Why do we need this device-tree property if it is
> already specified in the SoC data?
Soc data specifies chip is capable of wait-polling.
Wait polling still has to be selected on slave devices that can support it.
I will add one line description for the properties in next version.
> 
> Jon
> 
> --
> nvpublic

RE: [PATCH 3/3] spi: dt-bindings: Add wait state polling flag

[Krishna Yarlagadda]

> -----Original Message-----
> From: Mikko Perttunen <cyndis@kapsi.fi>
> Sent: 17 March 2022 14:13
> To: Krishna Yarlagadda <kyarlagadda@nvidia.com>; broonie@kernel.org; thierry.reding@gmail.com; Jonathan Hunter
> <jonathanh@nvidia.com>; linux-spi@vger.kernel.org; linux-tegra@vger.kernel.org; Ashish Singhal <ashishsingha@nvidia.com>
> Cc: Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan <ldewangan@nvidia.com>; robh+dt@kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 3/3] spi: dt-bindings: Add wait state polling flag
> 
> External email: Use caution opening links or attachments
> 
> 
> On 3/17/22 03:20, Krishna Yarlagadda wrote:
> > Add flag to enable tpm wait state polling and Tegra Grace binding.
> >
> > Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> > ---
> >   .../devicetree/bindings/spi/nvidia,tegra210-quad.yaml       | 6 ++++++
> >   1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> > index 0296edd1de22..88b00fcad210 100644
> > --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> > +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> > @@ -20,6 +20,7 @@ properties:
> >         - nvidia,tegra186-qspi
> >         - nvidia,tegra194-qspi
> >         - nvidia,tegra234-qspi
> > +      - nvidia,tegra-grace-qspi
> 
> nvidia,tegra241-qspi. Similarly in other places that refer to the chip name.
Agree. Will change it to be consistent with rest of the chip patches.
> 
> Mikko
> 
> >
> >     reg:
> >       maxItems: 1
> > @@ -57,6 +58,11 @@ patternProperties:
> >         spi-tx-bus-width:
> >           enum: [1, 2, 4]
> >
> > +      nvidia,wait-polling:
> > +        description:
> > +          Enable TPM wait state polling on supported chips.
> > +     type: boolean
> > +
> >         nvidia,tx-clk-tap-delay:
> >           description:
> >             Delays the clock going out to device with this tap value.

Re: [PATCH 2/3] spi: tegra210-quad: Add wait polling support

[Jon Hunter]

On 17/03/2022 01:20, Krishna Yarlagadda wrote:
> Controller can poll for wait state inserted by TPM device and
> handle it.
> 
> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> ---
>   drivers/spi/spi-tegra210-quad.c | 31 +++++++++++++++++++++++++++++++
>   1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
> index a2e225e8f7f0..ecf171bfcdce 100644
> --- a/drivers/spi/spi-tegra210-quad.c
> +++ b/drivers/spi/spi-tegra210-quad.c
> @@ -142,6 +142,7 @@
>   
>   #define QSPI_GLOBAL_CONFIG			0X1a4
>   #define QSPI_CMB_SEQ_EN				BIT(0)
> +#define QSPI_TPM_WAIT_POLL_EN			BIT(1)
>   
>   #define QSPI_CMB_SEQ_ADDR			0x1a8
>   #define QSPI_ADDRESS_VALUE_SET(X)		(((x) & 0xFFFF) << 0)
> @@ -165,11 +166,13 @@ struct tegra_qspi_soc_data {
>   	bool has_dma;
>   	bool cmb_xfer_capable;
>   	bool cs_count;
> +	bool has_wait_polling;
>   };
>   
>   struct tegra_qspi_client_data {
>   	int tx_clk_tap_delay;
>   	int rx_clk_tap_delay;
> +	bool wait_polling;
>   };
>   
>   struct tegra_qspi {
> @@ -833,6 +836,11 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran
>   		else
>   			command1 |= QSPI_CONTROL_MODE_0;
>   
> +		if (tqspi->soc_data->cmb_xfer_capable)
> +			command1 &= ~QSPI_CS_SW_HW;
> +		else
> +			command1 |= QSPI_CS_SW_HW;
> +
>   		if (spi->mode & SPI_CS_HIGH)
>   			command1 |= QSPI_CS_SW_VAL;
>   		else
> @@ -917,6 +925,7 @@ static int tegra_qspi_start_transfer_one(struct spi_device *spi,
>   
>   static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_device *spi)
>   {
> +	struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
>   	struct tegra_qspi_client_data *cdata;
>   
>   	cdata = devm_kzalloc(&spi->dev, sizeof(*cdata), GFP_KERNEL);
> @@ -927,6 +936,11 @@ static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_devic
>   				 &cdata->tx_clk_tap_delay);
>   	device_property_read_u32(&spi->dev, "nvidia,rx-clk-tap-delay",
>   				 &cdata->rx_clk_tap_delay);
> +	if (tqspi->soc_data->has_wait_polling)
> +		cdata->wait_polling = device_property_read_bool
> +					(&spi->dev,
> +					 "nvidia,wait-polling");
> +
>   
>   	return cdata;
>   }
> @@ -1049,6 +1063,7 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
>   	bool is_first_msg = true;
>   	struct spi_transfer *xfer;
>   	struct spi_device *spi = msg->spi;
> +	struct tegra_qspi_client_data *cdata = spi->controller_data;
>   	u8 transfer_phase = 0;
>   	u32 cmd1 = 0, dma_ctl = 0;
>   	int ret = 0;
> @@ -1059,6 +1074,10 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
>   	/* Enable Combined sequence mode */
>   	val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
>   	val |= QSPI_CMB_SEQ_EN;
> +	if (cdata->wait_polling)
> +		val |= QSPI_TPM_WAIT_POLL_EN;
> +	else
> +		val &= ~QSPI_TPM_WAIT_POLL_EN;
>   	tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
>   	/* Process individual transfer list */
>   	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
> @@ -1158,6 +1177,8 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
>   		transfer_phase++;
>   	}
>   
> +	ret = 0;
> +
>   exit:
>   	msg->status = ret;
>   
> @@ -1180,6 +1201,7 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi,
>   	/* Disable Combined sequence mode */
>   	val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
>   	val &= ~QSPI_CMB_SEQ_EN;
> +	val &= ~QSPI_TPM_WAIT_POLL_EN;
>   	tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
>   	list_for_each_entry(transfer, &msg->transfers, transfer_list) {
>   		struct spi_transfer *xfer = transfer;
> @@ -1439,24 +1461,28 @@ static struct tegra_qspi_soc_data tegra210_qspi_soc_data = {
>   	.has_dma = true,
>   	.cmb_xfer_capable = false,
>   	.cs_count = 1,
> +	.has_wait_polling = false,
>   };
>   
>   static struct tegra_qspi_soc_data tegra186_qspi_soc_data = {
>   	.has_dma = true,
>   	.cmb_xfer_capable = true,
>   	.cs_count = 1,
> +	.has_wait_polling = false,
>   };
>   
>   static struct tegra_qspi_soc_data tegra234_qspi_soc_data = {
>   	.has_dma = false,
>   	.cmb_xfer_capable = true,
>   	.cs_count = 1,
> +	.has_wait_polling = true,
>   };
>   
>   static struct tegra_qspi_soc_data tegra_grace_qspi_soc_data = {
>   	.has_dma = false,
>   	.cmb_xfer_capable = true,
>   	.cs_count = 4,
> +	.has_wait_polling = true,
>   };
>   
>   static const struct of_device_id tegra_qspi_of_match[] = {
> @@ -1509,6 +1535,7 @@ static int tegra_qspi_probe(struct platform_device *pdev)
>   	struct resource		*r;
>   	int ret, qspi_irq;
>   	int bus_num;
> +	u8 val = 0;
>   
>   	master = devm_spi_alloc_master(&pdev->dev, sizeof(*tqspi));
>   	if (!master)
> @@ -1585,6 +1612,10 @@ static int tegra_qspi_probe(struct platform_device *pdev)
>   	tqspi->spi_cs_timing1 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING1);
>   	tqspi->spi_cs_timing2 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING2);
>   	tqspi->def_command2_reg = tegra_qspi_readl(tqspi, QSPI_COMMAND2);
> +	val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
> +	val &= ~QSPI_CMB_SEQ_EN;
> +	val &= ~QSPI_TPM_WAIT_POLL_EN;

Don't we need to check here is the device support this TPM_WAIT_POLL?

Jon

-- 
nvpublic

Re: [PATCH 2/3] spi: tegra210-quad: Add wait polling support

[Jon Hunter]

On 17/03/2022 09:02, Krishna Yarlagadda wrote:
>> -----Original Message-----
>> From: Jonathan Hunter <jonathanh@nvidia.com>
>> Sent: 17 March 2022 14:25
>> To: Krishna Yarlagadda <kyarlagadda@nvidia.com>; broonie@kernel.org; thierry.reding@gmail.com; linux-spi@vger.kernel.org; linux-
>> tegra@vger.kernel.org; Ashish Singhal <ashishsingha@nvidia.com>
>> Cc: Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan <ldewangan@nvidia.com>; robh+dt@kernel.org;
>> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH 2/3] spi: tegra210-quad: Add wait polling support
>>
>>
>> On 17/03/2022 01:20, Krishna Yarlagadda wrote:
>>> Controller can poll for wait state inserted by TPM device and
>>> handle it.
>>>
>>> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
>>> ---
>>>    drivers/spi/spi-tegra210-quad.c | 31 +++++++++++++++++++++++++++++++
>>>    1 file changed, 31 insertions(+)
>>>
>>> diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
>>> index a2e225e8f7f0..ecf171bfcdce 100644
>>> --- a/drivers/spi/spi-tegra210-quad.c
>>> +++ b/drivers/spi/spi-tegra210-quad.c
>>> @@ -142,6 +142,7 @@
>>>
>>>    #define QSPI_GLOBAL_CONFIG			0X1a4
>>>    #define QSPI_CMB_SEQ_EN				BIT(0)
>>> +#define QSPI_TPM_WAIT_POLL_EN			BIT(1)
>>>
>>>    #define QSPI_CMB_SEQ_ADDR			0x1a8
>>>    #define QSPI_ADDRESS_VALUE_SET(X)		(((x) & 0xFFFF) << 0)
>>> @@ -165,11 +166,13 @@ struct tegra_qspi_soc_data {
>>>    	bool has_dma;
>>>    	bool cmb_xfer_capable;
>>>    	bool cs_count;
>>> +	bool has_wait_polling;
>>>    };
>>>
>>>    struct tegra_qspi_client_data {
>>>    	int tx_clk_tap_delay;
>>>    	int rx_clk_tap_delay;
>>> +	bool wait_polling;
>>>    };
>>>
>>>    struct tegra_qspi {
>>> @@ -833,6 +836,11 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran
>>>    		else
>>>    			command1 |= QSPI_CONTROL_MODE_0;
>>>
>>> +		if (tqspi->soc_data->cmb_xfer_capable)
>>> +			command1 &= ~QSPI_CS_SW_HW;
>>> +		else
>>> +			command1 |= QSPI_CS_SW_HW;
>>> +
>>>    		if (spi->mode & SPI_CS_HIGH)
>>>    			command1 |= QSPI_CS_SW_VAL;
>>>    		else
>>> @@ -917,6 +925,7 @@ static int tegra_qspi_start_transfer_one(struct spi_device *spi,
>>>
>>>    static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_device *spi)
>>>    {
>>> +	struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
>>>    	struct tegra_qspi_client_data *cdata;
>>>
>>>    	cdata = devm_kzalloc(&spi->dev, sizeof(*cdata), GFP_KERNEL);
>>> @@ -927,6 +936,11 @@ static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_devic
>>>    				 &cdata->tx_clk_tap_delay);
>>>    	device_property_read_u32(&spi->dev, "nvidia,rx-clk-tap-delay",
>>>    				 &cdata->rx_clk_tap_delay);
>>> +	if (tqspi->soc_data->has_wait_polling)
>>> +		cdata->wait_polling = device_property_read_bool
>>> +					(&spi->dev,
>>> +					 "nvidia,wait-polling");
>>> +
>>
>>
>> This looks odd. Why do we need this device-tree property if it is
>> already specified in the SoC data?
> Soc data specifies chip is capable of wait-polling.
> Wait polling still has to be selected on slave devices that can support it.
> I will add one line description for the properties in next version.


I can't say I am familiar with this, but it seems that the ideal 
solution would be able to detect if this needs to be enabled depending 
on the device connected. Is that not possible?

Jon

-- 
nvpublic

Re: [PATCH 1/3] spi: tegra210-quad: Multi-cs support

[kernel test robot]

Hi Krishna,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on broonie-spi/for-next]
[also build test ERROR on next-20220316]
[cannot apply to v5.17-rc8]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Krishna-Yarlagadda/spi-tegra-quad-Add-Tegra-Grace-features/20220317-092247
base:   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
config: ia64-allmodconfig (https://download.01.org/0day-ci/archive/20220317/202203172241.iGAq0qeH-lkp@intel.com/config)
compiler: ia64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/38ff812651f89adc738066112000ec32eb73d106
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Krishna-Yarlagadda/spi-tegra-quad-Add-Tegra-Grace-features/20220317-092247
        git checkout 38ff812651f89adc738066112000ec32eb73d106
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=ia64 SHELL=/bin/bash drivers/spi/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/spi/spi-tegra210-quad.c:1497:49: error: 'th500_qspi_soc_data' undeclared here (not in a function); did you mean 'tegra_qspi_soc_data'?
    1497 |                 .driver_data = (kernel_ulong_t)&th500_qspi_soc_data,
         |                                                 ^~~~~~~~~~~~~~~~~~~
         |                                                 tegra_qspi_soc_data


vim +1497 drivers/spi/spi-tegra210-quad.c

  1483	
  1484	#ifdef CONFIG_ACPI
  1485	static const struct acpi_device_id tegra_qspi_acpi_match[] = {
  1486		{
  1487			.id = "NVDA1213",
  1488			.driver_data = (kernel_ulong_t)&tegra210_qspi_soc_data,
  1489		}, {
  1490			.id = "NVDA1313",
  1491			.driver_data = (kernel_ulong_t)&tegra186_qspi_soc_data,
  1492		}, {
  1493			.id = "NVDA1413",
  1494			.driver_data = (kernel_ulong_t)&tegra234_qspi_soc_data,
  1495		}, {
  1496			.id = "NVDA1513",
> 1497			.driver_data = (kernel_ulong_t)&th500_qspi_soc_data,
  1498		},
  1499		{}
  1500	};
  1501	

---
0-DAY CI Kernel Test Service
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

Re: [PATCH 2/3] spi: tegra210-quad: Add wait polling support

[Jon Hunter]

On 17/03/2022 09:44, Jon Hunter wrote:
> 
> On 17/03/2022 09:02, Krishna Yarlagadda wrote:
>>> -----Original Message-----
>>> From: Jonathan Hunter <jonathanh@nvidia.com>
>>> Sent: 17 March 2022 14:25
>>> To: Krishna Yarlagadda <kyarlagadda@nvidia.com>; broonie@kernel.org; 
>>> thierry.reding@gmail.com; linux-spi@vger.kernel.org; linux-
>>> tegra@vger.kernel.org; Ashish Singhal <ashishsingha@nvidia.com>
>>> Cc: Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan 
>>> <ldewangan@nvidia.com>; robh+dt@kernel.org;
>>> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
>>> Subject: Re: [PATCH 2/3] spi: tegra210-quad: Add wait polling support
>>>
>>>
>>> On 17/03/2022 01:20, Krishna Yarlagadda wrote:
>>>> Controller can poll for wait state inserted by TPM device and
>>>> handle it.
>>>>
>>>> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
>>>> ---
>>>>    drivers/spi/spi-tegra210-quad.c | 31 +++++++++++++++++++++++++++++++
>>>>    1 file changed, 31 insertions(+)
>>>>
>>>> diff --git a/drivers/spi/spi-tegra210-quad.c 
>>>> b/drivers/spi/spi-tegra210-quad.c
>>>> index a2e225e8f7f0..ecf171bfcdce 100644
>>>> --- a/drivers/spi/spi-tegra210-quad.c
>>>> +++ b/drivers/spi/spi-tegra210-quad.c
>>>> @@ -142,6 +142,7 @@
>>>>
>>>>    #define QSPI_GLOBAL_CONFIG            0X1a4
>>>>    #define QSPI_CMB_SEQ_EN                BIT(0)
>>>> +#define QSPI_TPM_WAIT_POLL_EN            BIT(1)
>>>>
>>>>    #define QSPI_CMB_SEQ_ADDR            0x1a8
>>>>    #define QSPI_ADDRESS_VALUE_SET(X)        (((x) & 0xFFFF) << 0)
>>>> @@ -165,11 +166,13 @@ struct tegra_qspi_soc_data {
>>>>        bool has_dma;
>>>>        bool cmb_xfer_capable;
>>>>        bool cs_count;
>>>> +    bool has_wait_polling;
>>>>    };
>>>>
>>>>    struct tegra_qspi_client_data {
>>>>        int tx_clk_tap_delay;
>>>>        int rx_clk_tap_delay;
>>>> +    bool wait_polling;
>>>>    };
>>>>
>>>>    struct tegra_qspi {
>>>> @@ -833,6 +836,11 @@ static u32 tegra_qspi_setup_transfer_one(struct 
>>>> spi_device *spi, struct spi_tran
>>>>            else
>>>>                command1 |= QSPI_CONTROL_MODE_0;
>>>>
>>>> +        if (tqspi->soc_data->cmb_xfer_capable)
>>>> +            command1 &= ~QSPI_CS_SW_HW;
>>>> +        else
>>>> +            command1 |= QSPI_CS_SW_HW;
>>>> +
>>>>            if (spi->mode & SPI_CS_HIGH)
>>>>                command1 |= QSPI_CS_SW_VAL;
>>>>            else
>>>> @@ -917,6 +925,7 @@ static int tegra_qspi_start_transfer_one(struct 
>>>> spi_device *spi,
>>>>
>>>>    static struct tegra_qspi_client_data 
>>>> *tegra_qspi_parse_cdata_dt(struct spi_device *spi)
>>>>    {
>>>> +    struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
>>>>        struct tegra_qspi_client_data *cdata;
>>>>
>>>>        cdata = devm_kzalloc(&spi->dev, sizeof(*cdata), GFP_KERNEL);
>>>> @@ -927,6 +936,11 @@ static struct tegra_qspi_client_data 
>>>> *tegra_qspi_parse_cdata_dt(struct spi_devic
>>>>                     &cdata->tx_clk_tap_delay);
>>>>        device_property_read_u32(&spi->dev, "nvidia,rx-clk-tap-delay",
>>>>                     &cdata->rx_clk_tap_delay);
>>>> +    if (tqspi->soc_data->has_wait_polling)
>>>> +        cdata->wait_polling = device_property_read_bool
>>>> +                    (&spi->dev,
>>>> +                     "nvidia,wait-polling");
>>>> +
>>>
>>>
>>> This looks odd. Why do we need this device-tree property if it is
>>> already specified in the SoC data?
>> Soc data specifies chip is capable of wait-polling.
>> Wait polling still has to be selected on slave devices that can 
>> support it.
>> I will add one line description for the properties in next version.
> 
> 
> I can't say I am familiar with this, but it seems that the ideal 
> solution would be able to detect if this needs to be enabled depending 
> on the device connected. Is that not possible?

Also, given that Grace supports 4 chip-selects per device, how does this 
work if there is TPM connected to one chip-select and something else 
connected to another?

Jon

-- 
nvpublic

RE: [PATCH 2/3] spi: tegra210-quad: Add wait polling support

[Krishna Yarlagadda]

Regards
KY

> -----Original Message-----
> From: Jonathan Hunter <jonathanh@nvidia.com>
> Sent: 17 March 2022 20:56
> To: Krishna Yarlagadda <kyarlagadda@nvidia.com>; broonie@kernel.org; thierry.reding@gmail.com; linux-spi@vger.kernel.org;
> linux-tegra@vger.kernel.org; Ashish Singhal <ashishsingha@nvidia.com>
> Cc: Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan <ldewangan@nvidia.com>; robh+dt@kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 2/3] spi: tegra210-quad: Add wait polling support
> 
> 
> On 17/03/2022 09:44, Jon Hunter wrote:
> >
> > On 17/03/2022 09:02, Krishna Yarlagadda wrote:
> >>> -----Original Message-----
> >>> From: Jonathan Hunter <jonathanh@nvidia.com>
> >>> Sent: 17 March 2022 14:25
> >>> To: Krishna Yarlagadda <kyarlagadda@nvidia.com>; broonie@kernel.org;
> >>> thierry.reding@gmail.com; linux-spi@vger.kernel.org; linux-
> >>> tegra@vger.kernel.org; Ashish Singhal <ashishsingha@nvidia.com>
> >>> Cc: Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan
> >>> <ldewangan@nvidia.com>; robh+dt@kernel.org;
> >>> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
> >>> Subject: Re: [PATCH 2/3] spi: tegra210-quad: Add wait polling support
> >>>
> >>>
> >>> On 17/03/2022 01:20, Krishna Yarlagadda wrote:
> >>>> Controller can poll for wait state inserted by TPM device and
> >>>> handle it.
> >>>>
> >>>> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> >>>> ---
> >>>>    drivers/spi/spi-tegra210-quad.c | 31 +++++++++++++++++++++++++++++++
> >>>>    1 file changed, 31 insertions(+)
> >>>>
> >>>> diff --git a/drivers/spi/spi-tegra210-quad.c
> >>>> b/drivers/spi/spi-tegra210-quad.c
> >>>> index a2e225e8f7f0..ecf171bfcdce 100644
> >>>> --- a/drivers/spi/spi-tegra210-quad.c
> >>>> +++ b/drivers/spi/spi-tegra210-quad.c
> >>>> @@ -142,6 +142,7 @@
> >>>>
> >>>>    #define QSPI_GLOBAL_CONFIG            0X1a4
> >>>>    #define QSPI_CMB_SEQ_EN                BIT(0)
> >>>> +#define QSPI_TPM_WAIT_POLL_EN            BIT(1)
> >>>>
> >>>>    #define QSPI_CMB_SEQ_ADDR            0x1a8
> >>>>    #define QSPI_ADDRESS_VALUE_SET(X)        (((x) & 0xFFFF) << 0)
> >>>> @@ -165,11 +166,13 @@ struct tegra_qspi_soc_data {
> >>>>        bool has_dma;
> >>>>        bool cmb_xfer_capable;
> >>>>        bool cs_count;
> >>>> +    bool has_wait_polling;
> >>>>    };
> >>>>
> >>>>    struct tegra_qspi_client_data {
> >>>>        int tx_clk_tap_delay;
> >>>>        int rx_clk_tap_delay;
> >>>> +    bool wait_polling;
> >>>>    };
> >>>>
> >>>>    struct tegra_qspi {
> >>>> @@ -833,6 +836,11 @@ static u32 tegra_qspi_setup_transfer_one(struct
> >>>> spi_device *spi, struct spi_tran
> >>>>            else
> >>>>                command1 |= QSPI_CONTROL_MODE_0;
> >>>>
> >>>> +        if (tqspi->soc_data->cmb_xfer_capable)
> >>>> +            command1 &= ~QSPI_CS_SW_HW;
> >>>> +        else
> >>>> +            command1 |= QSPI_CS_SW_HW;
> >>>> +
> >>>>            if (spi->mode & SPI_CS_HIGH)
> >>>>                command1 |= QSPI_CS_SW_VAL;
> >>>>            else
> >>>> @@ -917,6 +925,7 @@ static int tegra_qspi_start_transfer_one(struct
> >>>> spi_device *spi,
> >>>>
> >>>>    static struct tegra_qspi_client_data
> >>>> *tegra_qspi_parse_cdata_dt(struct spi_device *spi)
> >>>>    {
> >>>> +    struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
> >>>>        struct tegra_qspi_client_data *cdata;
> >>>>
> >>>>        cdata = devm_kzalloc(&spi->dev, sizeof(*cdata), GFP_KERNEL);
> >>>> @@ -927,6 +936,11 @@ static struct tegra_qspi_client_data
> >>>> *tegra_qspi_parse_cdata_dt(struct spi_devic
> >>>>                     &cdata->tx_clk_tap_delay);
> >>>>        device_property_read_u32(&spi->dev, "nvidia,rx-clk-tap-delay",
> >>>>                     &cdata->rx_clk_tap_delay);
> >>>> +    if (tqspi->soc_data->has_wait_polling)
> >>>> +        cdata->wait_polling = device_property_read_bool
> >>>> +                    (&spi->dev,
> >>>> +                     "nvidia,wait-polling");
> >>>> +
> >>>
> >>>
> >>> This looks odd. Why do we need this device-tree property if it is
> >>> already specified in the SoC data?
> >> Soc data specifies chip is capable of wait-polling.
> >> Wait polling still has to be selected on slave devices that can
> >> support it.
> >> I will add one line description for the properties in next version.
> >
> >
> > I can't say I am familiar with this, but it seems that the ideal
> > solution would be able to detect if this needs to be enabled depending
> > on the device connected. Is that not possible?
We cannot detect at runtime which slave supports wait polling.
> 
> Also, given that Grace supports 4 chip-selects per device, how does this
> work if there is TPM connected to one chip-select and something else
> connected to another?
Wait polling is part of client data which is unique for each cs slave.
This flag will be enabled on controller register while initiating transfer
for TPM slave and disabled for all other transfers.
> 
> Jon
> 
> --
> nvpublic

Re: [PATCH 2/3] spi: tegra210-quad: Add wait polling support

[Mark Brown]

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On Thu, Mar 17, 2022 at 06:00:25PM +0000, Krishna Yarlagadda wrote:

> > >> Wait polling still has to be selected on slave devices that can
> > >> support it.
> > >> I will add one line description for the properties in next version.

> > > I can't say I am familiar with this, but it seems that the ideal
> > > solution would be able to detect if this needs to be enabled depending
> > > on the device connected. Is that not possible?

> We cannot detect at runtime which slave supports wait polling.

How would the client device have any knowledge of how the controller
internal implementation works?  What even is a "wait state inserted by
TPM device"?  If this is something the client device is doing then it
should be something that is expressed through the generic SPI API by the
client device, if some controllers have some way of optimising this then
we can add support for that but presumably it's just something that's
generically supported by that device so we shouldn't need a DT property
for it on the device side either.

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Re: [PATCH 3/3] spi: dt-bindings: Add wait state polling flag

[Rob Herring]

On Thu, Mar 17, 2022 at 06:50:06AM +0530, Krishna Yarlagadda wrote:
> Add flag to enable tpm wait state polling and Tegra Grace binding.

TPM

> 
> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> ---
>  .../devicetree/bindings/spi/nvidia,tegra210-quad.yaml       | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> index 0296edd1de22..88b00fcad210 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> @@ -20,6 +20,7 @@ properties:
>        - nvidia,tegra186-qspi
>        - nvidia,tegra194-qspi
>        - nvidia,tegra234-qspi
> +      - nvidia,tegra-grace-qspi
>  
>    reg:
>      maxItems: 1
> @@ -57,6 +58,11 @@ patternProperties:
>        spi-tx-bus-width:
>          enum: [1, 2, 4]
>  
> +      nvidia,wait-polling:
> +        description:
> +          Enable TPM wait state polling on supported chips.

What's TPM?

Why is this not implied by the compatible string?

Also, how child node properties are handled has changed. See 
Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml. The 
NVidia specific properties should be refactored first before adding 
more.

> +	type: boolean
> +
>        nvidia,tx-clk-tap-delay:
>          description:
>            Delays the clock going out to device with this tap value.
> -- 
> 2.17.1
> 
>