[PATCH V9 0/9] CXL: Read CDAT and DSMAS data

[PATCH V9 0/9] CXL: Read CDAT and DSMAS data

[ira.weiny]

From: Ira Weiny <ira.weiny@intel.com>

Changes from V8:[5]
	For this version I've punted a bit to get it out and drop the auxiliary
	bus functionality.  I like where Jonathan is going with the port driver
	idea.  I think eventually the irq/mailbox creation will need to be more
	generic in a PCI port driver.  I've modeled this version on such an
	architecture but used the CXL port for the time being.

	From Dan
		Drop the auxiliary bus/device
	From Jonathan
		Cleanups
	From Bjorn
		Clean up commit messages
		move pci-doe.c to doe.c
		Clean up PCI spec references
		Ensure all messages use pci_*()
		Add offset to error messages to distinguish mailboxes
			use hex for DOE offsets
		Print 4 nibbles for Vendor ID and 2 for type.
		s/irq/IRQ in comments
		Fix long lines
		Fix typos


Changes from V7:[4]
	Avoid code bloat by making pci-doe.c conditional on CONFIG_PCI_DOE
		which is auto selected by the CXL_PCI config option.
	Minor code clean ups
	Fix bug in pci_doe_supports_prot()
	Rebase to cxl-pending

Changes from V6:[3]
	The big change is the removal of the auxiliary bus code from the PCI
	layer.  The auxiliary bus usage is now in the CXL layer.  The PCI layer
	provides helpers for subsystems to utilize DOE mailboxes by creating a
	pci_doe_mb object which controls a state machine for that mailbox
	capability.  The CXL layer wraps this object in an auxiliary device and
	driver which can then be used to determine if the kernel is controlling
	the capability or it is available to be used by user space.  Reads from
	user space via lspci are allowed.  Writes are allowed but flagged via a
	tainting the kernel.

	Feedback from Bjorn, Jonathan, and Dan
		Details in each patch

Changes from V5:[0]

	Rework the patch set to split PCI vs CXL changes
		Also make each change a bit more stand alone for easier review
	Add cxl_cdat structure
	Put CDAT related data structures in cdat.h
	Clarify some device lifetimes with comments
	Incorporate feedback from Jonathan, Bjorn and Dan
		The bigest change is placing the DOE scanning code into the
			pci_doe driver (part of the PCI codre).
		Validate the CDAT when it is read rather than before DSMAS
			parsing
		Do not report DSMAS failure as an error, report a warning and
			keep going.
		Retry reading the table 1 time.
	Update commit messages and this cover letter



CXL drivers need various data which are provided through generic DOE mailboxes
as defined in the PCIe 6.0 spec.[1]

One such data is the Coherent Device Atribute Table (CDAT).  CDAT data provides
coherent information about the various devices in the system.  It was developed
because systems no longer have a priori knowledge of all coherent devices
within a system.  CDAT describes the coherent characteristics of the
components on the CXL bus separate from system configurations.  The OS can
then, for example, use this information to form correct interleave sets.

To begin reading the CDAT the OS must have support to access the DOE mailboxes
provided by the CXL devices.

Because DOE is not specific to DOE but is provided within the PCI spec, the
series adds PCI DOE capability library functions.  These functions allow for
the iteration of the DOE capabilities on a device as well as creating
pci_doe_mb structures which can control the operation of the DOE state machine.

CXL iterates the DOE capabilities creates auxiliary bus devices.  These devices
are driven by a CXL DOE auxiliary driver which calls into the PCI DOE library
functions as appropriate.

The auxiliary bus architecture allows for root users to control which DOE
mailboxes are controlled by the kernel and which should be allowed for
unrestricted access by user space.  One such use case is to allow for CXL
Compliance Testing (CXL 2.0 14.16.4 Compliance Mode DOE).  By default the
kernel controls all mailboxes found.

After the devices are created and the driver attaches, CDAT data is read from
the device and DSMAS information parsed from that CDAT blob for use later.

This work was tested using qemu with additional patches.


[0] https://lore.kernel.org/linux-cxl/20211105235056.3711389-1-ira.weiny@intel.com/
[1] https://pcisig.com/specifications
[2] https://lore.kernel.org/qemu-devel/20210202005948.241655-1-ben.widawsky@intel.com/
[3] https://lore.kernel.org/linux-cxl/20220201071952.900068-1-ira.weiny@intel.com/
[4] https://lore.kernel.org/linux-cxl/20220330235920.2800929-1-ira.weiny@intel.com/
[5] https://lore.kernel.org/linux-cxl/20220414203237.2198665-1-ira.weiny@intel.com/


Ira Weiny (6):
PCI: Replace magic constant for PCI Sig Vendor ID
cxl/pci: Create PCI DOE mailbox's for memory devices
cxl/port: Find a DOE mailbox which supports CDAT
cxl/port: Introduce cxl_cdat_valid()
cxl/port: Retry reading CDAT on failure
cxl/port: Parse out DSMAS data from CDAT table

Jonathan Cameron (3):
PCI: Add vendor ID for the PCI SIG
PCI: Create PCI library functions in support of DOE mailboxes.
cxl/port: Read CDAT table

drivers/cxl/Kconfig | 1 +
drivers/cxl/cdat.h | 118 +++++++
drivers/cxl/core/pci.c | 267 ++++++++++++++
drivers/cxl/core/port.c | 45 +++
drivers/cxl/cxl.h | 7 +
drivers/cxl/cxlmem.h | 10 +
drivers/cxl/cxlpci.h | 3 +
drivers/cxl/mem.c | 1 +
drivers/cxl/pci.c | 111 ++++++
drivers/pci/Kconfig | 3 +
drivers/pci/Makefile | 1 +
drivers/pci/doe.c | 633 ++++++++++++++++++++++++++++++++++
drivers/pci/probe.c | 2 +-
include/linux/pci-doe.h | 120 +++++++
include/linux/pci_ids.h | 1 +
include/uapi/linux/pci_regs.h | 29 +-
16 files changed, 1350 insertions(+), 2 deletions(-)
create mode 100644 drivers/cxl/cdat.h
create mode 100644 drivers/pci/doe.c
create mode 100644 include/linux/pci-doe.h

--
2.35.1

[PATCH V9 1/9] PCI: Add vendor ID for the PCI SIG

[ira.weiny]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

This ID is used in DOE headers to identify protocols that are defined
within the PCI Express Base Specification, PCIe r6.0, sec 6.30.1.1 table
6-32.

Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 include/linux/pci_ids.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 0178823ce8c2..8af3b86206b1 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -151,6 +151,7 @@
 #define PCI_CLASS_OTHERS		0xff
 
 /* Vendors and devices.  Sort key: vendor first, device next. */
+#define PCI_VENDOR_ID_PCI_SIG		0x0001
 
 #define PCI_VENDOR_ID_LOONGSON		0x0014
 
-- 
2.35.1

Re: [PATCH v9 1/9] PCI: Add vendor ID for the PCI SIG

[Davidlohr Bueso]

On Tue, 31 May 2022, ira.weiny@intel.com wrote:

>From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
>This ID is used in DOE headers to identify protocols that are defined
>within the PCI Express Base Specification, PCIe r6.0, sec 6.30.1.1 table
>6-32.
>
>Acked-by: Bjorn Helgaas <bhelgaas@google.com>
>Reviewed-by: Dan Williams <dan.j.williams@intel.com>
>Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>

>---
> include/linux/pci_ids.h | 1 +
> 1 file changed, 1 insertion(+)
>
>diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
>index 0178823ce8c2..8af3b86206b1 100644
>--- a/include/linux/pci_ids.h
>+++ b/include/linux/pci_ids.h
>@@ -151,6 +151,7 @@
> #define PCI_CLASS_OTHERS		0xff
>
> /* Vendors and devices.  Sort key: vendor first, device next. */
>+#define PCI_VENDOR_ID_PCI_SIG		0x0001
>
> #define PCI_VENDOR_ID_LOONGSON		0x0014
>
>
>-- 
>2.35.1
>

[PATCH V9 2/9] PCI: Replace magic constant for PCI Sig Vendor ID

[ira.weiny]

From: Ira Weiny <ira.weiny@intel.com>

Replace the magic value in pci_bus_crs_vendor_id() with
PCI_VENDOR_ID_PCI_SIG.

Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>

---
Changes from V6
	Simplify commit message
---
 drivers/pci/probe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 17a969942d37..6280e780a48c 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2312,7 +2312,7 @@ EXPORT_SYMBOL(pci_alloc_dev);
 
 static bool pci_bus_crs_vendor_id(u32 l)
 {
-	return (l & 0xffff) == 0x0001;
+	return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
 }
 
 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
-- 
2.35.1

Re: [PATCH v9 2/9] PCI: Replace magic constant for PCI Sig Vendor ID

[Davidlohr Bueso]

On Tue, 31 May 2022, ira.weiny@intel.com wrote:

>From: Ira Weiny <ira.weiny@intel.com>
>
>Replace the magic value in pci_bus_crs_vendor_id() with
>PCI_VENDOR_ID_PCI_SIG.
>
>Reviewed-by: Dan Williams <dan.j.williams@intel.com>
>Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
>Acked-by: Bjorn Helgaas <bhelgaas@google.com>
>Signed-off-by: Ira Weiny <ira.weiny@intel.com>

Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>

>---
>Changes from V6
>	Simplify commit message
>---
> drivers/pci/probe.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
>index 17a969942d37..6280e780a48c 100644
>--- a/drivers/pci/probe.c
>+++ b/drivers/pci/probe.c
>@@ -2312,7 +2312,7 @@ EXPORT_SYMBOL(pci_alloc_dev);
>
> static bool pci_bus_crs_vendor_id(u32 l)
> {
>-	return (l & 0xffff) == 0x0001;
>+	return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
> }
>
> static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
>
>-- 
>2.35.1
>

[PATCH V9 3/9] PCI: Create PCI library functions in support of DOE mailboxes.

[ira.weiny]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Introduced in a PCI r6.0, sec 6.30, DOE provides a config space based mailbox
with standard protocol discovery.  Each mailbox is accessed through a
DOE Extended Capability.

Each DOE mailbox must support the DOE discovery protocol in addition to
any number of additional protocols.

Define core PCI functionality to manage a single PCI DOE mailbox at a
defined config space offset.  Functionality includes iterating,
creating, query of supported protocol, task submission, and destruction
of the mailboxes.

If interrupts are desired, the interrupt number can be queried and
passed to the create function.  Passing a negative value disables
interrupts for that mailbox.  It is the callers responsibility to ensure
enough interrupt vectors are allocated.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Co-developed-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>

---
Changes from V8
	Remove Bjorn's ack
	Expose a function to find the irq number for a mailbox based on
	offset.  This is the code Jonathan proposed for finding the irq
	number here:
	https://lore.kernel.org/linux-cxl/20220503153449.4088-2-Jonathan.Cameron@huawei.com/
		This removes funky bool parameter to create.
	Move pci_set_master() within the pci_doe_enable_irq()
	Per Bjorn
		Clean up commit messages
		move pci-doe.c to doe.c
		Clean up PCI spec references
		Ensure all messages use pci_*()
		Add offset to error messages to distinguish mailboxes
			use hex for DOE offsets
		Print 4 nibbles for Vendor ID and 2 for type.
		s/irq/IRQ in comments
		Fix long lines
		Fix typos

Changes from V7
	Add a Kconfig for this functionality
	Fix bug in pci_doe_supports_prot()
	Rebased on cxl-pending

Changes from V6
	Clean up signed off by lines
	Make this functionality all PCI library functions
	Clean up header files
	s/pci_doe_irq/pci_doe_irq_handler
	Use pci_{request,free}_irq
		Remove irq_name (maintained by pci_request_irq)
	Fix checks to use an irq
	Consistently use u16 for cap_offset
	Cleanup kdocs and comments
	Create a helper retire_cur_task() to handle locking of the
		current task pointer.
	Remove devm_ calls from PCI layer.
		The devm_ calls do not allow for the pci_doe_mb objects
		to be tied to an auxiliary device.  Leave it to the
		caller to use devm_ if desired.
	From Dan Williams
		s/cb/end_task/; Pass pci_doe_task to end_task
		Clarify exchange/task/request/response.
			Merge pci_doe_task and pci_doe_exchange into
			pci_doe_task which represents a single
			request/response task for the state machine to
			process.
		Simplify submitting work to the mailbox
			Replace pci_doe_exchange_sync() with
			pci_doe_submit_task() Consumers of the mailbox
			are now responsible for setting up callbacks
			within a task object and submitting them to the
			mailbox to be processed.
		Remove WARN_ON when task != NULL and be sure to abort that task.
		Convert abort/dead to atomic flags
		s/state_lock/task_lock to better define what the lock is
			protecting
		Remove all the auxiliary bus code from the PCI layer
			The PCI layer provides helpers to use the DOE
			Mailboxes.  Each subsystem can then use the
			helpers as they see fit.  The CXL layer in this
			series uses aux devices to manage the new
			pci_doe_mb objects.

	From Bjorn
		Clarify the fact that DOE mailboxes are capabilities of
			the device.
		Code clean ups
		Cleanup Makefile
		Update references to PCI SIG spec v6.0
		Move this attribution here:
		This code is based on Jonathan's V4 series here:
		https://lore.kernel.org/linux-cxl/20210524133938.2815206-1-Jonathan.Cameron@huawei.com/

Changes from V5
	From Bjorn
		s/pci_WARN/pci_warn
			Add timeout period to print
		Trim to 80 chars
		Use Tabs for DOE define spacing
		Use %#x for clarity
	From Jonathan
		Addresses concerns about the order of unwinding stuff
		s/doe/doe_dev in pci_doe_exhcnage_sync
		Correct kernel Doc comment
		Move pci_doe_task_complete() down in the file.
		Rework pci_doe_irq()
			process STATUS_ERROR first
			Return IRQ_NONE if the irq is not processed
			Use PCI_DOE_STATUS_INT_STATUS explicitly to
				clear the irq
	Clean up goto label s/err_free_irqs/err_free_irq
	use devm_kzalloc for doe struct
	clean up error paths in pci_doe_probe
	s/pci_doe_drv/pci_doe
	remove include mutex.h
	remove device name and define, move it in the next patch which uses it
	use devm_kasprintf() for irq_name
	use devm_request_irq()
	remove pci_doe_unregister()
		[get/put]_device() were unneeded and with the use of
		devm_* this function can be removed completely.
	refactor pci_doe_register and s/pci_doe_register/pci_doe_reg_irq
		make this function just a registration of the irq and
		move pci_doe_abort() into pci_doe_probe()
	use devm_* to allocate the protocol array

Changes from Jonathan's V4
	Move the DOE MB code into the DOE auxiliary driver
	Remove Task List in favor of a wait queue

Changes from Ben
	remove CXL references
	propagate rc from pci functions on error
---
 drivers/pci/Kconfig           |   3 +
 drivers/pci/Makefile          |   1 +
 drivers/pci/doe.c             | 633 ++++++++++++++++++++++++++++++++++
 include/linux/pci-doe.h       | 120 +++++++
 include/uapi/linux/pci_regs.h |  29 +-
 5 files changed, 785 insertions(+), 1 deletion(-)
 create mode 100644 drivers/pci/doe.c
 create mode 100644 include/linux/pci-doe.h

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 133c73207782..b2f2e588a817 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -121,6 +121,9 @@ config XEN_PCIDEV_FRONTEND
 config PCI_ATS
 	bool
 
+config PCI_DOE
+	bool
+
 config PCI_ECAM
 	bool
 
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 0da6b1ebc694..2680e4c92f0a 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_PCI_ECAM)		+= ecam.o
 obj-$(CONFIG_PCI_P2PDMA)	+= p2pdma.o
 obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o
 obj-$(CONFIG_VGA_ARB)		+= vgaarb.o
+obj-$(CONFIG_PCI_DOE)		+= doe.o
 
 # Endpoint library must be initialized before its users
 obj-$(CONFIG_PCI_ENDPOINT)	+= endpoint/
diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c
new file mode 100644
index 000000000000..5c533ba2e580
--- /dev/null
+++ b/drivers/pci/doe.c
@@ -0,0 +1,633 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Data Object Exchange
+ *	PCIe r6.0, sec 6.30 DOE
+ *
+ * Copyright (C) 2021 Huawei
+ *	Jonathan Cameron <Jonathan.Cameron@huawei.com>
+ *
+ * Copyright (C) 2022 Intel Corporation
+ *	Ira Weiny <ira.weiny@intel.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+#include <linux/mutex.h>
+#include <linux/pci.h>
+#include <linux/pci-doe.h>
+#include <linux/workqueue.h>
+
+#define PCI_DOE_PROTOCOL_DISCOVERY 0
+
+#define PCI_DOE_BUSY_MAX_RETRIES 16
+#define PCI_DOE_POLL_INTERVAL (HZ / 128)
+
+/* Timeout of 1 second from 6.30.2 Operation, PCI Spec r6.0 */
+#define PCI_DOE_TIMEOUT HZ
+
+static irqreturn_t pci_doe_irq_handler(int irq, void *data)
+{
+	struct pci_doe_mb *doe_mb = data;
+	struct pci_dev *pdev = doe_mb->pdev;
+	int offset = doe_mb->cap_offset;
+	u32 val;
+
+	pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
+
+	/* Leave the error case to be handled outside IRQ */
+	if (FIELD_GET(PCI_DOE_STATUS_ERROR, val)) {
+		mod_delayed_work(system_wq, &doe_mb->statemachine, 0);
+		return IRQ_HANDLED;
+	}
+
+	if (FIELD_GET(PCI_DOE_STATUS_INT_STATUS, val)) {
+		pci_write_config_dword(pdev, offset + PCI_DOE_STATUS,
+					PCI_DOE_STATUS_INT_STATUS);
+		mod_delayed_work(system_wq, &doe_mb->statemachine, 0);
+		return IRQ_HANDLED;
+	}
+
+	return IRQ_NONE;
+}
+
+/*
+ * Only called when safe to directly access the DOE from
+ * doe_statemachine_work().  Outside access is not protected.  Users who
+ * perform such access are left with the pieces.
+ */
+static void pci_doe_abort_start(struct pci_doe_mb *doe_mb)
+{
+	struct pci_dev *pdev = doe_mb->pdev;
+	int offset = doe_mb->cap_offset;
+	u32 val;
+
+	val = PCI_DOE_CTRL_ABORT;
+	if (doe_mb->irq >= 0)
+		val |= PCI_DOE_CTRL_INT_EN;
+	pci_write_config_dword(pdev, offset + PCI_DOE_CTRL, val);
+
+	doe_mb->timeout_jiffies = jiffies + HZ;
+	schedule_delayed_work(&doe_mb->statemachine, HZ);
+}
+
+static int pci_doe_send_req(struct pci_doe_mb *doe_mb,
+			    struct pci_doe_task *task)
+{
+	struct pci_dev *pdev = doe_mb->pdev;
+	int offset = doe_mb->cap_offset;
+	u32 val;
+	int i;
+
+	/*
+	 * Check the DOE busy bit is not set. If it is set, this could indicate
+	 * someone other than Linux (e.g. firmware) is using the mailbox. Note
+	 * it is expected that firmware and OS will negotiate access rights via
+	 * an, as yet to be defined method.
+	 */
+	pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
+	if (FIELD_GET(PCI_DOE_STATUS_BUSY, val))
+		return -EBUSY;
+
+	if (FIELD_GET(PCI_DOE_STATUS_ERROR, val))
+		return -EIO;
+
+	/* Write DOE Header */
+	val = FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_VID, task->prot.vid) |
+		FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, task->prot.type);
+	pci_write_config_dword(pdev, offset + PCI_DOE_WRITE, val);
+	/* Length is 2 DW of header + length of payload in DW */
+	pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
+			       FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH,
+					  2 + task->request_pl_sz /
+						sizeof(u32)));
+	for (i = 0; i < task->request_pl_sz / sizeof(u32); i++)
+		pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
+				       task->request_pl[i]);
+
+	val = PCI_DOE_CTRL_GO;
+	if (doe_mb->irq >= 0)
+		val |= PCI_DOE_CTRL_INT_EN;
+
+	pci_write_config_dword(pdev, offset + PCI_DOE_CTRL, val);
+	/* Request is sent - now wait for poll or IRQ */
+	return 0;
+}
+
+static int pci_doe_recv_resp(struct pci_doe_mb *doe_mb, struct pci_doe_task *task)
+{
+	struct pci_dev *pdev = doe_mb->pdev;
+	int offset = doe_mb->cap_offset;
+	size_t length;
+	u32 val;
+	int i;
+
+	/* Read the first dword to get the protocol */
+	pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val);
+	if ((FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_VID, val) != task->prot.vid) ||
+	    (FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, val) != task->prot.type)) {
+		pci_err(pdev,
+			"DOE [%x] expected [VID, Protocol] = [%04x, %02x], got [%04x, %02x]\n",
+			doe_mb->cap_offset,
+			task->prot.vid, task->prot.type,
+			FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_VID, val),
+			FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, val));
+		return -EIO;
+	}
+
+	pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
+	/* Read the second dword to get the length */
+	pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val);
+	pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
+
+	length = FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH, val);
+	if (length > SZ_1M || length < 2)
+		return -EIO;
+
+	/* First 2 dwords have already been read */
+	length -= 2;
+	/* Read the rest of the response payload */
+	for (i = 0; i < min(length, task->response_pl_sz / sizeof(u32)); i++) {
+		pci_read_config_dword(pdev, offset + PCI_DOE_READ,
+				      &task->response_pl[i]);
+		pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
+	}
+
+	/* Flush excess length */
+	for (; i < length; i++) {
+		pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val);
+		pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
+	}
+	/* Final error check to pick up on any since Data Object Ready */
+	pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
+	if (FIELD_GET(PCI_DOE_STATUS_ERROR, val))
+		return -EIO;
+
+	return min(length, task->response_pl_sz / sizeof(u32)) * sizeof(u32);
+}
+
+static void signal_task_complete(struct pci_doe_task *task, int rv)
+{
+	task->rv = rv;
+	task->complete(task);
+}
+
+static void retire_cur_task(struct pci_doe_mb *doe_mb)
+{
+	mutex_lock(&doe_mb->task_lock);
+	doe_mb->cur_task = NULL;
+	mutex_unlock(&doe_mb->task_lock);
+	wake_up_interruptible(&doe_mb->wq);
+}
+
+static void doe_statemachine_work(struct work_struct *work)
+{
+	struct delayed_work *w = to_delayed_work(work);
+	struct pci_doe_mb *doe_mb = container_of(w, struct pci_doe_mb,
+						 statemachine);
+	struct pci_dev *pdev = doe_mb->pdev;
+	int offset = doe_mb->cap_offset;
+	struct pci_doe_task *task;
+	u32 val;
+	int rc;
+
+	mutex_lock(&doe_mb->task_lock);
+	task = doe_mb->cur_task;
+	mutex_unlock(&doe_mb->task_lock);
+
+	if (test_and_clear_bit(PCI_DOE_FLAG_ABORT, &doe_mb->flags)) {
+		/*
+		 * Currently only used during init - care needed if
+		 * pci_doe_abort() is generally exposed as it would impact
+		 * queries in flight.
+		 */
+		if (task)
+			pci_err(pdev, "DOE [%x] Aborting with active task!\n",
+				doe_mb->cap_offset);
+		doe_mb->state = DOE_WAIT_ABORT;
+		pci_doe_abort_start(doe_mb);
+		return;
+	}
+
+	switch (doe_mb->state) {
+	case DOE_IDLE:
+		if (task == NULL)
+			return;
+
+		rc = pci_doe_send_req(doe_mb, task);
+
+		/*
+		 * The specification does not provide any guidance on how long
+		 * some other entity could keep the DOE busy, so try for 1
+		 * second then fail. Busy handling is best effort only, because
+		 * there is no way of avoiding racing against another user of
+		 * the DOE.
+		 */
+		if (rc == -EBUSY) {
+			doe_mb->busy_retries++;
+			if (doe_mb->busy_retries == PCI_DOE_BUSY_MAX_RETRIES) {
+				/* Long enough, fail this request */
+				pci_warn(pdev,
+					"DOE [%x] busy for too long (> 1 sec)\n",
+					doe_mb->cap_offset);
+				doe_mb->busy_retries = 0;
+				goto err_busy;
+			}
+			schedule_delayed_work(w, HZ / PCI_DOE_BUSY_MAX_RETRIES);
+			return;
+		}
+		if (rc)
+			goto err_abort;
+		doe_mb->busy_retries = 0;
+
+		doe_mb->state = DOE_WAIT_RESP;
+		doe_mb->timeout_jiffies = jiffies + HZ;
+		/* Now poll or wait for IRQ with timeout */
+		if (doe_mb->irq >= 0)
+			schedule_delayed_work(w, PCI_DOE_TIMEOUT);
+		else
+			schedule_delayed_work(w, PCI_DOE_POLL_INTERVAL);
+		return;
+
+	case DOE_WAIT_RESP:
+		/* Not possible to get here with NULL task */
+		pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
+		if (FIELD_GET(PCI_DOE_STATUS_ERROR, val)) {
+			rc = -EIO;
+			goto err_abort;
+		}
+
+		if (!FIELD_GET(PCI_DOE_STATUS_DATA_OBJECT_READY, val)) {
+			/* If not yet at timeout reschedule otherwise abort */
+			if (time_after(jiffies, doe_mb->timeout_jiffies)) {
+				rc = -ETIMEDOUT;
+				goto err_abort;
+			}
+			schedule_delayed_work(w, PCI_DOE_POLL_INTERVAL);
+			return;
+		}
+
+		rc  = pci_doe_recv_resp(doe_mb, task);
+		if (rc < 0)
+			goto err_abort;
+
+		doe_mb->state = DOE_IDLE;
+
+		retire_cur_task(doe_mb);
+		/* Set the return value to the length of received payload */
+		signal_task_complete(task, rc);
+
+		return;
+
+	case DOE_WAIT_ABORT:
+	case DOE_WAIT_ABORT_ON_ERR:
+		pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
+
+		if (!FIELD_GET(PCI_DOE_STATUS_ERROR, val) &&
+		    !FIELD_GET(PCI_DOE_STATUS_BUSY, val)) {
+			/* Back to normal state - carry on */
+			retire_cur_task(doe_mb);
+
+			/*
+			 * For deliberately triggered abort, someone is
+			 * waiting.
+			 */
+			if (doe_mb->state == DOE_WAIT_ABORT) {
+				if (task)
+					signal_task_complete(task, -EFAULT);
+				complete(&doe_mb->abort_c);
+			}
+
+			doe_mb->state = DOE_IDLE;
+			return;
+		}
+		if (time_after(jiffies, doe_mb->timeout_jiffies)) {
+			/* Task has timed out and is dead - abort */
+			pci_err(pdev, "DOE [%x] ABORT timed out\n",
+				doe_mb->cap_offset);
+			set_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags);
+			retire_cur_task(doe_mb);
+
+			if (doe_mb->state == DOE_WAIT_ABORT) {
+				if (task)
+					signal_task_complete(task, -EFAULT);
+				complete(&doe_mb->abort_c);
+			}
+		}
+		return;
+	}
+
+err_abort:
+	doe_mb->state = DOE_WAIT_ABORT_ON_ERR;
+	pci_doe_abort_start(doe_mb);
+err_busy:
+	signal_task_complete(task, rc);
+	if (doe_mb->state == DOE_IDLE)
+		retire_cur_task(doe_mb);
+}
+
+static void pci_doe_task_complete(struct pci_doe_task *task)
+{
+	complete(task->private);
+}
+
+static int pci_doe_discovery(struct pci_doe_mb *doe_mb, u8 *index, u16 *vid,
+			     u8 *protocol)
+{
+	u32 request_pl = FIELD_PREP(PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX,
+				    *index);
+	u32 response_pl;
+	DECLARE_COMPLETION_ONSTACK(c);
+	struct pci_doe_task task = {
+		.prot.vid = PCI_VENDOR_ID_PCI_SIG,
+		.prot.type = PCI_DOE_PROTOCOL_DISCOVERY,
+		.request_pl = &request_pl,
+		.request_pl_sz = sizeof(request_pl),
+		.response_pl = &response_pl,
+		.response_pl_sz = sizeof(response_pl),
+		.complete = pci_doe_task_complete,
+		.private = &c,
+	};
+	int ret;
+
+	ret = pci_doe_submit_task(doe_mb, &task);
+	if (ret < 0)
+		return ret;
+
+	wait_for_completion(&c);
+
+	if (task.rv != sizeof(response_pl))
+		return -EIO;
+
+	*vid = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID, response_pl);
+	*protocol = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL,
+			      response_pl);
+	*index = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX,
+			   response_pl);
+
+	return 0;
+}
+
+static int pci_doe_cache_protocols(struct pci_doe_mb *doe_mb)
+{
+	u8 index = 0;
+	int num_prots;
+	int rc;
+
+	/* Discovery protocol must always be supported and must report itself */
+	num_prots = 1;
+
+	doe_mb->prots = kcalloc(num_prots, sizeof(*doe_mb->prots), GFP_KERNEL);
+	if (!doe_mb->prots)
+		return -ENOMEM;
+
+	/*
+	 * NOTE: doe_mb_prots is freed by pci_doe_free_mb() automatically on
+	 * error if pci_doe_cache_protocols() fails past this point.
+	 */
+	do {
+		struct pci_doe_protocol *prot;
+
+		prot = &doe_mb->prots[num_prots - 1];
+		rc = pci_doe_discovery(doe_mb, &index, &prot->vid, &prot->type);
+		if (rc)
+			return rc;
+
+		if (index) {
+			struct pci_doe_protocol *prot_new;
+
+			num_prots++;
+			prot_new = krealloc(doe_mb->prots,
+					    sizeof(*doe_mb->prots) * num_prots,
+					    GFP_KERNEL);
+			if (!prot_new)
+				return -ENOMEM;
+
+			doe_mb->prots = prot_new;
+		}
+	} while (index);
+
+	doe_mb->num_prots = num_prots;
+	return 0;
+}
+
+static int pci_doe_abort(struct pci_doe_mb *doe_mb)
+{
+	reinit_completion(&doe_mb->abort_c);
+	set_bit(PCI_DOE_FLAG_ABORT, &doe_mb->flags);
+	schedule_delayed_work(&doe_mb->statemachine, 0);
+	wait_for_completion(&doe_mb->abort_c);
+
+	if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags))
+		return -EIO;
+
+	return 0;
+}
+
+static int pci_doe_enable_irq(struct pci_doe_mb *doe_mb, unsigned int irq)
+{
+	struct pci_dev *pdev = doe_mb->pdev;
+	int offset = doe_mb->cap_offset;
+	int rc;
+
+	/*
+	 * Enabling bus mastering is required for MSI/MSIx.  It is safe to call
+	 * this multiple times and thus is called here to ensure that mastering
+	 * is enabled even if the driver has done so.
+	 */
+	pci_set_master(pdev);
+	rc = pci_request_irq(pdev, irq, pci_doe_irq_handler, NULL, doe_mb,
+			     "DOE[%d:%s]", irq, pci_name(pdev));
+	if (rc)
+		return rc;
+
+	doe_mb->irq = irq;
+	pci_write_config_dword(pdev, offset + PCI_DOE_CTRL,
+			       PCI_DOE_CTRL_INT_EN);
+	return 0;
+}
+
+static void pci_doe_free_mb(struct pci_doe_mb *doe_mb)
+{
+	if (doe_mb->irq >= 0)
+		pci_free_irq(doe_mb->pdev, doe_mb->irq, doe_mb);
+	kfree(doe_mb->prots);
+	kfree(doe_mb);
+}
+
+/**
+ * pci_doe_get_irq_num() - Return the irq number for the mailbox at offset
+ *
+ * @pdev: The PCI device
+ * @offset: Offset of the DOE mailbox
+ *
+ * Returns: irq number on success
+ *	    -errno if irqs are not supported on this mailbox
+ */
+int pci_doe_get_irq_num(struct pci_dev *pdev, int offset)
+{
+	u32 val;
+
+	pci_read_config_dword(pdev, offset + PCI_DOE_CAP, &val);
+	if (!FIELD_GET(PCI_DOE_CAP_INT, val))
+		return -EOPNOTSUPP;
+
+	return FIELD_GET(PCI_DOE_CAP_IRQ, val);
+}
+EXPORT_SYMBOL_GPL(pci_doe_get_irq_num);
+
+/**
+ * pci_doe_create_mb() - Create a DOE mailbox object
+ *
+ * @pdev: PCI device to create the DOE mailbox for
+ * @cap_offset: Offset of the DOE mailbox
+ * @irq: irq number to use; a negative value means don't use interrupts
+ *
+ * Create a single mailbox object to manage the mailbox protocol at the
+ * cap_offset specified.
+ *
+ * Caller should allocate PCI IRQ vectors before setting use_irq.
+ *
+ * RETURNS: created mailbox object on success
+ *	    ERR_PTR(-errno) on failure
+ */
+struct pci_doe_mb *pci_doe_create_mb(struct pci_dev *pdev, u16 cap_offset,
+				     int irq)
+{
+	struct pci_doe_mb *doe_mb;
+	int rc;
+
+	doe_mb = kzalloc(sizeof(*doe_mb), GFP_KERNEL);
+	if (!doe_mb)
+		return ERR_PTR(-ENOMEM);
+
+	doe_mb->pdev = pdev;
+	init_completion(&doe_mb->abort_c);
+	doe_mb->irq = -1;
+	doe_mb->cap_offset = cap_offset;
+
+	init_waitqueue_head(&doe_mb->wq);
+	mutex_init(&doe_mb->task_lock);
+	INIT_DELAYED_WORK(&doe_mb->statemachine, doe_statemachine_work);
+	doe_mb->state = DOE_IDLE;
+
+	if (irq >= 0) {
+		rc = pci_doe_enable_irq(doe_mb, irq);
+		if (rc)
+			pci_err(pdev,
+				"DOE [%x] enable requested IRQ (%d) failed : %d\n",
+				doe_mb->cap_offset, irq, rc);
+	}
+
+	/* Reset the mailbox by issuing an abort */
+	rc = pci_doe_abort(doe_mb);
+	if (rc) {
+		pci_err(pdev, "DOE [%x] failed to reset : %d\n",
+			doe_mb->cap_offset, rc);
+		pci_doe_free_mb(doe_mb);
+		return ERR_PTR(rc);
+	}
+
+	rc = pci_doe_cache_protocols(doe_mb);
+	if (rc) {
+		pci_err(pdev, "DOE [%x] failed to cache protocols : %d\n",
+			doe_mb->cap_offset, rc);
+		pci_doe_free_mb(doe_mb);
+		return ERR_PTR(rc);
+	}
+
+	return doe_mb;
+}
+EXPORT_SYMBOL_GPL(pci_doe_create_mb);
+
+/**
+ * pci_doe_supports_prot() - Return if the DOE instance supports the given
+ *			     protocol
+ * @doe_mb: DOE mailbox capability to query
+ * @vid: Protocol Vendor ID
+ * @type: Protocol type
+ *
+ * RETURNS: True if the DOE mailbox supports the protocol specified
+ */
+bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type)
+{
+	int i;
+
+	/* The discovery protocol must always be supported */
+	if (vid == PCI_VENDOR_ID_PCI_SIG && type == PCI_DOE_PROTOCOL_DISCOVERY)
+		return true;
+
+	for (i = 0; i < doe_mb->num_prots; i++)
+		if ((doe_mb->prots[i].vid == vid) &&
+		    (doe_mb->prots[i].type == type))
+			return true;
+
+	return false;
+}
+EXPORT_SYMBOL_GPL(pci_doe_supports_prot);
+
+/**
+ * pci_doe_submit_task() - Submit a task to be processed by the state machine
+ *
+ * @doe_mb: DOE mailbox capability to submit to
+ * @task: task to be queued
+ *
+ * Submit a DOE task (request/response) to the DOE mailbox to be processed.
+ * Returns upon queueing the task object.  If the queue is full this function
+ * will sleep until there is room in the queue.
+ *
+ * task->complete will be called when the state machine is done processing this
+ * task.
+ *
+ * Excess data will be discarded.
+ *
+ * RETURNS: 0 when task has been successful queued, -ERRNO on error
+ */
+int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task)
+{
+	if (!pci_doe_supports_prot(doe_mb, task->prot.vid, task->prot.type))
+		return -EINVAL;
+
+	/* DOE requests must be a whole number of DW */
+	if (task->request_pl_sz % sizeof(u32))
+		return -EINVAL;
+
+again:
+	mutex_lock(&doe_mb->task_lock);
+	if (doe_mb->cur_task) {
+		mutex_unlock(&doe_mb->task_lock);
+		wait_event_interruptible(doe_mb->wq, doe_mb->cur_task == NULL);
+		goto again;
+	}
+
+	if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags)) {
+		mutex_unlock(&doe_mb->task_lock);
+		return -EIO;
+	}
+	doe_mb->cur_task = task;
+	mutex_unlock(&doe_mb->task_lock);
+	schedule_delayed_work(&doe_mb->statemachine, 0);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(pci_doe_submit_task);
+
+/**
+ * pci_doe_destroy_mb() - Destroy a DOE mailbox object created with
+ * pci_doe_create_mb()
+ *
+ * @doe_mb: DOE mailbox capability structure to destroy
+ *
+ * The mailbox becomes invalid and should not be used after this call.
+ */
+void pci_doe_destroy_mb(struct pci_doe_mb *doe_mb)
+{
+	/* abort any work in progress */
+	pci_doe_abort(doe_mb);
+
+	/* halt the state machine */
+	cancel_delayed_work_sync(&doe_mb->statemachine);
+
+	pci_doe_free_mb(doe_mb);
+}
+EXPORT_SYMBOL_GPL(pci_doe_destroy_mb);
diff --git a/include/linux/pci-doe.h b/include/linux/pci-doe.h
new file mode 100644
index 000000000000..90bd4bfbb809
--- /dev/null
+++ b/include/linux/pci-doe.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Data Object Exchange
+ *	PCIe r6.0, sec 6.30 DOE
+ *
+ * Copyright (C) 2021 Huawei
+ *     Jonathan Cameron <Jonathan.Cameron@huawei.com>
+ *
+ * Copyright (C) 2022 Intel Corporation
+ *	Ira Weiny <ira.weiny@intel.com>
+ */
+
+#ifndef LINUX_PCI_DOE_H
+#define LINUX_PCI_DOE_H
+
+#include <linux/completion.h>
+
+enum pci_doe_state {
+	DOE_IDLE,
+	DOE_WAIT_RESP,
+	DOE_WAIT_ABORT,
+	DOE_WAIT_ABORT_ON_ERR,
+};
+
+#define PCI_DOE_FLAG_ABORT	0
+#define PCI_DOE_FLAG_DEAD	1
+
+struct pci_doe_protocol {
+	u16 vid;
+	u8 type;
+};
+
+/**
+ * struct pci_doe_task - represents a single query/response
+ *
+ * @prot: DOE Protocol
+ * @request_pl: The request payload
+ * @request_pl_sz: Size of the request payload
+ * @response_pl: The response payload
+ * @response_pl_sz: Size of the response payload
+ * @rv: Return value.  Length of received response or error
+ * @complete: Called when task is complete
+ * @private: Private data for the consumer
+ */
+struct pci_doe_task {
+	struct pci_doe_protocol prot;
+	u32 *request_pl;
+	size_t request_pl_sz;
+	u32 *response_pl;
+	size_t response_pl_sz;
+	int rv;
+	void (*complete)(struct pci_doe_task *task);
+	void *private;
+};
+
+/**
+ * struct pci_doe_mb - State for a single DOE mailbox
+ *
+ * This state is used to manage a single DOE mailbox capability.  All fields
+ * should be considered opaque to the consumers and the structure passed into
+ * the helpers below after being created by devm_pci_doe_create()
+ *
+ * @pdev: PCI device this belongs to mailbox belongs to
+ * @abort_c: Completion used for initial abort handling
+ * @irq: Interrupt used for signaling DOE ready or abort
+ * @prots: Array of protocols supported on this DOE
+ * @num_prots: Size of prots array
+ * @cap_offset: Capability offset
+ * @wq: Wait queue to wait on if a query is in progress
+ * @cur_task: Current task the state machine is working on
+ * @task_lock: Protect cur_task
+ * @statemachine: Work item for the DOE state machine
+ * @state: Current state of this DOE
+ * @timeout_jiffies: 1 second after GO set
+ * @busy_retries: Count of retry attempts
+ * @flags: Bit array of PCI_DOE_FLAG_* flags
+ *
+ * Note: prots can't be allocated with struct size because the number of
+ * protocols is not known until after this structure is in use.  However, the
+ * single discovery protocol is always required to query for the number of
+ * protocols.
+ */
+struct pci_doe_mb {
+	struct pci_dev *pdev;
+	struct completion abort_c;
+	int irq;
+	struct pci_doe_protocol *prots;
+	int num_prots;
+	u16 cap_offset;
+
+	wait_queue_head_t wq;
+	struct pci_doe_task *cur_task;
+	struct mutex task_lock;
+	struct delayed_work statemachine;
+	enum pci_doe_state state;
+	unsigned long timeout_jiffies;
+	unsigned int busy_retries;
+	unsigned long flags;
+};
+
+/**
+ * pci_doe_for_each_off - Iterate each DOE capability
+ * @pdev: struct pci_dev to iterate
+ * @off: u16 of config space offset of each mailbox capability found
+ */
+#define pci_doe_for_each_off(pdev, off) \
+	for (off = pci_find_next_ext_capability(pdev, off, \
+					PCI_EXT_CAP_ID_DOE); \
+		off > 0; \
+		off = pci_find_next_ext_capability(pdev, off, \
+					PCI_EXT_CAP_ID_DOE))
+
+int pci_doe_get_irq_num(struct pci_dev *pdev, int offset);
+struct pci_doe_mb *pci_doe_create_mb(struct pci_dev *pdev, u16 cap_offset,
+				     int irq);
+void pci_doe_destroy_mb(struct pci_doe_mb *doe_mb);
+bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type);
+int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task);
+
+#endif
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index bee1a9ed6e66..4e96b45ee36d 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -736,7 +736,8 @@
 #define PCI_EXT_CAP_ID_DVSEC	0x23	/* Designated Vendor-Specific */
 #define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
 #define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
-#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PL_16GT
+#define PCI_EXT_CAP_ID_DOE	0x2E	/* Data Object Exchange */
+#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_DOE
 
 #define PCI_EXT_CAP_DSN_SIZEOF	12
 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
@@ -1102,4 +1103,30 @@
 #define  PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK		0x000000F0
 #define  PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT	4
 
+/* Data Object Exchange */
+#define PCI_DOE_CAP		0x04    /* DOE Capabilities Register */
+#define  PCI_DOE_CAP_INT			0x00000001  /* Interrupt Support */
+#define  PCI_DOE_CAP_IRQ			0x00000ffe  /* Interrupt Message Number */
+#define PCI_DOE_CTRL		0x08    /* DOE Control Register */
+#define  PCI_DOE_CTRL_ABORT			0x00000001  /* DOE Abort */
+#define  PCI_DOE_CTRL_INT_EN			0x00000002  /* DOE Interrupt Enable */
+#define  PCI_DOE_CTRL_GO			0x80000000  /* DOE Go */
+#define PCI_DOE_STATUS		0x0c    /* DOE Status Register */
+#define  PCI_DOE_STATUS_BUSY			0x00000001  /* DOE Busy */
+#define  PCI_DOE_STATUS_INT_STATUS		0x00000002  /* DOE Interrupt Status */
+#define  PCI_DOE_STATUS_ERROR			0x00000004  /* DOE Error */
+#define  PCI_DOE_STATUS_DATA_OBJECT_READY	0x80000000  /* Data Object Ready */
+#define PCI_DOE_WRITE		0x10    /* DOE Write Data Mailbox Register */
+#define PCI_DOE_READ		0x14    /* DOE Read Data Mailbox Register */
+
+/* DOE Data Object - note not actually registers */
+#define PCI_DOE_DATA_OBJECT_HEADER_1_VID		0x0000ffff
+#define PCI_DOE_DATA_OBJECT_HEADER_1_TYPE		0x00ff0000
+#define PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH		0x0003ffff
+
+#define PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX		0x000000ff
+#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID		0x0000ffff
+#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL		0x00ff0000
+#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX	0xff000000
+
 #endif /* LINUX_PCI_REGS_H */
-- 
2.35.1

Re: [PATCH v9 3/9] PCI: Create PCI library functions in support of DOE mailboxes.

[Davidlohr Bueso]

On Tue, 31 May 2022, ira.weiny@intel.com wrote:

>+static void doe_statemachine_work(struct work_struct *work)
>+{
>+	struct delayed_work *w = to_delayed_work(work);
>+	struct pci_doe_mb *doe_mb = container_of(w, struct pci_doe_mb,
>+						 statemachine);
>+	struct pci_dev *pdev = doe_mb->pdev;
>+	int offset = doe_mb->cap_offset;
>+	struct pci_doe_task *task;
>+	u32 val;
>+	int rc;
>+
>+	mutex_lock(&doe_mb->task_lock);
>+	task = doe_mb->cur_task;
>+	mutex_unlock(&doe_mb->task_lock);

Instead of a mutex, would it be better to use a rwsem here to protect
the state machine and allow for concurrent reads for the work callback?
It is a general interface and a trivial change, but not sure how much
performance is cared about.

Thanks,
Davidlohr

Re: [PATCH v9 3/9] PCI: Create PCI library functions in support of DOE mailboxes.

[Davidlohr Bueso]

On Tue, 31 May 2022, Davidlohr Bueso wrote:

>On Tue, 31 May 2022, ira.weiny@intel.com wrote:
>
>>+static void doe_statemachine_work(struct work_struct *work)
>>+{
>>+	struct delayed_work *w = to_delayed_work(work);
>>+	struct pci_doe_mb *doe_mb = container_of(w, struct pci_doe_mb,
>>+						 statemachine);
>>+	struct pci_dev *pdev = doe_mb->pdev;
>>+	int offset = doe_mb->cap_offset;
>>+	struct pci_doe_task *task;
>>+	u32 val;
>>+	int rc;
>>+
>>+	mutex_lock(&doe_mb->task_lock);
>>+	task = doe_mb->cur_task;
>>+	mutex_unlock(&doe_mb->task_lock);
>
>Instead of a mutex, would it be better to use a rwsem here to protect
>the state machine and allow for concurrent reads for the work callback?
>It is a general interface and a trivial change, but not sure how much
>performance is cared about.

Actually why is this a sleeping lock at all? Afaict all critical regions
are short and just deal with loads and stores of oe_mb->task_lock (and
pci_doe_submit_task also checks the doe_mb->flags with the lock held).
This could be a spinlock or similarly a rwlock.

Thanks,
Davidlohr

Re: [PATCH v9 3/9] PCI: Create PCI library functions in support of DOE mailboxes.

[Ira Weiny]

On Tue, May 31, 2022 at 10:56:52AM -0700, Davidlohr Bueso wrote:
> On Tue, 31 May 2022, Davidlohr Bueso wrote:
> 
> > On Tue, 31 May 2022, ira.weiny@intel.com wrote:
> > 
> > > +static void doe_statemachine_work(struct work_struct *work)
> > > +{
> > > +	struct delayed_work *w = to_delayed_work(work);
> > > +	struct pci_doe_mb *doe_mb = container_of(w, struct pci_doe_mb,
> > > +						 statemachine);
> > > +	struct pci_dev *pdev = doe_mb->pdev;
> > > +	int offset = doe_mb->cap_offset;
> > > +	struct pci_doe_task *task;
> > > +	u32 val;
> > > +	int rc;
> > > +
> > > +	mutex_lock(&doe_mb->task_lock);
> > > +	task = doe_mb->cur_task;
> > > +	mutex_unlock(&doe_mb->task_lock);
> > 
> > Instead of a mutex, would it be better to use a rwsem here to protect
> > the state machine and allow for concurrent reads for the work callback?
> > It is a general interface and a trivial change, but not sure how much
> > performance is cared about.
> 
> Actually why is this a sleeping lock at all? Afaict all critical regions
> are short and just deal with loads and stores of oe_mb->task_lock (and
> pci_doe_submit_task also checks the doe_mb->flags with the lock held).
> This could be a spinlock or similarly a rwlock.

This is a good point...  My only excuse is that task_lock used to lock more
than just the cur_task so I suspect that I just kept it as a mutex after a
rework at some point with out thinking about this deeper.

Thinking about it I don't see a benefit to a rwlock.  We don't have multiple
readers.

But I've just looked at this code again and I'm not sure that the exclusion is
correct with regard to the state machine.  I think the state needs to be IDLE
before retire_cur_task() is called or the state machine could be in an invalid
state when the next task runs.  I think there is a bug in the DOE_WAIT_ABORT*
cases when not error and not busy.  In that case there is a race with the next
task getting run the state being DOE_WAIT_ABORT*.  In the timeout case we will
call the mailbox dead.

I can't remember if Jonathan originally locked the state machine or the
task or both.

I think I have fixed it but, I'll look at it again in the morning.

Thanks,
Ira

> 
> Thanks,
> Davidlohr

Re: [PATCH v9 3/9] PCI: Create PCI library functions in support of DOE mailboxes.

[Davidlohr Bueso]

On Tue, 31 May 2022, Ira Weiny wrote:
>Thinking about it I don't see a benefit to a rwlock.  We don't have multiple
>readers.

... but you have concurrent workqueues reading the value of cur_task.

Thanks,
Davidlohr

Re: [PATCH v9 3/9] PCI: Create PCI library functions in support of DOE mailboxes.

[Ira Weiny]

On Wed, Jun 01, 2022 at 06:59:09AM -0700, Davidlohr Bueso wrote:
> On Tue, 31 May 2022, Ira Weiny wrote:
> > Thinking about it I don't see a benefit to a rwlock.  We don't have multiple
> > readers.
> 
> ... but you have concurrent workqueues reading the value of cur_task.

No, concurrent workqueues are reading the value of different DOE mailboxes'
cur_task.  Each mailbox has it's own lock for its current task.

This is a multiple writers to a single reader pattern.  The lock serializes
driver requests (possibly from different threads) into the single mailbox as
well as signaling when the cur_task is done; retire_cur_task().

At the same time multiple mailboxes can be running parallel.

I don't think taking the lock in doe_statemachine_work() is technically
necessary.   But I left it there for completeness because if the queue depth is
increased like it was in Jonathans original code the locking around cur_task
will need to be adjusted in this area.

Ira

> 
> Thanks,
> Davidlohr

[PATCH V9 4/9] cxl/pci: Create PCI DOE mailbox's for memory devices

[ira.weiny]

From: Ira Weiny <ira.weiny@intel.com>

DOE mailbox objects will be needed for various mailbox communications
with each memory device.

Iterate each DOE mailbox capability and create PCI DOE mailbox objects
as found.

It is not anticipated that this is the final resting place for the
iteration of the DOE devices.  The support of ports may drive this code
into the pcie side.  In this imagined architecture the CXL port driver
would then query into the PCI device for the DOE mailbox array.

For now this is good enough for the endpoints and the split is similar
to the envisioned architecture where getting the mailbox array is
separated from the various protocol needs.  For example, it is not
anticipated that the CDAT code will need to move because it is only
needed by the cxl_ports.

Likewise irq's are separated out in a similar design pattern to the
PCIe port driver.  But a much simpler irq enabling flag is used and only
DOE interrupts are supported.

Signed-off-by: Ira Weiny <ira.weiny@intel.com>

---
Changes from V8:
	Move PCI_DOE selection to CXL_BUS to support future patches
	which move queries into the port code.
	Remove Auxiliary device arch
	Squash the functionality of the auxiliary driver into this
	patch.
	Split out the irq handling a bit.

Changes from V7:
	Minor code clean ups
	Rebased on cxl-pending

Changes from V6:
	Move all the auxiliary device stuff to the CXL layer

Changes from V5:
	Split the CXL specific stuff off from the PCI DOE create
	auxiliary device code.
---
 drivers/cxl/Kconfig  |   1 +
 drivers/cxl/cxlmem.h |   6 +++
 drivers/cxl/pci.c    | 111 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 118 insertions(+)

diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index f64e3984689f..7adaaf80b302 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -2,6 +2,7 @@
 menuconfig CXL_BUS
 	tristate "CXL (Compute Express Link) Devices Support"
 	depends on PCI
+	select PCI_DOE
 	help
 	  CXL is a bus that is electrically compatible with PCI Express, but
 	  layers three protocols on that signalling (CXL.io, CXL.cache, and
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 60d10ee1e7fc..4d2764b865ab 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -191,6 +191,8 @@ struct cxl_endpoint_dvsec_info {
  * @component_reg_phys: register base of component registers
  * @info: Cached DVSEC information about the device.
  * @serial: PCIe Device Serial Number
+ * @doe_mbs: PCI DOE mailbox array
+ * @num_mbs: Number of DOE mailboxes
  * @mbox_send: @dev specific transport for transmitting mailbox commands
  *
  * See section 8.2.9.5.2 Capacity Configuration and Label Storage for
@@ -224,6 +226,10 @@ struct cxl_dev_state {
 	resource_size_t component_reg_phys;
 	u64 serial;
 
+	bool doe_use_irq;
+	struct pci_doe_mb **doe_mbs;
+	int num_mbs;
+
 	int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
 };
 
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 5a0ae46d4989..131f89dec8e7 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -8,6 +8,7 @@
 #include <linux/mutex.h>
 #include <linux/list.h>
 #include <linux/pci.h>
+#include <linux/pci-doe.h>
 #include <linux/io.h>
 #include "cxlmem.h"
 #include "cxlpci.h"
@@ -386,6 +387,113 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
 	return rc;
 }
 
+static void cxl_pci_free_irq_vectors(void *data)
+{
+	pci_free_irq_vectors(data);
+}
+
+static void cxl_doe_destroy_mb(void *ds)
+{
+	struct cxl_dev_state *cxlds = ds;
+	int i;
+
+	for (i = 0; i < cxlds->num_mbs; i++) {
+		if (cxlds->doe_mbs[i])
+			pci_doe_destroy_mb(cxlds->doe_mbs[i]);
+	}
+}
+
+static void cxl_alloc_irq_vectors(struct cxl_dev_state *cxlds)
+{
+	struct device *dev = cxlds->dev;
+	struct pci_dev *pdev = to_pci_dev(dev);
+	int num_irqs = 0;
+	int off = 0;
+	int rc;
+
+	/* Account for all the DOE vectors needed */
+	pci_doe_for_each_off(pdev, off) {
+		int irq = pci_doe_get_irq_num(pdev, off);
+
+		if (irq < 0)
+			continue;
+		num_irqs = max(num_irqs, irq + 1);
+	}
+
+	/*
+	 * Allocate enough vectors for the DOE's
+	 */
+	rc = pci_alloc_irq_vectors(pdev, num_irqs, num_irqs, PCI_IRQ_MSI |
+							     PCI_IRQ_MSIX);
+	if (rc != num_irqs) {
+		pci_err(pdev, "Not enough interrupts; use polling\n");
+		/* Some got allocated; clean them up */
+		if (rc > 0)
+			cxl_pci_free_irq_vectors(pdev);
+		cxlds->doe_use_irq = false;
+		return;
+	}
+
+	rc = devm_add_action_or_reset(dev, cxl_pci_free_irq_vectors, pdev);
+	if (rc) {
+		cxlds->doe_use_irq = false;
+		return;
+	}
+
+	cxlds->doe_use_irq = true;
+}
+
+/**
+ * devm_cxl_pci_create_doe - Scan and set up DOE mailboxes
+ *
+ * @cxlds: The CXL device state
+ *
+ * RETURNS: 0 on success -ERRNO on failure.
+ */
+static int devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds)
+{
+	struct device *dev = cxlds->dev;
+	struct pci_dev *pdev = to_pci_dev(dev);
+	u16 off = 0;
+	int num_mbs = 0;
+	int rc;
+
+	pci_doe_for_each_off(pdev, off)
+		num_mbs++;
+
+	cxlds->doe_mbs = devm_kcalloc(dev, num_mbs, sizeof(*cxlds->doe_mbs),
+				      GFP_KERNEL);
+	if (!cxlds->doe_mbs)
+		return -ENOMEM;
+
+	pci_doe_for_each_off(pdev, off) {
+		struct pci_doe_mb *doe_mb;
+		int irq = -1;
+
+		if (cxlds->doe_use_irq)
+			irq = pci_doe_get_irq_num(pdev, off);
+
+		doe_mb = pci_doe_create_mb(pdev, off, irq);
+		if (IS_ERR(doe_mb)) {
+			pci_err(pdev,
+				"Failed to create MB object for MB @ %x\n",
+				off);
+			doe_mb = NULL;
+		}
+
+		cxlds->doe_mbs[cxlds->num_mbs] = doe_mb;
+		cxlds->num_mbs++;
+	}
+
+	rc = devm_add_action_or_reset(dev, cxl_doe_destroy_mb, cxlds);
+	if (rc)
+		return rc;
+
+	pci_info(pdev, "Configured %d DOE mailbox's\n", cxlds->num_mbs);
+
+	return 0;
+}
+
 static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
 	struct cxl_register_map map;
@@ -454,6 +562,9 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	if (IS_ERR(cxlmd))
 		return PTR_ERR(cxlmd);
 
+	cxl_alloc_irq_vectors(cxlds);
+	devm_cxl_pci_create_doe(cxlds);
+
 	if (range_len(&cxlds->pmem_range) && IS_ENABLED(CONFIG_CXL_PMEM))
 		rc = devm_cxl_add_nvdimm(&pdev->dev, cxlmd);
 
-- 
2.35.1

Re: [PATCH V9 4/9] cxl/pci: Create PCI DOE mailbox's for memory devices

[Ben Widawsky]

On 22-05-31 08:26:27, ira.weiny@intel.com wrote:
> From: Ira Weiny <ira.weiny@intel.com>
> 
> DOE mailbox objects will be needed for various mailbox communications
> with each memory device.
> 
> Iterate each DOE mailbox capability and create PCI DOE mailbox objects
> as found.
> 
> It is not anticipated that this is the final resting place for the
> iteration of the DOE devices.  The support of ports may drive this code
> into the pcie side.  In this imagined architecture the CXL port driver
> would then query into the PCI device for the DOE mailbox array.

Not sure if direction has changed, but initially it would have been the cxl_pci
driver who would query this and pass it along when the port driver probes.
Personally, I've never had an issue with non cxl_pci drivers using PCI
interfaces and semantics, but it is something we've taken specific care to
avoid.

> 
> For now this is good enough for the endpoints and the split is similar
> to the envisioned architecture where getting the mailbox array is
> separated from the various protocol needs.  For example, it is not
> anticipated that the CDAT code will need to move because it is only
> needed by the cxl_ports.
> 
> Likewise irq's are separated out in a similar design pattern to the
> PCIe port driver.  But a much simpler irq enabling flag is used and only
> DOE interrupts are supported.
> 
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> 
> ---
> Changes from V8:
> 	Move PCI_DOE selection to CXL_BUS to support future patches
> 	which move queries into the port code.
> 	Remove Auxiliary device arch
> 	Squash the functionality of the auxiliary driver into this
> 	patch.
> 	Split out the irq handling a bit.
> 
> Changes from V7:
> 	Minor code clean ups
> 	Rebased on cxl-pending
> 
> Changes from V6:
> 	Move all the auxiliary device stuff to the CXL layer
> 
> Changes from V5:
> 	Split the CXL specific stuff off from the PCI DOE create
> 	auxiliary device code.
> ---
>  drivers/cxl/Kconfig  |   1 +
>  drivers/cxl/cxlmem.h |   6 +++
>  drivers/cxl/pci.c    | 111 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 118 insertions(+)
> 
> diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> index f64e3984689f..7adaaf80b302 100644
> --- a/drivers/cxl/Kconfig
> +++ b/drivers/cxl/Kconfig
> @@ -2,6 +2,7 @@
>  menuconfig CXL_BUS
>  	tristate "CXL (Compute Express Link) Devices Support"
>  	depends on PCI
> +	select PCI_DOE
>  	help
>  	  CXL is a bus that is electrically compatible with PCI Express, but
>  	  layers three protocols on that signalling (CXL.io, CXL.cache, and
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 60d10ee1e7fc..4d2764b865ab 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -191,6 +191,8 @@ struct cxl_endpoint_dvsec_info {
>   * @component_reg_phys: register base of component registers
>   * @info: Cached DVSEC information about the device.
>   * @serial: PCIe Device Serial Number
> + * @doe_mbs: PCI DOE mailbox array
> + * @num_mbs: Number of DOE mailboxes
>   * @mbox_send: @dev specific transport for transmitting mailbox commands
>   *
>   * See section 8.2.9.5.2 Capacity Configuration and Label Storage for
> @@ -224,6 +226,10 @@ struct cxl_dev_state {
>  	resource_size_t component_reg_phys;
>  	u64 serial;
>  
> +	bool doe_use_irq;
> +	struct pci_doe_mb **doe_mbs;
> +	int num_mbs;
> +
>  	int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
>  };
>  
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 5a0ae46d4989..131f89dec8e7 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -8,6 +8,7 @@
>  #include <linux/mutex.h>
>  #include <linux/list.h>
>  #include <linux/pci.h>
> +#include <linux/pci-doe.h>
>  #include <linux/io.h>
>  #include "cxlmem.h"
>  #include "cxlpci.h"
> @@ -386,6 +387,113 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
>  	return rc;
>  }
>  
> +static void cxl_pci_free_irq_vectors(void *data)
> +{
> +	pci_free_irq_vectors(data);
> +}
> +
> +static void cxl_doe_destroy_mb(void *ds)
> +{
> +	struct cxl_dev_state *cxlds = ds;
> +	int i;
> +
> +	for (i = 0; i < cxlds->num_mbs; i++) {
> +		if (cxlds->doe_mbs[i])
> +			pci_doe_destroy_mb(cxlds->doe_mbs[i]);
> +	}
> +}
> +
> +static void cxl_alloc_irq_vectors(struct cxl_dev_state *cxlds)
> +{
> +	struct device *dev = cxlds->dev;
> +	struct pci_dev *pdev = to_pci_dev(dev);
> +	int num_irqs = 0;
> +	int off = 0;
> +	int rc;
> +
> +	/* Account for all the DOE vectors needed */
> +	pci_doe_for_each_off(pdev, off) {
> +		int irq = pci_doe_get_irq_num(pdev, off);
> +
> +		if (irq < 0)
> +			continue;
> +		num_irqs = max(num_irqs, irq + 1);

This seems overly complicated. Isn't it just num_irqs++?

> +	}
> +
> +	/*
> +	 * Allocate enough vectors for the DOE's
> +	 */
> +	rc = pci_alloc_irq_vectors(pdev, num_irqs, num_irqs, PCI_IRQ_MSI |
> +							     PCI_IRQ_MSIX);
> +	if (rc != num_irqs) {
> +		pci_err(pdev, "Not enough interrupts; use polling\n");
> +		/* Some got allocated; clean them up */
> +		if (rc > 0)
> +			cxl_pci_free_irq_vectors(pdev);
> +		cxlds->doe_use_irq = false;
> +		return;
> +	}
> +
> +	rc = devm_add_action_or_reset(dev, cxl_pci_free_irq_vectors, pdev);
> +	if (rc) {
> +		cxlds->doe_use_irq = false;
> +		return;
> +	}
> +
> +	cxlds->doe_use_irq = true;

If you named it doe_poll, you could avoid having to do anything at the end of
the function... If you felt like it.

if (failure)
	return;
if (other_failure)
	return;

cxld->do_use_poll = false;

> +}
> +
> +/**
> + * devm_cxl_pci_create_doe - Scan and set up DOE mailboxes
> + *
> + * @cxlds: The CXL device state
> + *
> + * RETURNS: 0 on success -ERRNO on failure.
> + */
> +static int devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds)
> +{
> +	struct device *dev = cxlds->dev;
> +	struct pci_dev *pdev = to_pci_dev(dev);
> +	u16 off = 0;
> +	int num_mbs = 0;
> +	int rc;
> +
> +	pci_doe_for_each_off(pdev, off)
> +		num_mbs++;
> +

Do you want to bail here if num_mbs == 0?

> +	cxlds->doe_mbs = devm_kcalloc(dev, num_mbs, sizeof(*cxlds->doe_mbs),
> +				      GFP_KERNEL);
> +	if (!cxlds->doe_mbs)
> +		return -ENOMEM;
> +
> +	pci_doe_for_each_off(pdev, off) {
> +		struct pci_doe_mb *doe_mb;
> +		int irq = -1;
> +
> +		if (cxlds->doe_use_irq)
> +			irq = pci_doe_get_irq_num(pdev, off);
> +
> +		doe_mb = pci_doe_create_mb(pdev, off, irq);
> +		if (IS_ERR(doe_mb)) {
> +			pci_err(pdev,
> +				"Failed to create MB object for MB @ %x\n",
> +				off);
> +			doe_mb = NULL;
> +		}
> +
> +		cxlds->doe_mbs[cxlds->num_mbs] = doe_mb;
> +		cxlds->num_mbs++;
> +	}
> +
> +	rc = devm_add_action_or_reset(dev, cxl_doe_destroy_mb, cxlds);
> +	if (rc)
> +		return rc;
> +
> +	pci_info(pdev, "Configured %d DOE mailbox's\n", cxlds->num_mbs);
> +
> +	return 0;
> +}
> +
>  static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>  {
>  	struct cxl_register_map map;
> @@ -454,6 +562,9 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>  	if (IS_ERR(cxlmd))
>  		return PTR_ERR(cxlmd);
>  
> +	cxl_alloc_irq_vectors(cxlds);
> +	devm_cxl_pci_create_doe(cxlds);

If you're not going to check the return value, just make the functions void.

> +
>  	if (range_len(&cxlds->pmem_range) && IS_ENABLED(CONFIG_CXL_PMEM))
>  		rc = devm_cxl_add_nvdimm(&pdev->dev, cxlmd);
>  
> -- 
> 2.35.1
> 

Re: [PATCH V9 4/9] cxl/pci: Create PCI DOE mailbox's for memory devices

[Jonathan Cameron]

On Tue, 31 May 2022 10:50:20 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> On 22-05-31 08:26:27, ira.weiny@intel.com wrote:
> > From: Ira Weiny <ira.weiny@intel.com>
> > 
> > DOE mailbox objects will be needed for various mailbox communications
> > with each memory device.
> > 
> > Iterate each DOE mailbox capability and create PCI DOE mailbox objects
> > as found.
> > 
> > It is not anticipated that this is the final resting place for the
> > iteration of the DOE devices.  The support of ports may drive this code
> > into the pcie side.  In this imagined architecture the CXL port driver
> > would then query into the PCI device for the DOE mailbox array.  
> 
> Not sure if direction has changed, but initially it would have been the cxl_pci
> driver who would query this and pass it along when the port driver probes.
> Personally, I've never had an issue with non cxl_pci drivers using PCI
> interfaces and semantics, but it is something we've taken specific care to
> avoid.
> 
> > 
> > For now this is good enough for the endpoints and the split is similar
> > to the envisioned architecture where getting the mailbox array is
> > separated from the various protocol needs.  For example, it is not
> > anticipated that the CDAT code will need to move because it is only
> > needed by the cxl_ports.
> > 
> > Likewise irq's are separated out in a similar design pattern to the
> > PCIe port driver.  But a much simpler irq enabling flag is used and only
> > DOE interrupts are supported.
> > 
> > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> > 
> > ---
> > Changes from V8:
> > 	Move PCI_DOE selection to CXL_BUS to support future patches
> > 	which move queries into the port code.
> > 	Remove Auxiliary device arch
> > 	Squash the functionality of the auxiliary driver into this
> > 	patch.
> > 	Split out the irq handling a bit.
> > 
> > Changes from V7:
> > 	Minor code clean ups
> > 	Rebased on cxl-pending
> > 
> > Changes from V6:
> > 	Move all the auxiliary device stuff to the CXL layer
> > 
> > Changes from V5:
> > 	Split the CXL specific stuff off from the PCI DOE create
> > 	auxiliary device code.
> > ---
> >  drivers/cxl/Kconfig  |   1 +
> >  drivers/cxl/cxlmem.h |   6 +++
> >  drivers/cxl/pci.c    | 111 +++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 118 insertions(+)
> > 
> > diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> > index f64e3984689f..7adaaf80b302 100644
> > --- a/drivers/cxl/Kconfig
> > +++ b/drivers/cxl/Kconfig
> > @@ -2,6 +2,7 @@
> >  menuconfig CXL_BUS
> >  	tristate "CXL (Compute Express Link) Devices Support"
> >  	depends on PCI
> > +	select PCI_DOE
> >  	help
> >  	  CXL is a bus that is electrically compatible with PCI Express, but
> >  	  layers three protocols on that signalling (CXL.io, CXL.cache, and
> > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> > index 60d10ee1e7fc..4d2764b865ab 100644
> > --- a/drivers/cxl/cxlmem.h
> > +++ b/drivers/cxl/cxlmem.h
> > @@ -191,6 +191,8 @@ struct cxl_endpoint_dvsec_info {
> >   * @component_reg_phys: register base of component registers
> >   * @info: Cached DVSEC information about the device.
> >   * @serial: PCIe Device Serial Number
> > + * @doe_mbs: PCI DOE mailbox array
> > + * @num_mbs: Number of DOE mailboxes
> >   * @mbox_send: @dev specific transport for transmitting mailbox commands
> >   *
> >   * See section 8.2.9.5.2 Capacity Configuration and Label Storage for
> > @@ -224,6 +226,10 @@ struct cxl_dev_state {
> >  	resource_size_t component_reg_phys;
> >  	u64 serial;
> >  
> > +	bool doe_use_irq;
> > +	struct pci_doe_mb **doe_mbs;
> > +	int num_mbs;
> > +
> >  	int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
> >  };
> >  
> > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> > index 5a0ae46d4989..131f89dec8e7 100644
> > --- a/drivers/cxl/pci.c
> > +++ b/drivers/cxl/pci.c
> > @@ -8,6 +8,7 @@
> >  #include <linux/mutex.h>
> >  #include <linux/list.h>
> >  #include <linux/pci.h>
> > +#include <linux/pci-doe.h>
> >  #include <linux/io.h>
> >  #include "cxlmem.h"
> >  #include "cxlpci.h"
> > @@ -386,6 +387,113 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> >  	return rc;
> >  }
> >  
> > +static void cxl_pci_free_irq_vectors(void *data)
> > +{
> > +	pci_free_irq_vectors(data);
> > +}
> > +
> > +static void cxl_doe_destroy_mb(void *ds)
> > +{
> > +	struct cxl_dev_state *cxlds = ds;
> > +	int i;
> > +
> > +	for (i = 0; i < cxlds->num_mbs; i++) {
> > +		if (cxlds->doe_mbs[i])
> > +			pci_doe_destroy_mb(cxlds->doe_mbs[i]);
> > +	}
> > +}
> > +
> > +static void cxl_alloc_irq_vectors(struct cxl_dev_state *cxlds)
> > +{
> > +	struct device *dev = cxlds->dev;
> > +	struct pci_dev *pdev = to_pci_dev(dev);
> > +	int num_irqs = 0;
> > +	int off = 0;
> > +	int rc;
> > +
> > +	/* Account for all the DOE vectors needed */
> > +	pci_doe_for_each_off(pdev, off) {
> > +		int irq = pci_doe_get_irq_num(pdev, off);
> > +
> > +		if (irq < 0)
> > +			continue;
> > +		num_irqs = max(num_irqs, irq + 1);  
> 
> This seems overly complicated. Isn't it just num_irqs++?

nope.  

There is no guarantee the irq values are near zero or contiguous.

If irq is 33 for example, it pretty much implies that there are 34 or more irq
vectors used for something on this device, but we don't know what the rest are for.

Trick is used in portdrv to deal with enabling all the irqs needed for the various
supported services, which might not be all the irqs the hardware provides.

Maybe worth renaming num_irqs as max_irq or something like that and postpone the +1 to
where it is used?

Jonathan

> 
> > +	}

Re: [PATCH V9 4/9] cxl/pci: Create PCI DOE mailbox's for memory devices

[Ira Weiny]

On Tue, May 31, 2022 at 10:50:20AM -0700, Ben Widawsky wrote:
> On 22-05-31 08:26:27, ira.weiny@intel.com wrote:
> > From: Ira Weiny <ira.weiny@intel.com>
> > 
> > DOE mailbox objects will be needed for various mailbox communications
> > with each memory device.
> > 
> > Iterate each DOE mailbox capability and create PCI DOE mailbox objects
> > as found.
> > 
> > It is not anticipated that this is the final resting place for the
> > iteration of the DOE devices.  The support of ports may drive this code
> > into the pcie side.  In this imagined architecture the CXL port driver
> > would then query into the PCI device for the DOE mailbox array.
> 
> Not sure if direction has changed, but initially it would have been the cxl_pci
> driver who would query this and pass it along when the port driver probes.
> Personally, I've never had an issue with non cxl_pci drivers using PCI
> interfaces and semantics, but it is something we've taken specific care to
> avoid.

I really struggled with this and this is why the comment above was added.  I
agree with you but I think this actually belongs somewhere in the PCI code
eventually and the cxl_port should be grabbing the CDAT mailbox from there.

I really think that having the PCIe port driver iterate the DOE mailboxes and
then having either CXL or PCIe find the mailboxes they are interested in is the
way to go.

But this supports mailbox end points for now.

> 
> > 
> > For now this is good enough for the endpoints and the split is similar
> > to the envisioned architecture where getting the mailbox array is
> > separated from the various protocol needs.  For example, it is not
> > anticipated that the CDAT code will need to move because it is only
> > needed by the cxl_ports.
> > 
> > Likewise irq's are separated out in a similar design pattern to the
> > PCIe port driver.  But a much simpler irq enabling flag is used and only
> > DOE interrupts are supported.
> > 
> > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> > 
> > ---
> > Changes from V8:
> > 	Move PCI_DOE selection to CXL_BUS to support future patches
> > 	which move queries into the port code.
> > 	Remove Auxiliary device arch
> > 	Squash the functionality of the auxiliary driver into this
> > 	patch.
> > 	Split out the irq handling a bit.
> > 
> > Changes from V7:
> > 	Minor code clean ups
> > 	Rebased on cxl-pending
> > 
> > Changes from V6:
> > 	Move all the auxiliary device stuff to the CXL layer
> > 
> > Changes from V5:
> > 	Split the CXL specific stuff off from the PCI DOE create
> > 	auxiliary device code.
> > ---
> >  drivers/cxl/Kconfig  |   1 +
> >  drivers/cxl/cxlmem.h |   6 +++
> >  drivers/cxl/pci.c    | 111 +++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 118 insertions(+)
> > 
> > diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> > index f64e3984689f..7adaaf80b302 100644
> > --- a/drivers/cxl/Kconfig
> > +++ b/drivers/cxl/Kconfig
> > @@ -2,6 +2,7 @@
> >  menuconfig CXL_BUS
> >  	tristate "CXL (Compute Express Link) Devices Support"
> >  	depends on PCI
> > +	select PCI_DOE
> >  	help
> >  	  CXL is a bus that is electrically compatible with PCI Express, but
> >  	  layers three protocols on that signalling (CXL.io, CXL.cache, and
> > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> > index 60d10ee1e7fc..4d2764b865ab 100644
> > --- a/drivers/cxl/cxlmem.h
> > +++ b/drivers/cxl/cxlmem.h
> > @@ -191,6 +191,8 @@ struct cxl_endpoint_dvsec_info {
> >   * @component_reg_phys: register base of component registers
> >   * @info: Cached DVSEC information about the device.
> >   * @serial: PCIe Device Serial Number
> > + * @doe_mbs: PCI DOE mailbox array
> > + * @num_mbs: Number of DOE mailboxes
> >   * @mbox_send: @dev specific transport for transmitting mailbox commands
> >   *
> >   * See section 8.2.9.5.2 Capacity Configuration and Label Storage for
> > @@ -224,6 +226,10 @@ struct cxl_dev_state {
> >  	resource_size_t component_reg_phys;
> >  	u64 serial;
> >  
> > +	bool doe_use_irq;
> > +	struct pci_doe_mb **doe_mbs;
> > +	int num_mbs;
> > +
> >  	int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
> >  };
> >  
> > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> > index 5a0ae46d4989..131f89dec8e7 100644
> > --- a/drivers/cxl/pci.c
> > +++ b/drivers/cxl/pci.c
> > @@ -8,6 +8,7 @@
> >  #include <linux/mutex.h>
> >  #include <linux/list.h>
> >  #include <linux/pci.h>
> > +#include <linux/pci-doe.h>
> >  #include <linux/io.h>
> >  #include "cxlmem.h"
> >  #include "cxlpci.h"
> > @@ -386,6 +387,113 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> >  	return rc;
> >  }
> >  
> > +static void cxl_pci_free_irq_vectors(void *data)
> > +{
> > +	pci_free_irq_vectors(data);
> > +}
> > +
> > +static void cxl_doe_destroy_mb(void *ds)
> > +{
> > +	struct cxl_dev_state *cxlds = ds;
> > +	int i;
> > +
> > +	for (i = 0; i < cxlds->num_mbs; i++) {
> > +		if (cxlds->doe_mbs[i])
> > +			pci_doe_destroy_mb(cxlds->doe_mbs[i]);
> > +	}
> > +}
> > +
> > +static void cxl_alloc_irq_vectors(struct cxl_dev_state *cxlds)
> > +{
> > +	struct device *dev = cxlds->dev;
> > +	struct pci_dev *pdev = to_pci_dev(dev);
> > +	int num_irqs = 0;
> > +	int off = 0;
> > +	int rc;
> > +
> > +	/* Account for all the DOE vectors needed */
> > +	pci_doe_for_each_off(pdev, off) {
> > +		int irq = pci_doe_get_irq_num(pdev, off);
> > +
> > +		if (irq < 0)
> > +			continue;
> > +		num_irqs = max(num_irqs, irq + 1);
> 
> This seems overly complicated. Isn't it just num_irqs++?

See Jonathan's comment.  But I'll change it to 'max_irqs'.

> 
> > +	}
> > +
> > +	/*
> > +	 * Allocate enough vectors for the DOE's
> > +	 */
> > +	rc = pci_alloc_irq_vectors(pdev, num_irqs, num_irqs, PCI_IRQ_MSI |
> > +							     PCI_IRQ_MSIX);
> > +	if (rc != num_irqs) {
> > +		pci_err(pdev, "Not enough interrupts; use polling\n");
> > +		/* Some got allocated; clean them up */
> > +		if (rc > 0)
> > +			cxl_pci_free_irq_vectors(pdev);
> > +		cxlds->doe_use_irq = false;
> > +		return;
> > +	}
> > +
> > +	rc = devm_add_action_or_reset(dev, cxl_pci_free_irq_vectors, pdev);
> > +	if (rc) {
> > +		cxlds->doe_use_irq = false;
> > +		return;
> > +	}
> > +
> > +	cxlds->doe_use_irq = true;
> 
> If you named it doe_poll, you could avoid having to do anything at the end of
> the function... If you felt like it.
> 
> if (failure)
> 	return;
> if (other_failure)
> 	return;
> 
> cxld->do_use_poll = false;

Actually I could just set false at the top and return on error.

Thanks for the suggestion.

> 
> > +}
> > +
> > +/**
> > + * devm_cxl_pci_create_doe - Scan and set up DOE mailboxes
> > + *
> > + * @cxlds: The CXL device state
> > + *
> > + * RETURNS: 0 on success -ERRNO on failure.
> > + */
> > +static int devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds)
> > +{
> > +	struct device *dev = cxlds->dev;
> > +	struct pci_dev *pdev = to_pci_dev(dev);
> > +	u16 off = 0;
> > +	int num_mbs = 0;
> > +	int rc;
> > +
> > +	pci_doe_for_each_off(pdev, off)
> > +		num_mbs++;
> > +
> 
> Do you want to bail here if num_mbs == 0?

I do!  Thanks.  I need to skip using irq's above if none are found too.

> 
> > +	cxlds->doe_mbs = devm_kcalloc(dev, num_mbs, sizeof(*cxlds->doe_mbs),
> > +				      GFP_KERNEL);
> > +	if (!cxlds->doe_mbs)
> > +		return -ENOMEM;
> > +
> > +	pci_doe_for_each_off(pdev, off) {
> > +		struct pci_doe_mb *doe_mb;
> > +		int irq = -1;
> > +
> > +		if (cxlds->doe_use_irq)
> > +			irq = pci_doe_get_irq_num(pdev, off);
> > +
> > +		doe_mb = pci_doe_create_mb(pdev, off, irq);
> > +		if (IS_ERR(doe_mb)) {
> > +			pci_err(pdev,
> > +				"Failed to create MB object for MB @ %x\n",
> > +				off);
> > +			doe_mb = NULL;
> > +		}
> > +
> > +		cxlds->doe_mbs[cxlds->num_mbs] = doe_mb;
> > +		cxlds->num_mbs++;
> > +	}
> > +
> > +	rc = devm_add_action_or_reset(dev, cxl_doe_destroy_mb, cxlds);
> > +	if (rc)
> > +		return rc;
> > +
> > +	pci_info(pdev, "Configured %d DOE mailbox's\n", cxlds->num_mbs);
> > +
> > +	return 0;
> > +}
> > +
> >  static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> >  {
> >  	struct cxl_register_map map;
> > @@ -454,6 +562,9 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> >  	if (IS_ERR(cxlmd))
> >  		return PTR_ERR(cxlmd);
> >  
> > +	cxl_alloc_irq_vectors(cxlds);
> > +	devm_cxl_pci_create_doe(cxlds);
> 
> If you're not going to check the return value, just make the functions void.

Yea too much rework and I forgot this.

Thanks,
Ira

> 
> > +
> >  	if (range_len(&cxlds->pmem_range) && IS_ENABLED(CONFIG_CXL_PMEM))
> >  		rc = devm_cxl_add_nvdimm(&pdev->dev, cxlmd);
> >  
> > -- 
> > 2.35.1
> > 

[PATCH V9 5/9] cxl/port: Find a DOE mailbox which supports CDAT

[ira.weiny]

From: Ira Weiny <ira.weiny@intel.com>

Each CXL device may have multiple DOE mailbox capabilities and each
mailbox may support multiple protocols.  CXL port devices need to query
the CDAT information specifically.

Search the DOE mailboxes for one which supports the CDAT protocol.
Cache that mailbox to be used for future queries.

Only support memory devices at this time.

Signed-off-by: Ira Weiny <ira.weiny@intel.com>

---
Changes from V8
	Incorporate feedback from Jonathan
	Move all this to the cxl_port object

Changes from V7
	Minor code clean ups

Changes from V6
	Adjust for aux devices being a CXL only concept
	Update commit msg.
	Ensure devices iterated by auxiliary_find_device() are checked
		to be DOE devices prior to checking for the CDAT
		protocol
	From Ben
		Ensure reference from auxiliary_find_device() is dropped
---
 drivers/cxl/core/pci.c  | 28 ++++++++++++++++++++++++++++
 drivers/cxl/core/port.c |  2 ++
 drivers/cxl/cxl.h       |  2 ++
 drivers/cxl/cxlpci.h    |  1 +
 4 files changed, 33 insertions(+)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index c4c99ff7b55e..5497a65bdcf3 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -4,11 +4,14 @@
 #include <linux/device.h>
 #include <linux/delay.h>
 #include <linux/pci.h>
+#include <linux/pci-doe.h>
 #include <cxlpci.h>
 #include <cxlmem.h>
 #include <cxl.h>
 #include "core.h"
 
+#define CXL_DOE_PROTOCOL_TABLE_ACCESS 2
+
 /**
  * DOC: cxl core pci
  *
@@ -458,3 +461,28 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm)
 	return 0;
 }
 EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);
+
+void cxl_find_cdat_mb(struct cxl_port *port)
+{
+	struct device *dev = port->uport;
+	struct cxl_memdev *cxlmd;
+	struct cxl_dev_state *cxlds;
+	int i;
+
+	if (!is_cxl_memdev(dev))
+		return;
+
+	cxlmd = to_cxl_memdev(dev);
+	cxlds = cxlmd->cxlds;
+
+	for (i = 0; i < cxlds->num_mbs; i++) {
+		struct pci_doe_mb *cur = cxlds->doe_mbs[i];
+
+		if (pci_doe_supports_prot(cur, PCI_DVSEC_VENDOR_ID_CXL,
+					  CXL_DOE_PROTOCOL_TABLE_ACCESS)) {
+			port->cdat_mb = cur;
+			return;
+		}
+	}
+}
+EXPORT_SYMBOL_NS_GPL(cxl_find_cdat_mb, CXL);
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index ea60abda6500..2e2bd65c1024 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -461,6 +461,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
 	if (IS_ERR(port))
 		return port;
 
+	cxl_find_cdat_mb(port);
+
 	dev = &port->dev;
 	if (is_cxl_memdev(uport))
 		rc = dev_set_name(dev, "endpoint%d", port->id);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 140dc3278cde..0a86be589ffc 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -267,6 +267,7 @@ struct cxl_nvdimm {
  * @component_reg_phys: component register capability base address (optional)
  * @dead: last ep has been removed, force port re-creation
  * @depth: How deep this port is relative to the root. depth 0 is the root.
+ * @cdat_mb: Mailbox which supports the CDAT protocol
  */
 struct cxl_port {
 	struct device dev;
@@ -278,6 +279,7 @@ struct cxl_port {
 	resource_size_t component_reg_phys;
 	bool dead;
 	unsigned int depth;
+	struct pci_doe_mb *cdat_mb;
 };
 
 /**
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index fce1c11729c2..366b21bd1a01 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -74,4 +74,5 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
 int devm_cxl_port_enumerate_dports(struct cxl_port *port);
 struct cxl_dev_state;
 int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
+void cxl_find_cdat_mb(struct cxl_port *port);
 #endif /* __CXL_PCI_H__ */
-- 
2.35.1

Re: [PATCH V9 5/9] cxl/port: Find a DOE mailbox which supports CDAT

[Ben Widawsky]

On 22-05-31 08:26:28, ira.weiny@intel.com wrote:
> From: Ira Weiny <ira.weiny@intel.com>
> 
> Each CXL device may have multiple DOE mailbox capabilities and each
> mailbox may support multiple protocols.  CXL port devices need to query
> the CDAT information specifically.
> 
> Search the DOE mailboxes for one which supports the CDAT protocol.
> Cache that mailbox to be used for future queries.
> 
> Only support memory devices at this time.
> 
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> 
> ---
> Changes from V8
> 	Incorporate feedback from Jonathan
> 	Move all this to the cxl_port object
> 
> Changes from V7
> 	Minor code clean ups
> 
> Changes from V6
> 	Adjust for aux devices being a CXL only concept
> 	Update commit msg.
> 	Ensure devices iterated by auxiliary_find_device() are checked
> 		to be DOE devices prior to checking for the CDAT
> 		protocol
> 	From Ben
> 		Ensure reference from auxiliary_find_device() is dropped
> ---
>  drivers/cxl/core/pci.c  | 28 ++++++++++++++++++++++++++++
>  drivers/cxl/core/port.c |  2 ++
>  drivers/cxl/cxl.h       |  2 ++
>  drivers/cxl/cxlpci.h    |  1 +
>  4 files changed, 33 insertions(+)
> 
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index c4c99ff7b55e..5497a65bdcf3 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -4,11 +4,14 @@
>  #include <linux/device.h>
>  #include <linux/delay.h>
>  #include <linux/pci.h>
> +#include <linux/pci-doe.h>
>  #include <cxlpci.h>
>  #include <cxlmem.h>
>  #include <cxl.h>
>  #include "core.h"
>  
> +#define CXL_DOE_PROTOCOL_TABLE_ACCESS 2
> +
>  /**
>   * DOC: cxl core pci
>   *
> @@ -458,3 +461,28 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm)
>  	return 0;
>  }
>  EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);
> +
> +void cxl_find_cdat_mb(struct cxl_port *port)

kdoc would be good for exported symbols IMO. Also if you can come up with a
better verb than "find" for something that mutates the port's state, I think
that would be beneficial.

I'm not sure why this is exported yet, but I suppose I'll see soon :-)

> +{
> +	struct device *dev = port->uport;
> +	struct cxl_memdev *cxlmd;
> +	struct cxl_dev_state *cxlds;
> +	int i;
> +
> +	if (!is_cxl_memdev(dev))
> +		return;
> +
> +	cxlmd = to_cxl_memdev(dev);
> +	cxlds = cxlmd->cxlds;
> +
> +	for (i = 0; i < cxlds->num_mbs; i++) {
> +		struct pci_doe_mb *cur = cxlds->doe_mbs[i];
> +
> +		if (pci_doe_supports_prot(cur, PCI_DVSEC_VENDOR_ID_CXL,
> +					  CXL_DOE_PROTOCOL_TABLE_ACCESS)) {
> +			port->cdat_mb = cur;
> +			return;
> +		}
> +	}
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_find_cdat_mb, CXL);
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index ea60abda6500..2e2bd65c1024 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -461,6 +461,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
>  	if (IS_ERR(port))
>  		return port;
>  
> +	cxl_find_cdat_mb(port);
> +
>  	dev = &port->dev;
>  	if (is_cxl_memdev(uport))
>  		rc = dev_set_name(dev, "endpoint%d", port->id);
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 140dc3278cde..0a86be589ffc 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -267,6 +267,7 @@ struct cxl_nvdimm {
>   * @component_reg_phys: component register capability base address (optional)
>   * @dead: last ep has been removed, force port re-creation
>   * @depth: How deep this port is relative to the root. depth 0 is the root.
> + * @cdat_mb: Mailbox which supports the CDAT protocol
>   */
>  struct cxl_port {
>  	struct device dev;
> @@ -278,6 +279,7 @@ struct cxl_port {
>  	resource_size_t component_reg_phys;
>  	bool dead;
>  	unsigned int depth;
> +	struct pci_doe_mb *cdat_mb;
>  };
>  
>  /**
> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> index fce1c11729c2..366b21bd1a01 100644
> --- a/drivers/cxl/cxlpci.h
> +++ b/drivers/cxl/cxlpci.h
> @@ -74,4 +74,5 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
>  int devm_cxl_port_enumerate_dports(struct cxl_port *port);
>  struct cxl_dev_state;
>  int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
> +void cxl_find_cdat_mb(struct cxl_port *port);
>  #endif /* __CXL_PCI_H__ */
> -- 
> 2.35.1
> 

Re: [PATCH V9 5/9] cxl/port: Find a DOE mailbox which supports CDAT

[Ira Weiny]

On Tue, May 31, 2022 at 10:57:16AM -0700, Ben Widawsky wrote:
> On 22-05-31 08:26:28, ira.weiny@intel.com wrote:
> > From: Ira Weiny <ira.weiny@intel.com>
> > 
> > Each CXL device may have multiple DOE mailbox capabilities and each
> > mailbox may support multiple protocols.  CXL port devices need to query
> > the CDAT information specifically.
> > 
> > Search the DOE mailboxes for one which supports the CDAT protocol.
> > Cache that mailbox to be used for future queries.
> > 
> > Only support memory devices at this time.
> > 
> > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> > 
> > ---
> > Changes from V8
> > 	Incorporate feedback from Jonathan
> > 	Move all this to the cxl_port object
> > 
> > Changes from V7
> > 	Minor code clean ups
> > 
> > Changes from V6
> > 	Adjust for aux devices being a CXL only concept
> > 	Update commit msg.
> > 	Ensure devices iterated by auxiliary_find_device() are checked
> > 		to be DOE devices prior to checking for the CDAT
> > 		protocol
> > 	From Ben
> > 		Ensure reference from auxiliary_find_device() is dropped
> > ---
> >  drivers/cxl/core/pci.c  | 28 ++++++++++++++++++++++++++++
> >  drivers/cxl/core/port.c |  2 ++
> >  drivers/cxl/cxl.h       |  2 ++
> >  drivers/cxl/cxlpci.h    |  1 +
> >  4 files changed, 33 insertions(+)
> > 
> > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> > index c4c99ff7b55e..5497a65bdcf3 100644
> > --- a/drivers/cxl/core/pci.c
> > +++ b/drivers/cxl/core/pci.c
> > @@ -4,11 +4,14 @@
> >  #include <linux/device.h>
> >  #include <linux/delay.h>
> >  #include <linux/pci.h>
> > +#include <linux/pci-doe.h>
> >  #include <cxlpci.h>
> >  #include <cxlmem.h>
> >  #include <cxl.h>
> >  #include "core.h"
> >  
> > +#define CXL_DOE_PROTOCOL_TABLE_ACCESS 2
> > +
> >  /**
> >   * DOC: cxl core pci
> >   *
> > @@ -458,3 +461,28 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm)
> >  	return 0;
> >  }
> >  EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);
> > +
> > +void cxl_find_cdat_mb(struct cxl_port *port)
> 
> kdoc would be good for exported symbols IMO.

Yes.  This was not exported before and I forgot.

> Also if you can come up with a
> better verb than "find" for something that mutates the port's state, I think
> that would be beneficial.

cxl_cache_cdat_mb()?

Ira

> 
> I'm not sure why this is exported yet, but I suppose I'll see soon :-)
> 
> > +{
> > +	struct device *dev = port->uport;
> > +	struct cxl_memdev *cxlmd;
> > +	struct cxl_dev_state *cxlds;
> > +	int i;
> > +
> > +	if (!is_cxl_memdev(dev))
> > +		return;
> > +
> > +	cxlmd = to_cxl_memdev(dev);
> > +	cxlds = cxlmd->cxlds;
> > +
> > +	for (i = 0; i < cxlds->num_mbs; i++) {
> > +		struct pci_doe_mb *cur = cxlds->doe_mbs[i];
> > +
> > +		if (pci_doe_supports_prot(cur, PCI_DVSEC_VENDOR_ID_CXL,
> > +					  CXL_DOE_PROTOCOL_TABLE_ACCESS)) {
> > +			port->cdat_mb = cur;
> > +			return;
> > +		}
> > +	}
> > +}
> > +EXPORT_SYMBOL_NS_GPL(cxl_find_cdat_mb, CXL);
> > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> > index ea60abda6500..2e2bd65c1024 100644
> > --- a/drivers/cxl/core/port.c
> > +++ b/drivers/cxl/core/port.c
> > @@ -461,6 +461,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
> >  	if (IS_ERR(port))
> >  		return port;
> >  
> > +	cxl_find_cdat_mb(port);
> > +
> >  	dev = &port->dev;
> >  	if (is_cxl_memdev(uport))
> >  		rc = dev_set_name(dev, "endpoint%d", port->id);
> > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> > index 140dc3278cde..0a86be589ffc 100644
> > --- a/drivers/cxl/cxl.h
> > +++ b/drivers/cxl/cxl.h
> > @@ -267,6 +267,7 @@ struct cxl_nvdimm {
> >   * @component_reg_phys: component register capability base address (optional)
> >   * @dead: last ep has been removed, force port re-creation
> >   * @depth: How deep this port is relative to the root. depth 0 is the root.
> > + * @cdat_mb: Mailbox which supports the CDAT protocol
> >   */
> >  struct cxl_port {
> >  	struct device dev;
> > @@ -278,6 +279,7 @@ struct cxl_port {
> >  	resource_size_t component_reg_phys;
> >  	bool dead;
> >  	unsigned int depth;
> > +	struct pci_doe_mb *cdat_mb;
> >  };
> >  
> >  /**
> > diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> > index fce1c11729c2..366b21bd1a01 100644
> > --- a/drivers/cxl/cxlpci.h
> > +++ b/drivers/cxl/cxlpci.h
> > @@ -74,4 +74,5 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
> >  int devm_cxl_port_enumerate_dports(struct cxl_port *port);
> >  struct cxl_dev_state;
> >  int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
> > +void cxl_find_cdat_mb(struct cxl_port *port);
> >  #endif /* __CXL_PCI_H__ */
> > -- 
> > 2.35.1
> > 

[PATCH V9 6/9] cxl/port: Read CDAT table

[ira.weiny]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

The OS will need CDAT data from CXL devices to properly set up
interleave sets.  Currently this is supported through a DOE mailbox
which supports CDAT.

Cache the CDAT data for later parsing.  Provide a sysfs binary attribute
to allow dumping of the CDAT.

Binary dumping is modeled on /sys/firmware/ACPI/tables/

The ability to dump this table will be very useful for emulation of real
devices once they become available as QEMU CXL type 3 device emulation will
be able to load this file in.

This does not support table updates at runtime. It will always provide
whatever was there when first cached. Handling of table updates can be
implemented later.

Finally create a complete list of DOE defines within cdat.h for code
wishing to decode the CDAT table.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Co-developed-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>

---
Changes from V8:
	Fix length print format
	Incorporate feedback from Jonathan
	Move all this to cxl_port which can help support switches when
	the time comes.

Changes from V6:
	Fix issue with devm use
		Move cached cdat data to cxl_dev_state
	Use new pci_doe_submit_task()
	Ensure the aux driver is locked while processing tasks
	Rebased on cxl-pending

Changes from V5:
	Add proper guards around cdat.h
	Split out finding the CDAT DOE mailbox
	Use cxl_cdat to group CDAT data together
	Adjust to use auxiliary_find_device() to find the DOE device
		which supplies the CDAT protocol.
	Rebased to latest
	Remove dev_dbg(length)
	Remove unneeded DOE Table access defines
	Move CXL_DOE_PROTOCOL_TABLE_ACCESS define into this patch where
		it is used

Changes from V4:
	Split this into it's own patch
	Rearchitect this such that the memdev driver calls into the DOE
	driver via the cxl_mem state object.  This allows CDAT data to
	come from any type of cxl_mem object not just PCI DOE.
	Rebase on new struct cxl_dev_state
---
 drivers/cxl/cdat.h      |  99 ++++++++++++++++++++++++++++++
 drivers/cxl/core/pci.c  | 132 +++++++++++++++++++++++++++++++++++++++-
 drivers/cxl/core/port.c |  43 +++++++++++++
 drivers/cxl/cxl.h       |   3 +
 drivers/cxl/cxlpci.h    |   1 +
 5 files changed, 276 insertions(+), 2 deletions(-)
 create mode 100644 drivers/cxl/cdat.h

diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h
new file mode 100644
index 000000000000..f5193a6a51fe
--- /dev/null
+++ b/drivers/cxl/cdat.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CXL_CDAT_H__
+#define __CXL_CDAT_H__
+
+/*
+ * Coherent Device Attribute table (CDAT)
+ *
+ * Specification available from UEFI.org
+ *
+ * Whilst CDAT is defined as a single table, the access via DOE maiboxes is
+ * done one entry at a time, where the first entry is the header.
+ */
+
+#define CXL_DOE_TABLE_ACCESS_REQ_CODE		0x000000ff
+#define   CXL_DOE_TABLE_ACCESS_REQ_CODE_READ	0
+#define CXL_DOE_TABLE_ACCESS_TABLE_TYPE		0x0000ff00
+#define   CXL_DOE_TABLE_ACCESS_TABLE_TYPE_CDATA	0
+#define CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE	0xffff0000
+
+/*
+ * CDAT entries are little endian and are read from PCI config space which
+ * is also little endian.
+ * As such, on a big endian system these will have been reversed.
+ * This prevents us from making easy use of packed structures.
+ * Style form pci_regs.h
+ */
+
+#define CDAT_HEADER_LENGTH_DW 4
+#define CDAT_HEADER_LENGTH_BYTES (CDAT_HEADER_LENGTH_DW * sizeof(u32))
+#define CDAT_HEADER_DW0_LENGTH		0xffffffff
+#define CDAT_HEADER_DW1_REVISION	0x000000ff
+#define CDAT_HEADER_DW1_CHECKSUM	0x0000ff00
+/* CDAT_HEADER_DW2_RESERVED	*/
+#define CDAT_HEADER_DW3_SEQUENCE	0xffffffff
+
+/* All structures have a common first DW */
+#define CDAT_STRUCTURE_DW0_TYPE		0x000000ff
+#define   CDAT_STRUCTURE_DW0_TYPE_DSMAS 0
+#define   CDAT_STRUCTURE_DW0_TYPE_DSLBIS 1
+#define   CDAT_STRUCTURE_DW0_TYPE_DSMSCIS 2
+#define   CDAT_STRUCTURE_DW0_TYPE_DSIS 3
+#define   CDAT_STRUCTURE_DW0_TYPE_DSEMTS 4
+#define   CDAT_STRUCTURE_DW0_TYPE_SSLBIS 5
+
+#define CDAT_STRUCTURE_DW0_LENGTH	0xffff0000
+
+/* Device Scoped Memory Affinity Structure */
+#define CDAT_DSMAS_DW1_DSMAD_HANDLE	0x000000ff
+#define CDAT_DSMAS_DW1_FLAGS		0x0000ff00
+#define CDAT_DSMAS_DPA_OFFSET(entry) ((u64)((entry)[3]) << 32 | (entry)[2])
+#define CDAT_DSMAS_DPA_LEN(entry) ((u64)((entry)[5]) << 32 | (entry)[4])
+#define CDAT_DSMAS_NON_VOLATILE(flags)  ((flags & 0x04) >> 2)
+
+/* Device Scoped Latency and Bandwidth Information Structure */
+#define CDAT_DSLBIS_DW1_HANDLE		0x000000ff
+#define CDAT_DSLBIS_DW1_FLAGS		0x0000ff00
+#define CDAT_DSLBIS_DW1_DATA_TYPE	0x00ff0000
+#define CDAT_DSLBIS_BASE_UNIT(entry) ((u64)((entry)[3]) << 32 | (entry)[2])
+#define CDAT_DSLBIS_DW4_ENTRY_0		0x0000ffff
+#define CDAT_DSLBIS_DW4_ENTRY_1		0xffff0000
+#define CDAT_DSLBIS_DW5_ENTRY_2		0x0000ffff
+
+/* Device Scoped Memory Side Cache Information Structure */
+#define CDAT_DSMSCIS_DW1_HANDLE		0x000000ff
+#define CDAT_DSMSCIS_MEMORY_SIDE_CACHE_SIZE(entry) \
+	((u64)((entry)[3]) << 32 | (entry)[2])
+#define CDAT_DSMSCIS_DW4_MEMORY_SIDE_CACHE_ATTRS 0xffffffff
+
+/* Device Scoped Initiator Structure */
+#define CDAT_DSIS_DW1_FLAGS		0x000000ff
+#define CDAT_DSIS_DW1_HANDLE		0x0000ff00
+
+/* Device Scoped EFI Memory Type Structure */
+#define CDAT_DSEMTS_DW1_HANDLE		0x000000ff
+#define CDAT_DSEMTS_DW1_EFI_MEMORY_TYPE_ATTR	0x0000ff00
+#define CDAT_DSEMTS_DPA_OFFSET(entry)	((u64)((entry)[3]) << 32 | (entry)[2])
+#define CDAT_DSEMTS_DPA_LENGTH(entry)	((u64)((entry)[5]) << 32 | (entry)[4])
+
+/* Switch Scoped Latency and Bandwidth Information Structure */
+#define CDAT_SSLBIS_DW1_DATA_TYPE	0x000000ff
+#define CDAT_SSLBIS_BASE_UNIT(entry)	((u64)((entry)[3]) << 32 | (entry)[2])
+#define CDAT_SSLBIS_ENTRY_PORT_X(entry, i) ((entry)[4 + (i) * 2] & 0x0000ffff)
+#define CDAT_SSLBIS_ENTRY_PORT_Y(entry, i) (((entry)[4 + (i) * 2] & 0xffff0000) >> 16)
+#define CDAT_SSLBIS_ENTRY_LAT_OR_BW(entry, i) ((entry)[4 + (i) * 2 + 1] & 0x0000ffff)
+
+#define CXL_DOE_PROTOCOL_TABLE_ACCESS 2
+
+/**
+ * struct cxl_cdat - CXL CDAT data
+ *
+ * @table: cache of CDAT table
+ * @length: length of cached CDAT table
+ */
+struct cxl_cdat {
+	void *table;
+	size_t length;
+};
+
+#endif /* !__CXL_CDAT_H__ */
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 5497a65bdcf3..4c25a7d7abfd 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -9,8 +9,7 @@
 #include <cxlmem.h>
 #include <cxl.h>
 #include "core.h"
-
-#define CXL_DOE_PROTOCOL_TABLE_ACCESS 2
+#include "cdat.h"
 
 /**
  * DOC: cxl core pci
@@ -486,3 +485,132 @@ void cxl_find_cdat_mb(struct cxl_port *port)
 	}
 }
 EXPORT_SYMBOL_NS_GPL(cxl_find_cdat_mb, CXL);
+
+#define CDAT_DOE_REQ(entry_handle)					\
+	(FIELD_PREP(CXL_DOE_TABLE_ACCESS_REQ_CODE,			\
+		    CXL_DOE_TABLE_ACCESS_REQ_CODE_READ) |		\
+	 FIELD_PREP(CXL_DOE_TABLE_ACCESS_TABLE_TYPE,			\
+		    CXL_DOE_TABLE_ACCESS_TABLE_TYPE_CDATA) |		\
+	 FIELD_PREP(CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE, (entry_handle)))
+
+static void cxl_doe_task_complete(struct pci_doe_task *task)
+{
+	complete(task->private);
+}
+
+static int cxl_cdat_get_length(struct cxl_port *port, size_t *length)
+{
+	u32 cdat_request_pl = CDAT_DOE_REQ(0);
+	u32 cdat_response_pl[32];
+	DECLARE_COMPLETION_ONSTACK(c);
+	struct pci_doe_task task = {
+		.prot.vid = PCI_DVSEC_VENDOR_ID_CXL,
+		.prot.type = CXL_DOE_PROTOCOL_TABLE_ACCESS,
+		.request_pl = &cdat_request_pl,
+		.request_pl_sz = sizeof(cdat_request_pl),
+		.response_pl = cdat_response_pl,
+		.response_pl_sz = sizeof(cdat_response_pl),
+		.complete = cxl_doe_task_complete,
+		.private = &c,
+	};
+	int rc = 0;
+
+	if (!port->cdat_mb)
+		return -EIO;
+
+	rc = pci_doe_submit_task(port->cdat_mb, &task);
+	if (rc < 0) {
+		dev_err(&port->dev, "DOE submit failed: %d", rc);
+		return rc;
+	}
+	wait_for_completion(&c);
+
+	if (task.rv < 1)
+		return -EIO;
+
+	*length = cdat_response_pl[1];
+	dev_dbg(&port->dev, "CDAT length %zu\n", *length);
+
+	return rc;
+}
+
+static int cxl_cdat_read_table(struct cxl_port *port,
+			       struct cxl_cdat *cdat)
+{
+	size_t length = cdat->length;
+	u32 *data = cdat->table;
+	int entry_handle = 0;
+	int rc = 0;
+
+	if (!port->cdat_mb)
+		return -EIO;
+
+	do {
+		u32 cdat_request_pl = CDAT_DOE_REQ(entry_handle);
+		u32 cdat_response_pl[32];
+		DECLARE_COMPLETION_ONSTACK(c);
+		struct pci_doe_task task = {
+			.prot.vid = PCI_DVSEC_VENDOR_ID_CXL,
+			.prot.type = CXL_DOE_PROTOCOL_TABLE_ACCESS,
+			.request_pl = &cdat_request_pl,
+			.request_pl_sz = sizeof(cdat_request_pl),
+			.response_pl = cdat_response_pl,
+			.response_pl_sz = sizeof(cdat_response_pl),
+			.complete = cxl_doe_task_complete,
+			.private = &c,
+		};
+		size_t entry_dw;
+		u32 *entry;
+
+		rc = pci_doe_submit_task(port->cdat_mb, &task);
+		if (rc < 0) {
+			dev_err(&port->dev, "DOE submit failed: %d", rc);
+			return rc;
+		}
+		wait_for_completion(&c);
+
+		entry = cdat_response_pl + 1;
+		entry_dw = task.rv / sizeof(u32);
+		/* Skip Header */
+		entry_dw -= 1;
+		entry_dw = min(length / 4, entry_dw);
+		memcpy(data, entry, entry_dw * sizeof(u32));
+		length -= entry_dw * sizeof(u32);
+		data += entry_dw;
+		entry_handle = FIELD_GET(CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE, cdat_response_pl[0]);
+
+	} while (entry_handle != 0xFFFF);
+
+	return rc;
+}
+
+void read_cdat_data(struct cxl_port *port)
+{
+	struct device *dev = &port->dev;
+	size_t cdat_length;
+	int ret;
+
+	if (cxl_cdat_get_length(port, &cdat_length))
+		return;
+
+	port->cdat.table = devm_kzalloc(dev, cdat_length, GFP_KERNEL);
+	if (!port->cdat.table) {
+		ret = -ENOMEM;
+		goto error;
+	}
+
+	port->cdat.length = cdat_length;
+	ret = cxl_cdat_read_table(port, &port->cdat);
+	if (ret) {
+		devm_kfree(dev, port->cdat.table);
+		port->cdat.table = NULL;
+		port->cdat.length = 0;
+		ret = -EIO;
+		goto error;
+	}
+
+	return;
+error:
+	dev_err(dev, "CDAT data read error (%d)\n", ret);
+}
+EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 2e2bd65c1024..aa4229ddc1bc 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -320,7 +320,48 @@ static void cxl_port_release(struct device *dev)
 	kfree(port);
 }
 
+static ssize_t cdat_read(struct file *filp, struct kobject *kobj,
+			 struct bin_attribute *bin_attr, char *buf,
+			 loff_t offset, size_t count)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct cxl_port *port = to_cxl_port(dev);
+
+	if (!port->cdat.table)
+		return 0;
+
+	return memory_read_from_buffer(buf, count, &offset,
+				       port->cdat.table,
+				       port->cdat.length);
+}
+
+static BIN_ATTR_RO(cdat, 0);
+
+static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj,
+					      struct bin_attribute *attr, int i)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct cxl_port *port = to_cxl_port(dev);
+
+	if ((attr == &bin_attr_cdat) && port->cdat.table)
+		return 0400;
+
+	return 0;
+}
+
+static struct bin_attribute *cxl_cdat_bin_attributes[] = {
+	&bin_attr_cdat,
+	NULL,
+};
+
+static struct attribute_group cxl_cdat_attribute_group = {
+	.name = "CDAT",
+	.bin_attrs = cxl_cdat_bin_attributes,
+	.is_bin_visible = cxl_port_bin_attr_is_visible,
+};
+
 static const struct attribute_group *cxl_port_attribute_groups[] = {
+	&cxl_cdat_attribute_group,
 	&cxl_base_attribute_group,
 	NULL,
 };
@@ -462,6 +503,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
 		return port;
 
 	cxl_find_cdat_mb(port);
+	/* Cache the data early to ensure is_visible() works */
+	read_cdat_data(port);
 
 	dev = &port->dev;
 	if (is_cxl_memdev(uport))
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 0a86be589ffc..531b77d296c7 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -8,6 +8,7 @@
 #include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
+#include "cdat.h"
 
 /**
  * DOC: cxl objects
@@ -268,6 +269,7 @@ struct cxl_nvdimm {
  * @dead: last ep has been removed, force port re-creation
  * @depth: How deep this port is relative to the root. depth 0 is the root.
  * @cdat_mb: Mailbox which supports the CDAT protocol
+ * @cdat: Cached CDAT data
  */
 struct cxl_port {
 	struct device dev;
@@ -280,6 +282,7 @@ struct cxl_port {
 	bool dead;
 	unsigned int depth;
 	struct pci_doe_mb *cdat_mb;
+	struct cxl_cdat cdat;
 };
 
 /**
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index 366b21bd1a01..35f0d4892eaa 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -75,4 +75,5 @@ int devm_cxl_port_enumerate_dports(struct cxl_port *port);
 struct cxl_dev_state;
 int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
 void cxl_find_cdat_mb(struct cxl_port *port);
+void read_cdat_data(struct cxl_port *port);
 #endif /* __CXL_PCI_H__ */
-- 
2.35.1

Re: [PATCH V9 6/9] cxl/port: Read CDAT table

[Jonathan Cameron]

On Tue, 31 May 2022 08:26:29 -0700
ira.weiny@intel.com wrote:

> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> The OS will need CDAT data from CXL devices to properly set up
> interleave sets.  Currently this is supported through a DOE mailbox
> which supports CDAT.
> 
> Cache the CDAT data for later parsing.  Provide a sysfs binary attribute
> to allow dumping of the CDAT.
> 
> Binary dumping is modeled on /sys/firmware/ACPI/tables/
> 
> The ability to dump this table will be very useful for emulation of real
> devices once they become available as QEMU CXL type 3 device emulation will
> be able to load this file in.
> 
> This does not support table updates at runtime. It will always provide
> whatever was there when first cached. Handling of table updates can be
> implemented later.
> 
> Finally create a complete list of DOE defines within cdat.h for code
> wishing to decode the CDAT table.
> 
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Co-developed-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> 

Fun question of ownership inline...

...

> +void read_cdat_data(struct cxl_port *port)
> +{
> +	struct device *dev = &port->dev;
> +	size_t cdat_length;
> +	int ret;
> +
> +	if (cxl_cdat_get_length(port, &cdat_length))
> +		return;
> +
> +	port->cdat.table = devm_kzalloc(dev, cdat_length, GFP_KERNEL);

boom. See below for why :)

> +	if (!port->cdat.table) {
> +		ret = -ENOMEM;
> +		goto error;
> +	}
> +
> +	port->cdat.length = cdat_length;
> +	ret = cxl_cdat_read_table(port, &port->cdat);
> +	if (ret) {
> +		devm_kfree(dev, port->cdat.table);
> +		port->cdat.table = NULL;
> +		port->cdat.length = 0;
> +		ret = -EIO;
> +		goto error;
> +	}
> +
> +	return;
> +error:
> +	dev_err(dev, "CDAT data read error (%d)\n", ret);
> +}
> +EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 2e2bd65c1024..aa4229ddc1bc 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -320,7 +320,48 @@ static void cxl_port_release(struct device *dev)
>  	kfree(port);
>  }
>  
> +static ssize_t cdat_read(struct file *filp, struct kobject *kobj,
> +			 struct bin_attribute *bin_attr, char *buf,
> +			 loff_t offset, size_t count)
> +{
> +	struct device *dev = kobj_to_dev(kobj);
> +	struct cxl_port *port = to_cxl_port(dev);
> +
> +	if (!port->cdat.table)
> +		return 0;
> +
> +	return memory_read_from_buffer(buf, count, &offset,
> +				       port->cdat.table,
> +				       port->cdat.length);
> +}
> +
> +static BIN_ATTR_RO(cdat, 0);
> +
> +static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj,
> +					      struct bin_attribute *attr, int i)
> +{
> +	struct device *dev = kobj_to_dev(kobj);
> +	struct cxl_port *port = to_cxl_port(dev);
> +
> +	if ((attr == &bin_attr_cdat) && port->cdat.table)
> +		return 0400;
> +
> +	return 0;
> +}
> +
> +static struct bin_attribute *cxl_cdat_bin_attributes[] = {
> +	&bin_attr_cdat,
> +	NULL,
> +};
> +
> +static struct attribute_group cxl_cdat_attribute_group = {
> +	.name = "CDAT",
> +	.bin_attrs = cxl_cdat_bin_attributes,
> +	.is_bin_visible = cxl_port_bin_attr_is_visible,
> +};
> +
>  static const struct attribute_group *cxl_port_attribute_groups[] = {
> +	&cxl_cdat_attribute_group,o
>  	&cxl_base_attribute_group,
>  	NULL,
>  };
> @@ -462,6 +503,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
>  		return port;
>  
>  	cxl_find_cdat_mb(port);
> +	/* Cache the data early to ensure is_visible() works */
> +	read_cdat_data(port);

This uses port as the 'device' for devm_ calls.
Unfortunately if the port driver isn't loaded, it still "successfully" runs.
Then if the port driver is probed, you get both a bunch of errors due to
devm_ allocations on a device before the driver is loaded.

For extra fun it tries to probe the ports multiple times without freeing
the index which is 'interesting'. We had this happen a while ago (unrelated
to DOE) but this may be unrelated (or maybe related to the region stuff
I'm carrying on my test tree)

As to the question of what the correct fix is...
Maybe move them into the port driver probe but then is_visible
won't work.  Or pass a pointer to the struct device *host down
into read_cdat_data and __read_cdat_data calls to handle the
allocation. (I tried this and it seems superficially fine).

Jonathan



>  
>  	dev = &port->dev;
>  	if (is_cxl_memdev(uport))
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 0a86be589ffc..531b77d296c7 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -8,6 +8,7 @@
>  #include <linux/bitfield.h>
>  #include <linux/bitops.h>
>  #include <linux/io.h>
> +#include "cdat.h"
>  
>  /**
>   * DOC: cxl objects
> @@ -268,6 +269,7 @@ struct cxl_nvdimm {
>   * @dead: last ep has been removed, force port re-creation
>   * @depth: How deep this port is relative to the root. depth 0 is the root.
>   * @cdat_mb: Mailbox which supports the CDAT protocol
> + * @cdat: Cached CDAT data
>   */
>  struct cxl_port {
>  	struct device dev;
> @@ -280,6 +282,7 @@ struct cxl_port {
>  	bool dead;
>  	unsigned int depth;
>  	struct pci_doe_mb *cdat_mb;
> +	struct cxl_cdat cdat;
>  };
>  
>  /**
> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> index 366b21bd1a01..35f0d4892eaa 100644
> --- a/drivers/cxl/cxlpci.h
> +++ b/drivers/cxl/cxlpci.h
> @@ -75,4 +75,5 @@ int devm_cxl_port_enumerate_dports(struct cxl_port *port);
>  struct cxl_dev_state;
>  int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
>  void cxl_find_cdat_mb(struct cxl_port *port);
> +void read_cdat_data(struct cxl_port *port);
>  #endif /* __CXL_PCI_H__ */

Re: [PATCH V9 6/9] cxl/port: Read CDAT table

[Jonathan Cameron]

On Wed, 1 Jun 2022 16:35:40 +0100
Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:

> On Tue, 31 May 2022 08:26:29 -0700
> ira.weiny@intel.com wrote:
> 
> > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > 
> > The OS will need CDAT data from CXL devices to properly set up
> > interleave sets.  Currently this is supported through a DOE mailbox
> > which supports CDAT.
> > 
> > Cache the CDAT data for later parsing.  Provide a sysfs binary attribute
> > to allow dumping of the CDAT.
> > 
> > Binary dumping is modeled on /sys/firmware/ACPI/tables/
> > 
> > The ability to dump this table will be very useful for emulation of real
> > devices once they become available as QEMU CXL type 3 device emulation will
> > be able to load this file in.
> > 
> > This does not support table updates at runtime. It will always provide
> > whatever was there when first cached. Handling of table updates can be
> > implemented later.
> > 
> > Finally create a complete list of DOE defines within cdat.h for code
> > wishing to decode the CDAT table.
> > 
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > Co-developed-by: Ira Weiny <ira.weiny@intel.com>
> > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> >   
> 
> Fun question of ownership inline...

And a follow up due to triggering a bug that predated this series...

I'd send a fix, but I'm off on a long weekend shortly :)

> 
> ...
> 
> > +void read_cdat_data(struct cxl_port *port)
> > +{
> > +	struct device *dev = &port->dev;
> > +	size_t cdat_length;
> > +	int ret;
> > +
> > +	if (cxl_cdat_get_length(port, &cdat_length))
> > +		return;
> > +
> > +	port->cdat.table = devm_kzalloc(dev, cdat_length, GFP_KERNEL);  
> 
> boom. See below for why :)
> 
> > +	if (!port->cdat.table) {
> > +		ret = -ENOMEM;
> > +		goto error;
> > +	}
> > +
> > +	port->cdat.length = cdat_length;
> > +	ret = cxl_cdat_read_table(port, &port->cdat);
> > +	if (ret) {
> > +		devm_kfree(dev, port->cdat.table);
> > +		port->cdat.table = NULL;
> > +		port->cdat.length = 0;
> > +		ret = -EIO;
> > +		goto error;
> > +	}
> > +
> > +	return;
> > +error:
> > +	dev_err(dev, "CDAT data read error (%d)\n", ret);
> > +}
> > +EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
> > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> > index 2e2bd65c1024..aa4229ddc1bc 100644
> > --- a/drivers/cxl/core/port.c
> > +++ b/drivers/cxl/core/port.c
> > @@ -320,7 +320,48 @@ static void cxl_port_release(struct device *dev)
> >  	kfree(port);
> >  }
> >  
> > +static ssize_t cdat_read(struct file *filp, struct kobject *kobj,
> > +			 struct bin_attribute *bin_attr, char *buf,
> > +			 loff_t offset, size_t count)
> > +{
> > +	struct device *dev = kobj_to_dev(kobj);
> > +	struct cxl_port *port = to_cxl_port(dev);
> > +
> > +	if (!port->cdat.table)
> > +		return 0;
> > +
> > +	return memory_read_from_buffer(buf, count, &offset,
> > +				       port->cdat.table,
> > +				       port->cdat.length);
> > +}
> > +
> > +static BIN_ATTR_RO(cdat, 0);
> > +
> > +static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj,
> > +					      struct bin_attribute *attr, int i)
> > +{
> > +	struct device *dev = kobj_to_dev(kobj);
> > +	struct cxl_port *port = to_cxl_port(dev);
> > +
> > +	if ((attr == &bin_attr_cdat) && port->cdat.table)
> > +		return 0400;
> > +
> > +	return 0;
> > +}
> > +
> > +static struct bin_attribute *cxl_cdat_bin_attributes[] = {
> > +	&bin_attr_cdat,
> > +	NULL,
> > +};
> > +
> > +static struct attribute_group cxl_cdat_attribute_group = {
> > +	.name = "CDAT",
> > +	.bin_attrs = cxl_cdat_bin_attributes,
> > +	.is_bin_visible = cxl_port_bin_attr_is_visible,
> > +};
> > +
> >  static const struct attribute_group *cxl_port_attribute_groups[] = {
> > +	&cxl_cdat_attribute_group,o
> >  	&cxl_base_attribute_group,
> >  	NULL,
> >  };
> > @@ -462,6 +503,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
> >  		return port;
> >  
> >  	cxl_find_cdat_mb(port);
> > +	/* Cache the data early to ensure is_visible() works */
> > +	read_cdat_data(port);  
> 
> This uses port as the 'device' for devm_ calls.
> Unfortunately if the port driver isn't loaded, it still "successfully" runs.
> Then if the port driver is probed, you get both a bunch of errors due to
> devm_ allocations on a device before the driver is loaded.
> 
> For extra fun it tries to probe the ports multiple times without freeing
> the index which is 'interesting'. We had this happen a while ago (unrelated
> to DOE) but this may be unrelated (or maybe related to the region stuff
> I'm carrying on my test tree)

So the extra devices are a result of the obvious initial path of
cxl_mem_probe() from module probe and down failing, then bus_rescan_devices
coming along from the pmem driver having another go... 

So next question is why don't the first set of endpointX devices get cleaned up
if the create_endpoint() in cxl/mem.c fails.

I think this is because the cxl_endpoint_autoremove() call hasn't yet happened
when we detect the failure to bind a driver and error out of cxl_mem_probe().

So, fix is probably to do the cxl_endpoint_autoremove() unconditionally
by moving it before the check on driver binding.

https://elixir.bootlin.com/linux/latest/source/drivers/cxl/mem.c#L67

Move it up a few lines.



> 
> As to the question of what the correct fix is...
> Maybe move them into the port driver probe but then is_visible
> won't work.  Or pass a pointer to the struct device *host down
> into read_cdat_data and __read_cdat_data calls to handle the
> allocation. (I tried this and it seems superficially fine).
> 
> Jonathan
> 
> 
> 
> >  
> >  	dev = &port->dev;
> >  	if (is_cxl_memdev(uport))
> > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> > index 0a86be589ffc..531b77d296c7 100644
> > --- a/drivers/cxl/cxl.h
> > +++ b/drivers/cxl/cxl.h
> > @@ -8,6 +8,7 @@
> >  #include <linux/bitfield.h>
> >  #include <linux/bitops.h>
> >  #include <linux/io.h>
> > +#include "cdat.h"
> >  
> >  /**
> >   * DOC: cxl objects
> > @@ -268,6 +269,7 @@ struct cxl_nvdimm {
> >   * @dead: last ep has been removed, force port re-creation
> >   * @depth: How deep this port is relative to the root. depth 0 is the root.
> >   * @cdat_mb: Mailbox which supports the CDAT protocol
> > + * @cdat: Cached CDAT data
> >   */
> >  struct cxl_port {
> >  	struct device dev;
> > @@ -280,6 +282,7 @@ struct cxl_port {
> >  	bool dead;
> >  	unsigned int depth;
> >  	struct pci_doe_mb *cdat_mb;
> > +	struct cxl_cdat cdat;
> >  };
> >  
> >  /**
> > diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> > index 366b21bd1a01..35f0d4892eaa 100644
> > --- a/drivers/cxl/cxlpci.h
> > +++ b/drivers/cxl/cxlpci.h
> > @@ -75,4 +75,5 @@ int devm_cxl_port_enumerate_dports(struct cxl_port *port);
> >  struct cxl_dev_state;
> >  int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
> >  void cxl_find_cdat_mb(struct cxl_port *port);
> > +void read_cdat_data(struct cxl_port *port);
> >  #endif /* __CXL_PCI_H__ */  
> 

Re: [PATCH V9 6/9] cxl/port: Read CDAT table

[Ira Weiny]

On Wed, Jun 01, 2022 at 05:31:13PM +0100, Jonathan Cameron wrote:
> On Wed, 1 Jun 2022 16:35:40 +0100
> Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:
> 
> > On Tue, 31 May 2022 08:26:29 -0700
> > ira.weiny@intel.com wrote:
> > 
> > > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > 
> > > The OS will need CDAT data from CXL devices to properly set up
> > > interleave sets.  Currently this is supported through a DOE mailbox
> > > which supports CDAT.
> > > 
> > > Cache the CDAT data for later parsing.  Provide a sysfs binary attribute
> > > to allow dumping of the CDAT.
> > > 
> > > Binary dumping is modeled on /sys/firmware/ACPI/tables/
> > > 
> > > The ability to dump this table will be very useful for emulation of real
> > > devices once they become available as QEMU CXL type 3 device emulation will
> > > be able to load this file in.
> > > 
> > > This does not support table updates at runtime. It will always provide
> > > whatever was there when first cached. Handling of table updates can be
> > > implemented later.
> > > 
> > > Finally create a complete list of DOE defines within cdat.h for code
> > > wishing to decode the CDAT table.
> > > 
> > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > Co-developed-by: Ira Weiny <ira.weiny@intel.com>
> > > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> > >   
> > 
> > Fun question of ownership inline...
> 
> And a follow up due to triggering a bug that predated this series...
> 
> I'd send a fix, but I'm off on a long weekend shortly :)

NP I discussed with Dan and the use of dev_groups should allow me to move this
to port probe where it belongs.  I put it here for the sysfs stuff.

> 
> > 
> > ...
> > 
> > > +void read_cdat_data(struct cxl_port *port)
> > > +{
> > > +	struct device *dev = &port->dev;
> > > +	size_t cdat_length;
> > > +	int ret;
> > > +
> > > +	if (cxl_cdat_get_length(port, &cdat_length))
> > > +		return;
> > > +
> > > +	port->cdat.table = devm_kzalloc(dev, cdat_length, GFP_KERNEL);  
> > 
> > boom. See below for why :)
> > 
> > > +	if (!port->cdat.table) {
> > > +		ret = -ENOMEM;
> > > +		goto error;
> > > +	}
> > > +
> > > +	port->cdat.length = cdat_length;
> > > +	ret = cxl_cdat_read_table(port, &port->cdat);
> > > +	if (ret) {
> > > +		devm_kfree(dev, port->cdat.table);
> > > +		port->cdat.table = NULL;
> > > +		port->cdat.length = 0;
> > > +		ret = -EIO;
> > > +		goto error;
> > > +	}
> > > +
> > > +	return;
> > > +error:
> > > +	dev_err(dev, "CDAT data read error (%d)\n", ret);
> > > +}
> > > +EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
> > > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> > > index 2e2bd65c1024..aa4229ddc1bc 100644
> > > --- a/drivers/cxl/core/port.c
> > > +++ b/drivers/cxl/core/port.c
> > > @@ -320,7 +320,48 @@ static void cxl_port_release(struct device *dev)
> > >  	kfree(port);
> > >  }
> > >  
> > > +static ssize_t cdat_read(struct file *filp, struct kobject *kobj,
> > > +			 struct bin_attribute *bin_attr, char *buf,
> > > +			 loff_t offset, size_t count)
> > > +{
> > > +	struct device *dev = kobj_to_dev(kobj);
> > > +	struct cxl_port *port = to_cxl_port(dev);
> > > +
> > > +	if (!port->cdat.table)
> > > +		return 0;
> > > +
> > > +	return memory_read_from_buffer(buf, count, &offset,
> > > +				       port->cdat.table,
> > > +				       port->cdat.length);
> > > +}
> > > +
> > > +static BIN_ATTR_RO(cdat, 0);
> > > +
> > > +static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj,
> > > +					      struct bin_attribute *attr, int i)
> > > +{
> > > +	struct device *dev = kobj_to_dev(kobj);
> > > +	struct cxl_port *port = to_cxl_port(dev);
> > > +
> > > +	if ((attr == &bin_attr_cdat) && port->cdat.table)
> > > +		return 0400;
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static struct bin_attribute *cxl_cdat_bin_attributes[] = {
> > > +	&bin_attr_cdat,
> > > +	NULL,
> > > +};
> > > +
> > > +static struct attribute_group cxl_cdat_attribute_group = {
> > > +	.name = "CDAT",
> > > +	.bin_attrs = cxl_cdat_bin_attributes,
> > > +	.is_bin_visible = cxl_port_bin_attr_is_visible,
> > > +};
> > > +
> > >  static const struct attribute_group *cxl_port_attribute_groups[] = {
> > > +	&cxl_cdat_attribute_group,o
> > >  	&cxl_base_attribute_group,
> > >  	NULL,
> > >  };
> > > @@ -462,6 +503,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
> > >  		return port;
> > >  
> > >  	cxl_find_cdat_mb(port);
> > > +	/* Cache the data early to ensure is_visible() works */
> > > +	read_cdat_data(port);  
> > 
> > This uses port as the 'device' for devm_ calls.
> > Unfortunately if the port driver isn't loaded, it still "successfully" runs.
> > Then if the port driver is probed, you get both a bunch of errors due to
> > devm_ allocations on a device before the driver is loaded.
> > 
> > For extra fun it tries to probe the ports multiple times without freeing
> > the index which is 'interesting'. We had this happen a while ago (unrelated
> > to DOE) but this may be unrelated (or maybe related to the region stuff
> > I'm carrying on my test tree)
> 
> So the extra devices are a result of the obvious initial path of
> cxl_mem_probe() from module probe and down failing, then bus_rescan_devices
> coming along from the pmem driver having another go... 
> 
> So next question is why don't the first set of endpointX devices get cleaned up
> if the create_endpoint() in cxl/mem.c fails.
> 
> I think this is because the cxl_endpoint_autoremove() call hasn't yet happened
> when we detect the failure to bind a driver and error out of cxl_mem_probe().
> 
> So, fix is probably to do the cxl_endpoint_autoremove() unconditionally
> by moving it before the check on driver binding.
> 
> https://elixir.bootlin.com/linux/latest/source/drivers/cxl/mem.c#L67
> 
> Move it up a few lines.
> 

I think I can make it work by moving into the port probe.

Ira

> 
> 
> > 
> > As to the question of what the correct fix is...
> > Maybe move them into the port driver probe but then is_visible
> > won't work.  Or pass a pointer to the struct device *host down
> > into read_cdat_data and __read_cdat_data calls to handle the
> > allocation. (I tried this and it seems superficially fine).
> > 
> > Jonathan
> > 
> > 
> > 
> > >  
> > >  	dev = &port->dev;
> > >  	if (is_cxl_memdev(uport))
> > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> > > index 0a86be589ffc..531b77d296c7 100644
> > > --- a/drivers/cxl/cxl.h
> > > +++ b/drivers/cxl/cxl.h
> > > @@ -8,6 +8,7 @@
> > >  #include <linux/bitfield.h>
> > >  #include <linux/bitops.h>
> > >  #include <linux/io.h>
> > > +#include "cdat.h"
> > >  
> > >  /**
> > >   * DOC: cxl objects
> > > @@ -268,6 +269,7 @@ struct cxl_nvdimm {
> > >   * @dead: last ep has been removed, force port re-creation
> > >   * @depth: How deep this port is relative to the root. depth 0 is the root.
> > >   * @cdat_mb: Mailbox which supports the CDAT protocol
> > > + * @cdat: Cached CDAT data
> > >   */
> > >  struct cxl_port {
> > >  	struct device dev;
> > > @@ -280,6 +282,7 @@ struct cxl_port {
> > >  	bool dead;
> > >  	unsigned int depth;
> > >  	struct pci_doe_mb *cdat_mb;
> > > +	struct cxl_cdat cdat;
> > >  };
> > >  
> > >  /**
> > > diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> > > index 366b21bd1a01..35f0d4892eaa 100644
> > > --- a/drivers/cxl/cxlpci.h
> > > +++ b/drivers/cxl/cxlpci.h
> > > @@ -75,4 +75,5 @@ int devm_cxl_port_enumerate_dports(struct cxl_port *port);
> > >  struct cxl_dev_state;
> > >  int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
> > >  void cxl_find_cdat_mb(struct cxl_port *port);
> > > +void read_cdat_data(struct cxl_port *port);
> > >  #endif /* __CXL_PCI_H__ */  
> > 
> 

Re: [PATCH V9 6/9] cxl/port: Read CDAT table

[Ira Weiny]

On Thu, Jun 02, 2022 at 11:31:56AM -0700, Ira wrote:
> On Wed, Jun 01, 2022 at 05:31:13PM +0100, Jonathan Cameron wrote:
> > On Wed, 1 Jun 2022 16:35:40 +0100
> > Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:
> > 
> > > On Tue, 31 May 2022 08:26:29 -0700
> > > ira.weiny@intel.com wrote:
> > > 
> > > > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > > 
> > > > The OS will need CDAT data from CXL devices to properly set up
> > > > interleave sets.  Currently this is supported through a DOE mailbox
> > > > which supports CDAT.
> > > > 
> > > > Cache the CDAT data for later parsing.  Provide a sysfs binary attribute
> > > > to allow dumping of the CDAT.
> > > > 
> > > > Binary dumping is modeled on /sys/firmware/ACPI/tables/
> > > > 
> > > > The ability to dump this table will be very useful for emulation of real
> > > > devices once they become available as QEMU CXL type 3 device emulation will
> > > > be able to load this file in.
> > > > 
> > > > This does not support table updates at runtime. It will always provide
> > > > whatever was there when first cached. Handling of table updates can be
> > > > implemented later.
> > > > 
> > > > Finally create a complete list of DOE defines within cdat.h for code
> > > > wishing to decode the CDAT table.
> > > > 
> > > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > > Co-developed-by: Ira Weiny <ira.weiny@intel.com>
> > > > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> > > >   
> > > 
> > > Fun question of ownership inline...
> > 
> > And a follow up due to triggering a bug that predated this series...
> > 
> > I'd send a fix, but I'm off on a long weekend shortly :)
> 
> NP I discussed with Dan and the use of dev_groups should allow me to move this
> to port probe where it belongs.  I put it here for the sysfs stuff.

Not to make a habit of replying to my own mails but this works.

So I'm going to go forward with spinning this again.

Ira

Re: [PATCH V9 6/9] cxl/port: Read CDAT table

[Jonathan Cameron]

On Thu, 2 Jun 2022 15:47:37 -0700
Ira Weiny <ira.weiny@intel.com> wrote:

> On Thu, Jun 02, 2022 at 11:31:56AM -0700, Ira wrote:
> > On Wed, Jun 01, 2022 at 05:31:13PM +0100, Jonathan Cameron wrote:  
> > > On Wed, 1 Jun 2022 16:35:40 +0100
> > > Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:
> > >   
> > > > On Tue, 31 May 2022 08:26:29 -0700
> > > > ira.weiny@intel.com wrote:
> > > >   
> > > > > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > > > 
> > > > > The OS will need CDAT data from CXL devices to properly set up
> > > > > interleave sets.  Currently this is supported through a DOE mailbox
> > > > > which supports CDAT.
> > > > > 
> > > > > Cache the CDAT data for later parsing.  Provide a sysfs binary attribute
> > > > > to allow dumping of the CDAT.
> > > > > 
> > > > > Binary dumping is modeled on /sys/firmware/ACPI/tables/
> > > > > 
> > > > > The ability to dump this table will be very useful for emulation of real
> > > > > devices once they become available as QEMU CXL type 3 device emulation will
> > > > > be able to load this file in.
> > > > > 
> > > > > This does not support table updates at runtime. It will always provide
> > > > > whatever was there when first cached. Handling of table updates can be
> > > > > implemented later.
> > > > > 
> > > > > Finally create a complete list of DOE defines within cdat.h for code
> > > > > wishing to decode the CDAT table.
> > > > > 
> > > > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > > > Co-developed-by: Ira Weiny <ira.weiny@intel.com>
> > > > > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> > > > >     
> > > > 
> > > > Fun question of ownership inline...  
> > > 
> > > And a follow up due to triggering a bug that predated this series...
> > > 
> > > I'd send a fix, but I'm off on a long weekend shortly :)  
> > 
> > NP I discussed with Dan and the use of dev_groups should allow me to move this
> > to port probe where it belongs.  I put it here for the sysfs stuff.  
> 
> Not to make a habit of replying to my own mails but this works.
> 
> So I'm going to go forward with spinning this again.

It's the right solution - cleaner than moving the ownership.

Jonathan

> 
> Ira

[PATCH V9 7/9] cxl/port: Introduce cxl_cdat_valid()

[ira.weiny]

From: Ira Weiny <ira.weiny@intel.com>

The CDAT data is protected by a checksum and should be the proper
length.

Introduce cxl_cdat_valid() to validate the data.  While at it check and
store the sequence number.

Signed-off-by: Ira Weiny <ira.weiny@intel.com>

---
Changes from V8
	Move code to cxl/core/pci.c

Changes from V6
	Change name to cxl_cdat_valid() as this validates all the CDAT
		data not just the header
	Add error and debug prints

Changes from V5
	New patch, split out
	Update cdat_hdr_valid()
		Remove revision and cs field parsing
			There is no point in these
		Add seq check and debug print.
---
 drivers/cxl/cdat.h     |  2 ++
 drivers/cxl/core/pci.c | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h
index f5193a6a51fe..3d8945612511 100644
--- a/drivers/cxl/cdat.h
+++ b/drivers/cxl/cdat.h
@@ -90,10 +90,12 @@
  *
  * @table: cache of CDAT table
  * @length: length of cached CDAT table
+ * @seq: Last read Sequence number of the CDAT table
  */
 struct cxl_cdat {
 	void *table;
 	size_t length;
+	u32 seq;
 };
 
 #endif /* !__CXL_CDAT_H__ */
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 4c25a7d7abfd..bb370df1cb6c 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -534,6 +534,40 @@ static int cxl_cdat_get_length(struct cxl_port *port, size_t *length)
 	return rc;
 }
 
+static bool cxl_cdat_valid(struct device *dev, struct cxl_cdat *cdat)
+{
+	u32 *table = cdat->table;
+	u8 *data8 = cdat->table;
+	u32 length, seq;
+	u8 check;
+	int i;
+
+	length = FIELD_GET(CDAT_HEADER_DW0_LENGTH, table[0]);
+	if ((length < CDAT_HEADER_LENGTH_BYTES) || (length > cdat->length)) {
+		dev_err(dev, "Invalid length %u (%zu-%zu)\n", length,
+			CDAT_HEADER_LENGTH_BYTES, cdat->length);
+		return false;
+	}
+
+	for (check = 0, i = 0; i < length; i++)
+		check += data8[i];
+
+	dev_dbg(dev, "CDAT length %u CS %u\n", length, check);
+	if (check != 0) {
+		dev_err(dev, "Invalid checksum %u\n", check);
+		return false;
+	}
+
+	seq = FIELD_GET(CDAT_HEADER_DW3_SEQUENCE, table[3]);
+	/* Store the sequence for now. */
+	if (cdat->seq != seq) {
+		dev_info(dev, "CDAT seq change %x -> %x\n", cdat->seq, seq);
+		cdat->seq = seq;
+	}
+
+	return true;
+}
+
 static int cxl_cdat_read_table(struct cxl_port *port,
 			       struct cxl_cdat *cdat)
 {
@@ -581,6 +615,8 @@ static int cxl_cdat_read_table(struct cxl_port *port,
 
 	} while (entry_handle != 0xFFFF);
 
+	if (!rc && !cxl_cdat_valid(&port->dev, cdat))
+		return -EIO;
 	return rc;
 }
 
-- 
2.35.1

Re: [PATCH V9 7/9] cxl/port: Introduce cxl_cdat_valid()

[Alison Schofield]

On Tue, May 31, 2022 at 08:26:30AM -0700, Ira Weiny wrote:
> From: Ira Weiny <ira.weiny@intel.com>
> 
> The CDAT data is protected by a checksum and should be the proper
> length.
> 
> Introduce cxl_cdat_valid() to validate the data.  While at it check and
> store the sequence number.
> 
Store it for ?

>  
> +static bool cxl_cdat_valid(struct device *dev, struct cxl_cdat *cdat)
> +{

snip

> +
> +	seq = FIELD_GET(CDAT_HEADER_DW3_SEQUENCE, table[3]);
> +	/* Store the sequence for now. */
> +	if (cdat->seq != seq) {
> +		dev_info(dev, "CDAT seq change %x -> %x\n", cdat->seq, seq);
> +		cdat->seq = seq;
> +	}
> +

Wondering when does/will this sequence number come into play?

> 

Re: [PATCH V9 7/9] cxl/port: Introduce cxl_cdat_valid()

[Ira Weiny]

On Tue, May 31, 2022 at 10:21:46AM -0700, Alison Schofield wrote:
> On Tue, May 31, 2022 at 08:26:30AM -0700, Ira Weiny wrote:
> > From: Ira Weiny <ira.weiny@intel.com>
> > 
> > The CDAT data is protected by a checksum and should be the proper
> > length.
> > 
> > Introduce cxl_cdat_valid() to validate the data.  While at it check and
> > store the sequence number.
> > 
> Store it for ?

To see if a subsequent read shows new data.

> 
> >  
> > +static bool cxl_cdat_valid(struct device *dev, struct cxl_cdat *cdat)
> > +{
> 
> snip
> 
> > +
> > +	seq = FIELD_GET(CDAT_HEADER_DW3_SEQUENCE, table[3]);
> > +	/* Store the sequence for now. */
> > +	if (cdat->seq != seq) {
> > +		dev_info(dev, "CDAT seq change %x -> %x\n", cdat->seq, seq);
> > +		cdat->seq = seq;
> > +	}
> > +
> 
> Wondering when does/will this sequence number come into play?
>

Not until we start reacting to changes in CDAT.

Ira

[PATCH V9 8/9] cxl/port: Retry reading CDAT on failure

[ira.weiny]

From: Ira Weiny <ira.weiny@intel.com>

The CDAT read may fail for a number of reasons but mainly it is possible
to get different parts of a valid state.  The checksum in the CDAT table
protects against this.

Now that the cdat data is validated issue a retries if the CDAT read
fails.  For now 5 retries are implemented.

Signed-off-by: Ira Weiny <ira.weiny@intel.com>

---
Changes from V8
	Move code to cxl/core/pci.c

Changes from V6
	Move to pci.c
	Fix retries count
	Change to 5 retries

Changes from V5:
	New patch -- easy to push off or drop.
---
 drivers/cxl/core/pci.c | 32 +++++++++++++++++++++-----------
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index bb370df1cb6c..7f7dac9030a6 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -620,20 +620,18 @@ static int cxl_cdat_read_table(struct cxl_port *port,
 	return rc;
 }
 
-void read_cdat_data(struct cxl_port *port)
+static int __read_cdat_data(struct cxl_port *port)
 {
 	struct device *dev = &port->dev;
 	size_t cdat_length;
 	int ret;
 
 	if (cxl_cdat_get_length(port, &cdat_length))
-		return;
+		return 0;
 
 	port->cdat.table = devm_kzalloc(dev, cdat_length, GFP_KERNEL);
-	if (!port->cdat.table) {
-		ret = -ENOMEM;
-		goto error;
-	}
+	if (!port->cdat.table)
+		return -ENOMEM;
 
 	port->cdat.length = cdat_length;
 	ret = cxl_cdat_read_table(port, &port->cdat);
@@ -641,12 +639,24 @@ void read_cdat_data(struct cxl_port *port)
 		devm_kfree(dev, port->cdat.table);
 		port->cdat.table = NULL;
 		port->cdat.length = 0;
-		ret = -EIO;
-		goto error;
+		return -EIO;
 	}
 
-	return;
-error:
-	dev_err(dev, "CDAT data read error (%d)\n", ret);
+	return 0;
+}
+
+void read_cdat_data(struct cxl_port *port)
+{
+	int retries = 5;
+	int rc;
+
+	while (retries--) {
+		rc = __read_cdat_data(port);
+		if (!rc)
+			break;
+		dev_err(&port->dev,
+			"CDAT data read error rc=%d (retries %d)\n",
+			rc, retries);
+	}
 }
 EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
-- 
2.35.1

Re: [PATCH V9 8/9] cxl/port: Retry reading CDAT on failure

[Alison Schofield]

On Tue, May 31, 2022 at 08:26:31AM -0700, Ira Weiny wrote:
> From: Ira Weiny <ira.weiny@intel.com>
> 
> The CDAT read may fail for a number of reasons but mainly it is possible
> to get different parts of a valid state.  The checksum in the CDAT table
> protects against this.
> 
> Now that the cdat data is validated issue a retries if the CDAT read
> fails.  For now 5 retries are implemented.
> 
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> 
> ---

snip

> +
> +void read_cdat_data(struct cxl_port *port)
> +{
> +	int retries = 5;
> +	int rc;
> +
> +	while (retries--) {
> +		rc = __read_cdat_data(port);
> +		if (!rc)
> +			break;
> +		dev_err(&port->dev,
> +			"CDAT data read error rc=%d (retries %d)\n",
> +			rc, retries);
> +	}

Perhaps dev_dbg() on retries and dev_err() only when retries are exhausted.


>  }
>  EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
> -- 
> 2.35.1
> 

Re: [PATCH V9 8/9] cxl/port: Retry reading CDAT on failure

[Ira Weiny]

On Tue, May 31, 2022 at 10:07:43AM -0700, Alison Schofield wrote:
> On Tue, May 31, 2022 at 08:26:31AM -0700, Ira Weiny wrote:
> > From: Ira Weiny <ira.weiny@intel.com>
> > 
> > The CDAT read may fail for a number of reasons but mainly it is possible
> > to get different parts of a valid state.  The checksum in the CDAT table
> > protects against this.
> > 
> > Now that the cdat data is validated issue a retries if the CDAT read
> > fails.  For now 5 retries are implemented.
> > 
> > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> > 
> > ---
> 
> snip
> 
> > +
> > +void read_cdat_data(struct cxl_port *port)
> > +{
> > +	int retries = 5;
> > +	int rc;
> > +
> > +	while (retries--) {
> > +		rc = __read_cdat_data(port);
> > +		if (!rc)
> > +			break;
> > +		dev_err(&port->dev,
> > +			"CDAT data read error rc=%d (retries %d)\n",
> > +			rc, retries);
> > +	}
> 
> Perhaps dev_dbg() on retries and dev_err() only when retries are exhausted.

Yes thanks!
Ira

> 
> 
> >  }
> >  EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
> > -- 
> > 2.35.1
> > 

Re: [PATCH v9 8/9] cxl/port: Retry reading CDAT on failure

[Davidlohr Bueso]

On Tue, 31 May 2022, ira.weiny@intel.com wrote:

>From: Ira Weiny <ira.weiny@intel.com>
>
>The CDAT read may fail for a number of reasons but mainly it is possible
>to get different parts of a valid state.  The checksum in the CDAT table
>protects against this.
>
>Now that the cdat data is validated issue a retries if the CDAT read
>fails.  For now 5 retries are implemented.
>
>Signed-off-by: Ira Weiny <ira.weiny@intel.com>
>---
>Changes from V8
>	Move code to cxl/core/pci.c
>
>Changes from V6
>	Move to pci.c
>	Fix retries count
>	Change to 5 retries
>
>Changes from V5:
>	New patch -- easy to push off or drop.
>---
> drivers/cxl/core/pci.c | 32 +++++++++++++++++++++-----------
> 1 file changed, 21 insertions(+), 11 deletions(-)
>
>diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>index bb370df1cb6c..7f7dac9030a6 100644
>--- a/drivers/cxl/core/pci.c
>+++ b/drivers/cxl/core/pci.c
>@@ -620,20 +620,18 @@ static int cxl_cdat_read_table(struct cxl_port *port,
> 	return rc;
> }
>
>-void read_cdat_data(struct cxl_port *port)
>+static int __read_cdat_data(struct cxl_port *port)
> {
> 	struct device *dev = &port->dev;
> 	size_t cdat_length;
> 	int ret;
>
> 	if (cxl_cdat_get_length(port, &cdat_length))
>-		return;
>+		return 0;
>
> 	port->cdat.table = devm_kzalloc(dev, cdat_length, GFP_KERNEL);
>-	if (!port->cdat.table) {
>-		ret = -ENOMEM;
>-		goto error;
>-	}
>+	if (!port->cdat.table)
>+		return -ENOMEM;
>
> 	port->cdat.length = cdat_length;
> 	ret = cxl_cdat_read_table(port, &port->cdat);
>@@ -641,12 +639,24 @@ void read_cdat_data(struct cxl_port *port)
> 		devm_kfree(dev, port->cdat.table);
> 		port->cdat.table = NULL;
> 		port->cdat.length = 0;
>-		ret = -EIO;
>-		goto error;
>+		return -EIO;
> 	}
>
>-	return;
>-error:
>-	dev_err(dev, "CDAT data read error (%d)\n", ret);
>+	return 0;
>+}
>+
>+void read_cdat_data(struct cxl_port *port)
>+{
>+	int retries = 5;
>+	int rc;
>+
>+	while (retries--) {
>+		rc = __read_cdat_data(port);
>+		if (!rc)
>+			break;
>+		dev_err(&port->dev,
>+			"CDAT data read error rc=%d (retries %d)\n",
>+			rc, retries);
>+	}
> }
> EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);


Better a single final error message after exhausting all retries
instead of each time.

Thanks,
Davidlohr

[PATCH V9 9/9] cxl/port: Parse out DSMAS data from CDAT table

[ira.weiny]

From: Ira Weiny <ira.weiny@intel.com>

CXL Ports with memory devices attached need the information from the
Device Scoped Memory Affinity Structure (DSMAS).  This information is
contained within the CDAT table buffer which is previously read and
cached in the port device.

If CDAT data is available, parse and cache DSMAS data from the table.
Store this data in unmarshaled struct dsmas data structures for ease of
use later.

Signed-off-by: Ira Weiny <ira.weiny@intel.com>

---
Changes from V8
	Adjust to the cdat data being in cxl_port

Changes from V7
	Rebased on cxl-pending

Changes from V6
	Move to port.c
	It is not an error if no DSMAS data is found

Changes from V5
	Fix up sparse warnings
	Split out cdat_hdr_valid()
	Update cdat_hdr_valid()
		Remove revision and cs field parsing
			There is no point in these
		Add seq check and debug print.
	From Jonathan
		Add spaces around '+' and '/'
		use devm_krealloc() for dmas_ary
---
 drivers/cxl/cdat.h     | 17 +++++++++++
 drivers/cxl/core/pci.c | 65 ++++++++++++++++++++++++++++++++++++++++++
 drivers/cxl/cxl.h      |  2 ++
 drivers/cxl/cxlmem.h   |  4 +++
 drivers/cxl/cxlpci.h   |  1 +
 drivers/cxl/mem.c      |  1 +
 6 files changed, 90 insertions(+)

diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h
index 3d8945612511..0a510f73fe6d 100644
--- a/drivers/cxl/cdat.h
+++ b/drivers/cxl/cdat.h
@@ -85,6 +85,23 @@
 
 #define CXL_DOE_PROTOCOL_TABLE_ACCESS 2
 
+/**
+ * struct cxl_dsmas - host unmarshaled version of DSMAS data
+ *
+ * As defined in the Coherent Device Attribute Table (CDAT) specification this
+ * represents a single DSMAS entry in that table.
+ *
+ * @dpa_base: The lowest Device Physical Address associated with this DSMAD
+ * @length: Length in bytes of this DSMAD
+ * @non_volatile: If set, the memory region represents Non-Volatile memory
+ */
+struct cxl_dsmas {
+	u64 dpa_base;
+	u64 length;
+	/* Flags */
+	u8 non_volatile:1;
+};
+
 /**
  * struct cxl_cdat - CXL CDAT data
  *
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 7f7dac9030a6..a63c7dca056e 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -660,3 +660,68 @@ void read_cdat_data(struct cxl_port *port)
 	}
 }
 EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
+
+void parse_dsmas(struct cxl_memdev *cxlmd, struct cxl_port *port)
+{
+	struct device *dev = &port->dev;
+	struct cxl_dsmas *dsmas_ary = NULL;
+	u32 *data = port->cdat.table;
+	int bytes_left = port->cdat.length;
+	int nr_dsmas = 0;
+
+	if (!data) {
+		dev_info(dev, "No CDAT data available for DSMAS\n");
+		return;
+	}
+
+	/* Skip header */
+	data += CDAT_HEADER_LENGTH_DW;
+	bytes_left -= CDAT_HEADER_LENGTH_BYTES;
+
+	while (bytes_left > 0) {
+		u32 *cur_rec = data;
+		u8 type = FIELD_GET(CDAT_STRUCTURE_DW0_TYPE, cur_rec[0]);
+		u16 length = FIELD_GET(CDAT_STRUCTURE_DW0_LENGTH, cur_rec[0]);
+
+		if (type == CDAT_STRUCTURE_DW0_TYPE_DSMAS) {
+			struct cxl_dsmas *new_ary;
+			u8 flags;
+
+			new_ary = devm_krealloc(dev, dsmas_ary,
+					   sizeof(*dsmas_ary) * (nr_dsmas + 1),
+					   GFP_KERNEL);
+			if (!new_ary) {
+				dev_err(dev,
+					"Failed to allocate memory for DSMAS data (nr_dsmas %d)\n",
+					nr_dsmas);
+				return;
+			}
+			dsmas_ary = new_ary;
+
+			flags = FIELD_GET(CDAT_DSMAS_DW1_FLAGS, cur_rec[1]);
+
+			dsmas_ary[nr_dsmas].dpa_base = CDAT_DSMAS_DPA_OFFSET(cur_rec);
+			dsmas_ary[nr_dsmas].length = CDAT_DSMAS_DPA_LEN(cur_rec);
+			dsmas_ary[nr_dsmas].non_volatile = CDAT_DSMAS_NON_VOLATILE(flags);
+
+			dev_dbg(dev, "DSMAS %d: %llx:%llx %s\n",
+				nr_dsmas,
+				dsmas_ary[nr_dsmas].dpa_base,
+				dsmas_ary[nr_dsmas].dpa_base +
+					dsmas_ary[nr_dsmas].length,
+				(dsmas_ary[nr_dsmas].non_volatile ?
+					"Persistent" : "Volatile")
+				);
+
+			nr_dsmas++;
+		}
+
+		data += (length / sizeof(u32));
+		bytes_left -= length;
+	}
+
+	dev_dbg(dev, "Found %d DSMAS entries\n", nr_dsmas);
+	cxlmd->dsmas_ary = dsmas_ary;
+	cxlmd->nr_dsmas = nr_dsmas;
+}
+EXPORT_SYMBOL_NS_GPL(parse_dsmas, CXL);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 531b77d296c7..4d779a8fb807 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -10,6 +10,8 @@
 #include <linux/io.h>
 #include "cdat.h"
 
+#include "cdat.h"
+
 /**
  * DOC: cxl objects
  *
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 4d2764b865ab..ce5b00f3ebcb 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -36,6 +36,8 @@
  * @cxlds: The device state backing this device
  * @detach_work: active memdev lost a port in its ancestry
  * @id: id number of this memdev instance.
+ * @dsmas_ary: Array of DSMAS entries as parsed from the CDAT table
+ * @nr_dsmas: Number of entries in dsmas_ary
  */
 struct cxl_memdev {
 	struct device dev;
@@ -43,6 +45,8 @@ struct cxl_memdev {
 	struct cxl_dev_state *cxlds;
 	struct work_struct detach_work;
 	int id;
+	struct cxl_dsmas *dsmas_ary;
+	int nr_dsmas;
 };
 
 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index 35f0d4892eaa..5ab148fe7d65 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -76,4 +76,5 @@ struct cxl_dev_state;
 int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
 void cxl_find_cdat_mb(struct cxl_port *port);
 void read_cdat_data(struct cxl_port *port);
+void parse_dsmas(struct cxl_memdev *cxlmd, struct cxl_port *port);
 #endif /* __CXL_PCI_H__ */
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index c310f1fd3db0..a8768df4ae38 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -35,6 +35,7 @@ static int create_endpoint(struct cxl_memdev *cxlmd,
 	if (IS_ERR(endpoint))
 		return PTR_ERR(endpoint);
 
+	parse_dsmas(cxlmd, endpoint);
 	dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev));
 
 	if (!endpoint->dev.driver) {
-- 
2.35.1

Re: [PATCH V9 4/9] cxl/pci: Create PCI DOE mailbox's for memory devices

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 12667 bytes --]

CC: kbuild-all(a)lists.01.org
BCC: lkp(a)intel.com
In-Reply-To: <20220531152632.1397976-5-ira.weiny@intel.com>
References: <20220531152632.1397976-5-ira.weiny@intel.com>
TO: ira.weiny(a)intel.com

Hi,

I love your patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on next-20220601]
[cannot apply to helgaas-pci/next v5.18]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/intel-lab-lkp/linux/commits/ira-weiny-intel-com/CXL-Read-CDAT-and-DSMAS-data/20220531-232807
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 8ab2afa23bd197df47819a87f0265c0ac95c5b6a
:::::: branch date: 14 hours ago
:::::: commit date: 14 hours ago
config: i386-randconfig-m021 (https://download.01.org/0day-ci/archive/20220601/202206011300.xtt4Q8PJ-lkp(a)intel.com/config)
compiler: gcc-11 (Debian 11.3.0-1) 11.3.0

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/pci/doe.c:324 doe_statemachine_work() error: uninitialized symbol 'rc'.

vim +/rc +324 drivers/pci/doe.c

c67f0d52ff51105 Jonathan Cameron 2022-05-31  182  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  183  static void doe_statemachine_work(struct work_struct *work)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  184  {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  185  	struct delayed_work *w = to_delayed_work(work);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  186  	struct pci_doe_mb *doe_mb = container_of(w, struct pci_doe_mb,
c67f0d52ff51105 Jonathan Cameron 2022-05-31  187  						 statemachine);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  188  	struct pci_dev *pdev = doe_mb->pdev;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  189  	int offset = doe_mb->cap_offset;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  190  	struct pci_doe_task *task;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  191  	u32 val;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  192  	int rc;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  193  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  194  	mutex_lock(&doe_mb->task_lock);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  195  	task = doe_mb->cur_task;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  196  	mutex_unlock(&doe_mb->task_lock);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  197  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  198  	if (test_and_clear_bit(PCI_DOE_FLAG_ABORT, &doe_mb->flags)) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  199  		/*
c67f0d52ff51105 Jonathan Cameron 2022-05-31  200  		 * Currently only used during init - care needed if
c67f0d52ff51105 Jonathan Cameron 2022-05-31  201  		 * pci_doe_abort() is generally exposed as it would impact
c67f0d52ff51105 Jonathan Cameron 2022-05-31  202  		 * queries in flight.
c67f0d52ff51105 Jonathan Cameron 2022-05-31  203  		 */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  204  		if (task)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  205  			pci_err(pdev, "DOE [%x] Aborting with active task!\n",
c67f0d52ff51105 Jonathan Cameron 2022-05-31  206  				doe_mb->cap_offset);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  207  		doe_mb->state = DOE_WAIT_ABORT;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  208  		pci_doe_abort_start(doe_mb);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  209  		return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  210  	}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  211  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  212  	switch (doe_mb->state) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  213  	case DOE_IDLE:
c67f0d52ff51105 Jonathan Cameron 2022-05-31  214  		if (task == NULL)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  215  			return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  216  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  217  		rc = pci_doe_send_req(doe_mb, task);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  218  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  219  		/*
c67f0d52ff51105 Jonathan Cameron 2022-05-31  220  		 * The specification does not provide any guidance on how long
c67f0d52ff51105 Jonathan Cameron 2022-05-31  221  		 * some other entity could keep the DOE busy, so try for 1
c67f0d52ff51105 Jonathan Cameron 2022-05-31  222  		 * second then fail. Busy handling is best effort only, because
c67f0d52ff51105 Jonathan Cameron 2022-05-31  223  		 * there is no way of avoiding racing against another user of
c67f0d52ff51105 Jonathan Cameron 2022-05-31  224  		 * the DOE.
c67f0d52ff51105 Jonathan Cameron 2022-05-31  225  		 */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  226  		if (rc == -EBUSY) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  227  			doe_mb->busy_retries++;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  228  			if (doe_mb->busy_retries == PCI_DOE_BUSY_MAX_RETRIES) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  229  				/* Long enough, fail this request */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  230  				pci_warn(pdev,
c67f0d52ff51105 Jonathan Cameron 2022-05-31  231  					"DOE [%x] busy for too long (> 1 sec)\n",
c67f0d52ff51105 Jonathan Cameron 2022-05-31  232  					doe_mb->cap_offset);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  233  				doe_mb->busy_retries = 0;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  234  				goto err_busy;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  235  			}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  236  			schedule_delayed_work(w, HZ / PCI_DOE_BUSY_MAX_RETRIES);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  237  			return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  238  		}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  239  		if (rc)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  240  			goto err_abort;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  241  		doe_mb->busy_retries = 0;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  242  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  243  		doe_mb->state = DOE_WAIT_RESP;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  244  		doe_mb->timeout_jiffies = jiffies + HZ;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  245  		/* Now poll or wait for IRQ with timeout */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  246  		if (doe_mb->irq >= 0)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  247  			schedule_delayed_work(w, PCI_DOE_TIMEOUT);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  248  		else
c67f0d52ff51105 Jonathan Cameron 2022-05-31  249  			schedule_delayed_work(w, PCI_DOE_POLL_INTERVAL);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  250  		return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  251  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  252  	case DOE_WAIT_RESP:
c67f0d52ff51105 Jonathan Cameron 2022-05-31  253  		/* Not possible to get here with NULL task */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  254  		pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  255  		if (FIELD_GET(PCI_DOE_STATUS_ERROR, val)) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  256  			rc = -EIO;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  257  			goto err_abort;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  258  		}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  259  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  260  		if (!FIELD_GET(PCI_DOE_STATUS_DATA_OBJECT_READY, val)) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  261  			/* If not yet at timeout reschedule otherwise abort */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  262  			if (time_after(jiffies, doe_mb->timeout_jiffies)) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  263  				rc = -ETIMEDOUT;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  264  				goto err_abort;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  265  			}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  266  			schedule_delayed_work(w, PCI_DOE_POLL_INTERVAL);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  267  			return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  268  		}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  269  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  270  		rc  = pci_doe_recv_resp(doe_mb, task);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  271  		if (rc < 0)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  272  			goto err_abort;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  273  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  274  		doe_mb->state = DOE_IDLE;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  275  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  276  		retire_cur_task(doe_mb);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  277  		/* Set the return value to the length of received payload */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  278  		signal_task_complete(task, rc);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  279  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  280  		return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  281  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  282  	case DOE_WAIT_ABORT:
c67f0d52ff51105 Jonathan Cameron 2022-05-31  283  	case DOE_WAIT_ABORT_ON_ERR:
c67f0d52ff51105 Jonathan Cameron 2022-05-31  284  		pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  285  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  286  		if (!FIELD_GET(PCI_DOE_STATUS_ERROR, val) &&
c67f0d52ff51105 Jonathan Cameron 2022-05-31  287  		    !FIELD_GET(PCI_DOE_STATUS_BUSY, val)) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  288  			/* Back to normal state - carry on */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  289  			retire_cur_task(doe_mb);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  290  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  291  			/*
c67f0d52ff51105 Jonathan Cameron 2022-05-31  292  			 * For deliberately triggered abort, someone is
c67f0d52ff51105 Jonathan Cameron 2022-05-31  293  			 * waiting.
c67f0d52ff51105 Jonathan Cameron 2022-05-31  294  			 */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  295  			if (doe_mb->state == DOE_WAIT_ABORT) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  296  				if (task)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  297  					signal_task_complete(task, -EFAULT);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  298  				complete(&doe_mb->abort_c);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  299  			}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  300  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  301  			doe_mb->state = DOE_IDLE;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  302  			return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  303  		}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  304  		if (time_after(jiffies, doe_mb->timeout_jiffies)) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  305  			/* Task has timed out and is dead - abort */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  306  			pci_err(pdev, "DOE [%x] ABORT timed out\n",
c67f0d52ff51105 Jonathan Cameron 2022-05-31  307  				doe_mb->cap_offset);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  308  			set_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  309  			retire_cur_task(doe_mb);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  310  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  311  			if (doe_mb->state == DOE_WAIT_ABORT) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  312  				if (task)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  313  					signal_task_complete(task, -EFAULT);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  314  				complete(&doe_mb->abort_c);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  315  			}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  316  		}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  317  		return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  318  	}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  319  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  320  err_abort:
c67f0d52ff51105 Jonathan Cameron 2022-05-31  321  	doe_mb->state = DOE_WAIT_ABORT_ON_ERR;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  322  	pci_doe_abort_start(doe_mb);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  323  err_busy:
c67f0d52ff51105 Jonathan Cameron 2022-05-31 @324  	signal_task_complete(task, rc);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  325  	if (doe_mb->state == DOE_IDLE)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  326  		retire_cur_task(doe_mb);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  327  }
c67f0d52ff51105 Jonathan Cameron 2022-05-31  328  

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Re: [PATCH V9 4/9] cxl/pci: Create PCI DOE mailbox's for memory devices

[Dan Carpenter]

[-- Attachment #1: Type: text/plain, Size: 12005 bytes --]

Hi,

url:    https://github.com/intel-lab-lkp/linux/commits/ira-weiny-intel-com/CXL-Read-CDAT-and-DSMAS-data/20220531-232807
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 8ab2afa23bd197df47819a87f0265c0ac95c5b6a
config: i386-randconfig-m021 (https://download.01.org/0day-ci/archive/20220601/202206011300.xtt4Q8PJ-lkp(a)intel.com/config)
compiler: gcc-11 (Debian 11.3.0-1) 11.3.0

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/pci/doe.c:324 doe_statemachine_work() error: uninitialized symbol 'rc'.

vim +/rc +324 drivers/pci/doe.c

c67f0d52ff51105 Jonathan Cameron 2022-05-31  183  static void doe_statemachine_work(struct work_struct *work)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  184  {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  185  	struct delayed_work *w = to_delayed_work(work);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  186  	struct pci_doe_mb *doe_mb = container_of(w, struct pci_doe_mb,
c67f0d52ff51105 Jonathan Cameron 2022-05-31  187  						 statemachine);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  188  	struct pci_dev *pdev = doe_mb->pdev;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  189  	int offset = doe_mb->cap_offset;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  190  	struct pci_doe_task *task;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  191  	u32 val;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  192  	int rc;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  193  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  194  	mutex_lock(&doe_mb->task_lock);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  195  	task = doe_mb->cur_task;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  196  	mutex_unlock(&doe_mb->task_lock);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  197  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  198  	if (test_and_clear_bit(PCI_DOE_FLAG_ABORT, &doe_mb->flags)) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  199  		/*
c67f0d52ff51105 Jonathan Cameron 2022-05-31  200  		 * Currently only used during init - care needed if
c67f0d52ff51105 Jonathan Cameron 2022-05-31  201  		 * pci_doe_abort() is generally exposed as it would impact
c67f0d52ff51105 Jonathan Cameron 2022-05-31  202  		 * queries in flight.
c67f0d52ff51105 Jonathan Cameron 2022-05-31  203  		 */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  204  		if (task)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  205  			pci_err(pdev, "DOE [%x] Aborting with active task!\n",
c67f0d52ff51105 Jonathan Cameron 2022-05-31  206  				doe_mb->cap_offset);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  207  		doe_mb->state = DOE_WAIT_ABORT;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  208  		pci_doe_abort_start(doe_mb);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  209  		return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  210  	}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  211  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  212  	switch (doe_mb->state) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  213  	case DOE_IDLE:
c67f0d52ff51105 Jonathan Cameron 2022-05-31  214  		if (task == NULL)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  215  			return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  216  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  217  		rc = pci_doe_send_req(doe_mb, task);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  218  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  219  		/*
c67f0d52ff51105 Jonathan Cameron 2022-05-31  220  		 * The specification does not provide any guidance on how long
c67f0d52ff51105 Jonathan Cameron 2022-05-31  221  		 * some other entity could keep the DOE busy, so try for 1
c67f0d52ff51105 Jonathan Cameron 2022-05-31  222  		 * second then fail. Busy handling is best effort only, because
c67f0d52ff51105 Jonathan Cameron 2022-05-31  223  		 * there is no way of avoiding racing against another user of
c67f0d52ff51105 Jonathan Cameron 2022-05-31  224  		 * the DOE.
c67f0d52ff51105 Jonathan Cameron 2022-05-31  225  		 */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  226  		if (rc == -EBUSY) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  227  			doe_mb->busy_retries++;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  228  			if (doe_mb->busy_retries == PCI_DOE_BUSY_MAX_RETRIES) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  229  				/* Long enough, fail this request */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  230  				pci_warn(pdev,
c67f0d52ff51105 Jonathan Cameron 2022-05-31  231  					"DOE [%x] busy for too long (> 1 sec)\n",
c67f0d52ff51105 Jonathan Cameron 2022-05-31  232  					doe_mb->cap_offset);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  233  				doe_mb->busy_retries = 0;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  234  				goto err_busy;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  235  			}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  236  			schedule_delayed_work(w, HZ / PCI_DOE_BUSY_MAX_RETRIES);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  237  			return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  238  		}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  239  		if (rc)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  240  			goto err_abort;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  241  		doe_mb->busy_retries = 0;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  242  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  243  		doe_mb->state = DOE_WAIT_RESP;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  244  		doe_mb->timeout_jiffies = jiffies + HZ;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  245  		/* Now poll or wait for IRQ with timeout */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  246  		if (doe_mb->irq >= 0)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  247  			schedule_delayed_work(w, PCI_DOE_TIMEOUT);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  248  		else
c67f0d52ff51105 Jonathan Cameron 2022-05-31  249  			schedule_delayed_work(w, PCI_DOE_POLL_INTERVAL);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  250  		return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  251  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  252  	case DOE_WAIT_RESP:
c67f0d52ff51105 Jonathan Cameron 2022-05-31  253  		/* Not possible to get here with NULL task */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  254  		pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  255  		if (FIELD_GET(PCI_DOE_STATUS_ERROR, val)) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  256  			rc = -EIO;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  257  			goto err_abort;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  258  		}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  259  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  260  		if (!FIELD_GET(PCI_DOE_STATUS_DATA_OBJECT_READY, val)) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  261  			/* If not yet at timeout reschedule otherwise abort */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  262  			if (time_after(jiffies, doe_mb->timeout_jiffies)) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  263  				rc = -ETIMEDOUT;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  264  				goto err_abort;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  265  			}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  266  			schedule_delayed_work(w, PCI_DOE_POLL_INTERVAL);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  267  			return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  268  		}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  269  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  270  		rc  = pci_doe_recv_resp(doe_mb, task);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  271  		if (rc < 0)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  272  			goto err_abort;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  273  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  274  		doe_mb->state = DOE_IDLE;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  275  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  276  		retire_cur_task(doe_mb);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  277  		/* Set the return value to the length of received payload */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  278  		signal_task_complete(task, rc);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  279  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  280  		return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  281  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  282  	case DOE_WAIT_ABORT:
c67f0d52ff51105 Jonathan Cameron 2022-05-31  283  	case DOE_WAIT_ABORT_ON_ERR:
c67f0d52ff51105 Jonathan Cameron 2022-05-31  284  		pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  285  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  286  		if (!FIELD_GET(PCI_DOE_STATUS_ERROR, val) &&
c67f0d52ff51105 Jonathan Cameron 2022-05-31  287  		    !FIELD_GET(PCI_DOE_STATUS_BUSY, val)) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  288  			/* Back to normal state - carry on */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  289  			retire_cur_task(doe_mb);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  290  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  291  			/*
c67f0d52ff51105 Jonathan Cameron 2022-05-31  292  			 * For deliberately triggered abort, someone is
c67f0d52ff51105 Jonathan Cameron 2022-05-31  293  			 * waiting.
c67f0d52ff51105 Jonathan Cameron 2022-05-31  294  			 */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  295  			if (doe_mb->state == DOE_WAIT_ABORT) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  296  				if (task)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  297  					signal_task_complete(task, -EFAULT);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  298  				complete(&doe_mb->abort_c);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  299  			}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  300  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  301  			doe_mb->state = DOE_IDLE;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  302  			return;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  303  		}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  304  		if (time_after(jiffies, doe_mb->timeout_jiffies)) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  305  			/* Task has timed out and is dead - abort */
c67f0d52ff51105 Jonathan Cameron 2022-05-31  306  			pci_err(pdev, "DOE [%x] ABORT timed out\n",
c67f0d52ff51105 Jonathan Cameron 2022-05-31  307  				doe_mb->cap_offset);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  308  			set_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  309  			retire_cur_task(doe_mb);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  310  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  311  			if (doe_mb->state == DOE_WAIT_ABORT) {
c67f0d52ff51105 Jonathan Cameron 2022-05-31  312  				if (task)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  313  					signal_task_complete(task, -EFAULT);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  314  				complete(&doe_mb->abort_c);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  315  			}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  316  		}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  317  		return;

Smatch thinks there needs to be a default path.  Ignore if a false
positive.

c67f0d52ff51105 Jonathan Cameron 2022-05-31  318  	}
c67f0d52ff51105 Jonathan Cameron 2022-05-31  319  
c67f0d52ff51105 Jonathan Cameron 2022-05-31  320  err_abort:
c67f0d52ff51105 Jonathan Cameron 2022-05-31  321  	doe_mb->state = DOE_WAIT_ABORT_ON_ERR;
c67f0d52ff51105 Jonathan Cameron 2022-05-31  322  	pci_doe_abort_start(doe_mb);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  323  err_busy:
c67f0d52ff51105 Jonathan Cameron 2022-05-31 @324  	signal_task_complete(task, rc);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  325  	if (doe_mb->state == DOE_IDLE)
c67f0d52ff51105 Jonathan Cameron 2022-05-31  326  		retire_cur_task(doe_mb);
c67f0d52ff51105 Jonathan Cameron 2022-05-31  327  }

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