* [Buildroot] [PATCH 1/2] board/freescale/common/imx: align u-boot-spl to 4 bytes
@ 2022-08-16 12:07 Bram Vlerick
2022-08-23 21:30 ` Thomas Petazzoni via buildroot
2022-09-17 12:32 ` Peter Korsgaard
0 siblings, 2 replies; 4+ messages in thread
From: Bram Vlerick @ 2022-08-16 12:07 UTC (permalink / raw)
To: buildroot
When enable DM for SPL binary, the DTB part of SPL may not 4 bytes aligned.
If u-boot-spl is not aligned, the offset of the DDR firmware is not 4
byte aligned when u-boot-spl-ddr.bin is created. This causes the ddr
firmware to not be loaded correctly at boot.
See imx-mkimage commit bba038d893046b44683182dba540f104dab80fe7 for
implementation in imx-mkimage.
Signed-off-by: Bram Vlerick <bram.vlerick@openpixelsystems.org>
---
.../freescale/common/imx/imx8-bootloader-prepare.sh | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/board/freescale/common/imx/imx8-bootloader-prepare.sh b/board/freescale/common/imx/imx8-bootloader-prepare.sh
index 9025fb132d..ace0f6d610 100755
--- a/board/freescale/common/imx/imx8-bootloader-prepare.sh
+++ b/board/freescale/common/imx/imx8-bootloader-prepare.sh
@@ -9,7 +9,8 @@ main ()
fi
if grep -Eq "^BR2_PACKAGE_FREESCALE_IMX_PLATFORM_IMX8M=y$" ${BR2_CONFIG}; then
- cat ${BINARIES_DIR}/u-boot-spl.bin ${BINARIES_DIR}/ddr_fw.bin > ${BINARIES_DIR}/u-boot-spl-ddr.bin
+ dd if=${BINARIES_DIR}/u-boot-spl.bin of=${BINARIES_DIR}/u-boot-spl-padded.bin bs=4 conv=sync
+ cat ${BINARIES_DIR}/u-boot-spl-padded.bin ${BINARIES_DIR}/ddr_fw.bin > ${BINARIES_DIR}/u-boot-spl-ddr.bin
if grep -Eq "^BR2_TARGET_OPTEE_OS=y$" ${BR2_CONFIG}; then
BL31=${BINARIES_DIR}/bl31.bin BL32=${BINARIES_DIR}/tee.bin BL33=${BINARIES_DIR}/u-boot-nodtb.bin TEE_LOAD_ADDR=0xfe000000 ATF_LOAD_ADDR=0x00910000 ${HOST_DIR}/bin/mkimage_fit_atf.sh ${UBOOT_DTB} > ${BINARIES_DIR}/u-boot.its
else
@@ -20,7 +21,8 @@ main ()
${HOST_DIR}/bin/mkimage_imx8 -fit -signed_hdmi ${BINARIES_DIR}/signed_hdmi_imx8m.bin -loader ${BINARIES_DIR}/u-boot-spl-ddr.bin 0x7E1000 -second_loader ${BINARIES_DIR}/u-boot.itb 0x40200000 0x60000 -out ${BINARIES_DIR}/imx8-boot-sd.bin
elif grep -Eq "^BR2_PACKAGE_FREESCALE_IMX_PLATFORM_IMX8MM=y$" ${BR2_CONFIG}; then
- cat ${BINARIES_DIR}/u-boot-spl.bin ${BINARIES_DIR}/ddr_fw.bin > ${BINARIES_DIR}/u-boot-spl-ddr.bin
+ dd if=${BINARIES_DIR}/u-boot-spl.bin of=${BINARIES_DIR}/u-boot-spl-padded.bin bs=4 conv=sync
+ cat ${BINARIES_DIR}/u-boot-spl-padded.bin ${BINARIES_DIR}/ddr_fw.bin > ${BINARIES_DIR}/u-boot-spl-ddr.bin
if grep -Eq "^BR2_TARGET_OPTEE_OS=y$" ${BR2_CONFIG}; then
BL31=${BINARIES_DIR}/bl31.bin BL32=${BINARIES_DIR}/tee.bin BL33=${BINARIES_DIR}/u-boot-nodtb.bin TEE_LOAD_ADDR=0xbe000000 ATF_LOAD_ADDR=0x00920000 ${HOST_DIR}/bin/mkimage_fit_atf.sh ${UBOOT_DTB} > ${BINARIES_DIR}/u-boot.its
else
@@ -31,7 +33,8 @@ main ()
${HOST_DIR}/bin/mkimage_imx8 -fit -loader ${BINARIES_DIR}/u-boot-spl-ddr.bin 0x7E1000 -second_loader ${BINARIES_DIR}/u-boot.itb 0x40200000 0x60000 -out ${BINARIES_DIR}/imx8-boot-sd.bin
elif grep -Eq "^BR2_PACKAGE_FREESCALE_IMX_PLATFORM_IMX8MN=y$" ${BR2_CONFIG}; then
- cat ${BINARIES_DIR}/u-boot-spl.bin ${BINARIES_DIR}/ddr_fw.bin > ${BINARIES_DIR}/u-boot-spl-ddr.bin
+ dd if=${BINARIES_DIR}/u-boot-spl.bin of=${BINARIES_DIR}/u-boot-spl-padded.bin bs=4 conv=sync
+ cat ${BINARIES_DIR}/u-boot-spl-padded.bin ${BINARIES_DIR}/ddr_fw.bin > ${BINARIES_DIR}/u-boot-spl-ddr.bin
if grep -Eq "^BR2_TARGET_OPTEE_OS=y$" ${BR2_CONFIG}; then
BL31=${BINARIES_DIR}/bl31.bin BL32=${BINARIES_DIR}/tee.bin BL33=${BINARIES_DIR}/u-boot-nodtb.bin TEE_LOAD_ADDR=0x56000000 ATF_LOAD_ADDR=0x00960000 ${HOST_DIR}/bin/mkimage_fit_atf.sh ${UBOOT_DTB} > ${BINARIES_DIR}/u-boot.its
else
@@ -42,7 +45,8 @@ main ()
${HOST_DIR}/bin/mkimage_imx8 -v v2 -fit -loader ${BINARIES_DIR}/u-boot-spl-ddr.bin 0x912000 -second_loader ${BINARIES_DIR}/u-boot.itb 0x40200000 0x60000 -out ${BINARIES_DIR}/imx8-boot-sd.bin
elif grep -Eq "^BR2_PACKAGE_FREESCALE_IMX_PLATFORM_IMX8MP=y$" ${BR2_CONFIG}; then
- cat ${BINARIES_DIR}/u-boot-spl.bin ${BINARIES_DIR}/ddr_fw.bin > ${BINARIES_DIR}/u-boot-spl-ddr.bin
+ dd if=${BINARIES_DIR}/u-boot-spl.bin of=${BINARIES_DIR}/u-boot-spl-padded.bin bs=4 conv=sync
+ cat ${BINARIES_DIR}/u-boot-spl-padded.bin ${BINARIES_DIR}/ddr_fw.bin > ${BINARIES_DIR}/u-boot-spl-ddr.bin
if grep -Eq "^BR2_TARGET_OPTEE_OS=y$" ${BR2_CONFIG}; then
BL31=${BINARIES_DIR}/bl31.bin BL32=${BINARIES_DIR}/tee.bin BL33=${BINARIES_DIR}/u-boot-nodtb.bin TEE_LOAD_ADDR=0x56000000 ATF_LOAD_ADDR=0x00970000 ${HOST_DIR}/bin/mkimage_fit_atf.sh ${UBOOT_DTB} > ${BINARIES_DIR}/u-boot.its
else
--
2.31.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Buildroot] [PATCH 1/2] board/freescale/common/imx: align u-boot-spl to 4 bytes
2022-08-16 12:07 [Buildroot] [PATCH 1/2] board/freescale/common/imx: align u-boot-spl to 4 bytes Bram Vlerick
@ 2022-08-23 21:30 ` Thomas Petazzoni via buildroot
2022-08-24 7:38 ` Bram Vlerick
2022-09-17 12:32 ` Peter Korsgaard
1 sibling, 1 reply; 4+ messages in thread
From: Thomas Petazzoni via buildroot @ 2022-08-23 21:30 UTC (permalink / raw)
To: Bram Vlerick; +Cc: buildroot
Hello Bram,
On Tue, 16 Aug 2022 14:07:17 +0200
Bram Vlerick <bram.vlerick@openpixelsystems.org> wrote:
> When enable DM for SPL binary, the DTB part of SPL may not 4 bytes aligned.
> If u-boot-spl is not aligned, the offset of the DDR firmware is not 4
> byte aligned when u-boot-spl-ddr.bin is created. This causes the ddr
> firmware to not be loaded correctly at boot.
>
> See imx-mkimage commit bba038d893046b44683182dba540f104dab80fe7 for
> implementation in imx-mkimage.
>
> Signed-off-by: Bram Vlerick <bram.vlerick@openpixelsystems.org>
> ---
> .../freescale/common/imx/imx8-bootloader-prepare.sh | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
Applied to master, thanks. Even though your patch was marked PATCH 1/2,
there was no PATCH 2/2 posted on the list. Was this a mistake?
Thanks!
Thomas
--
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Buildroot] [PATCH 1/2] board/freescale/common/imx: align u-boot-spl to 4 bytes
2022-08-23 21:30 ` Thomas Petazzoni via buildroot
@ 2022-08-24 7:38 ` Bram Vlerick
0 siblings, 0 replies; 4+ messages in thread
From: Bram Vlerick @ 2022-08-24 7:38 UTC (permalink / raw)
To: Thomas Petazzoni; +Cc: buildroot
Hi Thomas,
Seems like I made a mistake in my git send-email. Indeed there is no
PATCH 2/2. Sorry for that.
Thanks,
Bram
On Tue, Aug 23, 2022 at 11:30:12PM +0200, Thomas Petazzoni wrote:
> Hello Bram,
>
> On Tue, 16 Aug 2022 14:07:17 +0200
> Bram Vlerick <bram.vlerick@openpixelsystems.org> wrote:
>
> > When enable DM for SPL binary, the DTB part of SPL may not 4 bytes aligned.
> > If u-boot-spl is not aligned, the offset of the DDR firmware is not 4
> > byte aligned when u-boot-spl-ddr.bin is created. This causes the ddr
> > firmware to not be loaded correctly at boot.
> >
> > See imx-mkimage commit bba038d893046b44683182dba540f104dab80fe7 for
> > implementation in imx-mkimage.
> >
> > Signed-off-by: Bram Vlerick <bram.vlerick@openpixelsystems.org>
> > ---
> > .../freescale/common/imx/imx8-bootloader-prepare.sh | 12 ++++++++----
> > 1 file changed, 8 insertions(+), 4 deletions(-)
>
> Applied to master, thanks. Even though your patch was marked PATCH 1/2,
> there was no PATCH 2/2 posted on the list. Was this a mistake?
>
> Thanks!
>
> Thomas
> --
> Thomas Petazzoni, CTO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Buildroot] [PATCH 1/2] board/freescale/common/imx: align u-boot-spl to 4 bytes
2022-08-16 12:07 [Buildroot] [PATCH 1/2] board/freescale/common/imx: align u-boot-spl to 4 bytes Bram Vlerick
2022-08-23 21:30 ` Thomas Petazzoni via buildroot
@ 2022-09-17 12:32 ` Peter Korsgaard
1 sibling, 0 replies; 4+ messages in thread
From: Peter Korsgaard @ 2022-09-17 12:32 UTC (permalink / raw)
To: Bram Vlerick; +Cc: buildroot
>>>>> "Bram" == Bram Vlerick <bram.vlerick@openpixelsystems.org> writes:
> When enable DM for SPL binary, the DTB part of SPL may not 4 bytes aligned.
> If u-boot-spl is not aligned, the offset of the DDR firmware is not 4
> byte aligned when u-boot-spl-ddr.bin is created. This causes the ddr
> firmware to not be loaded correctly at boot.
> See imx-mkimage commit bba038d893046b44683182dba540f104dab80fe7 for
> implementation in imx-mkimage.
> Signed-off-by: Bram Vlerick <bram.vlerick@openpixelsystems.org>
Committed to 2022.05.x and 2022.02.x, thanks.
--
Bye, Peter Korsgaard
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-08-16 12:07 [Buildroot] [PATCH 1/2] board/freescale/common/imx: align u-boot-spl to 4 bytes Bram Vlerick
2022-08-23 21:30 ` Thomas Petazzoni via buildroot
2022-08-24 7:38 ` Bram Vlerick
2022-09-17 12:32 ` Peter Korsgaard
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