* [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC
@ 2024-02-05 12:40 Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 01/48] ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names properties Lad Prabhakar
` (50 more replies)
0 siblings, 51 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:40 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
Hi All,
This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
support for this SoC has already been added to 6.1-cip kernel.
RFC->v1
* Patch #35 updated according uptstream for easier maitainance.
Rest of the patches have been unchanged.
* Merged RFC series [0] and preporatory series [1].
* Previous test run results can be found at [2].
* RISC-V Renesas defconfig file can be found at [3].
[0] https://patchwork.kernel.org/project/cip-dev/cover/20240130203346.94488-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[1] https://patchwork.kernel.org/project/cip-dev/cover/20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[2] https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1160504705
[3] https://gitlab.com/cip-project/cip-kernel/cip-kernel-config/-/blob/rzfive-5.10-cip/5.10.y-cip/riscv/renesas_defconfig?ref_type=heads
Cheers,
Prabhakar
Christoph Hellwig (5):
dma-direct: add support for dma_coherent_default_memory
dma-mapping: allow using the global coherent pool for !ARM
dma-mapping: simplify dma_init_coherent_memory
dma-mapping: add a dma_init_global_coherent helper
dma-mapping: make the global coherent pool conditional
Conor Dooley (1):
riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy
node
Heiko Stuebner (1):
of: also handle dma-noncoherent in of_dma_is_coherent()
Lad Prabhakar (34):
ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and
interrupt-names properties
ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels
arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels
arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels
arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to
board DTS
arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS
arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro
to specify interrupt property
arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels
arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
riscv: Kconfig: Enable cpufreq kconfig menu
irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC
clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback
mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option
dependant on ARCH_RENESAS
dt-bindings: riscv: Sort the CPU core list alphabetically
dt-bindings: riscv: Add Andes AX45MP core to the list
dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and
Reset Definitions
dt-bindings: cache: andestech,ax45mp-cache: Add DT binding
documentation for L2 cache controller
soc: renesas: Identify RZ/Five SoC
clk: renesas: r9a07g043: Add support for RZ/Five SoC
cache: Add L2 cache management for Andes AX45MP RISC-V core
cache: ax45mp_cache: Add non coherent support
soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable
ADC/OPP/Thermal Zones/TSU
riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
riscv: dts: renesas: rzfive-smarc-som: Enable WDT
riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes
riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for
ETH{0,1}
riscv: dts: renesas: r9a07g043f: Add L2 cache node
riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property
riscv: dts: renesas: rzfive-smarc: Enable the blocks which were
explicitly disabled
Niklas Cassel (2):
irqchip/sifive-plic: Improve naming scheme for per context offsets
irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode
Samuel Holland (4):
of/irq: Use interrupts-extended to find parent
irqchip/sifive-plic: Make better use of the effective affinity mask
irqchip/sifive-plic: Separate the enable and mask operations
clocksource/drivers/riscv: Increase the clock source rating
Xiongfeng Wang (1):
cacheinfo: clear cache_leaves(cpu) in free_cache_attributes()
.../cache/andestech,ax45mp-cache.yaml | 81 ++++
.../devicetree/bindings/riscv/cpus.yaml | 7 +-
.../bindings/sound/renesas,rz-ssi.yaml | 21 +-
MAINTAINERS | 7 +
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 350 ++++++++----------
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 72 ++++
.../boot/dts/renesas/r9a07g043u11-smarc.dts | 17 +-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +-
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 19 +-
arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 14 -
arch/riscv/Kconfig | 3 +-
arch/riscv/Kconfig.socs | 5 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/Makefile | 2 +
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 72 ++++
.../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 24 ++
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 8 +
arch/riscv/kernel/time.c | 9 -
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/base/cacheinfo.c | 1 +
drivers/cache/Kconfig | 12 +
drivers/cache/Makefile | 3 +
drivers/cache/ax45mp_cache.c | 239 ++++++++++++
drivers/clk/renesas/r9a07g043-cpg.c | 32 ++
drivers/clocksource/renesas-ostm.c | 2 +-
drivers/clocksource/timer-riscv.c | 7 +-
drivers/irqchip/Kconfig | 1 +
drivers/irqchip/irq-sifive-plic.c | 178 ++++++---
drivers/mmc/host/Kconfig | 4 +-
drivers/of/address.c | 17 +-
drivers/of/irq.c | 13 +-
drivers/soc/renesas/Kconfig | 12 +
drivers/soc/renesas/renesas-soc.c | 13 +
include/dt-bindings/clock/r9a07g043-cpg.h | 20 +
include/linux/dma-map-ops.h | 18 +-
kernel/dma/Kconfig | 4 +
kernel/dma/coherent.c | 161 ++++----
kernel/dma/direct.c | 17 +
sound/soc/sh/rz-ssi.c | 63 +++-
41 files changed, 1143 insertions(+), 435 deletions(-)
create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/Makefile
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
create mode 100644 drivers/cache/Kconfig
create mode 100644 drivers/cache/Makefile
create mode 100644 drivers/cache/ax45mp_cache.c
--
2.34.1
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 01/48] ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names properties
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
@ 2024-02-05 12:40 ` Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 02/48] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels Lad Prabhakar
` (49 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:40 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 56a3840486ae22c42176828e25d4073712837bfd upstream.
From R01UH0914EJ0120 Rev.1.20 HW manual, for full duplex channels
(SSI0/1/3) dma_rt interrupt has now being marked as reserved and similarly
for half duplex channel (SSI2) dma_rx and dma_tx interrupts have now being
marked as reserved (this applies to RZ/G2L and alike SoC's). This patch
updates the binding doc to match the same.
While at it also updated the example node.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230217185225.43310-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/sound/renesas,rz-ssi.yaml | 21 +++++++++++--------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
index 0d9840375132..5bd86a685cf7 100644
--- a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
+++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
@@ -22,14 +22,18 @@ properties:
maxItems: 1
interrupts:
- maxItems: 4
+ minItems: 2
+ maxItems: 3
interrupt-names:
- items:
- - const: int_req
- - const: dma_rx
- - const: dma_tx
- - const: dma_rt
+ oneOf:
+ - items:
+ - const: int_req
+ - const: dma_rx
+ - const: dma_tx
+ - items:
+ - const: int_req
+ - const: dma_rt
clocks:
maxItems: 4
@@ -103,9 +107,8 @@ examples:
reg = <0x10049c00 0x400>;
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
<&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
<&audio_clk1>,
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 02/48] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 01/48] ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names properties Lad Prabhakar
@ 2024-02-05 12:40 ` Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 03/48] arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels Lad Prabhakar
` (48 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:40 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 38c042b59af0248a8b13f01b1a09d890997c9f6e upstream.
For half duplex channels we dont have separate interrupts for Tx and Rx
instead we have single interrupt Rt (where the signal for Rx and Tx is
muxed). To handle such a case install a handler in case we have a dma_rt
interrupt specified in the DT for the PIO mode.
Note, for backward compatibility we check if the Rx and Tx interrupts
are present first instead of checking Rt interrupt.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20230217185225.43310-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
sound/soc/sh/rz-ssi.c | 63 ++++++++++++++++++++++++++++++-------------
1 file changed, 44 insertions(+), 19 deletions(-)
diff --git a/sound/soc/sh/rz-ssi.c b/sound/soc/sh/rz-ssi.c
index 4901a660ffc5..ff5a650ac2b1 100644
--- a/sound/soc/sh/rz-ssi.c
+++ b/sound/soc/sh/rz-ssi.c
@@ -109,6 +109,7 @@ struct rz_ssi_priv {
int irq_int;
int irq_tx;
int irq_rx;
+ int irq_rt;
spinlock_t lock;
@@ -565,6 +566,17 @@ static irqreturn_t rz_ssi_interrupt(int irq, void *data)
rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
}
+ if (irq == ssi->irq_rt) {
+ struct snd_pcm_substream *substream = strm->substream;
+
+ if (rz_ssi_stream_is_play(ssi, substream)) {
+ strm->transfer(ssi, &ssi->playback);
+ } else {
+ strm->transfer(ssi, &ssi->capture);
+ rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
+ }
+ }
+
return IRQ_HANDLED;
}
@@ -992,26 +1004,39 @@ static int rz_ssi_probe(struct platform_device *pdev)
if (!rz_ssi_is_dma_enabled(ssi)) {
/* Tx and Rx interrupts (pio only) */
ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
- if (ssi->irq_tx < 0)
- return ssi->irq_tx;
-
- ret = devm_request_irq(&pdev->dev, ssi->irq_tx,
- &rz_ssi_interrupt, 0,
- dev_name(&pdev->dev), ssi);
- if (ret < 0)
- return dev_err_probe(&pdev->dev, ret,
- "irq request error (dma_tx)\n");
-
ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
- if (ssi->irq_rx < 0)
- return ssi->irq_rx;
-
- ret = devm_request_irq(&pdev->dev, ssi->irq_rx,
- &rz_ssi_interrupt, 0,
- dev_name(&pdev->dev), ssi);
- if (ret < 0)
- return dev_err_probe(&pdev->dev, ret,
- "irq request error (dma_rx)\n");
+ if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) {
+ ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt");
+ if (ssi->irq_rt < 0)
+ return ssi->irq_rt;
+
+ ret = devm_request_irq(&pdev->dev, ssi->irq_rt,
+ &rz_ssi_interrupt, 0,
+ dev_name(&pdev->dev), ssi);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "irq request error (dma_tx)\n");
+ } else {
+ if (ssi->irq_tx < 0)
+ return ssi->irq_tx;
+
+ if (ssi->irq_rx < 0)
+ return ssi->irq_rx;
+
+ ret = devm_request_irq(&pdev->dev, ssi->irq_tx,
+ &rz_ssi_interrupt, 0,
+ dev_name(&pdev->dev), ssi);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "irq request error (dma_tx)\n");
+
+ ret = devm_request_irq(&pdev->dev, ssi->irq_rx,
+ &rz_ssi_interrupt, 0,
+ dev_name(&pdev->dev), ssi);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "irq request error (dma_rx)\n");
+ }
}
ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 03/48] arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 01/48] ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names properties Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 02/48] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels Lad Prabhakar
@ 2024-02-05 12:40 ` Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 04/48] arm64: dts: renesas: r9a07g044: " Lad Prabhakar
` (47 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:40 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit c2b0dc0e83ef4a74cbe381fd0c84cea16cf067f0 upstream.
From R01UH0936EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI
channels have been updated,
SPI 329 - SSIF0 is now marked as reserved
SPI 333 - SSIF1 is now marked as reserved
SPI 335 - SSIF2 is now marked as reserved
SPI 336 - SSIF2 is now marked as reserved
SPI 341 - SSIF3 is now marked as reserved
This patch drops the above IRQs from SoC DTSI.
Fixes: cd0339ec25895c0b ("arm64: dts: renesas: r9a07g054: Add SSI{1,2,3} nodes and fillup the SSI0 stub node")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230217185225.43310-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index d2de7c615aed..fa2dfd5eee41 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -249,9 +249,8 @@ ssi0: ssi@10049c00 {
reg = <0 0x10049c00 0 0x400>;
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
<&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -270,9 +269,8 @@ ssi1: ssi@1004a000 {
reg = <0 0x1004a000 0 0x400>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
<&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -290,10 +288,8 @@ ssi2: ssi@1004a400 {
"renesas,rz-ssi";
reg = <0 0x1004a400 0 0x400>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ interrupt-names = "int_req", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
<&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -312,9 +308,8 @@ ssi3: ssi@1004a800 {
reg = <0 0x1004a800 0 0x400>;
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
<&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 04/48] arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (2 preceding siblings ...)
2024-02-05 12:40 ` [PATCH 5.10.y-cip 03/48] arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels Lad Prabhakar
@ 2024-02-05 12:40 ` Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 05/48] arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS Lad Prabhakar
` (46 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:40 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 5da750ddd96454757a3b467e968e3fb70bb12bc8 upstream.
From R01UH0914EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI
channels have been updated,
SPI 329 - SSIF0 is now marked as reserved
SPI 333 - SSIF1 is now marked as reserved
SPI 335 - SSIF2 is now marked as reserved
SPI 336 - SSIF2 is now marked as reserved
SPI 341 - SSIF3 is now marked as reserved
This patch drops the above IRQs from SoC DTSI.
Fixes: 92a341315afc9 ("arm64: dts: renesas: r9a07g044: Add SSI support")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230217185225.43310-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 0495f1168a6c..f7edace31807 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -249,9 +249,8 @@ ssi0: ssi@10049c00 {
reg = <0 0x10049c00 0 0x400>;
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
<&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -270,9 +269,8 @@ ssi1: ssi@1004a000 {
reg = <0 0x1004a000 0 0x400>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
<&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -290,10 +288,8 @@ ssi2: ssi@1004a400 {
"renesas,rz-ssi";
reg = <0 0x1004a400 0 0x400>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ interrupt-names = "int_req", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
<&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -312,9 +308,8 @@ ssi3: ssi@1004a800 {
reg = <0 0x1004a800 0 0x400>;
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
<&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 05/48] arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (3 preceding siblings ...)
2024-02-05 12:40 ` [PATCH 5.10.y-cip 04/48] arm64: dts: renesas: r9a07g044: " Lad Prabhakar
@ 2024-02-05 12:40 ` Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 06/48] arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into " Lad Prabhakar
` (45 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:40 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
It makes sense to have the configuration options in board dts, so move
PMOD_SCI0_EN macro to r9a07g043u11-smarc.dts.
This is in preparation of re-using the SoM and carrier board DTSIs
for RZ/Five SMARC EVK.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 4 ++++
arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 3 ---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
index 121e55282d18..d882661c6dde 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
@@ -6,6 +6,10 @@
*/
/dts-v1/;
+
+/* Please set this macro to 1 for enabling SCI0 on PMOD1 */
+#define PMOD_SCI0_EN 0
+
#include "r9a07g043.dtsi"
#include "rzg2ul-smarc.dtsi"
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
index c6981bea40a4..44d5c82a9f18 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
@@ -15,9 +15,6 @@
#define SW_SW0_DEV_SEL 1
#define SW_ET0_EN_N 1
-/* Please set this macro to 1 for enabling SCI0 on PMOD1 */
-#define PMOD_SCI0_EN 0
-
#include "rzg2ul-smarc-som.dtsi"
#include "rzg2ul-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 06/48] arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (4 preceding siblings ...)
2024-02-05 12:40 ` [PATCH 5.10.y-cip 05/48] arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS Lad Prabhakar
@ 2024-02-05 12:40 ` Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 07/48] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property Lad Prabhakar
` (44 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:40 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 53072ba67e534ddd208697d3465004738f1d4d61 upstream.
Move including the rzg2ul-smarc-som.dtsi from the carrier board
rzg2ul-smarc.dtsi to the actual RZ/G2UL SMARC EVK board dts
r9a07g043u11-smarc.dts. Also move the SW_SW0_DEV_SEL and
SW_ET0_EN_N macros to board dts as they are used by SoM and carrier
board DTS/I.
This is in preparation of re-using the SoM and carrier board DTSIs
for RZ/Five SMARC EVK.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220915165256.352843-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 11 +++++++++++
arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 11 -----------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
index d882661c6dde..990cb897083c 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
@@ -10,7 +10,18 @@
/* Please set this macro to 1 for enabling SCI0 on PMOD1 */
#define PMOD_SCI0_EN 0
+/*
+ * DIP-Switch SW1 setting
+ * 1 : High; 0: Low
+ * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
+ * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, SPI1)
+ * Please change below macros according to SW1 setting on the SoM
+ */
+#define SW_SW0_DEV_SEL 1
+#define SW_ET0_EN_N 1
+
#include "r9a07g043.dtsi"
+#include "rzg2ul-smarc-som.dtsi"
#include "rzg2ul-smarc.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
index 44d5c82a9f18..56c0752977d2 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
@@ -5,17 +5,6 @@
* Copyright (C) 2022 Renesas Electronics Corp.
*/
-/*
- * DIP-Switch SW1 setting
- * 1 : High; 0: Low
- * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
- * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
- * Please change below macros according to SW1 setting
- */
-#define SW_SW0_DEV_SEL 1
-#define SW_ET0_EN_N 1
-
-#include "rzg2ul-smarc-som.dtsi"
#include "rzg2ul-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 07/48] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (5 preceding siblings ...)
2024-02-05 12:40 ` [PATCH 5.10.y-cip 06/48] arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into " Lad Prabhakar
@ 2024-02-05 12:40 ` Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 08/48] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels Lad Prabhakar
` (43 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:40 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 49669da644cf000eb79dbede55bd04acf3f2f0a0 upstream.
Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property so
that we can share the common parts of the SoC DTSI with the RZ/Five
(RISC-V) SoC and the RZ/G2UL (ARM64) SoC.
This patch adds a new file r9a07g043u.dtsi to separate out RZ/G2UL
(ARM64) SoC specific parts. No functional changes (same DTB).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221025220629.79321-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 301 +++++++++---------
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 12 +
.../boot/dts/renesas/r9a07g043u11-smarc.dts | 2 +-
3 files changed, 163 insertions(+), 152 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index ba48156febe1..1422760a090b 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -5,7 +5,6 @@
* Copyright (C) 2022 Renesas Electronics Corp.
*/
-#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a07g043-cpg.h>
/ {
@@ -107,10 +106,10 @@ ssi0: ssi@10049c00 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x10049c00 0 0x400>;
- interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(329) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
@@ -128,10 +127,10 @@ ssi1: ssi@1004a000 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a000 0 0x400>;
- interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(333) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
@@ -149,10 +148,10 @@ ssi2: ssi@1004a400 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a400 0 0x400>;
- interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(335) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(336) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
@@ -170,10 +169,10 @@ ssi3: ssi@1004a800 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a800 0 0x400>;
- interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(341) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
@@ -190,9 +189,9 @@ ssi3: ssi@1004a800 {
spi0: spi@1004ac00 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004ac00 0 0x400>;
- interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(415) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(413) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(414) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
resets = <&cpg R9A07G043_RSPI0_RST>;
@@ -208,9 +207,9 @@ spi0: spi@1004ac00 {
spi1: spi@1004b000 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004b000 0 0x400>;
- interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(418) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(416) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(417) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
resets = <&cpg R9A07G043_RSPI1_RST>;
@@ -226,9 +225,9 @@ spi1: spi@1004b000 {
spi2: spi@1004b400 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004b400 0 0x400>;
- interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(421) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(419) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(420) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
resets = <&cpg R9A07G043_RSPI2_RST>;
@@ -245,12 +244,12 @@ scif0: serial@1004b800 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004b800 0 0x400>;
- interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(380) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(382) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(383) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(381) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
@@ -264,12 +263,12 @@ scif1: serial@1004bc00 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004bc00 0 0x400>;
- interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(385) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(387) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(388) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(386) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
@@ -283,12 +282,12 @@ scif2: serial@1004c000 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c000 0 0x400>;
- interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(390) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(392) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(393) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(391) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
@@ -302,12 +301,12 @@ scif3: serial@1004c400 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c400 0 0x400>;
- interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(395) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(397) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(398) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(396) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
@@ -321,12 +320,12 @@ scif4: serial@1004c800 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c800 0 0x400>;
- interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(400) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(402) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(403) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(401) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
@@ -339,10 +338,10 @@ scif4: serial@1004c800 {
sci0: serial@1004d000 {
compatible = "renesas,r9a07g043-sci", "renesas,sci";
reg = <0 0x1004d000 0 0x400>;
- interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(405) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(406) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(407) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(408) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
clock-names = "fck";
@@ -354,10 +353,10 @@ sci0: serial@1004d000 {
sci1: serial@1004d400 {
compatible = "renesas,r9a07g043-sci", "renesas,sci";
reg = <0 0x1004d400 0 0x400>;
- interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(409) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(410) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(411) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(412) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
clock-names = "fck";
@@ -369,14 +368,14 @@ sci1: serial@1004d400 {
canfd: can@10050000 {
compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd";
reg = <0 0x10050000 0 0x8000>;
- interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(426) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(427) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(422) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(424) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(428) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(423) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(425) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(429) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "g_err", "g_recc",
"ch0_err", "ch0_rec", "ch0_trx",
"ch1_err", "ch1_rec", "ch1_trx";
@@ -405,14 +404,14 @@ i2c0: i2c@10058000 {
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058000 0 0x400>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(350) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(348) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(349) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(352) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(353) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(351) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(354) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(355) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>;
@@ -427,14 +426,14 @@ i2c1: i2c@10058400 {
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058400 0 0x400>;
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(358) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(356) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(357) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(360) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(361) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(359) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(362) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(363) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>;
@@ -449,14 +448,14 @@ i2c2: i2c@10058800 {
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058800 0 0x400>;
- interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(366) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(364) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(365) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(368) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(369) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(367) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(370) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(371) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>;
@@ -471,14 +470,14 @@ i2c3: i2c@10058c00 {
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058c00 0 0x400>;
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(374) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(372) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(373) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(376) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(377) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(375) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(378) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(379) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>;
@@ -491,7 +490,7 @@ i2c3: i2c@10058c00 {
adc: adc@10059000 {
compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc";
reg = <0 0x10059000 0 0x400>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(347) IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>,
<&cpg CPG_MOD R9A07G043_ADC_PCLK>;
clock-names = "adclk", "pclk";
@@ -551,10 +550,10 @@ cpg: clock-controller@11010000 {
sysc: system-controller@11020000 {
compatible = "renesas,r9a07g043-sysc";
reg = <0 0x11020000 0 0x10000>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpm_int", "ca55stbydone_int",
"cm33stbyr_int", "ca55_deny";
status = "disabled";
@@ -578,23 +577,23 @@ dmac: dma-controller@11820000 {
"renesas,rz-dmac";
reg = <0 0x11820000 0 0x10000>,
<0 0x11830000 0 0x10000>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(141) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(125) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(126) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(127) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(128) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(129) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(130) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(132) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(133) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(134) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(135) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(136) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(137) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(138) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(139) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(140) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -625,8 +624,8 @@ sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
<&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
<&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
@@ -641,8 +640,8 @@ sdhi1: mmc@11c10000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(107) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
<&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
<&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
@@ -657,9 +656,9 @@ eth0: ethernet@11c20000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c20000 0 0x10000>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(85) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(86) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
@@ -677,9 +676,9 @@ eth1: ethernet@11c30000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c30000 0 0x10000>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(87) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(88) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(89) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
@@ -707,7 +706,7 @@ phyrst: usbphy-ctrl@11c40000 {
ohci0: usb@11c50000 {
compatible = "generic-ohci";
reg = <0 0x11c50000 0 0x100>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>,
@@ -721,7 +720,7 @@ ohci0: usb@11c50000 {
ohci1: usb@11c70000 {
compatible = "generic-ohci";
reg = <0 0x11c70000 0 0x100>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(96) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>,
@@ -735,7 +734,7 @@ ohci1: usb@11c70000 {
ehci0: usb@11c50100 {
compatible = "generic-ehci";
reg = <0 0x11c50100 0 0x100>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>,
@@ -750,7 +749,7 @@ ehci0: usb@11c50100 {
ehci1: usb@11c70100 {
compatible = "generic-ehci";
reg = <0 0x11c70100 0 0x100>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(97) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>,
@@ -766,7 +765,7 @@ usb2_phy0: usb-phy@11c50200 {
compatible = "renesas,usb2-phy-r9a07g043",
"renesas,rzg2l-usb2-phy";
reg = <0 0x11c50200 0 0x700>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(94) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>;
@@ -779,7 +778,7 @@ usb2_phy1: usb-phy@11c70200 {
compatible = "renesas,usb2-phy-r9a07g043",
"renesas,rzg2l-usb2-phy";
reg = <0 0x11c70200 0 0x700>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(99) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>;
@@ -792,10 +791,10 @@ hsusb: usb@11c60000 {
compatible = "renesas,usbhs-r9a07g043",
"renesas,rza2-usbhs";
reg = <0 0x11c60000 0 0x10000>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(100) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(101) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(102) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(103) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>;
resets = <&phyrst 0>,
@@ -814,8 +813,8 @@ wdt0: watchdog@12800800 {
clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>,
<&cpg CPG_MOD R9A07G043_WDT0_CLK>;
clock-names = "pclk", "oscclk";
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(49) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G043_WDT0_PRESETN>;
power-domains = <&cpg>;
@@ -826,7 +825,7 @@ ostm0: timer@12801000 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801000 0x0 0x400>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
power-domains = <&cpg>;
@@ -837,7 +836,7 @@ ostm1: timer@12801400 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801400 0x0 0x400>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
power-domains = <&cpg>;
@@ -848,7 +847,7 @@ ostm2: timer@12801800 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801800 0x0 0x400>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(48) IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
power-domains = <&cpg>;
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
new file mode 100644
index 000000000000..96f935bc2d4d
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2UL SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
+
+#include "r9a07g043.dtsi"
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
index 990cb897083c..bfe0e9f128a3 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
@@ -20,7 +20,7 @@
#define SW_SW0_DEV_SEL 1
#define SW_ET0_EN_N 1
-#include "r9a07g043.dtsi"
+#include "r9a07g043u.dtsi"
#include "rzg2ul-smarc-som.dtsi"
#include "rzg2ul-smarc.dtsi"
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 08/48] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (6 preceding siblings ...)
2024-02-05 12:40 ` [PATCH 5.10.y-cip 07/48] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property Lad Prabhakar
@ 2024-02-05 12:40 ` Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 09/48] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Lad Prabhakar
` (42 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:40 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 2a5c9891392dca47f6865a2add1986876e40849c upstream.
From R01UH0968EJ0100 Rev.1.00 HW manual the interrupt numbers for SSI
channels have been updated,
SPI 329 - SSIF0 is now marked as reserved
SPI 333 - SSIF1 is now marked as reserved
SPI 335 - SSIF2 is now marked as reserved
SPI 336 - SSIF2 is now marked as reserved
SPI 341 - SSIF3 is now marked as reserved
This patch drops the above IRQs from SoC DTSI.
Fixes: 559f2b0708c70 ("arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 stub node")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230217185225.43310-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 1422760a090b..ca937f88406c 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -108,9 +108,8 @@ ssi0: ssi@10049c00 {
reg = <0 0x10049c00 0 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>,
- <SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>,
- <SOC_PERIPHERAL_IRQ(329) IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ <SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -129,9 +128,8 @@ ssi1: ssi@1004a000 {
reg = <0 0x1004a000 0 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>,
- <SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>,
- <SOC_PERIPHERAL_IRQ(333) IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ <SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -149,10 +147,8 @@ ssi2: ssi@1004a400 {
"renesas,rz-ssi";
reg = <0 0x1004a400 0 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>,
- <SOC_PERIPHERAL_IRQ(335) IRQ_TYPE_EDGE_RISING>,
- <SOC_PERIPHERAL_IRQ(336) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ interrupt-names = "int_req", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -171,9 +167,8 @@ ssi3: ssi@1004a800 {
reg = <0 0x1004a800 0 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>,
- <SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>,
- <SOC_PERIPHERAL_IRQ(341) IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ <SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 09/48] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (7 preceding siblings ...)
2024-02-05 12:40 ` [PATCH 5.10.y-cip 08/48] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels Lad Prabhakar
@ 2024-02-05 12:40 ` Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 10/48] cacheinfo: clear cache_leaves(cpu) in free_cache_attributes() Lad Prabhakar
` (41 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:40 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit b9a0be2054964026aa58966ce9724b672f210835 upstream.
Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that
r9a07g043.dtsi can be shared with RZ/Five (RISC-V SoC).
Below are the changes due to which SoC specific parts are moved to
r9a07g043u.dtsi:
- RZ/G2UL has Cortex-A55 (ARM64) whereas RZ/Five has AX45MP (RISC-V),
- RZ/G2UL has GICv3 as interrupt controller whereas RZ/Five has PLIC,
- RZ/G2UL has interrupts for SYSC block whereas interrupts are missing
for SYSC block on RZ/Five,
- RZ/G2UL has armv8-timer whereas RZ/Five has riscv-timer,
- RZ/G2UL has PSCI whereas RZ/Five have OpenSBI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20221025220629.79321-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 54 +------------------
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 60 +++++++++++++++++++++
2 files changed, 61 insertions(+), 53 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index ca937f88406c..5f534db54d1c 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the RZ/G2UL SoC
+ * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
@@ -68,36 +68,8 @@ opp-1000000000 {
};
};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a55";
- reg = <0>;
- device_type = "cpu";
- #cooling-cells = <2>;
- next-level-cache = <&L3_CA55>;
- enable-method = "psci";
- clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- L3_CA55: cache-controller-0 {
- compatible = "cache";
- cache-unified;
- cache-size = <0x40000>;
- };
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
soc: soc {
compatible = "simple-bus";
- interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -545,12 +517,6 @@ cpg: clock-controller@11010000 {
sysc: system-controller@11020000 {
compatible = "renesas,r9a07g043-sysc";
reg = <0 0x11020000 0 0x10000>;
- interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
- <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
- <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
- <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "lpm_int", "ca55stbydone_int",
- "cm33stbyr_int", "ca55_deny";
status = "disabled";
};
@@ -605,16 +571,6 @@ dmac: dma-controller@11820000 {
dma-channels = <16>;
};
- gic: interrupt-controller@11900000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0x11900000 0 0x40000>,
- <0x0 0x11940000 0 0x60000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
- };
-
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
@@ -880,12 +836,4 @@ target: trip-point {
};
};
};
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- };
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index 96f935bc2d4d..b8bf06b51235 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -10,3 +10,63 @@
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
#include "r9a07g043.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ #cooling-cells = <2>;
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x40000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
+
+&soc {
+ interrupt-parent = <&gic>;
+
+ gic: interrupt-controller@11900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x11900000 0 0x40000>,
+ <0x0 0x11940000 0 0x60000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&sysc {
+ interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int",
+ "cm33stbyr_int", "ca55_deny";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 10/48] cacheinfo: clear cache_leaves(cpu) in free_cache_attributes()
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (8 preceding siblings ...)
2024-02-05 12:40 ` [PATCH 5.10.y-cip 09/48] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Lad Prabhakar
@ 2024-02-05 12:40 ` Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 11/48] riscv: Kconfig: Enable cpufreq kconfig menu Lad Prabhakar
` (40 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:40 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Xiongfeng Wang <wangxiongfeng2@huawei.com>
commit e022eac85ecd2140a0829970d923d984356185eb upstream.
On ARM64, when PPTT(Processor Properties Topology Table) is not
implemented in ACPI boot, we will goto 'free_ci' with the following
print:
Unable to detect cache hierarchy for CPU 0
But some other codes may still use 'num_leaves' to iterate through the
'info_list', such as get_cpu_cacheinfo_id(). If 'info_list' is NULL , it
would crash. So clear 'num_leaves' in free_cache_attributes().
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Link: https://lore.kernel.org/r/1626226375-58730-1-git-send-email-wangxiongfeng2@huawei.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/base/cacheinfo.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index bfc095956dd1..dad296229161 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -297,6 +297,7 @@ static void free_cache_attributes(unsigned int cpu)
kfree(per_cpu_cacheinfo(cpu));
per_cpu_cacheinfo(cpu) = NULL;
+ cache_leaves(cpu) = 0;
}
int __weak init_cache_level(unsigned int cpu)
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 11/48] riscv: Kconfig: Enable cpufreq kconfig menu
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (9 preceding siblings ...)
2024-02-05 12:40 ` [PATCH 5.10.y-cip 10/48] cacheinfo: clear cache_leaves(cpu) in free_cache_attributes() Lad Prabhakar
@ 2024-02-05 12:40 ` Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 12/48] dma-direct: add support for dma_coherent_default_memory Lad Prabhakar
` (39 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:40 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit effae0e3d9e1139d583e9b5d050f4f948825b8a3 upstream.
Enable cpufreq kconfig menu for RISC-V.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221115105135.1180490-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
[PL: manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b28fabfc91bf..6cdfb41a9181 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -456,6 +456,8 @@ menu "Power management options"
source "kernel/power/Kconfig"
+source "drivers/cpufreq/Kconfig"
+
endmenu
source "drivers/firmware/Kconfig"
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 12/48] dma-direct: add support for dma_coherent_default_memory
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (10 preceding siblings ...)
2024-02-05 12:40 ` [PATCH 5.10.y-cip 11/48] riscv: Kconfig: Enable cpufreq kconfig menu Lad Prabhakar
@ 2024-02-05 12:40 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 13/48] dma-mapping: allow using the global coherent pool for !ARM Lad Prabhakar
` (38 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:40 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Christoph Hellwig <hch@lst.de>
commit faf4ef823ac5f3b6a34a73b76c52895dee3dce55 upstream.
Add an option to allocate uncached memory for dma_alloc_coherent from
the global dma_coherent_default_memory. This will allow to move
arm-nommu (and eventually other platforms) to use generic code for
allocating uncached memory from a pre-populated pool.
Note that this is a different pool from the one that platforms that
can remap at runtime use for GFP_ATOMIC allocations for now, although
there might be opportunities to eventually end up with a common codebase
for the two use cases.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Tested-by: Dillon Min <dillon.minfei@gmail.com>
[PL: define page_order variable used by dma_release_from_global_coherent()]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
kernel/dma/Kconfig | 4 ++++
kernel/dma/direct.c | 17 +++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/kernel/dma/Kconfig b/kernel/dma/Kconfig
index c99de4a21458..87883d4e1ce3 100644
--- a/kernel/dma/Kconfig
+++ b/kernel/dma/Kconfig
@@ -97,6 +97,10 @@ config DMA_COHERENT_POOL
select GENERIC_ALLOCATOR
bool
+config DMA_GLOBAL_POOL
+ select DMA_DECLARE_COHERENT
+ bool
+
config DMA_REMAP
bool
depends on MMU
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index 2922250f93b4..34ac5a2c7efc 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -156,9 +156,14 @@ void *dma_direct_alloc(struct device *dev, size_t size,
if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
!IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
+ !IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
!dev_is_dma_coherent(dev))
return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
+ if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
+ !dev_is_dma_coherent(dev))
+ return dma_alloc_from_global_coherent(dev, size, dma_handle);
+
/*
* Remapping or decrypting memory may block. If either is required and
* we can't block, allocate the memory from the atomic pools.
@@ -253,11 +258,21 @@ void dma_direct_free(struct device *dev, size_t size,
if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
!IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
+ !IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
!dev_is_dma_coherent(dev)) {
arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
return;
}
+ if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
+ !dev_is_dma_coherent(dev)) {
+ unsigned int page_order = get_order(size);
+
+ if (!dma_release_from_global_coherent(page_order, cpu_addr))
+ WARN_ON_ONCE(1);
+ return;
+ }
+
/* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
@@ -458,6 +473,8 @@ int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
return ret;
+ if (dma_mmap_from_global_coherent(vma, cpu_addr, size, &ret))
+ return ret;
if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
return -ENXIO;
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 13/48] dma-mapping: allow using the global coherent pool for !ARM
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (11 preceding siblings ...)
2024-02-05 12:40 ` [PATCH 5.10.y-cip 12/48] dma-direct: add support for dma_coherent_default_memory Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory Lad Prabhakar
` (37 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Christoph Hellwig <hch@lst.de>
commit 70d6aa0ecfed253a2b14659a6c77359af6d9b3ee upstream.
Switch an ifdef so that the global coherent pool is initialized for
any architecture that selects the DMA_GLOBAL_POOL symbol insted of
hardcoding ARM.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Tested-by: Dillon Min <dillon.minfei@gmail.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
kernel/dma/coherent.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/kernel/dma/coherent.c b/kernel/dma/coherent.c
index 5b5b6c7ec7f2..d97edd70d353 100644
--- a/kernel/dma/coherent.c
+++ b/kernel/dma/coherent.c
@@ -361,7 +361,9 @@ static int __init rmem_dma_setup(struct reserved_mem *rmem)
pr_err("Reserved memory: regions without no-map are not yet supported\n");
return -EINVAL;
}
+#endif
+#ifdef CONFIG_DMA_GLOBAL_POOL
if (of_get_flat_dt_prop(node, "linux,dma-default", NULL)) {
WARN(dma_reserved_default_memory,
"Reserved memory: region for default DMA coherent area is redefined\n");
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (12 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 13/48] dma-mapping: allow using the global coherent pool for !ARM Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-06 9:18 ` nobuhiro1.iwamatsu
2024-02-05 12:41 ` [PATCH 5.10.y-cip 15/48] dma-mapping: add a dma_init_global_coherent helper Lad Prabhakar
` (36 subsequent siblings)
50 siblings, 1 reply; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Christoph Hellwig <hch@lst.de>
commit a6933571f34a9aee843fff2aa4b96949c57d6274 upstream.
Return the allocated dma_coherent_mem structure, set the
use_dma_pfn_offset and print the failure warning inside of
dma_init_coherent_memory instead of leaving that to the callers.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Tested-by: Dillon Min <dillon.minfei@gmail.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
kernel/dma/coherent.c | 78 ++++++++++++++++++-------------------------
1 file changed, 33 insertions(+), 45 deletions(-)
diff --git a/kernel/dma/coherent.c b/kernel/dma/coherent.c
index d97edd70d353..9610ed291f29 100644
--- a/kernel/dma/coherent.c
+++ b/kernel/dma/coherent.c
@@ -37,51 +37,44 @@ static inline dma_addr_t dma_get_device_base(struct device *dev,
return mem->device_base;
}
-static int dma_init_coherent_memory(phys_addr_t phys_addr,
- dma_addr_t device_addr, size_t size,
- struct dma_coherent_mem **mem)
+static struct dma_coherent_mem *dma_init_coherent_memory(phys_addr_t phys_addr,
+ dma_addr_t device_addr, size_t size, bool use_dma_pfn_offset)
{
- struct dma_coherent_mem *dma_mem = NULL;
- void *mem_base = NULL;
+ struct dma_coherent_mem *dma_mem;
int pages = size >> PAGE_SHIFT;
int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
- int ret;
+ void *mem_base;
- if (!size) {
- ret = -EINVAL;
- goto out;
- }
+ if (!size)
+ return ERR_PTR(-EINVAL);
mem_base = memremap(phys_addr, size, MEMREMAP_WC);
- if (!mem_base) {
- ret = -EINVAL;
- goto out;
- }
+ if (!mem_base)
+ return ERR_PTR(-EINVAL);
+
dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
- if (!dma_mem) {
- ret = -ENOMEM;
- goto out;
- }
+ if (!dma_mem)
+ goto out_unmap_membase;
dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
- if (!dma_mem->bitmap) {
- ret = -ENOMEM;
- goto out;
- }
+ if (!dma_mem->bitmap)
+ goto out_free_dma_mem;
dma_mem->virt_base = mem_base;
dma_mem->device_base = device_addr;
dma_mem->pfn_base = PFN_DOWN(phys_addr);
dma_mem->size = pages;
+ dma_mem->use_dev_dma_pfn_offset = use_dma_pfn_offset;
spin_lock_init(&dma_mem->spinlock);
- *mem = dma_mem;
- return 0;
+ return dma_mem;
-out:
+out_free_dma_mem:
kfree(dma_mem);
- if (mem_base)
- memunmap(mem_base);
- return ret;
+out_unmap_membase:
+ memunmap(mem_base);
+ pr_err("Reserved memory: failed to init DMA memory pool at %pa, size %zd MiB\n",
+ &phys_addr, size / SZ_1M);
+ return ERR_PTR(-ENOMEM);
}
static void dma_release_coherent_memory(struct dma_coherent_mem *mem)
@@ -130,9 +123,9 @@ int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
struct dma_coherent_mem *mem;
int ret;
- ret = dma_init_coherent_memory(phys_addr, device_addr, size, &mem);
- if (ret)
- return ret;
+ mem = dma_init_coherent_memory(phys_addr, device_addr, size, false);
+ if (IS_ERR(mem))
+ return PTR_ERR(mem);
ret = dma_assign_coherent_memory(dev, mem);
if (ret)
@@ -319,21 +312,16 @@ static struct reserved_mem *dma_reserved_default_memory __initdata;
static int rmem_dma_device_init(struct reserved_mem *rmem, struct device *dev)
{
- struct dma_coherent_mem *mem = rmem->priv;
- int ret;
-
- if (!mem) {
- ret = dma_init_coherent_memory(rmem->base, rmem->base,
- rmem->size, &mem);
- if (ret) {
- pr_err("Reserved memory: failed to init DMA memory pool at %pa, size %ld MiB\n",
- &rmem->base, (unsigned long)rmem->size / SZ_1M);
- return ret;
- }
+ if (!rmem->priv) {
+ struct dma_coherent_mem *mem;
+
+ mem = dma_init_coherent_memory(rmem->base, rmem->base,
+ rmem->size, true);
+ if (IS_ERR(mem))
+ return PTR_ERR(mem);
+ rmem->priv = mem;
}
- mem->use_dev_dma_pfn_offset = true;
- rmem->priv = mem;
- dma_assign_coherent_memory(dev, mem);
+ dma_assign_coherent_memory(dev, rmem->priv);
return 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 15/48] dma-mapping: add a dma_init_global_coherent helper
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (13 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 16/48] dma-mapping: make the global coherent pool conditional Lad Prabhakar
` (35 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Christoph Hellwig <hch@lst.de>
commit 39a2d3506b2d53c569a6db13d65b2f3728c4feec upstream.
Add a new helper to initialize the global coherent pool. This both
cleans up the existing initialization which indirects through the
reserved_mem_ops that are normally only used for struct device, and
also allows using the global pool for non-devicetree architectures.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Tested-by: Dillon Min <dillon.minfei@gmail.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
include/linux/dma-map-ops.h | 2 +-
kernel/dma/coherent.c | 32 ++++++++++++++------------------
2 files changed, 15 insertions(+), 19 deletions(-)
diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h
index a5f89fc4d6df..ac3c9f2bc975 100644
--- a/include/linux/dma-map-ops.h
+++ b/include/linux/dma-map-ops.h
@@ -176,7 +176,7 @@ void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size,
int dma_release_from_global_coherent(int order, void *vaddr);
int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *cpu_addr,
size_t size, int *ret);
-
+int dma_init_global_coherent(phys_addr_t phys_addr, size_t size);
#else
static inline int dma_declare_coherent_memory(struct device *dev,
phys_addr_t phys_addr, dma_addr_t device_addr, size_t size)
diff --git a/kernel/dma/coherent.c b/kernel/dma/coherent.c
index 9610ed291f29..78a951f6e2c7 100644
--- a/kernel/dma/coherent.c
+++ b/kernel/dma/coherent.c
@@ -300,6 +300,18 @@ int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *vaddr,
vaddr, size, ret);
}
+int dma_init_global_coherent(phys_addr_t phys_addr, size_t size)
+{
+ struct dma_coherent_mem *mem;
+
+ mem = dma_init_coherent_memory(phys_addr, phys_addr, size, true);
+ if (IS_ERR(mem))
+ return PTR_ERR(mem);
+ dma_coherent_default_memory = mem;
+ pr_info("DMA: default coherent area is set\n");
+ return 0;
+}
+
/*
* Support for reserved memory regions defined in device tree
*/
@@ -367,26 +379,10 @@ static int __init rmem_dma_setup(struct reserved_mem *rmem)
static int __init dma_init_reserved_memory(void)
{
- const struct reserved_mem_ops *ops;
- int ret;
-
if (!dma_reserved_default_memory)
return -ENOMEM;
-
- ops = dma_reserved_default_memory->ops;
-
- /*
- * We rely on rmem_dma_device_init() does not propagate error of
- * dma_assign_coherent_memory() for "NULL" device.
- */
- ret = ops->device_init(dma_reserved_default_memory, NULL);
-
- if (!ret) {
- dma_coherent_default_memory = dma_reserved_default_memory->priv;
- pr_info("DMA: default coherent area is set\n");
- }
-
- return ret;
+ return dma_init_global_coherent(dma_reserved_default_memory->base,
+ dma_reserved_default_memory->size);
}
core_initcall(dma_init_reserved_memory);
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 16/48] dma-mapping: make the global coherent pool conditional
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (14 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 15/48] dma-mapping: add a dma_init_global_coherent helper Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 17/48] of: also handle dma-noncoherent in of_dma_is_coherent() Lad Prabhakar
` (34 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Christoph Hellwig <hch@lst.de>
commit 22f9feb49950885cdb6e37513f134d154175e743 upstream.
Only build the code to support the global coherent pool if support for
it is enabled.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Tested-by: Dillon Min <dillon.minfei@gmail.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
include/linux/dma-map-ops.h | 18 ++++++++------
kernel/dma/coherent.c | 49 ++++++++++++++++++++-----------------
2 files changed, 37 insertions(+), 30 deletions(-)
diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h
index ac3c9f2bc975..b8ea283a60e0 100644
--- a/include/linux/dma-map-ops.h
+++ b/include/linux/dma-map-ops.h
@@ -170,13 +170,6 @@ int dma_alloc_from_dev_coherent(struct device *dev, ssize_t size,
int dma_release_from_dev_coherent(struct device *dev, int order, void *vaddr);
int dma_mmap_from_dev_coherent(struct device *dev, struct vm_area_struct *vma,
void *cpu_addr, size_t size, int *ret);
-
-void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size,
- dma_addr_t *dma_handle);
-int dma_release_from_global_coherent(int order, void *vaddr);
-int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *cpu_addr,
- size_t size, int *ret);
-int dma_init_global_coherent(phys_addr_t phys_addr, size_t size);
#else
static inline int dma_declare_coherent_memory(struct device *dev,
phys_addr_t phys_addr, dma_addr_t device_addr, size_t size)
@@ -186,7 +179,16 @@ static inline int dma_declare_coherent_memory(struct device *dev,
#define dma_alloc_from_dev_coherent(dev, size, handle, ret) (0)
#define dma_release_from_dev_coherent(dev, order, vaddr) (0)
#define dma_mmap_from_dev_coherent(dev, vma, vaddr, order, ret) (0)
+#endif /* CONFIG_DMA_DECLARE_COHERENT */
+#ifdef CONFIG_DMA_GLOBAL_POOL
+void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size,
+ dma_addr_t *dma_handle);
+int dma_release_from_global_coherent(int order, void *vaddr);
+int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *cpu_addr,
+ size_t size, int *ret);
+int dma_init_global_coherent(phys_addr_t phys_addr, size_t size);
+#else
static inline void *dma_alloc_from_global_coherent(struct device *dev,
ssize_t size, dma_addr_t *dma_handle)
{
@@ -201,7 +203,7 @@ static inline int dma_mmap_from_global_coherent(struct vm_area_struct *vma,
{
return 0;
}
-#endif /* CONFIG_DMA_DECLARE_COHERENT */
+#endif /* CONFIG_DMA_GLOBAL_POOL */
int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
void *cpu_addr, dma_addr_t dma_addr, size_t size,
diff --git a/kernel/dma/coherent.c b/kernel/dma/coherent.c
index 78a951f6e2c7..6243b4d34087 100644
--- a/kernel/dma/coherent.c
+++ b/kernel/dma/coherent.c
@@ -20,8 +20,6 @@ struct dma_coherent_mem {
bool use_dev_dma_pfn_offset;
};
-static struct dma_coherent_mem *dma_coherent_default_memory __ro_after_init;
-
static inline struct dma_coherent_mem *dev_get_coherent_memory(struct device *dev)
{
if (dev && dev->dma_mem)
@@ -191,16 +189,6 @@ int dma_alloc_from_dev_coherent(struct device *dev, ssize_t size,
return 1;
}
-void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size,
- dma_addr_t *dma_handle)
-{
- if (!dma_coherent_default_memory)
- return NULL;
-
- return __dma_alloc_from_coherent(dev, dma_coherent_default_memory, size,
- dma_handle);
-}
-
static int __dma_release_from_coherent(struct dma_coherent_mem *mem,
int order, void *vaddr)
{
@@ -236,15 +224,6 @@ int dma_release_from_dev_coherent(struct device *dev, int order, void *vaddr)
return __dma_release_from_coherent(mem, order, vaddr);
}
-int dma_release_from_global_coherent(int order, void *vaddr)
-{
- if (!dma_coherent_default_memory)
- return 0;
-
- return __dma_release_from_coherent(dma_coherent_default_memory, order,
- vaddr);
-}
-
static int __dma_mmap_from_coherent(struct dma_coherent_mem *mem,
struct vm_area_struct *vma, void *vaddr, size_t size, int *ret)
{
@@ -290,6 +269,28 @@ int dma_mmap_from_dev_coherent(struct device *dev, struct vm_area_struct *vma,
return __dma_mmap_from_coherent(mem, vma, vaddr, size, ret);
}
+#ifdef CONFIG_DMA_GLOBAL_POOL
+static struct dma_coherent_mem *dma_coherent_default_memory __ro_after_init;
+
+void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size,
+ dma_addr_t *dma_handle)
+{
+ if (!dma_coherent_default_memory)
+ return NULL;
+
+ return __dma_alloc_from_coherent(dev, dma_coherent_default_memory, size,
+ dma_handle);
+}
+
+int dma_release_from_global_coherent(int order, void *vaddr)
+{
+ if (!dma_coherent_default_memory)
+ return 0;
+
+ return __dma_release_from_coherent(dma_coherent_default_memory, order,
+ vaddr);
+}
+
int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *vaddr,
size_t size, int *ret)
{
@@ -311,6 +312,7 @@ int dma_init_global_coherent(phys_addr_t phys_addr, size_t size)
pr_info("DMA: default coherent area is set\n");
return 0;
}
+#endif /* CONFIG_DMA_GLOBAL_POOL */
/*
* Support for reserved memory regions defined in device tree
@@ -320,7 +322,9 @@ int dma_init_global_coherent(phys_addr_t phys_addr, size_t size)
#include <linux/of_fdt.h>
#include <linux/of_reserved_mem.h>
+#ifdef CONFIG_DMA_GLOBAL_POOL
static struct reserved_mem *dma_reserved_default_memory __initdata;
+#endif
static int rmem_dma_device_init(struct reserved_mem *rmem, struct device *dev)
{
@@ -377,6 +381,7 @@ static int __init rmem_dma_setup(struct reserved_mem *rmem)
return 0;
}
+#ifdef CONFIG_DMA_GLOBAL_POOL
static int __init dma_init_reserved_memory(void)
{
if (!dma_reserved_default_memory)
@@ -384,8 +389,8 @@ static int __init dma_init_reserved_memory(void)
return dma_init_global_coherent(dma_reserved_default_memory->base,
dma_reserved_default_memory->size);
}
-
core_initcall(dma_init_reserved_memory);
+#endif /* CONFIG_DMA_GLOBAL_POOL */
RESERVEDMEM_OF_DECLARE(dma, "shared-dma-pool", rmem_dma_setup);
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 17/48] of: also handle dma-noncoherent in of_dma_is_coherent()
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (15 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 16/48] dma-mapping: make the global coherent pool conditional Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 18/48] of/irq: Use interrupts-extended to find parent Lad Prabhakar
` (33 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Heiko Stuebner <heiko@sntech.de>
commit 12b827758f51d4b614a677dd453b0e854e46aa65 upstream.
of_dma_is_coherent() currently expects the architecture to be
non-coherent and some devices being coherent getting marked
as such with the dma-coherent devicetree property.
For PowerPC CONFIG_OF_DMA_DEFAULT_COHERENT was added which currently
makes of_dma_is_coherent() always return true but doesn't handle
the case of the architecture being coherent but some devices not.
So modify the function to also check for dma-noncoherent and
set a suitable default return value. If CONFIG_OF_DMA_DEFAULT_COHERENT
is set the value starts with true and finding dma-noncoherent will
set it to false and without CONFIG_OF_DMA_DEFAULT_COHERENT, the
behaviour is reversed.
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220706231536.2041855-2-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/of/address.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index f686fb5011b8..557a4be01103 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -1081,25 +1081,28 @@ phys_addr_t __init of_dma_get_max_cpu_address(struct device_node *np)
*
* It returns true if "dma-coherent" property was found
* for this device in the DT, or if DMA is coherent by
- * default for OF devices on the current platform.
+ * default for OF devices on the current platform and no
+ * "dma-noncoherent" property was found for this device.
*/
bool of_dma_is_coherent(struct device_node *np)
{
struct device_node *node;
-
- if (IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT))
- return true;
+ bool is_coherent = IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT);
node = of_node_get(np);
while (node) {
if (of_property_read_bool(node, "dma-coherent")) {
- of_node_put(node);
- return true;
+ is_coherent = true;
+ break;
+ }
+ if (of_property_read_bool(node, "dma-noncoherent")) {
+ is_coherent = false;
+ break;
}
node = of_get_next_dma_parent(node);
}
of_node_put(node);
- return false;
+ return is_coherent;
}
EXPORT_SYMBOL_GPL(of_dma_is_coherent);
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 18/48] of/irq: Use interrupts-extended to find parent
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (16 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 17/48] of: also handle dma-noncoherent in of_dma_is_coherent() Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 19/48] irqchip/sifive-plic: Improve naming scheme for per context offsets Lad Prabhakar
` (32 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Samuel Holland <samuel@sholland.org>
commit e91033621d56e055803c4c4ba507fbbb2d145a7f upstream.
The RISC-V PLIC binding uses interrupts-extended to specify its parent
domain(s). That binding does not allow the interrupt-parent property to
appear in the irqchip node. This prevents of_irq_init from properly
detecting the irqchip hierarchy.
If no interrupt-parent property is present in the enclosing bus or root
node, then desc->interrupt_parent will be NULL for both the per-CPU
RISC-V INTC (the actual root domain) and the RISC-V PLIC. Similarly, if
the bus or root node specifies `interrupt-parent = <&plic>`, then
of_irq_init will hit the `desc->interrupt_parent == np` check, and again
all parents will be NULL. So things happen to work today for some boards
due to Makefile ordering.
However, things break when another irqchip ("foo") is stacked on top of
the PLIC. The bus or root node will have `interrupt-parent = <&foo>`,
since that is what all of the other peripherals need. When of_irq_init
runs, it will try to find the PLIC's parent domain. of_irq_find_parent
will fall back to using the interrupt-parent property of the PLIC's
parent node (i.e. the bus or root node), and of_irq_init will see "foo"
as the PLIC's parent domain. But this is wrong, because "foo" is
actually the PLIC's child domain!
So of_irq_init wrongly attempts to init the stacked irqchip before the
PLIC. This fails and breaks booting.
Fix this by using the first node referenced by interrupts-extended as
the parent when that property is present. This allows of_irq_init to see
the relationship between the PLIC and the per-CPU RISC-V INTC, and thus
only the RISC-V INTC is (correctly) considered a root domain.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220412051529.6293-1-samuel@sholland.org
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/of/irq.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index 352e14b007e7..7f84e7649dc5 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -507,9 +507,18 @@ void __init of_irq_init(const struct of_device_id *matches)
desc->irq_init_cb = match->data;
desc->dev = of_node_get(np);
- desc->interrupt_parent = of_irq_find_parent(np);
- if (desc->interrupt_parent == np)
+ /*
+ * interrupts-extended can reference multiple parent domains.
+ * Arbitrarily pick the first one; assume any other parents
+ * are the same distance away from the root irq controller.
+ */
+ desc->interrupt_parent = of_parse_phandle(np, "interrupts-extended", 0);
+ if (!desc->interrupt_parent)
+ desc->interrupt_parent = of_irq_find_parent(np);
+ if (desc->interrupt_parent == np) {
+ of_node_put(desc->interrupt_parent);
desc->interrupt_parent = NULL;
+ }
list_add_tail(&desc->list, &intc_desc_list);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 19/48] irqchip/sifive-plic: Improve naming scheme for per context offsets
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (17 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 18/48] of/irq: Use interrupts-extended to find parent Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 20/48] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode Lad Prabhakar
` (31 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Niklas Cassel <niklas.cassel@wdc.com>
commit 0d3616bbd03cdfaa8a5fdf38e0fec2b1ef6ec0a0 upstream.
The PLIC supports a fixed number of contexts (15872).
Each context has fixed register offsets in PLIC.
The number of contexts that we need to initialize depends on the privilege
modes supported by each hart. Therefore, this mapping between PLIC context
registers to hart privilege modes is platform specific, and is currently
supplied via device tree.
For example, canaan,k210 has the following mapping:
Context0: hart0 M-mode
Context1: hart0 S-mode
Context2: hart1 M-mode
Context3: hart1 S-mode
While sifive,fu540 has the following mapping:
Context0: hart0 M-mode
Context1: hart1 M-mode
Context2: hart1 S-mode
Because the number of contexts per hart is not fixed, the names
ENABLE_PER_HART and CONTEXT_PER_HART for the register offsets are quite
confusing and might mislead the reader to think that these are fixed
register offsets per hart.
Rename the offsets to more clearly highlight that these are per PLIC
context and not per hart.
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220302131544.3166154-2-Niklas.Cassel@wdc.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/irqchip/irq-sifive-plic.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index bd99ee0ae433..5b25e275fa6f 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -44,8 +44,8 @@
* Each hart context has a vector of interrupt enable bits associated with it.
* There's one bit for each interrupt source.
*/
-#define ENABLE_BASE 0x2000
-#define ENABLE_PER_HART 0x80
+#define CONTEXT_ENABLE_BASE 0x2000
+#define CONTEXT_ENABLE_SIZE 0x80
/*
* Each hart context has a set of control registers associated with it. Right
@@ -53,7 +53,7 @@
* take an interrupt, and a register to claim interrupts.
*/
#define CONTEXT_BASE 0x200000
-#define CONTEXT_PER_HART 0x1000
+#define CONTEXT_SIZE 0x1000
#define CONTEXT_THRESHOLD 0x00
#define CONTEXT_CLAIM 0x04
@@ -363,11 +363,11 @@ static int __init plic_init(struct device_node *node,
cpumask_set_cpu(cpu, &priv->lmask);
handler->present = true;
- handler->hart_base =
- priv->regs + CONTEXT_BASE + i * CONTEXT_PER_HART;
+ handler->hart_base = priv->regs + CONTEXT_BASE +
+ i * CONTEXT_SIZE;
raw_spin_lock_init(&handler->enable_lock);
- handler->enable_base =
- priv->regs + ENABLE_BASE + i * ENABLE_PER_HART;
+ handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE +
+ i * CONTEXT_ENABLE_SIZE;
handler->priv = priv;
done:
for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 20/48] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (18 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 19/48] irqchip/sifive-plic: Improve naming scheme for per context offsets Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 21/48] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC Lad Prabhakar
` (30 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Niklas Cassel <niklas.cassel@wdc.com>
commit 098fdbc3531f06aae2426b3a6f9bd730e7691258 upstream.
When detecting a context for a privilege mode different from the current
running privilege mode, we simply skip to the next context register.
This means that we never clear the S-mode enable bits when running in
M-mode.
On canaan k210, a bunch of S-mode interrupts are enabled by the bootrom.
These S-mode specific interrupts should never trigger, since we never set
the mie.SEIE bit in the parent interrupt controller (riscv-intc).
However, we will be able to see the mip.SEIE bit set as pending.
This isn't a good default when CONFIG_RISCV_M_MODE is set, since in that
case we will never enter a lower privilege mode (e.g. S-mode).
Let's clear the S-mode enable bits when running the kernel in M-mode, such
that we won't have a interrupt pending bit set, which we will never clear.
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220302131544.3166154-3-Niklas.Cassel@wdc.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/irqchip/irq-sifive-plic.c | 24 +++++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 5b25e275fa6f..3a8a795000bf 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -81,17 +81,21 @@ static int plic_parent_irq;
static bool plic_cpuhp_setup_done;
static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
-static inline void plic_toggle(struct plic_handler *handler,
- int hwirq, int enable)
+static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
{
- u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32);
+ u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
u32 hwirq_mask = 1 << (hwirq % 32);
- raw_spin_lock(&handler->enable_lock);
if (enable)
writel(readl(reg) | hwirq_mask, reg);
else
writel(readl(reg) & ~hwirq_mask, reg);
+}
+
+static void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
+{
+ raw_spin_lock(&handler->enable_lock);
+ __plic_toggle(handler->enable_base, hwirq, enable);
raw_spin_unlock(&handler->enable_lock);
}
@@ -326,8 +330,18 @@ static int __init plic_init(struct device_node *node,
* Skip contexts other than external interrupts for our
* privilege level.
*/
- if (parent.args[0] != RV_IRQ_EXT)
+ if (parent.args[0] != RV_IRQ_EXT) {
+ /* Disable S-mode enable bits if running in M-mode. */
+ if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
+ void __iomem *enable_base = priv->regs +
+ CONTEXT_ENABLE_BASE +
+ i * CONTEXT_ENABLE_SIZE;
+
+ for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
+ __plic_toggle(enable_base, hwirq, 0);
+ }
continue;
+ }
hartid = riscv_of_parent_hartid(parent.np);
if (hartid < 0) {
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 21/48] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (19 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 20/48] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 22/48] irqchip/sifive-plic: Make better use of the effective affinity mask Lad Prabhakar
` (29 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit dd46337ca69662b6912bc230d393c4261d126b8f upstream.
The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
edge until the previous completion message has been received and
NCEPLIC100 doesn't support pending interrupt counter, hence losing the
interrupts if not acknowledged in time.
So the workaround for edge-triggered interrupts to be handled correctly
and without losing is that it needs to be acknowledged first and then
handler must be run so that we don't miss on the next edge-triggered
interrupt.
This patch adds a new compatible string for NCEPLIC100 (from Andes
Technology) interrupt controller found on Renesas RZ/Five SoC and adds
quirk bits to priv structure and implements PLIC_QUIRK_EDGE_INTERRUPT
quirk to change the interrupt flow.
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220630100241.35233-3-samuel@sholland.org
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/irqchip/irq-sifive-plic.c | 78 +++++++++++++++++++++++++++++--
1 file changed, 74 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 3a8a795000bf..c42d90543a01 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -60,10 +60,13 @@
#define PLIC_DISABLE_THRESHOLD 0x7
#define PLIC_ENABLE_THRESHOLD 0
+#define PLIC_QUIRK_EDGE_INTERRUPT 0
+
struct plic_priv {
struct cpumask lmask;
struct irq_domain *irqdomain;
void __iomem *regs;
+ unsigned long plic_quirks;
};
struct plic_handler {
@@ -81,6 +84,8 @@ static int plic_parent_irq;
static bool plic_cpuhp_setup_done;
static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
+static int plic_irq_set_type(struct irq_data *d, unsigned int type);
+
static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
{
u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
@@ -176,6 +181,17 @@ static void plic_irq_eoi(struct irq_data *d)
}
}
+static struct irq_chip plic_edge_chip = {
+ .name = "SiFive PLIC",
+ .irq_ack = plic_irq_eoi,
+ .irq_mask = plic_irq_mask,
+ .irq_unmask = plic_irq_unmask,
+#ifdef CONFIG_SMP
+ .irq_set_affinity = plic_set_affinity,
+#endif
+ .irq_set_type = plic_irq_set_type,
+};
+
static struct irq_chip plic_chip = {
.name = "SiFive PLIC",
.irq_mask = plic_irq_mask,
@@ -184,8 +200,32 @@ static struct irq_chip plic_chip = {
#ifdef CONFIG_SMP
.irq_set_affinity = plic_set_affinity,
#endif
+ .irq_set_type = plic_irq_set_type,
};
+static int plic_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ struct plic_priv *priv = irq_data_get_irq_chip_data(d);
+
+ if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
+ return IRQ_SET_MASK_OK_NOCOPY;
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ irq_set_chip_handler_name_locked(d, &plic_edge_chip,
+ handle_edge_irq, NULL);
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ irq_set_chip_handler_name_locked(d, &plic_chip,
+ handle_fasteoi_irq, NULL);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return IRQ_SET_MASK_OK;
+}
+
static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
@@ -198,6 +238,19 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
return 0;
}
+static int plic_irq_domain_translate(struct irq_domain *d,
+ struct irq_fwspec *fwspec,
+ unsigned long *hwirq,
+ unsigned int *type)
+{
+ struct plic_priv *priv = d->host_data;
+
+ if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
+ return irq_domain_translate_twocell(d, fwspec, hwirq, type);
+
+ return irq_domain_translate_onecell(d, fwspec, hwirq, type);
+}
+
static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
@@ -206,7 +259,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int type;
struct irq_fwspec *fwspec = arg;
- ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
+ ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
if (ret)
return ret;
@@ -220,7 +273,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
}
static const struct irq_domain_ops plic_irqdomain_ops = {
- .translate = irq_domain_translate_onecell,
+ .translate = plic_irq_domain_translate,
.alloc = plic_irq_domain_alloc,
.free = irq_domain_free_irqs_top,
};
@@ -283,8 +336,9 @@ static int plic_starting_cpu(unsigned int cpu)
return 0;
}
-static int __init plic_init(struct device_node *node,
- struct device_node *parent)
+static int __init __plic_init(struct device_node *node,
+ struct device_node *parent,
+ unsigned long plic_quirks)
{
int error = 0, nr_contexts, nr_handlers = 0, i;
u32 nr_irqs;
@@ -295,6 +349,8 @@ static int __init plic_init(struct device_node *node,
if (!priv)
return -ENOMEM;
+ priv->plic_quirks = plic_quirks;
+
priv->regs = of_iomap(node, 0);
if (WARN_ON(!priv->regs)) {
error = -EIO;
@@ -412,6 +468,20 @@ static int __init plic_init(struct device_node *node,
return error;
}
+static int __init plic_init(struct device_node *node,
+ struct device_node *parent)
+{
+ return __plic_init(node, parent, 0);
+}
+
IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */
+
+static int __init plic_edge_init(struct device_node *node,
+ struct device_node *parent)
+{
+ return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT));
+}
+
+IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init);
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 22/48] irqchip/sifive-plic: Make better use of the effective affinity mask
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (20 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 21/48] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 23/48] irqchip/sifive-plic: Separate the enable and mask operations Lad Prabhakar
` (28 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Samuel Holland <samuel@sholland.org>
commit de078949218242d57f791b63fac87cdb09cb0424 upstream.
The PLIC driver already updates the effective affinity mask in its
.irq_set_affinity callback. Take advantage of that information to only
touch bits (and take spinlocks) for the specific relevant hart contexts.
First, make sure the effective affinity mask is set before IRQ startup.
Then, since this mask already takes priv->lmask into account, checking
that mask later is no longer needed (and handler->present is equivalent
to the bit being set in priv->lmask).
Finally, when (un)masking or changing affinity, only clear/set the
enable bits in the specific old/new context(s). The cpumask operations
in plic_irq_unmask() are not needed because they duplicate the code in
plic_set_affinity().
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220701202440.59059-2-samuel@sholland.org
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/irqchip/Kconfig | 1 +
drivers/irqchip/irq-sifive-plic.c | 27 +++++++++------------------
2 files changed, 10 insertions(+), 18 deletions(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3c24bf45263c..63c65deb6737 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -529,6 +529,7 @@ config SIFIVE_PLIC
bool "SiFive Platform-Level Interrupt Controller"
depends on RISCV
select IRQ_DOMAIN_HIERARCHY
+ select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
help
This enables support for the PLIC chip found in SiFive (and
potentially other) RISC-V systems. The PLIC controls devices
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index c42d90543a01..364023c776d4 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -114,31 +114,18 @@ static inline void plic_irq_toggle(const struct cpumask *mask,
for_each_cpu(cpu, mask) {
struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
- if (handler->present &&
- cpumask_test_cpu(cpu, &handler->priv->lmask))
- plic_toggle(handler, d->hwirq, enable);
+ plic_toggle(handler, d->hwirq, enable);
}
}
static void plic_irq_unmask(struct irq_data *d)
{
- struct cpumask amask;
- unsigned int cpu;
- struct plic_priv *priv = irq_data_get_irq_chip_data(d);
-
- cpumask_and(&amask, &priv->lmask, cpu_online_mask);
- cpu = cpumask_any_and(irq_data_get_affinity_mask(d),
- &amask);
- if (WARN_ON_ONCE(cpu >= nr_cpu_ids))
- return;
- plic_irq_toggle(cpumask_of(cpu), d, 1);
+ plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1);
}
static void plic_irq_mask(struct irq_data *d)
{
- struct plic_priv *priv = irq_data_get_irq_chip_data(d);
-
- plic_irq_toggle(&priv->lmask, d, 0);
+ plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0);
}
#ifdef CONFIG_SMP
@@ -159,11 +146,13 @@ static int plic_set_affinity(struct irq_data *d,
if (cpu >= nr_cpu_ids)
return -EINVAL;
- plic_irq_toggle(&priv->lmask, d, 0);
- plic_irq_toggle(cpumask_of(cpu), d, !irqd_irq_masked(d));
+ plic_irq_mask(d);
irq_data_update_effective_affinity(d, cpumask_of(cpu));
+ if (!irqd_irq_masked(d))
+ plic_irq_unmask(d);
+
return IRQ_SET_MASK_OK_DONE;
}
#endif
@@ -190,6 +179,7 @@ static struct irq_chip plic_edge_chip = {
.irq_set_affinity = plic_set_affinity,
#endif
.irq_set_type = plic_irq_set_type,
+ .flags = IRQCHIP_AFFINITY_PRE_STARTUP,
};
static struct irq_chip plic_chip = {
@@ -201,6 +191,7 @@ static struct irq_chip plic_chip = {
.irq_set_affinity = plic_set_affinity,
#endif
.irq_set_type = plic_irq_set_type,
+ .flags = IRQCHIP_AFFINITY_PRE_STARTUP,
};
static int plic_irq_set_type(struct irq_data *d, unsigned int type)
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 23/48] irqchip/sifive-plic: Separate the enable and mask operations
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (21 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 22/48] irqchip/sifive-plic: Make better use of the effective affinity mask Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 24/48] clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC Lad Prabhakar
` (27 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Samuel Holland <samuel@sholland.org>
commit a1706a1c5062e0908528170f853601ed53f428c8 upstream.
The PLIC has two per-IRQ checks before sending an IRQ to a hart context.
First, it checks that the IRQ's priority is nonzero. Then, it checks
that the enable bit is set for that combination of IRQ and context.
Currently, the PLIC driver sets both the priority value and the enable
bit in its (un)mask operations. However, modifying the enable bit is
problematic for two reasons:
1) The enable bits are packed, so changes are not atomic and require
taking a spinlock.
2) The following requirement from the PLIC spec, which explains the
racy (un)mask operations in plic_irq_eoi():
If the completion ID does not match an interrupt source
that is currently enabled for the target, the completion
is silently ignored.
Both of these problems are solved by using the priority value to mask
IRQs. Each IRQ has a separate priority register, so writing the priority
value is atomic. And since the enable bit remains set while an IRQ is
masked, the EOI operation works normally. The enable bits are still used
to control the IRQ's affinity.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220701202440.59059-3-samuel@sholland.org
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/irqchip/irq-sifive-plic.c | 55 +++++++++++++++++++------------
1 file changed, 34 insertions(+), 21 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 364023c776d4..2673f726f85d 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -108,9 +108,7 @@ static inline void plic_irq_toggle(const struct cpumask *mask,
struct irq_data *d, int enable)
{
int cpu;
- struct plic_priv *priv = irq_data_get_irq_chip_data(d);
- writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
for_each_cpu(cpu, mask) {
struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
@@ -118,16 +116,37 @@ static inline void plic_irq_toggle(const struct cpumask *mask,
}
}
-static void plic_irq_unmask(struct irq_data *d)
+static void plic_irq_enable(struct irq_data *d)
{
plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1);
}
-static void plic_irq_mask(struct irq_data *d)
+static void plic_irq_disable(struct irq_data *d)
{
plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0);
}
+static void plic_irq_unmask(struct irq_data *d)
+{
+ struct plic_priv *priv = irq_data_get_irq_chip_data(d);
+
+ writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
+}
+
+static void plic_irq_mask(struct irq_data *d)
+{
+ struct plic_priv *priv = irq_data_get_irq_chip_data(d);
+
+ writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
+}
+
+static void plic_irq_eoi(struct irq_data *d)
+{
+ struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
+
+ writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
+}
+
#ifdef CONFIG_SMP
static int plic_set_affinity(struct irq_data *d,
const struct cpumask *mask_val, bool force)
@@ -146,32 +165,21 @@ static int plic_set_affinity(struct irq_data *d,
if (cpu >= nr_cpu_ids)
return -EINVAL;
- plic_irq_mask(d);
+ plic_irq_disable(d);
irq_data_update_effective_affinity(d, cpumask_of(cpu));
- if (!irqd_irq_masked(d))
- plic_irq_unmask(d);
+ if (!irqd_irq_disabled(d))
+ plic_irq_enable(d);
return IRQ_SET_MASK_OK_DONE;
}
#endif
-static void plic_irq_eoi(struct irq_data *d)
-{
- struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
-
- if (irqd_irq_masked(d)) {
- plic_irq_unmask(d);
- writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
- plic_irq_mask(d);
- } else {
- writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
- }
-}
-
static struct irq_chip plic_edge_chip = {
.name = "SiFive PLIC",
+ .irq_enable = plic_irq_enable,
+ .irq_disable = plic_irq_disable,
.irq_ack = plic_irq_eoi,
.irq_mask = plic_irq_mask,
.irq_unmask = plic_irq_unmask,
@@ -184,6 +192,8 @@ static struct irq_chip plic_edge_chip = {
static struct irq_chip plic_chip = {
.name = "SiFive PLIC",
+ .irq_enable = plic_irq_enable,
+ .irq_disable = plic_irq_disable,
.irq_mask = plic_irq_mask,
.irq_unmask = plic_irq_unmask,
.irq_eoi = plic_irq_eoi,
@@ -431,8 +441,11 @@ static int __init __plic_init(struct device_node *node,
i * CONTEXT_ENABLE_SIZE;
handler->priv = priv;
done:
- for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
+ for (hwirq = 1; hwirq <= nr_irqs; hwirq++) {
plic_toggle(handler, hwirq, 0);
+ writel(1, priv->regs + PRIORITY_BASE +
+ hwirq * PRIORITY_PER_ID);
+ }
nr_handlers++;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 24/48] clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (22 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 23/48] irqchip/sifive-plic: Separate the enable and mask operations Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 25/48] clocksource/drivers/riscv: Increase the clock source rating Lad Prabhakar
` (26 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit eaa1a955094b20ca4b1c5064200d140b27f8d96f upstream.
The OSTM block is identical on Renesas RZ/G2L and RZ/V2L SoC's, so instead
of adding dependency for each SoC's add dependency on ARCH_RZG2L. The
ARCH_RZG2L config option is already selected by ARCH_R9A07G044 and
ARCH_R9A07G054.
With the above change OSTM will be enabled on RZ/V2L SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220907080056.3460-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clocksource/renesas-ostm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/renesas-ostm.c b/drivers/clocksource/renesas-ostm.c
index 21d1392637b8..8da972dc1713 100644
--- a/drivers/clocksource/renesas-ostm.c
+++ b/drivers/clocksource/renesas-ostm.c
@@ -224,7 +224,7 @@ static int __init ostm_init(struct device_node *np)
TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init);
-#ifdef CONFIG_ARCH_R9A07G044
+#ifdef CONFIG_ARCH_RZG2L
static int __init ostm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 25/48] clocksource/drivers/riscv: Increase the clock source rating
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (23 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 24/48] clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 26/48] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback Lad Prabhakar
` (25 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Samuel Holland <samuel@sholland.org>
commit 674402b0098b66b8ba91fe93c0d27af703256098 upstream.
RISC-V provides an architectural clock source via the time CSR. This
clock source exposes a 64-bit counter synchronized across all CPUs.
Because it is accessed using a CSR, it is much more efficient to read
than MMIO clock sources. For example, on the Allwinner D1, reading the
sun4i timer in a loop takes 131 cycles/iteration, while reading the
RISC-V time CSR takes only 5 cycles/iteration.
Adjust the RISC-V clock source rating so it is preferred over the
various platform-specific MMIO clock sources.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20221228004444.61568-1-samuel@sholland.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clocksource/timer-riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index c51c5ed15aa7..a035bdf6fc58 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -54,7 +54,7 @@ static u64 notrace riscv_sched_clock(void)
static struct clocksource riscv_clocksource = {
.name = "riscv_clocksource",
- .rating = 300,
+ .rating = 400,
.mask = CLOCKSOURCE_MASK(64),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
.read = riscv_clocksource_rdtime,
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 26/48] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (24 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 25/48] clocksource/drivers/riscv: Increase the clock source rating Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 27/48] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_RENESAS Lad Prabhakar
` (24 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 3aff0403f814df6ce2377a6ecf61dd7750a3925f upstream.
Having a clocksource_arch_init() callback always sets vdso_clock_mode to
VDSO_CLOCKMODE_ARCHTIMER if GENERIC_GETTIMEOFDAY is enabled, this is
required for the riscv-timer.
This works for platforms where just riscv-timer clocksource is present.
On platforms where other clock sources are available we want them to
register with vdso_clock_mode set to VDSO_CLOCKMODE_NONE.
On the Renesas RZ/Five SoC OSTM block can be used as clocksource [0], to
avoid multiple clock sources being registered as VDSO_CLOCKMODE_ARCHTIMER
move setting of vdso_clock_mode in the riscv-timer driver instead of doing
this in clocksource_arch_init() callback as done similarly for ARM/64
architecture.
[0] drivers/clocksource/renesas-ostm.c
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20221229224601.103851-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/Kconfig | 1 -
arch/riscv/kernel/time.c | 9 ---------
drivers/clocksource/timer-riscv.c | 5 +++++
3 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6cdfb41a9181..6b28e663fbed 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -12,7 +12,6 @@ config 32BIT
config RISCV
def_bool y
- select ARCH_CLOCKSOURCE_INIT
select ARCH_SUPPORTS_ATOMIC_RMW
select ARCH_HAS_BINFMT_FLAT
select ARCH_HAS_DEBUG_VM_PGTABLE
diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c
index 303ae47dfb4d..726860a490f3 100644
--- a/arch/riscv/kernel/time.c
+++ b/arch/riscv/kernel/time.c
@@ -32,12 +32,3 @@ void __init time_init(void)
tick_setup_hrtimer_broadcast();
}
-
-void clocksource_arch_init(struct clocksource *cs)
-{
-#ifdef CONFIG_GENERIC_GETTIMEOFDAY
- cs->vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER;
-#else
- cs->vdso_clock_mode = VDSO_CLOCKMODE_NONE;
-#endif
-}
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index a035bdf6fc58..a8210493cc21 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -58,6 +58,11 @@ static struct clocksource riscv_clocksource = {
.mask = CLOCKSOURCE_MASK(64),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
.read = riscv_clocksource_rdtime,
+#if IS_ENABLED(CONFIG_GENERIC_GETTIMEOFDAY)
+ .vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER,
+#else
+ .vdso_clock_mode = VDSO_CLOCKMODE_NONE,
+#endif
};
static int riscv_timer_starting_cpu(unsigned int cpu)
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 27/48] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_RENESAS
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (25 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 26/48] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 28/48] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
` (23 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit bbe6dc429bf52b0062c2a9b39f850cfd317289a7 upstream.
MMC_SDHI_INTERNAL_DMAC config option has dependency on ARM64 and
R7S9210/R8A77470 this dependency will keep growing for future SoCs for
varying architectures. So to simplify this configuration make
MMC_SDHI_INTERNAL_DMAC solely depend on ARCH_RENESAS, as all Renesas
SoCs inherently depend on the ARCH_RENESAS config option.
This allows selecting MMC_SDHI_INTERNAL_DMAC config option for RZ/Five SoC
which is based on RISC-V architecture.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20230901122701.318082-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/mmc/host/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6844d2880ba3..5ce9efe93d65 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -728,9 +728,9 @@ config MMC_SDHI_SYS_DMAC
config MMC_SDHI_INTERNAL_DMAC
tristate "DMA for SDHI SD/SDIO controllers using on-chip bus mastering"
- depends on ARM64 || ARCH_R7S9210 || ARCH_R8A77470 || COMPILE_TEST
+ depends on ARCH_RENESAS || COMPILE_TEST
depends on MMC_SDHI
- default MMC_SDHI if (ARM64 || ARCH_R7S9210 || ARCH_R8A77470)
+ default MMC_SDHI if ARCH_RENESAS
help
This provides DMA support for SDHI SD/SDIO controllers
using on-chip bus mastering. This supports the controllers
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 28/48] dt-bindings: riscv: Sort the CPU core list alphabetically
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (26 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 27/48] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_RENESAS Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 29/48] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
` (22 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 57e1b873c2f54253f4c81bddb782e183ee6544ae upstream.
Sort the CPU cores list alphabetically for maintenance.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221028165921.94487-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: dropped unsupported SoCs]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6925e0b16e4..cd218c8e2104 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,12 +27,12 @@ properties:
oneOf:
- items:
- enum:
- - sifive,rocket0
- sifive,e5
- sifive,e51
- - sifive,u54-mc
- - sifive,u54
+ - sifive,rocket0
- sifive,u5
+ - sifive,u54
+ - sifive,u54-mc
- const: riscv
- const: riscv # Simulator only
description:
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 29/48] dt-bindings: riscv: Add Andes AX45MP core to the list
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (27 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 28/48] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 30/48] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions Lad Prabhakar
` (21 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 9f643dc28e2c072d7d323898530ee37433e74595 upstream.
The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. In preparation to add support for RZ/Five SoC add
the Andes AX45MP core to the list.
More details about Andes AX45MP core can be found here:
[0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221028165921.94487-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index cd218c8e2104..eed1af09a610 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,6 +27,7 @@ properties:
oneOf:
- items:
- enum:
+ - andestech,ax45mp
- sifive,e5
- sifive,e51
- sifive,rocket0
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 30/48] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (28 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 29/48] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 31/48] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller Lad Prabhakar
` (20 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 668d361c9d893be3cbd4f3650e1934a62b204def upstream.
Renesas RZ/Five SoC has almost the same clock structure compared to the
Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just
amend the RZ/Five CPG clock and reset definitions.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220622181723.13033-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
include/dt-bindings/clock/r9a07g043-cpg.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h
index 27e232733096..77cde8effdc7 100644
--- a/include/dt-bindings/clock/r9a07g043-cpg.h
+++ b/include/dt-bindings/clock/r9a07g043-cpg.h
@@ -108,6 +108,15 @@
#define R9A07G043_ADC_ADCLK 76
#define R9A07G043_ADC_PCLK 77
#define R9A07G043_TSU_PCLK 78
+#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */
+#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */
+#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */
+#define R9A07G043_NCEPLMT_ACLK 82 /* RZ/Five Only */
+#define R9A07G043_NCEPLIC_ACLK 83 /* RZ/Five Only */
+#define R9A07G043_AX45MP_CORE0_CLK 84 /* RZ/Five Only */
+#define R9A07G043_AX45MP_ACLK 85 /* RZ/Five Only */
+#define R9A07G043_IAX45_CLK 86 /* RZ/Five Only */
+#define R9A07G043_IAX45_PCLK 87 /* RZ/Five Only */
/* R9A07G043 Resets */
#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */
@@ -180,5 +189,16 @@
#define R9A07G043_ADC_PRESETN 67
#define R9A07G043_ADC_ADRST_N 68
#define R9A07G043_TSU_PRESETN 69
+#define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70 /* RZ/Five Only */
+#define R9A07G043_NCEPLDM_ARESETN 71 /* RZ/Five Only */
+#define R9A07G043_NCEPLMT_POR_RSTN 72 /* RZ/Five Only */
+#define R9A07G043_NCEPLMT_ARESETN 73 /* RZ/Five Only */
+#define R9A07G043_NCEPLIC_ARESETN 74 /* RZ/Five Only */
+#define R9A07G043_AX45MP_ARESETNM 75 /* RZ/Five Only */
+#define R9A07G043_AX45MP_ARESETNS 76 /* RZ/Five Only */
+#define R9A07G043_AX45MP_L2_RESETN 77 /* RZ/Five Only */
+#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
+#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
+
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 31/48] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (29 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 30/48] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 32/48] soc: renesas: Identify RZ/Five SoC Lad Prabhakar
` (19 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 3e7bf4685e42786dc10a57512c8a767947f25c10 upstream.
Add DT binding documentation for L2 cache controller found on RZ/Five SoC.
The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. The AX45MP core has an L2 cache controller, this patch
describes the L2 cache block.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
Link: https://lore.kernel.org/r/20230818135723.80612-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../cache/andestech,ax45mp-cache.yaml | 81 +++++++++++++++++++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
new file mode 100644
index 000000000000..9ab5f0c435d4
--- /dev/null
+++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2023 Renesas Electronics Corp.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andestech AX45MP L2 Cache Controller
+
+maintainers:
+ - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+
+description:
+ A level-2 cache (L2C) is used to improve the system performance by providing
+ a large amount of cache line entries and reasonable access delays. The L2C
+ is shared between cores, and a non-inclusive non-exclusive policy is used.
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - andestech,ax45mp-cache
+
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: andestech,ax45mp-cache
+ - const: cache
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ cache-line-size:
+ const: 64
+
+ cache-level:
+ const: 2
+
+ cache-sets:
+ const: 1024
+
+ cache-size:
+ enum: [131072, 262144, 524288, 1048576, 2097152]
+
+ cache-unified: true
+
+ next-level-cache: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - cache-line-size
+ - cache-level
+ - cache-sets
+ - cache-size
+ - cache-unified
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ cache-controller@2010000 {
+ compatible = "andestech,ax45mp-cache", "cache";
+ reg = <0x13400000 0x100000>;
+ interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
+ cache-line-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <262144>;
+ cache-unified;
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 32/48] soc: renesas: Identify RZ/Five SoC
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (30 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 31/48] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 33/48] clk: renesas: r9a07g043: Add support for " Lad Prabhakar
` (18 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit ebd0e06f3063cc2e3a689112904b29720579c6d2 upstream.
Add support for identifying the (R9A07G043) RZ/Five SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220722141506.20171-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: manually applied changes for Kconfig]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/soc/renesas/Kconfig | 10 ++++++++++
drivers/soc/renesas/renesas-soc.c | 13 +++++++++++++
2 files changed, 23 insertions(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index dcc0d2ae1b2c..69f123f1b5f9 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -315,6 +315,16 @@ endif # ARM64
config PWC_RZV2M
bool "Renesas RZ/V2M PWC support" if COMPILE_TEST
+if RISCV
+
+config ARCH_R9A07G043
+ bool "RISC-V Platform support for RZ/Five"
+ select ARCH_RZG2L
+ help
+ This enables support for the Renesas RZ/Five SoC.
+
+endif # RISCV
+
config RST_RCAR
bool "Reset Controller support for R-Car" if COMPILE_TEST
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index aa5e1b9c4da8..92584f5ab967 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -46,6 +46,10 @@ static const struct renesas_family fam_rza2 __initconst __maybe_unused = {
.name = "RZ/A2",
};
+static const struct renesas_family fam_rzfive __initconst __maybe_unused = {
+ .name = "RZ/Five",
+};
+
static const struct renesas_family fam_rzg1 __initconst __maybe_unused = {
.name = "RZ/G1",
.reg = 0xff000044, /* PRR (Product Register) */
@@ -102,6 +106,11 @@ static const struct renesas_soc soc_rmobile_a1 __initconst __maybe_unused = {
.id = 0x40,
};
+static const struct renesas_soc soc_rz_five __initconst __maybe_unused = {
+ .family = &fam_rzfive,
+ .id = 0x847c447,
+};
+
static const struct renesas_soc soc_rz_g1h __initconst __maybe_unused = {
.family = &fam_rzg1,
.id = 0x45,
@@ -335,8 +344,12 @@ static const struct of_device_id renesas_socs[] __initconst = {
{ .compatible = "renesas,r8a779a0", .data = &soc_rcar_v3u },
#endif
#if defined(CONFIG_ARCH_R9A07G043)
+#ifdef CONFIG_RISCV
+ { .compatible = "renesas,r9a07g043", .data = &soc_rz_five },
+#else
{ .compatible = "renesas,r9a07g043", .data = &soc_rz_g2ul },
#endif
+#endif
#if defined(CONFIG_ARCH_R9A07G044)
{ .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l },
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 33/48] clk: renesas: r9a07g043: Add support for RZ/Five SoC
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (31 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 32/48] soc: renesas: Identify RZ/Five SoC Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 34/48] cache: Add L2 cache management for Andes AX45MP RISC-V core Lad Prabhakar
` (17 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 95d48d270305ad2ce4e6e8d84a9fb6ea49d6f8aa upstream.
Renesas RZ/Five SoC has almost the same clock structure compared to the
Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.c file to add support for
RZ/Five SoC.
This patch splits up the clocks and reset arrays for RZ/G2UL and RZ/Five
SoC using #ifdef CONFIG_ARM64 and #ifdef CONFIG_RISCV checks.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220622181723.13033-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a07g043-cpg.c | 32 +++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 9d4916aa97ce..1a7a6d60aca4 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -36,9 +36,11 @@ enum clk_ids {
CLK_PLL3_DIV2_4_2,
CLK_SEL_PLL3_3,
CLK_DIV_PLL3_C,
+#ifdef CONFIG_ARM64
CLK_PLL5,
CLK_PLL5_500,
CLK_PLL5_250,
+#endif
CLK_PLL6,
CLK_PLL6_250,
CLK_P1_DIV2,
@@ -100,9 +102,11 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
+#ifdef CONFIG_ARM64
DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6),
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2),
+#endif
DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
@@ -126,12 +130,20 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
};
static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
+#ifdef CONFIG_ARM64
DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
0x514, 0),
DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
0x518, 0),
DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
0x518, 1),
+#endif
+#ifdef CONFIG_RISCV
+ DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2,
+ 0x518, 0),
+ DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1,
+ 0x518, 1),
+#endif
DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
0x52c, 0),
DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
@@ -241,9 +253,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
};
static struct rzg2l_reset r9a07g043_resets[] = {
+#ifdef CONFIG_ARM64
DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
+#endif
+#ifdef CONFIG_RISCV
+ DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0),
+#endif
DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
@@ -289,8 +306,13 @@ static struct rzg2l_reset r9a07g043_resets[] = {
};
static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
+#ifdef CONFIG_ARM64
MOD_CLK_BASE + R9A07G043_GIC600_GICCLK,
MOD_CLK_BASE + R9A07G043_IA55_CLK,
+#endif
+#ifdef CONFIG_RISCV
+ MOD_CLK_BASE + R9A07G043_IAX45_CLK,
+#endif
MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
};
@@ -308,11 +330,21 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = {
/* Module Clocks */
.mod_clks = r9a07g043_mod_clks,
.num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks),
+#ifdef CONFIG_ARM64
.num_hw_mod_clks = R9A07G043_TSU_PCLK + 1,
+#endif
+#ifdef CONFIG_RISCV
+ .num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1,
+#endif
/* Resets */
.resets = r9a07g043_resets,
+#ifdef CONFIG_ARM64
.num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */
+#endif
+#ifdef CONFIG_RISCV
+ .num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
+#endif
.has_clk_mon_regs = true,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 34/48] cache: Add L2 cache management for Andes AX45MP RISC-V core
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (32 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 33/48] clk: renesas: r9a07g043: Add support for " Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 35/48] cache: ax45mp_cache: Add non coherent support Lad Prabhakar
` (16 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit d34599bcd2e4e93a28d5904bf94bc7dafc511f04 upstream.
I/O Coherence Port (IOCP) provides an AXI interface for connecting
external non-caching masters, such as DMA controllers. The accesses
from IOCP are coherent with D-Caches and L2 Cache.
IOCP is a specification option and is disabled on the Renesas RZ/Five
SoC due to this reason IP blocks using DMA will fail.
The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
block that allows dynamic adjustment of memory attributes in the runtime.
It contains a configurable amount of PMA entries implemented as CSR
registers to control the attributes of memory locations in interest.
Below are the memory attributes supported:
* Device, Non-bufferable
* Device, bufferable
* Memory, Non-cacheable, Non-bufferable
* Memory, Non-cacheable, Bufferable
* Memory, Write-back, No-allocate
* Memory, Write-back, Read-allocate
* Memory, Write-back, Write-allocate
* Memory, Write-back, Read and Write-allocate
More info about PMA (section 10.3):
Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
As a workaround for SoCs with IOCP disabled CMO needs to be handled by
software. Firstly OpenSBI configures the memory region as
"Memory, Non-cacheable, Bufferable" and passes this region as a global
shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA
allocations happen from this region and synchronization callbacks are
implemented to synchronize when doing DMA transactions.
Example PMA region passes as a DT node from OpenSBI:
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pma_resv0@58000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x58000000 0x0 0x08000000>;
no-map;
linux,dma-default;
};
};
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
Link: https://lore.kernel.org/r/20230818135723.80612-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
[PL: Dropped calling riscv_noncoherent_register_cache_ops() and also ax45mp_cmo_ops struct]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
MAINTAINERS | 7 ++
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/cache/Kconfig | 9 ++
drivers/cache/Makefile | 3 +
drivers/cache/ax45mp_cache.c | 185 +++++++++++++++++++++++++++++++++++
6 files changed, 207 insertions(+)
create mode 100644 drivers/cache/Kconfig
create mode 100644 drivers/cache/Makefile
create mode 100644 drivers/cache/ax45mp_cache.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 3f1f76eaf48d..8f2e94c0ec19 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16672,6 +16672,13 @@ S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git
F: drivers/staging/
+STANDALONE CACHE CONTROLLER DRIVERS
+M: Conor Dooley <conor@kernel.org>
+L: linux-riscv@lists.infradead.org
+S: Maintained
+T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
+F: drivers/cache
+
STARFIRE/DURALAN NETWORK DRIVER
M: Ion Badulescu <ionut@badula.org>
S: Odd Fixes
diff --git a/drivers/Kconfig b/drivers/Kconfig
index dcecc9f6e33f..5c521370a595 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/base/Kconfig"
source "drivers/bus/Kconfig"
+source "drivers/cache/Kconfig"
+
source "drivers/connector/Kconfig"
source "drivers/gnss/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 576228037718..1428e4d0755e 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -6,6 +6,7 @@
# Rewritten to use lists instead of if-statements.
#
+obj-y += cache/
obj-y += irqchip/
obj-y += bus/
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
new file mode 100644
index 000000000000..3370a5f0e77f
--- /dev/null
+++ b/drivers/cache/Kconfig
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+menu "Cache Drivers"
+
+config AX45MP_L2_CACHE
+ bool "Andes Technology AX45MP L2 Cache controller"
+ help
+ Support for the L2 cache controller on Andes Technology AX45MP platforms.
+
+endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
new file mode 100644
index 000000000000..2012e7fb978d
--- /dev/null
+++ b/drivers/cache/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c
new file mode 100644
index 000000000000..7984b90d04f2
--- /dev/null
+++ b/drivers/cache/ax45mp_cache.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * non-coherent cache functions for Andes AX45MP
+ *
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#include <linux/dma-direction.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+
+/* L2 cache registers */
+#define AX45MP_L2C_REG_CTL_OFFSET 0x8
+
+#define AX45MP_L2C_REG_C0_CMD_OFFSET 0x40
+#define AX45MP_L2C_REG_C0_ACC_OFFSET 0x48
+#define AX45MP_L2C_REG_STATUS_OFFSET 0x80
+
+/* D-cache operation */
+#define AX45MP_CCTL_L1D_VA_INVAL 0 /* Invalidate an L1 cache entry */
+#define AX45MP_CCTL_L1D_VA_WB 1 /* Write-back an L1 cache entry */
+
+/* L2 CCTL status */
+#define AX45MP_CCTL_L2_STATUS_IDLE 0
+
+/* L2 CCTL status cores mask */
+#define AX45MP_CCTL_L2_STATUS_C0_MASK 0xf
+
+/* L2 cache operation */
+#define AX45MP_CCTL_L2_PA_INVAL 0x8 /* Invalidate an L2 cache entry */
+#define AX45MP_CCTL_L2_PA_WB 0x9 /* Write-back an L2 cache entry */
+
+#define AX45MP_L2C_REG_PER_CORE_OFFSET 0x10
+#define AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET 4
+
+#define AX45MP_L2C_REG_CN_CMD_OFFSET(n) \
+ (AX45MP_L2C_REG_C0_CMD_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET))
+#define AX45MP_L2C_REG_CN_ACC_OFFSET(n) \
+ (AX45MP_L2C_REG_C0_ACC_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET))
+#define AX45MP_CCTL_L2_STATUS_CN_MASK(n) \
+ (AX45MP_CCTL_L2_STATUS_C0_MASK << ((n) * AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET))
+
+#define AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM 0x80b
+#define AX45MP_CCTL_REG_UCCTLCOMMAND_NUM 0x80c
+
+#define AX45MP_CACHE_LINE_SIZE 64
+
+struct ax45mp_priv {
+ void __iomem *l2c_base;
+ u32 ax45mp_cache_line_size;
+};
+
+static struct ax45mp_priv ax45mp_priv;
+
+/* L2 Cache operations */
+static inline uint32_t ax45mp_cpu_l2c_get_cctl_status(void)
+{
+ return readl(ax45mp_priv.l2c_base + AX45MP_L2C_REG_STATUS_OFFSET);
+}
+
+static void ax45mp_cpu_cache_operation(unsigned long start, unsigned long end,
+ unsigned int l1_op, unsigned int l2_op)
+{
+ unsigned long line_size = ax45mp_priv.ax45mp_cache_line_size;
+ void __iomem *base = ax45mp_priv.l2c_base;
+ int mhartid = smp_processor_id();
+ unsigned long pa;
+
+ while (end > start) {
+ csr_write(AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM, start);
+ csr_write(AX45MP_CCTL_REG_UCCTLCOMMAND_NUM, l1_op);
+
+ pa = virt_to_phys((void *)start);
+ writel(pa, base + AX45MP_L2C_REG_CN_ACC_OFFSET(mhartid));
+ writel(l2_op, base + AX45MP_L2C_REG_CN_CMD_OFFSET(mhartid));
+ while ((ax45mp_cpu_l2c_get_cctl_status() &
+ AX45MP_CCTL_L2_STATUS_CN_MASK(mhartid)) !=
+ AX45MP_CCTL_L2_STATUS_IDLE)
+ ;
+
+ start += line_size;
+ }
+}
+
+/* Write-back L1 and L2 cache entry */
+static inline void ax45mp_cpu_dcache_wb_range(unsigned long start, unsigned long end)
+{
+ ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_WB,
+ AX45MP_CCTL_L2_PA_WB);
+}
+
+/* Invalidate the L1 and L2 cache entry */
+static inline void ax45mp_cpu_dcache_inval_range(unsigned long start, unsigned long end)
+{
+ ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_INVAL,
+ AX45MP_CCTL_L2_PA_INVAL);
+}
+
+static void ax45mp_dma_cache_inv(phys_addr_t paddr, size_t size)
+{
+ unsigned long start = (unsigned long)phys_to_virt(paddr);
+ unsigned long end = start + size;
+ unsigned long line_size;
+ unsigned long flags;
+
+ if (unlikely(start == end))
+ return;
+
+ line_size = ax45mp_priv.ax45mp_cache_line_size;
+
+ start = start & (~(line_size - 1));
+ end = ((end + line_size - 1) & (~(line_size - 1)));
+
+ local_irq_save(flags);
+
+ ax45mp_cpu_dcache_inval_range(start, end);
+
+ local_irq_restore(flags);
+}
+
+static void ax45mp_dma_cache_wback(phys_addr_t paddr, size_t size)
+{
+ unsigned long start = (unsigned long)phys_to_virt(paddr);
+ unsigned long end = start + size;
+ unsigned long line_size;
+ unsigned long flags;
+
+ line_size = ax45mp_priv.ax45mp_cache_line_size;
+ start = start & (~(line_size - 1));
+ local_irq_save(flags);
+ ax45mp_cpu_dcache_wb_range(start, end);
+ local_irq_restore(flags);
+}
+
+static int ax45mp_get_l2_line_size(struct device_node *np)
+{
+ int ret;
+
+ ret = of_property_read_u32(np, "cache-line-size", &ax45mp_priv.ax45mp_cache_line_size);
+ if (ret) {
+ pr_err("Failed to get cache-line-size, defaulting to 64 bytes\n");
+ return ret;
+ }
+
+ if (ax45mp_priv.ax45mp_cache_line_size != AX45MP_CACHE_LINE_SIZE) {
+ pr_err("Expected cache-line-size to be 64 bytes (found:%u)\n",
+ ax45mp_priv.ax45mp_cache_line_size);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id ax45mp_cache_ids[] = {
+ { .compatible = "andestech,ax45mp-cache" },
+ { /* sentinel */ }
+};
+
+static int __init ax45mp_cache_init(void)
+{
+ struct device_node *np;
+ struct resource res;
+ int ret;
+
+ np = of_find_matching_node(NULL, ax45mp_cache_ids);
+ if (!of_device_is_available(np))
+ return -ENODEV;
+
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret)
+ return ret;
+
+ ax45mp_priv.l2c_base = ioremap(res.start, resource_size(&res));
+ if (!ax45mp_priv.l2c_base)
+ return -ENOMEM;
+
+ ret = ax45mp_get_l2_line_size(np);
+ if (ret) {
+ iounmap(ax45mp_priv.l2c_base);
+ return ret;
+ }
+
+ return 0;
+}
+early_initcall(ax45mp_cache_init);
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 35/48] cache: ax45mp_cache: Add non coherent support
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (33 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 34/48] cache: Add L2 cache management for Andes AX45MP RISC-V core Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 19:36 ` Pavel Machek
2024-02-05 12:41 ` [PATCH 5.10.y-cip 36/48] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Lad Prabhakar
` (15 subsequent siblings)
50 siblings, 1 reply; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
As support for non-coherent DMA is missing in 5.10-cip for RISC-V
architecture, introducing a new patch to support non-coherent DMA
support on RZ/Five SoC.
This enables the required config and the callbacks required to handle
the non-coherent DMA support for Renesas RZ/Five SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/cache/Kconfig | 3 ++
drivers/cache/ax45mp_cache.c | 54 ++++++++++++++++++++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 3370a5f0e77f..400cb09f6bd4 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -3,6 +3,9 @@ menu "Cache Drivers"
config AX45MP_L2_CACHE
bool "Andes Technology AX45MP L2 Cache controller"
+ select ARCH_HAS_SYNC_DMA_FOR_CPU
+ select ARCH_HAS_SYNC_DMA_FOR_DEVICE
+ select ARCH_HAS_SETUP_DMA_OPS
help
Support for the L2 cache controller on Andes Technology AX45MP platforms.
diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c
index 7984b90d04f2..f7db1ed3e973 100644
--- a/drivers/cache/ax45mp_cache.c
+++ b/drivers/cache/ax45mp_cache.c
@@ -132,6 +132,60 @@ static void ax45mp_dma_cache_wback(phys_addr_t paddr, size_t size)
local_irq_restore(flags);
}
+static void ax45mp_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+ ax45mp_dma_cache_wback(paddr, size);
+ ax45mp_dma_cache_inv(paddr, size);
+}
+
+void arch_sync_dma_for_device(phys_addr_t paddr,
+ size_t size, enum dma_data_direction dir)
+{
+ switch (dir) {
+ case DMA_TO_DEVICE:
+ ax45mp_dma_cache_wback(paddr, size);
+ break;
+
+ case DMA_FROM_DEVICE:
+ fallthrough;
+
+ case DMA_BIDIRECTIONAL:
+ /* Skip the invalidate here if it's done later */
+ if (IS_ENABLED(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU))
+ ax45mp_dma_cache_wback(paddr, size);
+ else
+ ax45mp_dma_cache_wback_inv(paddr, size);
+ break;
+
+ default:
+ break;
+ }
+}
+
+void arch_sync_dma_for_cpu(phys_addr_t paddr,
+ size_t size, enum dma_data_direction dir)
+{
+ switch (dir) {
+ case DMA_TO_DEVICE:
+ break;
+
+ case DMA_FROM_DEVICE:
+ case DMA_BIDIRECTIONAL:
+ /* FROM_DEVICE invalidate needed if speculative CPU prefetch only */
+ ax45mp_dma_cache_inv(paddr, size);
+ break;
+
+ default:
+ break;
+ }
+}
+
+void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
+ const struct iommu_ops *iommu, bool coherent)
+{
+ dev->dma_coherent = coherent;
+}
+
static int ax45mp_get_l2_line_size(struct device_node *np)
{
int ret;
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 36/48] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (34 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 35/48] cache: ax45mp_cache: Add non coherent support Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 37/48] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Lad Prabhakar
` (14 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 484861e09f3ed8fb2e1de290d9e33fee3611b9fc upstream.
Explicitly select the required Cache management and Errata configs
required for the RZ/Five SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
Link: https://lore.kernel.org/r/20230818135723.80612-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
[PL: dropped selecting ERRATA_ANDES/_CMO]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/soc/renesas/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 69f123f1b5f9..d8d0d37948ad 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -320,6 +320,8 @@ if RISCV
config ARCH_R9A07G043
bool "RISC-V Platform support for RZ/Five"
select ARCH_RZG2L
+ select AX45MP_L2_CACHE
+ select DMA_GLOBAL_POOL
help
This enables support for the Renesas RZ/Five SoC.
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 37/48] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (35 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 36/48] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 38/48] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
` (13 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 8292493c22c8e28b6e67a01e0f5c6db1cf231eb1 upstream.
Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221028165921.94487-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/Kconfig.socs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 8a55f6156661..506bef444396 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,10 @@
menu "SoC selection"
+config ARCH_RENESAS
+ bool "Renesas RISC-V SoCs"
+ help
+ This enables support for the RISC-V based Renesas SoCs.
+
config SOC_SIFIVE
bool "SiFive SoCs"
select SERIAL_SIFIVE if TTY
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 38/48] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (36 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 37/48] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 39/48] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar
` (12 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit b3e77da00f1b7b670983c69d0295f4ce132bf87c upstream.
Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
Single).
RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
Below are the RZ/Five SoC specific blocks added in the initial DTSI which
can be used to boot via initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- PLIC
[0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221028165921.94487-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
new file mode 100644
index 000000000000..50134be548f5
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
+
+#include <arm64/renesas/r9a07g043.dtsi>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <12000000>;
+
+ cpu0: cpu@0 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ reg = <0x0>;
+ status = "okay";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x40>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x40>;
+ clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+};
+
+&soc {
+ interrupt-parent = <&plic>;
+
+ plic: interrupt-controller@12c00000 {
+ compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ riscv,ndev = <511>;
+ interrupt-controller;
+ reg = <0x0 0x12c00000 0 0x400000>;
+ clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+ interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 39/48] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (37 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 38/48] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 40/48] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU Lad Prabhakar
` (11 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 4adb690aa1b41c1e52af579574d1d6aa58da1187 upstream.
Enable the minimal blocks required for booting the Renesas RZ/Five
SMARC EVK with initramfs.
Below are the blocks which are enabled:
- CPG
- CPU0
- DDR (memory regions)
- PINCTRL
- PLIC
- SCIF0
As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and
carrier [2] board DTSIs which enables almost all the blocks supported
by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually
enabling the blocks hence the aliases for ETH/I2C are deleted and rest
of the IP blocks are marked as disabled/deleted.
[0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
[1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
[2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221028165921.94487-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/Makefile | 2 +
.../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++
5 files changed, 179 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/Makefile
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ca1f8cbd78c0..c968514d0b4d 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += sifive
subdir-y += kendryte
+subdir-y += renesas
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile
new file mode 100644
index 000000000000..2d3f5751a649
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
new file mode 100644
index 000000000000..2aa8515451d3
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+/*
+ * DIP-Switch SW1 setting
+ * 1 : High; 0: Low
+ * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
+ * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
+ * Please change below macros according to SW1 setting on the SoM
+ */
+#define SW_SW0_DEV_SEL 1
+#define SW_ET0_EN_N 1
+
+#include "r9a07g043f.dtsi"
+#include "rzfive-smarc-som.dtsi"
+#include "rzfive-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g043f01";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
+};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
new file mode 100644
index 000000000000..45a182fa3b4b
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK SOM
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
+
+/ {
+ aliases {
+ /delete-property/ ethernet0;
+ /delete-property/ ethernet1;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ };
+
+ /delete-node/opp-table-0;
+ /delete-node/thermal-zones;
+};
+
+&adc {
+ status = "disabled";
+};
+
+&dmac {
+ status = "disabled";
+};
+
+ð0 {
+ status = "disabled";
+};
+
+ð1 {
+ status = "disabled";
+};
+
+&ostm1 {
+ status = "disabled";
+};
+
+&ostm2 {
+ status = "disabled";
+};
+
+&sdhi0 {
+ status = "disabled";
+};
+
+&tsu {
+ status = "disabled";
+};
+
+&wdt0 {
+ status = "disabled";
+};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
new file mode 100644
index 000000000000..e64f0e5f8e30
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK carrier board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc.dtsi>
+
+/ {
+ aliases {
+ /delete-property/ i2c0;
+ /delete-property/ i2c1;
+ };
+};
+
+&canfd {
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+
+ channel1 {
+ status = "disabled";
+ };
+};
+
+&ehci0 {
+ status = "disabled";
+};
+
+&ehci1 {
+ status = "disabled";
+};
+
+&hsusb {
+ status = "disabled";
+};
+
+&i2c0 {
+ status = "disabled";
+};
+
+&i2c1 {
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "disabled";
+};
+
+&ohci1 {
+ status = "disabled";
+};
+
+&phyrst {
+ status = "disabled";
+};
+
+&sdhi1 {
+ status = "disabled";
+};
+
+&snd_rzg2l {
+ status = "disabled";
+};
+
+&spi1 {
+ status = "disabled";
+};
+
+&ssi1 {
+ status = "disabled";
+};
+
+&usb0_vbus_otg {
+ status = "disabled";
+};
+
+&usb2_phy0 {
+ status = "disabled";
+};
+
+&usb2_phy1 {
+ status = "disabled";
+};
+
+&vccq_sdhi1 {
+ status = "disabled";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 40/48] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (38 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 39/48] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 41/48] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C Lad Prabhakar
` (10 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 42d3345eb3466587798c25a7e5704e15b738263e upstream.
Enable support for below blocks found on RZ/Five SMARC EVK SoC/SoM:
- ADC
- OPP
- Thermal Zones
- TSU
Note, these blocks are enabled in RZ/G2UL SMARC SoM DTSI [0] hence
deleting these disabled nodes from RZ/Five SMARC SoM DTSI enables them
here too as we include [0] in RZ/Five SMARC SoM DTSI.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221115105135.1180490-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 ++
arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi | 11 -----------
2 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 50134be548f5..6ec1c6f9a403 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -20,6 +20,7 @@ cpus {
cpu0: cpu@0 {
compatible = "andestech,ax45mp", "riscv";
device_type = "cpu";
+ #cooling-cells = <2>;
reg = <0x0>;
status = "okay";
riscv,isa = "rv64imafdc";
@@ -29,6 +30,7 @@ cpu0: cpu@0 {
d-cache-size = <0x8000>;
d-cache-line-size = <0x40>;
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+ operating-points-v2 = <&cluster0_opp>;
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
index 45a182fa3b4b..2b7672bc4b52 100644
--- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -16,13 +16,6 @@ aliases {
chosen {
bootargs = "ignore_loglevel";
};
-
- /delete-node/opp-table-0;
- /delete-node/thermal-zones;
-};
-
-&adc {
- status = "disabled";
};
&dmac {
@@ -49,10 +42,6 @@ &sdhi0 {
status = "disabled";
};
-&tsu {
- status = "disabled";
-};
-
&wdt0 {
status = "disabled";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 41/48] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (39 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 40/48] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 42/48] riscv: dts: renesas: rzfive-smarc-som: Enable WDT Lad Prabhakar
` (9 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 40005cb6093e92d24a1bdbc444311c25e4b28878 upstream.
Enable CANFD and I2C on RZ/Five SMARC EVK.
Note, these blocks are enabled in RZ/G2UL SMARC EVK DTSI [0] hence
deleting these disabled nodes from RZ/Five SMARC EVK DTSI enables them
here too as we include [0] in RZ/Five SMARC EVK DTSI.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221115105135.1180490-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 27 -------------------
1 file changed, 27 deletions(-)
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
index e64f0e5f8e30..c07a487c4e5a 100644
--- a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
@@ -7,25 +7,6 @@
#include <arm64/renesas/rzg2ul-smarc.dtsi>
-/ {
- aliases {
- /delete-property/ i2c0;
- /delete-property/ i2c1;
- };
-};
-
-&canfd {
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
-};
-
&ehci0 {
status = "disabled";
};
@@ -38,14 +19,6 @@ &hsusb {
status = "disabled";
};
-&i2c0 {
- status = "disabled";
-};
-
-&i2c1 {
- status = "disabled";
-};
-
&ohci0 {
status = "disabled";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 42/48] riscv: dts: renesas: rzfive-smarc-som: Enable WDT
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (40 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 41/48] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 43/48] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes Lad Prabhakar
` (8 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 3e9e6fc9c64f7b9b777c5b2c2e2c9a1326065137 upstream.
Enable WDT node on RZ/Five SMARC SoM.
Note, WDT block is enabled in RZ/G2UL SMARC SoM DTSI [0] hence deleting
the disabled node from RZ/Five SMARC SoM DTSI enables it here too as we
include [0] in RZ/Five SMARC SoM DTSI.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221118135715.14410-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
index 2b7672bc4b52..fdfd7cd2792b 100644
--- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -41,7 +41,3 @@ &ostm2 {
&sdhi0 {
status = "disabled";
};
-
-&wdt0 {
- status = "disabled";
-};
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 43/48] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (41 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 42/48] riscv: dts: renesas: rzfive-smarc-som: Enable WDT Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 44/48] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} Lad Prabhakar
` (7 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit c68b12a902067aa6c88aa02c29673a96ef086e5d upstream.
Enable OSTM{1,2} nodes on RZ/Five SMARC SoM.
Note, OSTM{1,2} nodes are enabled in the RZ/G2UL SMARC SoM DTSI [0] hence
deleting the disabled nodes from RZ/Five SMARC SoM DTSI enables it here
too as we include [0] in RZ/Five SMARC SoM DTSI.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230102222233.274021-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi | 8 --------
1 file changed, 8 deletions(-)
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
index fdfd7cd2792b..73941a5f844d 100644
--- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -30,14 +30,6 @@ ð1 {
status = "disabled";
};
-&ostm1 {
- status = "disabled";
-};
-
-&ostm2 {
- status = "disabled";
-};
-
&sdhi0 {
status = "disabled";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 44/48] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1}
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (42 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 43/48] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 45/48] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node Lad Prabhakar
` (6 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 7dd48e96d0cda9af79a2fee85e9135b4781f9ee1 upstream.
IRQC support for RZ/Five is still missing so drop the interrupts and
interrupt-parent properties from the PHY nodes of ETH{0,1}.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230102222708.274369-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
index 73941a5f844d..d6f18754eb5d 100644
--- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -24,10 +24,20 @@ &dmac {
ð0 {
status = "disabled";
+
+ phy0: ethernet-phy@7 {
+ /delete-property/ interrupt-parent;
+ /delete-property/ interrupts;
+ };
};
ð1 {
status = "disabled";
+
+ phy1: ethernet-phy@7 {
+ /delete-property/ interrupt-parent;
+ /delete-property/ interrupts;
+ };
};
&sdhi0 {
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 45/48] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (43 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 44/48] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 46/48] riscv: dts: renesas: r9a07g043f: Add L2 cache node Lad Prabhakar
` (5 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Conor Dooley <conor.dooley@microchip.com>
commit 7a98d75c4a63a90e81178170b748512e7a23417d upstream.
dtbs_check w/ W=1 complains:
Warning (unit_address_vs_reg): /soc/ethernet@11c20000/ethernet-phy@7: node has a unit name, but no reg or ranges property
Warning (avoid_unnecessary_addr_size): /soc/ethernet@11c20000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
The ethernet@11c20000 node is guarded by an `#if (!SW_ET0_EN_N)` in
rzg2ul-smarc-som.dtsi, where the phy child node is added. In
rzfive-smarc-som.dtsi, the ethernet node is marked disabled & the
interrupt properties are deleted from the phy child node. As a result,
the produced dts looks like:
ethernet@11c20000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
/* snip */
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ethernet-phy@7 {
};
};
Adding a corresponding `#if (!SW_ET0_EN_N)` around the node in
rzfive-smarc-som.dtsi avoids the complaint, as the empty child node is
not added:
ethernet@11c20000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
/* snip */
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230712-squealer-walmart-9587342ddec1@wendy
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
index d6f18754eb5d..c62debc7ca7e 100644
--- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -22,6 +22,7 @@ &dmac {
status = "disabled";
};
+#if (!SW_ET0_EN_N)
ð0 {
status = "disabled";
@@ -30,6 +31,7 @@ phy0: ethernet-phy@7 {
/delete-property/ interrupts;
};
};
+#endif
ð1 {
status = "disabled";
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 46/48] riscv: dts: renesas: r9a07g043f: Add L2 cache node
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (44 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 45/48] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 47/48] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property Lad Prabhakar
` (4 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit a38b1061d327c120844e5dc0217191b06ce3b25f upstream.
Add L2 cache node for RZ/Five SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929000704.53217-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 6ec1c6f9a403..c8d63a8f7d86 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -29,6 +29,7 @@ cpu0: cpu@0 {
i-cache-line-size = <0x40>;
d-cache-size = <0x8000>;
d-cache-line-size = <0x40>;
+ next-level-cache = <&l2cache>;
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
operating-points-v2 = <&cluster0_opp>;
@@ -56,4 +57,15 @@ plic: interrupt-controller@12c00000 {
resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
};
+
+ l2cache: cache-controller@13400000 {
+ compatible = "andestech,ax45mp-cache", "cache";
+ reg = <0x0 0x13400000 0x0 0x100000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-unified;
+ cache-level = <2>;
+ };
};
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 47/48] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (45 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 46/48] riscv: dts: renesas: r9a07g043f: Add L2 cache node Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 48/48] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled Lad Prabhakar
` (3 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 9e40584dc2592edbd35485731c3e9ab1291e6a13 upstream.
RZ/Five is a noncoherent SoC so to indicate this add dma-noncoherent
property to RZ/Five SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929000704.53217-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index c8d63a8f7d86..b0796015e36b 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -43,6 +43,7 @@ cpu0_intc: interrupt-controller {
};
&soc {
+ dma-noncoherent;
interrupt-parent = <&plic>;
plic: interrupt-controller@12c00000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 5.10.y-cip 48/48] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (46 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 47/48] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property Lad Prabhakar
@ 2024-02-05 12:41 ` Lad Prabhakar
2024-02-05 19:33 ` [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Pavel Machek
` (2 subsequent siblings)
50 siblings, 0 replies; 59+ messages in thread
From: Lad Prabhakar @ 2024-02-05 12:41 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit bfef0760d247550318a4a4a71ae472875caf711c upstream.
Now that noncoherent dma support for the RZ/Five SoC has been added, enable
the IP blocks which were disabled on the RZ/Five SMARC. This adds
support for the below peripherals:
* Ethernet
* DMAC
* SDHI
* USB
* RSPI
* SSI
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929000704.53217-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 23 --------
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 56 -------------------
2 files changed, 79 deletions(-)
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
index c62debc7ca7e..433ab5c6a626 100644
--- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -7,25 +7,8 @@
#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
-/ {
- aliases {
- /delete-property/ ethernet0;
- /delete-property/ ethernet1;
- };
-
- chosen {
- bootargs = "ignore_loglevel";
- };
-};
-
-&dmac {
- status = "disabled";
-};
-
#if (!SW_ET0_EN_N)
ð0 {
- status = "disabled";
-
phy0: ethernet-phy@7 {
/delete-property/ interrupt-parent;
/delete-property/ interrupts;
@@ -34,14 +17,8 @@ phy0: ethernet-phy@7 {
#endif
ð1 {
- status = "disabled";
-
phy1: ethernet-phy@7 {
/delete-property/ interrupt-parent;
/delete-property/ interrupts;
};
};
-
-&sdhi0 {
- status = "disabled";
-};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
index c07a487c4e5a..a8573fdfd8b1 100644
--- a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
@@ -6,59 +6,3 @@
*/
#include <arm64/renesas/rzg2ul-smarc.dtsi>
-
-&ehci0 {
- status = "disabled";
-};
-
-&ehci1 {
- status = "disabled";
-};
-
-&hsusb {
- status = "disabled";
-};
-
-&ohci0 {
- status = "disabled";
-};
-
-&ohci1 {
- status = "disabled";
-};
-
-&phyrst {
- status = "disabled";
-};
-
-&sdhi1 {
- status = "disabled";
-};
-
-&snd_rzg2l {
- status = "disabled";
-};
-
-&spi1 {
- status = "disabled";
-};
-
-&ssi1 {
- status = "disabled";
-};
-
-&usb0_vbus_otg {
- status = "disabled";
-};
-
-&usb2_phy0 {
- status = "disabled";
-};
-
-&usb2_phy1 {
- status = "disabled";
-};
-
-&vccq_sdhi1 {
- status = "disabled";
-};
--
2.34.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* Re: [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (47 preceding siblings ...)
2024-02-05 12:41 ` [PATCH 5.10.y-cip 48/48] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled Lad Prabhakar
@ 2024-02-05 19:33 ` Pavel Machek
2024-02-06 8:20 ` nobuhiro1.iwamatsu
2024-02-06 8:29 ` Pavel Machek
50 siblings, 0 replies; 59+ messages in thread
From: Pavel Machek @ 2024-02-05 19:33 UTC (permalink / raw)
To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das
[-- Attachment #1: Type: text/plain, Size: 986 bytes --]
Hi!
> This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
> support for this SoC has already been added to 6.1-cip kernel.
>
> RFC->v1
> * Patch #35 updated according uptstream for easier maitainance.
> Rest of the patches have been unchanged.
> * Merged RFC series [0] and preporatory series [1].
> * Previous test run results can be found at [2].
> * RISC-V Renesas defconfig file can be found at [3].
Thanks for patches. AFAICT 1..4 are already applied to the 5.10 tree,
so we won't duplicate those.
I only have minor comment to one of the patches, that should not
prevent merge. I can apply the series if there are no other comments.
I rely on you for testing. I'd like to see qemu-risv enabled for 5.10
and 6.1, so that we have more than once architecture.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 5.10.y-cip 35/48] cache: ax45mp_cache: Add non coherent support
2024-02-05 12:41 ` [PATCH 5.10.y-cip 35/48] cache: ax45mp_cache: Add non coherent support Lad Prabhakar
@ 2024-02-05 19:36 ` Pavel Machek
0 siblings, 0 replies; 59+ messages in thread
From: Pavel Machek @ 2024-02-05 19:36 UTC (permalink / raw)
To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das
[-- Attachment #1: Type: text/plain, Size: 980 bytes --]
Hi!
> As support for non-coherent DMA is missing in 5.10-cip for RISC-V
> architecture, introducing a new patch to support non-coherent DMA
> support on RZ/Five SoC.
> +void arch_sync_dma_for_cpu(phys_addr_t paddr,
> + size_t size, enum dma_data_direction dir)
> +{
> + switch (dir) {
> + case DMA_TO_DEVICE:
> + break;
> +
> + case DMA_FROM_DEVICE:
> + case DMA_BIDIRECTIONAL:
> + /* FROM_DEVICE invalidate needed if speculative CPU prefetch only */
I believe the comment will need fixing w.r.t. english.
Plus, some explanation. The risc-v CPU you are using is not doing
speculative execution, right?
> + ax45mp_dma_cache_inv(paddr, size);
If it is, it could do prefetch here, and break the rules, no?
If it is not, do we need the invalidate?
> + break;
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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^ permalink raw reply [flat|nested] 59+ messages in thread
* RE: [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (48 preceding siblings ...)
2024-02-05 19:33 ` [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Pavel Machek
@ 2024-02-06 8:20 ` nobuhiro1.iwamatsu
2024-02-06 8:29 ` Pavel Machek
50 siblings, 0 replies; 59+ messages in thread
From: nobuhiro1.iwamatsu @ 2024-02-06 8:20 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, cip-dev, pavel; +Cc: biju.das.jz
Hi all,
> -----Original Message-----
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Sent: Monday, February 5, 2024 9:41 PM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 ○ＤＩＴＣ□
> ＤＩＴ○ＯＳＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>
> Subject: [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V
> SoC
>
> Hi All,
>
> This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
> support for this SoC has already been added to 6.1-cip kernel.
>
> RFC->v1
> * Patch #35 updated according uptstream for easier maitainance.
> Rest of the patches have been unchanged.
> * Merged RFC series [0] and preporatory series [1].
> * Previous test run results can be found at [2].
> * RISC-V Renesas defconfig file can be found at [3].
>
> [0]
> https://patchwork.kernel.org/project/cip-dev/cover/20240130203346.94488-1
> -prabhakar.mahadev-lad.rj@bp.renesas.com/
> [1]
> https://patchwork.kernel.org/project/cip-dev/cover/20240130161555.85042-1
> -prabhakar.mahadev-lad.rj@bp.renesas.com/
> [2]
> https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1160504705
> [3]
> https://gitlab.com/cip-project/cip-kernel/cip-kernel-config/-/blob/rzfive-5.1
> 0-cip/5.10.y-cip/riscv/renesas_defconfig?ref_type=heads
>
> Cheers,
> Prabhakar
>
> Christoph Hellwig (5):
> dma-direct: add support for dma_coherent_default_memory
> dma-mapping: allow using the global coherent pool for !ARM
> dma-mapping: simplify dma_init_coherent_memory
> dma-mapping: add a dma_init_global_coherent helper
> dma-mapping: make the global coherent pool conditional
>
> Conor Dooley (1):
> riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy
> node
>
> Heiko Stuebner (1):
> of: also handle dma-noncoherent in of_dma_is_coherent()
>
> Lad Prabhakar (34):
> ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and
> interrupt-names properties
> ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels
> arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels
> arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels
> arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to
> board DTS
> arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS
> arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro
> to specify interrupt property
> arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels
> arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
> riscv: Kconfig: Enable cpufreq kconfig menu
> irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
> clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC
> clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback
> mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option
> dependant on ARCH_RENESAS
> dt-bindings: riscv: Sort the CPU core list alphabetically
> dt-bindings: riscv: Add Andes AX45MP core to the list
> dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and
> Reset Definitions
> dt-bindings: cache: andestech,ax45mp-cache: Add DT binding
> documentation for L2 cache controller
> soc: renesas: Identify RZ/Five SoC
> clk: renesas: r9a07g043: Add support for RZ/Five SoC
> cache: Add L2 cache management for Andes AX45MP RISC-V core
> cache: ax45mp_cache: Add non coherent support
> soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
> riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
> riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
> riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
> riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable
> ADC/OPP/Thermal Zones/TSU
> riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
> riscv: dts: renesas: rzfive-smarc-som: Enable WDT
> riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes
> riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for
> ETH{0,1}
> riscv: dts: renesas: r9a07g043f: Add L2 cache node
> riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property
> riscv: dts: renesas: rzfive-smarc: Enable the blocks which were
> explicitly disabled
>
> Niklas Cassel (2):
> irqchip/sifive-plic: Improve naming scheme for per context offsets
> irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode
>
> Samuel Holland (4):
> of/irq: Use interrupts-extended to find parent
> irqchip/sifive-plic: Make better use of the effective affinity mask
> irqchip/sifive-plic: Separate the enable and mask operations
> clocksource/drivers/riscv: Increase the clock source rating
>
> Xiongfeng Wang (1):
> cacheinfo: clear cache_leaves(cpu) in free_cache_attributes()
>
> .../cache/andestech,ax45mp-cache.yaml | 81 ++++
> .../devicetree/bindings/riscv/cpus.yaml | 7 +-
> .../bindings/sound/renesas,rz-ssi.yaml | 21 +-
> MAINTAINERS | 7 +
> arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 350
> ++++++++----------
> arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 72 ++++
> .../boot/dts/renesas/r9a07g043u11-smarc.dts | 17 +-
> arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +-
> arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 19 +-
> arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 14 -
> arch/riscv/Kconfig | 3 +-
> arch/riscv/Kconfig.socs | 5 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/Makefile | 2 +
> arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 72 ++++
> .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++
> .../boot/dts/renesas/rzfive-smarc-som.dtsi | 24 ++
> arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 8 +
> arch/riscv/kernel/time.c | 9 -
> drivers/Kconfig | 2 +
> drivers/Makefile | 1 +
> drivers/base/cacheinfo.c | 1 +
> drivers/cache/Kconfig | 12 +
> drivers/cache/Makefile | 3 +
> drivers/cache/ax45mp_cache.c | 239 ++++++++++++
> drivers/clk/renesas/r9a07g043-cpg.c | 32 ++
> drivers/clocksource/renesas-ostm.c | 2 +-
> drivers/clocksource/timer-riscv.c | 7 +-
> drivers/irqchip/Kconfig | 1 +
> drivers/irqchip/irq-sifive-plic.c | 178 ++++++---
> drivers/mmc/host/Kconfig | 4 +-
> drivers/of/address.c | 17 +-
> drivers/of/irq.c | 13 +-
> drivers/soc/renesas/Kconfig | 12 +
> drivers/soc/renesas/renesas-soc.c | 13 +
> include/dt-bindings/clock/r9a07g043-cpg.h | 20 +
> include/linux/dma-map-ops.h | 18 +-
> kernel/dma/Kconfig | 4 +
> kernel/dma/coherent.c | 161 ++++----
> kernel/dma/direct.c | 17 +
> sound/soc/sh/rz-ssi.c | 63 +++-
> 41 files changed, 1143 insertions(+), 435 deletions(-) create mode 100644
> Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> create mode 100644 drivers/cache/Kconfig create mode 100644
> drivers/cache/Makefile create mode 100644 drivers/cache/ax45mp_cache.c
I reviewed this series, there was nothing to point out without from 1/48 to 4/48.
# from 1/48 to 4/48 are already applied to Linux-5.10.y-cip.
I can apply this series, if there are no other comment.
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Best regards,
Nobuhiro
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
` (49 preceding siblings ...)
2024-02-06 8:20 ` nobuhiro1.iwamatsu
@ 2024-02-06 8:29 ` Pavel Machek
2024-02-06 9:02 ` Prabhakar Mahadev Lad
50 siblings, 1 reply; 59+ messages in thread
From: Pavel Machek @ 2024-02-06 8:29 UTC (permalink / raw)
To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das
[-- Attachment #1: Type: text/plain, Size: 1059 bytes --]
Hi!
> This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
> support for this SoC has already been added to 6.1-cip kernel.
>
> RFC->v1
> * Patch #35 updated according uptstream for easier maitainance.
> Rest of the patches have been unchanged.
> * Merged RFC series [0] and preporatory series [1].
> * Previous test run results can be found at [2].
> * RISC-V Renesas defconfig file can be found at [3].
I tried to apply/test the series, and besides 1..4 being already
applied, these failed, too:
Can you double-check?
> Christoph Hellwig (5):
> dma-direct: add support for dma_coherent_default_memory
> dma-mapping: allow using the global coherent pool for !ARM
> dma-mapping: simplify dma_init_coherent_memory
> dma-mapping: add a dma_init_global_coherent helper
> dma-mapping: make the global coherent pool conditional
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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^ permalink raw reply [flat|nested] 59+ messages in thread
* RE: [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC
2024-02-06 8:29 ` Pavel Machek
@ 2024-02-06 9:02 ` Prabhakar Mahadev Lad
2024-02-06 9:08 ` Pavel Machek
0 siblings, 1 reply; 59+ messages in thread
From: Prabhakar Mahadev Lad @ 2024-02-06 9:02 UTC (permalink / raw)
To: Pavel Machek; +Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das
Hi Pavel,
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: Tuesday, February 6, 2024 8:29 AM
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC
>
> Hi!
>
> > This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
> > support for this SoC has already been added to 6.1-cip kernel.
> >
> > RFC->v1
> > * Patch #35 updated according uptstream for easier maitainance.
> > Rest of the patches have been unchanged.
> > * Merged RFC series [0] and preporatory series [1].
> > * Previous test run results can be found at [2].
> > * RISC-V Renesas defconfig file can be found at [3].
>
> I tried to apply/test the series, and besides 1..4 being already applied, these failed, too:
>
> Can you double-check?
>
Can you please point me to the pipeline.
Cheers,
Prabhakar
> > Christoph Hellwig (5):
> > dma-direct: add support for dma_coherent_default_memory
> > dma-mapping: allow using the global coherent pool for !ARM
> > dma-mapping: simplify dma_init_coherent_memory
> > dma-mapping: add a dma_init_global_coherent helper
> > dma-mapping: make the global coherent pool conditional
>
> Best regards,
> Pavel
> --
> DENX Software Engineering GmbH, Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC
2024-02-06 9:02 ` Prabhakar Mahadev Lad
@ 2024-02-06 9:08 ` Pavel Machek
0 siblings, 0 replies; 59+ messages in thread
From: Pavel Machek @ 2024-02-06 9:08 UTC (permalink / raw)
To: Prabhakar Mahadev Lad; +Cc: Pavel Machek, cip-dev, Nobuhiro Iwamatsu, Biju Das
[-- Attachment #1: Type: text/plain, Size: 930 bytes --]
Hi!
> > > This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
> > > support for this SoC has already been added to 6.1-cip kernel.
> > >
> > > RFC->v1
> > > * Patch #35 updated according uptstream for easier maitainance.
> > > Rest of the patches have been unchanged.
> > > * Merged RFC series [0] and preporatory series [1].
> > > * Previous test run results can be found at [2].
> > > * RISC-V Renesas defconfig file can be found at [3].
> >
> > I tried to apply/test the series, and besides 1..4 being already applied, these failed, too:
> >
> > Can you double-check?
> >
> Can you please point me to the pipeline.
git am failed for me, so I don't really have a pipeline. Do I need to
double-check? :-)
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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^ permalink raw reply [flat|nested] 59+ messages in thread
* RE: [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory
2024-02-05 12:41 ` [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory Lad Prabhakar
@ 2024-02-06 9:18 ` nobuhiro1.iwamatsu
2024-02-06 9:52 ` Prabhakar Mahadev Lad
0 siblings, 1 reply; 59+ messages in thread
From: nobuhiro1.iwamatsu @ 2024-02-06 9:18 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, cip-dev, pavel; +Cc: biju.das.jz
Hi,
> -----Original Message-----
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Sent: Monday, February 5, 2024 9:41 PM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 ○ＤＩＴＣ□
> ＤＩＴ○ＯＳＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>
> Subject: [PATCH 5.10.y-cip 14/48] dma-mapping: simplify
> dma_init_coherent_memory
>
> From: Christoph Hellwig <hch@lst.de>
>
> commit a6933571f34a9aee843fff2aa4b96949c57d6274 upstream.
>
> Return the allocated dma_coherent_mem structure, set the
> use_dma_pfn_offset and print the failure warning inside of
> dma_init_coherent_memory instead of leaving that to the callers.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> Tested-by: Dillon Min <dillon.minfei@gmail.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> kernel/dma/coherent.c | 78
> ++++++++++++++++++-------------------------
> 1 file changed, 33 insertions(+), 45 deletions(-)
>
I can not apply this patch cip/Linux-5.10.y-cip.
Could you check this ?
$ git am -s patch.series
Applying: arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS
Applying: arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS
Applying: arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property
Applying: arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels
Applying: arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
Applying: cacheinfo: clear cache_leaves(cpu) in free_cache_attributes()
Applying: riscv: Kconfig: Enable cpufreq kconfig menu
Applying: dma-direct: add support for dma_coherent_default_memory
Applying: dma-mapping: allow using the global coherent pool for !ARM
Applying: dma-mapping: simplify dma_init_coherent_memory
error: patch failed: kernel/dma/coherent.c:37
error: kernel/dma/coherent.c: patch does not apply
Patch failed at 0010 dma-mapping: simplify dma_init_coherent_memory
hint: Use 'git am --show-current-patch=diff' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Best regards,
Nobuhiro
^ permalink raw reply [flat|nested] 59+ messages in thread
* RE: [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory
2024-02-06 9:18 ` nobuhiro1.iwamatsu
@ 2024-02-06 9:52 ` Prabhakar Mahadev Lad
2024-02-06 10:12 ` Pavel Machek
0 siblings, 1 reply; 59+ messages in thread
From: Prabhakar Mahadev Lad @ 2024-02-06 9:52 UTC (permalink / raw)
To: nobuhiro1.iwamatsu, cip-dev, pavel; +Cc: Biju Das
Hi Nobuhiro, Pavel,
> -----Original Message-----
> From: nobuhiro1.iwamatsu@toshiba.co.jp <nobuhiro1.iwamatsu@toshiba.co.jp>
> Sent: Tuesday, February 6, 2024 9:19 AM
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; cip-dev@lists.cip-project.org;
> pavel@denx.de
> Cc: Biju Das <biju.das.jz@bp.renesas.com>
> Subject: RE: [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory
>
> Hi,
>
> > -----Original Message-----
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Sent: Monday, February 5, 2024 9:41 PM
> > To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 ○ＤＩＴＣ□
> > ＤＩＴ○ＯＳＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> > <pavel@denx.de>
> > Cc: Biju Das <biju.das.jz@bp.renesas.com>
> > Subject: [PATCH 5.10.y-cip 14/48] dma-mapping: simplify
> > dma_init_coherent_memory
> >
> > From: Christoph Hellwig <hch@lst.de>
> >
> > commit a6933571f34a9aee843fff2aa4b96949c57d6274 upstream.
> >
> > Return the allocated dma_coherent_mem structure, set the
> > use_dma_pfn_offset and print the failure warning inside of
> > dma_init_coherent_memory instead of leaving that to the callers.
> >
> > Signed-off-by: Christoph Hellwig <hch@lst.de>
> > Tested-by: Dillon Min <dillon.minfei@gmail.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > kernel/dma/coherent.c | 78
> > ++++++++++++++++++-------------------------
> > 1 file changed, 33 insertions(+), 45 deletions(-)
> >
>
> I can not apply this patch cip/Linux-5.10.y-cip.
> Could you check this ?
>
> $ git am -s patch.series
> Applying: arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS
> Applying: arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS
> Applying: arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt
> property
> Applying: arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels
> Applying: arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
> Applying: cacheinfo: clear cache_leaves(cpu) in free_cache_attributes()
> Applying: riscv: Kconfig: Enable cpufreq kconfig menu
> Applying: dma-direct: add support for dma_coherent_default_memory
> Applying: dma-mapping: allow using the global coherent pool for !ARM
> Applying: dma-mapping: simplify dma_init_coherent_memory
> error: patch failed: kernel/dma/coherent.c:37
> error: kernel/dma/coherent.c: patch does not apply Patch failed at 0010 dma-mapping: simplify
> dma_init_coherent_memory
> hint: Use 'git am --show-current-patch=diff' to see the failed patch When you have resolved this
> problem, run "git am --continue".
> If you prefer to skip this patch, run "git am --skip" instead.
> To restore the original branch and stop patching, run "git am --abort".
>
My patch series was based on v5.10.208-cip43, I'll rebase and send the v2 soon after testing.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory
2024-02-06 9:52 ` Prabhakar Mahadev Lad
@ 2024-02-06 10:12 ` Pavel Machek
2024-02-06 11:42 ` Prabhakar Mahadev Lad
0 siblings, 1 reply; 59+ messages in thread
From: Pavel Machek @ 2024-02-06 10:12 UTC (permalink / raw)
To: Prabhakar Mahadev Lad; +Cc: nobuhiro1.iwamatsu, cip-dev, pavel, Biju Das
[-- Attachment #1: Type: text/plain, Size: 1798 bytes --]
Hi!
> > I can not apply this patch cip/Linux-5.10.y-cip.
> > Could you check this ?
> >
> > $ git am -s patch.series
> > Applying: arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS
> > Applying: arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS
> > Applying: arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt
> > property
> > Applying: arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels
> > Applying: arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
> > Applying: cacheinfo: clear cache_leaves(cpu) in free_cache_attributes()
> > Applying: riscv: Kconfig: Enable cpufreq kconfig menu
> > Applying: dma-direct: add support for dma_coherent_default_memory
> > Applying: dma-mapping: allow using the global coherent pool for !ARM
> > Applying: dma-mapping: simplify dma_init_coherent_memory
> > error: patch failed: kernel/dma/coherent.c:37
> > error: kernel/dma/coherent.c: patch does not apply Patch failed at 0010 dma-mapping: simplify
> > dma_init_coherent_memory
> > hint: Use 'git am --show-current-patch=diff' to see the failed patch When you have resolved this
> > problem, run "git am --continue".
> > If you prefer to skip this patch, run "git am --skip" instead.
> > To restore the original branch and stop patching, run "git am --abort".
> >
> My patch series was based on v5.10.208-cip43, I'll rebase and send the v2 soon after testing.
That's a bad coincidence. Hopefully we won't have too many conflicts
in that code in future, as it looks a bit tricky.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 59+ messages in thread
* RE: [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory
2024-02-06 10:12 ` Pavel Machek
@ 2024-02-06 11:42 ` Prabhakar Mahadev Lad
0 siblings, 0 replies; 59+ messages in thread
From: Prabhakar Mahadev Lad @ 2024-02-06 11:42 UTC (permalink / raw)
To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, cip-dev, Biju Das
Hi Pavel,
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: Tuesday, February 6, 2024 10:13 AM
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: nobuhiro1.iwamatsu@toshiba.co.jp; cip-dev@lists.cip-project.org; pavel@denx.de; Biju Das
> <biju.das.jz@bp.renesas.com>
> Subject: Re: [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory
>
> Hi!
>
> > > I can not apply this patch cip/Linux-5.10.y-cip.
> > > Could you check this ?
> > >
> > > $ git am -s patch.series
> > > Applying: arm64: dts: renesas: rzg2ul-smarc: Move selecting
> > > PMOD_SCI0_EN to board DTS
> > > Applying: arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into
> > > board DTS
> > > Applying: arm64: dts: renesas: r9a07g043: Introduce
> > > SOC_PERIPHERAL_IRQ() macro to specify interrupt property
> > > Applying: arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI
> > > channels
> > > Applying: arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC
> > > specific parts
> > > Applying: cacheinfo: clear cache_leaves(cpu) in
> > > free_cache_attributes()
> > > Applying: riscv: Kconfig: Enable cpufreq kconfig menu
> > > Applying: dma-direct: add support for dma_coherent_default_memory
> > > Applying: dma-mapping: allow using the global coherent pool for !ARM
> > > Applying: dma-mapping: simplify dma_init_coherent_memory
> > > error: patch failed: kernel/dma/coherent.c:37
> > > error: kernel/dma/coherent.c: patch does not apply Patch failed at
> > > 0010 dma-mapping: simplify dma_init_coherent_memory
> > > hint: Use 'git am --show-current-patch=diff' to see the failed patch
> > > When you have resolved this problem, run "git am --continue".
> > > If you prefer to skip this patch, run "git am --skip" instead.
> > > To restore the original branch and stop patching, run "git am --abort".
> > >
> > My patch series was based on v5.10.208-cip43, I'll rebase and send the v2 soon after testing.
>
> That's a bad coincidence. Hopefully we won't have too many conflicts in that code in future, as it
> looks a bit tricky.
>
Agreed. Ive rebased the patches and kicked off the tests all seems to be OK. Ill send a v2.
Cheers,
Prabhakar
> Best regards,
> Pavel
> --
> DENX Software Engineering GmbH, Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 59+ messages in thread
end of thread, other threads:[~2024-02-06 11:42 UTC | newest]
Thread overview: 59+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-02-05 12:40 [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 01/48] ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names properties Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 02/48] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 03/48] arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 04/48] arm64: dts: renesas: r9a07g044: " Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 05/48] arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 06/48] arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into " Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 07/48] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 08/48] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 09/48] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 10/48] cacheinfo: clear cache_leaves(cpu) in free_cache_attributes() Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 11/48] riscv: Kconfig: Enable cpufreq kconfig menu Lad Prabhakar
2024-02-05 12:40 ` [PATCH 5.10.y-cip 12/48] dma-direct: add support for dma_coherent_default_memory Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 13/48] dma-mapping: allow using the global coherent pool for !ARM Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 14/48] dma-mapping: simplify dma_init_coherent_memory Lad Prabhakar
2024-02-06 9:18 ` nobuhiro1.iwamatsu
2024-02-06 9:52 ` Prabhakar Mahadev Lad
2024-02-06 10:12 ` Pavel Machek
2024-02-06 11:42 ` Prabhakar Mahadev Lad
2024-02-05 12:41 ` [PATCH 5.10.y-cip 15/48] dma-mapping: add a dma_init_global_coherent helper Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 16/48] dma-mapping: make the global coherent pool conditional Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 17/48] of: also handle dma-noncoherent in of_dma_is_coherent() Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 18/48] of/irq: Use interrupts-extended to find parent Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 19/48] irqchip/sifive-plic: Improve naming scheme for per context offsets Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 20/48] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 21/48] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 22/48] irqchip/sifive-plic: Make better use of the effective affinity mask Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 23/48] irqchip/sifive-plic: Separate the enable and mask operations Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 24/48] clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 25/48] clocksource/drivers/riscv: Increase the clock source rating Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 26/48] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 27/48] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_RENESAS Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 28/48] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 29/48] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 30/48] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 31/48] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 32/48] soc: renesas: Identify RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 33/48] clk: renesas: r9a07g043: Add support for " Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 34/48] cache: Add L2 cache management for Andes AX45MP RISC-V core Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 35/48] cache: ax45mp_cache: Add non coherent support Lad Prabhakar
2024-02-05 19:36 ` Pavel Machek
2024-02-05 12:41 ` [PATCH 5.10.y-cip 36/48] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 37/48] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 38/48] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 39/48] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 40/48] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 41/48] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 42/48] riscv: dts: renesas: rzfive-smarc-som: Enable WDT Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 43/48] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 44/48] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 45/48] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 46/48] riscv: dts: renesas: r9a07g043f: Add L2 cache node Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 47/48] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property Lad Prabhakar
2024-02-05 12:41 ` [PATCH 5.10.y-cip 48/48] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled Lad Prabhakar
2024-02-05 19:33 ` [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Pavel Machek
2024-02-06 8:20 ` nobuhiro1.iwamatsu
2024-02-06 8:29 ` Pavel Machek
2024-02-06 9:02 ` Prabhakar Mahadev Lad
2024-02-06 9:08 ` Pavel Machek
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