* [PATCH-for-9.0? 01/21] host/atomic128: Include missing 'qemu/atomic.h' header
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 17:05 ` Richard Henderson
2024-03-21 15:48 ` [PATCH-for-9.1 02/21] hw/core: Remove check on NEED_CPU_H in tcg-cpu-ops.h Philippe Mathieu-Daudé
` (19 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
qatomic_cmpxchg__nocheck(), qatomic_read__nocheck(),
qatomic_set__nocheck() are defined in "qemu/atomic.h".
Include it in order to avoid:
In file included from include/exec/helper-proto.h:10:
In file included from include/exec/helper-proto-common.h:10:
In file included from include/qemu/atomic128.h:61:
In file included from host/include/aarch64/host/atomic128-cas.h:16:
host/include/generic/host/atomic128-cas.h:23:11: error: call to undeclared function 'qatomic_cmpxchg__nocheck'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
r.i = qatomic_cmpxchg__nocheck(ptr_align, c.i, n.i);
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
host/include/generic/host/atomic128-cas.h | 2 ++
host/include/generic/host/atomic128-ldst.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/host/include/generic/host/atomic128-cas.h b/host/include/generic/host/atomic128-cas.h
index 6b40cc2271..4824f14659 100644
--- a/host/include/generic/host/atomic128-cas.h
+++ b/host/include/generic/host/atomic128-cas.h
@@ -11,6 +11,8 @@
#ifndef HOST_ATOMIC128_CAS_H
#define HOST_ATOMIC128_CAS_H
+#include "qemu/atomic.h"
+
#if defined(CONFIG_ATOMIC128)
static inline Int128 ATTRIBUTE_ATOMIC128_OPT
atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new)
diff --git a/host/include/generic/host/atomic128-ldst.h b/host/include/generic/host/atomic128-ldst.h
index 691e6a8531..12e4aca2da 100644
--- a/host/include/generic/host/atomic128-ldst.h
+++ b/host/include/generic/host/atomic128-ldst.h
@@ -11,6 +11,8 @@
#ifndef HOST_ATOMIC128_LDST_H
#define HOST_ATOMIC128_LDST_H
+#include "qemu/atomic.h"
+
#if defined(CONFIG_ATOMIC128)
# define HAVE_ATOMIC128_RO 1
# define HAVE_ATOMIC128_RW 1
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.0? 01/21] host/atomic128: Include missing 'qemu/atomic.h' header
2024-03-21 15:48 ` [PATCH-for-9.0? 01/21] host/atomic128: Include missing 'qemu/atomic.h' header Philippe Mathieu-Daudé
@ 2024-03-21 17:05 ` Richard Henderson
2024-04-23 13:54 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 46+ messages in thread
From: Richard Henderson @ 2024-03-21 17:05 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
On 3/21/24 05:48, Philippe Mathieu-Daudé wrote:
> qatomic_cmpxchg__nocheck(), qatomic_read__nocheck(),
> qatomic_set__nocheck() are defined in "qemu/atomic.h".
> Include it in order to avoid:
>
> In file included from include/exec/helper-proto.h:10:
> In file included from include/exec/helper-proto-common.h:10:
> In file included from include/qemu/atomic128.h:61:
> In file included from host/include/aarch64/host/atomic128-cas.h:16:
> host/include/generic/host/atomic128-cas.h:23:11: error: call to undeclared function 'qatomic_cmpxchg__nocheck'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
> r.i = qatomic_cmpxchg__nocheck(ptr_align, c.i, n.i);
Nak. We can rename these host/include/*/host/*atomic* as .h.inc if you need, but the
top-level header is include/qemu/atomic128.h.
r~
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH-for-9.0? 01/21] host/atomic128: Include missing 'qemu/atomic.h' header
2024-03-21 17:05 ` Richard Henderson
@ 2024-04-23 13:54 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-04-23 13:54 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 21/3/24 18:05, Richard Henderson wrote:
> On 3/21/24 05:48, Philippe Mathieu-Daudé wrote:
>> qatomic_cmpxchg__nocheck(), qatomic_read__nocheck(),
>> qatomic_set__nocheck() are defined in "qemu/atomic.h".
>> Include it in order to avoid:
>>
>> In file included from include/exec/helper-proto.h:10:
>> In file included from include/exec/helper-proto-common.h:10:
>> In file included from include/qemu/atomic128.h:61:
>> In file included from host/include/aarch64/host/atomic128-cas.h:16:
>> host/include/generic/host/atomic128-cas.h:23:11: error: call to
>> undeclared function 'qatomic_cmpxchg__nocheck'; ISO C99 and later do
>> not support implicit function declarations
>> [-Wimplicit-function-declaration]
>> r.i = qatomic_cmpxchg__nocheck(ptr_align, c.i, n.i);
>
>
> Nak. We can rename these host/include/*/host/*atomic* as .h.inc if you
> need, but the top-level header is include/qemu/atomic128.h.
Patch available here:
https://lore.kernel.org/qemu-devel/20240418160943.95047-3-philmd@linaro.org/
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH-for-9.1 02/21] hw/core: Remove check on NEED_CPU_H in tcg-cpu-ops.h
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
2024-03-21 15:48 ` [PATCH-for-9.0? 01/21] host/atomic128: Include missing 'qemu/atomic.h' header Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 21:17 ` Richard Henderson
2024-03-21 15:48 ` [PATCH-for-9.1 03/21] target/i386: Move APIC related code to cpu-apic.c Philippe Mathieu-Daudé
` (18 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Commit fd3f7d24d4 ("include/hw/core: Remove i386 conditional
on fake_user_interrupt") remove the need to check on NEED_CPU_H.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index bf8ff8e3ee..88857eb921 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -49,7 +49,6 @@ struct TCGCPUOps {
/** @debug_excp_handler: Callback for handling debug exceptions */
void (*debug_excp_handler)(CPUState *cpu);
-#ifdef NEED_CPU_H
#ifdef CONFIG_USER_ONLY
/**
* @fake_user_interrupt: Callback for 'fake exception' handling.
@@ -174,7 +173,6 @@ struct TCGCPUOps {
*/
bool (*need_replay_interrupt)(int interrupt_request);
#endif /* !CONFIG_USER_ONLY */
-#endif /* NEED_CPU_H */
};
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH-for-9.1 03/21] target/i386: Move APIC related code to cpu-apic.c
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
2024-03-21 15:48 ` [PATCH-for-9.0? 01/21] host/atomic128: Include missing 'qemu/atomic.h' header Philippe Mathieu-Daudé
2024-03-21 15:48 ` [PATCH-for-9.1 02/21] hw/core: Remove check on NEED_CPU_H in tcg-cpu-ops.h Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 21:43 ` Richard Henderson
2024-04-24 8:26 ` Zhao Liu
2024-03-21 15:48 ` [PATCH-for-9.1 04/21] target/i386: Extract x86_dump_mmu() from hmp_info_tlb() Philippe Mathieu-Daudé
` (17 subsequent siblings)
20 siblings, 2 replies; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Move APIC related code split in cpu-sysemu.c and
monitor.c to cpu-apic.c.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/i386/cpu-apic.c | 112 +++++++++++++++++++++++++++++++++++++++
target/i386/cpu-sysemu.c | 77 ---------------------------
target/i386/monitor.c | 25 ---------
target/i386/meson.build | 1 +
4 files changed, 113 insertions(+), 102 deletions(-)
create mode 100644 target/i386/cpu-apic.c
diff --git a/target/i386/cpu-apic.c b/target/i386/cpu-apic.c
new file mode 100644
index 0000000000..d397ec94dc
--- /dev/null
+++ b/target/i386/cpu-apic.c
@@ -0,0 +1,112 @@
+/*
+ * QEMU x86 CPU <-> APIC
+ *
+ * Copyright (c) 2003-2004 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/qmp/qdict.h"
+#include "qapi/error.h"
+#include "monitor/monitor.h"
+#include "monitor/hmp-target.h"
+#include "sysemu/hw_accel.h"
+#include "sysemu/kvm.h"
+#include "sysemu/xen.h"
+#include "exec/address-spaces.h"
+#include "hw/qdev-properties.h"
+#include "hw/i386/apic_internal.h"
+#include "cpu-internal.h"
+
+APICCommonClass *apic_get_class(Error **errp)
+{
+ const char *apic_type = "apic";
+
+ /* TODO: in-kernel irqchip for hvf */
+ if (kvm_enabled()) {
+ if (!kvm_irqchip_in_kernel()) {
+ error_setg(errp, "KVM does not support userspace APIC");
+ return NULL;
+ }
+ apic_type = "kvm-apic";
+ } else if (xen_enabled()) {
+ apic_type = "xen-apic";
+ } else if (whpx_apic_in_platform()) {
+ apic_type = "whpx-apic";
+ }
+
+ return APIC_COMMON_CLASS(object_class_by_name(apic_type));
+}
+
+void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
+{
+ APICCommonState *apic;
+ APICCommonClass *apic_class = apic_get_class(errp);
+
+ if (!apic_class) {
+ return;
+ }
+
+ cpu->apic_state = DEVICE(object_new_with_class(OBJECT_CLASS(apic_class)));
+ object_property_add_child(OBJECT(cpu), "lapic",
+ OBJECT(cpu->apic_state));
+ object_unref(OBJECT(cpu->apic_state));
+
+ /* TODO: convert to link<> */
+ apic = APIC_COMMON(cpu->apic_state);
+ apic->cpu = cpu;
+ apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
+
+ /*
+ * apic_common_set_id needs to check if the CPU has x2APIC
+ * feature in case APIC ID >= 255, so we need to set apic->cpu
+ * before setting APIC ID
+ */
+ qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
+}
+
+void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
+{
+ APICCommonState *apic;
+ static bool apic_mmio_map_once;
+
+ if (cpu->apic_state == NULL) {
+ return;
+ }
+ qdev_realize(DEVICE(cpu->apic_state), NULL, errp);
+
+ /* Map APIC MMIO area */
+ apic = APIC_COMMON(cpu->apic_state);
+ if (!apic_mmio_map_once) {
+ memory_region_add_subregion_overlap(get_system_memory(),
+ apic->apicbase &
+ MSR_IA32_APICBASE_BASE,
+ &apic->io_memory,
+ 0x1000);
+ apic_mmio_map_once = true;
+ }
+}
+
+void hmp_info_local_apic(Monitor *mon, const QDict *qdict)
+{
+ CPUState *cs;
+
+ if (qdict_haskey(qdict, "apic-id")) {
+ int id = qdict_get_try_int(qdict, "apic-id", 0);
+
+ cs = cpu_by_arch_id(id);
+ if (cs) {
+ cpu_synchronize_state(cs);
+ }
+ } else {
+ cs = mon_get_cpu(mon);
+ }
+
+
+ if (!cs) {
+ monitor_printf(mon, "No CPU available\n");
+ return;
+ }
+ x86_cpu_dump_local_apic_state(cs, CPU_DUMP_FPU);
+}
diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c
index 3f9093d285..227ac021f6 100644
--- a/target/i386/cpu-sysemu.c
+++ b/target/i386/cpu-sysemu.c
@@ -19,19 +19,12 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "sysemu/kvm.h"
-#include "sysemu/xen.h"
-#include "sysemu/whpx.h"
#include "qapi/error.h"
#include "qapi/qapi-visit-run-state.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qobject-input-visitor.h"
#include "qom/qom-qobject.h"
#include "qapi/qapi-commands-machine-target.h"
-#include "hw/qdev-properties.h"
-
-#include "exec/address-spaces.h"
-#include "hw/i386/apic_internal.h"
#include "cpu-internal.h"
@@ -273,75 +266,6 @@ void x86_cpu_machine_reset_cb(void *opaque)
cpu_reset(CPU(cpu));
}
-APICCommonClass *apic_get_class(Error **errp)
-{
- const char *apic_type = "apic";
-
- /* TODO: in-kernel irqchip for hvf */
- if (kvm_enabled()) {
- if (!kvm_irqchip_in_kernel()) {
- error_setg(errp, "KVM does not support userspace APIC");
- return NULL;
- }
- apic_type = "kvm-apic";
- } else if (xen_enabled()) {
- apic_type = "xen-apic";
- } else if (whpx_apic_in_platform()) {
- apic_type = "whpx-apic";
- }
-
- return APIC_COMMON_CLASS(object_class_by_name(apic_type));
-}
-
-void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
-{
- APICCommonState *apic;
- APICCommonClass *apic_class = apic_get_class(errp);
-
- if (!apic_class) {
- return;
- }
-
- cpu->apic_state = DEVICE(object_new_with_class(OBJECT_CLASS(apic_class)));
- object_property_add_child(OBJECT(cpu), "lapic",
- OBJECT(cpu->apic_state));
- object_unref(OBJECT(cpu->apic_state));
-
- /* TODO: convert to link<> */
- apic = APIC_COMMON(cpu->apic_state);
- apic->cpu = cpu;
- apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
-
- /*
- * apic_common_set_id needs to check if the CPU has x2APIC
- * feature in case APIC ID >= 255, so we need to set apic->cpu
- * before setting APIC ID
- */
- qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
-}
-
-void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
-{
- APICCommonState *apic;
- static bool apic_mmio_map_once;
-
- if (cpu->apic_state == NULL) {
- return;
- }
- qdev_realize(DEVICE(cpu->apic_state), NULL, errp);
-
- /* Map APIC MMIO area */
- apic = APIC_COMMON(cpu->apic_state);
- if (!apic_mmio_map_once) {
- memory_region_add_subregion_overlap(get_system_memory(),
- apic->apicbase &
- MSR_IA32_APICBASE_BASE,
- &apic->io_memory,
- 0x1000);
- apic_mmio_map_once = true;
- }
-}
-
GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
@@ -385,4 +309,3 @@ void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
errp);
qapi_free_GuestPanicInformation(panic_info);
}
-
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index 3a281dab02..2d766b2637 100644
--- a/target/i386/monitor.c
+++ b/target/i386/monitor.c
@@ -28,8 +28,6 @@
#include "monitor/hmp-target.h"
#include "monitor/hmp.h"
#include "qapi/qmp/qdict.h"
-#include "sysemu/hw_accel.h"
-#include "sysemu/kvm.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-misc-target.h"
#include "qapi/qapi-commands-misc.h"
@@ -647,26 +645,3 @@ const MonitorDef *target_monitor_defs(void)
{
return monitor_defs;
}
-
-void hmp_info_local_apic(Monitor *mon, const QDict *qdict)
-{
- CPUState *cs;
-
- if (qdict_haskey(qdict, "apic-id")) {
- int id = qdict_get_try_int(qdict, "apic-id", 0);
-
- cs = cpu_by_arch_id(id);
- if (cs) {
- cpu_synchronize_state(cs);
- }
- } else {
- cs = mon_get_cpu(mon);
- }
-
-
- if (!cs) {
- monitor_printf(mon, "No CPU available\n");
- return;
- }
- x86_cpu_dump_local_apic_state(cs, CPU_DUMP_FPU);
-}
diff --git a/target/i386/meson.build b/target/i386/meson.build
index 7c74bfa859..ba8dc68a34 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -18,6 +18,7 @@ i386_system_ss.add(files(
'arch_memory_mapping.c',
'machine.c',
'monitor.c',
+ 'cpu-apic.c',
'cpu-sysemu.c',
))
i386_system_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-sysemu-stub.c'))
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 03/21] target/i386: Move APIC related code to cpu-apic.c
2024-03-21 15:48 ` [PATCH-for-9.1 03/21] target/i386: Move APIC related code to cpu-apic.c Philippe Mathieu-Daudé
@ 2024-03-21 21:43 ` Richard Henderson
2024-04-24 8:26 ` Zhao Liu
1 sibling, 0 replies; 46+ messages in thread
From: Richard Henderson @ 2024-03-21 21:43 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
On 3/21/24 05:48, Philippe Mathieu-Daudé wrote:
> Move APIC related code split in cpu-sysemu.c and
> monitor.c to cpu-apic.c.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/i386/cpu-apic.c | 112 +++++++++++++++++++++++++++++++++++++++
> target/i386/cpu-sysemu.c | 77 ---------------------------
> target/i386/monitor.c | 25 ---------
> target/i386/meson.build | 1 +
> 4 files changed, 113 insertions(+), 102 deletions(-)
> create mode 100644 target/i386/cpu-apic.c
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH-for-9.1 03/21] target/i386: Move APIC related code to cpu-apic.c
2024-03-21 15:48 ` [PATCH-for-9.1 03/21] target/i386: Move APIC related code to cpu-apic.c Philippe Mathieu-Daudé
2024-03-21 21:43 ` Richard Henderson
@ 2024-04-24 8:26 ` Zhao Liu
2024-04-24 12:05 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 46+ messages in thread
From: Zhao Liu @ 2024-04-24 8:26 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland
On Thu, Mar 21, 2024 at 04:48:19PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Thu, 21 Mar 2024 16:48:19 +0100
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH-for-9.1 03/21] target/i386: Move APIC related code to
> cpu-apic.c
> X-Mailer: git-send-email 2.41.0
>
> Move APIC related code split in cpu-sysemu.c and
> monitor.c to cpu-apic.c.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/i386/cpu-apic.c | 112 +++++++++++++++++++++++++++++++++++++++
> target/i386/cpu-sysemu.c | 77 ---------------------------
> target/i386/monitor.c | 25 ---------
> target/i386/meson.build | 1 +
> 4 files changed, 113 insertions(+), 102 deletions(-)
> create mode 100644 target/i386/cpu-apic.c
>
> diff --git a/target/i386/cpu-apic.c b/target/i386/cpu-apic.c
> new file mode 100644
> index 0000000000..d397ec94dc
> --- /dev/null
> +++ b/target/i386/cpu-apic.c
Nit: New file needs a MAINTAINER entry ;-).
Others LGTM,
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH-for-9.1 03/21] target/i386: Move APIC related code to cpu-apic.c
2024-04-24 8:26 ` Zhao Liu
@ 2024-04-24 12:05 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-04-24 12:05 UTC (permalink / raw)
To: Zhao Liu
Cc: qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland
On 24/4/24 10:26, Zhao Liu wrote:
> On Thu, Mar 21, 2024 at 04:48:19PM +0100, Philippe Mathieu-Daudé wrote:
>> Date: Thu, 21 Mar 2024 16:48:19 +0100
>> From: Philippe Mathieu-Daudé <philmd@linaro.org>
>> Subject: [PATCH-for-9.1 03/21] target/i386: Move APIC related code to
>> cpu-apic.c
>> X-Mailer: git-send-email 2.41.0
>>
>> Move APIC related code split in cpu-sysemu.c and
>> monitor.c to cpu-apic.c.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> target/i386/cpu-apic.c | 112 +++++++++++++++++++++++++++++++++++++++
>> target/i386/cpu-sysemu.c | 77 ---------------------------
>> target/i386/monitor.c | 25 ---------
>> target/i386/meson.build | 1 +
>> 4 files changed, 113 insertions(+), 102 deletions(-)
>> create mode 100644 target/i386/cpu-apic.c
>>
>> diff --git a/target/i386/cpu-apic.c b/target/i386/cpu-apic.c
>> new file mode 100644
>> index 0000000000..d397ec94dc
>> --- /dev/null
>> +++ b/target/i386/cpu-apic.c
>
> Nit: New file needs a MAINTAINER entry ;-).
Already covered here:
X86 general architecture support
M: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: configs/devices/i386-softmmu/default.mak
F: configs/targets/i386-softmmu.mak
F: configs/targets/x86_64-softmmu.mak
F: docs/system/target-i386*
F: target/i386/*.[ch]
^^^^^^
$ ./scripts/get_maintainer.pl -f target/i386/cpu-apic.c
Paolo Bonzini <pbonzini@redhat.com> (maintainer:X86 general archi...)
qemu-devel@nongnu.org (open list:All patches CC here)
> Others LGTM,
>
> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Thanks!
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH-for-9.1 04/21] target/i386: Extract x86_dump_mmu() from hmp_info_tlb()
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 03/21] target/i386: Move APIC related code to cpu-apic.c Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 21:46 ` Richard Henderson
2024-03-21 15:48 ` [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
` (16 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
hmp_info_tlb() is specific to tcg/system, move it to
target/i386/tcg/sysemu/hmp-cmds.c, along with the functions
it depend on (except addr_canonical() which is exposed in
"cpu.h").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/i386/cpu.h | 7 ++
target/i386/mmu.c | 231 ++++++++++++++++++++++++++++++++++++++++
target/i386/monitor.c | 215 -------------------------------------
target/i386/meson.build | 1 +
4 files changed, 239 insertions(+), 215 deletions(-)
create mode 100644 target/i386/mmu.c
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 952174bb6f..055c5b99de 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2342,6 +2342,13 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
return mmu_index_base + mmu_index_32;
}
+#if !defined(CONFIG_USER_ONLY)
+void x86_dump_mmu(Monitor *mon, CPUX86State *env);
+
+/* Perform linear address sign extension */
+hwaddr addr_canonical(CPUArchState *env, hwaddr addr);
+#endif
+
#define CC_DST (env->cc_dst)
#define CC_SRC (env->cc_src)
#define CC_SRC2 (env->cc_src2)
diff --git a/target/i386/mmu.c b/target/i386/mmu.c
new file mode 100644
index 0000000000..da9b2263b4
--- /dev/null
+++ b/target/i386/mmu.c
@@ -0,0 +1,231 @@
+/*
+ * QEMU x86 MMU monitor commands
+ *
+ * Copyright (c) 2003-2004 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "qemu/osdep.h"
+#include "monitor/monitor.h"
+#include "monitor/hmp-target.h"
+#include "cpu.h"
+
+hwaddr addr_canonical(CPUArchState *env, hwaddr addr)
+{
+#ifdef TARGET_X86_64
+ if (env->cr[4] & CR4_LA57_MASK) {
+ if (addr & (1ULL << 56)) {
+ addr |= (hwaddr)-(1LL << 57);
+ }
+ } else {
+ if (addr & (1ULL << 47)) {
+ addr |= (hwaddr)-(1LL << 48);
+ }
+ }
+#endif
+ return addr;
+}
+
+static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr,
+ hwaddr pte, hwaddr mask)
+{
+ addr = addr_canonical(env, addr);
+
+ monitor_printf(mon, HWADDR_FMT_plx ": " HWADDR_FMT_plx
+ " %c%c%c%c%c%c%c%c%c\n",
+ addr,
+ pte & mask,
+ pte & PG_NX_MASK ? 'X' : '-',
+ pte & PG_GLOBAL_MASK ? 'G' : '-',
+ pte & PG_PSE_MASK ? 'P' : '-',
+ pte & PG_DIRTY_MASK ? 'D' : '-',
+ pte & PG_ACCESSED_MASK ? 'A' : '-',
+ pte & PG_PCD_MASK ? 'C' : '-',
+ pte & PG_PWT_MASK ? 'T' : '-',
+ pte & PG_USER_MASK ? 'U' : '-',
+ pte & PG_RW_MASK ? 'W' : '-');
+}
+
+static void tlb_info_32(Monitor *mon, CPUArchState *env)
+{
+ unsigned int l1, l2;
+ uint32_t pgd, pde, pte;
+
+ pgd = env->cr[3] & ~0xfff;
+ for(l1 = 0; l1 < 1024; l1++) {
+ cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
+ pde = le32_to_cpu(pde);
+ if (pde & PG_PRESENT_MASK) {
+ if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
+ /* 4M pages */
+ print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1));
+ } else {
+ for(l2 = 0; l2 < 1024; l2++) {
+ cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
+ pte = le32_to_cpu(pte);
+ if (pte & PG_PRESENT_MASK) {
+ print_pte(mon, env, (l1 << 22) + (l2 << 12),
+ pte & ~PG_PSE_MASK,
+ ~0xfff);
+ }
+ }
+ }
+ }
+ }
+}
+
+static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
+{
+ unsigned int l1, l2, l3;
+ uint64_t pdpe, pde, pte;
+ uint64_t pdp_addr, pd_addr, pt_addr;
+
+ pdp_addr = env->cr[3] & ~0x1f;
+ for (l1 = 0; l1 < 4; l1++) {
+ cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
+ pdpe = le64_to_cpu(pdpe);
+ if (pdpe & PG_PRESENT_MASK) {
+ pd_addr = pdpe & 0x3fffffffff000ULL;
+ for (l2 = 0; l2 < 512; l2++) {
+ cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
+ pde = le64_to_cpu(pde);
+ if (pde & PG_PRESENT_MASK) {
+ if (pde & PG_PSE_MASK) {
+ /* 2M pages with PAE, CR4.PSE is ignored */
+ print_pte(mon, env, (l1 << 30) + (l2 << 21), pde,
+ ~((hwaddr)(1 << 20) - 1));
+ } else {
+ pt_addr = pde & 0x3fffffffff000ULL;
+ for (l3 = 0; l3 < 512; l3++) {
+ cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
+ pte = le64_to_cpu(pte);
+ if (pte & PG_PRESENT_MASK) {
+ print_pte(mon, env, (l1 << 30) + (l2 << 21)
+ + (l3 << 12),
+ pte & ~PG_PSE_MASK,
+ ~(hwaddr)0xfff);
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+}
+
+#ifdef TARGET_X86_64
+static void tlb_info_la48(Monitor *mon, CPUArchState *env,
+ uint64_t l0, uint64_t pml4_addr)
+{
+ uint64_t l1, l2, l3, l4;
+ uint64_t pml4e, pdpe, pde, pte;
+ uint64_t pdp_addr, pd_addr, pt_addr;
+
+ for (l1 = 0; l1 < 512; l1++) {
+ cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
+ pml4e = le64_to_cpu(pml4e);
+ if (!(pml4e & PG_PRESENT_MASK)) {
+ continue;
+ }
+
+ pdp_addr = pml4e & 0x3fffffffff000ULL;
+ for (l2 = 0; l2 < 512; l2++) {
+ cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
+ pdpe = le64_to_cpu(pdpe);
+ if (!(pdpe & PG_PRESENT_MASK)) {
+ continue;
+ }
+
+ if (pdpe & PG_PSE_MASK) {
+ /* 1G pages, CR4.PSE is ignored */
+ print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30),
+ pdpe, 0x3ffffc0000000ULL);
+ continue;
+ }
+
+ pd_addr = pdpe & 0x3fffffffff000ULL;
+ for (l3 = 0; l3 < 512; l3++) {
+ cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
+ pde = le64_to_cpu(pde);
+ if (!(pde & PG_PRESENT_MASK)) {
+ continue;
+ }
+
+ if (pde & PG_PSE_MASK) {
+ /* 2M pages, CR4.PSE is ignored */
+ print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30) +
+ (l3 << 21), pde, 0x3ffffffe00000ULL);
+ continue;
+ }
+
+ pt_addr = pde & 0x3fffffffff000ULL;
+ for (l4 = 0; l4 < 512; l4++) {
+ cpu_physical_memory_read(pt_addr
+ + l4 * 8,
+ &pte, 8);
+ pte = le64_to_cpu(pte);
+ if (pte & PG_PRESENT_MASK) {
+ print_pte(mon, env, (l0 << 48) + (l1 << 39) +
+ (l2 << 30) + (l3 << 21) + (l4 << 12),
+ pte & ~PG_PSE_MASK, 0x3fffffffff000ULL);
+ }
+ }
+ }
+ }
+ }
+}
+
+static void tlb_info_la57(Monitor *mon, CPUArchState *env)
+{
+ uint64_t l0;
+ uint64_t pml5e;
+ uint64_t pml5_addr;
+
+ pml5_addr = env->cr[3] & 0x3fffffffff000ULL;
+ for (l0 = 0; l0 < 512; l0++) {
+ cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8);
+ pml5e = le64_to_cpu(pml5e);
+ if (pml5e & PG_PRESENT_MASK) {
+ tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL);
+ }
+ }
+}
+#endif /* TARGET_X86_64 */
+
+void x86_dump_mmu(Monitor *mon, CPUX86State *env)
+{
+ if (!(env->cr[0] & CR0_PG_MASK)) {
+ monitor_printf(mon, "PG disabled\n");
+ return;
+ }
+ if (env->cr[4] & CR4_PAE_MASK) {
+#ifdef TARGET_X86_64
+ if (env->hflags & HF_LMA_MASK) {
+ if (env->cr[4] & CR4_LA57_MASK) {
+ tlb_info_la57(mon, env);
+ } else {
+ tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL);
+ }
+ } else
+#endif
+ {
+ tlb_info_pae32(mon, env);
+ }
+ } else {
+ tlb_info_32(mon, env);
+ }
+}
+
+void hmp_info_tlb(Monitor *mon, const QDict *qdict)
+{
+ CPUArchState *env;
+
+ env = mon_get_cpu_env(mon);
+ if (!env) {
+ monitor_printf(mon, "No CPU available\n");
+ return;
+ }
+
+ x86_dump_mmu(mon, env);
+}
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index 2d766b2637..fa155ac3c9 100644
--- a/target/i386/monitor.c
+++ b/target/i386/monitor.c
@@ -32,221 +32,6 @@
#include "qapi/qapi-commands-misc-target.h"
#include "qapi/qapi-commands-misc.h"
-/* Perform linear address sign extension */
-static hwaddr addr_canonical(CPUArchState *env, hwaddr addr)
-{
-#ifdef TARGET_X86_64
- if (env->cr[4] & CR4_LA57_MASK) {
- if (addr & (1ULL << 56)) {
- addr |= (hwaddr)-(1LL << 57);
- }
- } else {
- if (addr & (1ULL << 47)) {
- addr |= (hwaddr)-(1LL << 48);
- }
- }
-#endif
- return addr;
-}
-
-static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr,
- hwaddr pte, hwaddr mask)
-{
- addr = addr_canonical(env, addr);
-
- monitor_printf(mon, HWADDR_FMT_plx ": " HWADDR_FMT_plx
- " %c%c%c%c%c%c%c%c%c\n",
- addr,
- pte & mask,
- pte & PG_NX_MASK ? 'X' : '-',
- pte & PG_GLOBAL_MASK ? 'G' : '-',
- pte & PG_PSE_MASK ? 'P' : '-',
- pte & PG_DIRTY_MASK ? 'D' : '-',
- pte & PG_ACCESSED_MASK ? 'A' : '-',
- pte & PG_PCD_MASK ? 'C' : '-',
- pte & PG_PWT_MASK ? 'T' : '-',
- pte & PG_USER_MASK ? 'U' : '-',
- pte & PG_RW_MASK ? 'W' : '-');
-}
-
-static void tlb_info_32(Monitor *mon, CPUArchState *env)
-{
- unsigned int l1, l2;
- uint32_t pgd, pde, pte;
-
- pgd = env->cr[3] & ~0xfff;
- for(l1 = 0; l1 < 1024; l1++) {
- cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
- pde = le32_to_cpu(pde);
- if (pde & PG_PRESENT_MASK) {
- if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
- /* 4M pages */
- print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1));
- } else {
- for(l2 = 0; l2 < 1024; l2++) {
- cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
- pte = le32_to_cpu(pte);
- if (pte & PG_PRESENT_MASK) {
- print_pte(mon, env, (l1 << 22) + (l2 << 12),
- pte & ~PG_PSE_MASK,
- ~0xfff);
- }
- }
- }
- }
- }
-}
-
-static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
-{
- unsigned int l1, l2, l3;
- uint64_t pdpe, pde, pte;
- uint64_t pdp_addr, pd_addr, pt_addr;
-
- pdp_addr = env->cr[3] & ~0x1f;
- for (l1 = 0; l1 < 4; l1++) {
- cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
- pdpe = le64_to_cpu(pdpe);
- if (pdpe & PG_PRESENT_MASK) {
- pd_addr = pdpe & 0x3fffffffff000ULL;
- for (l2 = 0; l2 < 512; l2++) {
- cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
- pde = le64_to_cpu(pde);
- if (pde & PG_PRESENT_MASK) {
- if (pde & PG_PSE_MASK) {
- /* 2M pages with PAE, CR4.PSE is ignored */
- print_pte(mon, env, (l1 << 30) + (l2 << 21), pde,
- ~((hwaddr)(1 << 20) - 1));
- } else {
- pt_addr = pde & 0x3fffffffff000ULL;
- for (l3 = 0; l3 < 512; l3++) {
- cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
- pte = le64_to_cpu(pte);
- if (pte & PG_PRESENT_MASK) {
- print_pte(mon, env, (l1 << 30) + (l2 << 21)
- + (l3 << 12),
- pte & ~PG_PSE_MASK,
- ~(hwaddr)0xfff);
- }
- }
- }
- }
- }
- }
- }
-}
-
-#ifdef TARGET_X86_64
-static void tlb_info_la48(Monitor *mon, CPUArchState *env,
- uint64_t l0, uint64_t pml4_addr)
-{
- uint64_t l1, l2, l3, l4;
- uint64_t pml4e, pdpe, pde, pte;
- uint64_t pdp_addr, pd_addr, pt_addr;
-
- for (l1 = 0; l1 < 512; l1++) {
- cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
- pml4e = le64_to_cpu(pml4e);
- if (!(pml4e & PG_PRESENT_MASK)) {
- continue;
- }
-
- pdp_addr = pml4e & 0x3fffffffff000ULL;
- for (l2 = 0; l2 < 512; l2++) {
- cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
- pdpe = le64_to_cpu(pdpe);
- if (!(pdpe & PG_PRESENT_MASK)) {
- continue;
- }
-
- if (pdpe & PG_PSE_MASK) {
- /* 1G pages, CR4.PSE is ignored */
- print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30),
- pdpe, 0x3ffffc0000000ULL);
- continue;
- }
-
- pd_addr = pdpe & 0x3fffffffff000ULL;
- for (l3 = 0; l3 < 512; l3++) {
- cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
- pde = le64_to_cpu(pde);
- if (!(pde & PG_PRESENT_MASK)) {
- continue;
- }
-
- if (pde & PG_PSE_MASK) {
- /* 2M pages, CR4.PSE is ignored */
- print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30) +
- (l3 << 21), pde, 0x3ffffffe00000ULL);
- continue;
- }
-
- pt_addr = pde & 0x3fffffffff000ULL;
- for (l4 = 0; l4 < 512; l4++) {
- cpu_physical_memory_read(pt_addr
- + l4 * 8,
- &pte, 8);
- pte = le64_to_cpu(pte);
- if (pte & PG_PRESENT_MASK) {
- print_pte(mon, env, (l0 << 48) + (l1 << 39) +
- (l2 << 30) + (l3 << 21) + (l4 << 12),
- pte & ~PG_PSE_MASK, 0x3fffffffff000ULL);
- }
- }
- }
- }
- }
-}
-
-static void tlb_info_la57(Monitor *mon, CPUArchState *env)
-{
- uint64_t l0;
- uint64_t pml5e;
- uint64_t pml5_addr;
-
- pml5_addr = env->cr[3] & 0x3fffffffff000ULL;
- for (l0 = 0; l0 < 512; l0++) {
- cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8);
- pml5e = le64_to_cpu(pml5e);
- if (pml5e & PG_PRESENT_MASK) {
- tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL);
- }
- }
-}
-#endif /* TARGET_X86_64 */
-
-void hmp_info_tlb(Monitor *mon, const QDict *qdict)
-{
- CPUArchState *env;
-
- env = mon_get_cpu_env(mon);
- if (!env) {
- monitor_printf(mon, "No CPU available\n");
- return;
- }
-
- if (!(env->cr[0] & CR0_PG_MASK)) {
- monitor_printf(mon, "PG disabled\n");
- return;
- }
- if (env->cr[4] & CR4_PAE_MASK) {
-#ifdef TARGET_X86_64
- if (env->hflags & HF_LMA_MASK) {
- if (env->cr[4] & CR4_LA57_MASK) {
- tlb_info_la57(mon, env);
- } else {
- tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL);
- }
- } else
-#endif
- {
- tlb_info_pae32(mon, env);
- }
- } else {
- tlb_info_32(mon, env);
- }
-}
-
static void mem_print(Monitor *mon, CPUArchState *env,
hwaddr *pstart, int *plast_prot,
hwaddr end, int prot)
diff --git a/target/i386/meson.build b/target/i386/meson.build
index ba8dc68a34..6c6f383e2e 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -18,6 +18,7 @@ i386_system_ss.add(files(
'arch_memory_mapping.c',
'machine.c',
'monitor.c',
+ 'mmu.c',
'cpu-apic.c',
'cpu-sysemu.c',
))
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 04/21] target/i386: Extract x86_dump_mmu() from hmp_info_tlb()
2024-03-21 15:48 ` [PATCH-for-9.1 04/21] target/i386: Extract x86_dump_mmu() from hmp_info_tlb() Philippe Mathieu-Daudé
@ 2024-03-21 21:46 ` Richard Henderson
0 siblings, 0 replies; 46+ messages in thread
From: Richard Henderson @ 2024-03-21 21:46 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
On 3/21/24 05:48, Philippe Mathieu-Daudé wrote:
> hmp_info_tlb() is specific to tcg/system, move it to
> target/i386/tcg/sysemu/hmp-cmds.c, along with the functions
> it depend on (except addr_canonical() which is exposed in
> "cpu.h").
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/i386/cpu.h | 7 ++
> target/i386/mmu.c | 231 ++++++++++++++++++++++++++++++++++++++++
> target/i386/monitor.c | 215 -------------------------------------
> target/i386/meson.build | 1 +
> 4 files changed, 239 insertions(+), 215 deletions(-)
> create mode 100644 target/i386/mmu.c
Patch commit message appears to be out of date wrt filename.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 04/21] target/i386: Extract x86_dump_mmu() from hmp_info_tlb() Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 21:49 ` Richard Henderson
` (2 more replies)
2024-03-21 15:48 ` [PATCH-for-9.1 06/21] target/m68k: Have dump_ttr() take a @description argument Philippe Mathieu-Daudé
` (15 subsequent siblings)
20 siblings, 3 replies; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/m68k/cpu.h | 2 +-
target/m68k/helper.c | 126 +++++++++++++++++++++---------------------
target/m68k/monitor.c | 4 +-
3 files changed, 67 insertions(+), 65 deletions(-)
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 346427e144..4e4307956d 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -620,6 +620,6 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc,
}
}
-void dump_mmu(CPUM68KState *env);
+void dump_mmu(Monitor *mon, CPUM68KState *env);
#endif
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 1a475f082a..310e26dfa1 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -25,7 +25,7 @@
#include "exec/helper-proto.h"
#include "gdbstub/helpers.h"
#include "fpu/softfloat.h"
-#include "qemu/qemu-print.h"
+#include "monitor/monitor.h"
#define SIGNBIT (1u << 31)
@@ -455,28 +455,30 @@ void m68k_switch_sp(CPUM68KState *env)
#if !defined(CONFIG_USER_ONLY)
/* MMU: 68040 only */
-static void print_address_zone(uint32_t logical, uint32_t physical,
+static void print_address_zone(Monitor *mon,
+ uint32_t logical, uint32_t physical,
uint32_t size, int attr)
{
- qemu_printf("%08x - %08x -> %08x - %08x %c ",
- logical, logical + size - 1,
- physical, physical + size - 1,
- attr & 4 ? 'W' : '-');
+ monitor_printf(mon, "%08x - %08x -> %08x - %08x %c ",
+ logical, logical + size - 1,
+ physical, physical + size - 1,
+ attr & 4 ? 'W' : '-');
size >>= 10;
if (size < 1024) {
- qemu_printf("(%d KiB)\n", size);
+ monitor_printf(mon, "(%d KiB)\n", size);
} else {
size >>= 10;
if (size < 1024) {
- qemu_printf("(%d MiB)\n", size);
+ monitor_printf(mon, "(%d MiB)\n", size);
} else {
size >>= 10;
- qemu_printf("(%d GiB)\n", size);
+ monitor_printf(mon, "(%d GiB)\n", size);
}
}
}
-static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
+static void dump_address_map(Monitor *mon, CPUM68KState *env,
+ uint32_t root_pointer)
{
int i, j, k;
int tic_size, tic_shift;
@@ -545,7 +547,7 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
if (first_logical != 0xffffffff) {
size = last_logical + (1 << tic_shift) -
first_logical;
- print_address_zone(first_logical,
+ print_address_zone(mon, first_logical,
first_physical, size, last_attr);
}
first_logical = logical;
@@ -556,125 +558,125 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
}
if (first_logical != logical || (attr & 4) != (last_attr & 4)) {
size = logical + (1 << tic_shift) - first_logical;
- print_address_zone(first_logical, first_physical, size, last_attr);
+ print_address_zone(mon, first_logical, first_physical, size, last_attr);
}
}
#define DUMP_CACHEFLAGS(a) \
switch (a & M68K_DESC_CACHEMODE) { \
case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \
- qemu_printf("T"); \
+ monitor_puts(mon, "T"); \
break; \
case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \
- qemu_printf("C"); \
+ monitor_puts(mon, "C"); \
break; \
case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \
- qemu_printf("S"); \
+ monitor_puts(mon, "S"); \
break; \
case M68K_DESC_CM_NCACHE: /* noncachable */ \
- qemu_printf("N"); \
+ monitor_puts(mon, "N"); \
break; \
}
-static void dump_ttr(uint32_t ttr)
+static void dump_ttr(Monitor *mon, uint32_t ttr)
{
if ((ttr & M68K_TTR_ENABLED) == 0) {
- qemu_printf("disabled\n");
+ monitor_puts(mon, "disabled\n");
return;
}
- qemu_printf("Base: 0x%08x Mask: 0x%08x Control: ",
- ttr & M68K_TTR_ADDR_BASE,
- (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
+ monitor_printf(mon, "Base: 0x%08x Mask: 0x%08x Control: ",
+ ttr & M68K_TTR_ADDR_BASE,
+ (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
switch (ttr & M68K_TTR_SFIELD) {
case M68K_TTR_SFIELD_USER:
- qemu_printf("U");
+ monitor_puts(mon, "U");
break;
case M68K_TTR_SFIELD_SUPER:
- qemu_printf("S");
+ monitor_puts(mon, "S");
break;
default:
- qemu_printf("*");
+ monitor_puts(mon, "*");
break;
}
DUMP_CACHEFLAGS(ttr);
if (ttr & M68K_DESC_WRITEPROT) {
- qemu_printf("R");
+ monitor_puts(mon, "R");
} else {
- qemu_printf("W");
+ monitor_puts(mon, "W");
}
- qemu_printf(" U: %d\n", (ttr & M68K_DESC_USERATTR) >>
+ monitor_printf(mon, " U: %d\n", (ttr & M68K_DESC_USERATTR) >>
M68K_DESC_USERATTR_SHIFT);
}
-void dump_mmu(CPUM68KState *env)
+void dump_mmu(Monitor *mon, CPUM68KState *env)
{
if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
- qemu_printf("Translation disabled\n");
+ monitor_puts(mon, "Translation disabled\n");
return;
}
- qemu_printf("Page Size: ");
+ monitor_puts(mon, "Page Size: ");
if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
- qemu_printf("8kB\n");
+ monitor_puts(mon, "8kB\n");
} else {
- qemu_printf("4kB\n");
+ monitor_puts(mon, "4kB\n");
}
- qemu_printf("MMUSR: ");
+ monitor_puts(mon, "MMUSR: ");
if (env->mmu.mmusr & M68K_MMU_B_040) {
- qemu_printf("BUS ERROR\n");
+ monitor_puts(mon, "BUS ERROR\n");
} else {
- qemu_printf("Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
+ monitor_printf(mon, "Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
/* flags found on the page descriptor */
if (env->mmu.mmusr & M68K_MMU_G_040) {
- qemu_printf("G"); /* Global */
+ monitor_puts(mon, "G"); /* Global */
} else {
- qemu_printf(".");
+ monitor_puts(mon, ".");
}
if (env->mmu.mmusr & M68K_MMU_S_040) {
- qemu_printf("S"); /* Supervisor */
+ monitor_puts(mon, "S"); /* Supervisor */
} else {
- qemu_printf(".");
+ monitor_puts(mon, ".");
}
if (env->mmu.mmusr & M68K_MMU_M_040) {
- qemu_printf("M"); /* Modified */
+ monitor_puts(mon, "M"); /* Modified */
} else {
- qemu_printf(".");
+ monitor_puts(mon, ".");
}
if (env->mmu.mmusr & M68K_MMU_WP_040) {
- qemu_printf("W"); /* Write protect */
+ monitor_puts(mon, "W"); /* Write protect */
} else {
- qemu_printf(".");
+ monitor_puts(mon, ".");
}
if (env->mmu.mmusr & M68K_MMU_T_040) {
- qemu_printf("T"); /* Transparent */
+ monitor_puts(mon, "T"); /* Transparent */
} else {
- qemu_printf(".");
+ monitor_puts(mon, ".");
}
if (env->mmu.mmusr & M68K_MMU_R_040) {
- qemu_printf("R"); /* Resident */
+ monitor_puts(mon, "R"); /* Resident */
} else {
- qemu_printf(".");
+ monitor_puts(mon, ".");
}
- qemu_printf(" Cache: ");
+ monitor_puts(mon, " Cache: ");
DUMP_CACHEFLAGS(env->mmu.mmusr);
- qemu_printf(" U: %d\n", (env->mmu.mmusr >> 8) & 3);
- qemu_printf("\n");
+ monitor_printf(mon, " U: %d\n", (env->mmu.mmusr >> 8) & 3);
+ monitor_puts(mon, "\n");
}
- qemu_printf("ITTR0: ");
- dump_ttr(env->mmu.ttr[M68K_ITTR0]);
- qemu_printf("ITTR1: ");
- dump_ttr(env->mmu.ttr[M68K_ITTR1]);
- qemu_printf("DTTR0: ");
- dump_ttr(env->mmu.ttr[M68K_DTTR0]);
- qemu_printf("DTTR1: ");
- dump_ttr(env->mmu.ttr[M68K_DTTR1]);
+ monitor_puts(mon, "ITTR0: ");
+ dump_ttr(mon, env->mmu.ttr[M68K_ITTR0]);
+ monitor_puts(mon, "ITTR1: ");
+ dump_ttr(mon, env->mmu.ttr[M68K_ITTR1]);
+ monitor_puts(mon, "DTTR0: ");
+ dump_ttr(mon, env->mmu.ttr[M68K_DTTR0]);
+ monitor_puts(mon, "DTTR1: ");
+ dump_ttr(mon, env->mmu.ttr[M68K_DTTR1]);
- qemu_printf("SRP: 0x%08x\n", env->mmu.srp);
- dump_address_map(env, env->mmu.srp);
+ monitor_printf(mon, "SRP: 0x%08x\n", env->mmu.srp);
+ dump_address_map(mon, env, env->mmu.srp);
- qemu_printf("URP: 0x%08x\n", env->mmu.urp);
- dump_address_map(env, env->mmu.urp);
+ monitor_printf(mon, "URP: 0x%08x\n", env->mmu.urp);
+ dump_address_map(mon, env, env->mmu.urp);
}
static int check_TTR(uint32_t ttr, int *prot, target_ulong addr,
diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c
index 2bdf6acae0..623c6ab635 100644
--- a/target/m68k/monitor.c
+++ b/target/m68k/monitor.c
@@ -15,11 +15,11 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
CPUArchState *env1 = mon_get_cpu_env(mon);
if (!env1) {
- monitor_printf(mon, "No CPU available\n");
+ monitor_puts(mon, "No CPU available\n");
return;
}
- dump_mmu(env1);
+ dump_mmu(mon, env1);
}
static const MonitorDef monitor_defs[] = {
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor
2024-03-21 15:48 ` [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
@ 2024-03-21 21:49 ` Richard Henderson
2024-03-24 23:43 ` Dr. David Alan Gilbert
2024-04-24 7:35 ` Markus Armbruster
2 siblings, 0 replies; 46+ messages in thread
From: Richard Henderson @ 2024-03-21 21:49 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
On 3/21/24 05:48, Philippe Mathieu-Daudé wrote:
> Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/m68k/cpu.h | 2 +-
> target/m68k/helper.c | 126 +++++++++++++++++++++---------------------
> target/m68k/monitor.c | 4 +-
> 3 files changed, 67 insertions(+), 65 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor
2024-03-21 15:48 ` [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
2024-03-21 21:49 ` Richard Henderson
@ 2024-03-24 23:43 ` Dr. David Alan Gilbert
2024-03-25 0:38 ` BALATON Zoltan
2024-04-24 7:35 ` Markus Armbruster
2 siblings, 1 reply; 46+ messages in thread
From: Dr. David Alan Gilbert @ 2024-03-24 23:43 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Jiaxun Yang, Nicholas Piggin,
Paolo Bonzini, Daniel Henrique Barboza, Yoshinori Sato,
Markus Armbruster, Richard Henderson, qemu-ppc, Laurent Vivier,
Mark Cave-Ayland
* Philippe Mathieu-Daudé (philmd@linaro.org) wrote:
> Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/m68k/cpu.h | 2 +-
> target/m68k/helper.c | 126 +++++++++++++++++++++---------------------
> target/m68k/monitor.c | 4 +-
> 3 files changed, 67 insertions(+), 65 deletions(-)
>
> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
> index 346427e144..4e4307956d 100644
> --- a/target/m68k/cpu.h
> +++ b/target/m68k/cpu.h
> @@ -620,6 +620,6 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc,
> }
> }
>
> -void dump_mmu(CPUM68KState *env);
> +void dump_mmu(Monitor *mon, CPUM68KState *env);
>
> #endif
> diff --git a/target/m68k/helper.c b/target/m68k/helper.c
> index 1a475f082a..310e26dfa1 100644
> --- a/target/m68k/helper.c
> +++ b/target/m68k/helper.c
> @@ -25,7 +25,7 @@
> #include "exec/helper-proto.h"
> #include "gdbstub/helpers.h"
> #include "fpu/softfloat.h"
> -#include "qemu/qemu-print.h"
> +#include "monitor/monitor.h"
>
> #define SIGNBIT (1u << 31)
>
> @@ -455,28 +455,30 @@ void m68k_switch_sp(CPUM68KState *env)
> #if !defined(CONFIG_USER_ONLY)
> /* MMU: 68040 only */
>
> -static void print_address_zone(uint32_t logical, uint32_t physical,
> +static void print_address_zone(Monitor *mon,
> + uint32_t logical, uint32_t physical,
> uint32_t size, int attr)
> {
> - qemu_printf("%08x - %08x -> %08x - %08x %c ",
> - logical, logical + size - 1,
> - physical, physical + size - 1,
> - attr & 4 ? 'W' : '-');
> + monitor_printf(mon, "%08x - %08x -> %08x - %08x %c ",
> + logical, logical + size - 1,
> + physical, physical + size - 1,
> + attr & 4 ? 'W' : '-');
> size >>= 10;
> if (size < 1024) {
> - qemu_printf("(%d KiB)\n", size);
> + monitor_printf(mon, "(%d KiB)\n", size);
> } else {
> size >>= 10;
> if (size < 1024) {
> - qemu_printf("(%d MiB)\n", size);
> + monitor_printf(mon, "(%d MiB)\n", size);
> } else {
> size >>= 10;
> - qemu_printf("(%d GiB)\n", size);
> + monitor_printf(mon, "(%d GiB)\n", size);
> }
> }
> }
>
> -static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
> +static void dump_address_map(Monitor *mon, CPUM68KState *env,
> + uint32_t root_pointer)
> {
> int i, j, k;
> int tic_size, tic_shift;
> @@ -545,7 +547,7 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
> if (first_logical != 0xffffffff) {
> size = last_logical + (1 << tic_shift) -
> first_logical;
> - print_address_zone(first_logical,
> + print_address_zone(mon, first_logical,
> first_physical, size, last_attr);
> }
> first_logical = logical;
> @@ -556,125 +558,125 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
> }
> if (first_logical != logical || (attr & 4) != (last_attr & 4)) {
> size = logical + (1 << tic_shift) - first_logical;
> - print_address_zone(first_logical, first_physical, size, last_attr);
> + print_address_zone(mon, first_logical, first_physical, size, last_attr);
> }
> }
>
> #define DUMP_CACHEFLAGS(a) \
> switch (a & M68K_DESC_CACHEMODE) { \
> case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \
> - qemu_printf("T"); \
> + monitor_puts(mon, "T"); \
> break; \
> case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \
> - qemu_printf("C"); \
> + monitor_puts(mon, "C"); \
> break; \
> case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \
> - qemu_printf("S"); \
> + monitor_puts(mon, "S"); \
> break; \
> case M68K_DESC_CM_NCACHE: /* noncachable */ \
> - qemu_printf("N"); \
> + monitor_puts(mon, "N"); \
> break; \
> }
>
> -static void dump_ttr(uint32_t ttr)
> +static void dump_ttr(Monitor *mon, uint32_t ttr)
> {
> if ((ttr & M68K_TTR_ENABLED) == 0) {
> - qemu_printf("disabled\n");
> + monitor_puts(mon, "disabled\n");
> return;
> }
> - qemu_printf("Base: 0x%08x Mask: 0x%08x Control: ",
> - ttr & M68K_TTR_ADDR_BASE,
> - (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
> + monitor_printf(mon, "Base: 0x%08x Mask: 0x%08x Control: ",
> + ttr & M68K_TTR_ADDR_BASE,
> + (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
> switch (ttr & M68K_TTR_SFIELD) {
> case M68K_TTR_SFIELD_USER:
> - qemu_printf("U");
> + monitor_puts(mon, "U");
> break;
> case M68K_TTR_SFIELD_SUPER:
> - qemu_printf("S");
> + monitor_puts(mon, "S");
> break;
> default:
> - qemu_printf("*");
> + monitor_puts(mon, "*");
> break;
> }
> DUMP_CACHEFLAGS(ttr);
> if (ttr & M68K_DESC_WRITEPROT) {
> - qemu_printf("R");
> + monitor_puts(mon, "R");
> } else {
> - qemu_printf("W");
> + monitor_puts(mon, "W");
> }
> - qemu_printf(" U: %d\n", (ttr & M68K_DESC_USERATTR) >>
> + monitor_printf(mon, " U: %d\n", (ttr & M68K_DESC_USERATTR) >>
> M68K_DESC_USERATTR_SHIFT);
> }
>
> -void dump_mmu(CPUM68KState *env)
> +void dump_mmu(Monitor *mon, CPUM68KState *env)
> {
> if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
> - qemu_printf("Translation disabled\n");
> + monitor_puts(mon, "Translation disabled\n");
> return;
> }
> - qemu_printf("Page Size: ");
> + monitor_puts(mon, "Page Size: ");
> if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
> - qemu_printf("8kB\n");
> + monitor_puts(mon, "8kB\n");
> } else {
> - qemu_printf("4kB\n");
> + monitor_puts(mon, "4kB\n");
> }
>
> - qemu_printf("MMUSR: ");
> + monitor_puts(mon, "MMUSR: ");
> if (env->mmu.mmusr & M68K_MMU_B_040) {
> - qemu_printf("BUS ERROR\n");
> + monitor_puts(mon, "BUS ERROR\n");
> } else {
> - qemu_printf("Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
> + monitor_printf(mon, "Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
> /* flags found on the page descriptor */
> if (env->mmu.mmusr & M68K_MMU_G_040) {
> - qemu_printf("G"); /* Global */
> + monitor_puts(mon, "G"); /* Global */
> } else {
> - qemu_printf(".");
> + monitor_puts(mon, ".");
> }
> if (env->mmu.mmusr & M68K_MMU_S_040) {
> - qemu_printf("S"); /* Supervisor */
> + monitor_puts(mon, "S"); /* Supervisor */
> } else {
> - qemu_printf(".");
> + monitor_puts(mon, ".");
> }
> if (env->mmu.mmusr & M68K_MMU_M_040) {
> - qemu_printf("M"); /* Modified */
> + monitor_puts(mon, "M"); /* Modified */
> } else {
> - qemu_printf(".");
> + monitor_puts(mon, ".");
> }
> if (env->mmu.mmusr & M68K_MMU_WP_040) {
> - qemu_printf("W"); /* Write protect */
> + monitor_puts(mon, "W"); /* Write protect */
> } else {
> - qemu_printf(".");
> + monitor_puts(mon, ".");
> }
> if (env->mmu.mmusr & M68K_MMU_T_040) {
> - qemu_printf("T"); /* Transparent */
> + monitor_puts(mon, "T"); /* Transparent */
> } else {
> - qemu_printf(".");
> + monitor_puts(mon, ".");
> }
> if (env->mmu.mmusr & M68K_MMU_R_040) {
> - qemu_printf("R"); /* Resident */
> + monitor_puts(mon, "R"); /* Resident */
> } else {
> - qemu_printf(".");
> + monitor_puts(mon, ".");
> }
> - qemu_printf(" Cache: ");
> + monitor_puts(mon, " Cache: ");
> DUMP_CACHEFLAGS(env->mmu.mmusr);
> - qemu_printf(" U: %d\n", (env->mmu.mmusr >> 8) & 3);
> - qemu_printf("\n");
> + monitor_printf(mon, " U: %d\n", (env->mmu.mmusr >> 8) & 3);
> + monitor_puts(mon, "\n");
That one is a little odd isn't it; still, generally
Reviewed-by: Dr. David Alan Gilbert <dave@treblig.org>
> }
>
> - qemu_printf("ITTR0: ");
> - dump_ttr(env->mmu.ttr[M68K_ITTR0]);
> - qemu_printf("ITTR1: ");
> - dump_ttr(env->mmu.ttr[M68K_ITTR1]);
> - qemu_printf("DTTR0: ");
> - dump_ttr(env->mmu.ttr[M68K_DTTR0]);
> - qemu_printf("DTTR1: ");
> - dump_ttr(env->mmu.ttr[M68K_DTTR1]);
> + monitor_puts(mon, "ITTR0: ");
> + dump_ttr(mon, env->mmu.ttr[M68K_ITTR0]);
> + monitor_puts(mon, "ITTR1: ");
> + dump_ttr(mon, env->mmu.ttr[M68K_ITTR1]);
> + monitor_puts(mon, "DTTR0: ");
> + dump_ttr(mon, env->mmu.ttr[M68K_DTTR0]);
> + monitor_puts(mon, "DTTR1: ");
> + dump_ttr(mon, env->mmu.ttr[M68K_DTTR1]);
>
> - qemu_printf("SRP: 0x%08x\n", env->mmu.srp);
> - dump_address_map(env, env->mmu.srp);
> + monitor_printf(mon, "SRP: 0x%08x\n", env->mmu.srp);
> + dump_address_map(mon, env, env->mmu.srp);
>
> - qemu_printf("URP: 0x%08x\n", env->mmu.urp);
> - dump_address_map(env, env->mmu.urp);
> + monitor_printf(mon, "URP: 0x%08x\n", env->mmu.urp);
> + dump_address_map(mon, env, env->mmu.urp);
> }
>
> static int check_TTR(uint32_t ttr, int *prot, target_ulong addr,
> diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c
> index 2bdf6acae0..623c6ab635 100644
> --- a/target/m68k/monitor.c
> +++ b/target/m68k/monitor.c
> @@ -15,11 +15,11 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
> CPUArchState *env1 = mon_get_cpu_env(mon);
>
> if (!env1) {
> - monitor_printf(mon, "No CPU available\n");
> + monitor_puts(mon, "No CPU available\n");
> return;
> }
>
> - dump_mmu(env1);
> + dump_mmu(mon, env1);
> }
>
> static const MonitorDef monitor_defs[] = {
> --
> 2.41.0
>
--
-----Open up your eyes, open up your mind, open up your code -------
/ Dr. David Alan Gilbert | Running GNU/Linux | Happy \
\ dave @ treblig.org | | In Hex /
\ _________________________|_____ http://www.treblig.org |_______/
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor
2024-03-24 23:43 ` Dr. David Alan Gilbert
@ 2024-03-25 0:38 ` BALATON Zoltan
2024-03-28 21:59 ` Dr. David Alan Gilbert
0 siblings, 1 reply; 46+ messages in thread
From: BALATON Zoltan @ 2024-03-25 0:38 UTC (permalink / raw)
To: Dr. David Alan Gilbert
Cc: Philippe Mathieu-Daudé,
qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Jiaxun Yang, Nicholas Piggin,
Paolo Bonzini, Daniel Henrique Barboza, Yoshinori Sato,
Markus Armbruster, Richard Henderson, qemu-ppc, Laurent Vivier,
Mark Cave-Ayland
[-- Attachment #1: Type: text/plain, Size: 10826 bytes --]
On Sun, 24 Mar 2024, Dr. David Alan Gilbert wrote:
> * Philippe Mathieu-Daudé (philmd@linaro.org) wrote:
>> Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> target/m68k/cpu.h | 2 +-
>> target/m68k/helper.c | 126 +++++++++++++++++++++---------------------
>> target/m68k/monitor.c | 4 +-
>> 3 files changed, 67 insertions(+), 65 deletions(-)
>>
>> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
>> index 346427e144..4e4307956d 100644
>> --- a/target/m68k/cpu.h
>> +++ b/target/m68k/cpu.h
>> @@ -620,6 +620,6 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc,
>> }
>> }
>>
>> -void dump_mmu(CPUM68KState *env);
>> +void dump_mmu(Monitor *mon, CPUM68KState *env);
>>
>> #endif
>> diff --git a/target/m68k/helper.c b/target/m68k/helper.c
>> index 1a475f082a..310e26dfa1 100644
>> --- a/target/m68k/helper.c
>> +++ b/target/m68k/helper.c
>> @@ -25,7 +25,7 @@
>> #include "exec/helper-proto.h"
>> #include "gdbstub/helpers.h"
>> #include "fpu/softfloat.h"
>> -#include "qemu/qemu-print.h"
>> +#include "monitor/monitor.h"
>>
>> #define SIGNBIT (1u << 31)
>>
>> @@ -455,28 +455,30 @@ void m68k_switch_sp(CPUM68KState *env)
>> #if !defined(CONFIG_USER_ONLY)
>> /* MMU: 68040 only */
>>
>> -static void print_address_zone(uint32_t logical, uint32_t physical,
>> +static void print_address_zone(Monitor *mon,
>> + uint32_t logical, uint32_t physical,
>> uint32_t size, int attr)
>> {
>> - qemu_printf("%08x - %08x -> %08x - %08x %c ",
>> - logical, logical + size - 1,
>> - physical, physical + size - 1,
>> - attr & 4 ? 'W' : '-');
>> + monitor_printf(mon, "%08x - %08x -> %08x - %08x %c ",
>> + logical, logical + size - 1,
>> + physical, physical + size - 1,
>> + attr & 4 ? 'W' : '-');
>> size >>= 10;
>> if (size < 1024) {
>> - qemu_printf("(%d KiB)\n", size);
>> + monitor_printf(mon, "(%d KiB)\n", size);
>> } else {
>> size >>= 10;
>> if (size < 1024) {
>> - qemu_printf("(%d MiB)\n", size);
>> + monitor_printf(mon, "(%d MiB)\n", size);
>> } else {
>> size >>= 10;
>> - qemu_printf("(%d GiB)\n", size);
>> + monitor_printf(mon, "(%d GiB)\n", size);
>> }
>> }
>> }
>>
>> -static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
>> +static void dump_address_map(Monitor *mon, CPUM68KState *env,
>> + uint32_t root_pointer)
>> {
>> int i, j, k;
>> int tic_size, tic_shift;
>> @@ -545,7 +547,7 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
>> if (first_logical != 0xffffffff) {
>> size = last_logical + (1 << tic_shift) -
>> first_logical;
>> - print_address_zone(first_logical,
>> + print_address_zone(mon, first_logical,
>> first_physical, size, last_attr);
>> }
>> first_logical = logical;
>> @@ -556,125 +558,125 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
>> }
>> if (first_logical != logical || (attr & 4) != (last_attr & 4)) {
>> size = logical + (1 << tic_shift) - first_logical;
>> - print_address_zone(first_logical, first_physical, size, last_attr);
>> + print_address_zone(mon, first_logical, first_physical, size, last_attr);
>> }
>> }
>>
>> #define DUMP_CACHEFLAGS(a) \
>> switch (a & M68K_DESC_CACHEMODE) { \
>> case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \
>> - qemu_printf("T"); \
>> + monitor_puts(mon, "T"); \
>> break; \
>> case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \
>> - qemu_printf("C"); \
>> + monitor_puts(mon, "C"); \
>> break; \
>> case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \
>> - qemu_printf("S"); \
>> + monitor_puts(mon, "S"); \
>> break; \
>> case M68K_DESC_CM_NCACHE: /* noncachable */ \
>> - qemu_printf("N"); \
>> + monitor_puts(mon, "N"); \
>> break; \
>> }
>>
>> -static void dump_ttr(uint32_t ttr)
>> +static void dump_ttr(Monitor *mon, uint32_t ttr)
>> {
>> if ((ttr & M68K_TTR_ENABLED) == 0) {
>> - qemu_printf("disabled\n");
>> + monitor_puts(mon, "disabled\n");
>> return;
>> }
>> - qemu_printf("Base: 0x%08x Mask: 0x%08x Control: ",
>> - ttr & M68K_TTR_ADDR_BASE,
>> - (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
>> + monitor_printf(mon, "Base: 0x%08x Mask: 0x%08x Control: ",
>> + ttr & M68K_TTR_ADDR_BASE,
>> + (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
>> switch (ttr & M68K_TTR_SFIELD) {
>> case M68K_TTR_SFIELD_USER:
>> - qemu_printf("U");
>> + monitor_puts(mon, "U");
>> break;
>> case M68K_TTR_SFIELD_SUPER:
>> - qemu_printf("S");
>> + monitor_puts(mon, "S");
>> break;
>> default:
>> - qemu_printf("*");
>> + monitor_puts(mon, "*");
>> break;
>> }
>> DUMP_CACHEFLAGS(ttr);
>> if (ttr & M68K_DESC_WRITEPROT) {
>> - qemu_printf("R");
>> + monitor_puts(mon, "R");
>> } else {
>> - qemu_printf("W");
>> + monitor_puts(mon, "W");
>> }
>> - qemu_printf(" U: %d\n", (ttr & M68K_DESC_USERATTR) >>
>> + monitor_printf(mon, " U: %d\n", (ttr & M68K_DESC_USERATTR) >>
>> M68K_DESC_USERATTR_SHIFT);
>> }
>>
>> -void dump_mmu(CPUM68KState *env)
>> +void dump_mmu(Monitor *mon, CPUM68KState *env)
>> {
>> if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
>> - qemu_printf("Translation disabled\n");
>> + monitor_puts(mon, "Translation disabled\n");
>> return;
>> }
>> - qemu_printf("Page Size: ");
>> + monitor_puts(mon, "Page Size: ");
>> if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
>> - qemu_printf("8kB\n");
>> + monitor_puts(mon, "8kB\n");
>> } else {
>> - qemu_printf("4kB\n");
>> + monitor_puts(mon, "4kB\n");
>> }
>>
>> - qemu_printf("MMUSR: ");
>> + monitor_puts(mon, "MMUSR: ");
>> if (env->mmu.mmusr & M68K_MMU_B_040) {
>> - qemu_printf("BUS ERROR\n");
>> + monitor_puts(mon, "BUS ERROR\n");
>> } else {
>> - qemu_printf("Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
>> + monitor_printf(mon, "Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
>> /* flags found on the page descriptor */
>> if (env->mmu.mmusr & M68K_MMU_G_040) {
>> - qemu_printf("G"); /* Global */
>> + monitor_puts(mon, "G"); /* Global */
>> } else {
>> - qemu_printf(".");
>> + monitor_puts(mon, ".");
>> }
>> if (env->mmu.mmusr & M68K_MMU_S_040) {
>> - qemu_printf("S"); /* Supervisor */
>> + monitor_puts(mon, "S"); /* Supervisor */
>> } else {
>> - qemu_printf(".");
>> + monitor_puts(mon, ".");
>> }
>> if (env->mmu.mmusr & M68K_MMU_M_040) {
>> - qemu_printf("M"); /* Modified */
>> + monitor_puts(mon, "M"); /* Modified */
>> } else {
>> - qemu_printf(".");
>> + monitor_puts(mon, ".");
>> }
>> if (env->mmu.mmusr & M68K_MMU_WP_040) {
>> - qemu_printf("W"); /* Write protect */
>> + monitor_puts(mon, "W"); /* Write protect */
>> } else {
>> - qemu_printf(".");
>> + monitor_puts(mon, ".");
>> }
>> if (env->mmu.mmusr & M68K_MMU_T_040) {
>> - qemu_printf("T"); /* Transparent */
>> + monitor_puts(mon, "T"); /* Transparent */
>> } else {
>> - qemu_printf(".");
>> + monitor_puts(mon, ".");
>> }
>> if (env->mmu.mmusr & M68K_MMU_R_040) {
>> - qemu_printf("R"); /* Resident */
>> + monitor_puts(mon, "R"); /* Resident */
>> } else {
>> - qemu_printf(".");
>> + monitor_puts(mon, ".");
>> }
>> - qemu_printf(" Cache: ");
>> + monitor_puts(mon, " Cache: ");
>> DUMP_CACHEFLAGS(env->mmu.mmusr);
>> - qemu_printf(" U: %d\n", (env->mmu.mmusr >> 8) & 3);
>> - qemu_printf("\n");
>> + monitor_printf(mon, " U: %d\n", (env->mmu.mmusr >> 8) & 3);
>> + monitor_puts(mon, "\n");
>
> That one is a little odd isn't it; still, generally
Doesn't puts append a newline? Then this would add an extra empty line.
Regards,
BALATON Zoltan
> Reviewed-by: Dr. David Alan Gilbert <dave@treblig.org>
>
>> }
>>
>> - qemu_printf("ITTR0: ");
>> - dump_ttr(env->mmu.ttr[M68K_ITTR0]);
>> - qemu_printf("ITTR1: ");
>> - dump_ttr(env->mmu.ttr[M68K_ITTR1]);
>> - qemu_printf("DTTR0: ");
>> - dump_ttr(env->mmu.ttr[M68K_DTTR0]);
>> - qemu_printf("DTTR1: ");
>> - dump_ttr(env->mmu.ttr[M68K_DTTR1]);
>> + monitor_puts(mon, "ITTR0: ");
>> + dump_ttr(mon, env->mmu.ttr[M68K_ITTR0]);
>> + monitor_puts(mon, "ITTR1: ");
>> + dump_ttr(mon, env->mmu.ttr[M68K_ITTR1]);
>> + monitor_puts(mon, "DTTR0: ");
>> + dump_ttr(mon, env->mmu.ttr[M68K_DTTR0]);
>> + monitor_puts(mon, "DTTR1: ");
>> + dump_ttr(mon, env->mmu.ttr[M68K_DTTR1]);
>>
>> - qemu_printf("SRP: 0x%08x\n", env->mmu.srp);
>> - dump_address_map(env, env->mmu.srp);
>> + monitor_printf(mon, "SRP: 0x%08x\n", env->mmu.srp);
>> + dump_address_map(mon, env, env->mmu.srp);
>>
>> - qemu_printf("URP: 0x%08x\n", env->mmu.urp);
>> - dump_address_map(env, env->mmu.urp);
>> + monitor_printf(mon, "URP: 0x%08x\n", env->mmu.urp);
>> + dump_address_map(mon, env, env->mmu.urp);
>> }
>>
>> static int check_TTR(uint32_t ttr, int *prot, target_ulong addr,
>> diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c
>> index 2bdf6acae0..623c6ab635 100644
>> --- a/target/m68k/monitor.c
>> +++ b/target/m68k/monitor.c
>> @@ -15,11 +15,11 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
>> CPUArchState *env1 = mon_get_cpu_env(mon);
>>
>> if (!env1) {
>> - monitor_printf(mon, "No CPU available\n");
>> + monitor_puts(mon, "No CPU available\n");
>> return;
>> }
>>
>> - dump_mmu(env1);
>> + dump_mmu(mon, env1);
>> }
>>
>> static const MonitorDef monitor_defs[] = {
>> --
>> 2.41.0
>>
>
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor
2024-03-25 0:38 ` BALATON Zoltan
@ 2024-03-28 21:59 ` Dr. David Alan Gilbert
2024-03-28 22:29 ` BALATON Zoltan
0 siblings, 1 reply; 46+ messages in thread
From: Dr. David Alan Gilbert @ 2024-03-28 21:59 UTC (permalink / raw)
To: BALATON Zoltan
Cc: Philippe Mathieu-Daudé,
qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Jiaxun Yang, Nicholas Piggin,
Paolo Bonzini, Daniel Henrique Barboza, Yoshinori Sato,
Markus Armbruster, Richard Henderson, qemu-ppc, Laurent Vivier,
Mark Cave-Ayland
* BALATON Zoltan (balaton@eik.bme.hu) wrote:
> On Sun, 24 Mar 2024, Dr. David Alan Gilbert wrote:
> > * Philippe Mathieu-Daudé (philmd@linaro.org) wrote:
> > > Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
> > >
> > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> > > ---
> > > target/m68k/cpu.h | 2 +-
> > > target/m68k/helper.c | 126 +++++++++++++++++++++---------------------
> > > target/m68k/monitor.c | 4 +-
> > > 3 files changed, 67 insertions(+), 65 deletions(-)
> > >
> > > diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
> > > index 346427e144..4e4307956d 100644
> > > --- a/target/m68k/cpu.h
> > > +++ b/target/m68k/cpu.h
> > > @@ -620,6 +620,6 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc,
> > > }
> > > }
> > >
> > > -void dump_mmu(CPUM68KState *env);
> > > +void dump_mmu(Monitor *mon, CPUM68KState *env);
> > >
> > > #endif
> > > diff --git a/target/m68k/helper.c b/target/m68k/helper.c
> > > index 1a475f082a..310e26dfa1 100644
> > > --- a/target/m68k/helper.c
> > > +++ b/target/m68k/helper.c
> > > @@ -25,7 +25,7 @@
> > > #include "exec/helper-proto.h"
> > > #include "gdbstub/helpers.h"
> > > #include "fpu/softfloat.h"
> > > -#include "qemu/qemu-print.h"
> > > +#include "monitor/monitor.h"
> > >
> > > #define SIGNBIT (1u << 31)
> > >
> > > @@ -455,28 +455,30 @@ void m68k_switch_sp(CPUM68KState *env)
> > > #if !defined(CONFIG_USER_ONLY)
> > > /* MMU: 68040 only */
> > >
> > > -static void print_address_zone(uint32_t logical, uint32_t physical,
> > > +static void print_address_zone(Monitor *mon,
> > > + uint32_t logical, uint32_t physical,
> > > uint32_t size, int attr)
> > > {
> > > - qemu_printf("%08x - %08x -> %08x - %08x %c ",
> > > - logical, logical + size - 1,
> > > - physical, physical + size - 1,
> > > - attr & 4 ? 'W' : '-');
> > > + monitor_printf(mon, "%08x - %08x -> %08x - %08x %c ",
> > > + logical, logical + size - 1,
> > > + physical, physical + size - 1,
> > > + attr & 4 ? 'W' : '-');
> > > size >>= 10;
> > > if (size < 1024) {
> > > - qemu_printf("(%d KiB)\n", size);
> > > + monitor_printf(mon, "(%d KiB)\n", size);
> > > } else {
> > > size >>= 10;
> > > if (size < 1024) {
> > > - qemu_printf("(%d MiB)\n", size);
> > > + monitor_printf(mon, "(%d MiB)\n", size);
> > > } else {
> > > size >>= 10;
> > > - qemu_printf("(%d GiB)\n", size);
> > > + monitor_printf(mon, "(%d GiB)\n", size);
> > > }
> > > }
> > > }
> > >
> > > -static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
> > > +static void dump_address_map(Monitor *mon, CPUM68KState *env,
> > > + uint32_t root_pointer)
> > > {
> > > int i, j, k;
> > > int tic_size, tic_shift;
> > > @@ -545,7 +547,7 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
> > > if (first_logical != 0xffffffff) {
> > > size = last_logical + (1 << tic_shift) -
> > > first_logical;
> > > - print_address_zone(first_logical,
> > > + print_address_zone(mon, first_logical,
> > > first_physical, size, last_attr);
> > > }
> > > first_logical = logical;
> > > @@ -556,125 +558,125 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
> > > }
> > > if (first_logical != logical || (attr & 4) != (last_attr & 4)) {
> > > size = logical + (1 << tic_shift) - first_logical;
> > > - print_address_zone(first_logical, first_physical, size, last_attr);
> > > + print_address_zone(mon, first_logical, first_physical, size, last_attr);
> > > }
> > > }
> > >
> > > #define DUMP_CACHEFLAGS(a) \
> > > switch (a & M68K_DESC_CACHEMODE) { \
> > > case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \
> > > - qemu_printf("T"); \
> > > + monitor_puts(mon, "T"); \
> > > break; \
> > > case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \
> > > - qemu_printf("C"); \
> > > + monitor_puts(mon, "C"); \
> > > break; \
> > > case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \
> > > - qemu_printf("S"); \
> > > + monitor_puts(mon, "S"); \
> > > break; \
> > > case M68K_DESC_CM_NCACHE: /* noncachable */ \
> > > - qemu_printf("N"); \
> > > + monitor_puts(mon, "N"); \
> > > break; \
> > > }
> > >
> > > -static void dump_ttr(uint32_t ttr)
> > > +static void dump_ttr(Monitor *mon, uint32_t ttr)
> > > {
> > > if ((ttr & M68K_TTR_ENABLED) == 0) {
> > > - qemu_printf("disabled\n");
> > > + monitor_puts(mon, "disabled\n");
> > > return;
> > > }
> > > - qemu_printf("Base: 0x%08x Mask: 0x%08x Control: ",
> > > - ttr & M68K_TTR_ADDR_BASE,
> > > - (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
> > > + monitor_printf(mon, "Base: 0x%08x Mask: 0x%08x Control: ",
> > > + ttr & M68K_TTR_ADDR_BASE,
> > > + (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
> > > switch (ttr & M68K_TTR_SFIELD) {
> > > case M68K_TTR_SFIELD_USER:
> > > - qemu_printf("U");
> > > + monitor_puts(mon, "U");
> > > break;
> > > case M68K_TTR_SFIELD_SUPER:
> > > - qemu_printf("S");
> > > + monitor_puts(mon, "S");
> > > break;
> > > default:
> > > - qemu_printf("*");
> > > + monitor_puts(mon, "*");
> > > break;
> > > }
> > > DUMP_CACHEFLAGS(ttr);
> > > if (ttr & M68K_DESC_WRITEPROT) {
> > > - qemu_printf("R");
> > > + monitor_puts(mon, "R");
> > > } else {
> > > - qemu_printf("W");
> > > + monitor_puts(mon, "W");
> > > }
> > > - qemu_printf(" U: %d\n", (ttr & M68K_DESC_USERATTR) >>
> > > + monitor_printf(mon, " U: %d\n", (ttr & M68K_DESC_USERATTR) >>
> > > M68K_DESC_USERATTR_SHIFT);
> > > }
> > >
> > > -void dump_mmu(CPUM68KState *env)
> > > +void dump_mmu(Monitor *mon, CPUM68KState *env)
> > > {
> > > if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
> > > - qemu_printf("Translation disabled\n");
> > > + monitor_puts(mon, "Translation disabled\n");
> > > return;
> > > }
> > > - qemu_printf("Page Size: ");
> > > + monitor_puts(mon, "Page Size: ");
> > > if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
> > > - qemu_printf("8kB\n");
> > > + monitor_puts(mon, "8kB\n");
> > > } else {
> > > - qemu_printf("4kB\n");
> > > + monitor_puts(mon, "4kB\n");
> > > }
> > >
> > > - qemu_printf("MMUSR: ");
> > > + monitor_puts(mon, "MMUSR: ");
> > > if (env->mmu.mmusr & M68K_MMU_B_040) {
> > > - qemu_printf("BUS ERROR\n");
> > > + monitor_puts(mon, "BUS ERROR\n");
> > > } else {
> > > - qemu_printf("Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
> > > + monitor_printf(mon, "Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
> > > /* flags found on the page descriptor */
> > > if (env->mmu.mmusr & M68K_MMU_G_040) {
> > > - qemu_printf("G"); /* Global */
> > > + monitor_puts(mon, "G"); /* Global */
> > > } else {
> > > - qemu_printf(".");
> > > + monitor_puts(mon, ".");
> > > }
> > > if (env->mmu.mmusr & M68K_MMU_S_040) {
> > > - qemu_printf("S"); /* Supervisor */
> > > + monitor_puts(mon, "S"); /* Supervisor */
> > > } else {
> > > - qemu_printf(".");
> > > + monitor_puts(mon, ".");
> > > }
> > > if (env->mmu.mmusr & M68K_MMU_M_040) {
> > > - qemu_printf("M"); /* Modified */
> > > + monitor_puts(mon, "M"); /* Modified */
> > > } else {
> > > - qemu_printf(".");
> > > + monitor_puts(mon, ".");
> > > }
> > > if (env->mmu.mmusr & M68K_MMU_WP_040) {
> > > - qemu_printf("W"); /* Write protect */
> > > + monitor_puts(mon, "W"); /* Write protect */
> > > } else {
> > > - qemu_printf(".");
> > > + monitor_puts(mon, ".");
> > > }
> > > if (env->mmu.mmusr & M68K_MMU_T_040) {
> > > - qemu_printf("T"); /* Transparent */
> > > + monitor_puts(mon, "T"); /* Transparent */
> > > } else {
> > > - qemu_printf(".");
> > > + monitor_puts(mon, ".");
> > > }
> > > if (env->mmu.mmusr & M68K_MMU_R_040) {
> > > - qemu_printf("R"); /* Resident */
> > > + monitor_puts(mon, "R"); /* Resident */
> > > } else {
> > > - qemu_printf(".");
> > > + monitor_puts(mon, ".");
> > > }
> > > - qemu_printf(" Cache: ");
> > > + monitor_puts(mon, " Cache: ");
> > > DUMP_CACHEFLAGS(env->mmu.mmusr);
> > > - qemu_printf(" U: %d\n", (env->mmu.mmusr >> 8) & 3);
> > > - qemu_printf("\n");
> > > + monitor_printf(mon, " U: %d\n", (env->mmu.mmusr >> 8) & 3);
> > > + monitor_puts(mon, "\n");
> >
> > That one is a little odd isn't it; still, generally
>
> Doesn't puts append a newline? Then this would add an extra empty line.
As rth said, apparently not.
But what made me more curious in this case is why not just flatten it
down so that the printf has a second \n rather than needing the second
call to puts.
Dave
> Regards,
> BALATON Zoltan
>
> > Reviewed-by: Dr. David Alan Gilbert <dave@treblig.org>
> >
> > > }
> > >
> > > - qemu_printf("ITTR0: ");
> > > - dump_ttr(env->mmu.ttr[M68K_ITTR0]);
> > > - qemu_printf("ITTR1: ");
> > > - dump_ttr(env->mmu.ttr[M68K_ITTR1]);
> > > - qemu_printf("DTTR0: ");
> > > - dump_ttr(env->mmu.ttr[M68K_DTTR0]);
> > > - qemu_printf("DTTR1: ");
> > > - dump_ttr(env->mmu.ttr[M68K_DTTR1]);
> > > + monitor_puts(mon, "ITTR0: ");
> > > + dump_ttr(mon, env->mmu.ttr[M68K_ITTR0]);
> > > + monitor_puts(mon, "ITTR1: ");
> > > + dump_ttr(mon, env->mmu.ttr[M68K_ITTR1]);
> > > + monitor_puts(mon, "DTTR0: ");
> > > + dump_ttr(mon, env->mmu.ttr[M68K_DTTR0]);
> > > + monitor_puts(mon, "DTTR1: ");
> > > + dump_ttr(mon, env->mmu.ttr[M68K_DTTR1]);
> > >
> > > - qemu_printf("SRP: 0x%08x\n", env->mmu.srp);
> > > - dump_address_map(env, env->mmu.srp);
> > > + monitor_printf(mon, "SRP: 0x%08x\n", env->mmu.srp);
> > > + dump_address_map(mon, env, env->mmu.srp);
> > >
> > > - qemu_printf("URP: 0x%08x\n", env->mmu.urp);
> > > - dump_address_map(env, env->mmu.urp);
> > > + monitor_printf(mon, "URP: 0x%08x\n", env->mmu.urp);
> > > + dump_address_map(mon, env, env->mmu.urp);
> > > }
> > >
> > > static int check_TTR(uint32_t ttr, int *prot, target_ulong addr,
> > > diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c
> > > index 2bdf6acae0..623c6ab635 100644
> > > --- a/target/m68k/monitor.c
> > > +++ b/target/m68k/monitor.c
> > > @@ -15,11 +15,11 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
> > > CPUArchState *env1 = mon_get_cpu_env(mon);
> > >
> > > if (!env1) {
> > > - monitor_printf(mon, "No CPU available\n");
> > > + monitor_puts(mon, "No CPU available\n");
> > > return;
> > > }
> > >
> > > - dump_mmu(env1);
> > > + dump_mmu(mon, env1);
> > > }
> > >
> > > static const MonitorDef monitor_defs[] = {
> > > --
> > > 2.41.0
> > >
> >
--
-----Open up your eyes, open up your mind, open up your code -------
/ Dr. David Alan Gilbert | Running GNU/Linux | Happy \
\ dave @ treblig.org | | In Hex /
\ _________________________|_____ http://www.treblig.org |_______/
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor
2024-03-28 21:59 ` Dr. David Alan Gilbert
@ 2024-03-28 22:29 ` BALATON Zoltan
0 siblings, 0 replies; 46+ messages in thread
From: BALATON Zoltan @ 2024-03-28 22:29 UTC (permalink / raw)
To: Dr. David Alan Gilbert
Cc: Philippe Mathieu-Daudé,
qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Jiaxun Yang, Nicholas Piggin,
Paolo Bonzini, Daniel Henrique Barboza, Yoshinori Sato,
Markus Armbruster, Richard Henderson, qemu-ppc, Laurent Vivier,
Mark Cave-Ayland
[-- Attachment #1: Type: text/plain, Size: 9982 bytes --]
On Thu, 28 Mar 2024, Dr. David Alan Gilbert wrote:
> * BALATON Zoltan (balaton@eik.bme.hu) wrote:
>> On Sun, 24 Mar 2024, Dr. David Alan Gilbert wrote:
>>> * Philippe Mathieu-Daudé (philmd@linaro.org) wrote:
>>>> Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
>>>>
>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>>> ---
>>>> target/m68k/cpu.h | 2 +-
>>>> target/m68k/helper.c | 126 +++++++++++++++++++++---------------------
>>>> target/m68k/monitor.c | 4 +-
>>>> 3 files changed, 67 insertions(+), 65 deletions(-)
>>>>
>>>> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
>>>> index 346427e144..4e4307956d 100644
>>>> --- a/target/m68k/cpu.h
>>>> +++ b/target/m68k/cpu.h
>>>> @@ -620,6 +620,6 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc,
>>>> }
>>>> }
>>>>
>>>> -void dump_mmu(CPUM68KState *env);
>>>> +void dump_mmu(Monitor *mon, CPUM68KState *env);
>>>>
>>>> #endif
>>>> diff --git a/target/m68k/helper.c b/target/m68k/helper.c
>>>> index 1a475f082a..310e26dfa1 100644
>>>> --- a/target/m68k/helper.c
>>>> +++ b/target/m68k/helper.c
>>>> @@ -25,7 +25,7 @@
>>>> #include "exec/helper-proto.h"
>>>> #include "gdbstub/helpers.h"
>>>> #include "fpu/softfloat.h"
>>>> -#include "qemu/qemu-print.h"
>>>> +#include "monitor/monitor.h"
>>>>
>>>> #define SIGNBIT (1u << 31)
>>>>
>>>> @@ -455,28 +455,30 @@ void m68k_switch_sp(CPUM68KState *env)
>>>> #if !defined(CONFIG_USER_ONLY)
>>>> /* MMU: 68040 only */
>>>>
>>>> -static void print_address_zone(uint32_t logical, uint32_t physical,
>>>> +static void print_address_zone(Monitor *mon,
>>>> + uint32_t logical, uint32_t physical,
>>>> uint32_t size, int attr)
>>>> {
>>>> - qemu_printf("%08x - %08x -> %08x - %08x %c ",
>>>> - logical, logical + size - 1,
>>>> - physical, physical + size - 1,
>>>> - attr & 4 ? 'W' : '-');
>>>> + monitor_printf(mon, "%08x - %08x -> %08x - %08x %c ",
>>>> + logical, logical + size - 1,
>>>> + physical, physical + size - 1,
>>>> + attr & 4 ? 'W' : '-');
>>>> size >>= 10;
>>>> if (size < 1024) {
>>>> - qemu_printf("(%d KiB)\n", size);
>>>> + monitor_printf(mon, "(%d KiB)\n", size);
>>>> } else {
>>>> size >>= 10;
>>>> if (size < 1024) {
>>>> - qemu_printf("(%d MiB)\n", size);
>>>> + monitor_printf(mon, "(%d MiB)\n", size);
>>>> } else {
>>>> size >>= 10;
>>>> - qemu_printf("(%d GiB)\n", size);
>>>> + monitor_printf(mon, "(%d GiB)\n", size);
>>>> }
>>>> }
>>>> }
>>>>
>>>> -static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
>>>> +static void dump_address_map(Monitor *mon, CPUM68KState *env,
>>>> + uint32_t root_pointer)
>>>> {
>>>> int i, j, k;
>>>> int tic_size, tic_shift;
>>>> @@ -545,7 +547,7 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
>>>> if (first_logical != 0xffffffff) {
>>>> size = last_logical + (1 << tic_shift) -
>>>> first_logical;
>>>> - print_address_zone(first_logical,
>>>> + print_address_zone(mon, first_logical,
>>>> first_physical, size, last_attr);
>>>> }
>>>> first_logical = logical;
>>>> @@ -556,125 +558,125 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
>>>> }
>>>> if (first_logical != logical || (attr & 4) != (last_attr & 4)) {
>>>> size = logical + (1 << tic_shift) - first_logical;
>>>> - print_address_zone(first_logical, first_physical, size, last_attr);
>>>> + print_address_zone(mon, first_logical, first_physical, size, last_attr);
>>>> }
>>>> }
>>>>
>>>> #define DUMP_CACHEFLAGS(a) \
>>>> switch (a & M68K_DESC_CACHEMODE) { \
>>>> case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \
>>>> - qemu_printf("T"); \
>>>> + monitor_puts(mon, "T"); \
>>>> break; \
>>>> case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \
>>>> - qemu_printf("C"); \
>>>> + monitor_puts(mon, "C"); \
>>>> break; \
>>>> case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \
>>>> - qemu_printf("S"); \
>>>> + monitor_puts(mon, "S"); \
>>>> break; \
>>>> case M68K_DESC_CM_NCACHE: /* noncachable */ \
>>>> - qemu_printf("N"); \
>>>> + monitor_puts(mon, "N"); \
>>>> break; \
>>>> }
>>>>
>>>> -static void dump_ttr(uint32_t ttr)
>>>> +static void dump_ttr(Monitor *mon, uint32_t ttr)
>>>> {
>>>> if ((ttr & M68K_TTR_ENABLED) == 0) {
>>>> - qemu_printf("disabled\n");
>>>> + monitor_puts(mon, "disabled\n");
>>>> return;
>>>> }
>>>> - qemu_printf("Base: 0x%08x Mask: 0x%08x Control: ",
>>>> - ttr & M68K_TTR_ADDR_BASE,
>>>> - (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
>>>> + monitor_printf(mon, "Base: 0x%08x Mask: 0x%08x Control: ",
>>>> + ttr & M68K_TTR_ADDR_BASE,
>>>> + (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
>>>> switch (ttr & M68K_TTR_SFIELD) {
>>>> case M68K_TTR_SFIELD_USER:
>>>> - qemu_printf("U");
>>>> + monitor_puts(mon, "U");
>>>> break;
>>>> case M68K_TTR_SFIELD_SUPER:
>>>> - qemu_printf("S");
>>>> + monitor_puts(mon, "S");
>>>> break;
>>>> default:
>>>> - qemu_printf("*");
>>>> + monitor_puts(mon, "*");
>>>> break;
>>>> }
>>>> DUMP_CACHEFLAGS(ttr);
>>>> if (ttr & M68K_DESC_WRITEPROT) {
>>>> - qemu_printf("R");
>>>> + monitor_puts(mon, "R");
>>>> } else {
>>>> - qemu_printf("W");
>>>> + monitor_puts(mon, "W");
>>>> }
>>>> - qemu_printf(" U: %d\n", (ttr & M68K_DESC_USERATTR) >>
>>>> + monitor_printf(mon, " U: %d\n", (ttr & M68K_DESC_USERATTR) >>
>>>> M68K_DESC_USERATTR_SHIFT);
>>>> }
>>>>
>>>> -void dump_mmu(CPUM68KState *env)
>>>> +void dump_mmu(Monitor *mon, CPUM68KState *env)
>>>> {
>>>> if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
>>>> - qemu_printf("Translation disabled\n");
>>>> + monitor_puts(mon, "Translation disabled\n");
>>>> return;
>>>> }
>>>> - qemu_printf("Page Size: ");
>>>> + monitor_puts(mon, "Page Size: ");
>>>> if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
>>>> - qemu_printf("8kB\n");
>>>> + monitor_puts(mon, "8kB\n");
>>>> } else {
>>>> - qemu_printf("4kB\n");
>>>> + monitor_puts(mon, "4kB\n");
>>>> }
>>>>
>>>> - qemu_printf("MMUSR: ");
>>>> + monitor_puts(mon, "MMUSR: ");
>>>> if (env->mmu.mmusr & M68K_MMU_B_040) {
>>>> - qemu_printf("BUS ERROR\n");
>>>> + monitor_puts(mon, "BUS ERROR\n");
>>>> } else {
>>>> - qemu_printf("Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
>>>> + monitor_printf(mon, "Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
>>>> /* flags found on the page descriptor */
>>>> if (env->mmu.mmusr & M68K_MMU_G_040) {
>>>> - qemu_printf("G"); /* Global */
>>>> + monitor_puts(mon, "G"); /* Global */
>>>> } else {
>>>> - qemu_printf(".");
>>>> + monitor_puts(mon, ".");
>>>> }
>>>> if (env->mmu.mmusr & M68K_MMU_S_040) {
>>>> - qemu_printf("S"); /* Supervisor */
>>>> + monitor_puts(mon, "S"); /* Supervisor */
>>>> } else {
>>>> - qemu_printf(".");
>>>> + monitor_puts(mon, ".");
>>>> }
>>>> if (env->mmu.mmusr & M68K_MMU_M_040) {
>>>> - qemu_printf("M"); /* Modified */
>>>> + monitor_puts(mon, "M"); /* Modified */
>>>> } else {
>>>> - qemu_printf(".");
>>>> + monitor_puts(mon, ".");
>>>> }
>>>> if (env->mmu.mmusr & M68K_MMU_WP_040) {
>>>> - qemu_printf("W"); /* Write protect */
>>>> + monitor_puts(mon, "W"); /* Write protect */
>>>> } else {
>>>> - qemu_printf(".");
>>>> + monitor_puts(mon, ".");
>>>> }
>>>> if (env->mmu.mmusr & M68K_MMU_T_040) {
>>>> - qemu_printf("T"); /* Transparent */
>>>> + monitor_puts(mon, "T"); /* Transparent */
>>>> } else {
>>>> - qemu_printf(".");
>>>> + monitor_puts(mon, ".");
>>>> }
>>>> if (env->mmu.mmusr & M68K_MMU_R_040) {
>>>> - qemu_printf("R"); /* Resident */
>>>> + monitor_puts(mon, "R"); /* Resident */
>>>> } else {
>>>> - qemu_printf(".");
>>>> + monitor_puts(mon, ".");
>>>> }
>>>> - qemu_printf(" Cache: ");
>>>> + monitor_puts(mon, " Cache: ");
>>>> DUMP_CACHEFLAGS(env->mmu.mmusr);
>>>> - qemu_printf(" U: %d\n", (env->mmu.mmusr >> 8) & 3);
>>>> - qemu_printf("\n");
>>>> + monitor_printf(mon, " U: %d\n", (env->mmu.mmusr >> 8) & 3);
>>>> + monitor_puts(mon, "\n");
>>>
>>> That one is a little odd isn't it; still, generally
>>
>> Doesn't puts append a newline? Then this would add an extra empty line.
>
> As rth said, apparently not.
> But what made me more curious in this case is why not just flatten it
> down so that the printf has a second \n rather than needing the second
> call to puts.
Maybe because monitor_puts also seems to have a flush so that separate
call would do an additional flush to make sure the previously printed
lines are displayed? But I have no idea just guessing.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor
2024-03-21 15:48 ` [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
2024-03-21 21:49 ` Richard Henderson
2024-03-24 23:43 ` Dr. David Alan Gilbert
@ 2024-04-24 7:35 ` Markus Armbruster
2024-04-24 9:19 ` BALATON Zoltan
2 siblings, 1 reply; 46+ messages in thread
From: Markus Armbruster @ 2024-04-24 7:35 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Richard Henderson, qemu-ppc, Laurent Vivier,
Mark Cave-Ayland
Philippe Mathieu-Daudé <philmd@linaro.org> writes:
> Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
Why? Here's my attempt at an answer: because this runs only within HMP
command "info tlb". Using qemu_printf() there isn't wrong, but with
monitor_printf(), it's obvious that we print to the monitor.
On monitor_printf() vs. monitor_puts().
qemu_printf() behaves like monitor_printf() when monitor_cur() returns
non-null, which it certainly does within a monitor command.
monitor_printf() prints like monitor_puts() when monitor_is_qmp()
returns false, which it certainly does within an HMP command.
Note: despite their names, monitor_printf() and monitor_puts() are at
different interface layers!
We need a low-level function to send to a monitor, be it HMP or QMP:
monitor_puts().
We need a high-level function to format JSON and send it to QMP:
qmp_send_response().
We need a high-level functions to format text and send it to HMP:
monitor_printf(), ...
Naming the functions that expect an HMP monitor hmp_FOO() would make
more sense. Renaming them now would be quite some churn, though.
Discussed at
<https://lore.kernel.org/qemu-devel/87y1adm0os.fsf@pond.sub.org/>.
HMP code using both two layers to print gives me a slightly queasy
feeling. It's not wrong, though.
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/m68k/cpu.h | 2 +-
> target/m68k/helper.c | 126 +++++++++++++++++++++---------------------
> target/m68k/monitor.c | 4 +-
> 3 files changed, 67 insertions(+), 65 deletions(-)
>
> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
> index 346427e144..4e4307956d 100644
> --- a/target/m68k/cpu.h
> +++ b/target/m68k/cpu.h
> @@ -620,6 +620,6 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc,
> }
> }
>
> -void dump_mmu(CPUM68KState *env);
> +void dump_mmu(Monitor *mon, CPUM68KState *env);
>
> #endif
> diff --git a/target/m68k/helper.c b/target/m68k/helper.c
> index 1a475f082a..310e26dfa1 100644
> --- a/target/m68k/helper.c
> +++ b/target/m68k/helper.c
> @@ -25,7 +25,7 @@
> #include "exec/helper-proto.h"
> #include "gdbstub/helpers.h"
> #include "fpu/softfloat.h"
> -#include "qemu/qemu-print.h"
> +#include "monitor/monitor.h"
>
> #define SIGNBIT (1u << 31)
>
> @@ -455,28 +455,30 @@ void m68k_switch_sp(CPUM68KState *env)
> #if !defined(CONFIG_USER_ONLY)
> /* MMU: 68040 only */
>
> -static void print_address_zone(uint32_t logical, uint32_t physical,
> +static void print_address_zone(Monitor *mon,
> + uint32_t logical, uint32_t physical,
> uint32_t size, int attr)
> {
> - qemu_printf("%08x - %08x -> %08x - %08x %c ",
> - logical, logical + size - 1,
> - physical, physical + size - 1,
> - attr & 4 ? 'W' : '-');
> + monitor_printf(mon, "%08x - %08x -> %08x - %08x %c ",
> + logical, logical + size - 1,
> + physical, physical + size - 1,
> + attr & 4 ? 'W' : '-');
> size >>= 10;
> if (size < 1024) {
> - qemu_printf("(%d KiB)\n", size);
> + monitor_printf(mon, "(%d KiB)\n", size);
> } else {
> size >>= 10;
> if (size < 1024) {
> - qemu_printf("(%d MiB)\n", size);
> + monitor_printf(mon, "(%d MiB)\n", size);
> } else {
> size >>= 10;
> - qemu_printf("(%d GiB)\n", size);
> + monitor_printf(mon, "(%d GiB)\n", size);
> }
> }
> }
>
> -static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
> +static void dump_address_map(Monitor *mon, CPUM68KState *env,
> + uint32_t root_pointer)
> {
> int i, j, k;
> int tic_size, tic_shift;
> @@ -545,7 +547,7 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
> if (first_logical != 0xffffffff) {
> size = last_logical + (1 << tic_shift) -
> first_logical;
> - print_address_zone(first_logical,
> + print_address_zone(mon, first_logical,
> first_physical, size, last_attr);
> }
> first_logical = logical;
> @@ -556,125 +558,125 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
> }
> if (first_logical != logical || (attr & 4) != (last_attr & 4)) {
> size = logical + (1 << tic_shift) - first_logical;
> - print_address_zone(first_logical, first_physical, size, last_attr);
> + print_address_zone(mon, first_logical, first_physical, size, last_attr);
> }
> }
>
> #define DUMP_CACHEFLAGS(a) \
> switch (a & M68K_DESC_CACHEMODE) { \
> case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \
> - qemu_printf("T"); \
> + monitor_puts(mon, "T"); \
Not wrong, but I'd stick to monitor_printf() to keep the transformation
as simple as possible, and to sidestep the need for explaining the
subtleties around monitor_printf() vs. monitor_puts() in the commit
message.
> break; \
> case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \
> - qemu_printf("C"); \
> + monitor_puts(mon, "C"); \
Likewise. Not going to note this again.
> break; \
> case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \
> - qemu_printf("S"); \
> + monitor_puts(mon, "S"); \
> break; \
> case M68K_DESC_CM_NCACHE: /* noncachable */ \
> - qemu_printf("N"); \
> + monitor_puts(mon, "N"); \
> break; \
> }
>
> -static void dump_ttr(uint32_t ttr)
> +static void dump_ttr(Monitor *mon, uint32_t ttr)
> {
> if ((ttr & M68K_TTR_ENABLED) == 0) {
> - qemu_printf("disabled\n");
> + monitor_puts(mon, "disabled\n");
> return;
> }
> - qemu_printf("Base: 0x%08x Mask: 0x%08x Control: ",
> - ttr & M68K_TTR_ADDR_BASE,
> - (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
> + monitor_printf(mon, "Base: 0x%08x Mask: 0x%08x Control: ",
> + ttr & M68K_TTR_ADDR_BASE,
> + (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
> switch (ttr & M68K_TTR_SFIELD) {
> case M68K_TTR_SFIELD_USER:
> - qemu_printf("U");
> + monitor_puts(mon, "U");
> break;
> case M68K_TTR_SFIELD_SUPER:
> - qemu_printf("S");
> + monitor_puts(mon, "S");
> break;
> default:
> - qemu_printf("*");
> + monitor_puts(mon, "*");
> break;
> }
> DUMP_CACHEFLAGS(ttr);
> if (ttr & M68K_DESC_WRITEPROT) {
> - qemu_printf("R");
> + monitor_puts(mon, "R");
> } else {
> - qemu_printf("W");
> + monitor_puts(mon, "W");
> }
> - qemu_printf(" U: %d\n", (ttr & M68K_DESC_USERATTR) >>
> + monitor_printf(mon, " U: %d\n", (ttr & M68K_DESC_USERATTR) >>
> M68K_DESC_USERATTR_SHIFT);
> }
>
> -void dump_mmu(CPUM68KState *env)
> +void dump_mmu(Monitor *mon, CPUM68KState *env)
> {
> if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
> - qemu_printf("Translation disabled\n");
> + monitor_puts(mon, "Translation disabled\n");
> return;
> }
> - qemu_printf("Page Size: ");
> + monitor_puts(mon, "Page Size: ");
> if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
> - qemu_printf("8kB\n");
> + monitor_puts(mon, "8kB\n");
> } else {
> - qemu_printf("4kB\n");
> + monitor_puts(mon, "4kB\n");
> }
>
> - qemu_printf("MMUSR: ");
> + monitor_puts(mon, "MMUSR: ");
> if (env->mmu.mmusr & M68K_MMU_B_040) {
> - qemu_printf("BUS ERROR\n");
> + monitor_puts(mon, "BUS ERROR\n");
> } else {
> - qemu_printf("Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
> + monitor_printf(mon, "Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
> /* flags found on the page descriptor */
> if (env->mmu.mmusr & M68K_MMU_G_040) {
> - qemu_printf("G"); /* Global */
> + monitor_puts(mon, "G"); /* Global */
> } else {
> - qemu_printf(".");
> + monitor_puts(mon, ".");
> }
> if (env->mmu.mmusr & M68K_MMU_S_040) {
> - qemu_printf("S"); /* Supervisor */
> + monitor_puts(mon, "S"); /* Supervisor */
> } else {
> - qemu_printf(".");
> + monitor_puts(mon, ".");
> }
> if (env->mmu.mmusr & M68K_MMU_M_040) {
> - qemu_printf("M"); /* Modified */
> + monitor_puts(mon, "M"); /* Modified */
> } else {
> - qemu_printf(".");
> + monitor_puts(mon, ".");
> }
> if (env->mmu.mmusr & M68K_MMU_WP_040) {
> - qemu_printf("W"); /* Write protect */
> + monitor_puts(mon, "W"); /* Write protect */
> } else {
> - qemu_printf(".");
> + monitor_puts(mon, ".");
> }
> if (env->mmu.mmusr & M68K_MMU_T_040) {
> - qemu_printf("T"); /* Transparent */
> + monitor_puts(mon, "T"); /* Transparent */
> } else {
> - qemu_printf(".");
> + monitor_puts(mon, ".");
> }
> if (env->mmu.mmusr & M68K_MMU_R_040) {
> - qemu_printf("R"); /* Resident */
> + monitor_puts(mon, "R"); /* Resident */
> } else {
> - qemu_printf(".");
> + monitor_puts(mon, ".");
> }
> - qemu_printf(" Cache: ");
> + monitor_puts(mon, " Cache: ");
> DUMP_CACHEFLAGS(env->mmu.mmusr);
> - qemu_printf(" U: %d\n", (env->mmu.mmusr >> 8) & 3);
> - qemu_printf("\n");
> + monitor_printf(mon, " U: %d\n", (env->mmu.mmusr >> 8) & 3);
> + monitor_puts(mon, "\n");
> }
>
> - qemu_printf("ITTR0: ");
> - dump_ttr(env->mmu.ttr[M68K_ITTR0]);
> - qemu_printf("ITTR1: ");
> - dump_ttr(env->mmu.ttr[M68K_ITTR1]);
> - qemu_printf("DTTR0: ");
> - dump_ttr(env->mmu.ttr[M68K_DTTR0]);
> - qemu_printf("DTTR1: ");
> - dump_ttr(env->mmu.ttr[M68K_DTTR1]);
> + monitor_puts(mon, "ITTR0: ");
> + dump_ttr(mon, env->mmu.ttr[M68K_ITTR0]);
> + monitor_puts(mon, "ITTR1: ");
> + dump_ttr(mon, env->mmu.ttr[M68K_ITTR1]);
> + monitor_puts(mon, "DTTR0: ");
> + dump_ttr(mon, env->mmu.ttr[M68K_DTTR0]);
> + monitor_puts(mon, "DTTR1: ");
> + dump_ttr(mon, env->mmu.ttr[M68K_DTTR1]);
>
> - qemu_printf("SRP: 0x%08x\n", env->mmu.srp);
> - dump_address_map(env, env->mmu.srp);
> + monitor_printf(mon, "SRP: 0x%08x\n", env->mmu.srp);
> + dump_address_map(mon, env, env->mmu.srp);
>
> - qemu_printf("URP: 0x%08x\n", env->mmu.urp);
> - dump_address_map(env, env->mmu.urp);
> + monitor_printf(mon, "URP: 0x%08x\n", env->mmu.urp);
> + dump_address_map(mon, env, env->mmu.urp);
> }
>
> static int check_TTR(uint32_t ttr, int *prot, target_ulong addr,
> diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c
> index 2bdf6acae0..623c6ab635 100644
> --- a/target/m68k/monitor.c
> +++ b/target/m68k/monitor.c
> @@ -15,11 +15,11 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
> CPUArchState *env1 = mon_get_cpu_env(mon);
>
> if (!env1) {
> - monitor_printf(mon, "No CPU available\n");
> + monitor_puts(mon, "No CPU available\n");
> return;
> }
>
> - dump_mmu(env1);
> + dump_mmu(mon, env1);
> }
>
> static const MonitorDef monitor_defs[] = {
In addition to replacing qemu_printf(), the patch passes the current
monitor around. The alternative is monitor_cur(). I guess you pass
because you consider it cleaner and/or simpler. No objection, but I
suggest to mention it the commit message.
The patch is not wrong, so
Reviewed-by: Markus Armbruster <armbru@redhat.com>
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor
2024-04-24 7:35 ` Markus Armbruster
@ 2024-04-24 9:19 ` BALATON Zoltan
2024-04-24 9:22 ` BALATON Zoltan
0 siblings, 1 reply; 46+ messages in thread
From: BALATON Zoltan @ 2024-04-24 9:19 UTC (permalink / raw)
To: Markus Armbruster
Cc: Philippe Mathieu-Daudé,
qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Richard Henderson, qemu-ppc, Laurent Vivier,
Mark Cave-Ayland
[-- Attachment #1: Type: text/plain, Size: 1856 bytes --]
On Wed, 24 Apr 2024, Markus Armbruster wrote:
> Philippe Mathieu-Daudé <philmd@linaro.org> writes:
>
>> Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
>
> Why? Here's my attempt at an answer: because this runs only within HMP
> command "info tlb". Using qemu_printf() there isn't wrong, but with
> monitor_printf(), it's obvious that we print to the monitor.
>
> On monitor_printf() vs. monitor_puts().
>
> qemu_printf() behaves like monitor_printf() when monitor_cur() returns
> non-null, which it certainly does within a monitor command.
>
> monitor_printf() prints like monitor_puts() when monitor_is_qmp()
> returns false, which it certainly does within an HMP command.
>
> Note: despite their names, monitor_printf() and monitor_puts() are at
> different interface layers!
>
> We need a low-level function to send to a monitor, be it HMP or QMP:
> monitor_puts().
>
> We need a high-level function to format JSON and send it to QMP:
> qmp_send_response().
>
> We need a high-level functions to format text and send it to HMP:
> monitor_printf(), ...
>
> Naming the functions that expect an HMP monitor hmp_FOO() would make
> more sense. Renaming them now would be quite some churn, though.
> Discussed at
> <https://lore.kernel.org/qemu-devel/87y1adm0os.fsf@pond.sub.org/>.
The hmp_ prefix is more cryptic than monitor_. Without knowing QEMU too
much I can guess what monitor_ does but would have to look up what
hmp_means so keeping monitor_ is better IMO. The solution to the naming
issue mentioned above may be renaming monitor_puts to something that tells
it's a low level function (and add a momitor_puts that behaves as
expected) but I can't come up with a name either. Maybe the low level
function could be called hmp_putt? Or add a comment near monitor_puts to
explain this for now.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor
2024-04-24 9:19 ` BALATON Zoltan
@ 2024-04-24 9:22 ` BALATON Zoltan
0 siblings, 0 replies; 46+ messages in thread
From: BALATON Zoltan @ 2024-04-24 9:22 UTC (permalink / raw)
To: Markus Armbruster
Cc: Philippe Mathieu-Daudé,
qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Richard Henderson, qemu-ppc, Laurent Vivier,
Mark Cave-Ayland
[-- Attachment #1: Type: text/plain, Size: 1977 bytes --]
On Wed, 24 Apr 2024, BALATON Zoltan wrote:
> On Wed, 24 Apr 2024, Markus Armbruster wrote:
>> Philippe Mathieu-Daudé <philmd@linaro.org> writes:
>>
>>> Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
>>
>> Why? Here's my attempt at an answer: because this runs only within HMP
>> command "info tlb". Using qemu_printf() there isn't wrong, but with
>> monitor_printf(), it's obvious that we print to the monitor.
>>
>> On monitor_printf() vs. monitor_puts().
>>
>> qemu_printf() behaves like monitor_printf() when monitor_cur() returns
>> non-null, which it certainly does within a monitor command.
>>
>> monitor_printf() prints like monitor_puts() when monitor_is_qmp()
>> returns false, which it certainly does within an HMP command.
>>
>> Note: despite their names, monitor_printf() and monitor_puts() are at
>> different interface layers!
>>
>> We need a low-level function to send to a monitor, be it HMP or QMP:
>> monitor_puts().
>>
>> We need a high-level function to format JSON and send it to QMP:
>> qmp_send_response().
>>
>> We need a high-level functions to format text and send it to HMP:
>> monitor_printf(), ...
>>
>> Naming the functions that expect an HMP monitor hmp_FOO() would make
>> more sense. Renaming them now would be quite some churn, though.
>> Discussed at
>> <https://lore.kernel.org/qemu-devel/87y1adm0os.fsf@pond.sub.org/>.
>
> The hmp_ prefix is more cryptic than monitor_. Without knowing QEMU too much
> I can guess what monitor_ does but would have to look up what hmp_means so
> keeping monitor_ is better IMO. The solution to the naming issue mentioned
> above may be renaming monitor_puts to something that tells it's a low level
> function (and add a momitor_puts that behaves as expected) but I can't come
> up with a name either. Maybe the low level function could be called hmp_putt?
Meant hmp_puts.
> Or add a comment near monitor_puts to explain this for now.
> Regards,
> BALATON Zoltan
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH-for-9.1 06/21] target/m68k: Have dump_ttr() take a @description argument
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 21:49 ` Richard Henderson
2024-03-21 15:48 ` [PATCH-for-9.1 07/21] target/m68k: Move MMU monitor commands from helper.c to monitor.c Philippe Mathieu-Daudé
` (14 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Slightly simplify dump_mmu() by passing the description as
argument to dump_ttr().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/m68k/helper.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 310e26dfa1..cf9d83e47e 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -578,8 +578,9 @@ static void dump_address_map(Monitor *mon, CPUM68KState *env,
break; \
}
-static void dump_ttr(Monitor *mon, uint32_t ttr)
+static void dump_ttr(Monitor *mon, const char *desc, uint32_t ttr)
{
+ monitor_printf(mon, "%s: ", desc);
if ((ttr & M68K_TTR_ENABLED) == 0) {
monitor_puts(mon, "disabled\n");
return;
@@ -663,14 +664,10 @@ void dump_mmu(Monitor *mon, CPUM68KState *env)
monitor_puts(mon, "\n");
}
- monitor_puts(mon, "ITTR0: ");
- dump_ttr(mon, env->mmu.ttr[M68K_ITTR0]);
- monitor_puts(mon, "ITTR1: ");
- dump_ttr(mon, env->mmu.ttr[M68K_ITTR1]);
- monitor_puts(mon, "DTTR0: ");
- dump_ttr(mon, env->mmu.ttr[M68K_DTTR0]);
- monitor_puts(mon, "DTTR1: ");
- dump_ttr(mon, env->mmu.ttr[M68K_DTTR1]);
+ dump_ttr(mon, "ITTR0", env->mmu.ttr[M68K_ITTR0]);
+ dump_ttr(mon, "ITTR1", env->mmu.ttr[M68K_ITTR1]);
+ dump_ttr(mon, "DTTR0", env->mmu.ttr[M68K_DTTR0]);
+ dump_ttr(mon, "DTTR1", env->mmu.ttr[M68K_DTTR1]);
monitor_printf(mon, "SRP: 0x%08x\n", env->mmu.srp);
dump_address_map(mon, env, env->mmu.srp);
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 06/21] target/m68k: Have dump_ttr() take a @description argument
2024-03-21 15:48 ` [PATCH-for-9.1 06/21] target/m68k: Have dump_ttr() take a @description argument Philippe Mathieu-Daudé
@ 2024-03-21 21:49 ` Richard Henderson
0 siblings, 0 replies; 46+ messages in thread
From: Richard Henderson @ 2024-03-21 21:49 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, qemu-ppc, Laurent Vivier,
Mark Cave-Ayland
On 3/21/24 05:48, Philippe Mathieu-Daudé wrote:
> Slightly simplify dump_mmu() by passing the description as
> argument to dump_ttr().
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/m68k/helper.c | 15 ++++++---------
> 1 file changed, 6 insertions(+), 9 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH-for-9.1 07/21] target/m68k: Move MMU monitor commands from helper.c to monitor.c
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 06/21] target/m68k: Have dump_ttr() take a @description argument Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 21:50 ` Richard Henderson
2024-03-21 15:48 ` [PATCH-for-9.1 08/21] target/microblaze: Prefix MMU API with 'mb_' Philippe Mathieu-Daudé
` (13 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Keep all HMP commands in monitor.c.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/m68k/cpu.h | 3 +-
target/m68k/helper.c | 222 -----------------------------------------
target/m68k/monitor.c | 223 +++++++++++++++++++++++++++++++++++++++++-
3 files changed, 223 insertions(+), 225 deletions(-)
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 4e4307956d..0c2a9fa717 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -589,6 +589,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
unsigned size, MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
+void m68k_dump_mmu(Monitor *mon, CPUM68KState *env);
#endif
#include "exec/cpu-all.h"
@@ -620,6 +621,4 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc,
}
}
-void dump_mmu(Monitor *mon, CPUM68KState *env);
-
#endif
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index cf9d83e47e..bd833aed5d 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -25,7 +25,6 @@
#include "exec/helper-proto.h"
#include "gdbstub/helpers.h"
#include "fpu/softfloat.h"
-#include "monitor/monitor.h"
#define SIGNBIT (1u << 31)
@@ -455,227 +454,6 @@ void m68k_switch_sp(CPUM68KState *env)
#if !defined(CONFIG_USER_ONLY)
/* MMU: 68040 only */
-static void print_address_zone(Monitor *mon,
- uint32_t logical, uint32_t physical,
- uint32_t size, int attr)
-{
- monitor_printf(mon, "%08x - %08x -> %08x - %08x %c ",
- logical, logical + size - 1,
- physical, physical + size - 1,
- attr & 4 ? 'W' : '-');
- size >>= 10;
- if (size < 1024) {
- monitor_printf(mon, "(%d KiB)\n", size);
- } else {
- size >>= 10;
- if (size < 1024) {
- monitor_printf(mon, "(%d MiB)\n", size);
- } else {
- size >>= 10;
- monitor_printf(mon, "(%d GiB)\n", size);
- }
- }
-}
-
-static void dump_address_map(Monitor *mon, CPUM68KState *env,
- uint32_t root_pointer)
-{
- int i, j, k;
- int tic_size, tic_shift;
- uint32_t tib_mask;
- uint32_t tia, tib, tic;
- uint32_t logical = 0xffffffff, physical = 0xffffffff;
- uint32_t first_logical = 0xffffffff, first_physical = 0xffffffff;
- uint32_t last_logical, last_physical;
- int32_t size;
- int last_attr = -1, attr = -1;
- CPUState *cs = env_cpu(env);
- MemTxResult txres;
-
- if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
- /* 8k page */
- tic_size = 32;
- tic_shift = 13;
- tib_mask = M68K_8K_PAGE_MASK;
- } else {
- /* 4k page */
- tic_size = 64;
- tic_shift = 12;
- tib_mask = M68K_4K_PAGE_MASK;
- }
- for (i = 0; i < M68K_ROOT_POINTER_ENTRIES; i++) {
- tia = address_space_ldl(cs->as, M68K_POINTER_BASE(root_pointer) + i * 4,
- MEMTXATTRS_UNSPECIFIED, &txres);
- if (txres != MEMTX_OK || !M68K_UDT_VALID(tia)) {
- continue;
- }
- for (j = 0; j < M68K_ROOT_POINTER_ENTRIES; j++) {
- tib = address_space_ldl(cs->as, M68K_POINTER_BASE(tia) + j * 4,
- MEMTXATTRS_UNSPECIFIED, &txres);
- if (txres != MEMTX_OK || !M68K_UDT_VALID(tib)) {
- continue;
- }
- for (k = 0; k < tic_size; k++) {
- tic = address_space_ldl(cs->as, (tib & tib_mask) + k * 4,
- MEMTXATTRS_UNSPECIFIED, &txres);
- if (txres != MEMTX_OK || !M68K_PDT_VALID(tic)) {
- continue;
- }
- if (M68K_PDT_INDIRECT(tic)) {
- tic = address_space_ldl(cs->as, M68K_INDIRECT_POINTER(tic),
- MEMTXATTRS_UNSPECIFIED, &txres);
- if (txres != MEMTX_OK) {
- continue;
- }
- }
-
- last_logical = logical;
- logical = (i << M68K_TTS_ROOT_SHIFT) |
- (j << M68K_TTS_POINTER_SHIFT) |
- (k << tic_shift);
-
- last_physical = physical;
- physical = tic & ~((1 << tic_shift) - 1);
-
- last_attr = attr;
- attr = tic & ((1 << tic_shift) - 1);
-
- if ((logical != (last_logical + (1 << tic_shift))) ||
- (physical != (last_physical + (1 << tic_shift))) ||
- (attr & 4) != (last_attr & 4)) {
-
- if (first_logical != 0xffffffff) {
- size = last_logical + (1 << tic_shift) -
- first_logical;
- print_address_zone(mon, first_logical,
- first_physical, size, last_attr);
- }
- first_logical = logical;
- first_physical = physical;
- }
- }
- }
- }
- if (first_logical != logical || (attr & 4) != (last_attr & 4)) {
- size = logical + (1 << tic_shift) - first_logical;
- print_address_zone(mon, first_logical, first_physical, size, last_attr);
- }
-}
-
-#define DUMP_CACHEFLAGS(a) \
- switch (a & M68K_DESC_CACHEMODE) { \
- case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \
- monitor_puts(mon, "T"); \
- break; \
- case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \
- monitor_puts(mon, "C"); \
- break; \
- case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \
- monitor_puts(mon, "S"); \
- break; \
- case M68K_DESC_CM_NCACHE: /* noncachable */ \
- monitor_puts(mon, "N"); \
- break; \
- }
-
-static void dump_ttr(Monitor *mon, const char *desc, uint32_t ttr)
-{
- monitor_printf(mon, "%s: ", desc);
- if ((ttr & M68K_TTR_ENABLED) == 0) {
- monitor_puts(mon, "disabled\n");
- return;
- }
- monitor_printf(mon, "Base: 0x%08x Mask: 0x%08x Control: ",
- ttr & M68K_TTR_ADDR_BASE,
- (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
- switch (ttr & M68K_TTR_SFIELD) {
- case M68K_TTR_SFIELD_USER:
- monitor_puts(mon, "U");
- break;
- case M68K_TTR_SFIELD_SUPER:
- monitor_puts(mon, "S");
- break;
- default:
- monitor_puts(mon, "*");
- break;
- }
- DUMP_CACHEFLAGS(ttr);
- if (ttr & M68K_DESC_WRITEPROT) {
- monitor_puts(mon, "R");
- } else {
- monitor_puts(mon, "W");
- }
- monitor_printf(mon, " U: %d\n", (ttr & M68K_DESC_USERATTR) >>
- M68K_DESC_USERATTR_SHIFT);
-}
-
-void dump_mmu(Monitor *mon, CPUM68KState *env)
-{
- if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
- monitor_puts(mon, "Translation disabled\n");
- return;
- }
- monitor_puts(mon, "Page Size: ");
- if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
- monitor_puts(mon, "8kB\n");
- } else {
- monitor_puts(mon, "4kB\n");
- }
-
- monitor_puts(mon, "MMUSR: ");
- if (env->mmu.mmusr & M68K_MMU_B_040) {
- monitor_puts(mon, "BUS ERROR\n");
- } else {
- monitor_printf(mon, "Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
- /* flags found on the page descriptor */
- if (env->mmu.mmusr & M68K_MMU_G_040) {
- monitor_puts(mon, "G"); /* Global */
- } else {
- monitor_puts(mon, ".");
- }
- if (env->mmu.mmusr & M68K_MMU_S_040) {
- monitor_puts(mon, "S"); /* Supervisor */
- } else {
- monitor_puts(mon, ".");
- }
- if (env->mmu.mmusr & M68K_MMU_M_040) {
- monitor_puts(mon, "M"); /* Modified */
- } else {
- monitor_puts(mon, ".");
- }
- if (env->mmu.mmusr & M68K_MMU_WP_040) {
- monitor_puts(mon, "W"); /* Write protect */
- } else {
- monitor_puts(mon, ".");
- }
- if (env->mmu.mmusr & M68K_MMU_T_040) {
- monitor_puts(mon, "T"); /* Transparent */
- } else {
- monitor_puts(mon, ".");
- }
- if (env->mmu.mmusr & M68K_MMU_R_040) {
- monitor_puts(mon, "R"); /* Resident */
- } else {
- monitor_puts(mon, ".");
- }
- monitor_puts(mon, " Cache: ");
- DUMP_CACHEFLAGS(env->mmu.mmusr);
- monitor_printf(mon, " U: %d\n", (env->mmu.mmusr >> 8) & 3);
- monitor_puts(mon, "\n");
- }
-
- dump_ttr(mon, "ITTR0", env->mmu.ttr[M68K_ITTR0]);
- dump_ttr(mon, "ITTR1", env->mmu.ttr[M68K_ITTR1]);
- dump_ttr(mon, "DTTR0", env->mmu.ttr[M68K_DTTR0]);
- dump_ttr(mon, "DTTR1", env->mmu.ttr[M68K_DTTR1]);
-
- monitor_printf(mon, "SRP: 0x%08x\n", env->mmu.srp);
- dump_address_map(mon, env, env->mmu.srp);
-
- monitor_printf(mon, "URP: 0x%08x\n", env->mmu.urp);
- dump_address_map(mon, env, env->mmu.urp);
-}
-
static int check_TTR(uint32_t ttr, int *prot, target_ulong addr,
int access_type)
{
diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c
index 623c6ab635..c225846540 100644
--- a/target/m68k/monitor.c
+++ b/target/m68k/monitor.c
@@ -10,6 +10,227 @@
#include "monitor/hmp-target.h"
#include "monitor/monitor.h"
+static void print_address_zone(Monitor *mon,
+ uint32_t logical, uint32_t physical,
+ uint32_t size, int attr)
+{
+ monitor_printf(mon, "%08x - %08x -> %08x - %08x %c ",
+ logical, logical + size - 1,
+ physical, physical + size - 1,
+ attr & 4 ? 'W' : '-');
+ size >>= 10;
+ if (size < 1024) {
+ monitor_printf(mon, "(%d KiB)\n", size);
+ } else {
+ size >>= 10;
+ if (size < 1024) {
+ monitor_printf(mon, "(%d MiB)\n", size);
+ } else {
+ size >>= 10;
+ monitor_printf(mon, "(%d GiB)\n", size);
+ }
+ }
+}
+
+static void dump_address_map(Monitor *mon, CPUM68KState *env,
+ uint32_t root_pointer)
+{
+ int i, j, k;
+ int tic_size, tic_shift;
+ uint32_t tib_mask;
+ uint32_t tia, tib, tic;
+ uint32_t logical = 0xffffffff, physical = 0xffffffff;
+ uint32_t first_logical = 0xffffffff, first_physical = 0xffffffff;
+ uint32_t last_logical, last_physical;
+ int32_t size;
+ int last_attr = -1, attr = -1;
+ CPUState *cs = env_cpu(env);
+ MemTxResult txres;
+
+ if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
+ /* 8k page */
+ tic_size = 32;
+ tic_shift = 13;
+ tib_mask = M68K_8K_PAGE_MASK;
+ } else {
+ /* 4k page */
+ tic_size = 64;
+ tic_shift = 12;
+ tib_mask = M68K_4K_PAGE_MASK;
+ }
+ for (i = 0; i < M68K_ROOT_POINTER_ENTRIES; i++) {
+ tia = address_space_ldl(cs->as, M68K_POINTER_BASE(root_pointer) + i * 4,
+ MEMTXATTRS_UNSPECIFIED, &txres);
+ if (txres != MEMTX_OK || !M68K_UDT_VALID(tia)) {
+ continue;
+ }
+ for (j = 0; j < M68K_ROOT_POINTER_ENTRIES; j++) {
+ tib = address_space_ldl(cs->as, M68K_POINTER_BASE(tia) + j * 4,
+ MEMTXATTRS_UNSPECIFIED, &txres);
+ if (txres != MEMTX_OK || !M68K_UDT_VALID(tib)) {
+ continue;
+ }
+ for (k = 0; k < tic_size; k++) {
+ tic = address_space_ldl(cs->as, (tib & tib_mask) + k * 4,
+ MEMTXATTRS_UNSPECIFIED, &txres);
+ if (txres != MEMTX_OK || !M68K_PDT_VALID(tic)) {
+ continue;
+ }
+ if (M68K_PDT_INDIRECT(tic)) {
+ tic = address_space_ldl(cs->as, M68K_INDIRECT_POINTER(tic),
+ MEMTXATTRS_UNSPECIFIED, &txres);
+ if (txres != MEMTX_OK) {
+ continue;
+ }
+ }
+
+ last_logical = logical;
+ logical = (i << M68K_TTS_ROOT_SHIFT) |
+ (j << M68K_TTS_POINTER_SHIFT) |
+ (k << tic_shift);
+
+ last_physical = physical;
+ physical = tic & ~((1 << tic_shift) - 1);
+
+ last_attr = attr;
+ attr = tic & ((1 << tic_shift) - 1);
+
+ if ((logical != (last_logical + (1 << tic_shift))) ||
+ (physical != (last_physical + (1 << tic_shift))) ||
+ (attr & 4) != (last_attr & 4)) {
+
+ if (first_logical != 0xffffffff) {
+ size = last_logical + (1 << tic_shift) -
+ first_logical;
+ print_address_zone(mon, first_logical,
+ first_physical, size, last_attr);
+ }
+ first_logical = logical;
+ first_physical = physical;
+ }
+ }
+ }
+ }
+ if (first_logical != logical || (attr & 4) != (last_attr & 4)) {
+ size = logical + (1 << tic_shift) - first_logical;
+ print_address_zone(mon, first_logical, first_physical, size, last_attr);
+ }
+}
+
+#define DUMP_CACHEFLAGS(a) \
+ switch (a & M68K_DESC_CACHEMODE) { \
+ case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \
+ monitor_puts(mon, "T"); \
+ break; \
+ case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \
+ monitor_puts(mon, "C"); \
+ break; \
+ case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \
+ monitor_puts(mon, "S"); \
+ break; \
+ case M68K_DESC_CM_NCACHE: /* noncachable */ \
+ monitor_puts(mon, "N"); \
+ break; \
+ }
+
+static void dump_ttr(Monitor *mon, const char *desc, uint32_t ttr)
+{
+ monitor_printf(mon, "%s: ", desc);
+ if ((ttr & M68K_TTR_ENABLED) == 0) {
+ monitor_puts(mon, "disabled\n");
+ return;
+ }
+ monitor_printf(mon, "Base: 0x%08x Mask: 0x%08x Control: ",
+ ttr & M68K_TTR_ADDR_BASE,
+ (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
+ switch (ttr & M68K_TTR_SFIELD) {
+ case M68K_TTR_SFIELD_USER:
+ monitor_puts(mon, "U");
+ break;
+ case M68K_TTR_SFIELD_SUPER:
+ monitor_puts(mon, "S");
+ break;
+ default:
+ monitor_puts(mon, "*");
+ break;
+ }
+ DUMP_CACHEFLAGS(ttr);
+ if (ttr & M68K_DESC_WRITEPROT) {
+ monitor_puts(mon, "R");
+ } else {
+ monitor_puts(mon, "W");
+ }
+ monitor_printf(mon, " U: %d\n", (ttr & M68K_DESC_USERATTR) >>
+ M68K_DESC_USERATTR_SHIFT);
+}
+
+void m68k_dump_mmu(Monitor *mon, CPUM68KState *env)
+{
+ if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
+ monitor_puts(mon, "Translation disabled\n");
+ return;
+ }
+ monitor_puts(mon, "Page Size: ");
+ if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
+ monitor_puts(mon, "8kB\n");
+ } else {
+ monitor_puts(mon, "4kB\n");
+ }
+
+ monitor_puts(mon, "MMUSR: ");
+ if (env->mmu.mmusr & M68K_MMU_B_040) {
+ monitor_puts(mon, "BUS ERROR\n");
+ } else {
+ monitor_printf(mon, "Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
+ /* flags found on the page descriptor */
+ if (env->mmu.mmusr & M68K_MMU_G_040) {
+ monitor_puts(mon, "G"); /* Global */
+ } else {
+ monitor_puts(mon, ".");
+ }
+ if (env->mmu.mmusr & M68K_MMU_S_040) {
+ monitor_puts(mon, "S"); /* Supervisor */
+ } else {
+ monitor_puts(mon, ".");
+ }
+ if (env->mmu.mmusr & M68K_MMU_M_040) {
+ monitor_puts(mon, "M"); /* Modified */
+ } else {
+ monitor_puts(mon, ".");
+ }
+ if (env->mmu.mmusr & M68K_MMU_WP_040) {
+ monitor_puts(mon, "W"); /* Write protect */
+ } else {
+ monitor_puts(mon, ".");
+ }
+ if (env->mmu.mmusr & M68K_MMU_T_040) {
+ monitor_puts(mon, "T"); /* Transparent */
+ } else {
+ monitor_puts(mon, ".");
+ }
+ if (env->mmu.mmusr & M68K_MMU_R_040) {
+ monitor_puts(mon, "R"); /* Resident */
+ } else {
+ monitor_puts(mon, ".");
+ }
+ monitor_puts(mon, " Cache: ");
+ DUMP_CACHEFLAGS(env->mmu.mmusr);
+ monitor_printf(mon, " U: %d\n", (env->mmu.mmusr >> 8) & 3);
+ monitor_puts(mon, "\n");
+ }
+
+ dump_ttr(mon, "ITTR0", env->mmu.ttr[M68K_ITTR0]);
+ dump_ttr(mon, "ITTR1", env->mmu.ttr[M68K_ITTR1]);
+ dump_ttr(mon, "DTTR0", env->mmu.ttr[M68K_DTTR0]);
+ dump_ttr(mon, "DTTR1", env->mmu.ttr[M68K_DTTR1]);
+
+ monitor_printf(mon, "SRP: 0x%08x\n", env->mmu.srp);
+ dump_address_map(mon, env, env->mmu.srp);
+
+ monitor_printf(mon, "URP: 0x%08x\n", env->mmu.urp);
+ dump_address_map(mon, env, env->mmu.urp);
+}
+
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
{
CPUArchState *env1 = mon_get_cpu_env(mon);
@@ -19,7 +240,7 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
return;
}
- dump_mmu(mon, env1);
+ m68k_dump_mmu(mon, env1);
}
static const MonitorDef monitor_defs[] = {
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH-for-9.1 08/21] target/microblaze: Prefix MMU API with 'mb_'
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 07/21] target/m68k: Move MMU monitor commands from helper.c to monitor.c Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-23 13:13 ` Edgar E. Iglesias
2024-03-21 15:48 ` [PATCH-for-9.1 09/21] target/mips: Prefix MMU API with 'mips_' Philippe Mathieu-Daudé
` (12 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
MicroBlaze MMU API is exposed in "mmu.h". In order to avoid
name clashing with other targets, prefix the API with 'mb_'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/microblaze/mmu.h | 10 +++++-----
target/microblaze/cpu.c | 2 +-
target/microblaze/helper.c | 4 ++--
target/microblaze/mmu.c | 14 +++++++-------
target/microblaze/op_helper.c | 4 ++--
5 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
index 1068bd2d52..5b51e0a9c6 100644
--- a/target/microblaze/mmu.h
+++ b/target/microblaze/mmu.h
@@ -85,10 +85,10 @@ typedef struct {
} err;
} MicroBlazeMMULookup;
-unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
- target_ulong vaddr, MMUAccessType rw, int mmu_idx);
-uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
-void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
-void mmu_init(MicroBlazeMMU *mmu);
+unsigned int mb_mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
+ target_ulong vaddr, MMUAccessType rw, int mmu_idx);
+uint32_t mb_mmu_read(CPUMBState *env, bool ea, uint32_t rn);
+void mb_mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
+void mb_mmu_init(MicroBlazeMMU *mmu);
#endif
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 96c2b71f7f..59bfb5c45d 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -205,7 +205,7 @@ static void mb_cpu_reset_hold(Object *obj)
mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
#else
mb_cpu_write_msr(env, 0);
- mmu_init(&env->mmu);
+ mb_mmu_init(&env->mmu);
#endif
}
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index d25c9eb4d3..961687bae7 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -57,7 +57,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
return true;
}
- hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx);
+ hit = mb_mmu_translate(cpu, &lu, address, access_type, mmu_idx);
if (likely(hit)) {
uint32_t vaddr = address & TARGET_PAGE_MASK;
uint32_t paddr = lu.paddr + vaddr - lu.vaddr;
@@ -238,7 +238,7 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
attrs->secure = mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD);
if (mmu_idx != MMU_NOMMU_IDX) {
- hit = mmu_translate(cpu, &lu, addr, 0, 0);
+ hit = mb_mmu_translate(cpu, &lu, addr, 0, 0);
if (hit) {
vaddr = addr & TARGET_PAGE_MASK;
paddr = lu.paddr + vaddr - lu.vaddr;
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 234006634e..5fb8ee8418 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -74,8 +74,8 @@ static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
}
/* rw - 0 = read, 1 = write, 2 = fetch. */
-unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
- target_ulong vaddr, MMUAccessType rw, int mmu_idx)
+unsigned int mb_mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
+ target_ulong vaddr, MMUAccessType rw, int mmu_idx)
{
MicroBlazeMMU *mmu = &cpu->env.mmu;
unsigned int i, hit = 0;
@@ -175,7 +175,7 @@ done:
}
/* Writes/reads to the MMU's special regs end up here. */
-uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
+uint32_t mb_mmu_read(CPUMBState *env, bool ext, uint32_t rn)
{
MicroBlazeCPU *cpu = env_archcpu(env);
unsigned int i;
@@ -228,7 +228,7 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
return r;
}
-void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
+void mb_mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
{
MicroBlazeCPU *cpu = env_archcpu(env);
uint64_t tmp64;
@@ -304,8 +304,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
return;
}
- hit = mmu_translate(cpu, &lu, v & TLB_EPN_MASK,
- 0, cpu_mmu_index(env_cpu(env), false));
+ hit = mb_mmu_translate(cpu, &lu, v & TLB_EPN_MASK,
+ 0, cpu_mmu_index(env_cpu(env), false));
if (hit) {
env->mmu.regs[MMU_R_TLBX] = lu.idx;
} else {
@@ -319,7 +319,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
}
}
-void mmu_init(MicroBlazeMMU *mmu)
+void mb_mmu_init(MicroBlazeMMU *mmu)
{
int i;
for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index f6378030b7..58475a3af5 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -386,12 +386,12 @@ void helper_stackprot(CPUMBState *env, target_ulong addr)
/* Writes/reads to the MMU's special regs end up here. */
uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
{
- return mmu_read(env, ext, rn);
+ return mb_mmu_read(env, ext, rn);
}
void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
{
- mmu_write(env, ext, rn, v);
+ mb_mmu_write(env, ext, rn, v);
}
void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 08/21] target/microblaze: Prefix MMU API with 'mb_'
2024-03-21 15:48 ` [PATCH-for-9.1 08/21] target/microblaze: Prefix MMU API with 'mb_' Philippe Mathieu-Daudé
@ 2024-03-23 13:13 ` Edgar E. Iglesias
0 siblings, 0 replies; 46+ messages in thread
From: Edgar E. Iglesias @ 2024-03-23 13:13 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Artyom Tarasenko, Chris Wulff, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland
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On Thu, Mar 21, 2024 at 4:49 PM Philippe Mathieu-Daudé <philmd@linaro.org>
wrote:
> MicroBlaze MMU API is exposed in "mmu.h". In order to avoid
> name clashing with other targets, prefix the API with 'mb_'.
>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/microblaze/mmu.h | 10 +++++-----
> target/microblaze/cpu.c | 2 +-
> target/microblaze/helper.c | 4 ++--
> target/microblaze/mmu.c | 14 +++++++-------
> target/microblaze/op_helper.c | 4 ++--
> 5 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
> index 1068bd2d52..5b51e0a9c6 100644
> --- a/target/microblaze/mmu.h
> +++ b/target/microblaze/mmu.h
> @@ -85,10 +85,10 @@ typedef struct {
> } err;
> } MicroBlazeMMULookup;
>
> -unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
> - target_ulong vaddr, MMUAccessType rw, int
> mmu_idx);
> -uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
> -void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
> -void mmu_init(MicroBlazeMMU *mmu);
> +unsigned int mb_mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
> + target_ulong vaddr, MMUAccessType rw, int
> mmu_idx);
> +uint32_t mb_mmu_read(CPUMBState *env, bool ea, uint32_t rn);
> +void mb_mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
> +void mb_mmu_init(MicroBlazeMMU *mmu);
>
> #endif
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 96c2b71f7f..59bfb5c45d 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -205,7 +205,7 @@ static void mb_cpu_reset_hold(Object *obj)
> mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
> #else
> mb_cpu_write_msr(env, 0);
> - mmu_init(&env->mmu);
> + mb_mmu_init(&env->mmu);
> #endif
> }
>
> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
> index d25c9eb4d3..961687bae7 100644
> --- a/target/microblaze/helper.c
> +++ b/target/microblaze/helper.c
> @@ -57,7 +57,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int
> size,
> return true;
> }
>
> - hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx);
> + hit = mb_mmu_translate(cpu, &lu, address, access_type, mmu_idx);
> if (likely(hit)) {
> uint32_t vaddr = address & TARGET_PAGE_MASK;
> uint32_t paddr = lu.paddr + vaddr - lu.vaddr;
> @@ -238,7 +238,7 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs,
> vaddr addr,
> attrs->secure = mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD);
>
> if (mmu_idx != MMU_NOMMU_IDX) {
> - hit = mmu_translate(cpu, &lu, addr, 0, 0);
> + hit = mb_mmu_translate(cpu, &lu, addr, 0, 0);
> if (hit) {
> vaddr = addr & TARGET_PAGE_MASK;
> paddr = lu.paddr + vaddr - lu.vaddr;
> diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
> index 234006634e..5fb8ee8418 100644
> --- a/target/microblaze/mmu.c
> +++ b/target/microblaze/mmu.c
> @@ -74,8 +74,8 @@ static void mmu_change_pid(CPUMBState *env, unsigned int
> newpid)
> }
>
> /* rw - 0 = read, 1 = write, 2 = fetch. */
> -unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
> - target_ulong vaddr, MMUAccessType rw, int
> mmu_idx)
> +unsigned int mb_mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
> + target_ulong vaddr, MMUAccessType rw, int
> mmu_idx)
> {
> MicroBlazeMMU *mmu = &cpu->env.mmu;
> unsigned int i, hit = 0;
> @@ -175,7 +175,7 @@ done:
> }
>
> /* Writes/reads to the MMU's special regs end up here. */
> -uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
> +uint32_t mb_mmu_read(CPUMBState *env, bool ext, uint32_t rn)
> {
> MicroBlazeCPU *cpu = env_archcpu(env);
> unsigned int i;
> @@ -228,7 +228,7 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t
> rn)
> return r;
> }
>
> -void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
> +void mb_mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
> {
> MicroBlazeCPU *cpu = env_archcpu(env);
> uint64_t tmp64;
> @@ -304,8 +304,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn,
> uint32_t v)
> return;
> }
>
> - hit = mmu_translate(cpu, &lu, v & TLB_EPN_MASK,
> - 0, cpu_mmu_index(env_cpu(env), false));
> + hit = mb_mmu_translate(cpu, &lu, v & TLB_EPN_MASK,
> + 0, cpu_mmu_index(env_cpu(env), false));
> if (hit) {
> env->mmu.regs[MMU_R_TLBX] = lu.idx;
> } else {
> @@ -319,7 +319,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn,
> uint32_t v)
> }
> }
>
> -void mmu_init(MicroBlazeMMU *mmu)
> +void mb_mmu_init(MicroBlazeMMU *mmu)
> {
> int i;
> for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
> index f6378030b7..58475a3af5 100644
> --- a/target/microblaze/op_helper.c
> +++ b/target/microblaze/op_helper.c
> @@ -386,12 +386,12 @@ void helper_stackprot(CPUMBState *env, target_ulong
> addr)
> /* Writes/reads to the MMU's special regs end up here. */
> uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
> {
> - return mmu_read(env, ext, rn);
> + return mb_mmu_read(env, ext, rn);
> }
>
> void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn,
> uint32_t v)
> {
> - mmu_write(env, ext, rn, v);
> + mb_mmu_write(env, ext, rn, v);
> }
>
> void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
> --
> 2.41.0
>
>
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^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH-for-9.1 09/21] target/mips: Prefix MMU API with 'mips_'
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 08/21] target/microblaze: Prefix MMU API with 'mb_' Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 15:48 ` [PATCH-for-9.1 10/21] target/nios2: Prefix MMU API with 'nios2_' Philippe Mathieu-Daudé
` (11 subsequent siblings)
20 siblings, 0 replies; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé,
Aurelien Jarno, Aleksandar Rikalo
MIPS MMU API declared in tcg-internal.h has public linkage.
In order to avoid name clashing with other targets, prefix
the API with 'mips_'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/tcg-internal.h | 2 +-
target/mips/cpu.c | 2 +-
target/mips/tcg/sysemu/tlb_helper.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index aef032c48d..2dc9d9100f 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -43,7 +43,7 @@ void do_raise_exception(CPUMIPSState *env,
void mips_cpu_do_interrupt(CPUState *cpu);
bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
-void mmu_init(CPUMIPSState *env, const mips_def_t *def);
+void mips_mmu_init(CPUMIPSState *env, const mips_def_t *def);
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 8d8f690a53..8acf691b0b 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -485,7 +485,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
env->exception_base = (int32_t)0xBFC00000;
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
- mmu_init(env, env->cpu_model);
+ mips_mmu_init(env, env->cpu_model);
#endif
fpu_init(env, env->cpu_model);
mvp_init(env);
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index 119eae771e..0167b1162f 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -464,7 +464,7 @@ static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
}
-void mmu_init(CPUMIPSState *env, const mips_def_t *def)
+void mips_mmu_init(CPUMIPSState *env, const mips_def_t *def)
{
env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH-for-9.1 10/21] target/nios2: Prefix MMU API with 'nios2_'
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 09/21] target/mips: Prefix MMU API with 'mips_' Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 15:48 ` [PATCH-for-9.1 11/21] target/nios2: Move monitor commands to monitor.c Philippe Mathieu-Daudé
` (10 subsequent siblings)
20 siblings, 0 replies; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Nios2 MMU API is exposed in "mmu.h". In order to avoid
name clashing with other targets, prefix the API with
'nios2_'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/nios2/mmu.h | 11 +++++------
target/nios2/cpu.c | 2 +-
target/nios2/helper.c | 4 ++--
target/nios2/mmu.c | 7 +++----
4 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/nios2/mmu.h b/target/nios2/mmu.h
index 5b085900fb..5b16a5facf 100644
--- a/target/nios2/mmu.h
+++ b/target/nios2/mmu.h
@@ -42,11 +42,10 @@ typedef struct Nios2MMULookup {
int prot;
} Nios2MMULookup;
-void mmu_flip_um(CPUNios2State *env, unsigned int um);
-unsigned int mmu_translate(CPUNios2State *env,
- Nios2MMULookup *lu,
- target_ulong vaddr, int rw, int mmu_idx);
-void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v);
-void mmu_init(CPUNios2State *env);
+void nios2_mmu_flip_um(CPUNios2State *env, unsigned int um);
+unsigned int nios2_mmu_translate(CPUNios2State *env, Nios2MMULookup *lu,
+ target_ulong vaddr, int rw, int mmu_idx);
+void nios2_mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v);
+void nios2_mmu_init(CPUNios2State *env);
#endif /* NIOS2_MMU_H */
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 679aff5730..d2a9a0d4f1 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -113,7 +113,7 @@ static void nios2_cpu_initfn(Object *obj)
#if !defined(CONFIG_USER_ONLY)
Nios2CPU *cpu = NIOS2_CPU(obj);
- mmu_init(&cpu->env);
+ nios2_mmu_init(&cpu->env);
#endif
}
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index ac57121afc..2b6bdfbc55 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -268,7 +268,7 @@ hwaddr nios2_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
unsigned int hit;
if (cpu->mmu_present && (addr < 0xC0000000)) {
- hit = mmu_translate(env, &lu, addr, 0, 0);
+ hit = nios2_mmu_translate(env, &lu, addr, 0, 0);
if (hit) {
vaddr = addr & TARGET_PAGE_MASK;
paddr = lu.paddr + vaddr - lu.vaddr;
@@ -335,7 +335,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
/* Virtual page. */
- hit = mmu_translate(env, &lu, address, access_type, mmu_idx);
+ hit = nios2_mmu_translate(env, &lu, address, access_type, mmu_idx);
if (hit) {
vaddr = address & TARGET_PAGE_MASK;
paddr = lu.paddr + vaddr - lu.vaddr;
diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c
index d9b690b78e..272bd9fc6a 100644
--- a/target/nios2/mmu.c
+++ b/target/nios2/mmu.c
@@ -28,9 +28,8 @@
/* rw - 0 = read, 1 = write, 2 = fetch. */
-unsigned int mmu_translate(CPUNios2State *env,
- Nios2MMULookup *lu,
- target_ulong vaddr, int rw, int mmu_idx)
+unsigned int nios2_mmu_translate(CPUNios2State *env, Nios2MMULookup *lu,
+ target_ulong vaddr, int rw, int mmu_idx)
{
Nios2CPU *cpu = env_archcpu(env);
int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
@@ -180,7 +179,7 @@ void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v)
env->mmu.pteaddr_wr = v;
}
-void mmu_init(CPUNios2State *env)
+void nios2_mmu_init(CPUNios2State *env)
{
Nios2CPU *cpu = env_archcpu(env);
Nios2MMU *mmu = &env->mmu;
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH-for-9.1 11/21] target/nios2: Move monitor commands to monitor.c
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 10/21] target/nios2: Prefix MMU API with 'nios2_' Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 15:48 ` [PATCH-for-9.1 12/21] target/nios2: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
` (9 subsequent siblings)
20 siblings, 0 replies; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Move 'info tlb' monitor commands to monitor.c,
rename dump_mmu() as nios2_info_mmu().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/nios2/cpu.h | 2 +-
target/nios2/mmu.c | 27 ---------------------------
target/nios2/monitor.c | 28 +++++++++++++++++++++++++++-
3 files changed, 28 insertions(+), 29 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 4164a3432e..27e835cf40 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -250,7 +250,7 @@ static inline void nios2_update_crs(CPUNios2State *env)
void nios2_tcg_init(void);
void nios2_cpu_do_interrupt(CPUState *cs);
-void dump_mmu(CPUNios2State *env);
+void nios2_info_mmu(Monitor *mon, CPUNios2State *env);
void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
G_NORETURN void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type, int mmu_idx,
diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c
index 272bd9fc6a..278eba1b0a 100644
--- a/target/nios2/mmu.c
+++ b/target/nios2/mmu.c
@@ -19,7 +19,6 @@
*/
#include "qemu/osdep.h"
-#include "qemu/qemu-print.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "mmu.h"
@@ -187,29 +186,3 @@ void nios2_mmu_init(CPUNios2State *env)
mmu->tlb_entry_mask = (cpu->tlb_num_entries / cpu->tlb_num_ways) - 1;
mmu->tlb = g_new0(Nios2TLBEntry, cpu->tlb_num_entries);
}
-
-void dump_mmu(CPUNios2State *env)
-{
- Nios2CPU *cpu = env_archcpu(env);
- int i;
-
- qemu_printf("MMU: ways %d, entries %d, pid bits %d\n",
- cpu->tlb_num_ways, cpu->tlb_num_entries,
- cpu->pid_num_bits);
-
- for (i = 0; i < cpu->tlb_num_entries; i++) {
- Nios2TLBEntry *entry = &env->mmu.tlb[i];
- qemu_printf("TLB[%d] = %08X %08X %c VPN %05X "
- "PID %02X %c PFN %05X %c%c%c%c\n",
- i, entry->tag, entry->data,
- (entry->tag & (1 << 10)) ? 'V' : '-',
- entry->tag >> 12,
- entry->tag & ((1 << cpu->pid_num_bits) - 1),
- (entry->tag & (1 << 11)) ? 'G' : '-',
- FIELD_EX32(entry->data, CR_TLBACC, PFN),
- (entry->data & CR_TLBACC_C) ? 'C' : '-',
- (entry->data & CR_TLBACC_R) ? 'R' : '-',
- (entry->data & CR_TLBACC_W) ? 'W' : '-',
- (entry->data & CR_TLBACC_X) ? 'X' : '-');
- }
-}
diff --git a/target/nios2/monitor.c b/target/nios2/monitor.c
index 0152dec3fa..c6043769e4 100644
--- a/target/nios2/monitor.c
+++ b/target/nios2/monitor.c
@@ -22,14 +22,40 @@
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
+#include "qemu/qemu-print.h"
#include "cpu.h"
#include "monitor/monitor.h"
#include "monitor/hmp-target.h"
#include "monitor/hmp.h"
+void nios2_info_mmu(Monitor *mon, CPUNios2State *env)
+{
+ Nios2CPU *cpu = env_archcpu(env);
+
+ qemu_printf("MMU: ways %d, entries %d, pid bits %d\n",
+ cpu->tlb_num_ways, cpu->tlb_num_entries,
+ cpu->pid_num_bits);
+
+ for (int i = 0; i < cpu->tlb_num_entries; i++) {
+ Nios2TLBEntry *entry = &env->mmu.tlb[i];
+ qemu_printf("TLB[%d] = %08X %08X %c VPN %05X "
+ "PID %02X %c PFN %05X %c%c%c%c\n",
+ i, entry->tag, entry->data,
+ (entry->tag & (1 << 10)) ? 'V' : '-',
+ entry->tag >> 12,
+ entry->tag & ((1 << cpu->pid_num_bits) - 1),
+ (entry->tag & (1 << 11)) ? 'G' : '-',
+ FIELD_EX32(entry->data, CR_TLBACC, PFN),
+ (entry->data & CR_TLBACC_C) ? 'C' : '-',
+ (entry->data & CR_TLBACC_R) ? 'R' : '-',
+ (entry->data & CR_TLBACC_W) ? 'W' : '-',
+ (entry->data & CR_TLBACC_X) ? 'X' : '-');
+ }
+}
+
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
{
CPUArchState *env1 = mon_get_cpu_env(mon);
- dump_mmu(env1);
+ nios2_info_mmu(mon, env1);
}
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH-for-9.1 12/21] target/nios2: Replace qemu_printf() by monitor_printf() in monitor
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 11/21] target/nios2: Move monitor commands to monitor.c Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-04-24 7:38 ` Markus Armbruster
2024-03-21 15:48 ` [PATCH-for-9.1 13/21] target/ppc: " Philippe Mathieu-Daudé
` (8 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/nios2/monitor.c | 31 +++++++++++++++----------------
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/target/nios2/monitor.c b/target/nios2/monitor.c
index c6043769e4..983c16d7f8 100644
--- a/target/nios2/monitor.c
+++ b/target/nios2/monitor.c
@@ -22,7 +22,6 @@
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
-#include "qemu/qemu-print.h"
#include "cpu.h"
#include "monitor/monitor.h"
#include "monitor/hmp-target.h"
@@ -32,24 +31,24 @@ void nios2_info_mmu(Monitor *mon, CPUNios2State *env)
{
Nios2CPU *cpu = env_archcpu(env);
- qemu_printf("MMU: ways %d, entries %d, pid bits %d\n",
- cpu->tlb_num_ways, cpu->tlb_num_entries,
- cpu->pid_num_bits);
+ monitor_printf(mon, "MMU: ways %d, entries %d, pid bits %d\n",
+ cpu->tlb_num_ways, cpu->tlb_num_entries,
+ cpu->pid_num_bits);
for (int i = 0; i < cpu->tlb_num_entries; i++) {
Nios2TLBEntry *entry = &env->mmu.tlb[i];
- qemu_printf("TLB[%d] = %08X %08X %c VPN %05X "
- "PID %02X %c PFN %05X %c%c%c%c\n",
- i, entry->tag, entry->data,
- (entry->tag & (1 << 10)) ? 'V' : '-',
- entry->tag >> 12,
- entry->tag & ((1 << cpu->pid_num_bits) - 1),
- (entry->tag & (1 << 11)) ? 'G' : '-',
- FIELD_EX32(entry->data, CR_TLBACC, PFN),
- (entry->data & CR_TLBACC_C) ? 'C' : '-',
- (entry->data & CR_TLBACC_R) ? 'R' : '-',
- (entry->data & CR_TLBACC_W) ? 'W' : '-',
- (entry->data & CR_TLBACC_X) ? 'X' : '-');
+ monitor_printf(mon, "TLB[%d] = %08X %08X %c VPN %05X "
+ "PID %02X %c PFN %05X %c%c%c%c\n",
+ i, entry->tag, entry->data,
+ (entry->tag & (1 << 10)) ? 'V' : '-',
+ entry->tag >> 12,
+ entry->tag & ((1 << cpu->pid_num_bits) - 1),
+ (entry->tag & (1 << 11)) ? 'G' : '-',
+ FIELD_EX32(entry->data, CR_TLBACC, PFN),
+ (entry->data & CR_TLBACC_C) ? 'C' : '-',
+ (entry->data & CR_TLBACC_R) ? 'R' : '-',
+ (entry->data & CR_TLBACC_W) ? 'W' : '-',
+ (entry->data & CR_TLBACC_X) ? 'X' : '-');
}
}
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 12/21] target/nios2: Replace qemu_printf() by monitor_printf() in monitor
2024-03-21 15:48 ` [PATCH-for-9.1 12/21] target/nios2: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
@ 2024-04-24 7:38 ` Markus Armbruster
0 siblings, 0 replies; 46+ messages in thread
From: Markus Armbruster @ 2024-04-24 7:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Richard Henderson, qemu-ppc, Laurent Vivier,
Mark Cave-Ayland
Philippe Mathieu-Daudé <philmd@linaro.org> writes:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Same "why?" as for PATCH 05.
Reviewed-by: Markus Armbruster <armbru@redhat.com>
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH-for-9.1 13/21] target/ppc: Replace qemu_printf() by monitor_printf() in monitor
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 12/21] target/nios2: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-04-24 7:39 ` Markus Armbruster
2024-03-21 15:48 ` [PATCH-for-9.1 14/21] target/sh4: Extract sh4_dump_mmu() from hmp_info_tlb() Philippe Mathieu-Daudé
` (7 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/ppc/cpu.h | 2 +-
target/ppc/mmu_common.c | 147 +++++++++++++++++++-------------------
target/ppc/ppc-qmp-cmds.c | 2 +-
3 files changed, 77 insertions(+), 74 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 67e6b2effd..52ac667470 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2982,7 +2982,7 @@ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
}
#endif
-void dump_mmu(CPUPPCState *env);
+void ppc_dump_mmu(Monitor *mon, CPUPPCState *env);
void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 751403f1c8..ba8e91b949 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -32,6 +32,7 @@
#include "internal.h"
#include "mmu-book3s-v3.h"
#include "mmu-radix64.h"
+#include "monitor/monitor.h"
/* #define DUMP_PAGE_TABLES */
@@ -924,21 +925,21 @@ static const char *book3e_tsize_to_str[32] = {
"1T", "2T"
};
-static void mmubooke_dump_mmu(CPUPPCState *env)
+static void mmubooke_dump_mmu(Monitor *mon, CPUPPCState *env)
{
ppcemb_tlb_t *entry;
int i;
#ifdef CONFIG_KVM
if (kvm_enabled() && !env->kvm_sw_tlb) {
- qemu_printf("Cannot access KVM TLB\n");
+ monitor_puts(mon, "Cannot access KVM TLB\n");
return;
}
#endif
- qemu_printf("\nTLB:\n");
- qemu_printf("Effective Physical Size PID Prot "
- "Attr\n");
+ monitor_puts(mon, "\nTLB:\n");
+ monitor_puts(mon, "Effective Physical Size PID Prot "
+ "Attr\n");
entry = &env->tlb.tlbe[0];
for (i = 0; i < env->nb_tlb; i++, entry++) {
@@ -962,22 +963,22 @@ static void mmubooke_dump_mmu(CPUPPCState *env)
} else {
snprintf(size_buf, sizeof(size_buf), "%3" PRId64 "k", size / KiB);
}
- qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n",
- (uint64_t)ea, (uint64_t)pa, size_buf, (uint32_t)entry->PID,
- entry->prot, entry->attr);
+ monitor_printf(mon, "0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n",
+ (uint64_t)ea, (uint64_t)pa, size_buf, (uint32_t)entry->PID,
+ entry->prot, entry->attr);
}
}
-static void mmubooke206_dump_one_tlb(CPUPPCState *env, int tlbn, int offset,
- int tlbsize)
+static void mmubooke206_dump_one_tlb(Monitor *mon, CPUPPCState *env,
+ int tlbn, int offset, int tlbsize)
{
ppcmas_tlb_t *entry;
int i;
- qemu_printf("\nTLB%d:\n", tlbn);
- qemu_printf("Effective Physical Size TID TS SRWX"
- " URWX WIMGE U0123\n");
+ monitor_printf(mon, "\nTLB%d:\n", tlbn);
+ monitor_puts(mon, "Effective Physical Size TID TS SRWX"
+ " URWX WIMGE U0123\n");
entry = &env->tlb.tlbm[offset];
for (i = 0; i < tlbsize; i++, entry++) {
@@ -993,38 +994,38 @@ static void mmubooke206_dump_one_tlb(CPUPPCState *env, int tlbn, int offset,
ea = entry->mas2 & ~(size - 1);
pa = entry->mas7_3 & ~(size - 1);
- qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u S%c%c%c"
- " U%c%c%c %c%c%c%c%c U%c%c%c%c\n",
- (uint64_t)ea, (uint64_t)pa,
- book3e_tsize_to_str[tsize],
- (entry->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT,
- (entry->mas1 & MAS1_TS) >> MAS1_TS_SHIFT,
- entry->mas7_3 & MAS3_SR ? 'R' : '-',
- entry->mas7_3 & MAS3_SW ? 'W' : '-',
- entry->mas7_3 & MAS3_SX ? 'X' : '-',
- entry->mas7_3 & MAS3_UR ? 'R' : '-',
- entry->mas7_3 & MAS3_UW ? 'W' : '-',
- entry->mas7_3 & MAS3_UX ? 'X' : '-',
- entry->mas2 & MAS2_W ? 'W' : '-',
- entry->mas2 & MAS2_I ? 'I' : '-',
- entry->mas2 & MAS2_M ? 'M' : '-',
- entry->mas2 & MAS2_G ? 'G' : '-',
- entry->mas2 & MAS2_E ? 'E' : '-',
- entry->mas7_3 & MAS3_U0 ? '0' : '-',
- entry->mas7_3 & MAS3_U1 ? '1' : '-',
- entry->mas7_3 & MAS3_U2 ? '2' : '-',
- entry->mas7_3 & MAS3_U3 ? '3' : '-');
+ monitor_printf(mon, "0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u S%c%c%c"
+ " U%c%c%c %c%c%c%c%c U%c%c%c%c\n",
+ (uint64_t)ea, (uint64_t)pa,
+ book3e_tsize_to_str[tsize],
+ (entry->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT,
+ (entry->mas1 & MAS1_TS) >> MAS1_TS_SHIFT,
+ entry->mas7_3 & MAS3_SR ? 'R' : '-',
+ entry->mas7_3 & MAS3_SW ? 'W' : '-',
+ entry->mas7_3 & MAS3_SX ? 'X' : '-',
+ entry->mas7_3 & MAS3_UR ? 'R' : '-',
+ entry->mas7_3 & MAS3_UW ? 'W' : '-',
+ entry->mas7_3 & MAS3_UX ? 'X' : '-',
+ entry->mas2 & MAS2_W ? 'W' : '-',
+ entry->mas2 & MAS2_I ? 'I' : '-',
+ entry->mas2 & MAS2_M ? 'M' : '-',
+ entry->mas2 & MAS2_G ? 'G' : '-',
+ entry->mas2 & MAS2_E ? 'E' : '-',
+ entry->mas7_3 & MAS3_U0 ? '0' : '-',
+ entry->mas7_3 & MAS3_U1 ? '1' : '-',
+ entry->mas7_3 & MAS3_U2 ? '2' : '-',
+ entry->mas7_3 & MAS3_U3 ? '3' : '-');
}
}
-static void mmubooke206_dump_mmu(CPUPPCState *env)
+static void mmubooke206_dump_mmu(Monitor *mon, CPUPPCState *env)
{
int offset = 0;
int i;
#ifdef CONFIG_KVM
if (kvm_enabled() && !env->kvm_sw_tlb) {
- qemu_printf("Cannot access KVM TLB\n");
+ monitor_puts(mon, "Cannot access KVM TLB\n");
return;
}
#endif
@@ -1036,12 +1037,12 @@ static void mmubooke206_dump_mmu(CPUPPCState *env)
continue;
}
- mmubooke206_dump_one_tlb(env, i, offset, size);
+ mmubooke206_dump_one_tlb(mon, env, i, offset, size);
offset += size;
}
}
-static void mmu6xx_dump_BATs(CPUPPCState *env, int type)
+static void mmu6xx_dump_BATs(Monitor *mon, CPUPPCState *env, int type)
{
target_ulong *BATlt, *BATut, *BATu, *BATl;
target_ulong BEPIl, BEPIu, bl;
@@ -1064,51 +1065,53 @@ static void mmu6xx_dump_BATs(CPUPPCState *env, int type)
BEPIu = *BATu & 0xF0000000;
BEPIl = *BATu & 0x0FFE0000;
bl = (*BATu & 0x00001FFC) << 15;
- qemu_printf("%s BAT%d BATu " TARGET_FMT_lx
- " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
- TARGET_FMT_lx " " TARGET_FMT_lx "\n",
- type == ACCESS_CODE ? "code" : "data", i,
- *BATu, *BATl, BEPIu, BEPIl, bl);
+ monitor_printf(mon, "%s BAT%d BATu " TARGET_FMT_lx
+ " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
+ TARGET_FMT_lx " " TARGET_FMT_lx "\n",
+ type == ACCESS_CODE ? "code" : "data", i,
+ *BATu, *BATl, BEPIu, BEPIl, bl);
}
}
-static void mmu6xx_dump_mmu(CPUPPCState *env)
+static void mmu6xx_dump_mmu(Monitor *mon, CPUPPCState *env)
{
PowerPCCPU *cpu = env_archcpu(env);
ppc6xx_tlb_t *tlb;
target_ulong sr;
int type, way, entry, i;
- qemu_printf("HTAB base = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_base(cpu));
- qemu_printf("HTAB mask = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_mask(cpu));
+ monitor_printf(mon, "HTAB base = 0x%"HWADDR_PRIx"\n",
+ ppc_hash32_hpt_base(cpu));
+ monitor_printf(mon, "HTAB mask = 0x%"HWADDR_PRIx"\n",
+ ppc_hash32_hpt_mask(cpu));
- qemu_printf("\nSegment registers:\n");
+ monitor_puts(mon, "\nSegment registers:\n");
for (i = 0; i < 32; i++) {
sr = env->sr[i];
if (sr & 0x80000000) {
- qemu_printf("%02d T=%d Ks=%d Kp=%d BUID=0x%03x "
- "CNTLR_SPEC=0x%05x\n", i,
- sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
- sr & 0x20000000 ? 1 : 0, (uint32_t)((sr >> 20) & 0x1FF),
- (uint32_t)(sr & 0xFFFFF));
+ monitor_printf(mon, "%02d T=%d Ks=%d Kp=%d BUID=0x%03x "
+ "CNTLR_SPEC=0x%05x\n", i,
+ sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
+ sr & 0x20000000 ? 1 : 0, (uint32_t)((sr >> 20) & 0x1FF),
+ (uint32_t)(sr & 0xFFFFF));
} else {
- qemu_printf("%02d T=%d Ks=%d Kp=%d N=%d VSID=0x%06x\n", i,
- sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
- sr & 0x20000000 ? 1 : 0, sr & 0x10000000 ? 1 : 0,
- (uint32_t)(sr & 0x00FFFFFF));
+ monitor_printf(mon, "%02d T=%d Ks=%d Kp=%d N=%d VSID=0x%06x\n", i,
+ sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
+ sr & 0x20000000 ? 1 : 0, sr & 0x10000000 ? 1 : 0,
+ (uint32_t)(sr & 0x00FFFFFF));
}
}
- qemu_printf("\nBATs:\n");
- mmu6xx_dump_BATs(env, ACCESS_INT);
- mmu6xx_dump_BATs(env, ACCESS_CODE);
+ monitor_puts(mon, "\nBATs:\n");
+ mmu6xx_dump_BATs(mon, env, ACCESS_INT);
+ mmu6xx_dump_BATs(mon, env, ACCESS_CODE);
if (env->id_tlbs != 1) {
- qemu_printf("ERROR: 6xx MMU should have separated TLB"
- " for code and data\n");
+ monitor_puts(mon, "ERROR: 6xx MMU should have separated TLB"
+ " for code and data\n");
}
- qemu_printf("\nTLBs [EPN EPN + SIZE]\n");
+ monitor_puts(mon, "\nTLBs [EPN EPN + SIZE]\n");
for (type = 0; type < 2; type++) {
for (way = 0; way < env->nb_ways; way++) {
@@ -1117,28 +1120,28 @@ static void mmu6xx_dump_mmu(CPUPPCState *env)
entry++) {
tlb = &env->tlb.tlb6[entry];
- qemu_printf("%s TLB %02d/%02d way:%d %s ["
- TARGET_FMT_lx " " TARGET_FMT_lx "]\n",
- type ? "code" : "data", entry % env->nb_tlb,
- env->nb_tlb, way,
- pte_is_valid(tlb->pte0) ? "valid" : "inval",
- tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE);
+ monitor_printf(mon, "%s TLB %02d/%02d way:%d %s ["
+ TARGET_FMT_lx " " TARGET_FMT_lx "]\n",
+ type ? "code" : "data", entry % env->nb_tlb,
+ env->nb_tlb, way,
+ pte_is_valid(tlb->pte0) ? "valid" : "inval",
+ tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE);
}
}
}
}
-void dump_mmu(CPUPPCState *env)
+void ppc_dump_mmu(Monitor *mon, CPUPPCState *env)
{
switch (env->mmu_model) {
case POWERPC_MMU_BOOKE:
- mmubooke_dump_mmu(env);
+ mmubooke_dump_mmu(mon, env);
break;
case POWERPC_MMU_BOOKE206:
- mmubooke206_dump_mmu(env);
+ mmubooke206_dump_mmu(mon, env);
break;
case POWERPC_MMU_SOFT_6xx:
- mmu6xx_dump_mmu(env);
+ mmu6xx_dump_mmu(mon, env);
break;
#if defined(TARGET_PPC64)
case POWERPC_MMU_64B:
diff --git a/target/ppc/ppc-qmp-cmds.c b/target/ppc/ppc-qmp-cmds.c
index a25d86a8d1..e798c30f91 100644
--- a/target/ppc/ppc-qmp-cmds.c
+++ b/target/ppc/ppc-qmp-cmds.c
@@ -88,7 +88,7 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
monitor_printf(mon, "No CPU available\n");
return;
}
- dump_mmu(env1);
+ ppc_dump_mmu(mon, env1);
}
const MonitorDef monitor_defs[] = {
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 13/21] target/ppc: Replace qemu_printf() by monitor_printf() in monitor
2024-03-21 15:48 ` [PATCH-for-9.1 13/21] target/ppc: " Philippe Mathieu-Daudé
@ 2024-04-24 7:39 ` Markus Armbruster
0 siblings, 0 replies; 46+ messages in thread
From: Markus Armbruster @ 2024-04-24 7:39 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Richard Henderson, qemu-ppc, Laurent Vivier,
Mark Cave-Ayland
Philippe Mathieu-Daudé <philmd@linaro.org> writes:
> Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
My review comments to PATCH 05 apply.
Reviewed-by: Markus Armbruster <armbru@redhat.com>
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH-for-9.1 14/21] target/sh4: Extract sh4_dump_mmu() from hmp_info_tlb()
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 13/21] target/ppc: " Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 15:48 ` [PATCH-for-9.0? 15/21] target/sparc: Fix string format errors when DEBUG_MMU is defined Philippe Mathieu-Daudé
` (6 subsequent siblings)
20 siblings, 0 replies; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Extract sh4_dump_mmu() from hmp_info_tlb(), replacing
monitor_printf(FIXED_STRING_WITHOUT_FORMAT) by monitor_puts().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/sh4/cpu.h | 2 ++
target/sh4/monitor.c | 22 +++++++++++++++-------
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 9211da6bde..4e2e9ffd66 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -385,4 +385,6 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc,
#endif
}
+void sh4_dump_mmu(Monitor *mon, CPUSH4State *env);
+
#endif /* SH4_CPU_H */
diff --git a/target/sh4/monitor.c b/target/sh4/monitor.c
index 2da6a5426e..1befb42b07 100644
--- a/target/sh4/monitor.c
+++ b/target/sh4/monitor.c
@@ -39,20 +39,28 @@ static void print_tlb(Monitor *mon, int idx, tlb_t *tlb)
tlb->d, tlb->wt);
}
+void sh4_dump_mmu(Monitor *mon, CPUSH4State *env)
+{
+ int i;
+
+ monitor_puts(mon, "ITLB:\n");
+ for (i = 0 ; i < ITLB_SIZE ; i++) {
+ print_tlb (mon, i, &env->itlb[i]);
+ }
+ monitor_puts(mon, "UTLB:\n");
+ for (i = 0 ; i < UTLB_SIZE ; i++) {
+ print_tlb (mon, i, &env->utlb[i]);
+ }
+}
+
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
{
CPUArchState *env = mon_get_cpu_env(mon);
- int i;
if (!env) {
monitor_printf(mon, "No CPU available\n");
return;
}
- monitor_printf (mon, "ITLB:\n");
- for (i = 0 ; i < ITLB_SIZE ; i++)
- print_tlb (mon, i, &env->itlb[i]);
- monitor_printf (mon, "UTLB:\n");
- for (i = 0 ; i < UTLB_SIZE ; i++)
- print_tlb (mon, i, &env->utlb[i]);
+ sh4_dump_mmu(mon, env);
}
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH-for-9.0? 15/21] target/sparc: Fix string format errors when DEBUG_MMU is defined
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 14/21] target/sh4: Extract sh4_dump_mmu() from hmp_info_tlb() Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 15:48 ` [PATCH-for-9.1 16/21] target/sparc: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
` (5 subsequent siblings)
20 siblings, 0 replies; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Fix when building with DEBUG_MMU:
target/sparc/ldst_helper.c:245:72: error: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Werror,-Wformat]
DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr,
~~~ ^~~~~
%llx
target/sparc/ldst_helper.c:1736:60: error: no member named 'immuregs' in 'struct CPUArchState'
PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
~~~ ^
target/sparc/ldst_helper.c:1820:60: error: no member named 'dmmuregs' in 'struct CPUArchState'
PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
~~~ ^
Fixes: 96df2bc99f ("target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/sparc/ldst_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index e581bb42ac..064390d1d4 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -242,8 +242,8 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
if (new_vaddr == vaddr
|| (new_vaddr < vaddr + size
&& vaddr < new_vaddr + new_size)) {
- DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr,
- new_vaddr);
+ DPRINTF_MMU("auto demap entry [%d] %"PRIx64"->%"PRIx64"\n",
+ i, vaddr, new_vaddr);
replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
return;
}
@@ -1733,7 +1733,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
if (oldreg != env->immu.mmuregs[reg]) {
DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
- PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
+ PRIx64 "\n", reg, oldreg, env->immu.mmuregs[reg]);
}
#ifdef DEBUG_MMU
dump_mmu(env);
@@ -1817,7 +1817,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
if (oldreg != env->dmmu.mmuregs[reg]) {
DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
- PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
+ PRIx64 "\n", reg, oldreg, env->dmmu.mmuregs[reg]);
}
#ifdef DEBUG_MMU
dump_mmu(env);
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH-for-9.1 16/21] target/sparc: Replace qemu_printf() by monitor_printf() in monitor
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.0? 15/21] target/sparc: Fix string format errors when DEBUG_MMU is defined Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-04-24 7:44 ` Markus Armbruster
2024-03-21 15:48 ` [PATCH-for-9.1 17/21] target/xtensa: Prefix MMU API with 'xtensa_' Philippe Mathieu-Daudé
` (4 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Replace qemu_printf() by monitor_printf() in monitor.c.
Rename dump_mmu() as sparc_dump_mmu().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/sparc/cpu.h | 2 +-
target/sparc/ldst_helper.c | 18 +++----
target/sparc/mmu_helper.c | 102 ++++++++++++++++++-------------------
target/sparc/monitor.c | 2 +-
4 files changed, 62 insertions(+), 62 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index f3cdd17c62..55589c8ae4 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -601,7 +601,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
-void dump_mmu(CPUSPARCState *env);
+void sparc_dump_mmu(Monitor *mon, CPUSPARCState *env);
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 064390d1d4..44f8b2bb7a 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -195,7 +195,7 @@ static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
replace_tlb_entry(&tlb[i], 0, 0, env1);
#ifdef DEBUG_MMU
DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
- dump_mmu(env1);
+ sparc_dump_mmu(env1);
#endif
}
}
@@ -257,7 +257,7 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
#ifdef DEBUG_MMU
DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
- dump_mmu(env1);
+ sparc_dump_mmu(env1);
#endif
return;
}
@@ -276,7 +276,7 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
#ifdef DEBUG_MMU
DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
strmmu, (replace_used ? "used" : "unused"), i);
- dump_mmu(env1);
+ sparc_dump_mmu(env1);
#endif
return;
}
@@ -995,7 +995,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
break;
}
#ifdef DEBUG_MMU
- dump_mmu(env);
+ sparc_dump_mmu(env);
#endif
}
break;
@@ -1050,7 +1050,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
reg, oldreg, env->mmuregs[reg]);
}
#ifdef DEBUG_MMU
- dump_mmu(env);
+ sparc_dump_mmu(env);
#endif
}
break;
@@ -1736,7 +1736,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
PRIx64 "\n", reg, oldreg, env->immu.mmuregs[reg]);
}
#ifdef DEBUG_MMU
- dump_mmu(env);
+ sparc_dump_mmu(env);
#endif
return;
}
@@ -1760,7 +1760,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
}
#ifdef DEBUG_MMU
DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
- dump_mmu(env);
+ sparc_dump_mmu(env);
#endif
return;
}
@@ -1820,7 +1820,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
PRIx64 "\n", reg, oldreg, env->dmmu.mmuregs[reg]);
}
#ifdef DEBUG_MMU
- dump_mmu(env);
+ sparc_dump_mmu(env);
#endif
return;
}
@@ -1842,7 +1842,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
}
#ifdef DEBUG_MMU
DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
- dump_mmu(env);
+ sparc_dump_mmu(env);
#endif
return;
}
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index ad1591d9fd..f325c9a4cc 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -21,7 +21,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
-#include "qemu/qemu-print.h"
+#include "monitor/monitor.h"
#include "trace.h"
/* Sparc MMU emulation */
@@ -344,7 +344,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
return 0;
}
-void dump_mmu(CPUSPARCState *env)
+void sparc_dump_mmu(Monitor *mon, CPUSPARCState *env)
{
CPUState *cs = env_cpu(env);
target_ulong va, va1, va2;
@@ -352,29 +352,29 @@ void dump_mmu(CPUSPARCState *env)
hwaddr pa;
uint32_t pde;
- qemu_printf("Root ptr: " HWADDR_FMT_plx ", ctx: %d\n",
- (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
+ monitor_printf(mon, "Root ptr: " HWADDR_FMT_plx ", ctx: %d\n",
+ (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
pde = mmu_probe(env, va, 2);
if (pde) {
pa = cpu_get_phys_page_debug(cs, va);
- qemu_printf("VA: " TARGET_FMT_lx ", PA: " HWADDR_FMT_plx
- " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
+ monitor_printf(mon, "VA: " TARGET_FMT_lx ", PA: " HWADDR_FMT_plx
+ " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
pde = mmu_probe(env, va1, 1);
if (pde) {
pa = cpu_get_phys_page_debug(cs, va1);
- qemu_printf(" VA: " TARGET_FMT_lx ", PA: "
- HWADDR_FMT_plx " PDE: " TARGET_FMT_lx "\n",
- va1, pa, pde);
+ monitor_printf(mon, " VA: " TARGET_FMT_lx ", PA: "
+ HWADDR_FMT_plx " PDE: " TARGET_FMT_lx "\n",
+ va1, pa, pde);
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
pde = mmu_probe(env, va2, 0);
if (pde) {
pa = cpu_get_phys_page_debug(cs, va2);
- qemu_printf(" VA: " TARGET_FMT_lx ", PA: "
- HWADDR_FMT_plx " PTE: "
- TARGET_FMT_lx "\n",
- va2, pa, pde);
+ monitor_printf(mon, " VA: " TARGET_FMT_lx ", PA: "
+ HWADDR_FMT_plx " PTE: "
+ TARGET_FMT_lx "\n",
+ va2, pa, pde);
}
}
}
@@ -777,21 +777,21 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
cpu_loop_exit_restore(cs, retaddr);
}
-void dump_mmu(CPUSPARCState *env)
+void sparc_dump_mmu(Monitor *mon, CPUSPARCState *env)
{
unsigned int i;
const char *mask;
- qemu_printf("MMU contexts: Primary: %" PRId64 ", Secondary: %"
- PRId64 "\n",
- env->dmmu.mmu_primary_context,
- env->dmmu.mmu_secondary_context);
- qemu_printf("DMMU Tag Access: %" PRIx64 ", TSB Tag Target: %" PRIx64
- "\n", env->dmmu.tag_access, env->dmmu.tsb_tag_target);
+ monitor_printf(mon, "MMU contexts: Primary: %" PRId64 ", Secondary: %"
+ PRId64 "\n",
+ env->dmmu.mmu_primary_context,
+ env->dmmu.mmu_secondary_context);
+ monitor_printf(mon, "DMMU Tag Access: %" PRIx64 ", TSB Tag Target: %" PRIx64
+ "\n", env->dmmu.tag_access, env->dmmu.tsb_tag_target);
if ((env->lsu & DMMU_E) == 0) {
- qemu_printf("DMMU disabled\n");
+ monitor_printf(mon, "DMMU disabled\n");
} else {
- qemu_printf("DMMU dump\n");
+ monitor_printf(mon, "DMMU dump\n");
for (i = 0; i < 64; i++) {
switch (TTE_PGSIZE(env->dtlb[i].tte)) {
default:
@@ -809,28 +809,28 @@ void dump_mmu(CPUSPARCState *env)
break;
}
if (TTE_IS_VALID(env->dtlb[i].tte)) {
- qemu_printf("[%02u] VA: %" PRIx64 ", PA: %llx"
- ", %s, %s, %s, %s, ie %s, ctx %" PRId64 " %s\n",
- i,
- env->dtlb[i].tag & (uint64_t)~0x1fffULL,
- TTE_PA(env->dtlb[i].tte),
- mask,
- TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user",
- TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO",
- TTE_IS_LOCKED(env->dtlb[i].tte) ?
- "locked" : "unlocked",
- TTE_IS_IE(env->dtlb[i].tte) ?
- "yes" : "no",
- env->dtlb[i].tag & (uint64_t)0x1fffULL,
- TTE_IS_GLOBAL(env->dtlb[i].tte) ?
- "global" : "local");
+ monitor_printf(mon, "[%02u] VA: %" PRIx64 ", PA: %llx"
+ ", %s, %s, %s, %s, ie %s, ctx %" PRId64 " %s\n",
+ i,
+ env->dtlb[i].tag & (uint64_t)~0x1fffULL,
+ TTE_PA(env->dtlb[i].tte),
+ mask,
+ TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user",
+ TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO",
+ TTE_IS_LOCKED(env->dtlb[i].tte) ?
+ "locked" : "unlocked",
+ TTE_IS_IE(env->dtlb[i].tte) ?
+ "yes" : "no",
+ env->dtlb[i].tag & (uint64_t)0x1fffULL,
+ TTE_IS_GLOBAL(env->dtlb[i].tte) ?
+ "global" : "local");
}
}
}
if ((env->lsu & IMMU_E) == 0) {
- qemu_printf("IMMU disabled\n");
+ monitor_printf(mon, "IMMU disabled\n");
} else {
- qemu_printf("IMMU dump\n");
+ monitor_printf(mon, "IMMU dump\n");
for (i = 0; i < 64; i++) {
switch (TTE_PGSIZE(env->itlb[i].tte)) {
default:
@@ -848,18 +848,18 @@ void dump_mmu(CPUSPARCState *env)
break;
}
if (TTE_IS_VALID(env->itlb[i].tte)) {
- qemu_printf("[%02u] VA: %" PRIx64 ", PA: %llx"
- ", %s, %s, %s, ctx %" PRId64 " %s\n",
- i,
- env->itlb[i].tag & (uint64_t)~0x1fffULL,
- TTE_PA(env->itlb[i].tte),
- mask,
- TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user",
- TTE_IS_LOCKED(env->itlb[i].tte) ?
- "locked" : "unlocked",
- env->itlb[i].tag & (uint64_t)0x1fffULL,
- TTE_IS_GLOBAL(env->itlb[i].tte) ?
- "global" : "local");
+ monitor_printf(mon, "[%02u] VA: %" PRIx64 ", PA: %llx"
+ ", %s, %s, %s, ctx %" PRId64 " %s\n",
+ i,
+ env->itlb[i].tag & (uint64_t)~0x1fffULL,
+ TTE_PA(env->itlb[i].tte),
+ mask,
+ TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user",
+ TTE_IS_LOCKED(env->itlb[i].tte) ?
+ "locked" : "unlocked",
+ env->itlb[i].tag & (uint64_t)0x1fffULL,
+ TTE_IS_GLOBAL(env->itlb[i].tte) ?
+ "global" : "local");
}
}
}
diff --git a/target/sparc/monitor.c b/target/sparc/monitor.c
index 73f15aa272..4fcdf75932 100644
--- a/target/sparc/monitor.c
+++ b/target/sparc/monitor.c
@@ -36,7 +36,7 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
monitor_printf(mon, "No CPU available\n");
return;
}
- dump_mmu(env1);
+ sparc_dump_mmu(mon, env1);
}
#ifndef TARGET_SPARC64
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 16/21] target/sparc: Replace qemu_printf() by monitor_printf() in monitor
2024-03-21 15:48 ` [PATCH-for-9.1 16/21] target/sparc: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
@ 2024-04-24 7:44 ` Markus Armbruster
2024-04-24 12:08 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 46+ messages in thread
From: Markus Armbruster @ 2024-04-24 7:44 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Richard Henderson, qemu-ppc, Laurent Vivier,
Mark Cave-Ayland
Philippe Mathieu-Daudé <philmd@linaro.org> writes:
> Replace qemu_printf() by monitor_printf() in monitor.c.
> Rename dump_mmu() as sparc_dump_mmu().
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Same "why?" and "suggest to mention passing current monitor" as for
PATCH 05.
In addition:
> ---
> target/sparc/cpu.h | 2 +-
> target/sparc/ldst_helper.c | 18 +++----
> target/sparc/mmu_helper.c | 102 ++++++++++++++++++-------------------
> target/sparc/monitor.c | 2 +-
> 4 files changed, 62 insertions(+), 62 deletions(-)
>
> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
> index f3cdd17c62..55589c8ae4 100644
> --- a/target/sparc/cpu.h
> +++ b/target/sparc/cpu.h
> @@ -601,7 +601,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> bool probe, uintptr_t retaddr);
> target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
> -void dump_mmu(CPUSPARCState *env);
> +void sparc_dump_mmu(Monitor *mon, CPUSPARCState *env);
>
> #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
> int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
> diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
> index 064390d1d4..44f8b2bb7a 100644
> --- a/target/sparc/ldst_helper.c
> +++ b/target/sparc/ldst_helper.c
> @@ -195,7 +195,7 @@ static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
> replace_tlb_entry(&tlb[i], 0, 0, env1);
> #ifdef DEBUG_MMU
> DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
> - dump_mmu(env1);
> + sparc_dump_mmu(env1);
You add a parameter below. I don't think this compiles :)
Several more instances follow.
> #endif
> }
> }
[...]
With that fixed
Reviewed-by: Markus Armbruster <armbru@redhat.com>
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 16/21] target/sparc: Replace qemu_printf() by monitor_printf() in monitor
2024-04-24 7:44 ` Markus Armbruster
@ 2024-04-24 12:08 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-04-24 12:08 UTC (permalink / raw)
To: Markus Armbruster
Cc: qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Richard Henderson, qemu-ppc, Laurent Vivier,
Mark Cave-Ayland
On 24/4/24 09:44, Markus Armbruster wrote:
> Philippe Mathieu-Daudé <philmd@linaro.org> writes:
>
>> Replace qemu_printf() by monitor_printf() in monitor.c.
>> Rename dump_mmu() as sparc_dump_mmu().
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>
> Same "why?" and "suggest to mention passing current monitor" as for
> PATCH 05.
>
> In addition:
>
>> ---
>> target/sparc/cpu.h | 2 +-
>> target/sparc/ldst_helper.c | 18 +++----
>> target/sparc/mmu_helper.c | 102 ++++++++++++++++++-------------------
>> target/sparc/monitor.c | 2 +-
>> 4 files changed, 62 insertions(+), 62 deletions(-)
>>
>> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
>> index f3cdd17c62..55589c8ae4 100644
>> --- a/target/sparc/cpu.h
>> +++ b/target/sparc/cpu.h
>> @@ -601,7 +601,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
>> MMUAccessType access_type, int mmu_idx,
>> bool probe, uintptr_t retaddr);
>> target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
>> -void dump_mmu(CPUSPARCState *env);
>> +void sparc_dump_mmu(Monitor *mon, CPUSPARCState *env);
>>
>> #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
>> int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
>> diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
>> index 064390d1d4..44f8b2bb7a 100644
>> --- a/target/sparc/ldst_helper.c
>> +++ b/target/sparc/ldst_helper.c
>> @@ -195,7 +195,7 @@ static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
>> replace_tlb_entry(&tlb[i], 0, 0, env1);
>> #ifdef DEBUG_MMU
>> DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
>> - dump_mmu(env1);
>> + sparc_dump_mmu(env1);
>
> You add a parameter below. I don't think this compiles :)
It does compile, because this is dead code (guarded
by undefined DEBUG_MMU). Good example that dead code
tends to bitrot, thanks for noticing.
>
> Several more instances follow.
>
>> #endif
>> }
>> }
>
> [...]
>
> With that fixed
> Reviewed-by: Markus Armbruster <armbru@redhat.com>
>
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH-for-9.1 17/21] target/xtensa: Prefix MMU API with 'xtensa_'
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 16/21] target/sparc: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 15:48 ` [PATCH-for-9.1 18/21] target/xtensa: Extract MMU API to new mmu.c/mmu.h files Philippe Mathieu-Daudé
` (3 subsequent siblings)
20 siblings, 0 replies; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
In order to extract the MMU API to a new "mmu.h" header,
prefix it with the target name.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/xtensa/cpu.h | 4 ++--
target/xtensa/cpu.c | 2 +-
target/xtensa/mmu_helper.c | 41 +++++++++++++++++++++-----------------
target/xtensa/monitor.c | 2 +-
4 files changed, 27 insertions(+), 22 deletions(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 6b8d0636d2..b2cfc78e9d 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -692,8 +692,8 @@ static inline int xtensa_get_cring(const CPUXtensaState *env)
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access);
-void reset_mmu(CPUXtensaState *env);
-void dump_mmu(CPUXtensaState *env);
+void xtensa_reset_mmu(CPUXtensaState *env);
+void xtensa_dump_mmu(CPUXtensaState *env);
static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
{
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 875cf843c9..ae0c4aab24 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -130,7 +130,7 @@ static void xtensa_cpu_reset_hold(Object *obj)
env->exclusive_addr = -1;
#ifndef CONFIG_USER_ONLY
- reset_mmu(env);
+ xtensa_reset_mmu(env);
cs->halted = env->runstall;
#endif
set_no_signaling_nans(!dfpu, &env->fp_status);
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index 47063b0a57..31ee3fa957 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -139,7 +139,8 @@ static uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env,
* Get bit mask for the 'VPN without index' field.
* See ISA, 4.6.5.6, data format for RxTLB0
*/
-static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
+static uint32_t xtensa_get_vpn_mask(const CPUXtensaState *env, bool dtlb,
+ uint32_t way)
{
if (way < 4) {
bool is32 = (dtlb ?
@@ -168,9 +169,10 @@ static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
* Split virtual address into VPN (with index) and entry index
* for the given TLB way
*/
-static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v,
- bool dtlb, uint32_t *vpn,
- uint32_t wi, uint32_t *ei)
+static void xtensa_split_tlb_entry_spec_way(const CPUXtensaState *env,
+ uint32_t v,
+ bool dtlb, uint32_t *vpn,
+ uint32_t wi, uint32_t *ei)
{
bool varway56 = dtlb ?
env->config->dtlb.varway56 :
@@ -224,13 +226,15 @@ static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v,
* Split TLB address into TLB way, entry index and VPN (with index).
* See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
*/
-static bool split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
- uint32_t *vpn, uint32_t *wi, uint32_t *ei)
+static bool xtensa_split_tlb_entry_spec(CPUXtensaState *env,
+ uint32_t v, bool dtlb,
+ uint32_t *vpn, uint32_t *wi,
+ uint32_t *ei)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
*wi = v & (dtlb ? 0xf : 0x7);
if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nways)) {
- split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
+ xtensa_split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
return true;
} else {
return false;
@@ -254,14 +258,14 @@ static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb,
env->itlb[wi] + ei;
}
-static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
+static xtensa_tlb_entry *xtensa_get_tlb_entry(CPUXtensaState *env,
uint32_t v, bool dtlb, uint32_t *pwi)
{
uint32_t vpn;
uint32_t wi;
uint32_t ei;
- if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) {
+ if (xtensa_split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) {
if (pwi) {
*pwi = wi;
}
@@ -405,7 +409,7 @@ static void reset_tlb_region_way0(CPUXtensaState *env,
}
}
-void reset_mmu(CPUXtensaState *env)
+void xtensa_reset_mmu(CPUXtensaState *env)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
env->sregs[RASID] = 0x04030201;
@@ -470,7 +474,7 @@ static int xtensa_tlb_lookup(const CPUXtensaState *env,
for (wi = 0; wi < tlb->nways; ++wi) {
uint32_t vpn;
uint32_t ei;
- split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
+ xtensa_split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
unsigned ring = get_ring(env, entry[wi][ei].asid);
if (ring < 4) {
@@ -493,10 +497,11 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
- const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
+ const xtensa_tlb_entry *entry = xtensa_get_tlb_entry(env, v, dtlb, &wi);
if (entry) {
- return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
+ return (entry->vaddr & xtensa_get_vpn_mask(env, dtlb, wi))
+ | entry->asid;
} else {
return 0;
}
@@ -507,7 +512,7 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
- const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
+ const xtensa_tlb_entry *entry = xtensa_get_tlb_entry(env, v, dtlb, NULL);
if (entry) {
return entry->paddr | entry->attr;
@@ -520,7 +525,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
- xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
+ xtensa_tlb_entry *entry = xtensa_get_tlb_entry(env, v, dtlb, &wi);
if (entry && entry->variable && entry->asid) {
tlb_flush_page(env_cpu(env), entry->vaddr);
entry->asid = 0;
@@ -559,7 +564,7 @@ void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
uint32_t vpn;
uint32_t wi;
uint32_t ei;
- if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) {
+ if (xtensa_split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) {
xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
}
}
@@ -818,7 +823,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
may_lookup_pt && get_pte(env, vaddr, &pte)) {
ring = (pte >> 4) & 0x3;
wi = 0;
- split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
+ xtensa_split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
if (update_tlb) {
wi = ++env->autorefill_idx & 0x3;
@@ -1192,7 +1197,7 @@ static void dump_mpu(CPUXtensaState *env,
}
}
-void dump_mmu(CPUXtensaState *env)
+void xtensa_dump_mmu(CPUXtensaState *env)
{
if (xtensa_option_bits_enabled(env->config,
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
diff --git a/target/xtensa/monitor.c b/target/xtensa/monitor.c
index fbf60d5553..ce1b791a5c 100644
--- a/target/xtensa/monitor.c
+++ b/target/xtensa/monitor.c
@@ -35,5 +35,5 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
monitor_printf(mon, "No CPU available\n");
return;
}
- dump_mmu(env1);
+ xtensa_dump_mmu(env1);
}
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH-for-9.1 18/21] target/xtensa: Extract MMU API to new mmu.c/mmu.h files
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 17/21] target/xtensa: Prefix MMU API with 'xtensa_' Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-23 19:23 ` Max Filippov
2024-03-21 15:48 ` [PATCH-for-9.1 19/21] target/xtensa: Simplify dump_mpu() and dump_tlb() Philippe Mathieu-Daudé
` (2 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Extract the MMU API and expose it via "mmu.h" so we can
reuse the methods in target/xtensa/ files.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/xtensa/cpu.h | 32 +-
target/xtensa/mmu.h | 95 ++++
target/xtensa/mmu.c | 889 ++++++++++++++++++++++++++++++++++++
target/xtensa/mmu_helper.c | 892 +------------------------------------
target/xtensa/meson.build | 1 +
5 files changed, 991 insertions(+), 918 deletions(-)
create mode 100644 target/xtensa/mmu.h
create mode 100644 target/xtensa/mmu.c
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index b2cfc78e9d..b67ee987f3 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -34,6 +34,10 @@
#include "hw/clock.h"
#include "xtensa-isa.h"
+typedef struct CPUArchState CPUXtensaState;
+
+#include "mmu.h"
+
/* Xtensa processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
@@ -309,28 +313,6 @@ typedef enum {
INTTYPE_MAX
} interrupt_type;
-typedef struct CPUArchState CPUXtensaState;
-
-typedef struct xtensa_tlb_entry {
- uint32_t vaddr;
- uint32_t paddr;
- uint8_t asid;
- uint8_t attr;
- bool variable;
-} xtensa_tlb_entry;
-
-typedef struct xtensa_tlb {
- unsigned nways;
- const unsigned way_size[10];
- bool varway56;
- unsigned nrefillentries;
-} xtensa_tlb;
-
-typedef struct xtensa_mpu_entry {
- uint32_t vaddr;
- uint32_t attr;
-} xtensa_mpu_entry;
-
typedef struct XtensaGdbReg {
int targno;
unsigned flags;
@@ -689,12 +671,6 @@ static inline int xtensa_get_cring(const CPUXtensaState *env)
}
#ifndef CONFIG_USER_ONLY
-int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
- uint32_t vaddr, int is_write, int mmu_idx,
- uint32_t *paddr, uint32_t *page_size, unsigned *access);
-void xtensa_reset_mmu(CPUXtensaState *env);
-void xtensa_dump_mmu(CPUXtensaState *env);
-
static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
{
return env->system_er;
diff --git a/target/xtensa/mmu.h b/target/xtensa/mmu.h
new file mode 100644
index 0000000000..3e1d2c03ea
--- /dev/null
+++ b/target/xtensa/mmu.h
@@ -0,0 +1,95 @@
+/*
+ * Xtensa MMU/MPU helpers
+ *
+ * SPDX-FileCopyrightText: 2011 - 2019, Max Filippov, Open Source and Linux Lab.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TARGET_XTENSA_MMU_H
+#define TARGET_XTENSA_MMU_H
+
+#include "cpu.h"
+
+typedef struct xtensa_tlb_entry {
+ uint32_t vaddr;
+ uint32_t paddr;
+ uint8_t asid;
+ uint8_t attr;
+ bool variable;
+} xtensa_tlb_entry;
+
+typedef struct xtensa_tlb {
+ unsigned nways;
+ const unsigned way_size[10];
+ bool varway56;
+ unsigned nrefillentries;
+} xtensa_tlb;
+
+typedef struct xtensa_mpu_entry {
+ uint32_t vaddr;
+ uint32_t attr;
+} xtensa_mpu_entry;
+
+#define XTENSA_MPU_SEGMENT_MASK 0x0000001f
+#define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00
+#define XTENSA_MPU_ACC_RIGHTS_SHIFT 8
+#define XTENSA_MPU_MEM_TYPE_MASK 0x001ff000
+#define XTENSA_MPU_MEM_TYPE_SHIFT 12
+#define XTENSA_MPU_ATTR_MASK 0x001fff00
+
+#define XTENSA_MPU_PROBE_B 0x40000000
+#define XTENSA_MPU_PROBE_V 0x80000000
+
+#define XTENSA_MPU_SYSTEM_TYPE_DEVICE 0x0001
+#define XTENSA_MPU_SYSTEM_TYPE_NC 0x0002
+#define XTENSA_MPU_SYSTEM_TYPE_C 0x0003
+#define XTENSA_MPU_SYSTEM_TYPE_MASK 0x0003
+
+#define XTENSA_MPU_TYPE_SYS_C 0x0010
+#define XTENSA_MPU_TYPE_SYS_W 0x0020
+#define XTENSA_MPU_TYPE_SYS_R 0x0040
+#define XTENSA_MPU_TYPE_CPU_C 0x0100
+#define XTENSA_MPU_TYPE_CPU_W 0x0200
+#define XTENSA_MPU_TYPE_CPU_R 0x0400
+#define XTENSA_MPU_TYPE_CPU_CACHE 0x0800
+#define XTENSA_MPU_TYPE_B 0x1000
+#define XTENSA_MPU_TYPE_INT 0x2000
+
+unsigned mmu_attr_to_access(uint32_t attr);
+unsigned mpu_attr_to_access(uint32_t attr, unsigned ring);
+unsigned mpu_attr_to_cpu_cache(uint32_t attr);
+unsigned mpu_attr_to_type(uint32_t attr);
+
+unsigned region_attr_to_access(uint32_t attr);
+unsigned cacheattr_attr_to_access(uint32_t attr);
+
+xtensa_tlb_entry *xtensa_get_tlb_entry(CPUXtensaState *env,
+ uint32_t v, bool dtlb, uint32_t *pwi);
+xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb,
+ unsigned wi, unsigned ei);
+void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
+ unsigned wi, unsigned ei,
+ uint32_t vpn, uint32_t pte);
+
+uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb,
+ uint32_t way);
+uint32_t xtensa_get_vpn_mask(const CPUXtensaState *env, bool dtlb,
+ uint32_t way);
+
+bool xtensa_split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
+ uint32_t *vpn, uint32_t *wi, uint32_t *ei);
+
+int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
+ uint32_t *pwi, uint32_t *pei, uint8_t *pring);
+int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n,
+ uint32_t vaddr, unsigned *segment);
+
+int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
+ uint32_t vaddr, int is_write, int mmu_idx,
+ uint32_t *paddr, uint32_t *page_size,
+ unsigned *access);
+
+void xtensa_reset_mmu(CPUXtensaState *env);
+void xtensa_dump_mmu(CPUXtensaState *env);
+
+#endif
diff --git a/target/xtensa/mmu.c b/target/xtensa/mmu.c
new file mode 100644
index 0000000000..4f17fb2980
--- /dev/null
+++ b/target/xtensa/mmu.c
@@ -0,0 +1,889 @@
+/*
+ * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Open Source and Linux Lab nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/host-utils.h"
+#include "exec/exec-all.h"
+#include "cpu.h"
+#include "mmu.h"
+
+static uint32_t get_page_size(const CPUXtensaState *env,
+ bool dtlb, uint32_t way)
+{
+ uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
+
+ switch (way) {
+ case 4:
+ return (tlbcfg >> 16) & 0x3;
+
+ case 5:
+ return (tlbcfg >> 20) & 0x1;
+
+ case 6:
+ return (tlbcfg >> 24) & 0x1;
+
+ default:
+ return 0;
+ }
+}
+
+/*!
+ * Get bit mask for the virtual address bits translated by the TLB way
+ */
+uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env,
+ bool dtlb, uint32_t way)
+{
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ bool varway56 = dtlb ?
+ env->config->dtlb.varway56 :
+ env->config->itlb.varway56;
+
+ switch (way) {
+ case 4:
+ return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
+
+ case 5:
+ if (varway56) {
+ return 0xf8000000 << get_page_size(env, dtlb, way);
+ } else {
+ return 0xf8000000;
+ }
+
+ case 6:
+ if (varway56) {
+ return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
+ } else {
+ return 0xf0000000;
+ }
+
+ default:
+ return 0xfffff000;
+ }
+ } else {
+ return REGION_PAGE_MASK;
+ }
+}
+
+/*!
+ * Get bit mask for the 'VPN without index' field.
+ * See ISA, 4.6.5.6, data format for RxTLB0
+ */
+uint32_t xtensa_get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
+{
+ if (way < 4) {
+ bool is32 = (dtlb ?
+ env->config->dtlb.nrefillentries :
+ env->config->itlb.nrefillentries) == 32;
+ return is32 ? 0xffff8000 : 0xffffc000;
+ } else if (way == 4) {
+ return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
+ } else if (way <= 6) {
+ uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
+ bool varway56 = dtlb ?
+ env->config->dtlb.varway56 :
+ env->config->itlb.varway56;
+
+ if (varway56) {
+ return mask << (way == 5 ? 2 : 3);
+ } else {
+ return mask << 1;
+ }
+ } else {
+ return 0xfffff000;
+ }
+}
+
+/*!
+ * Split virtual address into VPN (with index) and entry index
+ * for the given TLB way
+ */
+static void xtensa_split_tlb_entry_spec_way(const CPUXtensaState *env,
+ uint32_t v,
+ bool dtlb, uint32_t *vpn,
+ uint32_t wi, uint32_t *ei)
+{
+ bool varway56 = dtlb ?
+ env->config->dtlb.varway56 :
+ env->config->itlb.varway56;
+
+ if (!dtlb) {
+ wi &= 7;
+ }
+
+ if (wi < 4) {
+ bool is32 = (dtlb ?
+ env->config->dtlb.nrefillentries :
+ env->config->itlb.nrefillentries) == 32;
+ *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
+ } else {
+ switch (wi) {
+ case 4:
+ {
+ uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
+ *ei = (v >> eibase) & 0x3;
+ }
+ break;
+
+ case 5:
+ if (varway56) {
+ uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
+ *ei = (v >> eibase) & 0x3;
+ } else {
+ *ei = (v >> 27) & 0x1;
+ }
+ break;
+
+ case 6:
+ if (varway56) {
+ uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
+ *ei = (v >> eibase) & 0x7;
+ } else {
+ *ei = (v >> 28) & 0x1;
+ }
+ break;
+
+ default:
+ *ei = 0;
+ break;
+ }
+ }
+ *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
+}
+
+/*!
+ * Split TLB address into TLB way, entry index and VPN (with index).
+ * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
+ */
+bool xtensa_split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
+ uint32_t *vpn, uint32_t *wi, uint32_t *ei)
+{
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ *wi = v & (dtlb ? 0xf : 0x7);
+ if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nways)) {
+ xtensa_split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
+ return true;
+ } else {
+ return false;
+ }
+ } else {
+ *vpn = v & REGION_PAGE_MASK;
+ *wi = 0;
+ *ei = (v >> 29) & 0x7;
+ return true;
+ }
+}
+
+xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb,
+ unsigned wi, unsigned ei)
+{
+ const xtensa_tlb *tlb = dtlb ? &env->config->dtlb : &env->config->itlb;
+
+ assert(wi < tlb->nways && ei < tlb->way_size[wi]);
+ return dtlb ?
+ env->dtlb[wi] + ei :
+ env->itlb[wi] + ei;
+}
+
+xtensa_tlb_entry *xtensa_get_tlb_entry(CPUXtensaState *env, uint32_t v,
+ bool dtlb, uint32_t *pwi)
+{
+ uint32_t vpn;
+ uint32_t wi;
+ uint32_t ei;
+
+ if (xtensa_split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) {
+ if (pwi) {
+ *pwi = wi;
+ }
+ return xtensa_tlb_get_entry(env, dtlb, wi, ei);
+ } else {
+ return NULL;
+ }
+}
+
+static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
+ xtensa_tlb_entry *entry, bool dtlb,
+ unsigned wi, unsigned ei, uint32_t vpn,
+ uint32_t pte)
+{
+ entry->vaddr = vpn;
+ entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
+ entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
+ entry->attr = pte & 0xf;
+}
+
+void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
+ unsigned wi, unsigned ei,
+ uint32_t vpn, uint32_t pte)
+{
+ CPUState *cs = env_cpu(env);
+ xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
+
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ if (entry->variable) {
+ if (entry->asid) {
+ tlb_flush_page(cs, entry->vaddr);
+ }
+ xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
+ tlb_flush_page(cs, entry->vaddr);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s %d, %d, %d trying to set immutable entry\n",
+ __func__, dtlb, wi, ei);
+ }
+ } else {
+ tlb_flush_page(cs, entry->vaddr);
+ if (xtensa_option_enabled(env->config,
+ XTENSA_OPTION_REGION_TRANSLATION)) {
+ entry->paddr = pte & REGION_PAGE_MASK;
+ }
+ entry->attr = pte & 0xf;
+ }
+}
+
+hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
+{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+ uint32_t paddr;
+ uint32_t page_size;
+ unsigned access;
+
+ if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0,
+ &paddr, &page_size, &access) == 0) {
+ return paddr;
+ }
+ if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0,
+ &paddr, &page_size, &access) == 0) {
+ return paddr;
+ }
+ return ~0;
+}
+
+static void reset_tlb_mmu_all_ways(CPUXtensaState *env, const xtensa_tlb *tlb,
+ xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
+{
+ unsigned wi, ei;
+
+ for (wi = 0; wi < tlb->nways; ++wi) {
+ for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
+ entry[wi][ei].asid = 0;
+ entry[wi][ei].variable = true;
+ }
+ }
+}
+
+static void reset_tlb_mmu_ways56(CPUXtensaState *env, const xtensa_tlb *tlb,
+ xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
+{
+ if (!tlb->varway56) {
+ static const xtensa_tlb_entry way5[] = {
+ {
+ .vaddr = 0xd0000000,
+ .paddr = 0,
+ .asid = 1,
+ .attr = 7,
+ .variable = false,
+ }, {
+ .vaddr = 0xd8000000,
+ .paddr = 0,
+ .asid = 1,
+ .attr = 3,
+ .variable = false,
+ }
+ };
+ static const xtensa_tlb_entry way6[] = {
+ {
+ .vaddr = 0xe0000000,
+ .paddr = 0xf0000000,
+ .asid = 1,
+ .attr = 7,
+ .variable = false,
+ }, {
+ .vaddr = 0xf0000000,
+ .paddr = 0xf0000000,
+ .asid = 1,
+ .attr = 3,
+ .variable = false,
+ }
+ };
+ memcpy(entry[5], way5, sizeof(way5));
+ memcpy(entry[6], way6, sizeof(way6));
+ } else {
+ uint32_t ei;
+ for (ei = 0; ei < 8; ++ei) {
+ entry[6][ei].vaddr = ei << 29;
+ entry[6][ei].paddr = ei << 29;
+ entry[6][ei].asid = 1;
+ entry[6][ei].attr = 3;
+ }
+ }
+}
+
+static void reset_tlb_region_way0(CPUXtensaState *env,
+ xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
+{
+ unsigned ei;
+
+ for (ei = 0; ei < 8; ++ei) {
+ entry[0][ei].vaddr = ei << 29;
+ entry[0][ei].paddr = ei << 29;
+ entry[0][ei].asid = 1;
+ entry[0][ei].attr = 2;
+ entry[0][ei].variable = true;
+ }
+}
+
+void xtensa_reset_mmu(CPUXtensaState *env)
+{
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ env->sregs[RASID] = 0x04030201;
+ env->sregs[ITLBCFG] = 0;
+ env->sregs[DTLBCFG] = 0;
+ env->autorefill_idx = 0;
+ reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
+ reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
+ reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
+ reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
+ } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) {
+ unsigned i;
+
+ env->sregs[MPUENB] = 0;
+ env->sregs[MPUCFG] = env->config->n_mpu_fg_segments;
+ env->sregs[CACHEADRDIS] = 0;
+ assert(env->config->n_mpu_bg_segments > 0 &&
+ env->config->mpu_bg[0].vaddr == 0);
+ for (i = 1; i < env->config->n_mpu_bg_segments; ++i) {
+ assert(env->config->mpu_bg[i].vaddr >=
+ env->config->mpu_bg[i - 1].vaddr);
+ }
+ } else {
+ env->sregs[CACHEATTR] = 0x22222222;
+ reset_tlb_region_way0(env, env->itlb);
+ reset_tlb_region_way0(env, env->dtlb);
+ }
+}
+
+static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
+{
+ unsigned i;
+ for (i = 0; i < 4; ++i) {
+ if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
+ return i;
+ }
+ }
+ return 0xff;
+}
+
+/*!
+ * Lookup xtensa TLB for the given virtual address.
+ * See ISA, 4.6.2.2
+ *
+ * \param pwi: [out] way index
+ * \param pei: [out] entry index
+ * \param pring: [out] access ring
+ * \return 0 if ok, exception cause code otherwise
+ */
+int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
+ uint32_t *pwi, uint32_t *pei, uint8_t *pring)
+{
+ const xtensa_tlb *tlb = dtlb ?
+ &env->config->dtlb : &env->config->itlb;
+ const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
+ env->dtlb : env->itlb;
+
+ int nhits = 0;
+ unsigned wi;
+
+ for (wi = 0; wi < tlb->nways; ++wi) {
+ uint32_t vpn;
+ uint32_t ei;
+ xtensa_split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
+ if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
+ unsigned ring = get_ring(env, entry[wi][ei].asid);
+ if (ring < 4) {
+ if (++nhits > 1) {
+ return dtlb ?
+ LOAD_STORE_TLB_MULTI_HIT_CAUSE :
+ INST_TLB_MULTI_HIT_CAUSE;
+ }
+ *pwi = wi;
+ *pei = ei;
+ *pring = ring;
+ }
+ }
+ }
+ return nhits ? 0 :
+ (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
+}
+
+/*!
+ * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
+ * See ISA, 4.6.5.10
+ */
+unsigned mmu_attr_to_access(uint32_t attr)
+{
+ unsigned access = 0;
+
+ if (attr < 12) {
+ access |= PAGE_READ;
+ if (attr & 0x1) {
+ access |= PAGE_EXEC;
+ }
+ if (attr & 0x2) {
+ access |= PAGE_WRITE;
+ }
+
+ switch (attr & 0xc) {
+ case 0:
+ access |= PAGE_CACHE_BYPASS;
+ break;
+
+ case 4:
+ access |= PAGE_CACHE_WB;
+ break;
+
+ case 8:
+ access |= PAGE_CACHE_WT;
+ break;
+ }
+ } else if (attr == 13) {
+ access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
+ }
+ return access;
+}
+
+/*!
+ * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
+ * See ISA, 4.6.3.3
+ */
+unsigned region_attr_to_access(uint32_t attr)
+{
+ static const unsigned access[16] = {
+ [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
+ [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
+ [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
+ [3] = PAGE_EXEC | PAGE_CACHE_WB,
+ [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
+ [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
+ [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
+ };
+
+ return access[attr & 0xf];
+}
+
+/*!
+ * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask.
+ * See ISA, A.2.14 The Cache Attribute Register
+ */
+unsigned cacheattr_attr_to_access(uint32_t attr)
+{
+ static const unsigned access[16] = {
+ [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
+ [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
+ [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
+ [3] = PAGE_EXEC | PAGE_CACHE_WB,
+ [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
+ [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
+ };
+
+ return access[attr & 0xf];
+}
+
+struct attr_pattern {
+ uint32_t mask;
+ uint32_t value;
+};
+
+static int attr_pattern_match(uint32_t attr,
+ const struct attr_pattern *pattern,
+ size_t n)
+{
+ size_t i;
+
+ for (i = 0; i < n; ++i) {
+ if ((attr & pattern[i].mask) == pattern[i].value) {
+ return 1;
+ }
+ }
+ return 0;
+}
+
+unsigned mpu_attr_to_cpu_cache(uint32_t attr)
+{
+ static const struct attr_pattern cpu_c[] = {
+ { .mask = 0x18f, .value = 0x089 },
+ { .mask = 0x188, .value = 0x080 },
+ { .mask = 0x180, .value = 0x180 },
+ };
+
+ unsigned type = 0;
+
+ if (attr_pattern_match(attr, cpu_c, ARRAY_SIZE(cpu_c))) {
+ type |= XTENSA_MPU_TYPE_CPU_CACHE;
+ if (attr & 0x10) {
+ type |= XTENSA_MPU_TYPE_CPU_C;
+ }
+ if (attr & 0x20) {
+ type |= XTENSA_MPU_TYPE_CPU_W;
+ }
+ if (attr & 0x40) {
+ type |= XTENSA_MPU_TYPE_CPU_R;
+ }
+ }
+ return type;
+}
+
+unsigned mpu_attr_to_type(uint32_t attr)
+{
+ static const struct attr_pattern device_type[] = {
+ { .mask = 0x1f6, .value = 0x000 },
+ { .mask = 0x1f6, .value = 0x006 },
+ };
+ static const struct attr_pattern sys_nc_type[] = {
+ { .mask = 0x1fe, .value = 0x018 },
+ { .mask = 0x1fe, .value = 0x01e },
+ { .mask = 0x18f, .value = 0x089 },
+ };
+ static const struct attr_pattern sys_c_type[] = {
+ { .mask = 0x1f8, .value = 0x010 },
+ { .mask = 0x188, .value = 0x080 },
+ { .mask = 0x1f0, .value = 0x030 },
+ { .mask = 0x180, .value = 0x180 },
+ };
+ static const struct attr_pattern b[] = {
+ { .mask = 0x1f7, .value = 0x001 },
+ { .mask = 0x1f7, .value = 0x007 },
+ { .mask = 0x1ff, .value = 0x019 },
+ { .mask = 0x1ff, .value = 0x01f },
+ };
+
+ unsigned type = 0;
+
+ attr = (attr & XTENSA_MPU_MEM_TYPE_MASK) >> XTENSA_MPU_MEM_TYPE_SHIFT;
+ if (attr_pattern_match(attr, device_type, ARRAY_SIZE(device_type))) {
+ type |= XTENSA_MPU_SYSTEM_TYPE_DEVICE;
+ if (attr & 0x80) {
+ type |= XTENSA_MPU_TYPE_INT;
+ }
+ }
+ if (attr_pattern_match(attr, sys_nc_type, ARRAY_SIZE(sys_nc_type))) {
+ type |= XTENSA_MPU_SYSTEM_TYPE_NC;
+ }
+ if (attr_pattern_match(attr, sys_c_type, ARRAY_SIZE(sys_c_type))) {
+ type |= XTENSA_MPU_SYSTEM_TYPE_C;
+ if (attr & 0x1) {
+ type |= XTENSA_MPU_TYPE_SYS_C;
+ }
+ if (attr & 0x2) {
+ type |= XTENSA_MPU_TYPE_SYS_W;
+ }
+ if (attr & 0x4) {
+ type |= XTENSA_MPU_TYPE_SYS_R;
+ }
+ }
+ if (attr_pattern_match(attr, b, ARRAY_SIZE(b))) {
+ type |= XTENSA_MPU_TYPE_B;
+ }
+ type |= mpu_attr_to_cpu_cache(attr);
+
+ return type;
+}
+
+unsigned mpu_attr_to_access(uint32_t attr, unsigned ring)
+{
+ static const unsigned access[2][16] = {
+ [0] = {
+ [4] = PAGE_READ,
+ [5] = PAGE_READ | PAGE_EXEC,
+ [6] = PAGE_READ | PAGE_WRITE,
+ [7] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
+ [8] = PAGE_WRITE,
+ [9] = PAGE_READ | PAGE_WRITE,
+ [10] = PAGE_READ | PAGE_WRITE,
+ [11] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
+ [12] = PAGE_READ,
+ [13] = PAGE_READ | PAGE_EXEC,
+ [14] = PAGE_READ | PAGE_WRITE,
+ [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
+ },
+ [1] = {
+ [8] = PAGE_WRITE,
+ [9] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
+ [10] = PAGE_READ,
+ [11] = PAGE_READ | PAGE_EXEC,
+ [12] = PAGE_READ,
+ [13] = PAGE_READ | PAGE_EXEC,
+ [14] = PAGE_READ | PAGE_WRITE,
+ [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
+ },
+ };
+ unsigned rv;
+ unsigned type;
+
+ type = mpu_attr_to_cpu_cache(attr);
+ rv = access[ring != 0][(attr & XTENSA_MPU_ACC_RIGHTS_MASK) >>
+ XTENSA_MPU_ACC_RIGHTS_SHIFT];
+
+ if (type & XTENSA_MPU_TYPE_CPU_CACHE) {
+ rv |= (type & XTENSA_MPU_TYPE_CPU_C) ? PAGE_CACHE_WB : PAGE_CACHE_WT;
+ } else {
+ rv |= PAGE_CACHE_BYPASS;
+ }
+ return rv;
+}
+
+static bool is_access_granted(unsigned access, int is_write)
+{
+ switch (is_write) {
+ case 0:
+ return access & PAGE_READ;
+
+ case 1:
+ return access & PAGE_WRITE;
+
+ case 2:
+ return access & PAGE_EXEC;
+
+ default:
+ return 0;
+ }
+}
+
+static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
+
+static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
+ uint32_t vaddr, int is_write, int mmu_idx,
+ uint32_t *paddr, uint32_t *page_size,
+ unsigned *access, bool may_lookup_pt)
+{
+ bool dtlb = is_write != 2;
+ uint32_t wi;
+ uint32_t ei;
+ uint8_t ring;
+ uint32_t vpn;
+ uint32_t pte;
+ const xtensa_tlb_entry *entry = NULL;
+ xtensa_tlb_entry tmp_entry;
+ int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
+
+ if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
+ may_lookup_pt && get_pte(env, vaddr, &pte)) {
+ ring = (pte >> 4) & 0x3;
+ wi = 0;
+ xtensa_split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
+
+ if (update_tlb) {
+ wi = ++env->autorefill_idx & 0x3;
+ xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
+ env->sregs[EXCVADDR] = vaddr;
+ qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n",
+ __func__, vaddr, vpn, pte);
+ } else {
+ xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
+ entry = &tmp_entry;
+ }
+ ret = 0;
+ }
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (entry == NULL) {
+ entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
+ }
+
+ if (ring < mmu_idx) {
+ return dtlb ?
+ LOAD_STORE_PRIVILEGE_CAUSE :
+ INST_FETCH_PRIVILEGE_CAUSE;
+ }
+
+ *access = mmu_attr_to_access(entry->attr) &
+ ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
+ if (!is_access_granted(*access, is_write)) {
+ return dtlb ?
+ (is_write ?
+ STORE_PROHIBITED_CAUSE :
+ LOAD_PROHIBITED_CAUSE) :
+ INST_FETCH_PROHIBITED_CAUSE;
+ }
+
+ *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
+ *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
+
+ return 0;
+}
+
+static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
+{
+ CPUState *cs = env_cpu(env);
+ uint32_t paddr;
+ uint32_t page_size;
+ unsigned access;
+ uint32_t pt_vaddr =
+ (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
+ int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
+ &paddr, &page_size, &access, false);
+
+ if (ret == 0) {
+ qemu_log_mask(CPU_LOG_MMU,
+ "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n",
+ __func__, vaddr, pt_vaddr, paddr);
+ } else {
+ qemu_log_mask(CPU_LOG_MMU,
+ "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n",
+ __func__, vaddr, pt_vaddr, ret);
+ }
+
+ if (ret == 0) {
+ MemTxResult result;
+
+ *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED,
+ &result);
+ if (result != MEMTX_OK) {
+ qemu_log_mask(CPU_LOG_MMU,
+ "%s: couldn't load PTE: transaction failed (%u)\n",
+ __func__, (unsigned)result);
+ ret = 1;
+ }
+ }
+ return ret == 0;
+}
+
+static int get_physical_addr_region(CPUXtensaState *env,
+ uint32_t vaddr, int is_write, int mmu_idx,
+ uint32_t *paddr, uint32_t *page_size,
+ unsigned *access)
+{
+ bool dtlb = is_write != 2;
+ uint32_t wi = 0;
+ uint32_t ei = (vaddr >> 29) & 0x7;
+ const xtensa_tlb_entry *entry =
+ xtensa_tlb_get_entry(env, dtlb, wi, ei);
+
+ *access = region_attr_to_access(entry->attr);
+ if (!is_access_granted(*access, is_write)) {
+ return dtlb ?
+ (is_write ?
+ STORE_PROHIBITED_CAUSE :
+ LOAD_PROHIBITED_CAUSE) :
+ INST_FETCH_PROHIBITED_CAUSE;
+ }
+
+ *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
+ *page_size = ~REGION_PAGE_MASK + 1;
+
+ return 0;
+}
+
+int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n,
+ uint32_t vaddr, unsigned *segment)
+{
+ unsigned nhits = 0;
+ unsigned i;
+
+ for (i = 0; i < n; ++i) {
+ if (vaddr >= entry[i].vaddr &&
+ (i == n - 1 || vaddr < entry[i + 1].vaddr)) {
+ if (nhits++) {
+ break;
+ }
+ *segment = i;
+ }
+ }
+ return nhits;
+}
+
+static int get_physical_addr_mpu(CPUXtensaState *env,
+ uint32_t vaddr, int is_write, int mmu_idx,
+ uint32_t *paddr, uint32_t *page_size,
+ unsigned *access)
+{
+ unsigned nhits;
+ unsigned segment;
+ uint32_t attr;
+
+ nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments,
+ vaddr, &segment);
+ if (nhits > 1) {
+ return is_write < 2 ?
+ LOAD_STORE_TLB_MULTI_HIT_CAUSE :
+ INST_TLB_MULTI_HIT_CAUSE;
+ } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) {
+ attr = env->mpu_fg[segment].attr;
+ } else {
+ xtensa_mpu_lookup(env->config->mpu_bg,
+ env->config->n_mpu_bg_segments,
+ vaddr, &segment);
+ attr = env->config->mpu_bg[segment].attr;
+ }
+
+ *access = mpu_attr_to_access(attr, mmu_idx);
+ if (!is_access_granted(*access, is_write)) {
+ return is_write < 2 ?
+ (is_write ?
+ STORE_PROHIBITED_CAUSE :
+ LOAD_PROHIBITED_CAUSE) :
+ INST_FETCH_PROHIBITED_CAUSE;
+ }
+ *paddr = vaddr;
+ *page_size = env->config->mpu_align;
+ return 0;
+}
+
+/*!
+ * Convert virtual address to physical addr.
+ * MMU may issue pagewalk and change xtensa autorefill TLB way entry.
+ *
+ * \return 0 if ok, exception cause code otherwise
+ */
+int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
+ uint32_t vaddr, int is_write, int mmu_idx,
+ uint32_t *paddr, uint32_t *page_size,
+ unsigned *access)
+{
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ return get_physical_addr_mmu(env, update_tlb,
+ vaddr, is_write, mmu_idx, paddr,
+ page_size, access, true);
+ } else if (xtensa_option_bits_enabled(env->config,
+ XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
+ XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
+ return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
+ paddr, page_size, access);
+ } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) {
+ return get_physical_addr_mpu(env, vaddr, is_write, mmu_idx,
+ paddr, page_size, access);
+ } else {
+ *paddr = vaddr;
+ *page_size = TARGET_PAGE_SIZE;
+ *access = cacheattr_attr_to_access(env->sregs[CACHEATTR] >>
+ ((vaddr & 0xe0000000) >> 27));
+ return 0;
+ }
+}
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index 31ee3fa957..8be8d79dcd 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -26,38 +26,12 @@
*/
#include "qemu/osdep.h"
-#include "qemu/log.h"
#include "qemu/qemu-print.h"
#include "qemu/units.h"
-#include "cpu.h"
#include "exec/helper-proto.h"
-#include "qemu/host-utils.h"
#include "exec/exec-all.h"
-
-#define XTENSA_MPU_SEGMENT_MASK 0x0000001f
-#define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00
-#define XTENSA_MPU_ACC_RIGHTS_SHIFT 8
-#define XTENSA_MPU_MEM_TYPE_MASK 0x001ff000
-#define XTENSA_MPU_MEM_TYPE_SHIFT 12
-#define XTENSA_MPU_ATTR_MASK 0x001fff00
-
-#define XTENSA_MPU_PROBE_B 0x40000000
-#define XTENSA_MPU_PROBE_V 0x80000000
-
-#define XTENSA_MPU_SYSTEM_TYPE_DEVICE 0x0001
-#define XTENSA_MPU_SYSTEM_TYPE_NC 0x0002
-#define XTENSA_MPU_SYSTEM_TYPE_C 0x0003
-#define XTENSA_MPU_SYSTEM_TYPE_MASK 0x0003
-
-#define XTENSA_MPU_TYPE_SYS_C 0x0010
-#define XTENSA_MPU_TYPE_SYS_W 0x0020
-#define XTENSA_MPU_TYPE_SYS_R 0x0040
-#define XTENSA_MPU_TYPE_CPU_C 0x0100
-#define XTENSA_MPU_TYPE_CPU_W 0x0200
-#define XTENSA_MPU_TYPE_CPU_R 0x0400
-#define XTENSA_MPU_TYPE_CPU_CACHE 0x0800
-#define XTENSA_MPU_TYPE_B 0x1000
-#define XTENSA_MPU_TYPE_INT 0x2000
+#include "cpu.h"
+#include "mmu.h"
void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
{
@@ -78,421 +52,6 @@ void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
}
}
-static uint32_t get_page_size(const CPUXtensaState *env,
- bool dtlb, uint32_t way)
-{
- uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
-
- switch (way) {
- case 4:
- return (tlbcfg >> 16) & 0x3;
-
- case 5:
- return (tlbcfg >> 20) & 0x1;
-
- case 6:
- return (tlbcfg >> 24) & 0x1;
-
- default:
- return 0;
- }
-}
-
-/*!
- * Get bit mask for the virtual address bits translated by the TLB way
- */
-static uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env,
- bool dtlb, uint32_t way)
-{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
- bool varway56 = dtlb ?
- env->config->dtlb.varway56 :
- env->config->itlb.varway56;
-
- switch (way) {
- case 4:
- return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
-
- case 5:
- if (varway56) {
- return 0xf8000000 << get_page_size(env, dtlb, way);
- } else {
- return 0xf8000000;
- }
-
- case 6:
- if (varway56) {
- return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
- } else {
- return 0xf0000000;
- }
-
- default:
- return 0xfffff000;
- }
- } else {
- return REGION_PAGE_MASK;
- }
-}
-
-/*!
- * Get bit mask for the 'VPN without index' field.
- * See ISA, 4.6.5.6, data format for RxTLB0
- */
-static uint32_t xtensa_get_vpn_mask(const CPUXtensaState *env, bool dtlb,
- uint32_t way)
-{
- if (way < 4) {
- bool is32 = (dtlb ?
- env->config->dtlb.nrefillentries :
- env->config->itlb.nrefillentries) == 32;
- return is32 ? 0xffff8000 : 0xffffc000;
- } else if (way == 4) {
- return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
- } else if (way <= 6) {
- uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
- bool varway56 = dtlb ?
- env->config->dtlb.varway56 :
- env->config->itlb.varway56;
-
- if (varway56) {
- return mask << (way == 5 ? 2 : 3);
- } else {
- return mask << 1;
- }
- } else {
- return 0xfffff000;
- }
-}
-
-/*!
- * Split virtual address into VPN (with index) and entry index
- * for the given TLB way
- */
-static void xtensa_split_tlb_entry_spec_way(const CPUXtensaState *env,
- uint32_t v,
- bool dtlb, uint32_t *vpn,
- uint32_t wi, uint32_t *ei)
-{
- bool varway56 = dtlb ?
- env->config->dtlb.varway56 :
- env->config->itlb.varway56;
-
- if (!dtlb) {
- wi &= 7;
- }
-
- if (wi < 4) {
- bool is32 = (dtlb ?
- env->config->dtlb.nrefillentries :
- env->config->itlb.nrefillentries) == 32;
- *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
- } else {
- switch (wi) {
- case 4:
- {
- uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
- *ei = (v >> eibase) & 0x3;
- }
- break;
-
- case 5:
- if (varway56) {
- uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
- *ei = (v >> eibase) & 0x3;
- } else {
- *ei = (v >> 27) & 0x1;
- }
- break;
-
- case 6:
- if (varway56) {
- uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
- *ei = (v >> eibase) & 0x7;
- } else {
- *ei = (v >> 28) & 0x1;
- }
- break;
-
- default:
- *ei = 0;
- break;
- }
- }
- *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
-}
-
-/*!
- * Split TLB address into TLB way, entry index and VPN (with index).
- * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
- */
-static bool xtensa_split_tlb_entry_spec(CPUXtensaState *env,
- uint32_t v, bool dtlb,
- uint32_t *vpn, uint32_t *wi,
- uint32_t *ei)
-{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
- *wi = v & (dtlb ? 0xf : 0x7);
- if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nways)) {
- xtensa_split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
- return true;
- } else {
- return false;
- }
- } else {
- *vpn = v & REGION_PAGE_MASK;
- *wi = 0;
- *ei = (v >> 29) & 0x7;
- return true;
- }
-}
-
-static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb,
- unsigned wi, unsigned ei)
-{
- const xtensa_tlb *tlb = dtlb ? &env->config->dtlb : &env->config->itlb;
-
- assert(wi < tlb->nways && ei < tlb->way_size[wi]);
- return dtlb ?
- env->dtlb[wi] + ei :
- env->itlb[wi] + ei;
-}
-
-static xtensa_tlb_entry *xtensa_get_tlb_entry(CPUXtensaState *env,
- uint32_t v, bool dtlb, uint32_t *pwi)
-{
- uint32_t vpn;
- uint32_t wi;
- uint32_t ei;
-
- if (xtensa_split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) {
- if (pwi) {
- *pwi = wi;
- }
- return xtensa_tlb_get_entry(env, dtlb, wi, ei);
- } else {
- return NULL;
- }
-}
-
-static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
- xtensa_tlb_entry *entry, bool dtlb,
- unsigned wi, unsigned ei, uint32_t vpn,
- uint32_t pte)
-{
- entry->vaddr = vpn;
- entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
- entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
- entry->attr = pte & 0xf;
-}
-
-static void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
- unsigned wi, unsigned ei,
- uint32_t vpn, uint32_t pte)
-{
- CPUState *cs = env_cpu(env);
- xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
-
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
- if (entry->variable) {
- if (entry->asid) {
- tlb_flush_page(cs, entry->vaddr);
- }
- xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
- tlb_flush_page(cs, entry->vaddr);
- } else {
- qemu_log_mask(LOG_GUEST_ERROR,
- "%s %d, %d, %d trying to set immutable entry\n",
- __func__, dtlb, wi, ei);
- }
- } else {
- tlb_flush_page(cs, entry->vaddr);
- if (xtensa_option_enabled(env->config,
- XTENSA_OPTION_REGION_TRANSLATION)) {
- entry->paddr = pte & REGION_PAGE_MASK;
- }
- entry->attr = pte & 0xf;
- }
-}
-
-hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
-{
- XtensaCPU *cpu = XTENSA_CPU(cs);
- uint32_t paddr;
- uint32_t page_size;
- unsigned access;
-
- if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0,
- &paddr, &page_size, &access) == 0) {
- return paddr;
- }
- if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0,
- &paddr, &page_size, &access) == 0) {
- return paddr;
- }
- return ~0;
-}
-
-static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
- const xtensa_tlb *tlb,
- xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
-{
- unsigned wi, ei;
-
- for (wi = 0; wi < tlb->nways; ++wi) {
- for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
- entry[wi][ei].asid = 0;
- entry[wi][ei].variable = true;
- }
- }
-}
-
-static void reset_tlb_mmu_ways56(CPUXtensaState *env,
- const xtensa_tlb *tlb,
- xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
-{
- if (!tlb->varway56) {
- static const xtensa_tlb_entry way5[] = {
- {
- .vaddr = 0xd0000000,
- .paddr = 0,
- .asid = 1,
- .attr = 7,
- .variable = false,
- }, {
- .vaddr = 0xd8000000,
- .paddr = 0,
- .asid = 1,
- .attr = 3,
- .variable = false,
- }
- };
- static const xtensa_tlb_entry way6[] = {
- {
- .vaddr = 0xe0000000,
- .paddr = 0xf0000000,
- .asid = 1,
- .attr = 7,
- .variable = false,
- }, {
- .vaddr = 0xf0000000,
- .paddr = 0xf0000000,
- .asid = 1,
- .attr = 3,
- .variable = false,
- }
- };
- memcpy(entry[5], way5, sizeof(way5));
- memcpy(entry[6], way6, sizeof(way6));
- } else {
- uint32_t ei;
- for (ei = 0; ei < 8; ++ei) {
- entry[6][ei].vaddr = ei << 29;
- entry[6][ei].paddr = ei << 29;
- entry[6][ei].asid = 1;
- entry[6][ei].attr = 3;
- }
- }
-}
-
-static void reset_tlb_region_way0(CPUXtensaState *env,
- xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
-{
- unsigned ei;
-
- for (ei = 0; ei < 8; ++ei) {
- entry[0][ei].vaddr = ei << 29;
- entry[0][ei].paddr = ei << 29;
- entry[0][ei].asid = 1;
- entry[0][ei].attr = 2;
- entry[0][ei].variable = true;
- }
-}
-
-void xtensa_reset_mmu(CPUXtensaState *env)
-{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
- env->sregs[RASID] = 0x04030201;
- env->sregs[ITLBCFG] = 0;
- env->sregs[DTLBCFG] = 0;
- env->autorefill_idx = 0;
- reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
- reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
- reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
- reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
- } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) {
- unsigned i;
-
- env->sregs[MPUENB] = 0;
- env->sregs[MPUCFG] = env->config->n_mpu_fg_segments;
- env->sregs[CACHEADRDIS] = 0;
- assert(env->config->n_mpu_bg_segments > 0 &&
- env->config->mpu_bg[0].vaddr == 0);
- for (i = 1; i < env->config->n_mpu_bg_segments; ++i) {
- assert(env->config->mpu_bg[i].vaddr >=
- env->config->mpu_bg[i - 1].vaddr);
- }
- } else {
- env->sregs[CACHEATTR] = 0x22222222;
- reset_tlb_region_way0(env, env->itlb);
- reset_tlb_region_way0(env, env->dtlb);
- }
-}
-
-static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
-{
- unsigned i;
- for (i = 0; i < 4; ++i) {
- if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
- return i;
- }
- }
- return 0xff;
-}
-
-/*!
- * Lookup xtensa TLB for the given virtual address.
- * See ISA, 4.6.2.2
- *
- * \param pwi: [out] way index
- * \param pei: [out] entry index
- * \param pring: [out] access ring
- * \return 0 if ok, exception cause code otherwise
- */
-static int xtensa_tlb_lookup(const CPUXtensaState *env,
- uint32_t addr, bool dtlb,
- uint32_t *pwi, uint32_t *pei, uint8_t *pring)
-{
- const xtensa_tlb *tlb = dtlb ?
- &env->config->dtlb : &env->config->itlb;
- const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
- env->dtlb : env->itlb;
-
- int nhits = 0;
- unsigned wi;
-
- for (wi = 0; wi < tlb->nways; ++wi) {
- uint32_t vpn;
- uint32_t ei;
- xtensa_split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
- if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
- unsigned ring = get_ring(env, entry[wi][ei].asid);
- if (ring < 4) {
- if (++nhits > 1) {
- return dtlb ?
- LOAD_STORE_TLB_MULTI_HIT_CAUSE :
- INST_TLB_MULTI_HIT_CAUSE;
- }
- *pwi = wi;
- *pei = ei;
- *pring = ring;
- }
- }
- }
- return nhits ? 0 :
- (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
-}
-
uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
@@ -569,384 +128,6 @@ void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
}
}
-/*!
- * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
- * See ISA, 4.6.5.10
- */
-static unsigned mmu_attr_to_access(uint32_t attr)
-{
- unsigned access = 0;
-
- if (attr < 12) {
- access |= PAGE_READ;
- if (attr & 0x1) {
- access |= PAGE_EXEC;
- }
- if (attr & 0x2) {
- access |= PAGE_WRITE;
- }
-
- switch (attr & 0xc) {
- case 0:
- access |= PAGE_CACHE_BYPASS;
- break;
-
- case 4:
- access |= PAGE_CACHE_WB;
- break;
-
- case 8:
- access |= PAGE_CACHE_WT;
- break;
- }
- } else if (attr == 13) {
- access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
- }
- return access;
-}
-
-/*!
- * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
- * See ISA, 4.6.3.3
- */
-static unsigned region_attr_to_access(uint32_t attr)
-{
- static const unsigned access[16] = {
- [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
- [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
- [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
- [3] = PAGE_EXEC | PAGE_CACHE_WB,
- [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
- [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
- [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
- };
-
- return access[attr & 0xf];
-}
-
-/*!
- * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask.
- * See ISA, A.2.14 The Cache Attribute Register
- */
-static unsigned cacheattr_attr_to_access(uint32_t attr)
-{
- static const unsigned access[16] = {
- [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
- [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
- [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
- [3] = PAGE_EXEC | PAGE_CACHE_WB,
- [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
- [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
- };
-
- return access[attr & 0xf];
-}
-
-struct attr_pattern {
- uint32_t mask;
- uint32_t value;
-};
-
-static int attr_pattern_match(uint32_t attr,
- const struct attr_pattern *pattern,
- size_t n)
-{
- size_t i;
-
- for (i = 0; i < n; ++i) {
- if ((attr & pattern[i].mask) == pattern[i].value) {
- return 1;
- }
- }
- return 0;
-}
-
-static unsigned mpu_attr_to_cpu_cache(uint32_t attr)
-{
- static const struct attr_pattern cpu_c[] = {
- { .mask = 0x18f, .value = 0x089 },
- { .mask = 0x188, .value = 0x080 },
- { .mask = 0x180, .value = 0x180 },
- };
-
- unsigned type = 0;
-
- if (attr_pattern_match(attr, cpu_c, ARRAY_SIZE(cpu_c))) {
- type |= XTENSA_MPU_TYPE_CPU_CACHE;
- if (attr & 0x10) {
- type |= XTENSA_MPU_TYPE_CPU_C;
- }
- if (attr & 0x20) {
- type |= XTENSA_MPU_TYPE_CPU_W;
- }
- if (attr & 0x40) {
- type |= XTENSA_MPU_TYPE_CPU_R;
- }
- }
- return type;
-}
-
-static unsigned mpu_attr_to_type(uint32_t attr)
-{
- static const struct attr_pattern device_type[] = {
- { .mask = 0x1f6, .value = 0x000 },
- { .mask = 0x1f6, .value = 0x006 },
- };
- static const struct attr_pattern sys_nc_type[] = {
- { .mask = 0x1fe, .value = 0x018 },
- { .mask = 0x1fe, .value = 0x01e },
- { .mask = 0x18f, .value = 0x089 },
- };
- static const struct attr_pattern sys_c_type[] = {
- { .mask = 0x1f8, .value = 0x010 },
- { .mask = 0x188, .value = 0x080 },
- { .mask = 0x1f0, .value = 0x030 },
- { .mask = 0x180, .value = 0x180 },
- };
- static const struct attr_pattern b[] = {
- { .mask = 0x1f7, .value = 0x001 },
- { .mask = 0x1f7, .value = 0x007 },
- { .mask = 0x1ff, .value = 0x019 },
- { .mask = 0x1ff, .value = 0x01f },
- };
-
- unsigned type = 0;
-
- attr = (attr & XTENSA_MPU_MEM_TYPE_MASK) >> XTENSA_MPU_MEM_TYPE_SHIFT;
- if (attr_pattern_match(attr, device_type, ARRAY_SIZE(device_type))) {
- type |= XTENSA_MPU_SYSTEM_TYPE_DEVICE;
- if (attr & 0x80) {
- type |= XTENSA_MPU_TYPE_INT;
- }
- }
- if (attr_pattern_match(attr, sys_nc_type, ARRAY_SIZE(sys_nc_type))) {
- type |= XTENSA_MPU_SYSTEM_TYPE_NC;
- }
- if (attr_pattern_match(attr, sys_c_type, ARRAY_SIZE(sys_c_type))) {
- type |= XTENSA_MPU_SYSTEM_TYPE_C;
- if (attr & 0x1) {
- type |= XTENSA_MPU_TYPE_SYS_C;
- }
- if (attr & 0x2) {
- type |= XTENSA_MPU_TYPE_SYS_W;
- }
- if (attr & 0x4) {
- type |= XTENSA_MPU_TYPE_SYS_R;
- }
- }
- if (attr_pattern_match(attr, b, ARRAY_SIZE(b))) {
- type |= XTENSA_MPU_TYPE_B;
- }
- type |= mpu_attr_to_cpu_cache(attr);
-
- return type;
-}
-
-static unsigned mpu_attr_to_access(uint32_t attr, unsigned ring)
-{
- static const unsigned access[2][16] = {
- [0] = {
- [4] = PAGE_READ,
- [5] = PAGE_READ | PAGE_EXEC,
- [6] = PAGE_READ | PAGE_WRITE,
- [7] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
- [8] = PAGE_WRITE,
- [9] = PAGE_READ | PAGE_WRITE,
- [10] = PAGE_READ | PAGE_WRITE,
- [11] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
- [12] = PAGE_READ,
- [13] = PAGE_READ | PAGE_EXEC,
- [14] = PAGE_READ | PAGE_WRITE,
- [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
- },
- [1] = {
- [8] = PAGE_WRITE,
- [9] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
- [10] = PAGE_READ,
- [11] = PAGE_READ | PAGE_EXEC,
- [12] = PAGE_READ,
- [13] = PAGE_READ | PAGE_EXEC,
- [14] = PAGE_READ | PAGE_WRITE,
- [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
- },
- };
- unsigned rv;
- unsigned type;
-
- type = mpu_attr_to_cpu_cache(attr);
- rv = access[ring != 0][(attr & XTENSA_MPU_ACC_RIGHTS_MASK) >>
- XTENSA_MPU_ACC_RIGHTS_SHIFT];
-
- if (type & XTENSA_MPU_TYPE_CPU_CACHE) {
- rv |= (type & XTENSA_MPU_TYPE_CPU_C) ? PAGE_CACHE_WB : PAGE_CACHE_WT;
- } else {
- rv |= PAGE_CACHE_BYPASS;
- }
- return rv;
-}
-
-static bool is_access_granted(unsigned access, int is_write)
-{
- switch (is_write) {
- case 0:
- return access & PAGE_READ;
-
- case 1:
- return access & PAGE_WRITE;
-
- case 2:
- return access & PAGE_EXEC;
-
- default:
- return 0;
- }
-}
-
-static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
-
-static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
- uint32_t vaddr, int is_write, int mmu_idx,
- uint32_t *paddr, uint32_t *page_size,
- unsigned *access, bool may_lookup_pt)
-{
- bool dtlb = is_write != 2;
- uint32_t wi;
- uint32_t ei;
- uint8_t ring;
- uint32_t vpn;
- uint32_t pte;
- const xtensa_tlb_entry *entry = NULL;
- xtensa_tlb_entry tmp_entry;
- int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
-
- if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
- may_lookup_pt && get_pte(env, vaddr, &pte)) {
- ring = (pte >> 4) & 0x3;
- wi = 0;
- xtensa_split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
-
- if (update_tlb) {
- wi = ++env->autorefill_idx & 0x3;
- xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
- env->sregs[EXCVADDR] = vaddr;
- qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n",
- __func__, vaddr, vpn, pte);
- } else {
- xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
- entry = &tmp_entry;
- }
- ret = 0;
- }
- if (ret != 0) {
- return ret;
- }
-
- if (entry == NULL) {
- entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
- }
-
- if (ring < mmu_idx) {
- return dtlb ?
- LOAD_STORE_PRIVILEGE_CAUSE :
- INST_FETCH_PRIVILEGE_CAUSE;
- }
-
- *access = mmu_attr_to_access(entry->attr) &
- ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
- if (!is_access_granted(*access, is_write)) {
- return dtlb ?
- (is_write ?
- STORE_PROHIBITED_CAUSE :
- LOAD_PROHIBITED_CAUSE) :
- INST_FETCH_PROHIBITED_CAUSE;
- }
-
- *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
- *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
-
- return 0;
-}
-
-static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
-{
- CPUState *cs = env_cpu(env);
- uint32_t paddr;
- uint32_t page_size;
- unsigned access;
- uint32_t pt_vaddr =
- (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
- int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
- &paddr, &page_size, &access, false);
-
- if (ret == 0) {
- qemu_log_mask(CPU_LOG_MMU,
- "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n",
- __func__, vaddr, pt_vaddr, paddr);
- } else {
- qemu_log_mask(CPU_LOG_MMU,
- "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n",
- __func__, vaddr, pt_vaddr, ret);
- }
-
- if (ret == 0) {
- MemTxResult result;
-
- *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED,
- &result);
- if (result != MEMTX_OK) {
- qemu_log_mask(CPU_LOG_MMU,
- "%s: couldn't load PTE: transaction failed (%u)\n",
- __func__, (unsigned)result);
- ret = 1;
- }
- }
- return ret == 0;
-}
-
-static int get_physical_addr_region(CPUXtensaState *env,
- uint32_t vaddr, int is_write, int mmu_idx,
- uint32_t *paddr, uint32_t *page_size,
- unsigned *access)
-{
- bool dtlb = is_write != 2;
- uint32_t wi = 0;
- uint32_t ei = (vaddr >> 29) & 0x7;
- const xtensa_tlb_entry *entry =
- xtensa_tlb_get_entry(env, dtlb, wi, ei);
-
- *access = region_attr_to_access(entry->attr);
- if (!is_access_granted(*access, is_write)) {
- return dtlb ?
- (is_write ?
- STORE_PROHIBITED_CAUSE :
- LOAD_PROHIBITED_CAUSE) :
- INST_FETCH_PROHIBITED_CAUSE;
- }
-
- *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
- *page_size = ~REGION_PAGE_MASK + 1;
-
- return 0;
-}
-
-static int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n,
- uint32_t vaddr, unsigned *segment)
-{
- unsigned nhits = 0;
- unsigned i;
-
- for (i = 0; i < n; ++i) {
- if (vaddr >= entry[i].vaddr &&
- (i == n - 1 || vaddr < entry[i + 1].vaddr)) {
- if (nhits++) {
- break;
- }
- *segment = i;
- }
- }
- return nhits;
-}
-
void HELPER(wsr_mpuenb)(CPUXtensaState *env, uint32_t v)
{
v &= (2u << (env->config->n_mpu_fg_segments - 1)) - 1;
@@ -1013,75 +194,6 @@ uint32_t HELPER(pptlb)(CPUXtensaState *env, uint32_t v)
}
}
-static int get_physical_addr_mpu(CPUXtensaState *env,
- uint32_t vaddr, int is_write, int mmu_idx,
- uint32_t *paddr, uint32_t *page_size,
- unsigned *access)
-{
- unsigned nhits;
- unsigned segment;
- uint32_t attr;
-
- nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments,
- vaddr, &segment);
- if (nhits > 1) {
- return is_write < 2 ?
- LOAD_STORE_TLB_MULTI_HIT_CAUSE :
- INST_TLB_MULTI_HIT_CAUSE;
- } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) {
- attr = env->mpu_fg[segment].attr;
- } else {
- xtensa_mpu_lookup(env->config->mpu_bg,
- env->config->n_mpu_bg_segments,
- vaddr, &segment);
- attr = env->config->mpu_bg[segment].attr;
- }
-
- *access = mpu_attr_to_access(attr, mmu_idx);
- if (!is_access_granted(*access, is_write)) {
- return is_write < 2 ?
- (is_write ?
- STORE_PROHIBITED_CAUSE :
- LOAD_PROHIBITED_CAUSE) :
- INST_FETCH_PROHIBITED_CAUSE;
- }
- *paddr = vaddr;
- *page_size = env->config->mpu_align;
- return 0;
-}
-
-/*!
- * Convert virtual address to physical addr.
- * MMU may issue pagewalk and change xtensa autorefill TLB way entry.
- *
- * \return 0 if ok, exception cause code otherwise
- */
-int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
- uint32_t vaddr, int is_write, int mmu_idx,
- uint32_t *paddr, uint32_t *page_size,
- unsigned *access)
-{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
- return get_physical_addr_mmu(env, update_tlb,
- vaddr, is_write, mmu_idx, paddr,
- page_size, access, true);
- } else if (xtensa_option_bits_enabled(env->config,
- XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
- XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
- return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
- paddr, page_size, access);
- } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) {
- return get_physical_addr_mpu(env, vaddr, is_write, mmu_idx,
- paddr, page_size, access);
- } else {
- *paddr = vaddr;
- *page_size = TARGET_PAGE_SIZE;
- *access = cacheattr_attr_to_access(env->sregs[CACHEATTR] >>
- ((vaddr & 0xe0000000) >> 27));
- return 0;
- }
-}
-
static void dump_tlb(CPUXtensaState *env, bool dtlb)
{
unsigned wi, ei;
diff --git a/target/xtensa/meson.build b/target/xtensa/meson.build
index f8d60101e3..46010c35c4 100644
--- a/target/xtensa/meson.build
+++ b/target/xtensa/meson.build
@@ -18,6 +18,7 @@ xtensa_ss.add(files(
xtensa_system_ss = ss.source_set()
xtensa_system_ss.add(files(
'dbg_helper.c',
+ 'mmu.c',
'mmu_helper.c',
'monitor.c',
'xtensa-semi.c',
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 18/21] target/xtensa: Extract MMU API to new mmu.c/mmu.h files
2024-03-21 15:48 ` [PATCH-for-9.1 18/21] target/xtensa: Extract MMU API to new mmu.c/mmu.h files Philippe Mathieu-Daudé
@ 2024-03-23 19:23 ` Max Filippov
0 siblings, 0 replies; 46+ messages in thread
From: Max Filippov @ 2024-03-23 19:23 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland
On Thu, Mar 21, 2024 at 8:50 AM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Extract the MMU API and expose it via "mmu.h" so we can
> reuse the methods in target/xtensa/ files.
The MMU/MPU are replaceable configuration blocks in the xtensa
architecture, their internals don't have architecture-wide significance
and I believe their exposure should be kept to a minimum.
I have a half-done xtensa MMU rework which I'd like to complete,
it only exposes the interface for address translation, opcode translation
and dumping.
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/xtensa/cpu.h | 32 +-
> target/xtensa/mmu.h | 95 ++++
> target/xtensa/mmu.c | 889 ++++++++++++++++++++++++++++++++++++
> target/xtensa/mmu_helper.c | 892 +------------------------------------
> target/xtensa/meson.build | 1 +
> 5 files changed, 991 insertions(+), 918 deletions(-)
> create mode 100644 target/xtensa/mmu.h
> create mode 100644 target/xtensa/mmu.c
--
Thanks.
-- Max
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH-for-9.1 19/21] target/xtensa: Simplify dump_mpu() and dump_tlb()
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 18/21] target/xtensa: Extract MMU API to new mmu.c/mmu.h files Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 15:48 ` [PATCH-for-9.1 20/21] target/xtensa: Move monitor commands to monitor.c Philippe Mathieu-Daudé
2024-03-21 15:48 ` [PATCH-for-9.1 21/21] target/xtensa: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
20 siblings, 0 replies; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Remove few qemu_printf() calls in xtensa_dump_mmu()
by slightly reworking dump_mpu() and dump_tlb().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/xtensa/mmu_helper.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index 8be8d79dcd..3b4f53feb0 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -203,6 +203,7 @@ static void dump_tlb(CPUXtensaState *env, bool dtlb)
xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
mmu_attr_to_access : region_attr_to_access;
+ qemu_printf("%s:\n", dtlb ? "DTLB" : "IBLB");
for (wi = 0; wi < conf->nways; ++wi) {
uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
const char *sz_text;
@@ -252,11 +253,12 @@ static void dump_tlb(CPUXtensaState *env, bool dtlb)
}
}
-static void dump_mpu(CPUXtensaState *env,
+static void dump_mpu(CPUXtensaState *env, const char *map_desc,
const xtensa_mpu_entry *entry, unsigned n)
{
unsigned i;
+ qemu_printf("%s map:\n", map_desc);
qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n"
"\t%s ---------- ---------- ----- ----- ------------- ---------\n",
env ? "En" : " ",
@@ -316,15 +318,15 @@ void xtensa_dump_mmu(CPUXtensaState *env)
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
- qemu_printf("ITLB:\n");
dump_tlb(env, false);
- qemu_printf("\nDTLB:\n");
+ qemu_printf("\n");
dump_tlb(env, true);
} else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) {
- qemu_printf("Foreground map:\n");
- dump_mpu(env, env->mpu_fg, env->config->n_mpu_fg_segments);
- qemu_printf("\nBackground map:\n");
- dump_mpu(NULL, env->config->mpu_bg, env->config->n_mpu_bg_segments);
+ dump_mpu(env, "Foreground",
+ env->mpu_fg, env->config->n_mpu_fg_segments);
+ qemu_printf("\n");
+ dump_mpu(NULL, "Background",
+ env->config->mpu_bg, env->config->n_mpu_bg_segments);
} else {
qemu_printf("No TLB for this CPU core\n");
}
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH-for-9.1 20/21] target/xtensa: Move monitor commands to monitor.c
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (18 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 19/21] target/xtensa: Simplify dump_mpu() and dump_tlb() Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-03-21 15:48 ` [PATCH-for-9.1 21/21] target/xtensa: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
20 siblings, 0 replies; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/xtensa/mmu_helper.c | 140 ------------------------------------
target/xtensa/monitor.c | 144 ++++++++++++++++++++++++++++++++++++-
2 files changed, 143 insertions(+), 141 deletions(-)
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index 3b4f53feb0..892730f0f0 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -26,8 +26,6 @@
*/
#include "qemu/osdep.h"
-#include "qemu/qemu-print.h"
-#include "qemu/units.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "cpu.h"
@@ -193,141 +191,3 @@ uint32_t HELPER(pptlb)(CPUXtensaState *env, uint32_t v)
return env->config->mpu_bg[bg_segment].attr | segment;
}
}
-
-static void dump_tlb(CPUXtensaState *env, bool dtlb)
-{
- unsigned wi, ei;
- const xtensa_tlb *conf =
- dtlb ? &env->config->dtlb : &env->config->itlb;
- unsigned (*attr_to_access)(uint32_t) =
- xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
- mmu_attr_to_access : region_attr_to_access;
-
- qemu_printf("%s:\n", dtlb ? "DTLB" : "IBLB");
- for (wi = 0; wi < conf->nways; ++wi) {
- uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
- const char *sz_text;
- bool print_header = true;
-
- if (sz >= 0x100000) {
- sz /= MiB;
- sz_text = "MB";
- } else {
- sz /= KiB;
- sz_text = "KB";
- }
-
- for (ei = 0; ei < conf->way_size[wi]; ++ei) {
- const xtensa_tlb_entry *entry =
- xtensa_tlb_get_entry(env, dtlb, wi, ei);
-
- if (entry->asid) {
- static const char * const cache_text[8] = {
- [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
- [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
- [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
- [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
- };
- unsigned access = attr_to_access(entry->attr);
- unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
- PAGE_CACHE_SHIFT;
-
- if (print_header) {
- print_header = false;
- qemu_printf("Way %u (%d %s)\n", wi, sz, sz_text);
- qemu_printf("\tVaddr Paddr ASID Attr RWX Cache\n"
- "\t---------- ---------- ---- ---- --- -------\n");
- }
- qemu_printf("\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %s\n",
- entry->vaddr,
- entry->paddr,
- entry->asid,
- entry->attr,
- (access & PAGE_READ) ? 'R' : '-',
- (access & PAGE_WRITE) ? 'W' : '-',
- (access & PAGE_EXEC) ? 'X' : '-',
- cache_text[cache_idx] ?
- cache_text[cache_idx] : "Invalid");
- }
- }
- }
-}
-
-static void dump_mpu(CPUXtensaState *env, const char *map_desc,
- const xtensa_mpu_entry *entry, unsigned n)
-{
- unsigned i;
-
- qemu_printf("%s map:\n", map_desc);
- qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n"
- "\t%s ---------- ---------- ----- ----- ------------- ---------\n",
- env ? "En" : " ",
- env ? "--" : " ");
-
- for (i = 0; i < n; ++i) {
- uint32_t attr = entry[i].attr;
- unsigned access0 = mpu_attr_to_access(attr, 0);
- unsigned access1 = mpu_attr_to_access(attr, 1);
- unsigned type = mpu_attr_to_type(attr);
- char cpu_cache = (type & XTENSA_MPU_TYPE_CPU_CACHE) ? '-' : ' ';
-
- qemu_printf("\t %c 0x%08x 0x%08x %c%c%c %c%c%c ",
- env ?
- ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ',
- entry[i].vaddr, attr,
- (access0 & PAGE_READ) ? 'R' : '-',
- (access0 & PAGE_WRITE) ? 'W' : '-',
- (access0 & PAGE_EXEC) ? 'X' : '-',
- (access1 & PAGE_READ) ? 'R' : '-',
- (access1 & PAGE_WRITE) ? 'W' : '-',
- (access1 & PAGE_EXEC) ? 'X' : '-');
-
- switch (type & XTENSA_MPU_SYSTEM_TYPE_MASK) {
- case XTENSA_MPU_SYSTEM_TYPE_DEVICE:
- qemu_printf("Device %cB %3s\n",
- (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n',
- (type & XTENSA_MPU_TYPE_INT) ? "int" : "");
- break;
- case XTENSA_MPU_SYSTEM_TYPE_NC:
- qemu_printf("Sys NC %cB %c%c%c\n",
- (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n',
- (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache,
- (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache,
- (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache);
- break;
- case XTENSA_MPU_SYSTEM_TYPE_C:
- qemu_printf("Sys C %c%c%c %c%c%c\n",
- (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-',
- (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-',
- (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-',
- (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache,
- (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache,
- (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache);
- break;
- default:
- qemu_printf("Unknown\n");
- break;
- }
- }
-}
-
-void xtensa_dump_mmu(CPUXtensaState *env)
-{
- if (xtensa_option_bits_enabled(env->config,
- XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
- XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
- XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
-
- dump_tlb(env, false);
- qemu_printf("\n");
- dump_tlb(env, true);
- } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) {
- dump_mpu(env, "Foreground",
- env->mpu_fg, env->config->n_mpu_fg_segments);
- qemu_printf("\n");
- dump_mpu(NULL, "Background",
- env->config->mpu_bg, env->config->n_mpu_bg_segments);
- } else {
- qemu_printf("No TLB for this CPU core\n");
- }
-}
diff --git a/target/xtensa/monitor.c b/target/xtensa/monitor.c
index ce1b791a5c..9ba068d624 100644
--- a/target/xtensa/monitor.c
+++ b/target/xtensa/monitor.c
@@ -22,10 +22,152 @@
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
-#include "cpu.h"
+#include "qemu/qemu-print.h"
+#include "qemu/units.h"
#include "monitor/monitor.h"
#include "monitor/hmp-target.h"
#include "monitor/hmp.h"
+#include "cpu.h"
+#include "mmu.h"
+
+
+static void dump_tlb(CPUXtensaState *env, bool dtlb)
+{
+ unsigned wi, ei;
+ const xtensa_tlb *conf =
+ dtlb ? &env->config->dtlb : &env->config->itlb;
+ unsigned (*attr_to_access)(uint32_t) =
+ xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
+ mmu_attr_to_access : region_attr_to_access;
+
+ qemu_printf("%s:\n", dtlb ? "DTLB" : "IBLB");
+ for (wi = 0; wi < conf->nways; ++wi) {
+ uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
+ const char *sz_text;
+ bool print_header = true;
+
+ if (sz >= 0x100000) {
+ sz /= MiB;
+ sz_text = "MB";
+ } else {
+ sz /= KiB;
+ sz_text = "KB";
+ }
+
+ for (ei = 0; ei < conf->way_size[wi]; ++ei) {
+ const xtensa_tlb_entry *entry =
+ xtensa_tlb_get_entry(env, dtlb, wi, ei);
+
+ if (entry->asid) {
+ static const char * const cache_text[8] = {
+ [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
+ [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
+ [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
+ [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
+ };
+ unsigned access = attr_to_access(entry->attr);
+ unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
+ PAGE_CACHE_SHIFT;
+
+ if (print_header) {
+ print_header = false;
+ qemu_printf("Way %u (%d %s)\n", wi, sz, sz_text);
+ qemu_printf("\tVaddr Paddr ASID Attr RWX Cache\n"
+ "\t---------- ---------- ---- ---- --- -------\n");
+ }
+ qemu_printf("\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %s\n",
+ entry->vaddr,
+ entry->paddr,
+ entry->asid,
+ entry->attr,
+ (access & PAGE_READ) ? 'R' : '-',
+ (access & PAGE_WRITE) ? 'W' : '-',
+ (access & PAGE_EXEC) ? 'X' : '-',
+ cache_text[cache_idx] ?
+ cache_text[cache_idx] : "Invalid");
+ }
+ }
+ }
+}
+
+static void dump_mpu(CPUXtensaState *env, const char *map_desc,
+ const xtensa_mpu_entry *entry, unsigned n)
+{
+ unsigned i;
+
+ qemu_printf("%s map:\n", map_desc);
+ qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n"
+ "\t%s ---------- ---------- ----- ----- ------------- ---------\n",
+ env ? "En" : " ",
+ env ? "--" : " ");
+
+ for (i = 0; i < n; ++i) {
+ uint32_t attr = entry[i].attr;
+ unsigned access0 = mpu_attr_to_access(attr, 0);
+ unsigned access1 = mpu_attr_to_access(attr, 1);
+ unsigned type = mpu_attr_to_type(attr);
+ char cpu_cache = (type & XTENSA_MPU_TYPE_CPU_CACHE) ? '-' : ' ';
+
+ qemu_printf("\t %c 0x%08x 0x%08x %c%c%c %c%c%c ",
+ env ?
+ ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ',
+ entry[i].vaddr, attr,
+ (access0 & PAGE_READ) ? 'R' : '-',
+ (access0 & PAGE_WRITE) ? 'W' : '-',
+ (access0 & PAGE_EXEC) ? 'X' : '-',
+ (access1 & PAGE_READ) ? 'R' : '-',
+ (access1 & PAGE_WRITE) ? 'W' : '-',
+ (access1 & PAGE_EXEC) ? 'X' : '-');
+
+ switch (type & XTENSA_MPU_SYSTEM_TYPE_MASK) {
+ case XTENSA_MPU_SYSTEM_TYPE_DEVICE:
+ qemu_printf("Device %cB %3s\n",
+ (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n',
+ (type & XTENSA_MPU_TYPE_INT) ? "int" : "");
+ break;
+ case XTENSA_MPU_SYSTEM_TYPE_NC:
+ qemu_printf("Sys NC %cB %c%c%c\n",
+ (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n',
+ (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache,
+ (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache,
+ (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache);
+ break;
+ case XTENSA_MPU_SYSTEM_TYPE_C:
+ qemu_printf("Sys C %c%c%c %c%c%c\n",
+ (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-',
+ (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-',
+ (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-',
+ (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache,
+ (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache,
+ (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache);
+ break;
+ default:
+ qemu_printf("Unknown\n");
+ break;
+ }
+ }
+}
+
+void xtensa_dump_mmu(CPUXtensaState *env)
+{
+ if (xtensa_option_bits_enabled(env->config,
+ XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
+ XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
+ XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
+
+ dump_tlb(env, false);
+ qemu_printf("\n");
+ dump_tlb(env, true);
+ } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) {
+ dump_mpu(env, "Foreground",
+ env->mpu_fg, env->config->n_mpu_fg_segments);
+ qemu_printf("\n");
+ dump_mpu(NULL, "Background",
+ env->config->mpu_bg, env->config->n_mpu_bg_segments);
+ } else {
+ qemu_printf("No TLB for this CPU core\n");
+ }
+}
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
{
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH-for-9.1 21/21] target/xtensa: Replace qemu_printf() by monitor_printf() in monitor
2024-03-21 15:48 [PATCH-for-9.1 00/21] target/monitor: Cleanup around hmp_info_tlb() Philippe Mathieu-Daudé
` (19 preceding siblings ...)
2024-03-21 15:48 ` [PATCH-for-9.1 20/21] target/xtensa: Move monitor commands to monitor.c Philippe Mathieu-Daudé
@ 2024-03-21 15:48 ` Philippe Mathieu-Daudé
2024-04-24 7:45 ` Markus Armbruster
20 siblings, 1 reply; 46+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-21 15:48 UTC (permalink / raw)
To: qemu-devel
Cc: Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias, Marek Vasut,
Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland, Philippe Mathieu-Daudé
Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/xtensa/mmu.h | 2 +-
target/xtensa/monitor.c | 117 ++++++++++++++++++++--------------------
2 files changed, 61 insertions(+), 58 deletions(-)
diff --git a/target/xtensa/mmu.h b/target/xtensa/mmu.h
index 3e1d2c03ea..ef7504e16e 100644
--- a/target/xtensa/mmu.h
+++ b/target/xtensa/mmu.h
@@ -90,6 +90,6 @@ int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
unsigned *access);
void xtensa_reset_mmu(CPUXtensaState *env);
-void xtensa_dump_mmu(CPUXtensaState *env);
+void xtensa_dump_mmu(Monitor *mon, CPUXtensaState *env);
#endif
diff --git a/target/xtensa/monitor.c b/target/xtensa/monitor.c
index 9ba068d624..1c3dc85ea1 100644
--- a/target/xtensa/monitor.c
+++ b/target/xtensa/monitor.c
@@ -22,7 +22,6 @@
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
-#include "qemu/qemu-print.h"
#include "qemu/units.h"
#include "monitor/monitor.h"
#include "monitor/hmp-target.h"
@@ -31,7 +30,7 @@
#include "mmu.h"
-static void dump_tlb(CPUXtensaState *env, bool dtlb)
+static void dump_tlb(Monitor *mon, CPUXtensaState *env, bool dtlb)
{
unsigned wi, ei;
const xtensa_tlb *conf =
@@ -40,7 +39,7 @@ static void dump_tlb(CPUXtensaState *env, bool dtlb)
xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
mmu_attr_to_access : region_attr_to_access;
- qemu_printf("%s:\n", dtlb ? "DTLB" : "IBLB");
+ monitor_puts(mon, dtlb ? "DTLB\n" : "IBLB\n");
for (wi = 0; wi < conf->nways; ++wi) {
uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
const char *sz_text;
@@ -71,35 +70,39 @@ static void dump_tlb(CPUXtensaState *env, bool dtlb)
if (print_header) {
print_header = false;
- qemu_printf("Way %u (%d %s)\n", wi, sz, sz_text);
- qemu_printf("\tVaddr Paddr ASID Attr RWX Cache\n"
- "\t---------- ---------- ---- ---- --- -------\n");
+ monitor_printf(mon,
+ "Way %u (%d %s)\n", wi, sz, sz_text);
+ monitor_puts(mon,
+ "\tVaddr Paddr ASID Attr RWX Cache\n"
+ "\t---------- ---------- ---- ---- --- -------\n");
}
- qemu_printf("\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %s\n",
- entry->vaddr,
- entry->paddr,
- entry->asid,
- entry->attr,
- (access & PAGE_READ) ? 'R' : '-',
- (access & PAGE_WRITE) ? 'W' : '-',
- (access & PAGE_EXEC) ? 'X' : '-',
- cache_text[cache_idx] ?
- cache_text[cache_idx] : "Invalid");
+ monitor_printf(mon,
+ "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %s\n",
+ entry->vaddr,
+ entry->paddr,
+ entry->asid,
+ entry->attr,
+ (access & PAGE_READ) ? 'R' : '-',
+ (access & PAGE_WRITE) ? 'W' : '-',
+ (access & PAGE_EXEC) ? 'X' : '-',
+ cache_text[cache_idx] ?
+ cache_text[cache_idx] : "Invalid");
}
}
}
}
-static void dump_mpu(CPUXtensaState *env, const char *map_desc,
+static void dump_mpu(Monitor *mon, CPUXtensaState *env, const char *map_desc,
const xtensa_mpu_entry *entry, unsigned n)
{
unsigned i;
- qemu_printf("%s map:\n", map_desc);
- qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n"
- "\t%s ---------- ---------- ----- ----- ------------- ---------\n",
- env ? "En" : " ",
- env ? "--" : " ");
+ monitor_printf(mon, "%s map:\n", map_desc);
+ monitor_printf(mon,
+ "\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n"
+ "\t%s ---------- ---------- ----- ----- ------------- ---------\n",
+ env ? "En" : " ",
+ env ? "--" : " ");
for (i = 0; i < n; ++i) {
uint32_t attr = entry[i].attr;
@@ -108,64 +111,64 @@ static void dump_mpu(CPUXtensaState *env, const char *map_desc,
unsigned type = mpu_attr_to_type(attr);
char cpu_cache = (type & XTENSA_MPU_TYPE_CPU_CACHE) ? '-' : ' ';
- qemu_printf("\t %c 0x%08x 0x%08x %c%c%c %c%c%c ",
- env ?
- ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ',
- entry[i].vaddr, attr,
- (access0 & PAGE_READ) ? 'R' : '-',
- (access0 & PAGE_WRITE) ? 'W' : '-',
- (access0 & PAGE_EXEC) ? 'X' : '-',
- (access1 & PAGE_READ) ? 'R' : '-',
- (access1 & PAGE_WRITE) ? 'W' : '-',
- (access1 & PAGE_EXEC) ? 'X' : '-');
+ monitor_printf(mon, "\t %c 0x%08x 0x%08x %c%c%c %c%c%c ",
+ env ?
+ ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ',
+ entry[i].vaddr, attr,
+ (access0 & PAGE_READ) ? 'R' : '-',
+ (access0 & PAGE_WRITE) ? 'W' : '-',
+ (access0 & PAGE_EXEC) ? 'X' : '-',
+ (access1 & PAGE_READ) ? 'R' : '-',
+ (access1 & PAGE_WRITE) ? 'W' : '-',
+ (access1 & PAGE_EXEC) ? 'X' : '-');
switch (type & XTENSA_MPU_SYSTEM_TYPE_MASK) {
case XTENSA_MPU_SYSTEM_TYPE_DEVICE:
- qemu_printf("Device %cB %3s\n",
- (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n',
- (type & XTENSA_MPU_TYPE_INT) ? "int" : "");
+ monitor_printf(mon, "Device %cB %3s\n",
+ (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n',
+ (type & XTENSA_MPU_TYPE_INT) ? "int" : "");
break;
case XTENSA_MPU_SYSTEM_TYPE_NC:
- qemu_printf("Sys NC %cB %c%c%c\n",
- (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n',
- (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache,
- (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache,
- (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache);
+ monitor_printf(mon, "Sys NC %cB %c%c%c\n",
+ (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n',
+ (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache,
+ (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache,
+ (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache);
break;
case XTENSA_MPU_SYSTEM_TYPE_C:
- qemu_printf("Sys C %c%c%c %c%c%c\n",
- (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-',
- (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-',
- (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-',
- (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache,
- (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache,
- (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache);
+ monitor_printf(mon, "Sys C %c%c%c %c%c%c\n",
+ (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-',
+ (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-',
+ (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-',
+ (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache,
+ (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache,
+ (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache);
break;
default:
- qemu_printf("Unknown\n");
+ monitor_puts(mon, "Unknown\n");
break;
}
}
}
-void xtensa_dump_mmu(CPUXtensaState *env)
+void xtensa_dump_mmu(Monitor *mon, CPUXtensaState *env)
{
if (xtensa_option_bits_enabled(env->config,
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
- dump_tlb(env, false);
- qemu_printf("\n");
- dump_tlb(env, true);
+ dump_tlb(mon, env, false);
+ monitor_puts(mon, "\n");
+ dump_tlb(mon, env, true);
} else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) {
- dump_mpu(env, "Foreground",
+ dump_mpu(mon, env, "Foreground",
env->mpu_fg, env->config->n_mpu_fg_segments);
- qemu_printf("\n");
- dump_mpu(NULL, "Background",
+ monitor_puts(mon, "\n");
+ dump_mpu(mon, NULL, "Background",
env->config->mpu_bg, env->config->n_mpu_bg_segments);
} else {
- qemu_printf("No TLB for this CPU core\n");
+ monitor_puts(mon, "No TLB for this CPU core\n");
}
}
@@ -177,5 +180,5 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
monitor_printf(mon, "No CPU available\n");
return;
}
- xtensa_dump_mmu(env1);
+ xtensa_dump_mmu(mon, env1);
}
--
2.41.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH-for-9.1 21/21] target/xtensa: Replace qemu_printf() by monitor_printf() in monitor
2024-03-21 15:48 ` [PATCH-for-9.1 21/21] target/xtensa: Replace qemu_printf() by monitor_printf() in monitor Philippe Mathieu-Daudé
@ 2024-04-24 7:45 ` Markus Armbruster
0 siblings, 0 replies; 46+ messages in thread
From: Markus Armbruster @ 2024-04-24 7:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Artyom Tarasenko, Chris Wulff, Edgar E. Iglesias,
Marek Vasut, Max Filippov, Dr . David Alan Gilbert, Jiaxun Yang,
Nicholas Piggin, Paolo Bonzini, Daniel Henrique Barboza,
Yoshinori Sato, Markus Armbruster, Richard Henderson, qemu-ppc,
Laurent Vivier, Mark Cave-Ayland
Philippe Mathieu-Daudé <philmd@linaro.org> writes:
> Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
My review comments to PATCH 05 apply.
Reviewed-by: Markus Armbruster <armbru@redhat.com>
^ permalink raw reply [flat|nested] 46+ messages in thread