All of lore.kernel.org
 help / color / mirror / Atom feed
From: Xiao Guangrong <guangrong.xiao@gmail.com>
To: Paolo Bonzini <pbonzini@redhat.com>, "Emilio G. Cota" <cota@braap.org>
Cc: kvm@vger.kernel.org, quintela@redhat.com, mtosatti@redhat.com,
	Xiao Guangrong <xiaoguangrong@tencent.com>,
	qemu-devel@nongnu.org, peterx@redhat.com, dgilbert@redhat.com,
	wei.w.wang@intel.com, mst@redhat.com, jiang.biao2@zte.com.cn
Subject: Re: [PATCH 1/4] ptr_ring: port ptr_ring from linux kernel to QEMU
Date: Thu, 18 Oct 2018 14:52:17 +0800	[thread overview]
Message-ID: <a37a8ddb-e6f3-083c-1251-cba835a214f8@gmail.com> (raw)
In-Reply-To: <40c0df2a-5a3e-5296-0894-efadf47f3d56@redhat.com>



On 10/17/2018 04:14 PM, Paolo Bonzini wrote:
> On 16/10/2018 18:40, Emilio G. Cota wrote:
>>> +#define SMP_CACHE_BYTES      64
>>> +#define ____cacheline_aligned_in_smp \
>>> +        __attribute__((__aligned__(SMP_CACHE_BYTES)))
>> You could use QEMU_ALIGNED() here.

Yes, you are right.

>>
>>> +
>>> +#define WRITE_ONCE(ptr, val) \
>>> +    (*((volatile typeof(ptr) *)(&(ptr))) = (val))
>>> +#define READ_ONCE(ptr) (*((volatile typeof(ptr) *)(&(ptr))))
>> Why not atomic_read/set, like in the rest of the QEMU code base?
> 
> Or even atomic_rcu_read/atomic_rcu_set, which includes the necessary
> barriers.
> 

Okay, will fix it, thank you and Emilio for pointing the
issue out.

> Also, please do not use __ identifiers in QEMU code.
> ____cacheline_aligned_in_smp can become just QEMU_ALIGNED(SMP_CACHE_BYTES).
> 

Sure, will keep that in my mind. :)

WARNING: multiple messages have this Message-ID (diff)
From: Xiao Guangrong <guangrong.xiao@gmail.com>
To: Paolo Bonzini <pbonzini@redhat.com>, "Emilio G. Cota" <cota@braap.org>
Cc: mst@redhat.com, mtosatti@redhat.com, kvm@vger.kernel.org,
	quintela@redhat.com, Xiao Guangrong <xiaoguangrong@tencent.com>,
	qemu-devel@nongnu.org, peterx@redhat.com, dgilbert@redhat.com,
	wei.w.wang@intel.com, jiang.biao2@zte.com.cn
Subject: Re: [Qemu-devel] [PATCH 1/4] ptr_ring: port ptr_ring from linux kernel to QEMU
Date: Thu, 18 Oct 2018 14:52:17 +0800	[thread overview]
Message-ID: <a37a8ddb-e6f3-083c-1251-cba835a214f8@gmail.com> (raw)
In-Reply-To: <40c0df2a-5a3e-5296-0894-efadf47f3d56@redhat.com>



On 10/17/2018 04:14 PM, Paolo Bonzini wrote:
> On 16/10/2018 18:40, Emilio G. Cota wrote:
>>> +#define SMP_CACHE_BYTES      64
>>> +#define ____cacheline_aligned_in_smp \
>>> +        __attribute__((__aligned__(SMP_CACHE_BYTES)))
>> You could use QEMU_ALIGNED() here.

Yes, you are right.

>>
>>> +
>>> +#define WRITE_ONCE(ptr, val) \
>>> +    (*((volatile typeof(ptr) *)(&(ptr))) = (val))
>>> +#define READ_ONCE(ptr) (*((volatile typeof(ptr) *)(&(ptr))))
>> Why not atomic_read/set, like in the rest of the QEMU code base?
> 
> Or even atomic_rcu_read/atomic_rcu_set, which includes the necessary
> barriers.
> 

Okay, will fix it, thank you and Emilio for pointing the
issue out.

> Also, please do not use __ identifiers in QEMU code.
> ____cacheline_aligned_in_smp can become just QEMU_ALIGNED(SMP_CACHE_BYTES).
> 

Sure, will keep that in my mind. :)

  reply	other threads:[~2018-10-18  6:52 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-16 11:10 [PATCH 0/4] migration: improve multithreads guangrong.xiao
2018-10-16 11:10 ` [Qemu-devel] " guangrong.xiao
2018-10-16 11:10 ` [PATCH 1/4] ptr_ring: port ptr_ring from linux kernel to QEMU guangrong.xiao
2018-10-16 11:10   ` [Qemu-devel] " guangrong.xiao
2018-10-16 16:40   ` Emilio G. Cota
2018-10-16 16:40     ` [Qemu-devel] " Emilio G. Cota
2018-10-17  8:14     ` Paolo Bonzini
2018-10-17  8:14       ` [Qemu-devel] " Paolo Bonzini
2018-10-18  6:52       ` Xiao Guangrong [this message]
2018-10-18  6:52         ` Xiao Guangrong
2018-10-16 11:10 ` [PATCH 2/4] migration: introduce lockless multithreads model guangrong.xiao
2018-10-16 11:10   ` [Qemu-devel] " guangrong.xiao
2018-10-17 10:10   ` Paolo Bonzini
2018-10-17 10:10     ` [Qemu-devel] " Paolo Bonzini
2018-10-18  9:30     ` Xiao Guangrong
2018-10-18  9:30       ` [Qemu-devel] " Xiao Guangrong
2018-10-18 10:39       ` Paolo Bonzini
2018-10-18 10:39         ` [Qemu-devel] " Paolo Bonzini
2018-10-26 23:33     ` Emilio G. Cota
2018-10-26 23:33       ` [Qemu-devel] " Emilio G. Cota
2018-10-28  7:50       ` Paolo Bonzini
2018-10-28  7:50         ` [Qemu-devel] " Paolo Bonzini
2018-10-29  2:52         ` Xiao Guangrong
2018-10-29  2:52           ` [Qemu-devel] " Xiao Guangrong
2018-10-16 11:10 ` [PATCH 3/4] migration: use lockless Multithread model for compression guangrong.xiao
2018-10-16 11:10   ` [Qemu-devel] " guangrong.xiao
2018-10-16 11:10 ` [PATCH 4/4] migration: use lockless Multithread model for decompression guangrong.xiao
2018-10-16 11:10   ` [Qemu-devel] " guangrong.xiao

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=a37a8ddb-e6f3-083c-1251-cba835a214f8@gmail.com \
    --to=guangrong.xiao@gmail.com \
    --cc=cota@braap.org \
    --cc=dgilbert@redhat.com \
    --cc=jiang.biao2@zte.com.cn \
    --cc=kvm@vger.kernel.org \
    --cc=mst@redhat.com \
    --cc=mtosatti@redhat.com \
    --cc=pbonzini@redhat.com \
    --cc=peterx@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=quintela@redhat.com \
    --cc=wei.w.wang@intel.com \
    --cc=xiaoguangrong@tencent.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.