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From: Robin Murphy <robin.murphy@arm.com>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
	linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,
	iommu@lists.linux-foundation.org
Cc: linuxarm@huawei.com, lorenzo.pieralisi@arm.com, joro@8bytes.org,
	wanghuiqiang@huawei.com, guohanjun@huawei.com,
	steven.price@arm.com, Sami.Mujawar@arm.com, jon@solid-run.com,
	eric.auger@redhat.com, yangyicong@huawei.com
Subject: Re: [PATCH v5 5/8] iommu/arm-smmu-v3: Add bypass flag to arm_smmu_write_strtab_ent()
Date: Mon, 14 Jun 2021 11:23:07 +0100	[thread overview]
Message-ID: <ab9a8ca2-8611-2dcc-8b03-e13715521905@arm.com> (raw)
In-Reply-To: <20210524110222.2212-6-shameerali.kolothum.thodi@huawei.com>

On 2021-05-24 12:02, Shameer Kolothum wrote:
> By default, disable_bypass is set and any dev without an iommu domain
> installs STE with CFG_ABORT during arm_smmu_init_bypass_stes(). Introduce
> a "bypass" flag to arm_smmu_write_strtab_ent() so that we can force it to
> install CFG_BYPASS STE for specific SIDs. This will be useful in follow
> up patch to install bypass for IORT RMR SIDs.
> 
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> ---
>   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> index 754bad6092c1..f9195b740f48 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> @@ -1174,7 +1174,7 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
>   }
>   
>   static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
> -				      __le64 *dst)
> +				      __le64 *dst, bool bypass)
>   {
>   	/*
>   	 * This is hideously complicated, but we only really care about
> @@ -1245,7 +1245,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
>   
>   	/* Bypass/fault */
>   	if (!smmu_domain || !(s1_cfg || s2_cfg)) {
> -		if (!smmu_domain && disable_bypass)
> +		if (!smmu_domain && disable_bypass && !bypass)

Umm...

>   			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT);
>   		else
>   			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);
> @@ -1320,7 +1320,7 @@ static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent)
>   	unsigned int i;
>   
>   	for (i = 0; i < nent; ++i) {
> -		arm_smmu_write_strtab_ent(NULL, -1, strtab);
> +		arm_smmu_write_strtab_ent(NULL, -1, strtab, false);

...and in particular, an operation named "init_bypass_stes" passing 
bypass=false is just breaking my brain. Can we pull the logic for 
default bypass/fault out to here as part of the refactoring so that it 
actually makes sense?

Robin.

>   		strtab += STRTAB_STE_DWORDS;
>   	}
>   }
> @@ -2097,7 +2097,7 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master)
>   		if (j < i)
>   			continue;
>   
> -		arm_smmu_write_strtab_ent(master, sid, step);
> +		arm_smmu_write_strtab_ent(master, sid, step, false);
>   	}
>   }
>   
> 

WARNING: multiple messages have this Message-ID (diff)
From: Robin Murphy <robin.murphy@arm.com>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
	linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,
	iommu@lists.linux-foundation.org
Cc: jon@solid-run.com, linuxarm@huawei.com, steven.price@arm.com,
	guohanjun@huawei.com, yangyicong@huawei.com,
	Sami.Mujawar@arm.com, wanghuiqiang@huawei.com
Subject: Re: [PATCH v5 5/8] iommu/arm-smmu-v3: Add bypass flag to arm_smmu_write_strtab_ent()
Date: Mon, 14 Jun 2021 11:23:07 +0100	[thread overview]
Message-ID: <ab9a8ca2-8611-2dcc-8b03-e13715521905@arm.com> (raw)
In-Reply-To: <20210524110222.2212-6-shameerali.kolothum.thodi@huawei.com>

On 2021-05-24 12:02, Shameer Kolothum wrote:
> By default, disable_bypass is set and any dev without an iommu domain
> installs STE with CFG_ABORT during arm_smmu_init_bypass_stes(). Introduce
> a "bypass" flag to arm_smmu_write_strtab_ent() so that we can force it to
> install CFG_BYPASS STE for specific SIDs. This will be useful in follow
> up patch to install bypass for IORT RMR SIDs.
> 
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> ---
>   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> index 754bad6092c1..f9195b740f48 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> @@ -1174,7 +1174,7 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
>   }
>   
>   static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
> -				      __le64 *dst)
> +				      __le64 *dst, bool bypass)
>   {
>   	/*
>   	 * This is hideously complicated, but we only really care about
> @@ -1245,7 +1245,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
>   
>   	/* Bypass/fault */
>   	if (!smmu_domain || !(s1_cfg || s2_cfg)) {
> -		if (!smmu_domain && disable_bypass)
> +		if (!smmu_domain && disable_bypass && !bypass)

Umm...

>   			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT);
>   		else
>   			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);
> @@ -1320,7 +1320,7 @@ static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent)
>   	unsigned int i;
>   
>   	for (i = 0; i < nent; ++i) {
> -		arm_smmu_write_strtab_ent(NULL, -1, strtab);
> +		arm_smmu_write_strtab_ent(NULL, -1, strtab, false);

...and in particular, an operation named "init_bypass_stes" passing 
bypass=false is just breaking my brain. Can we pull the logic for 
default bypass/fault out to here as part of the refactoring so that it 
actually makes sense?

Robin.

>   		strtab += STRTAB_STE_DWORDS;
>   	}
>   }
> @@ -2097,7 +2097,7 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master)
>   		if (j < i)
>   			continue;
>   
> -		arm_smmu_write_strtab_ent(master, sid, step);
> +		arm_smmu_write_strtab_ent(master, sid, step, false);
>   	}
>   }
>   
> 
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Robin Murphy <robin.murphy@arm.com>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
	linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,
	iommu@lists.linux-foundation.org
Cc: linuxarm@huawei.com, lorenzo.pieralisi@arm.com, joro@8bytes.org,
	wanghuiqiang@huawei.com, guohanjun@huawei.com,
	steven.price@arm.com, Sami.Mujawar@arm.com, jon@solid-run.com,
	eric.auger@redhat.com, yangyicong@huawei.com
Subject: Re: [PATCH v5 5/8] iommu/arm-smmu-v3: Add bypass flag to arm_smmu_write_strtab_ent()
Date: Mon, 14 Jun 2021 11:23:07 +0100	[thread overview]
Message-ID: <ab9a8ca2-8611-2dcc-8b03-e13715521905@arm.com> (raw)
In-Reply-To: <20210524110222.2212-6-shameerali.kolothum.thodi@huawei.com>

On 2021-05-24 12:02, Shameer Kolothum wrote:
> By default, disable_bypass is set and any dev without an iommu domain
> installs STE with CFG_ABORT during arm_smmu_init_bypass_stes(). Introduce
> a "bypass" flag to arm_smmu_write_strtab_ent() so that we can force it to
> install CFG_BYPASS STE for specific SIDs. This will be useful in follow
> up patch to install bypass for IORT RMR SIDs.
> 
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> ---
>   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> index 754bad6092c1..f9195b740f48 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> @@ -1174,7 +1174,7 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
>   }
>   
>   static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
> -				      __le64 *dst)
> +				      __le64 *dst, bool bypass)
>   {
>   	/*
>   	 * This is hideously complicated, but we only really care about
> @@ -1245,7 +1245,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
>   
>   	/* Bypass/fault */
>   	if (!smmu_domain || !(s1_cfg || s2_cfg)) {
> -		if (!smmu_domain && disable_bypass)
> +		if (!smmu_domain && disable_bypass && !bypass)

Umm...

>   			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT);
>   		else
>   			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);
> @@ -1320,7 +1320,7 @@ static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent)
>   	unsigned int i;
>   
>   	for (i = 0; i < nent; ++i) {
> -		arm_smmu_write_strtab_ent(NULL, -1, strtab);
> +		arm_smmu_write_strtab_ent(NULL, -1, strtab, false);

...and in particular, an operation named "init_bypass_stes" passing 
bypass=false is just breaking my brain. Can we pull the logic for 
default bypass/fault out to here as part of the refactoring so that it 
actually makes sense?

Robin.

>   		strtab += STRTAB_STE_DWORDS;
>   	}
>   }
> @@ -2097,7 +2097,7 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master)
>   		if (j < i)
>   			continue;
>   
> -		arm_smmu_write_strtab_ent(master, sid, step);
> +		arm_smmu_write_strtab_ent(master, sid, step, false);
>   	}
>   }
>   
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-06-14 10:23 UTC|newest]

Thread overview: 121+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-24 11:02 [PATCH v5 0/8] ACPI/IORT: Support for IORT RMR node Shameer Kolothum
2021-05-24 11:02 ` Shameer Kolothum
2021-05-24 11:02 ` Shameer Kolothum
2021-05-24 11:02 ` [PATCH v5 1/8] ACPI/IORT: Add support for RMR node parsing Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-06-14 11:14   ` Robin Murphy
2021-06-14 11:14     ` Robin Murphy
2021-06-14 11:14     ` Robin Murphy
2021-06-14 12:37     ` Shameerali Kolothum Thodi
2021-06-14 12:37       ` Shameerali Kolothum Thodi
2021-06-14 12:37       ` Shameerali Kolothum Thodi
2021-05-24 11:02 ` [PATCH v5 2/8] iommu/dma: Introduce generic helper to retrieve RMR info Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-05-24 15:35   ` kernel test robot
2021-05-24 15:35     ` kernel test robot
2021-05-24 15:35     ` kernel test robot
2021-05-24 15:35     ` kernel test robot
2021-05-24 11:02 ` [PATCH v5 3/8] ACPI/IORT: Add a helper to retrieve RMR memory regions Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-05-26  7:53   ` Laurentiu Tudor
2021-05-26  7:53     ` Laurentiu Tudor
2021-05-26  7:53     ` Laurentiu Tudor
2021-05-26 16:36     ` Shameerali Kolothum Thodi
2021-05-26 16:36       ` Shameerali Kolothum Thodi
2021-05-26 16:36       ` Shameerali Kolothum Thodi
2021-05-26 17:11       ` Laurentiu Tudor
2021-05-26 17:11         ` Laurentiu Tudor
2021-05-26 17:11         ` Laurentiu Tudor
2021-06-03 12:27         ` Jon Nettleton
2021-06-03 12:27           ` Jon Nettleton
2021-06-03 12:27           ` Jon Nettleton
2021-06-03 12:32           ` Laurentiu Tudor
2021-06-03 12:32             ` Laurentiu Tudor
2021-06-03 12:32             ` Laurentiu Tudor
2021-05-27  4:25       ` Jon Nettleton
2021-05-27  4:25         ` Jon Nettleton
2021-05-27  4:25         ` Jon Nettleton
2021-06-14 10:35       ` Robin Murphy
2021-06-14 10:35         ` Robin Murphy
2021-06-14 10:35         ` Robin Murphy
2021-06-14 11:23   ` Robin Murphy
2021-06-14 11:23     ` Robin Murphy
2021-06-14 11:23     ` Robin Murphy
2021-06-14 12:49     ` Shameerali Kolothum Thodi
2021-06-14 12:49       ` Shameerali Kolothum Thodi
2021-06-14 12:49       ` Shameerali Kolothum Thodi
2021-06-29 17:34       ` Jon Nettleton
2021-06-29 17:34         ` Jon Nettleton
2021-06-29 17:34         ` Jon Nettleton
2021-07-04  7:38         ` Jon Nettleton
2021-07-04  7:38           ` Jon Nettleton
2021-07-04  7:38           ` Jon Nettleton
2021-07-05  9:10           ` Shameerali Kolothum Thodi
2021-07-05  9:10             ` Shameerali Kolothum Thodi
2021-07-05  9:10             ` Shameerali Kolothum Thodi
2021-05-24 11:02 ` [PATCH v5 4/8] iommu/arm-smmu-v3: Introduce strtab init helper Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-05-24 11:02 ` [PATCH v5 5/8] iommu/arm-smmu-v3: Add bypass flag to arm_smmu_write_strtab_ent() Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-06-14 10:23   ` Robin Murphy [this message]
2021-06-14 10:23     ` Robin Murphy
2021-06-14 10:23     ` Robin Murphy
2021-06-14 12:51     ` Shameerali Kolothum Thodi
2021-06-14 12:51       ` Shameerali Kolothum Thodi
2021-06-14 12:51       ` Shameerali Kolothum Thodi
2021-05-24 11:02 ` [PATCH v5 6/8] iommu/arm-smmu-v3: Get associated RMR info and install Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-06-14 10:15   ` Robin Murphy
2021-06-14 10:15     ` Robin Murphy
2021-06-14 10:15     ` Robin Murphy
2021-05-24 11:02 ` [PATCH v5 7/8] iommu/arm-smmu: Get associated RMR info and install bypass SMR Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-06-03  8:52   ` Jon Nettleton
2021-06-03  8:52     ` Jon Nettleton
2021-06-03  8:52     ` Jon Nettleton
2021-06-03 11:27     ` Steven Price
2021-06-03 11:27       ` Steven Price
2021-06-03 11:27       ` Steven Price
2021-06-03 11:51       ` Jon Nettleton
2021-06-03 11:51         ` Jon Nettleton
2021-06-03 11:51         ` Jon Nettleton
2021-06-13  7:40         ` Jon Nettleton
2021-06-13  7:40           ` Jon Nettleton
2021-06-13  7:40           ` Jon Nettleton
2021-06-14  9:23           ` Robin Murphy
2021-06-14  9:23             ` Robin Murphy
2021-06-14  9:23             ` Robin Murphy
2021-06-14 10:06   ` Robin Murphy
2021-06-14 10:06     ` Robin Murphy
2021-06-14 10:06     ` Robin Murphy
2021-06-14 16:51     ` Shameerali Kolothum Thodi
2021-06-14 16:51       ` Shameerali Kolothum Thodi
2021-06-14 16:51       ` Shameerali Kolothum Thodi
2021-06-15  8:02       ` Jon Nettleton
2021-06-15  8:02         ` Jon Nettleton
2021-06-15  8:02         ` Jon Nettleton
2021-06-29  7:03     ` Jon Nettleton
2021-06-29  7:03       ` Jon Nettleton
2021-06-29  7:03       ` Jon Nettleton
2021-06-29 13:22       ` Robin Murphy
2021-06-29 13:22         ` Robin Murphy
2021-06-29 13:22         ` Robin Murphy
2021-06-29 16:25         ` Jon Nettleton
2021-06-29 16:25           ` Jon Nettleton
2021-06-29 16:25           ` Jon Nettleton
2021-06-30  8:50           ` Shameerali Kolothum Thodi
2021-06-30  8:50             ` Shameerali Kolothum Thodi
2021-06-30  8:50             ` Shameerali Kolothum Thodi
2021-05-24 11:02 ` [PATCH v5 8/8] iommu/dma: Reserve any RMR regions associated with a dev Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-05-24 11:02   ` Shameer Kolothum
2021-05-24 15:18 ` [PATCH v5 0/8] ACPI/IORT: Support for IORT RMR node Steven Price
2021-05-24 15:18   ` Steven Price
2021-05-24 15:18   ` Steven Price

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