From: "Maciej W. Rozycki" <macro@orcam.me.uk> To: Arnd Bergmann <arnd@arndb.de> Cc: "Linus Torvalds" <torvalds@linux-foundation.org>, "Matthew Wilcox" <willy@infradead.org>, "Peter Zijlstra" <peterz@infradead.org>, "the arch/x86 maintainers" <x86@kernel.org>, "Yu Zhao" <yuzhao@google.com>, "Andrew Morton" <akpm@linux-foundation.org>, "Andi Kleen" <ak@linux.intel.com>, "Aneesh Kumar" <aneesh.kumar@linux.ibm.com>, "Catalin Marinas" <catalin.marinas@arm.com>, "Dave Hansen" <dave.hansen@linux.intel.com>, "Hillf Danton" <hdanton@sina.com>, "Jens Axboe" <axboe@kernel.dk>, "Johannes Weiner" <hannes@cmpxchg.org>, "Jonathan Corbet" <corbet@lwn.net>, "Mel Gorman" <mgorman@suse.de>, "Michael Larabel" <Michael@michaellarabel.com>, "Michal Hocko" <mhocko@kernel.org>, "Mike Rapoport" <rppt@kernel.org>, "Tejun Heo" <tj@kernel.org>, "Vlastimil Babka" <vbabka@suse.cz>, "Will Deacon" <will@kernel.org>, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, page-reclaim@google.com, "Brian Geffon" <bgeffon@google.com>, "Jan Alexander Steffens" <heftig@archlinux.org>, "Oleksandr Natalenko" <oleksandr@natalenko.name>, "Steven Barrett" <steven@liquorix.net>, "Suleiman Souhlal" <suleiman@google.com>, "Daniel Byrne" <djbyrne@mtu.edu>, "Donald Carr" <d@chaos-reins.com>, "Holger Hoffstätte" <holger@applied-asynchrony.com>, "Konstantin Kharlamov" <Hi-Angel@yandex.ru>, "Shuang Zhai" <szhai2@cs.rochester.edu>, "Sofia Trinh" <sofia.trinh@edi.works>, "Vaibhav Jain" <vaibhav@linux.ibm.com> Subject: Re: [PATCH v14 08/14] mm: multi-gen LRU: support page table walks Date: Fri, 28 Oct 2022 00:08:18 +0100 (BST) [thread overview] Message-ID: <alpine.DEB.2.21.2210272332590.3199@angie.orcam.me.uk> (raw) In-Reply-To: <d24a5273-1c66-4653-9730-4de31ffcf0e8@app.fastmail.com> On Wed, 26 Oct 2022, Arnd Bergmann wrote: > >> In fact, I don't understand how current kernels work on an i486 at > >> all, since it looks like > >> > >> exit_to_user_mode_prepare -> > >> arch_exit_to_user_mode_prepare > >> > >> ends up having an unconditional 'rdtsc' instruction in it. > >> > > > The fix here is obviously and trivially: > > > > select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET if !M486SX && !M486 > > I think that would be "if X86_TSC", otherwise you still include the > TSC-less 586-class (5x86, 6x86, Elan, Winchip C6, MediaGX, ...) Right, I tend to forget about these more exotic chips from the 1990s era. I'll run some verification and come up with the actual fix in the next several days. > > So what's the actual burden from keeping this support around? Would my > > proposal to emulate CMPXCHG8B (and possibly RDTSC) in #UD handler help? > > That sounds worse to me than the current use of runtime alternatives > for picking between cmpxchg8b_emu and the native instruction. Why is that so? Because of the trap-and-emulate technique? It's been around since forever and specified in some processor ISAs even, where some machine instructions are explicitly allowed to be omitted from actual hardware and delegated to OS emulation without making affected hardware non-compliant. VAX had it back from 1970s and RISC-V has it now. We've been using it to retrofit operations ourselves, though maybe not with the x86 arch. Or is it because of the complex address decoding x86 requires? Well, I have actually realised we do have it already, in the x87 CR0.EM emulator. While IEEE-754 exceptions can make use of the address of the operand recorded in the FPU environment full emulation requires decoding by hand. > For arm32, we have a combination of two other approaches: > > - On the oldest processors that never had SMP support (ARMv5 and > earlier), it is not possible to enable support for SMP at all. > Using a Kconfig 'depends on X86_CMPXCHG64' for CONFIG_SMP would > still allow building 486 kernels, but completely avoid the problem > of trying to make the same kernel work on later SMP machines. That would be fine with me of course. > - For the special case of early ARMv6 hardware that has 32-bit > atomics but not 64-bit ones, the kernel just falls back to > CONFIG_GENERIC_ATOMIC64 and no cmpxchg64(). The same should work > for an i486+SMP kernel. It's obviously slower, but most users > can trivially avoid this by either running an i686 SMP kernel > or an i486 UP kernel. You meant an M586TSC+ SMP kernel presumably (I have such a machine), but otherwise I'd be fine with such an approach too. So it looks to me like we have at least three options to keep 486 alive, two of which seem fairly straightforward to deploy and maintain long-term. I like your last proposal the most, FWIW. Do we have a consensus here? Maciej
WARNING: multiple messages have this Message-ID (diff)
From: "Maciej W. Rozycki" <macro@orcam.me.uk> To: Arnd Bergmann <arnd@arndb.de> Cc: "Linus Torvalds" <torvalds@linux-foundation.org>, "Matthew Wilcox" <willy@infradead.org>, "Peter Zijlstra" <peterz@infradead.org>, "the arch/x86 maintainers" <x86@kernel.org>, "Yu Zhao" <yuzhao@google.com>, "Andrew Morton" <akpm@linux-foundation.org>, "Andi Kleen" <ak@linux.intel.com>, "Aneesh Kumar" <aneesh.kumar@linux.ibm.com>, "Catalin Marinas" <catalin.marinas@arm.com>, "Dave Hansen" <dave.hansen@linux.intel.com>, "Hillf Danton" <hdanton@sina.com>, "Jens Axboe" <axboe@kernel.dk>, "Johannes Weiner" <hannes@cmpxchg.org>, "Jonathan Corbet" <corbet@lwn.net>, "Mel Gorman" <mgorman@suse.de>, "Michael Larabel" <Michael@michaellarabel.com>, "Michal Hocko" <mhocko@kernel.org>, "Mike Rapoport" <rppt@kernel.org>, "Tejun Heo" <tj@kernel.org>, "Vlastimil Babka" <vbabka@suse.cz>, "Will Deacon" <will@kernel.org>, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, page-reclaim@google.com, "Brian Geffon" <bgeffon@google.com>, "Jan Alexander Steffens" <heftig@archlinux.org>, "Oleksandr Natalenko" <oleksandr@natalenko.name>, "Steven Barrett" <steven@liquorix.net>, "Suleiman Souhlal" <suleiman@google.com>, "Daniel Byrne" <djbyrne@mtu.edu>, "Donald Carr" <d@chaos-reins.com>, "Holger Hoffstätte" <holger@applied-asynchrony.com>, "Konstantin Kharlamov" <Hi-Angel@yandex.ru>, "Shuang Zhai" <szhai2@cs.rochester.edu>, "Sofia Trinh" <sofia.trinh@edi.works>, "Vaibhav Jain" <vaibhav@linux.ibm.com> Subject: Re: [PATCH v14 08/14] mm: multi-gen LRU: support page table walks Date: Fri, 28 Oct 2022 00:08:18 +0100 (BST) [thread overview] Message-ID: <alpine.DEB.2.21.2210272332590.3199@angie.orcam.me.uk> (raw) In-Reply-To: <d24a5273-1c66-4653-9730-4de31ffcf0e8@app.fastmail.com> On Wed, 26 Oct 2022, Arnd Bergmann wrote: > >> In fact, I don't understand how current kernels work on an i486 at > >> all, since it looks like > >> > >> exit_to_user_mode_prepare -> > >> arch_exit_to_user_mode_prepare > >> > >> ends up having an unconditional 'rdtsc' instruction in it. > >> > > > The fix here is obviously and trivially: > > > > select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET if !M486SX && !M486 > > I think that would be "if X86_TSC", otherwise you still include the > TSC-less 586-class (5x86, 6x86, Elan, Winchip C6, MediaGX, ...) Right, I tend to forget about these more exotic chips from the 1990s era. I'll run some verification and come up with the actual fix in the next several days. > > So what's the actual burden from keeping this support around? Would my > > proposal to emulate CMPXCHG8B (and possibly RDTSC) in #UD handler help? > > That sounds worse to me than the current use of runtime alternatives > for picking between cmpxchg8b_emu and the native instruction. Why is that so? Because of the trap-and-emulate technique? It's been around since forever and specified in some processor ISAs even, where some machine instructions are explicitly allowed to be omitted from actual hardware and delegated to OS emulation without making affected hardware non-compliant. VAX had it back from 1970s and RISC-V has it now. We've been using it to retrofit operations ourselves, though maybe not with the x86 arch. Or is it because of the complex address decoding x86 requires? Well, I have actually realised we do have it already, in the x87 CR0.EM emulator. While IEEE-754 exceptions can make use of the address of the operand recorded in the FPU environment full emulation requires decoding by hand. > For arm32, we have a combination of two other approaches: > > - On the oldest processors that never had SMP support (ARMv5 and > earlier), it is not possible to enable support for SMP at all. > Using a Kconfig 'depends on X86_CMPXCHG64' for CONFIG_SMP would > still allow building 486 kernels, but completely avoid the problem > of trying to make the same kernel work on later SMP machines. That would be fine with me of course. > - For the special case of early ARMv6 hardware that has 32-bit > atomics but not 64-bit ones, the kernel just falls back to > CONFIG_GENERIC_ATOMIC64 and no cmpxchg64(). The same should work > for an i486+SMP kernel. It's obviously slower, but most users > can trivially avoid this by either running an i686 SMP kernel > or an i486 UP kernel. You meant an M586TSC+ SMP kernel presumably (I have such a machine), but otherwise I'd be fine with such an approach too. So it looks to me like we have at least three options to keep 486 alive, two of which seem fairly straightforward to deploy and maintain long-term. I like your last proposal the most, FWIW. Do we have a consensus here? Maciej _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-10-27 23:08 UTC|newest] Thread overview: 118+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-15 7:13 [PATCH v14 00/14] Multi-Gen LRU Framework Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-08-15 7:13 ` [PATCH v14 01/14] mm: x86, arm64: add arch_has_hw_pte_young() Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-08-15 7:13 ` [PATCH v14 02/14] mm: x86: add CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-08-15 7:13 ` [PATCH v14 03/14] mm/vmscan.c: refactor shrink_node() Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-08-15 7:13 ` [PATCH v14 04/14] Revert "include/linux/mm_inline.h: fold __update_lru_size() into its sole caller" Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-08-15 7:13 ` [PATCH v14 05/14] mm: multi-gen LRU: groundwork Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-08-15 7:13 ` [PATCH v14 06/14] mm: multi-gen LRU: minimal implementation Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-08-15 7:13 ` [PATCH v14 07/14] mm: multi-gen LRU: exploit locality in rmap Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-09-01 9:18 ` Nadav Amit 2022-09-01 9:18 ` Nadav Amit 2022-09-02 1:17 ` Yu Zhao 2022-09-02 1:17 ` Yu Zhao 2022-09-02 1:28 ` Yu Zhao 2022-09-02 1:28 ` Yu Zhao 2022-08-15 7:13 ` [PATCH v14 08/14] mm: multi-gen LRU: support page table walks Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-10-13 15:04 ` Peter Zijlstra 2022-10-13 15:04 ` Peter Zijlstra 2022-10-19 5:51 ` Yu Zhao 2022-10-19 5:51 ` Yu Zhao 2022-10-19 17:40 ` Linus Torvalds 2022-10-19 17:40 ` Linus Torvalds 2022-10-20 14:13 ` Peter Zijlstra 2022-10-20 14:13 ` Peter Zijlstra 2022-10-20 17:29 ` Yu Zhao 2022-10-20 17:29 ` Yu Zhao 2022-10-20 17:35 ` Linus Torvalds 2022-10-20 17:35 ` Linus Torvalds 2022-10-20 18:55 ` Peter Zijlstra 2022-10-20 18:55 ` Peter Zijlstra 2022-10-21 2:10 ` Linus Torvalds 2022-10-21 2:10 ` Linus Torvalds 2022-10-21 3:38 ` Matthew Wilcox 2022-10-21 3:38 ` Matthew Wilcox 2022-10-21 16:50 ` Linus Torvalds 2022-10-21 16:50 ` Linus Torvalds 2022-10-23 14:44 ` David Gow 2022-10-23 14:44 ` David Gow 2022-10-23 17:55 ` Maciej W. Rozycki 2022-10-23 17:55 ` Maciej W. Rozycki 2022-10-23 18:35 ` Linus Torvalds 2022-10-23 18:35 ` Linus Torvalds 2022-10-24 7:30 ` Arnd Bergmann 2022-10-24 7:30 ` Arnd Bergmann 2022-10-25 16:28 ` Maciej W. Rozycki 2022-10-25 16:28 ` Maciej W. Rozycki 2022-10-26 15:43 ` Arnd Bergmann 2022-10-26 15:43 ` Arnd Bergmann 2022-10-27 23:08 ` Maciej W. Rozycki [this message] 2022-10-27 23:08 ` Maciej W. Rozycki 2022-10-28 7:27 ` Arnd Bergmann 2022-10-28 7:27 ` Arnd Bergmann 2022-10-21 10:12 ` Peter Zijlstra 2022-10-21 10:12 ` Peter Zijlstra 2022-10-24 18:20 ` Gareth Poole 2022-10-24 18:20 ` Gareth Poole 2022-10-24 19:28 ` Serentty 2022-10-24 19:28 ` Serentty 2022-08-15 7:13 ` [PATCH v14 09/14] mm: multi-gen LRU: optimize multiple memcgs Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-08-15 7:13 ` [PATCH v14 10/14] mm: multi-gen LRU: kill switch Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-08-15 7:13 ` [PATCH v14 11/14] mm: multi-gen LRU: thrashing prevention Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-08-15 7:13 ` [PATCH v14 12/14] mm: multi-gen LRU: debugfs interface Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-08-15 7:13 ` [PATCH v14 13/14] mm: multi-gen LRU: admin guide Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-08-15 9:06 ` Bagas Sanjaya 2022-08-15 9:06 ` Bagas Sanjaya 2022-08-15 9:12 ` Mike Rapoport 2022-08-15 9:12 ` Mike Rapoport 2022-08-17 22:46 ` Yu Zhao 2022-08-17 22:46 ` Yu Zhao 2022-09-20 7:43 ` Bagas Sanjaya 2022-09-20 7:43 ` Bagas Sanjaya 2022-08-15 7:13 ` [PATCH v14 14/14] mm: multi-gen LRU: design doc Yu Zhao 2022-08-15 7:13 ` Yu Zhao 2022-08-15 9:07 ` Bagas Sanjaya 2022-08-15 9:07 ` Bagas Sanjaya 2022-08-31 4:17 ` OpenWrt / MIPS benchmark with MGLRU Yu Zhao 2022-08-31 4:17 ` Yu Zhao 2022-08-31 9:44 ` Arnd Bergmann 2022-08-31 12:12 ` Arnd Bergmann 2022-08-31 12:12 ` Arnd Bergmann 2022-08-31 15:13 ` Dave Hansen 2022-08-31 15:13 ` Dave Hansen 2022-08-31 22:18 ` Yu Zhao 2022-08-31 22:18 ` Yu Zhao 2022-09-12 0:08 ` [PATCH v14 00/14] Multi-Gen LRU Framework Andrew Morton 2022-09-12 0:08 ` Andrew Morton 2022-09-15 17:56 ` Yu Zhao 2022-09-15 17:56 ` Yu Zhao 2022-09-18 20:40 ` Yu Zhao 2022-09-18 20:40 ` Yu Zhao 2022-09-18 20:47 ` [PATCH v14-fix 01/11] mm: multi-gen LRU: update admin guide Yu Zhao 2022-09-18 20:47 ` [PATCH v14-fix 02/11] mm: multi-gen LRU: add comment in lru_gen_use_mm() Yu Zhao 2022-09-18 20:47 ` [PATCH v14-fix 03/11] mm: multi-gen LRU: warn on !ptep_test_and_clear_young() Yu Zhao 2022-09-18 23:47 ` Andrew Morton 2022-09-18 23:53 ` Yu Zhao 2022-09-18 20:47 ` [PATCH v14-fix 04/11] mm: multi-gen LRU: fix warning from __rcu Yu Zhao 2022-09-18 20:47 ` [PATCH v14-fix 05/11] mm: multi-gen LRU: fix warning from seq_is_valid() Yu Zhao 2022-09-18 20:47 ` [PATCH v14-fix 06/11] mm: multi-gen LRU: delete overcautious VM_WARN_ON_ONCE() Yu Zhao 2022-09-18 20:47 ` [PATCH v14-fix 07/11] mm: multi-gen LRU: dial down MAX_LRU_BATCH Yu Zhao 2022-09-18 20:47 ` [PATCH v14-fix 08/11] mm: multi-gen LRU: delete newline in kswapd_age_node() Yu Zhao 2022-09-18 20:47 ` [PATCH v14-fix 09/11] mm: multi-gen LRU: add comment in lru_gen_look_around() Yu Zhao 2022-09-18 20:47 ` [PATCH v14-fix 10/11] mm: multi-gen LRU: fixed long-tailed direct reclaim latency Yu Zhao 2022-09-18 20:47 ` [PATCH v14-fix 11/11] mm: multi-gen LRU: refactor get_nr_evictable() Yu Zhao 2022-09-18 23:47 ` [PATCH v14 00/14] Multi-Gen LRU Framework Andrew Morton 2022-09-18 23:47 ` Andrew Morton
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