* [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n)
@ 2022-01-18 18:44 Fabiano Rosas
2022-01-18 18:44 ` [PATCH v2 01/14] target/ppc: 405: Rename MSR_POW to MSR_WE Fabiano Rosas
` (14 more replies)
0 siblings, 15 replies; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
changes from v1:
- New patch that renames MSR_POW to MSR_WE for the 405.
- New patch that adds just MSR_ME to the msr_mask.
- New patches to cleanup exceptions I missed the first time around.
- Dropped the patch that added all the missing MSR bits. We have an
issue when two different MSR bits share the same number in different
CPUs. Described in v1 here:
https://lists.nongnu.org/archive/html/qemu-ppc/2022-01/msg00503.html
- Dropped the patch that adds missing exception vectors because Linux
clearly cannot handle them. And I don't have access to real hardware
to confirm some of the questions raised, so let's keep things as they
are.
- Kept the split in two patches. One that copies powerpc_excp_legacy
and other that does the changes.
Based on legoater/ppc-7.0
With only the fixes from the above branch, the ref405ep machine boots
until the shell. This series doesn't change that.
v1:
https://lists.nongnu.org/archive/html/qemu-ppc/2022-01/msg00300.html
Fabiano Rosas (14):
target/ppc: 405: Rename MSR_POW to MSR_WE
target/ppc: 405: Add missing MSR_ME bit
target/ppc: Introduce powerpc_excp_40x
target/ppc: Simplify powerpc_excp_40x
target/ppc: 405: Critical exceptions cleanup
target/ppc: 405: Machine check exception cleanup
target/ppc: 405: External exception cleanup
target/ppc: 405: System call exception cleanup
target/ppc: 405: Alignment exception cleanup
target/ppc: 405: Debug exception cleanup
target/ppc: 405: Data Storage exception cleanup
target/ppc: 405: Instruction storage interrupt cleanup
target/ppc: 405: Program exception cleanup
target/ppc: 405: Watchdog timer exception cleanup
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 3 +-
target/ppc/excp_helper.c | 159 ++++++++++++++++++++++++++++++++++++++-
3 files changed, 161 insertions(+), 2 deletions(-)
--
2.33.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v2 01/14] target/ppc: 405: Rename MSR_POW to MSR_WE
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-19 11:27 ` Cédric Le Goater
2022-01-18 18:44 ` [PATCH v2 02/14] target/ppc: 405: Add missing MSR_ME bit Fabiano Rosas
` (13 subsequent siblings)
14 siblings, 1 reply; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Bit 13 is the Wait State Enable bit. Give it its proper name.
As far as I can see we don't do anything with MSR_POW for the 405, so
this change has no effect.
Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 2560b70c5f..66e13075c3 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -327,6 +327,7 @@ typedef enum {
#define MSR_S 22 /* Secure state */
#define MSR_KEY 19 /* key bit on 603e */
#define MSR_POW 18 /* Power management */
+#define MSR_WE 18 /* Wait State Enable on 405 */
#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
#define MSR_ILE 16 /* Interrupt little-endian mode */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index e30e86fe9d..e63705b1c6 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2535,7 +2535,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << MSR_POW) |
+ pcc->msr_mask = (1ull << MSR_WE) |
(1ull << MSR_CE) |
(1ull << MSR_EE) |
(1ull << MSR_PR) |
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 02/14] target/ppc: 405: Add missing MSR_ME bit
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
2022-01-18 18:44 ` [PATCH v2 01/14] target/ppc: 405: Rename MSR_POW to MSR_WE Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-19 11:26 ` Cédric Le Goater
2022-01-18 18:44 ` [PATCH v2 03/14] target/ppc: Introduce powerpc_excp_40x Fabiano Rosas
` (12 subsequent siblings)
14 siblings, 1 reply; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The 405 MSR has the Machine Check Enable bit. We're making use of it
when dispatching Machine Check, so add the bit to the msr_mask.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/cpu_init.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index e63705b1c6..23a13036b2 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2540,6 +2540,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
(1ull << MSR_EE) |
(1ull << MSR_PR) |
(1ull << MSR_FP) |
+ (1ull << MSR_ME) |
(1ull << MSR_DWE) |
(1ull << MSR_DE) |
(1ull << MSR_IR) |
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 03/14] target/ppc: Introduce powerpc_excp_40x
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
2022-01-18 18:44 ` [PATCH v2 01/14] target/ppc: 405: Rename MSR_POW to MSR_WE Fabiano Rosas
2022-01-18 18:44 ` [PATCH v2 02/14] target/ppc: 405: Add missing MSR_ME bit Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-19 11:28 ` Cédric Le Goater
2022-01-26 21:58 ` Richard Henderson
2022-01-18 18:44 ` [PATCH v2 04/14] target/ppc: Simplify powerpc_excp_40x Fabiano Rosas
` (11 subsequent siblings)
14 siblings, 2 replies; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Introduce a new powerpc_excp function specific for 40x CPUs. This
commit copies powerpc_excp_legacy verbatim so the next one has a clean
diff.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 474 +++++++++++++++++++++++++++++++++++++++
1 file changed, 474 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index bc646c67a0..12ab5e1b34 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -392,6 +392,477 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu,
check_tlb_flush(env, false);
}
+static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
+{
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+ int excp_model = env->excp_model;
+ target_ulong msr, new_msr, vector;
+ int srr0, srr1, lev = -1;
+
+ if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ }
+
+ qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
+ " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
+ excp, env->error_code);
+
+ /* new srr1 value excluding must-be-zero bits */
+ if (excp_model == POWERPC_EXCP_BOOKE) {
+ msr = env->msr;
+ } else {
+ msr = env->msr & ~0x783f0000ULL;
+ }
+
+ /*
+ * new interrupt handler msr preserves existing HV and ME unless
+ * explicitly overriden
+ */
+ new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
+
+ /* target registers */
+ srr0 = SPR_SRR0;
+ srr1 = SPR_SRR1;
+
+ /*
+ * check for special resume at 0x100 from doze/nap/sleep/winkle on
+ * P7/P8/P9
+ */
+ if (env->resume_as_sreset) {
+ excp = powerpc_reset_wakeup(cs, env, excp, &msr);
+ }
+
+ /*
+ * Hypervisor emulation assistance interrupt only exists on server
+ * arch 2.05 server or later. We also don't want to generate it if
+ * we don't have HVB in msr_mask (PAPR mode).
+ */
+ if (excp == POWERPC_EXCP_HV_EMU
+#if defined(TARGET_PPC64)
+ && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
+#endif /* defined(TARGET_PPC64) */
+
+ ) {
+ excp = POWERPC_EXCP_PROGRAM;
+ }
+
+#ifdef TARGET_PPC64
+ /*
+ * SPEU and VPU share the same IVOR but they exist in different
+ * processors. SPEU is e500v1/2 only and VPU is e6500 only.
+ */
+ if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
+ excp = POWERPC_EXCP_SPEU;
+ }
+#endif
+
+ vector = env->excp_vectors[excp];
+ if (vector == (target_ulong)-1ULL) {
+ cpu_abort(cs, "Raised an exception without defined vector %d\n",
+ excp);
+ }
+
+ vector |= env->excp_prefix;
+
+ switch (excp) {
+ case POWERPC_EXCP_CRITICAL: /* Critical input */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ case POWERPC_EXCP_G2:
+ break;
+ default:
+ goto excp_invalid;
+ }
+ break;
+ case POWERPC_EXCP_MCHECK: /* Machine check exception */
+ if (msr_me == 0) {
+ /*
+ * Machine check exception is not enabled. Enter
+ * checkstop state.
+ */
+ fprintf(stderr, "Machine check while not allowed. "
+ "Entering checkstop state\n");
+ if (qemu_log_separate()) {
+ qemu_log("Machine check while not allowed. "
+ "Entering checkstop state\n");
+ }
+ cs->halted = 1;
+ cpu_interrupt_exittb(cs);
+ }
+ if (env->msr_mask & MSR_HVB) {
+ /*
+ * ISA specifies HV, but can be delivered to guest with HV
+ * clear (e.g., see FWNMI in PAPR).
+ */
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+
+ /* machine check exceptions don't have ME set */
+ new_msr &= ~((target_ulong)1 << MSR_ME);
+
+ /* XXX: should also have something loaded in DAR / DSISR */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ /* FIXME: choose one or the other based on CPU type */
+ srr0 = SPR_BOOKE_MCSRR0;
+ srr1 = SPR_BOOKE_MCSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+ break;
+ default:
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DSI: /* Data storage exception */
+ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+ break;
+ case POWERPC_EXCP_ISI: /* Instruction storage exception */
+ trace_ppc_excp_isi(msr, env->nip);
+ msr |= env->error_code;
+ break;
+ case POWERPC_EXCP_EXTERNAL: /* External input */
+ {
+ bool lpes0;
+
+ cs = CPU(cpu);
+
+ /*
+ * Exception targeting modifiers
+ *
+ * LPES0 is supported on POWER7/8/9
+ * LPES1 is not supported (old iSeries mode)
+ *
+ * On anything else, we behave as if LPES0 is 1
+ * (externals don't alter MSR:HV)
+ */
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_POWER7 ||
+ excp_model == POWERPC_EXCP_POWER8 ||
+ excp_model == POWERPC_EXCP_POWER9 ||
+ excp_model == POWERPC_EXCP_POWER10) {
+ lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
+ } else
+#endif /* defined(TARGET_PPC64) */
+ {
+ lpes0 = true;
+ }
+
+ if (!lpes0) {
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ }
+ if (env->mpic_proxy) {
+ /* IACK the IRQ on delivery */
+ env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
+ }
+ break;
+ }
+ case POWERPC_EXCP_ALIGN: /* Alignment exception */
+ /* Get rS/rD and rA from faulting opcode */
+ /*
+ * Note: the opcode fields will not be set properly for a
+ * direct store load/store, but nobody cares as nobody
+ * actually uses direct store segments.
+ */
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
+ break;
+ case POWERPC_EXCP_PROGRAM: /* Program exception */
+ switch (env->error_code & ~0xF) {
+ case POWERPC_EXCP_FP:
+ if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+ trace_ppc_excp_fp_ignore();
+ cs->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+ return;
+ }
+
+ /*
+ * FP exceptions always have NIP pointing to the faulting
+ * instruction, so always use store_next and claim we are
+ * precise in the MSR.
+ */
+ msr |= 0x00100000;
+ env->spr[SPR_BOOKE_ESR] = ESR_FP;
+ break;
+ case POWERPC_EXCP_INVAL:
+ trace_ppc_excp_inval(env->nip);
+ msr |= 0x00080000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PIL;
+ break;
+ case POWERPC_EXCP_PRIV:
+ msr |= 0x00040000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PPR;
+ break;
+ case POWERPC_EXCP_TRAP:
+ msr |= 0x00020000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PTR;
+ break;
+ default:
+ /* Should never occur */
+ cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ env->error_code);
+ break;
+ }
+ break;
+ case POWERPC_EXCP_SYSCALL: /* System call exception */
+ lev = env->error_code;
+
+ if ((lev == 1) && cpu->vhyp) {
+ dump_hcall(env);
+ } else {
+ dump_syscall(env);
+ }
+
+ /*
+ * We need to correct the NIP which in this case is supposed
+ * to point to the next instruction
+ */
+ env->nip += 4;
+
+ /* "PAPR mode" built-in hypercall emulation */
+ if ((lev == 1) && cpu->vhyp) {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ vhc->hypercall(cpu->vhyp, cpu);
+ return;
+ }
+ if (lev == 1) {
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+ break;
+ case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
+ lev = env->error_code;
+ dump_syscall(env);
+ env->nip += 4;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+
+ vector += lev * 0x20;
+
+ env->lr = env->nip;
+ env->ctr = msr;
+ break;
+ case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
+ case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
+ case POWERPC_EXCP_DECR: /* Decrementer exception */
+ break;
+ case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
+ /* FIT on 4xx */
+ trace_ppc_excp_print("FIT");
+ break;
+ case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
+ trace_ppc_excp_print("WDT");
+ switch (excp_model) {
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ default:
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DTLB: /* Data TLB error */
+ case POWERPC_EXCP_ITLB: /* Instruction TLB error */
+ break;
+ case POWERPC_EXCP_DEBUG: /* Debug interrupt */
+ if (env->flags & POWERPC_FLAG_DE) {
+ /* FIXME: choose one or the other based on CPU type */
+ srr0 = SPR_BOOKE_DSRR0;
+ srr1 = SPR_BOOKE_DSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+
+ /* DBSR already modified by caller */
+ } else {
+ cpu_abort(cs, "Debug exception triggered on unsupported model\n");
+ }
+ break;
+ case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
+ env->spr[SPR_BOOKE_ESR] = ESR_SPV;
+ break;
+ case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
+ break;
+ case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ case POWERPC_EXCP_RESET: /* System reset exception */
+ /* A power-saving exception sets ME, otherwise it is unchanged */
+ if (msr_pow) {
+ /* indicate that we resumed from power save mode */
+ msr |= 0x10000;
+ new_msr |= ((target_ulong)1 << MSR_ME);
+ }
+ if (env->msr_mask & MSR_HVB) {
+ /*
+ * ISA specifies HV, but can be delivered to guest with HV
+ * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
+ */
+ new_msr |= (target_ulong)MSR_HVB;
+ } else {
+ if (msr_pow) {
+ cpu_abort(cs, "Trying to deliver power-saving system reset "
+ "exception %d with no HV support\n", excp);
+ }
+ }
+ break;
+ case POWERPC_EXCP_DSEG: /* Data segment exception */
+ case POWERPC_EXCP_ISEG: /* Instruction segment exception */
+ case POWERPC_EXCP_TRACE: /* Trace exception */
+ break;
+ case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
+ msr |= env->error_code;
+ /* fall through */
+ case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
+ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
+ case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
+ case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
+ case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
+ case POWERPC_EXCP_HV_EMU:
+ case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+ break;
+ case POWERPC_EXCP_VPU: /* Vector unavailable exception */
+ case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
+ case POWERPC_EXCP_FU: /* Facility unavailable exception */
+#ifdef TARGET_PPC64
+ env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
+#endif
+ break;
+ case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
+#ifdef TARGET_PPC64
+ env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+#endif
+ break;
+ case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
+ trace_ppc_excp_print("PIT");
+ break;
+ case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
+ case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
+ case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
+ switch (excp_model) {
+ case POWERPC_EXCP_602:
+ case POWERPC_EXCP_603:
+ case POWERPC_EXCP_G2:
+ /* Swap temporary saved registers with GPRs */
+ if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
+ new_msr |= (target_ulong)1 << MSR_TGPR;
+ hreg_swap_gpr_tgpr(env);
+ }
+ /* fall through */
+ case POWERPC_EXCP_7x5:
+ ppc_excp_debug_sw_tlb(env, excp);
+
+ msr |= env->crf[0] << 28;
+ msr |= env->error_code; /* key, D/I, S/L bits */
+ /* Set way using a LRU mechanism */
+ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
+ break;
+ default:
+ cpu_abort(cs, "Invalid TLB miss exception\n");
+ break;
+ }
+ break;
+ case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
+ case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
+ case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
+ case POWERPC_EXCP_IO: /* IO error exception */
+ case POWERPC_EXCP_RUNM: /* Run mode exception */
+ case POWERPC_EXCP_EMUL: /* Emulation trap exception */
+ case POWERPC_EXCP_FPA: /* Floating-point assist exception */
+ case POWERPC_EXCP_DABR: /* Data address breakpoint */
+ case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
+ case POWERPC_EXCP_SMI: /* System management interrupt */
+ case POWERPC_EXCP_THERM: /* Thermal interrupt */
+ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
+ case POWERPC_EXCP_VPUA: /* Vector assist exception */
+ case POWERPC_EXCP_SOFTP: /* Soft patch exception */
+ case POWERPC_EXCP_MAINT: /* Maintenance exception */
+ case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
+ case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
+ cpu_abort(cs, "%s exception not implemented\n",
+ powerpc_excp_name(excp));
+ break;
+ default:
+ excp_invalid:
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ break;
+ }
+
+ /* Sanity check */
+ if (!(env->msr_mask & MSR_HVB)) {
+ if (new_msr & MSR_HVB) {
+ cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
+ "no HV support\n", excp);
+ }
+ if (srr0 == SPR_HSRR0) {
+ cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
+ "no HV support\n", excp);
+ }
+ }
+
+ /*
+ * Sort out endianness of interrupt, this differs depending on the
+ * CPU, the HV mode, etc...
+ */
+ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
+ new_msr |= (target_ulong)1 << MSR_LE;
+ }
+
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_BOOKE) {
+ if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
+ /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
+ new_msr |= (target_ulong)1 << MSR_CM;
+ } else {
+ vector = (uint32_t)vector;
+ }
+ } else {
+ if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
+ vector = (uint32_t)vector;
+ } else {
+ new_msr |= (target_ulong)1 << MSR_SF;
+ }
+ }
+#endif
+
+ if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
+ /* Save PC */
+ env->spr[srr0] = env->nip;
+
+ /* Save MSR */
+ env->spr[srr1] = msr;
+ }
+
+ /* This can update new_msr and vector if AIL applies */
+ ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+
+ powerpc_set_excp_state(cpu, vector, new_msr);
+}
+
/*
* Note that this function should be greatly optimized when called
* with a constant excp, from ppc_hw_interrupt
@@ -872,6 +1343,9 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
CPUPPCState *env = &cpu->env;
switch (env->excp_model) {
+ case POWERPC_EXCP_40x:
+ powerpc_excp_40x(cpu, excp);
+ break;
default:
powerpc_excp_legacy(cpu, excp);
}
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 04/14] target/ppc: Simplify powerpc_excp_40x
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
` (2 preceding siblings ...)
2022-01-18 18:44 ` [PATCH v2 03/14] target/ppc: Introduce powerpc_excp_40x Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-19 6:04 ` David Gibson
2022-01-18 18:44 ` [PATCH v2 05/14] target/ppc: 405: Critical exceptions cleanup Fabiano Rosas
` (10 subsequent siblings)
14 siblings, 1 reply; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV or MSR_LE;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Interrupts Little Endian;
- No Alternate Interrupt Location.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_CRITICAL
POWERPC_EXCP_DEBUG
POWERPC_EXCP_DSI
POWERPC_EXCP_DTLB
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FIT
POWERPC_EXCP_ISI
POWERPC_EXCP_ITLB
POWERPC_EXCP_MCHECK
POWERPC_EXCP_PIT
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_WDT
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 205 ++-------------------------------------
1 file changed, 10 insertions(+), 195 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 12ab5e1b34..b5975dff3e 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -409,54 +409,26 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
excp, env->error_code);
/* new srr1 value excluding must-be-zero bits */
- if (excp_model == POWERPC_EXCP_BOOKE) {
- msr = env->msr;
- } else {
- msr = env->msr & ~0x783f0000ULL;
- }
+ msr = env->msr & ~0x783f0000ULL;
/*
- * new interrupt handler msr preserves existing HV and ME unless
- * explicitly overriden
+ * new interrupt handler msr preserves existing ME unless
+ * explicitly overriden.
*/
- new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
+ new_msr = env->msr & (((target_ulong)1 << MSR_ME));
/* target registers */
srr0 = SPR_SRR0;
srr1 = SPR_SRR1;
- /*
- * check for special resume at 0x100 from doze/nap/sleep/winkle on
- * P7/P8/P9
- */
- if (env->resume_as_sreset) {
- excp = powerpc_reset_wakeup(cs, env, excp, &msr);
- }
-
/*
* Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later. We also don't want to generate it if
- * we don't have HVB in msr_mask (PAPR mode).
+ * arch 2.05 server or later.
*/
- if (excp == POWERPC_EXCP_HV_EMU
-#if defined(TARGET_PPC64)
- && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
-#endif /* defined(TARGET_PPC64) */
-
- ) {
+ if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
-#ifdef TARGET_PPC64
- /*
- * SPEU and VPU share the same IVOR but they exist in different
- * processors. SPEU is e500v1/2 only and VPU is e6500 only.
- */
- if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
- excp = POWERPC_EXCP_SPEU;
- }
-#endif
-
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
cpu_abort(cs, "Raised an exception without defined vector %d\n",
@@ -645,24 +617,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)MSR_HVB;
}
break;
- case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
- lev = env->error_code;
- dump_syscall(env);
- env->nip += 4;
- new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-
- vector += lev * 0x20;
-
- env->lr = env->nip;
- env->ctr = msr;
- break;
- case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
- case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
- case POWERPC_EXCP_DECR: /* Decrementer exception */
- break;
case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
- /* FIT on 4xx */
trace_ppc_excp_print("FIT");
break;
case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
@@ -693,119 +648,9 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
cpu_abort(cs, "Debug exception triggered on unsupported model\n");
}
break;
- case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
- env->spr[SPR_BOOKE_ESR] = ESR_SPV;
- break;
- case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
- break;
- case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- case POWERPC_EXCP_RESET: /* System reset exception */
- /* A power-saving exception sets ME, otherwise it is unchanged */
- if (msr_pow) {
- /* indicate that we resumed from power save mode */
- msr |= 0x10000;
- new_msr |= ((target_ulong)1 << MSR_ME);
- }
- if (env->msr_mask & MSR_HVB) {
- /*
- * ISA specifies HV, but can be delivered to guest with HV
- * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
- */
- new_msr |= (target_ulong)MSR_HVB;
- } else {
- if (msr_pow) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
- "exception %d with no HV support\n", excp);
- }
- }
- break;
- case POWERPC_EXCP_DSEG: /* Data segment exception */
- case POWERPC_EXCP_ISEG: /* Instruction segment exception */
- case POWERPC_EXCP_TRACE: /* Trace exception */
- break;
- case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
- msr |= env->error_code;
- /* fall through */
- case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
- case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
- case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
- case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
- case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
- case POWERPC_EXCP_HV_EMU:
- case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- break;
- case POWERPC_EXCP_VPU: /* Vector unavailable exception */
- case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
- case POWERPC_EXCP_FU: /* Facility unavailable exception */
-#ifdef TARGET_PPC64
- env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
-#endif
- break;
- case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
-#ifdef TARGET_PPC64
- env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-#endif
- break;
case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
trace_ppc_excp_print("PIT");
break;
- case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
- case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
- case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
- switch (excp_model) {
- case POWERPC_EXCP_602:
- case POWERPC_EXCP_603:
- case POWERPC_EXCP_G2:
- /* Swap temporary saved registers with GPRs */
- if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
- new_msr |= (target_ulong)1 << MSR_TGPR;
- hreg_swap_gpr_tgpr(env);
- }
- /* fall through */
- case POWERPC_EXCP_7x5:
- ppc_excp_debug_sw_tlb(env, excp);
-
- msr |= env->crf[0] << 28;
- msr |= env->error_code; /* key, D/I, S/L bits */
- /* Set way using a LRU mechanism */
- msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
- break;
- default:
- cpu_abort(cs, "Invalid TLB miss exception\n");
- break;
- }
- break;
- case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
- case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
- case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
- case POWERPC_EXCP_IO: /* IO error exception */
- case POWERPC_EXCP_RUNM: /* Run mode exception */
- case POWERPC_EXCP_EMUL: /* Emulation trap exception */
- case POWERPC_EXCP_FPA: /* Floating-point assist exception */
- case POWERPC_EXCP_DABR: /* Data address breakpoint */
- case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
- case POWERPC_EXCP_SMI: /* System management interrupt */
- case POWERPC_EXCP_THERM: /* Thermal interrupt */
- case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
- case POWERPC_EXCP_VPUA: /* Vector assist exception */
- case POWERPC_EXCP_SOFTP: /* Soft patch exception */
- case POWERPC_EXCP_MAINT: /* Maintenance exception */
- case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
- case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
- cpu_abort(cs, "%s exception not implemented\n",
- powerpc_excp_name(excp));
- break;
default:
excp_invalid:
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -824,41 +669,11 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
}
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
- if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
- new_msr |= (target_ulong)1 << MSR_LE;
- }
+ /* Save PC */
+ env->spr[srr0] = env->nip;
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_BOOKE) {
- if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
- /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
- new_msr |= (target_ulong)1 << MSR_CM;
- } else {
- vector = (uint32_t)vector;
- }
- } else {
- if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
- vector = (uint32_t)vector;
- } else {
- new_msr |= (target_ulong)1 << MSR_SF;
- }
- }
-#endif
-
- if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
- /* Save PC */
- env->spr[srr0] = env->nip;
-
- /* Save MSR */
- env->spr[srr1] = msr;
- }
-
- /* This can update new_msr and vector if AIL applies */
- ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+ /* Save MSR */
+ env->spr[srr1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
}
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 05/14] target/ppc: 405: Critical exceptions cleanup
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
` (3 preceding siblings ...)
2022-01-18 18:44 ` [PATCH v2 04/14] target/ppc: Simplify powerpc_excp_40x Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-26 21:58 ` Richard Henderson
2022-01-18 18:44 ` [PATCH v2 06/14] target/ppc: 405: Machine check exception cleanup Fabiano Rosas
` (9 subsequent siblings)
14 siblings, 1 reply; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
In powerpc_excp_40x the Critical exception is now for 405 only, so we
can remove the BookE and G2 blocks.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/excp_helper.c | 17 ++---------------
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index b5975dff3e..bddea702be 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -439,20 +439,8 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
switch (excp) {
case POWERPC_EXCP_CRITICAL: /* Critical input */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- case POWERPC_EXCP_G2:
- break;
- default:
- goto excp_invalid;
- }
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
if (msr_me == 0) {
@@ -652,7 +640,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
trace_ppc_excp_print("PIT");
break;
default:
- excp_invalid:
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
break;
}
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 06/14] target/ppc: 405: Machine check exception cleanup
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
` (4 preceding siblings ...)
2022-01-18 18:44 ` [PATCH v2 05/14] target/ppc: 405: Critical exceptions cleanup Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-19 6:06 ` David Gibson
2022-01-18 18:44 ` [PATCH v2 07/14] target/ppc: 405: External " Fabiano Rosas
` (8 subsequent siblings)
14 siblings, 1 reply; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
powerpc_excp_40x applies only to the 405, so remove HV code and
references to BookE.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/excp_helper.c | 26 ++------------------------
1 file changed, 2 insertions(+), 24 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index bddea702be..e98d783ecd 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -457,34 +457,12 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
cs->halted = 1;
cpu_interrupt_exittb(cs);
}
- if (env->msr_mask & MSR_HVB) {
- /*
- * ISA specifies HV, but can be delivered to guest with HV
- * clear (e.g., see FWNMI in PAPR).
- */
- new_msr |= (target_ulong)MSR_HVB;
- }
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
- /* XXX: should also have something loaded in DAR / DSISR */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_MCSRR0;
- srr1 = SPR_BOOKE_MCSRR1;
-
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
- break;
- default:
- break;
- }
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 07/14] target/ppc: 405: External exception cleanup
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
` (5 preceding siblings ...)
2022-01-18 18:44 ` [PATCH v2 06/14] target/ppc: 405: Machine check exception cleanup Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-26 22:02 ` Richard Henderson
2022-01-18 18:44 ` [PATCH v2 08/14] target/ppc: 405: System call " Fabiano Rosas
` (7 subsequent siblings)
14 siblings, 1 reply; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
405 has no MSR_HV and EPR is BookE only so we can remove it all.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/excp_helper.c | 37 -------------------------------------
1 file changed, 37 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index e98d783ecd..8fae8aa0be 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -472,44 +472,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
msr |= env->error_code;
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
- {
- bool lpes0;
-
- cs = CPU(cpu);
-
- /*
- * Exception targeting modifiers
- *
- * LPES0 is supported on POWER7/8/9
- * LPES1 is not supported (old iSeries mode)
- *
- * On anything else, we behave as if LPES0 is 1
- * (externals don't alter MSR:HV)
- */
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_POWER7 ||
- excp_model == POWERPC_EXCP_POWER8 ||
- excp_model == POWERPC_EXCP_POWER9 ||
- excp_model == POWERPC_EXCP_POWER10) {
- lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- } else
-#endif /* defined(TARGET_PPC64) */
- {
- lpes0 = true;
- }
-
- if (!lpes0) {
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- }
- if (env->mpic_proxy) {
- /* IACK the IRQ on delivery */
- env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
- }
break;
- }
case POWERPC_EXCP_ALIGN: /* Alignment exception */
/* Get rS/rD and rA from faulting opcode */
/*
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 08/14] target/ppc: 405: System call exception cleanup
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
` (6 preceding siblings ...)
2022-01-18 18:44 ` [PATCH v2 07/14] target/ppc: 405: External " Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-19 6:09 ` David Gibson
2022-01-26 22:02 ` Richard Henderson
2022-01-18 18:44 ` [PATCH v2 09/14] target/ppc: 405: Alignment " Fabiano Rosas
` (6 subsequent siblings)
14 siblings, 2 replies; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There's no sc 1.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 21 ++-------------------
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 8fae8aa0be..9a6f8365d6 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -398,7 +398,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
CPUPPCState *env = &cpu->env;
int excp_model = env->excp_model;
target_ulong msr, new_msr, vector;
- int srr0, srr1, lev = -1;
+ int srr0, srr1;
if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -521,30 +521,13 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
}
break;
case POWERPC_EXCP_SYSCALL: /* System call exception */
- lev = env->error_code;
-
- if ((lev == 1) && cpu->vhyp) {
- dump_hcall(env);
- } else {
- dump_syscall(env);
- }
+ dump_syscall(env);
/*
* We need to correct the NIP which in this case is supposed
* to point to the next instruction
*/
env->nip += 4;
-
- /* "PAPR mode" built-in hypercall emulation */
- if ((lev == 1) && cpu->vhyp) {
- PPCVirtualHypervisorClass *vhc =
- PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
- vhc->hypercall(cpu->vhyp, cpu);
- return;
- }
- if (lev == 1) {
- new_msr |= (target_ulong)MSR_HVB;
- }
break;
case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
trace_ppc_excp_print("FIT");
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 09/14] target/ppc: 405: Alignment exception cleanup
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
` (7 preceding siblings ...)
2022-01-18 18:44 ` [PATCH v2 08/14] target/ppc: 405: System call " Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-19 6:11 ` David Gibson
2022-01-18 18:44 ` [PATCH v2 10/14] target/ppc: 405: Debug " Fabiano Rosas
` (5 subsequent siblings)
14 siblings, 1 reply; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There is no DSISR in the 405. It uses DEAR which we already set
earlier at ppc_cpu_do_unaligned_access.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 9a6f8365d6..d263f20002 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -474,13 +474,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_EXTERNAL: /* External input */
break;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
- /* Get rS/rD and rA from faulting opcode */
- /*
- * Note: the opcode fields will not be set properly for a
- * direct store load/store, but nobody cares as nobody
- * actually uses direct store segments.
- */
- env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 10/14] target/ppc: 405: Debug exception cleanup
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
` (8 preceding siblings ...)
2022-01-18 18:44 ` [PATCH v2 09/14] target/ppc: 405: Alignment " Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-19 6:12 ` David Gibson
2022-01-18 18:44 ` [PATCH v2 11/14] target/ppc: 405: Data Storage " Fabiano Rosas
` (4 subsequent siblings)
14 siblings, 1 reply; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The current Debug exception dispatch is the BookE one, so it is
different from the 405. We effectively don't support the 405 Debug
exception.
This patch removes the BookE code and moves the DEBUG into the "not
implemented" block.
Note that there is in theory a functional change here since we now
abort when a Debug exception happens. However, given how it was never
implemented, I don't believe this to have ever been dispatched for the
405.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 18 ++++--------------
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index d263f20002..84ec7e094a 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -539,23 +539,13 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_DTLB: /* Data TLB error */
case POWERPC_EXCP_ITLB: /* Instruction TLB error */
break;
- case POWERPC_EXCP_DEBUG: /* Debug interrupt */
- if (env->flags & POWERPC_FLAG_DE) {
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_DSRR0;
- srr1 = SPR_BOOKE_DSRR1;
-
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
-
- /* DBSR already modified by caller */
- } else {
- cpu_abort(cs, "Debug exception triggered on unsupported model\n");
- }
- break;
case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
trace_ppc_excp_print("PIT");
break;
+ case POWERPC_EXCP_DEBUG: /* Debug interrupt */
+ cpu_abort(cs, "%s exception not implemented\n",
+ powerpc_excp_name(excp));
+ break;
default:
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
break;
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 11/14] target/ppc: 405: Data Storage exception cleanup
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
` (9 preceding siblings ...)
2022-01-18 18:44 ` [PATCH v2 10/14] target/ppc: 405: Debug " Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-19 6:13 ` David Gibson
2022-01-18 18:44 ` [PATCH v2 12/14] target/ppc: 405: Instruction storage interrupt cleanup Fabiano Rosas
` (3 subsequent siblings)
14 siblings, 1 reply; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The 405 has no DSISR or DAR, so convert the trace entry to
trace_ppc_excp_print.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 84ec7e094a..e4e513322c 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -465,7 +465,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
srr1 = SPR_40x_SRR3;
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
- trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+ trace_ppc_excp_print("DSI");
break;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
trace_ppc_excp_isi(msr, env->nip);
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 12/14] target/ppc: 405: Instruction storage interrupt cleanup
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
` (10 preceding siblings ...)
2022-01-18 18:44 ` [PATCH v2 11/14] target/ppc: 405: Data Storage " Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-20 22:17 ` Cédric Le Goater
2022-01-25 7:24 ` Cédric Le Goater
2022-01-18 18:44 ` [PATCH v2 13/14] target/ppc: 405: Program exception cleanup Fabiano Rosas
` (2 subsequent siblings)
14 siblings, 2 replies; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The 405 ISI does not set SRR1 with any exception syndrome bits, only a
clean copy of the MSR.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index e4e513322c..13674a102f 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -715,7 +715,6 @@ static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
trace_ppc_excp_isi(msr, env->nip);
- msr |= env->error_code;
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
{
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 13/14] target/ppc: 405: Program exception cleanup
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
` (11 preceding siblings ...)
2022-01-18 18:44 ` [PATCH v2 12/14] target/ppc: 405: Instruction storage interrupt cleanup Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-19 6:15 ` David Gibson
2022-01-25 7:25 ` Cédric Le Goater
2022-01-18 18:44 ` [PATCH v2 14/14] target/ppc: 405: Watchdog timer " Fabiano Rosas
2022-01-20 9:33 ` [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Cédric Le Goater
14 siblings, 2 replies; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The 405 Program Interrupt does not set SRR1 with any diagnostic bits,
just a clean copy of the MSR.
We're using the BookE Exception Syndrome Register which is different
from the 405.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 13674a102f..2efec6d13b 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -484,30 +484,14 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
env->error_code = 0;
return;
}
-
- /*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
- */
- msr |= 0x00100000;
- env->spr[SPR_BOOKE_ESR] = ESR_FP;
break;
case POWERPC_EXCP_INVAL:
trace_ppc_excp_inval(env->nip);
- msr |= 0x00080000;
- env->spr[SPR_BOOKE_ESR] = ESR_PIL;
break;
case POWERPC_EXCP_PRIV:
- msr |= 0x00040000;
- env->spr[SPR_BOOKE_ESR] = ESR_PPR;
- break;
case POWERPC_EXCP_TRAP:
- msr |= 0x00020000;
- env->spr[SPR_BOOKE_ESR] = ESR_PTR;
break;
default:
- /* Should never occur */
cpu_abort(cs, "Invalid program exception %d. Aborting\n",
env->error_code);
break;
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 14/14] target/ppc: 405: Watchdog timer exception cleanup
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
` (12 preceding siblings ...)
2022-01-18 18:44 ` [PATCH v2 13/14] target/ppc: 405: Program exception cleanup Fabiano Rosas
@ 2022-01-18 18:44 ` Fabiano Rosas
2022-01-25 7:26 ` Cédric Le Goater
2022-01-20 9:33 ` [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Cédric Le Goater
14 siblings, 1 reply; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-18 18:44 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Remove references to BookE.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 2efec6d13b..a22b783ecb 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -396,7 +396,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- int excp_model = env->excp_model;
target_ulong msr, new_msr, vector;
int srr0, srr1;
@@ -511,14 +510,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
trace_ppc_excp_print("WDT");
- switch (excp_model) {
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- default:
- break;
- }
break;
case POWERPC_EXCP_DTLB: /* Data TLB error */
case POWERPC_EXCP_ITLB: /* Instruction TLB error */
--
2.33.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [PATCH v2 04/14] target/ppc: Simplify powerpc_excp_40x
2022-01-18 18:44 ` [PATCH v2 04/14] target/ppc: Simplify powerpc_excp_40x Fabiano Rosas
@ 2022-01-19 6:04 ` David Gibson
0 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2022-01-19 6:04 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, clg
[-- Attachment #1: Type: text/plain, Size: 12486 bytes --]
On Tue, Jan 18, 2022 at 03:44:38PM -0300, Fabiano Rosas wrote:
> Differences from the generic powerpc_excp code:
>
> - Not BookE, so some MSR bits are cleared at interrupt dispatch;
> - No MSR_HV or MSR_LE;
> - No power saving states;
> - No Hypervisor Emulation Assistance;
> - Not 64 bits;
> - No System call vectored;
> - No Interrupts Little Endian;
> - No Alternate Interrupt Location.
>
> Exceptions used:
>
> POWERPC_EXCP_ALIGN
> POWERPC_EXCP_CRITICAL
> POWERPC_EXCP_DEBUG
> POWERPC_EXCP_DSI
> POWERPC_EXCP_DTLB
> POWERPC_EXCP_EXTERNAL
> POWERPC_EXCP_FIT
> POWERPC_EXCP_ISI
> POWERPC_EXCP_ITLB
> POWERPC_EXCP_MCHECK
> POWERPC_EXCP_PIT
> POWERPC_EXCP_PROGRAM
> POWERPC_EXCP_SYSCALL
> POWERPC_EXCP_WDT
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/excp_helper.c | 205 ++-------------------------------------
> 1 file changed, 10 insertions(+), 195 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 12ab5e1b34..b5975dff3e 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -409,54 +409,26 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> excp, env->error_code);
>
> /* new srr1 value excluding must-be-zero bits */
> - if (excp_model == POWERPC_EXCP_BOOKE) {
> - msr = env->msr;
> - } else {
> - msr = env->msr & ~0x783f0000ULL;
> - }
> + msr = env->msr & ~0x783f0000ULL;
>
> /*
> - * new interrupt handler msr preserves existing HV and ME unless
> - * explicitly overriden
> + * new interrupt handler msr preserves existing ME unless
> + * explicitly overriden.
> */
> - new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
> + new_msr = env->msr & (((target_ulong)1 << MSR_ME));
>
> /* target registers */
> srr0 = SPR_SRR0;
> srr1 = SPR_SRR1;
>
> - /*
> - * check for special resume at 0x100 from doze/nap/sleep/winkle on
> - * P7/P8/P9
> - */
> - if (env->resume_as_sreset) {
> - excp = powerpc_reset_wakeup(cs, env, excp, &msr);
> - }
> -
> /*
> * Hypervisor emulation assistance interrupt only exists on server
> - * arch 2.05 server or later. We also don't want to generate it if
> - * we don't have HVB in msr_mask (PAPR mode).
> + * arch 2.05 server or later.
> */
> - if (excp == POWERPC_EXCP_HV_EMU
> -#if defined(TARGET_PPC64)
> - && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
> -#endif /* defined(TARGET_PPC64) */
> -
> - ) {
> + if (excp == POWERPC_EXCP_HV_EMU) {
> excp = POWERPC_EXCP_PROGRAM;
> }
>
> -#ifdef TARGET_PPC64
> - /*
> - * SPEU and VPU share the same IVOR but they exist in different
> - * processors. SPEU is e500v1/2 only and VPU is e6500 only.
> - */
> - if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
> - excp = POWERPC_EXCP_SPEU;
> - }
> -#endif
> -
> vector = env->excp_vectors[excp];
> if (vector == (target_ulong)-1ULL) {
> cpu_abort(cs, "Raised an exception without defined vector %d\n",
> @@ -645,24 +617,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> new_msr |= (target_ulong)MSR_HVB;
> }
> break;
> - case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
> - lev = env->error_code;
> - dump_syscall(env);
> - env->nip += 4;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> -
> - vector += lev * 0x20;
> -
> - env->lr = env->nip;
> - env->ctr = msr;
> - break;
> - case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
> - case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
> - case POWERPC_EXCP_DECR: /* Decrementer exception */
> - break;
> case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
> - /* FIT on 4xx */
> trace_ppc_excp_print("FIT");
> break;
> case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
> @@ -693,119 +648,9 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> cpu_abort(cs, "Debug exception triggered on unsupported model\n");
> }
> break;
> - case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
> - env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> - break;
> - case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
> - break;
> - case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - case POWERPC_EXCP_RESET: /* System reset exception */
> - /* A power-saving exception sets ME, otherwise it is unchanged */
> - if (msr_pow) {
> - /* indicate that we resumed from power save mode */
> - msr |= 0x10000;
> - new_msr |= ((target_ulong)1 << MSR_ME);
> - }
> - if (env->msr_mask & MSR_HVB) {
> - /*
> - * ISA specifies HV, but can be delivered to guest with HV
> - * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
> - */
> - new_msr |= (target_ulong)MSR_HVB;
> - } else {
> - if (msr_pow) {
> - cpu_abort(cs, "Trying to deliver power-saving system reset "
> - "exception %d with no HV support\n", excp);
> - }
> - }
> - break;
> - case POWERPC_EXCP_DSEG: /* Data segment exception */
> - case POWERPC_EXCP_ISEG: /* Instruction segment exception */
> - case POWERPC_EXCP_TRACE: /* Trace exception */
> - break;
> - case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
> - msr |= env->error_code;
> - /* fall through */
> - case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
> - case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
> - case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
> - case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
> - case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
> - case POWERPC_EXCP_HV_EMU:
> - case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
> - srr0 = SPR_HSRR0;
> - srr1 = SPR_HSRR1;
> - new_msr |= (target_ulong)MSR_HVB;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> - break;
> - case POWERPC_EXCP_VPU: /* Vector unavailable exception */
> - case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
> - case POWERPC_EXCP_FU: /* Facility unavailable exception */
> -#ifdef TARGET_PPC64
> - env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
> -#endif
> - break;
> - case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
> -#ifdef TARGET_PPC64
> - env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
> - srr0 = SPR_HSRR0;
> - srr1 = SPR_HSRR1;
> - new_msr |= (target_ulong)MSR_HVB;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> -#endif
> - break;
> case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
> trace_ppc_excp_print("PIT");
> break;
> - case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
> - case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
> - case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
> - switch (excp_model) {
> - case POWERPC_EXCP_602:
> - case POWERPC_EXCP_603:
> - case POWERPC_EXCP_G2:
> - /* Swap temporary saved registers with GPRs */
> - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
> - new_msr |= (target_ulong)1 << MSR_TGPR;
> - hreg_swap_gpr_tgpr(env);
> - }
> - /* fall through */
> - case POWERPC_EXCP_7x5:
> - ppc_excp_debug_sw_tlb(env, excp);
> -
> - msr |= env->crf[0] << 28;
> - msr |= env->error_code; /* key, D/I, S/L bits */
> - /* Set way using a LRU mechanism */
> - msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
> - break;
> - default:
> - cpu_abort(cs, "Invalid TLB miss exception\n");
> - break;
> - }
> - break;
> - case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
> - case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
> - case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
> - case POWERPC_EXCP_IO: /* IO error exception */
> - case POWERPC_EXCP_RUNM: /* Run mode exception */
> - case POWERPC_EXCP_EMUL: /* Emulation trap exception */
> - case POWERPC_EXCP_FPA: /* Floating-point assist exception */
> - case POWERPC_EXCP_DABR: /* Data address breakpoint */
> - case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
> - case POWERPC_EXCP_SMI: /* System management interrupt */
> - case POWERPC_EXCP_THERM: /* Thermal interrupt */
> - case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
> - case POWERPC_EXCP_VPUA: /* Vector assist exception */
> - case POWERPC_EXCP_SOFTP: /* Soft patch exception */
> - case POWERPC_EXCP_MAINT: /* Maintenance exception */
> - case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
> - case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
> - cpu_abort(cs, "%s exception not implemented\n",
> - powerpc_excp_name(excp));
> - break;
> default:
> excp_invalid:
> cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> @@ -824,41 +669,11 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> }
> }
>
> - /*
> - * Sort out endianness of interrupt, this differs depending on the
> - * CPU, the HV mode, etc...
> - */
> - if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
> - new_msr |= (target_ulong)1 << MSR_LE;
> - }
> + /* Save PC */
> + env->spr[srr0] = env->nip;
>
> -#if defined(TARGET_PPC64)
> - if (excp_model == POWERPC_EXCP_BOOKE) {
> - if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
> - /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
> - new_msr |= (target_ulong)1 << MSR_CM;
> - } else {
> - vector = (uint32_t)vector;
> - }
> - } else {
> - if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
> - vector = (uint32_t)vector;
> - } else {
> - new_msr |= (target_ulong)1 << MSR_SF;
> - }
> - }
> -#endif
> -
> - if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
> - /* Save PC */
> - env->spr[srr0] = env->nip;
> -
> - /* Save MSR */
> - env->spr[srr1] = msr;
> - }
> -
> - /* This can update new_msr and vector if AIL applies */
> - ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
> + /* Save MSR */
> + env->spr[srr1] = msr;
>
> powerpc_set_excp_state(cpu, vector, new_msr);
> }
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 06/14] target/ppc: 405: Machine check exception cleanup
2022-01-18 18:44 ` [PATCH v2 06/14] target/ppc: 405: Machine check exception cleanup Fabiano Rosas
@ 2022-01-19 6:06 ` David Gibson
2022-01-19 11:21 ` Cédric Le Goater
0 siblings, 1 reply; 44+ messages in thread
From: David Gibson @ 2022-01-19 6:06 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, clg
[-- Attachment #1: Type: text/plain, Size: 2319 bytes --]
On Tue, Jan 18, 2022 at 03:44:40PM -0300, Fabiano Rosas wrote:
> powerpc_excp_40x applies only to the 405, so remove HV code and
> references to BookE.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/excp_helper.c | 26 ++------------------------
> 1 file changed, 2 insertions(+), 24 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index bddea702be..e98d783ecd 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -457,34 +457,12 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> cs->halted = 1;
> cpu_interrupt_exittb(cs);
> }
> - if (env->msr_mask & MSR_HVB) {
> - /*
> - * ISA specifies HV, but can be delivered to guest with HV
> - * clear (e.g., see FWNMI in PAPR).
> - */
> - new_msr |= (target_ulong)MSR_HVB;
> - }
>
> /* machine check exceptions don't have ME set */
> new_msr &= ~((target_ulong)1 << MSR_ME);
>
> - /* XXX: should also have something loaded in DAR / DSISR */
DAR and DSISR don't apply for 40x, but I wonder if we should be
loading something into DEAR or ESR for machine checks.
> - switch (excp_model) {
> - case POWERPC_EXCP_40x:
> - srr0 = SPR_40x_SRR2;
> - srr1 = SPR_40x_SRR3;
> - break;
> - case POWERPC_EXCP_BOOKE:
> - /* FIXME: choose one or the other based on CPU type */
> - srr0 = SPR_BOOKE_MCSRR0;
> - srr1 = SPR_BOOKE_MCSRR1;
> -
> - env->spr[SPR_BOOKE_CSRR0] = env->nip;
> - env->spr[SPR_BOOKE_CSRR1] = msr;
> - break;
> - default:
> - break;
> - }
> + srr0 = SPR_40x_SRR2;
> + srr1 = SPR_40x_SRR3;
> break;
> case POWERPC_EXCP_DSI: /* Data storage exception */
> trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 08/14] target/ppc: 405: System call exception cleanup
2022-01-18 18:44 ` [PATCH v2 08/14] target/ppc: 405: System call " Fabiano Rosas
@ 2022-01-19 6:09 ` David Gibson
2022-01-25 8:18 ` Cédric Le Goater
2022-01-26 22:02 ` Richard Henderson
1 sibling, 1 reply; 44+ messages in thread
From: David Gibson @ 2022-01-19 6:09 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, clg
[-- Attachment #1: Type: text/plain, Size: 2472 bytes --]
On Tue, Jan 18, 2022 at 03:44:42PM -0300, Fabiano Rosas wrote:
> There's no sc 1.
No... but what exactly should and will happen if you attempt to
execute an "sc 1" on 40x. Will it be treated as an "sc 0", or will it
cause a 0x700? If it's a 0x700, better double check that that is
generated at translation time, if you're removing the check on level
here.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> target/ppc/excp_helper.c | 21 ++-------------------
> 1 file changed, 2 insertions(+), 19 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 8fae8aa0be..9a6f8365d6 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -398,7 +398,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> CPUPPCState *env = &cpu->env;
> int excp_model = env->excp_model;
> target_ulong msr, new_msr, vector;
> - int srr0, srr1, lev = -1;
> + int srr0, srr1;
>
> if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
> cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> @@ -521,30 +521,13 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> }
> break;
> case POWERPC_EXCP_SYSCALL: /* System call exception */
> - lev = env->error_code;
> -
> - if ((lev == 1) && cpu->vhyp) {
> - dump_hcall(env);
> - } else {
> - dump_syscall(env);
> - }
> + dump_syscall(env);
>
> /*
> * We need to correct the NIP which in this case is supposed
> * to point to the next instruction
> */
> env->nip += 4;
> -
> - /* "PAPR mode" built-in hypercall emulation */
> - if ((lev == 1) && cpu->vhyp) {
> - PPCVirtualHypervisorClass *vhc =
> - PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> - vhc->hypercall(cpu->vhyp, cpu);
> - return;
> - }
> - if (lev == 1) {
> - new_msr |= (target_ulong)MSR_HVB;
> - }
> break;
> case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
> trace_ppc_excp_print("FIT");
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 09/14] target/ppc: 405: Alignment exception cleanup
2022-01-18 18:44 ` [PATCH v2 09/14] target/ppc: 405: Alignment " Fabiano Rosas
@ 2022-01-19 6:11 ` David Gibson
0 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2022-01-19 6:11 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, clg
[-- Attachment #1: Type: text/plain, Size: 1660 bytes --]
On Tue, Jan 18, 2022 at 03:44:43PM -0300, Fabiano Rosas wrote:
> There is no DSISR in the 405. It uses DEAR which we already set
> earlier at ppc_cpu_do_unaligned_access.
Enabled specifically, I note, by env->mmu_model rather than
env->excp_model, which doesn't make a lot of sense. Another cleanup
for later.
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au
> ---
> target/ppc/excp_helper.c | 7 -------
> 1 file changed, 7 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 9a6f8365d6..d263f20002 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -474,13 +474,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> case POWERPC_EXCP_EXTERNAL: /* External input */
> break;
> case POWERPC_EXCP_ALIGN: /* Alignment exception */
> - /* Get rS/rD and rA from faulting opcode */
> - /*
> - * Note: the opcode fields will not be set properly for a
> - * direct store load/store, but nobody cares as nobody
> - * actually uses direct store segments.
> - */
> - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
> break;
> case POWERPC_EXCP_PROGRAM: /* Program exception */
> switch (env->error_code & ~0xF) {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 10/14] target/ppc: 405: Debug exception cleanup
2022-01-18 18:44 ` [PATCH v2 10/14] target/ppc: 405: Debug " Fabiano Rosas
@ 2022-01-19 6:12 ` David Gibson
0 siblings, 0 replies; 44+ messages in thread
From: David Gibson @ 2022-01-19 6:12 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, clg
[-- Attachment #1: Type: text/plain, Size: 2474 bytes --]
On Tue, Jan 18, 2022 at 03:44:44PM -0300, Fabiano Rosas wrote:
> The current Debug exception dispatch is the BookE one, so it is
> different from the 405. We effectively don't support the 405 Debug
> exception.
>
> This patch removes the BookE code and moves the DEBUG into the "not
> implemented" block.
>
> Note that there is in theory a functional change here since we now
> abort when a Debug exception happens. However, given how it was never
> implemented, I don't believe this to have ever been dispatched for the
> 405.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/excp_helper.c | 18 ++++--------------
> 1 file changed, 4 insertions(+), 14 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index d263f20002..84ec7e094a 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -539,23 +539,13 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> case POWERPC_EXCP_DTLB: /* Data TLB error */
> case POWERPC_EXCP_ITLB: /* Instruction TLB error */
> break;
> - case POWERPC_EXCP_DEBUG: /* Debug interrupt */
> - if (env->flags & POWERPC_FLAG_DE) {
> - /* FIXME: choose one or the other based on CPU type */
> - srr0 = SPR_BOOKE_DSRR0;
> - srr1 = SPR_BOOKE_DSRR1;
> -
> - env->spr[SPR_BOOKE_CSRR0] = env->nip;
> - env->spr[SPR_BOOKE_CSRR1] = msr;
> -
> - /* DBSR already modified by caller */
> - } else {
> - cpu_abort(cs, "Debug exception triggered on unsupported model\n");
> - }
> - break;
> case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
> trace_ppc_excp_print("PIT");
> break;
> + case POWERPC_EXCP_DEBUG: /* Debug interrupt */
> + cpu_abort(cs, "%s exception not implemented\n",
> + powerpc_excp_name(excp));
> + break;
> default:
> cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> break;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 11/14] target/ppc: 405: Data Storage exception cleanup
2022-01-18 18:44 ` [PATCH v2 11/14] target/ppc: 405: Data Storage " Fabiano Rosas
@ 2022-01-19 6:13 ` David Gibson
2022-01-19 11:25 ` Cédric Le Goater
2022-01-25 7:23 ` Cédric Le Goater
0 siblings, 2 replies; 44+ messages in thread
From: David Gibson @ 2022-01-19 6:13 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, clg
[-- Attachment #1: Type: text/plain, Size: 1378 bytes --]
On Tue, Jan 18, 2022 at 03:44:45PM -0300, Fabiano Rosas wrote:
> The 405 has no DSISR or DAR, so convert the trace entry to
> trace_ppc_excp_print.
I think it would be preferable to show ESR and DEAR here, which are
very loosely equivalent to DSISR and DAR on 40x. Might want to create
a new trace point explicitly for this so the terminology is clear as well.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> target/ppc/excp_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 84ec7e094a..e4e513322c 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -465,7 +465,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> srr1 = SPR_40x_SRR3;
> break;
> case POWERPC_EXCP_DSI: /* Data storage exception */
> - trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
> + trace_ppc_excp_print("DSI");
> break;
> case POWERPC_EXCP_ISI: /* Instruction storage exception */
> trace_ppc_excp_isi(msr, env->nip);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 13/14] target/ppc: 405: Program exception cleanup
2022-01-18 18:44 ` [PATCH v2 13/14] target/ppc: 405: Program exception cleanup Fabiano Rosas
@ 2022-01-19 6:15 ` David Gibson
2022-01-19 12:54 ` Fabiano Rosas
2022-01-25 7:25 ` Cédric Le Goater
1 sibling, 1 reply; 44+ messages in thread
From: David Gibson @ 2022-01-19 6:15 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, clg
[-- Attachment #1: Type: text/plain, Size: 2053 bytes --]
On Tue, Jan 18, 2022 at 03:44:47PM -0300, Fabiano Rosas wrote:
> The 405 Program Interrupt does not set SRR1 with any diagnostic bits,
> just a clean copy of the MSR.
>
> We're using the BookE Exception Syndrome Register which is different
> from the 405.
Hrm. We really do want to set the 40x ESR bits here, though.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> target/ppc/excp_helper.c | 16 ----------------
> 1 file changed, 16 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 13674a102f..2efec6d13b 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -484,30 +484,14 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> env->error_code = 0;
> return;
> }
> -
> - /*
> - * FP exceptions always have NIP pointing to the faulting
> - * instruction, so always use store_next and claim we are
> - * precise in the MSR.
> - */
> - msr |= 0x00100000;
> - env->spr[SPR_BOOKE_ESR] = ESR_FP;
> break;
> case POWERPC_EXCP_INVAL:
> trace_ppc_excp_inval(env->nip);
> - msr |= 0x00080000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PIL;
> break;
> case POWERPC_EXCP_PRIV:
> - msr |= 0x00040000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PPR;
> - break;
> case POWERPC_EXCP_TRAP:
> - msr |= 0x00020000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PTR;
> break;
> default:
> - /* Should never occur */
> cpu_abort(cs, "Invalid program exception %d. Aborting\n",
> env->error_code);
> break;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 06/14] target/ppc: 405: Machine check exception cleanup
2022-01-19 6:06 ` David Gibson
@ 2022-01-19 11:21 ` Cédric Le Goater
0 siblings, 0 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-19 11:21 UTC (permalink / raw)
To: David Gibson, Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel
On 1/19/22 07:06, David Gibson wrote:
> On Tue, Jan 18, 2022 at 03:44:40PM -0300, Fabiano Rosas wrote:
>> powerpc_excp_40x applies only to the 405, so remove HV code and
>> references to BookE.
>>
>> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
>> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
>> ---
>> target/ppc/excp_helper.c | 26 ++------------------------
>> 1 file changed, 2 insertions(+), 24 deletions(-)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index bddea702be..e98d783ecd 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -457,34 +457,12 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
>> cs->halted = 1;
>> cpu_interrupt_exittb(cs);
>> }
>> - if (env->msr_mask & MSR_HVB) {
>> - /*
>> - * ISA specifies HV, but can be delivered to guest with HV
>> - * clear (e.g., see FWNMI in PAPR).
>> - */
>> - new_msr |= (target_ulong)MSR_HVB;
>> - }
>>
>> /* machine check exceptions don't have ME set */
>> new_msr &= ~((target_ulong)1 << MSR_ME);
>>
>> - /* XXX: should also have something loaded in DAR / DSISR */
>
> DAR and DSISR don't apply for 40x, but I wonder if we should be
> loading something into DEAR or ESR for machine checks.
the user manuals only refers to SRR2 and SRR3.
Thanks,
C.
>
>> - switch (excp_model) {
>> - case POWERPC_EXCP_40x:
>> - srr0 = SPR_40x_SRR2;
>> - srr1 = SPR_40x_SRR3;
>> - break;
>> - case POWERPC_EXCP_BOOKE:
>> - /* FIXME: choose one or the other based on CPU type */
>> - srr0 = SPR_BOOKE_MCSRR0;
>> - srr1 = SPR_BOOKE_MCSRR1;
>> -
>> - env->spr[SPR_BOOKE_CSRR0] = env->nip;
>> - env->spr[SPR_BOOKE_CSRR1] = msr;
>> - break;
>> - default:
>> - break;
>> - }
>> + srr0 = SPR_40x_SRR2;
>> + srr1 = SPR_40x_SRR3;
>> break;
>> case POWERPC_EXCP_DSI: /* Data storage exception */
>> trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 11/14] target/ppc: 405: Data Storage exception cleanup
2022-01-19 6:13 ` David Gibson
@ 2022-01-19 11:25 ` Cédric Le Goater
2022-01-25 7:23 ` Cédric Le Goater
1 sibling, 0 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-19 11:25 UTC (permalink / raw)
To: David Gibson, Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel
On 1/19/22 07:13, David Gibson wrote:
> On Tue, Jan 18, 2022 at 03:44:45PM -0300, Fabiano Rosas wrote:
>> The 405 has no DSISR or DAR, so convert the trace entry to
>> trace_ppc_excp_print.
>
> I think it would be preferable to show ESR and DEAR here, which are
> very loosely equivalent to DSISR and DAR on 40x.
yes.
> Might want to create
> a new trace point explicitly for this so the terminology is clear as well.
trace_ppc_excp_print() s of my invention and not the best. I agree
we should add extra traces.
Thanks,
C.
>>
>> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
>> ---
>> target/ppc/excp_helper.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index 84ec7e094a..e4e513322c 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -465,7 +465,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
>> srr1 = SPR_40x_SRR3;
>> break;
>> case POWERPC_EXCP_DSI: /* Data storage exception */
>> - trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
>> + trace_ppc_excp_print("DSI");
>> break;
>> case POWERPC_EXCP_ISI: /* Instruction storage exception */
>> trace_ppc_excp_isi(msr, env->nip);
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 02/14] target/ppc: 405: Add missing MSR_ME bit
2022-01-18 18:44 ` [PATCH v2 02/14] target/ppc: 405: Add missing MSR_ME bit Fabiano Rosas
@ 2022-01-19 11:26 ` Cédric Le Goater
0 siblings, 0 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-19 11:26 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/18/22 19:44, Fabiano Rosas wrote:
> The 405 MSR has the Machine Check Enable bit. We're making use of it
> when dispatching Machine Check, so add the bit to the msr_mask.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/cpu_init.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index e63705b1c6..23a13036b2 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -2540,6 +2540,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
> (1ull << MSR_EE) |
> (1ull << MSR_PR) |
> (1ull << MSR_FP) |
> + (1ull << MSR_ME) |
> (1ull << MSR_DWE) |
> (1ull << MSR_DE) |
> (1ull << MSR_IR) |
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 01/14] target/ppc: 405: Rename MSR_POW to MSR_WE
2022-01-18 18:44 ` [PATCH v2 01/14] target/ppc: 405: Rename MSR_POW to MSR_WE Fabiano Rosas
@ 2022-01-19 11:27 ` Cédric Le Goater
0 siblings, 0 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-19 11:27 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/18/22 19:44, Fabiano Rosas wrote:
> Bit 13 is the Wait State Enable bit. Give it its proper name.
>
> As far as I can see we don't do anything with MSR_POW for the 405, so
> this change has no effect.
>
> Suggested-by: David Gibson <david@gibson.dropbear.id.au>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/cpu.h | 1 +
> target/ppc/cpu_init.c | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 2560b70c5f..66e13075c3 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -327,6 +327,7 @@ typedef enum {
> #define MSR_S 22 /* Secure state */
> #define MSR_KEY 19 /* key bit on 603e */
> #define MSR_POW 18 /* Power management */
> +#define MSR_WE 18 /* Wait State Enable on 405 */
> #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
> #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
> #define MSR_ILE 16 /* Interrupt little-endian mode */
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index e30e86fe9d..e63705b1c6 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -2535,7 +2535,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
> PPC_MEM_SYNC | PPC_MEM_EIEIO |
> PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
> PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
> - pcc->msr_mask = (1ull << MSR_POW) |
> + pcc->msr_mask = (1ull << MSR_WE) |
> (1ull << MSR_CE) |
> (1ull << MSR_EE) |
> (1ull << MSR_PR) |
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 03/14] target/ppc: Introduce powerpc_excp_40x
2022-01-18 18:44 ` [PATCH v2 03/14] target/ppc: Introduce powerpc_excp_40x Fabiano Rosas
@ 2022-01-19 11:28 ` Cédric Le Goater
2022-01-26 21:58 ` Richard Henderson
1 sibling, 0 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-19 11:28 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/18/22 19:44, Fabiano Rosas wrote:
> Introduce a new powerpc_excp function specific for 40x CPUs. This
> commit copies powerpc_excp_legacy verbatim so the next one has a clean
> diff.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/excp_helper.c | 474 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 474 insertions(+)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index bc646c67a0..12ab5e1b34 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -392,6 +392,477 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu,
> check_tlb_flush(env, false);
> }
>
> +static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> +{
> + CPUState *cs = CPU(cpu);
> + CPUPPCState *env = &cpu->env;
> + int excp_model = env->excp_model;
> + target_ulong msr, new_msr, vector;
> + int srr0, srr1, lev = -1;
> +
> + if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
> + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> + }
> +
> + qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
> + " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
> + excp, env->error_code);
> +
> + /* new srr1 value excluding must-be-zero bits */
> + if (excp_model == POWERPC_EXCP_BOOKE) {
> + msr = env->msr;
> + } else {
> + msr = env->msr & ~0x783f0000ULL;
> + }
> +
> + /*
> + * new interrupt handler msr preserves existing HV and ME unless
> + * explicitly overriden
> + */
> + new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
> +
> + /* target registers */
> + srr0 = SPR_SRR0;
> + srr1 = SPR_SRR1;
> +
> + /*
> + * check for special resume at 0x100 from doze/nap/sleep/winkle on
> + * P7/P8/P9
> + */
> + if (env->resume_as_sreset) {
> + excp = powerpc_reset_wakeup(cs, env, excp, &msr);
> + }
> +
> + /*
> + * Hypervisor emulation assistance interrupt only exists on server
> + * arch 2.05 server or later. We also don't want to generate it if
> + * we don't have HVB in msr_mask (PAPR mode).
> + */
> + if (excp == POWERPC_EXCP_HV_EMU
> +#if defined(TARGET_PPC64)
> + && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
> +#endif /* defined(TARGET_PPC64) */
> +
> + ) {
> + excp = POWERPC_EXCP_PROGRAM;
> + }
> +
> +#ifdef TARGET_PPC64
> + /*
> + * SPEU and VPU share the same IVOR but they exist in different
> + * processors. SPEU is e500v1/2 only and VPU is e6500 only.
> + */
> + if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
> + excp = POWERPC_EXCP_SPEU;
> + }
> +#endif
> +
> + vector = env->excp_vectors[excp];
> + if (vector == (target_ulong)-1ULL) {
> + cpu_abort(cs, "Raised an exception without defined vector %d\n",
> + excp);
> + }
> +
> + vector |= env->excp_prefix;
> +
> + switch (excp) {
> + case POWERPC_EXCP_CRITICAL: /* Critical input */
> + switch (excp_model) {
> + case POWERPC_EXCP_40x:
> + srr0 = SPR_40x_SRR2;
> + srr1 = SPR_40x_SRR3;
> + break;
> + case POWERPC_EXCP_BOOKE:
> + srr0 = SPR_BOOKE_CSRR0;
> + srr1 = SPR_BOOKE_CSRR1;
> + break;
> + case POWERPC_EXCP_G2:
> + break;
> + default:
> + goto excp_invalid;
> + }
> + break;
> + case POWERPC_EXCP_MCHECK: /* Machine check exception */
> + if (msr_me == 0) {
> + /*
> + * Machine check exception is not enabled. Enter
> + * checkstop state.
> + */
> + fprintf(stderr, "Machine check while not allowed. "
> + "Entering checkstop state\n");
> + if (qemu_log_separate()) {
> + qemu_log("Machine check while not allowed. "
> + "Entering checkstop state\n");
> + }
> + cs->halted = 1;
> + cpu_interrupt_exittb(cs);
> + }
> + if (env->msr_mask & MSR_HVB) {
> + /*
> + * ISA specifies HV, but can be delivered to guest with HV
> + * clear (e.g., see FWNMI in PAPR).
> + */
> + new_msr |= (target_ulong)MSR_HVB;
> + }
> +
> + /* machine check exceptions don't have ME set */
> + new_msr &= ~((target_ulong)1 << MSR_ME);
> +
> + /* XXX: should also have something loaded in DAR / DSISR */
> + switch (excp_model) {
> + case POWERPC_EXCP_40x:
> + srr0 = SPR_40x_SRR2;
> + srr1 = SPR_40x_SRR3;
> + break;
> + case POWERPC_EXCP_BOOKE:
> + /* FIXME: choose one or the other based on CPU type */
> + srr0 = SPR_BOOKE_MCSRR0;
> + srr1 = SPR_BOOKE_MCSRR1;
> +
> + env->spr[SPR_BOOKE_CSRR0] = env->nip;
> + env->spr[SPR_BOOKE_CSRR1] = msr;
> + break;
> + default:
> + break;
> + }
> + break;
> + case POWERPC_EXCP_DSI: /* Data storage exception */
> + trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
> + break;
> + case POWERPC_EXCP_ISI: /* Instruction storage exception */
> + trace_ppc_excp_isi(msr, env->nip);
> + msr |= env->error_code;
> + break;
> + case POWERPC_EXCP_EXTERNAL: /* External input */
> + {
> + bool lpes0;
> +
> + cs = CPU(cpu);
> +
> + /*
> + * Exception targeting modifiers
> + *
> + * LPES0 is supported on POWER7/8/9
> + * LPES1 is not supported (old iSeries mode)
> + *
> + * On anything else, we behave as if LPES0 is 1
> + * (externals don't alter MSR:HV)
> + */
> +#if defined(TARGET_PPC64)
> + if (excp_model == POWERPC_EXCP_POWER7 ||
> + excp_model == POWERPC_EXCP_POWER8 ||
> + excp_model == POWERPC_EXCP_POWER9 ||
> + excp_model == POWERPC_EXCP_POWER10) {
> + lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
> + } else
> +#endif /* defined(TARGET_PPC64) */
> + {
> + lpes0 = true;
> + }
> +
> + if (!lpes0) {
> + new_msr |= (target_ulong)MSR_HVB;
> + new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> + srr0 = SPR_HSRR0;
> + srr1 = SPR_HSRR1;
> + }
> + if (env->mpic_proxy) {
> + /* IACK the IRQ on delivery */
> + env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
> + }
> + break;
> + }
> + case POWERPC_EXCP_ALIGN: /* Alignment exception */
> + /* Get rS/rD and rA from faulting opcode */
> + /*
> + * Note: the opcode fields will not be set properly for a
> + * direct store load/store, but nobody cares as nobody
> + * actually uses direct store segments.
> + */
> + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
> + break;
> + case POWERPC_EXCP_PROGRAM: /* Program exception */
> + switch (env->error_code & ~0xF) {
> + case POWERPC_EXCP_FP:
> + if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
> + trace_ppc_excp_fp_ignore();
> + cs->exception_index = POWERPC_EXCP_NONE;
> + env->error_code = 0;
> + return;
> + }
> +
> + /*
> + * FP exceptions always have NIP pointing to the faulting
> + * instruction, so always use store_next and claim we are
> + * precise in the MSR.
> + */
> + msr |= 0x00100000;
> + env->spr[SPR_BOOKE_ESR] = ESR_FP;
> + break;
> + case POWERPC_EXCP_INVAL:
> + trace_ppc_excp_inval(env->nip);
> + msr |= 0x00080000;
> + env->spr[SPR_BOOKE_ESR] = ESR_PIL;
> + break;
> + case POWERPC_EXCP_PRIV:
> + msr |= 0x00040000;
> + env->spr[SPR_BOOKE_ESR] = ESR_PPR;
> + break;
> + case POWERPC_EXCP_TRAP:
> + msr |= 0x00020000;
> + env->spr[SPR_BOOKE_ESR] = ESR_PTR;
> + break;
> + default:
> + /* Should never occur */
> + cpu_abort(cs, "Invalid program exception %d. Aborting\n",
> + env->error_code);
> + break;
> + }
> + break;
> + case POWERPC_EXCP_SYSCALL: /* System call exception */
> + lev = env->error_code;
> +
> + if ((lev == 1) && cpu->vhyp) {
> + dump_hcall(env);
> + } else {
> + dump_syscall(env);
> + }
> +
> + /*
> + * We need to correct the NIP which in this case is supposed
> + * to point to the next instruction
> + */
> + env->nip += 4;
> +
> + /* "PAPR mode" built-in hypercall emulation */
> + if ((lev == 1) && cpu->vhyp) {
> + PPCVirtualHypervisorClass *vhc =
> + PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> + vhc->hypercall(cpu->vhyp, cpu);
> + return;
> + }
> + if (lev == 1) {
> + new_msr |= (target_ulong)MSR_HVB;
> + }
> + break;
> + case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
> + lev = env->error_code;
> + dump_syscall(env);
> + env->nip += 4;
> + new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
> + new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> +
> + vector += lev * 0x20;
> +
> + env->lr = env->nip;
> + env->ctr = msr;
> + break;
> + case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
> + case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
> + case POWERPC_EXCP_DECR: /* Decrementer exception */
> + break;
> + case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
> + /* FIT on 4xx */
> + trace_ppc_excp_print("FIT");
> + break;
> + case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
> + trace_ppc_excp_print("WDT");
> + switch (excp_model) {
> + case POWERPC_EXCP_BOOKE:
> + srr0 = SPR_BOOKE_CSRR0;
> + srr1 = SPR_BOOKE_CSRR1;
> + break;
> + default:
> + break;
> + }
> + break;
> + case POWERPC_EXCP_DTLB: /* Data TLB error */
> + case POWERPC_EXCP_ITLB: /* Instruction TLB error */
> + break;
> + case POWERPC_EXCP_DEBUG: /* Debug interrupt */
> + if (env->flags & POWERPC_FLAG_DE) {
> + /* FIXME: choose one or the other based on CPU type */
> + srr0 = SPR_BOOKE_DSRR0;
> + srr1 = SPR_BOOKE_DSRR1;
> +
> + env->spr[SPR_BOOKE_CSRR0] = env->nip;
> + env->spr[SPR_BOOKE_CSRR1] = msr;
> +
> + /* DBSR already modified by caller */
> + } else {
> + cpu_abort(cs, "Debug exception triggered on unsupported model\n");
> + }
> + break;
> + case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
> + env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> + break;
> + case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
> + break;
> + case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
> + srr0 = SPR_BOOKE_CSRR0;
> + srr1 = SPR_BOOKE_CSRR1;
> + break;
> + case POWERPC_EXCP_RESET: /* System reset exception */
> + /* A power-saving exception sets ME, otherwise it is unchanged */
> + if (msr_pow) {
> + /* indicate that we resumed from power save mode */
> + msr |= 0x10000;
> + new_msr |= ((target_ulong)1 << MSR_ME);
> + }
> + if (env->msr_mask & MSR_HVB) {
> + /*
> + * ISA specifies HV, but can be delivered to guest with HV
> + * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
> + */
> + new_msr |= (target_ulong)MSR_HVB;
> + } else {
> + if (msr_pow) {
> + cpu_abort(cs, "Trying to deliver power-saving system reset "
> + "exception %d with no HV support\n", excp);
> + }
> + }
> + break;
> + case POWERPC_EXCP_DSEG: /* Data segment exception */
> + case POWERPC_EXCP_ISEG: /* Instruction segment exception */
> + case POWERPC_EXCP_TRACE: /* Trace exception */
> + break;
> + case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
> + msr |= env->error_code;
> + /* fall through */
> + case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
> + case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
> + case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
> + case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
> + case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
> + case POWERPC_EXCP_HV_EMU:
> + case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
> + srr0 = SPR_HSRR0;
> + srr1 = SPR_HSRR1;
> + new_msr |= (target_ulong)MSR_HVB;
> + new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> + break;
> + case POWERPC_EXCP_VPU: /* Vector unavailable exception */
> + case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
> + case POWERPC_EXCP_FU: /* Facility unavailable exception */
> +#ifdef TARGET_PPC64
> + env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
> +#endif
> + break;
> + case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
> +#ifdef TARGET_PPC64
> + env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
> + srr0 = SPR_HSRR0;
> + srr1 = SPR_HSRR1;
> + new_msr |= (target_ulong)MSR_HVB;
> + new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> +#endif
> + break;
> + case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
> + trace_ppc_excp_print("PIT");
> + break;
> + case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
> + case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
> + case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
> + switch (excp_model) {
> + case POWERPC_EXCP_602:
> + case POWERPC_EXCP_603:
> + case POWERPC_EXCP_G2:
> + /* Swap temporary saved registers with GPRs */
> + if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
> + new_msr |= (target_ulong)1 << MSR_TGPR;
> + hreg_swap_gpr_tgpr(env);
> + }
> + /* fall through */
> + case POWERPC_EXCP_7x5:
> + ppc_excp_debug_sw_tlb(env, excp);
> +
> + msr |= env->crf[0] << 28;
> + msr |= env->error_code; /* key, D/I, S/L bits */
> + /* Set way using a LRU mechanism */
> + msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
> + break;
> + default:
> + cpu_abort(cs, "Invalid TLB miss exception\n");
> + break;
> + }
> + break;
> + case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
> + case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
> + case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
> + case POWERPC_EXCP_IO: /* IO error exception */
> + case POWERPC_EXCP_RUNM: /* Run mode exception */
> + case POWERPC_EXCP_EMUL: /* Emulation trap exception */
> + case POWERPC_EXCP_FPA: /* Floating-point assist exception */
> + case POWERPC_EXCP_DABR: /* Data address breakpoint */
> + case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
> + case POWERPC_EXCP_SMI: /* System management interrupt */
> + case POWERPC_EXCP_THERM: /* Thermal interrupt */
> + case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
> + case POWERPC_EXCP_VPUA: /* Vector assist exception */
> + case POWERPC_EXCP_SOFTP: /* Soft patch exception */
> + case POWERPC_EXCP_MAINT: /* Maintenance exception */
> + case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
> + case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
> + cpu_abort(cs, "%s exception not implemented\n",
> + powerpc_excp_name(excp));
> + break;
> + default:
> + excp_invalid:
> + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> + break;
> + }
> +
> + /* Sanity check */
> + if (!(env->msr_mask & MSR_HVB)) {
> + if (new_msr & MSR_HVB) {
> + cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
> + "no HV support\n", excp);
> + }
> + if (srr0 == SPR_HSRR0) {
> + cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
> + "no HV support\n", excp);
> + }
> + }
> +
> + /*
> + * Sort out endianness of interrupt, this differs depending on the
> + * CPU, the HV mode, etc...
> + */
> + if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
> + new_msr |= (target_ulong)1 << MSR_LE;
> + }
> +
> +#if defined(TARGET_PPC64)
> + if (excp_model == POWERPC_EXCP_BOOKE) {
> + if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
> + /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
> + new_msr |= (target_ulong)1 << MSR_CM;
> + } else {
> + vector = (uint32_t)vector;
> + }
> + } else {
> + if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
> + vector = (uint32_t)vector;
> + } else {
> + new_msr |= (target_ulong)1 << MSR_SF;
> + }
> + }
> +#endif
> +
> + if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
> + /* Save PC */
> + env->spr[srr0] = env->nip;
> +
> + /* Save MSR */
> + env->spr[srr1] = msr;
> + }
> +
> + /* This can update new_msr and vector if AIL applies */
> + ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
> +
> + powerpc_set_excp_state(cpu, vector, new_msr);
> +}
> +
> /*
> * Note that this function should be greatly optimized when called
> * with a constant excp, from ppc_hw_interrupt
> @@ -872,6 +1343,9 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
> CPUPPCState *env = &cpu->env;
>
> switch (env->excp_model) {
> + case POWERPC_EXCP_40x:
> + powerpc_excp_40x(cpu, excp);
> + break;
> default:
> powerpc_excp_legacy(cpu, excp);
> }
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 13/14] target/ppc: 405: Program exception cleanup
2022-01-19 6:15 ` David Gibson
@ 2022-01-19 12:54 ` Fabiano Rosas
2022-01-20 16:23 ` Cédric Le Goater
0 siblings, 1 reply; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-19 12:54 UTC (permalink / raw)
To: David Gibson; +Cc: clg, danielhb413, qemu-ppc, qemu-devel
David Gibson <david@gibson.dropbear.id.au> writes:
> On Tue, Jan 18, 2022 at 03:44:47PM -0300, Fabiano Rosas wrote:
>> The 405 Program Interrupt does not set SRR1 with any diagnostic bits,
>> just a clean copy of the MSR.
>>
>> We're using the BookE Exception Syndrome Register which is different
>> from the 405.
>
> Hrm. We really do want to set the 40x ESR bits here, though.
Well I wrote the code and nothing changed so I dropped it. Not sure if
we are even raising these properly in the translation code. I'll take
another look.
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n)
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
` (13 preceding siblings ...)
2022-01-18 18:44 ` [PATCH v2 14/14] target/ppc: 405: Watchdog timer " Fabiano Rosas
@ 2022-01-20 9:33 ` Cédric Le Goater
14 siblings, 0 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-20 9:33 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, Christophe Leroy, david
On 1/18/22 19:44, Fabiano Rosas wrote:
> changes from v1:
>
> - New patch that renames MSR_POW to MSR_WE for the 405.
>
> - New patch that adds just MSR_ME to the msr_mask.
>
> - New patches to cleanup exceptions I missed the first time around.
>
> - Dropped the patch that added all the missing MSR bits. We have an
> issue when two different MSR bits share the same number in different
> CPUs. Described in v1 here:
>
> https://lists.nongnu.org/archive/html/qemu-ppc/2022-01/msg00503.html
>
> - Dropped the patch that adds missing exception vectors because Linux
> clearly cannot handle them. And I don't have access to real hardware
> to confirm some of the questions raised, so let's keep things as they
> are.
>
> - Kept the split in two patches. One that copies powerpc_excp_legacy
> and other that does the changes.
>
> Based on legoater/ppc-7.0
>
> With only the fixes from the above branch, the ref405ep machine boots
> until the shell. This series doesn't change that.
FYI, with a couple of extra patches, adding a hotfoot variant
machine and its PCI controller, network comes up with a rtl8139
and a virtio-net-pci devices. I2C seems fine. The only open issue
is the timer which is twice too fast.
I will merge this series, unless Fabiano wants to send a v3, and
the patch fixing the TLBs. The patches for the hotfoot variant can
come later.
Thanks,
C.
qemu-system-ppc -M ref405ep-hotfoot -serial null -kernel /path/to/linux.git/build_ppc40x/arch/powerpc/boot/cuImage.hotfoot.elf -initrd /home/legoater/work/buildroot/images//qemu_ppc_ref405ep-latest//rootfs.cpio -net nic,model=virtio-net-pci,netdev=net0,addr=3 -netdev bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0 -device ds1338,address=0x68 -serial mon:stdio -nographic
Memory <- <0x0 0x8000000> (128MB)
CPU clock-frequency <- 0x7f28155 (133MHz)
CPU timebase-frequency <- 0x7f28155 (133MHz)
/plb: clock-frequency <- 1fca055 (33MHz)
/plb/opb: clock-frequency <- 1fca055 (33MHz)
/plb/ebc: clock-frequency <- 1fca055 (33MHz)
/plb/opb/serial@ef600300: clock-frequency <- 1d1079 (2MHz)
/plb/opb/serial@ef600400: clock-frequency <- 1d1079 (2MHz)
ethernet0: local-mac-address <- 00:00:00:00:00:00
ethernet1: local-mac-address <- 00:00:07:f2:81:55
Fixing devtree for 4M Flash
zImage starting: loaded at 0x00700000 (sp: 0xfff7ff98)
Decompression error: 'Not a gzip file'
No valid compressed data found, assume uncompressed data
Allocating 0x613ee0 bytes for kernel...
0x5f391c bytes of uncompressed data copied
Using loader supplied ramdisk at 0x1800000-0x1c6d800
initrd head: 0x30373037
Linux/PowerPC load:
Finalizing device tree... flat tree at 0xd1a960
Linux version 5.16.0-11200-g1d1df41c5a33-dirty (legoater@yukon) (powerpc64-linux-gnu-gcc (GCC) 11.2.1 20210728 (Red Hat Cross 11.2.1-1), GNU ld version 2.35.2-1.fc34) #127 Thu Jan 20 10:19:47 CET 2022
Found initrd at 0xc1800000:0xc1c6d800
Using PowerPC 40x Platform machine description
printk: bootconsole [udbg0] enabled
-----------------------------------------------------
phys_mem_size = 0x8000000
dcache_bsize = 0x20
icache_bsize = 0x20
cpu_features = 0x0000000000000100
possible = 0x0000000000000100
always = 0x0000000000000100
cpu_user_features = 0x86000000 0x00000000
mmu_features = 0x00000004
-----------------------------------------------------
Zone ranges:
Normal [mem 0x0000000000000000-0x0000000007ffffff]
Movable zone start for each node
Early memory node ranges
node 0: [mem 0x0000000000000000-0x0000000007ffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
MMU: Allocated 1088 bytes of context maps for 255 contexts
Built 1 zonelists, mobility grouping on. Total pages: 32512
Kernel command line:
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear)
mem auto-init: stack:off, heap alloc:off, heap free:off
Kernel virtual memory layout:
* 0xffbdf000..0xfffff000 : fixmap
* 0xc9000000..0xffbdf000 : vmalloc & ioremap
Memory: 119108K/131072K available (4372K kernel code, 248K rwdata, 1308K rodata, 168K init, 127K bss, 11964K reserved, 0K cma-reserved)
SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
NR_IRQS: 512, nr_irqs: 512, preallocated irqs: 16
UIC0 (32 IRQ sources) at DCR 0xc0
clocksource: timebase: mask: 0xffffffffffffffff max_cycles: 0x1ec031343f, max_idle_ns: 440795203544 ns
clocksource: timebase mult[7800000] shift[24] registered
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
devtmpfs: initialized
random: get_random_u32 called from bucket_table_alloc.isra.0+0x74/0x170 with crng_init=0
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 256 (order: -1, 3072 bytes, linear)
NET: Registered PF_NETLINK/PF_ROUTE protocol family
DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
thermal_sys: Registered thermal governor 'step_wise'
PCI host bridge /plb/pci@ec000000 (primary) ranges:
MEM 0x0000000080000000..0x000000009fffffff -> 0x0000000080000000
IO 0x00000000e8000000..0x00000000e800ffff -> 0x0000000000000000
4xx PCI DMA offset set to 0x00000000
4xx PCI DMA window base to 0x0000000000000000
DMA window size 0x0000000080000000
PCI: Probing PCI hardware
PCI host bridge to bus 0008:00
pci_bus 0008:00: root bus resource [io 0x0000-0xffff]
pci_bus 0008:00: root bus resource [mem 0x80000000-0x9fffffff]
pci_bus 0008:00: root bus resource [bus 00-ff]
pci_bus 0008:00: busn_res: [bus 00-ff] end is updated to ff
pci 0008:00:00.0: [1014:027f] type 00 class 0x068000
PCI: Hiding 4xx host bridge resources 0008:00:00.0
pci 0008:00:03.0: [1af4:1000] type 00 class 0x020000
pci 0008:00:03.0: reg 0x10: [io 0x0000-0x001f]
pci 0008:00:03.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
pci 0008:00:03.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
pci_bus 0008:00: busn_res: [bus 00-ff] end is updated to 00
pci 0008:00:03.0: BAR 6: assigned [mem 0x80000000-0x8003ffff pref]
pci 0008:00:03.0: BAR 4: assigned [mem 0x80040000-0x80043fff 64bit pref]
pci 0008:00:03.0: BAR 0: assigned [io 0x1000-0x101f]
pci_bus 0008:00: resource 4 [io 0x0000-0xffff]
pci_bus 0008:00: resource 5 [mem 0x80000000-0x9fffffff]
vgaarb: loaded
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
clocksource: Switched to clocksource timebase
NET: Registered PF_INET protocol family
IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear)
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear)
TCP bind hash table entries: 1024 (order: 0, 4096 bytes, linear)
TCP: Hash tables configured (established 1024 bind 1024)
UDP hash table entries: 256 (order: 0, 4096 bytes, linear)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes, linear)
NET: Registered PF_UNIX/PF_LOCAL protocol family
PCI: CLS 0 bytes, default 32
Trying to unpack rootfs image as initramfs...
workingset: timestamp_bits=30 max_order=15 bucket_order=0
io scheduler mq-deadline registered
io scheduler kyber registered
virtio-pci 0008:00:03.0: enabling device (0000 -> 0003)
Freeing initrd memory: 4532K
Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
printk: console [ttyS0] disabled
serial8250.0: ttyS0 at MMIO 0xef600400 (irq = 16, base_baud = 119047) is a 16550A
printk: console [ttyS0] enabled
printk: console [ttyS0] enabled
printk: bootconsole [udbg0] disabled
printk: bootconsole [udbg0] disabled
serial8250.0: ttyS1 at MMIO 0xef600300 (irq = 17, base_baud = 119047) is a 16550A
printk: console [ttyS0] disabled
printk: console [ttyS0] enabled
ef600300.serial: ttyS1 at MMIO 0xef600300 (irq = 17, base_baud = 119047) is a 16550
brd: module loaded
e1000: Intel(R) PRO/1000 Network Driver
e1000: Copyright (c) 1999-2006 Intel Corporation.
i2c_dev: i2c /dev entries driver
rtc-ds1307 0-0068: registered as rtc0
rtc-ds1307 0-0068: setting system clock to 2022-01-20T09:22:34 UTC (1642670554)
ibm-iic ef600500.i2c: using standard (100 kHz) mode
lm75: probe of 0-004a failed with error -121
NET: Registered PF_PACKET protocol family
drmem: No dynamic reconfiguration memory found
Freeing unused kernel image (initmem) memory: 168K
Kernel memory protection not selected by kernel config.
Run /init as init process
Starting syslogd: OK
Starting klogd: OK
Running sysctl: OK
Saving random seed: random: dd: uninitialized urandom read (512 bytes read)
OK
Starting network: udhcpc: started, v1.34.1
random: mktemp: uninitialized urandom read (6 bytes read)
udhcpc: broadcasting discover
udhcpc: broadcasting select for 192.168.199.76, server 192.168.199.1
udhcpc: lease of 192.168.199.76 obtained from 192.168.199.1, lease time 3600
deleting routers
random: mktemp: uninitialized urandom read (6 bytes read)
adding dns 192.168.199.1
OK
Welcome to Buildroot
buildroot login: root
# cat /proc/cpuinfo
processor : 0
cpu : 405EP
clock : 133.333333MHz
revision : 9.80 (pvr 5121 0950)
bogomips : 266.66
timebase : 133333333
platform : PowerPC 40x Platform
model : est,hotfoot
Memory : 128 MB
# cat /proc/interrupts
CPU0
16: 1552 UIC 1 Level ttyS0
23: 12 UIC 2 Level IBM IIC
27: 8 UIC 27 Level virtio0
LOC: 52166 Local timer interrupts for timer event device
BCT: 0 Broadcast timer interrupts for timer event device
LOC: 0 Local timer interrupts for others
SPU: 0 Spurious interrupts
PMI: 0 Performance monitoring interrupts
MCE: 0 Machine check exceptions
NMI: 0 System Reset interrupts
# ip a
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue qlen 1000
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
inet 127.0.0.1/8 scope host lo
valid_lft forever preferred_lft forever
2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast qlen 1000
link/ether 52:54:00:12:34:56 brd ff:ff:ff:ff:ff:ff
inet 192.168.199.76/24 brd 192.168.199.255 scope global eth0
valid_lft forever preferred_lft forever
# hwclock random: fast init done
Thu Jan 20 09:22:53 2022 0.000000 seconds
#
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 13/14] target/ppc: 405: Program exception cleanup
2022-01-19 12:54 ` Fabiano Rosas
@ 2022-01-20 16:23 ` Cédric Le Goater
0 siblings, 0 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-20 16:23 UTC (permalink / raw)
To: Fabiano Rosas, David Gibson; +Cc: danielhb413, qemu-ppc, qemu-devel
On 1/19/22 13:54, Fabiano Rosas wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
>> On Tue, Jan 18, 2022 at 03:44:47PM -0300, Fabiano Rosas wrote:
>>> The 405 Program Interrupt does not set SRR1 with any diagnostic bits,
>>> just a clean copy of the MSR.
>>>
>>> We're using the BookE Exception Syndrome Register which is different
>>> from the 405.
>>
>> Hrm. We really do want to set the 40x ESR bits here, though.
>
> Well I wrote the code and nothing changed so I dropped it. Not sure if
> we are even raising these properly in the translation code. I'll take
> another look.
>
For instance, this ESR bit allows Linux to handle traps correctly in
some cases, like when CONFIG_DEBUG_VM=y :
@@ -488,7 +488,9 @@ static void powerpc_excp_40x(PowerPCCPU
trace_ppc_excp_inval(env->nip);
break;
case POWERPC_EXCP_PRIV:
+ break;
case POWERPC_EXCP_TRAP:
+ env->spr[SPR_40x_ESR] = ESR_PTR;
break;
default:
cpu_abort(cs, "Invalid program exception %d. Aborting\n",
These could be reported to Linux :
/* On 4xx, the reason for the machine check or program exception
is in the ESR. */
#define get_reason(regs) ((regs)->esr)
#define REASON_FP ESR_FP
#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
#define REASON_PRIVILEGED ESR_PPR
#define REASON_TRAP ESR_PTR
#define REASON_PREFIXED 0
#define REASON_BOUNDARY 0
Thanks,
C.
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 12/14] target/ppc: 405: Instruction storage interrupt cleanup
2022-01-18 18:44 ` [PATCH v2 12/14] target/ppc: 405: Instruction storage interrupt cleanup Fabiano Rosas
@ 2022-01-20 22:17 ` Cédric Le Goater
2022-01-25 7:24 ` Cédric Le Goater
1 sibling, 0 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-20 22:17 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/18/22 19:44, Fabiano Rosas wrote:
> The 405 ISI does not set SRR1 with any exception syndrome bits, only a
> clean copy of the MSR.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> target/ppc/excp_helper.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index e4e513322c..13674a102f 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -715,7 +715,6 @@ static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int excp)
This change is done in the wrong routine.
Thanks,
C.
> break;
> case POWERPC_EXCP_ISI: /* Instruction storage exception */
> trace_ppc_excp_isi(msr, env->nip);
> - msr |= env->error_code;
> break;
> case POWERPC_EXCP_EXTERNAL: /* External input */
> {
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 11/14] target/ppc: 405: Data Storage exception cleanup
2022-01-19 6:13 ` David Gibson
2022-01-19 11:25 ` Cédric Le Goater
@ 2022-01-25 7:23 ` Cédric Le Goater
2022-01-25 7:29 ` Cédric Le Goater
1 sibling, 1 reply; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-25 7:23 UTC (permalink / raw)
To: David Gibson, Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel
On 1/19/22 07:13, David Gibson wrote:
> On Tue, Jan 18, 2022 at 03:44:45PM -0300, Fabiano Rosas wrote:
>> The 405 has no DSISR or DAR, so convert the trace entry to
>> trace_ppc_excp_print.
>
> I think it would be preferable to show ESR and DEAR here, which are
> very loosely equivalent to DSISR and DAR on 40x. Might want to create
> a new trace point explicitly for this so the terminology is clear as well.
I changed registers to ESR and DEAR and updated commit log.
Trace point changes can come later. Some have become a bit redundant
with CPU_LOG_INT.
Thanks,
C.
>
>>
>> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
>> ---
>> target/ppc/excp_helper.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index 84ec7e094a..e4e513322c 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -465,7 +465,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
>> srr1 = SPR_40x_SRR3;
>> break;
>> case POWERPC_EXCP_DSI: /* Data storage exception */
>> - trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
>> + trace_ppc_excp_print("DSI");
>> break;
>> case POWERPC_EXCP_ISI: /* Instruction storage exception */
>> trace_ppc_excp_isi(msr, env->nip);
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 12/14] target/ppc: 405: Instruction storage interrupt cleanup
2022-01-18 18:44 ` [PATCH v2 12/14] target/ppc: 405: Instruction storage interrupt cleanup Fabiano Rosas
2022-01-20 22:17 ` Cédric Le Goater
@ 2022-01-25 7:24 ` Cédric Le Goater
1 sibling, 0 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-25 7:24 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/18/22 19:44, Fabiano Rosas wrote:
> The 405 ISI does not set SRR1 with any exception syndrome bits, only a
> clean copy of the MSR.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
I changed the routine in which the removal was done. With that,
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/excp_helper.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index e4e513322c..13674a102f 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -715,7 +715,6 @@ static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int excp)
> break;
> case POWERPC_EXCP_ISI: /* Instruction storage exception */
> trace_ppc_excp_isi(msr, env->nip);
> - msr |= env->error_code;
> break;
> case POWERPC_EXCP_EXTERNAL: /* External input */
> {
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 13/14] target/ppc: 405: Program exception cleanup
2022-01-18 18:44 ` [PATCH v2 13/14] target/ppc: 405: Program exception cleanup Fabiano Rosas
2022-01-19 6:15 ` David Gibson
@ 2022-01-25 7:25 ` Cédric Le Goater
1 sibling, 0 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-25 7:25 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/18/22 19:44, Fabiano Rosas wrote:
> The 405 Program Interrupt does not set SRR1 with any diagnostic bits,
> just a clean copy of the MSR.
>
> We're using the BookE Exception Syndrome Register which is different
> from the 405.
I restored the setting of SPR_40x_ESR.
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/excp_helper.c | 16 ----------------
> 1 file changed, 16 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 13674a102f..2efec6d13b 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -484,30 +484,14 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> env->error_code = 0;
> return;
> }
> -
> - /*
> - * FP exceptions always have NIP pointing to the faulting
> - * instruction, so always use store_next and claim we are
> - * precise in the MSR.
> - */
> - msr |= 0x00100000;
> - env->spr[SPR_BOOKE_ESR] = ESR_FP;
> break;
> case POWERPC_EXCP_INVAL:
> trace_ppc_excp_inval(env->nip);
> - msr |= 0x00080000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PIL;
> break;
> case POWERPC_EXCP_PRIV:
> - msr |= 0x00040000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PPR;
> - break;
> case POWERPC_EXCP_TRAP:
> - msr |= 0x00020000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PTR;
> break;
> default:
> - /* Should never occur */
> cpu_abort(cs, "Invalid program exception %d. Aborting\n",
> env->error_code);
> break;
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 14/14] target/ppc: 405: Watchdog timer exception cleanup
2022-01-18 18:44 ` [PATCH v2 14/14] target/ppc: 405: Watchdog timer " Fabiano Rosas
@ 2022-01-25 7:26 ` Cédric Le Goater
0 siblings, 0 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-25 7:26 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/18/22 19:44, Fabiano Rosas wrote:
> Remove references to BookE.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
trace point is becoming redundant. Anyhow,
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/excp_helper.c | 9 ---------
> 1 file changed, 9 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 2efec6d13b..a22b783ecb 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -396,7 +396,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> {
> CPUState *cs = CPU(cpu);
> CPUPPCState *env = &cpu->env;
> - int excp_model = env->excp_model;
> target_ulong msr, new_msr, vector;
> int srr0, srr1;
>
> @@ -511,14 +510,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> break;
> case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
> trace_ppc_excp_print("WDT");
> - switch (excp_model) {
> - case POWERPC_EXCP_BOOKE:
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - default:
> - break;
> - }
> break;
> case POWERPC_EXCP_DTLB: /* Data TLB error */
> case POWERPC_EXCP_ITLB: /* Instruction TLB error */
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 11/14] target/ppc: 405: Data Storage exception cleanup
2022-01-25 7:23 ` Cédric Le Goater
@ 2022-01-25 7:29 ` Cédric Le Goater
0 siblings, 0 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-25 7:29 UTC (permalink / raw)
To: David Gibson, Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel
On 1/25/22 08:23, Cédric Le Goater wrote:
> On 1/19/22 07:13, David Gibson wrote:
>> On Tue, Jan 18, 2022 at 03:44:45PM -0300, Fabiano Rosas wrote:
>>> The 405 has no DSISR or DAR, so convert the trace entry to
>>> trace_ppc_excp_print.
>>
>> I think it would be preferable to show ESR and DEAR here, which are
>> very loosely equivalent to DSISR and DAR on 40x. Might want to create
>> a new trace point explicitly for this so the terminology is clear as well.
>
> I changed registers to ESR and DEAR and updated commit log.
>
> Trace point changes can come later. Some have become a bit redundant
> with CPU_LOG_INT.
And,
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 08/14] target/ppc: 405: System call exception cleanup
2022-01-19 6:09 ` David Gibson
@ 2022-01-25 8:18 ` Cédric Le Goater
2022-01-25 11:27 ` Cédric Le Goater
2022-01-25 12:49 ` BALATON Zoltan
0 siblings, 2 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-25 8:18 UTC (permalink / raw)
To: David Gibson, Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel
On 1/19/22 07:09, David Gibson wrote:
> On Tue, Jan 18, 2022 at 03:44:42PM -0300, Fabiano Rosas wrote:
>> There's no sc 1.
>
> No... but what exactly should and will happen if you attempt to
> execute an "sc 1" on 40x. Will it be treated as an "sc 0", or will it
> cause a 0x700? If it's a 0x700, better double check that that is
> generated at translation time, if you're removing the check on level
> here.
A Program Interrupt with the illegal instruction error code should be
generated at translation time but it is not the case today. It never
was correctly implemented AFAICT :
/* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
We would need a simple 'sc' instruction for the PPC405 and other
processors. Let's add that to the TODO list.
Thanks,
C.
>
>>
>> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
>> ---
>> target/ppc/excp_helper.c | 21 ++-------------------
>> 1 file changed, 2 insertions(+), 19 deletions(-)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index 8fae8aa0be..9a6f8365d6 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -398,7 +398,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
>> CPUPPCState *env = &cpu->env;
>> int excp_model = env->excp_model;
>> target_ulong msr, new_msr, vector;
>> - int srr0, srr1, lev = -1;
>> + int srr0, srr1;
>>
>> if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
>> cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
>> @@ -521,30 +521,13 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
>> }
>> break;
>> case POWERPC_EXCP_SYSCALL: /* System call exception */
>> - lev = env->error_code;
>> -
>> - if ((lev == 1) && cpu->vhyp) {
>> - dump_hcall(env);
>> - } else {
>> - dump_syscall(env);
>> - }
>> + dump_syscall(env);
>>
>> /*
>> * We need to correct the NIP which in this case is supposed
>> * to point to the next instruction
>> */
>> env->nip += 4;
>> -
>> - /* "PAPR mode" built-in hypercall emulation */
>> - if ((lev == 1) && cpu->vhyp) {
>> - PPCVirtualHypervisorClass *vhc =
>> - PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
>> - vhc->hypercall(cpu->vhyp, cpu);
>> - return;
>> - }
>> - if (lev == 1) {
>> - new_msr |= (target_ulong)MSR_HVB;
>> - }
>> break;
>> case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
>> trace_ppc_excp_print("FIT");
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 08/14] target/ppc: 405: System call exception cleanup
2022-01-25 8:18 ` Cédric Le Goater
@ 2022-01-25 11:27 ` Cédric Le Goater
2022-01-25 12:49 ` BALATON Zoltan
1 sibling, 0 replies; 44+ messages in thread
From: Cédric Le Goater @ 2022-01-25 11:27 UTC (permalink / raw)
To: David Gibson, Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel
On 1/25/22 09:18, Cédric Le Goater wrote:
> On 1/19/22 07:09, David Gibson wrote:
>> On Tue, Jan 18, 2022 at 03:44:42PM -0300, Fabiano Rosas wrote:
>>> There's no sc 1.
>>
>> No... but what exactly should and will happen if you attempt to
>> execute an "sc 1" on 40x. Will it be treated as an "sc 0", or will it
>> cause a 0x700? If it's a 0x700, better double check that that is
>> generated at translation time, if you're removing the check on level
>> here.
>
> A Program Interrupt with the illegal instruction error code should be
> generated at translation time but it is not the case today. It never
> was correctly implemented AFAICT :
>
> /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
> GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
> GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
>
> We would need a simple 'sc' instruction for the PPC405 and other
> processors. Let's add that to the TODO list.
The ref405ep machine now boots a mainline Linux with a buildroot user space.
Let's get this series merged first.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 08/14] target/ppc: 405: System call exception cleanup
2022-01-25 8:18 ` Cédric Le Goater
2022-01-25 11:27 ` Cédric Le Goater
@ 2022-01-25 12:49 ` BALATON Zoltan
1 sibling, 0 replies; 44+ messages in thread
From: BALATON Zoltan @ 2022-01-25 12:49 UTC (permalink / raw)
To: Cédric Le Goater
Cc: danielhb413, Fabiano Rosas, qemu-ppc, qemu-devel, David Gibson
[-- Attachment #1: Type: text/plain, Size: 1653 bytes --]
On Tue, 25 Jan 2022, Cédric Le Goater wrote:
> On 1/19/22 07:09, David Gibson wrote:
>> On Tue, Jan 18, 2022 at 03:44:42PM -0300, Fabiano Rosas wrote:
>>> There's no sc 1.
>>
>> No... but what exactly should and will happen if you attempt to
>> execute an "sc 1" on 40x. Will it be treated as an "sc 0", or will it
>> cause a 0x700? If it's a 0x700, better double check that that is
>> generated at translation time, if you're removing the check on level
>> here.
>
> A Program Interrupt with the illegal instruction error code should be
> generated at translation time but it is not the case today. It never
> was correctly implemented AFAICT :
>
> /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
> GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
> GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
>
> We would need a simple 'sc' instruction for the PPC405 and other
> processors. Let's add that to the TODO list.
Not directly related to this but as a reminder: if I remember correctly
VOF uses sc 1 for hypercalls and I use VOF on pegasos2 which has a G4 or
G3 CPU that does not have this instruction but we emulate that anyway so
this works now at least with TCG. AFAICT changes so far did not break this
but please consider this when getting there. We could use a different
method for hypercalls in VOF but that would either result in different VOF
binary for different machines or needing more changes to spap,r neither of
which is desirable, so we chose this solution for now to allow hypercalls
on 32bit PPC if the vhyp is set. This was in commit 5e994fc019862.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 03/14] target/ppc: Introduce powerpc_excp_40x
2022-01-18 18:44 ` [PATCH v2 03/14] target/ppc: Introduce powerpc_excp_40x Fabiano Rosas
2022-01-19 11:28 ` Cédric Le Goater
@ 2022-01-26 21:58 ` Richard Henderson
1 sibling, 0 replies; 44+ messages in thread
From: Richard Henderson @ 2022-01-26 21:58 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
On 1/19/22 5:44 AM, Fabiano Rosas wrote:
> Introduce a new powerpc_excp function specific for 40x CPUs. This
> commit copies powerpc_excp_legacy verbatim so the next one has a clean
> diff.
>
> Signed-off-by: Fabiano Rosas<farosas@linux.ibm.com>
> ---
> target/ppc/excp_helper.c | 474 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 474 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 05/14] target/ppc: 405: Critical exceptions cleanup
2022-01-18 18:44 ` [PATCH v2 05/14] target/ppc: 405: Critical exceptions cleanup Fabiano Rosas
@ 2022-01-26 21:58 ` Richard Henderson
0 siblings, 0 replies; 44+ messages in thread
From: Richard Henderson @ 2022-01-26 21:58 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
On 1/19/22 5:44 AM, Fabiano Rosas wrote:
> In powerpc_excp_40x the Critical exception is now for 405 only, so we
> can remove the BookE and G2 blocks.
>
> Signed-off-by: Fabiano Rosas<farosas@linux.ibm.com>
> Reviewed-by: David Gibson<david@gibson.dropbear.id.au>
> ---
> target/ppc/excp_helper.c | 17 ++---------------
> 1 file changed, 2 insertions(+), 15 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 07/14] target/ppc: 405: External exception cleanup
2022-01-18 18:44 ` [PATCH v2 07/14] target/ppc: 405: External " Fabiano Rosas
@ 2022-01-26 22:02 ` Richard Henderson
2022-01-26 22:20 ` Fabiano Rosas
0 siblings, 1 reply; 44+ messages in thread
From: Richard Henderson @ 2022-01-26 22:02 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
On 1/19/22 5:44 AM, Fabiano Rosas wrote:
> 405 has no MSR_HV and EPR is BookE only so we can remove it all.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/excp_helper.c | 37 -------------------------------------
> 1 file changed, 37 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index e98d783ecd..8fae8aa0be 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -472,44 +472,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> msr |= env->error_code;
> break;
> case POWERPC_EXCP_EXTERNAL: /* External input */
> - {
> - bool lpes0;
> -
> - cs = CPU(cpu);
> -
> - /*
> - * Exception targeting modifiers
> - *
> - * LPES0 is supported on POWER7/8/9
> - * LPES1 is not supported (old iSeries mode)
> - *
> - * On anything else, we behave as if LPES0 is 1
> - * (externals don't alter MSR:HV)
> - */
> -#if defined(TARGET_PPC64)
> - if (excp_model == POWERPC_EXCP_POWER7 ||
> - excp_model == POWERPC_EXCP_POWER8 ||
> - excp_model == POWERPC_EXCP_POWER9 ||
> - excp_model == POWERPC_EXCP_POWER10) {
> - lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
> - } else
> -#endif /* defined(TARGET_PPC64) */
> - {
> - lpes0 = true;
> - }
> -
> - if (!lpes0) {
> - new_msr |= (target_ulong)MSR_HVB;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> - srr0 = SPR_HSRR0;
> - srr1 = SPR_HSRR1;
> - }
> - if (env->mpic_proxy) {
> - /* IACK the IRQ on delivery */
> - env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
> - }
> break;
> - }
Bare break? Should this be reachable at all?
Should it in fact be g_assert_not_reached()?
r~
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 08/14] target/ppc: 405: System call exception cleanup
2022-01-18 18:44 ` [PATCH v2 08/14] target/ppc: 405: System call " Fabiano Rosas
2022-01-19 6:09 ` David Gibson
@ 2022-01-26 22:02 ` Richard Henderson
1 sibling, 0 replies; 44+ messages in thread
From: Richard Henderson @ 2022-01-26 22:02 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
On 1/19/22 5:44 AM, Fabiano Rosas wrote:
> There's no sc 1.
>
> Signed-off-by: Fabiano Rosas<farosas@linux.ibm.com>
> ---
> target/ppc/excp_helper.c | 21 ++-------------------
> 1 file changed, 2 insertions(+), 19 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 07/14] target/ppc: 405: External exception cleanup
2022-01-26 22:02 ` Richard Henderson
@ 2022-01-26 22:20 ` Fabiano Rosas
0 siblings, 0 replies; 44+ messages in thread
From: Fabiano Rosas @ 2022-01-26 22:20 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Richard Henderson <richard.henderson@linaro.org> writes:
> On 1/19/22 5:44 AM, Fabiano Rosas wrote:
>> 405 has no MSR_HV and EPR is BookE only so we can remove it all.
>>
>> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
>> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
>> ---
>> target/ppc/excp_helper.c | 37 -------------------------------------
>> 1 file changed, 37 deletions(-)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index e98d783ecd..8fae8aa0be 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -472,44 +472,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
>> msr |= env->error_code;
>> break;
>> case POWERPC_EXCP_EXTERNAL: /* External input */
>> - {
>> - bool lpes0;
>> -
>> - cs = CPU(cpu);
>> -
>> - /*
>> - * Exception targeting modifiers
>> - *
>> - * LPES0 is supported on POWER7/8/9
>> - * LPES1 is not supported (old iSeries mode)
>> - *
>> - * On anything else, we behave as if LPES0 is 1
>> - * (externals don't alter MSR:HV)
>> - */
>> -#if defined(TARGET_PPC64)
>> - if (excp_model == POWERPC_EXCP_POWER7 ||
>> - excp_model == POWERPC_EXCP_POWER8 ||
>> - excp_model == POWERPC_EXCP_POWER9 ||
>> - excp_model == POWERPC_EXCP_POWER10) {
>> - lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
>> - } else
>> -#endif /* defined(TARGET_PPC64) */
>> - {
>> - lpes0 = true;
>> - }
>> -
>> - if (!lpes0) {
>> - new_msr |= (target_ulong)MSR_HVB;
>> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
>> - srr0 = SPR_HSRR0;
>> - srr1 = SPR_HSRR1;
>> - }
>> - if (env->mpic_proxy) {
>> - /* IACK the IRQ on delivery */
>> - env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
>> - }
>> break;
>> - }
>
> Bare break? Should this be reachable at all?
> Should it in fact be g_assert_not_reached()?
It should be reachable. It is a valid exception for this CPU. We just
don't have anything else to do to dispatch it aside from what is done in
the generic code outside the switch statement.
^ permalink raw reply [flat|nested] 44+ messages in thread
end of thread, other threads:[~2022-01-26 22:23 UTC | newest]
Thread overview: 44+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-18 18:44 [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
2022-01-18 18:44 ` [PATCH v2 01/14] target/ppc: 405: Rename MSR_POW to MSR_WE Fabiano Rosas
2022-01-19 11:27 ` Cédric Le Goater
2022-01-18 18:44 ` [PATCH v2 02/14] target/ppc: 405: Add missing MSR_ME bit Fabiano Rosas
2022-01-19 11:26 ` Cédric Le Goater
2022-01-18 18:44 ` [PATCH v2 03/14] target/ppc: Introduce powerpc_excp_40x Fabiano Rosas
2022-01-19 11:28 ` Cédric Le Goater
2022-01-26 21:58 ` Richard Henderson
2022-01-18 18:44 ` [PATCH v2 04/14] target/ppc: Simplify powerpc_excp_40x Fabiano Rosas
2022-01-19 6:04 ` David Gibson
2022-01-18 18:44 ` [PATCH v2 05/14] target/ppc: 405: Critical exceptions cleanup Fabiano Rosas
2022-01-26 21:58 ` Richard Henderson
2022-01-18 18:44 ` [PATCH v2 06/14] target/ppc: 405: Machine check exception cleanup Fabiano Rosas
2022-01-19 6:06 ` David Gibson
2022-01-19 11:21 ` Cédric Le Goater
2022-01-18 18:44 ` [PATCH v2 07/14] target/ppc: 405: External " Fabiano Rosas
2022-01-26 22:02 ` Richard Henderson
2022-01-26 22:20 ` Fabiano Rosas
2022-01-18 18:44 ` [PATCH v2 08/14] target/ppc: 405: System call " Fabiano Rosas
2022-01-19 6:09 ` David Gibson
2022-01-25 8:18 ` Cédric Le Goater
2022-01-25 11:27 ` Cédric Le Goater
2022-01-25 12:49 ` BALATON Zoltan
2022-01-26 22:02 ` Richard Henderson
2022-01-18 18:44 ` [PATCH v2 09/14] target/ppc: 405: Alignment " Fabiano Rosas
2022-01-19 6:11 ` David Gibson
2022-01-18 18:44 ` [PATCH v2 10/14] target/ppc: 405: Debug " Fabiano Rosas
2022-01-19 6:12 ` David Gibson
2022-01-18 18:44 ` [PATCH v2 11/14] target/ppc: 405: Data Storage " Fabiano Rosas
2022-01-19 6:13 ` David Gibson
2022-01-19 11:25 ` Cédric Le Goater
2022-01-25 7:23 ` Cédric Le Goater
2022-01-25 7:29 ` Cédric Le Goater
2022-01-18 18:44 ` [PATCH v2 12/14] target/ppc: 405: Instruction storage interrupt cleanup Fabiano Rosas
2022-01-20 22:17 ` Cédric Le Goater
2022-01-25 7:24 ` Cédric Le Goater
2022-01-18 18:44 ` [PATCH v2 13/14] target/ppc: 405: Program exception cleanup Fabiano Rosas
2022-01-19 6:15 ` David Gibson
2022-01-19 12:54 ` Fabiano Rosas
2022-01-20 16:23 ` Cédric Le Goater
2022-01-25 7:25 ` Cédric Le Goater
2022-01-18 18:44 ` [PATCH v2 14/14] target/ppc: 405: Watchdog timer " Fabiano Rosas
2022-01-25 7:26 ` Cédric Le Goater
2022-01-20 9:33 ` [PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n) Cédric Le Goater
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