From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: will@kernel.org, linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu
Cc: linux-kernel@vger.kernel.org, mark.rutland@arm.com,
maz@kernel.org, anshuman.khandual@arm.com,
catalin.marinas@arm.com, saiprakash.ranjan@codeaurora.org,
dianders@chromium.org, kernel-team@android.com
Subject: Re: [PATCH 6/8] arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit only
Date: Wed, 15 Apr 2020 11:43:36 +0100 [thread overview]
Message-ID: <b648691c-e9cd-f0eb-2ed2-50451a4bceb8@arm.com> (raw)
In-Reply-To: <20200414213114.2378-7-will@kernel.org>
On 04/14/2020 10:31 PM, Will Deacon wrote:
> If AArch32 is not supported at EL1, the AArch32 feature register fields
> no longer advertise support for some system features:
>
> * ISAR4.SMC
> * PFR1.{Virt_frac, Sec_frac, Virtualization, Security, ProgMod}
>
> In which case, we don't need to emit "SANITY CHECK" failures for all of
> them.
>
> Add logic to relax the strictness of individual feature register fields
> at runtime and use this for the fields above if 32-bit EL1 is not
> supported.
>
> Signed-off-by: Will Deacon <will@kernel.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: will@kernel.org, linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu
Cc: saiprakash.ranjan@codeaurora.org, anshuman.khandual@arm.com,
maz@kernel.org, linux-kernel@vger.kernel.org,
dianders@chromium.org, catalin.marinas@arm.com,
kernel-team@android.com
Subject: Re: [PATCH 6/8] arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit only
Date: Wed, 15 Apr 2020 11:43:36 +0100 [thread overview]
Message-ID: <b648691c-e9cd-f0eb-2ed2-50451a4bceb8@arm.com> (raw)
In-Reply-To: <20200414213114.2378-7-will@kernel.org>
On 04/14/2020 10:31 PM, Will Deacon wrote:
> If AArch32 is not supported at EL1, the AArch32 feature register fields
> no longer advertise support for some system features:
>
> * ISAR4.SMC
> * PFR1.{Virt_frac, Sec_frac, Virtualization, Security, ProgMod}
>
> In which case, we don't need to emit "SANITY CHECK" failures for all of
> them.
>
> Add logic to relax the strictness of individual feature register fields
> at runtime and use this for the fields above if 32-bit EL1 is not
> supported.
>
> Signed-off-by: Will Deacon <will@kernel.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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kvmarm@lists.cs.columbia.edu
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WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: will@kernel.org, linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu
Cc: mark.rutland@arm.com, saiprakash.ranjan@codeaurora.org,
anshuman.khandual@arm.com, maz@kernel.org,
linux-kernel@vger.kernel.org, dianders@chromium.org,
catalin.marinas@arm.com, kernel-team@android.com
Subject: Re: [PATCH 6/8] arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit only
Date: Wed, 15 Apr 2020 11:43:36 +0100 [thread overview]
Message-ID: <b648691c-e9cd-f0eb-2ed2-50451a4bceb8@arm.com> (raw)
In-Reply-To: <20200414213114.2378-7-will@kernel.org>
On 04/14/2020 10:31 PM, Will Deacon wrote:
> If AArch32 is not supported at EL1, the AArch32 feature register fields
> no longer advertise support for some system features:
>
> * ISAR4.SMC
> * PFR1.{Virt_frac, Sec_frac, Virtualization, Security, ProgMod}
>
> In which case, we don't need to emit "SANITY CHECK" failures for all of
> them.
>
> Add logic to relax the strictness of individual feature register fields
> at runtime and use this for the fields above if 32-bit EL1 is not
> supported.
>
> Signed-off-by: Will Deacon <will@kernel.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-04-15 10:39 UTC|newest]
Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-14 21:31 [PATCH 0/8] Relax sanity checking for mismatched AArch32 EL1 Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` [PATCH 1/8] arm64: cpufeature: Relax check for IESB support Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 10:02 ` Suzuki K Poulose
2020-04-15 10:02 ` Suzuki K Poulose
2020-04-15 10:02 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 2/8] arm64: cpufeature: Spell out register fields for ID_ISAR4 and ID_PFR1 Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 10:09 ` Suzuki K Poulose
2020-04-15 10:09 ` Suzuki K Poulose
2020-04-15 10:09 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 3/8] arm64: cpufeature: Add CPU capability for AArch32 EL1 support Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 8:55 ` Marc Zyngier
2020-04-15 8:55 ` Marc Zyngier
2020-04-15 8:55 ` Marc Zyngier
2020-04-15 17:00 ` Will Deacon
2020-04-15 17:00 ` Will Deacon
2020-04-15 17:00 ` Will Deacon
2020-04-15 10:13 ` Suzuki K Poulose
2020-04-15 10:13 ` Suzuki K Poulose
2020-04-15 10:13 ` Suzuki K Poulose
2020-04-15 10:14 ` Will Deacon
2020-04-15 10:14 ` Will Deacon
2020-04-15 10:14 ` Will Deacon
2020-04-15 13:15 ` Suzuki K Poulose
2020-04-15 13:15 ` Suzuki K Poulose
2020-04-15 13:15 ` Suzuki K Poulose
2020-04-15 13:22 ` Marc Zyngier
2020-04-15 13:22 ` Marc Zyngier
2020-04-15 13:22 ` Marc Zyngier
2020-04-17 9:44 ` Suzuki K Poulose
2020-04-17 9:44 ` Suzuki K Poulose
2020-04-17 9:44 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 4/8] arm64: cpufeature: Remove redundant call to id_aa64pfr0_32bit_el0() Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 10:25 ` Suzuki K Poulose
2020-04-15 10:25 ` Suzuki K Poulose
2020-04-15 10:25 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 5/8] arm64: cpufeature: Factor out checking of AArch32 features Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 10:36 ` Suzuki K Poulose
2020-04-15 10:36 ` Suzuki K Poulose
2020-04-15 10:36 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 6/8] arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit only Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 10:43 ` Suzuki K Poulose [this message]
2020-04-15 10:43 ` Suzuki K Poulose
2020-04-15 10:43 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 7/8] arm64: cpufeature: Relax checks for AArch32 support at EL[0-2] Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-15 10:50 ` Suzuki K Poulose
2020-04-15 10:50 ` Suzuki K Poulose
2020-04-15 10:50 ` Suzuki K Poulose
2020-04-15 10:58 ` Will Deacon
2020-04-15 10:58 ` Will Deacon
2020-04-15 10:58 ` Will Deacon
2020-04-15 11:37 ` Suzuki K Poulose
2020-04-15 11:37 ` Suzuki K Poulose
2020-04-15 11:37 ` Suzuki K Poulose
2020-04-15 12:29 ` Will Deacon
2020-04-15 12:29 ` Will Deacon
2020-04-15 12:29 ` Will Deacon
2020-04-17 9:37 ` Suzuki K Poulose
2020-04-17 9:37 ` Suzuki K Poulose
2020-04-17 9:37 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 8/8] arm64: cpufeature: Add an overview comment for the cpufeature framework Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-14 21:31 ` Will Deacon
2020-04-16 11:58 ` Will Deacon
2020-04-16 11:58 ` Will Deacon
2020-04-16 11:58 ` Will Deacon
2020-04-16 14:59 ` Suzuki K Poulose
2020-04-16 14:59 ` Suzuki K Poulose
2020-04-16 14:59 ` Suzuki K Poulose
2020-04-16 15:26 ` Marc Zyngier
2020-04-16 15:26 ` Marc Zyngier
2020-04-16 15:26 ` Marc Zyngier
2020-04-16 18:12 ` Will Deacon
2020-04-16 18:12 ` Will Deacon
2020-04-16 18:12 ` Will Deacon
2020-04-16 8:39 ` [PATCH 0/8] Relax sanity checking for mismatched AArch32 EL1 Sai Prakash Ranjan
2020-04-16 8:39 ` Sai Prakash Ranjan
2020-04-16 8:39 ` Sai Prakash Ranjan
2020-04-16 10:26 ` Sai Prakash Ranjan
2020-04-16 10:26 ` Sai Prakash Ranjan
2020-04-16 10:26 ` Sai Prakash Ranjan
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