* [PATCH v5 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver
@ 2017-08-22 8:07 ` Shaokun Zhang
0 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: mark.rutland, will.deacon
Cc: jonathan.cameron, linux-arm-kernel, linux-kernel, linux-doc,
linuxarm, Shaokun Zhang
This patchset adds support for HiSilicon SoC uncore PMUs driver. It
includes L3C, Hydra Home Agent (HHA) and DDRC.
Changes in v5:
* remove unnecessary name/num_events member in hisi_pmu
* refactor hisi_pmu_hwevents structure
* remove hisi_pmu_alloc function
* revise cpuhotplug for L3C PMUs
* add cpuhotplug for HHA/DDRC PMUs
* fix the name format of uncore PMUs
* remove unnecessary variants
Changes in v4:
* remove redundant code and comments
* reverse the functions order in exit function
* remove some GPL information
* revise including header file
* fix Jonathan's other comments
Changes in v3:
* rebase to 4.13-rc1
* add dev_err if ioremap fails for PMUs
Changes in v2:
* fix kbuild test robot error
* make hisi_uncore_ops static
Shaokun Zhang (6):
Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
perf: hisi: Add support for HiSilicon SoC uncore PMU driver
perf: hisi: Add support for HiSilicon SoC L3C PMU driver
perf: hisi: Add support for HiSilicon SoC HHA PMU driver
perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
arm64: MAINTAINERS: hisi: Add HiSilicon SoC PMU support
Documentation/perf/hisi-pmu.txt | 53 +++
MAINTAINERS | 7 +
drivers/perf/Kconfig | 7 +
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 467 +++++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 477 +++++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 482 ++++++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 440 +++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 107 ++++++
include/linux/cpuhotplug.h | 3 +
11 files changed, 2045 insertions(+)
create mode 100644 Documentation/perf/hisi-pmu.txt
create mode 100644 drivers/perf/hisilicon/Makefile
create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h
--
1.9.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver
@ 2017-08-22 8:07 ` Shaokun Zhang
0 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: linux-arm-kernel
This patchset adds support for HiSilicon SoC uncore PMUs driver. It
includes L3C, Hydra Home Agent (HHA) and DDRC.
Changes in v5:
* remove unnecessary name/num_events member in hisi_pmu
* refactor hisi_pmu_hwevents structure
* remove hisi_pmu_alloc function
* revise cpuhotplug for L3C PMUs
* add cpuhotplug for HHA/DDRC PMUs
* fix the name format of uncore PMUs
* remove unnecessary variants
Changes in v4:
* remove redundant code and comments
* reverse the functions order in exit function
* remove some GPL information
* revise including header file
* fix Jonathan's other comments
Changes in v3:
* rebase to 4.13-rc1
* add dev_err if ioremap fails for PMUs
Changes in v2:
* fix kbuild test robot error
* make hisi_uncore_ops static
Shaokun Zhang (6):
Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
perf: hisi: Add support for HiSilicon SoC uncore PMU driver
perf: hisi: Add support for HiSilicon SoC L3C PMU driver
perf: hisi: Add support for HiSilicon SoC HHA PMU driver
perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
arm64: MAINTAINERS: hisi: Add HiSilicon SoC PMU support
Documentation/perf/hisi-pmu.txt | 53 +++
MAINTAINERS | 7 +
drivers/perf/Kconfig | 7 +
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 467 +++++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 477 +++++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 482 ++++++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 440 +++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 107 ++++++
include/linux/cpuhotplug.h | 3 +
11 files changed, 2045 insertions(+)
create mode 100644 Documentation/perf/hisi-pmu.txt
create mode 100644 drivers/perf/hisilicon/Makefile
create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h
--
1.9.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 1/6] Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
2017-08-22 8:07 ` Shaokun Zhang
@ 2017-08-22 8:07 ` Shaokun Zhang
-1 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: mark.rutland, will.deacon
Cc: jonathan.cameron, linux-arm-kernel, linux-kernel, linux-doc,
linuxarm, Shaokun Zhang, Anurup M
This patch adds documentation for the uncore PMUs on HiSilicon SoC.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
Documentation/perf/hisi-pmu.txt | 53 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/perf/hisi-pmu.txt
diff --git a/Documentation/perf/hisi-pmu.txt b/Documentation/perf/hisi-pmu.txt
new file mode 100644
index 0000000..267a028
--- /dev/null
+++ b/Documentation/perf/hisi-pmu.txt
@@ -0,0 +1,53 @@
+HiSilicon SoC uncore Performance Monitoring Unit (PMU)
+======================================================
+The HiSilicon SoC chip includes various independent system device PMUs
+such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
+independent and have hardware logic to gather statistics and performance
+information.
+
+The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
+(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is
+called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
+two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
+
+HiSilicon SoC uncore PMU driver
+---------------------------------------
+Each device PMU has separate registers for event counting, control and
+interrupt, and the PMU driver shall register perf PMU drivers like L3C,
+HHA and DDRC etc. The available events and configuration options shall
+be described in the sysfs, see :
+/sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
+/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
+The "perf list" command shall list the available events from sysfs.
+
+Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
+name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
+where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
+module.
+e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
+SCCL ID #3.
+e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
+SCCL ID #1.
+
+The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
+ID used to count the uncore PMU event.
+
+Example usage of perf:
+$# perf list
+hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]
+------------------------------------------
+hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]
+------------------------------------------
+hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]
+------------------------------------------
+hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]
+------------------------------------------
+
+$# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
+$# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
+
+The current driver does not support sampling. So "perf record" is unsupported.
+Also attach to a task is unsupported as the events are all uncore.
+
+Note: Please contact the maintainer for a complete list of events supported for
+the PMU devices in the SoC and its information if needed.
--
1.9.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 1/6] Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
@ 2017-08-22 8:07 ` Shaokun Zhang
0 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds documentation for the uncore PMUs on HiSilicon SoC.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
Documentation/perf/hisi-pmu.txt | 53 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/perf/hisi-pmu.txt
diff --git a/Documentation/perf/hisi-pmu.txt b/Documentation/perf/hisi-pmu.txt
new file mode 100644
index 0000000..267a028
--- /dev/null
+++ b/Documentation/perf/hisi-pmu.txt
@@ -0,0 +1,53 @@
+HiSilicon SoC uncore Performance Monitoring Unit (PMU)
+======================================================
+The HiSilicon SoC chip includes various independent system device PMUs
+such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
+independent and have hardware logic to gather statistics and performance
+information.
+
+The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
+(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is
+called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
+two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
+
+HiSilicon SoC uncore PMU driver
+---------------------------------------
+Each device PMU has separate registers for event counting, control and
+interrupt, and the PMU driver shall register perf PMU drivers like L3C,
+HHA and DDRC etc. The available events and configuration options shall
+be described in the sysfs, see :
+/sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
+/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
+The "perf list" command shall list the available events from sysfs.
+
+Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
+name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
+where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
+module.
+e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
+SCCL ID #3.
+e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
+SCCL ID #1.
+
+The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
+ID used to count the uncore PMU event.
+
+Example usage of perf:
+$# perf list
+hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]
+------------------------------------------
+hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]
+------------------------------------------
+hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]
+------------------------------------------
+hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]
+------------------------------------------
+
+$# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
+$# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
+
+The current driver does not support sampling. So "perf record" is unsupported.
+Also attach to a task is unsupported as the events are all uncore.
+
+Note: Please contact the maintainer for a complete list of events supported for
+the PMU devices in the SoC and its information if needed.
--
1.9.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 2/6] perf: hisi: Add support for HiSilicon SoC uncore PMU driver
2017-08-22 8:07 ` Shaokun Zhang
@ 2017-08-22 8:07 ` Shaokun Zhang
-1 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: mark.rutland, will.deacon
Cc: jonathan.cameron, linux-arm-kernel, linux-kernel, linux-doc,
linuxarm, Shaokun Zhang, Anurup M
This patch adds support HiSilicon SoC uncore PMU driver framework and
interfaces.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
drivers/perf/Kconfig | 7 +
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/hisi_uncore_pmu.c | 440 +++++++++++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 107 ++++++++
5 files changed, 556 insertions(+)
create mode 100644 drivers/perf/hisilicon/Makefile
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index e5197ff..b1a3894 100644
--- a/drivers/perf/Kconfig
+++ b/drivers/perf/Kconfig
@@ -17,6 +17,13 @@ config ARM_PMU_ACPI
depends on ARM_PMU && ACPI
def_bool y
+config HISI_PMU
+ bool "HiSilicon SoC PMU"
+ depends on ARM64 && ACPI
+ help
+ Support for HiSilicon SoC uncore performance monitoring
+ unit (PMU), such as: L3C, HHA and DDRC.
+
config QCOM_L2_PMU
bool "Qualcomm Technologies L2-cache PMU"
depends on ARCH_QCOM && ARM64 && ACPI
diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile
index 6420bd4..41d3342 100644
--- a/drivers/perf/Makefile
+++ b/drivers/perf/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_ARM_PMU) += arm_pmu.o arm_pmu_platform.o
obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o
+obj-$(CONFIG_HISI_PMU) += hisilicon/
obj-$(CONFIG_QCOM_L2_PMU) += qcom_l2_pmu.o
obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o
obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
new file mode 100644
index 0000000..2783bb3
--- /dev/null
+++ b/drivers/perf/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c
new file mode 100644
index 0000000..f7e8ca2
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c
@@ -0,0 +1,440 @@
+/*
+ * HiSilicon SoC Hardware event counters support
+ *
+ * Copyright (C) 2017 Hisilicon Limited
+ * Author: Anurup M <anurup.m@huawei.com>
+ * Shaokun Zhang <zhangshaokun@hisilicon.com>
+ *
+ * This code is based on the uncore PMUs like arm-cci and arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+
+#include <asm/local64.h>
+
+#include "hisi_uncore_pmu.h"
+
+#define HISI_GET_EVENTID(ev) (ev->hw.config_base & 0xff)
+#define HISI_MAX_PERIOD(nr) (BIT_ULL(nr) - 1)
+
+/*
+ * PMU format attributes
+ */
+ssize_t hisi_format_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct dev_ext_attribute *eattr;
+
+ eattr = container_of(attr, struct dev_ext_attribute, attr);
+
+ return sprintf(buf, "%s\n", (char *)eattr->var);
+}
+
+/*
+ * PMU event attributes
+ */
+ssize_t hisi_event_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *page)
+{
+ struct dev_ext_attribute *eattr;
+
+ eattr = container_of(attr, struct dev_ext_attribute, attr);
+
+ return sprintf(page, "config=0x%lx\n", (unsigned long)eattr->var);
+}
+
+/*
+ * sysfs cpumask attributes. For uncore PMU, we only have a single CPU to show
+ */
+ssize_t hisi_cpumask_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(dev_get_drvdata(dev));
+
+ return sprintf(buf, "%d\n", hisi_pmu->on_cpu);
+}
+
+static bool hisi_validate_event_group(struct perf_event *event)
+{
+ struct perf_event *sibling, *leader = event->group_leader;
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ /* Include count for the event */
+ int counters = 1;
+
+ /*
+ * We must NOT create groups containing mixed PMUs, although
+ * software events are acceptable
+ */
+ if (leader->pmu != event->pmu && !is_software_event(leader))
+ return false;
+
+ /* Increment counter for the leader */
+ counters++;
+
+ list_for_each_entry(sibling, &event->group_leader->sibling_list,
+ group_entry) {
+ if (is_software_event(sibling))
+ continue;
+ if (sibling->pmu != event->pmu)
+ return false;
+ /* Increment counter for each sibling */
+ counters++;
+ }
+
+ /* The group can not count events more than the counters in the HW */
+ return counters <= hisi_pmu->num_counters;
+}
+
+int hisi_uncore_pmu_counter_valid(struct hisi_pmu *hisi_pmu, int idx)
+{
+ return (idx >= 0 && idx < hisi_pmu->num_counters);
+}
+
+int hisi_uncore_pmu_get_event_idx(struct perf_event *event)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ unsigned long *used_mask = hisi_pmu->pmu_events.used_mask;
+ u32 num_counters = hisi_pmu->num_counters;
+ int idx;
+
+ idx = find_first_zero_bit(used_mask, num_counters);
+ if (idx == num_counters)
+ return -EAGAIN;
+
+ set_bit(idx, used_mask);
+
+ return idx;
+}
+
+static void hisi_uncore_pmu_clear_event_idx(struct hisi_pmu *hisi_pmu, int idx)
+{
+ if (!hisi_uncore_pmu_counter_valid(hisi_pmu, idx)) {
+ dev_err(hisi_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ clear_bit(idx, hisi_pmu->pmu_events.used_mask);
+}
+
+int hisi_uncore_pmu_event_init(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hisi_pmu *hisi_pmu;
+
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ /*
+ * We do not support sampling as the counters are all
+ * shared by all CPU cores in a CPU die(SCCL). Also we
+ * do not support attach to a task(per-process mode)
+ */
+ if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
+ return -EOPNOTSUPP;
+
+ /* counters do not have these bits */
+ if (event->attr.exclude_user ||
+ event->attr.exclude_kernel ||
+ event->attr.exclude_host ||
+ event->attr.exclude_guest ||
+ event->attr.exclude_hv ||
+ event->attr.exclude_idle)
+ return -EINVAL;
+
+ /*
+ * The uncore counters not specific to any CPU, so cannot
+ * support per-task
+ */
+ if (event->cpu < 0)
+ return -EINVAL;
+
+ /*
+ * Validate if the events in group does not exceed the
+ * available counters in hardware.
+ */
+ if (!hisi_validate_event_group(event))
+ return -EINVAL;
+
+ /*
+ * We don't assign an index until we actually place the event onto
+ * hardware. Use -1 to signify that we haven't decided where to put it
+ * yet.
+ */
+ hwc->idx = -1;
+ hwc->config_base = event->attr.config;
+
+ hisi_pmu = to_hisi_pmu(event->pmu);
+ /* Enforce to use the same CPU for all events in this PMU */
+ event->cpu = hisi_pmu->on_cpu;
+
+ return 0;
+}
+
+/*
+ * Set the counter to count the event that we're interested in,
+ * and enable interrupt and counter.
+ */
+static void hisi_uncore_pmu_enable_event(struct perf_event *event)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
+ hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx,
+ HISI_GET_EVENTID(event));
+
+ hisi_pmu->ops->enable_counter_int(hisi_pmu, hwc);
+ hisi_pmu->ops->enable_counter(hisi_pmu, hwc);
+}
+
+/*
+ * Disable counter and interrupt.
+ */
+static void hisi_uncore_pmu_disable_event(struct perf_event *event)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
+ hisi_pmu->ops->disable_counter(hisi_pmu, hwc);
+ hisi_pmu->ops->disable_counter_int(hisi_pmu, hwc);
+}
+
+void hisi_uncore_pmu_set_event_period(struct perf_event *event)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
+ /*
+ * The HiSilicon PMU counters support 32 bits or 48 bits, depending on
+ * the PMU. We reduce it to 2^(counter_bits - 1) to account for the
+ * extreme interrupt latency. So we could hopefully handle the overflow
+ * interrupt before another 2^(counter_bits - 1) events occur and the
+ * counter overtakes its previous value.
+ */
+ u64 val = BIT_ULL(hisi_pmu->counter_bits - 1);
+
+ local64_set(&hwc->prev_count, val);
+ /* Write start value to the hardware event counter */
+ hisi_pmu->ops->write_counter(hisi_pmu, hwc, val);
+}
+
+void hisi_uncore_pmu_event_update(struct perf_event *event)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ u64 delta, prev_raw_count, new_raw_count;
+
+ do {
+ /* Read the count from the counter register */
+ new_raw_count = hisi_pmu->ops->read_counter(hisi_pmu, hwc);
+ prev_raw_count = local64_read(&hwc->prev_count);
+ } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+ new_raw_count) != prev_raw_count);
+ /*
+ * compute the delta
+ */
+ delta = (new_raw_count - prev_raw_count) &
+ HISI_MAX_PERIOD(hisi_pmu->counter_bits);
+ local64_add(delta, &event->count);
+}
+
+void hisi_uncore_pmu_start(struct perf_event *event, int flags)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
+ if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
+ return;
+
+ WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+ hwc->state = 0;
+ hisi_uncore_pmu_set_event_period(event);
+
+ if (flags & PERF_EF_RELOAD) {
+ u64 prev_raw_count = local64_read(&hwc->prev_count);
+
+ hisi_pmu->ops->write_counter(hisi_pmu, hwc, prev_raw_count);
+ }
+
+ hisi_uncore_pmu_enable_event(event);
+ perf_event_update_userpage(event);
+}
+
+void hisi_uncore_pmu_stop(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ hisi_uncore_pmu_disable_event(event);
+ WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
+ hwc->state |= PERF_HES_STOPPED;
+
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ /* Read hardware counter and update the perf counter statistics */
+ hisi_uncore_pmu_event_update(event);
+ hwc->state |= PERF_HES_UPTODATE;
+}
+
+int hisi_uncore_pmu_add(struct perf_event *event, int flags)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx;
+
+ hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
+
+ /* Get an available counter index for counting */
+ idx = hisi_pmu->ops->get_event_idx(event);
+ if (idx < 0)
+ return idx;
+
+ event->hw.idx = idx;
+ hisi_pmu->pmu_events.hw_events[idx] = event;
+
+ if (flags & PERF_EF_START)
+ hisi_uncore_pmu_start(event, PERF_EF_RELOAD);
+
+ return 0;
+}
+
+void hisi_uncore_pmu_del(struct perf_event *event, int flags)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
+ hisi_uncore_pmu_stop(event, PERF_EF_UPDATE);
+ hisi_uncore_pmu_clear_event_idx(hisi_pmu, hwc->idx);
+ perf_event_update_userpage(event);
+ hisi_pmu->pmu_events.hw_events[hwc->idx] = NULL;
+}
+
+void hisi_uncore_pmu_read(struct perf_event *event)
+{
+ /* Read hardware counter and update the perf counter statistics */
+ hisi_uncore_pmu_event_update(event);
+}
+
+void hisi_uncore_pmu_enable(struct pmu *pmu)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
+ int enabled = bitmap_weight(hisi_pmu->pmu_events.used_mask,
+ hisi_pmu->num_counters);
+
+ if (!enabled)
+ return;
+
+ hisi_pmu->ops->start_counters(hisi_pmu);
+}
+
+void hisi_uncore_pmu_disable(struct pmu *pmu)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
+
+ hisi_pmu->ops->stop_counters(hisi_pmu);
+}
+
+/*
+ * Read Super CPU cluster and CPU cluster ID from MPIDR_EL1.
+ * If multi-threading is supported, SCCL_ID is in MPIDR[aff3] and CCL_ID
+ * is in MPIDR[aff2]; if not, SCCL_ID is in MPIDR[aff2] and CCL_ID is
+ * in MPIDR[aff1]. If this changes in future, this shall be updated.
+ */
+void hisi_read_sccl_and_ccl_id(u32 *sccl_id, u32 *ccl_id)
+{
+ u64 mpidr;
+
+ mpidr = read_cpuid_mpidr();
+ if (mpidr & MPIDR_MT_BITMASK) {
+ if (sccl_id)
+ *sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 3);
+ if (ccl_id)
+ *ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+ } else {
+ if (sccl_id)
+ *sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+ if (ccl_id)
+ *ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+ }
+}
+
+int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct hisi_pmu *hisi_pmu;
+
+ hisi_pmu = hlist_entry_safe(node, struct hisi_pmu, node);
+
+ /*
+ * If the CPU is associated with the PMU, set it in online_cpus of
+ * the PMU.
+ */
+ if (cpumask_test_cpu(cpu, &hisi_pmu->associated_cpus))
+ cpumask_set_cpu(cpu, &hisi_pmu->online_cpus);
+ else
+ return 0;
+
+ /* If another CPU is already managing this PMU, simply return. */
+ if (hisi_pmu->on_cpu != -1)
+ return 0;
+
+ /* Use this CPU in cpumask for event counting */
+ hisi_pmu->on_cpu = cpu;
+
+ /* Overflow interrupt also should use the same CPU */
+ WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(cpu)));
+
+ return 0;
+}
+
+int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct hisi_pmu *hisi_pmu;
+ cpumask_t pmu_online_cpus;
+ unsigned int target;
+
+ hisi_pmu = hlist_entry_safe(node, struct hisi_pmu, node);
+
+ /*
+ * If the CPU is online with the PMU, clear it in online_cpus of
+ * the PMU.
+ */
+ if (!cpumask_test_and_clear_cpu(cpu, &hisi_pmu->online_cpus) ||
+ (hisi_pmu->on_cpu != cpu))
+ return 0;
+
+ hisi_pmu->on_cpu = -1;
+
+ /* Any other CPU associated with the PMU is still online */
+ cpumask_and(&pmu_online_cpus, &hisi_pmu->online_cpus, cpu_online_mask);
+ target = cpumask_any_but(&pmu_online_cpus, cpu);
+ if (target >= nr_cpu_ids)
+ return 0;
+
+ perf_pmu_migrate_context(&hisi_pmu->pmu, cpu, target);
+ /* Use this CPU for event counting */
+ hisi_pmu->on_cpu = target;
+ WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(target)));
+
+ return 0;
+}
+
+/*
+ * Check whether the CPU is associated with this uncore PMU by SCCL_ID,
+ * if true, set the associated cpumask of the uncore PMU.
+ */
+void hisi_uncore_pmu_set_cpumask_by_sccl(void *arg)
+{
+ struct hisi_pmu *hisi_pmu = (struct hisi_pmu *)arg;
+ u32 sccl_id;
+
+ hisi_read_sccl_and_ccl_id(&sccl_id, NULL);
+ if (sccl_id == hisi_pmu->sccl_id)
+ cpumask_set_cpu(smp_processor_id(), &hisi_pmu->associated_cpus);
+}
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.h b/drivers/perf/hisilicon/hisi_uncore_pmu.h
new file mode 100644
index 0000000..4cda9ca
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.h
@@ -0,0 +1,107 @@
+/*
+ * HiSilicon SoC Hardware event counters support
+ *
+ * Copyright (C) 2017 Hisilicon Limited
+ * Author: Anurup M <anurup.m@huawei.com>
+ * Shaokun Zhang <zhangshaokun@hisilicon.com>
+ *
+ * This code is based on the uncore PMUs like arm-cci and arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __HISI_UNCORE_PMU_H__
+#define __HISI_UNCORE_PMU_H__
+
+#include <linux/cpumask.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/perf_event.h>
+#include <linux/types.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "hisi_pmu: " fmt
+
+#define HISI_MAX_COUNTERS 0x10
+#define to_hisi_pmu(p) (container_of(p, struct hisi_pmu, pmu))
+
+#define HISI_PMU_ATTR(_name, _func, _config) \
+ (&((struct dev_ext_attribute[]) { \
+ { __ATTR(_name, 0444, _func, NULL), (void *)_config } \
+ })[0].attr.attr)
+
+#define HISI_PMU_FORMAT_ATTR(_name, _config) \
+ HISI_PMU_ATTR(_name, hisi_format_sysfs_show, (void *)_config)
+#define HISI_PMU_EVENT_ATTR(_name, _config) \
+ HISI_PMU_ATTR(_name, hisi_event_sysfs_show, (unsigned long)_config)
+
+struct hisi_pmu;
+
+struct hisi_uncore_ops {
+ void (*write_evtype)(struct hisi_pmu *, int, u32);
+ int (*get_event_idx)(struct perf_event *);
+ u64 (*read_counter)(struct hisi_pmu *, struct hw_perf_event *);
+ void (*write_counter)(struct hisi_pmu *, struct hw_perf_event *, u64);
+ void (*enable_counter)(struct hisi_pmu *, struct hw_perf_event *);
+ void (*disable_counter)(struct hisi_pmu *, struct hw_perf_event *);
+ void (*enable_counter_int)(struct hisi_pmu *, struct hw_perf_event *);
+ void (*disable_counter_int)(struct hisi_pmu *, struct hw_perf_event *);
+ void (*start_counters)(struct hisi_pmu *);
+ void (*stop_counters)(struct hisi_pmu *);
+};
+
+struct hisi_pmu_hwevents {
+ struct perf_event *hw_events[HISI_MAX_COUNTERS];
+ DECLARE_BITMAP(used_mask, HISI_MAX_COUNTERS);
+};
+
+/* Generic pmu struct for different pmu types */
+struct hisi_pmu {
+ struct pmu pmu;
+ const struct hisi_uncore_ops *ops;
+ struct hisi_pmu_hwevents pmu_events;
+ /*
+ * online_cpus: All online CPUs associated with the PMU
+ * associated_cpus: All CPUs associated with the PMU who is
+ * initialised when probe.
+ */
+ cpumask_t online_cpus, associated_cpus;
+ /* CPU used for counting */
+ int on_cpu;
+ int irq;
+ struct device *dev;
+ struct hlist_node node;
+ u32 sccl_id;
+ u32 ccl_id;
+ /* Hardware information for different pmu types */
+ void __iomem *base;
+ /* the ID of the PMU modules */
+ u32 id;
+ int num_counters;
+ int counter_bits;
+};
+
+int hisi_uncore_pmu_counter_valid(struct hisi_pmu *hisi_pmu, int idx);
+int hisi_uncore_pmu_get_event_idx(struct perf_event *event);
+void hisi_uncore_pmu_read(struct perf_event *event);
+int hisi_uncore_pmu_add(struct perf_event *event, int flags);
+void hisi_uncore_pmu_del(struct perf_event *event, int flags);
+void hisi_uncore_pmu_start(struct perf_event *event, int flags);
+void hisi_uncore_pmu_stop(struct perf_event *event, int flags);
+void hisi_uncore_pmu_set_event_period(struct perf_event *event);
+void hisi_uncore_pmu_event_update(struct perf_event *event);
+int hisi_uncore_pmu_event_init(struct perf_event *event);
+void hisi_uncore_pmu_enable(struct pmu *pmu);
+void hisi_uncore_pmu_disable(struct pmu *pmu);
+ssize_t hisi_event_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf);
+ssize_t hisi_format_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf);
+ssize_t hisi_cpumask_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf);
+void hisi_read_sccl_and_ccl_id(u32 *sccl_id, u32 *ccl_id);
+int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node);
+int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node);
+void hisi_uncore_pmu_set_cpumask_by_sccl(void *arg);
+#endif /* __HISI_UNCORE_PMU_H__ */
--
1.9.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 2/6] perf: hisi: Add support for HiSilicon SoC uncore PMU driver
@ 2017-08-22 8:07 ` Shaokun Zhang
0 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support HiSilicon SoC uncore PMU driver framework and
interfaces.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
drivers/perf/Kconfig | 7 +
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/hisi_uncore_pmu.c | 440 +++++++++++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 107 ++++++++
5 files changed, 556 insertions(+)
create mode 100644 drivers/perf/hisilicon/Makefile
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index e5197ff..b1a3894 100644
--- a/drivers/perf/Kconfig
+++ b/drivers/perf/Kconfig
@@ -17,6 +17,13 @@ config ARM_PMU_ACPI
depends on ARM_PMU && ACPI
def_bool y
+config HISI_PMU
+ bool "HiSilicon SoC PMU"
+ depends on ARM64 && ACPI
+ help
+ Support for HiSilicon SoC uncore performance monitoring
+ unit (PMU), such as: L3C, HHA and DDRC.
+
config QCOM_L2_PMU
bool "Qualcomm Technologies L2-cache PMU"
depends on ARCH_QCOM && ARM64 && ACPI
diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile
index 6420bd4..41d3342 100644
--- a/drivers/perf/Makefile
+++ b/drivers/perf/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_ARM_PMU) += arm_pmu.o arm_pmu_platform.o
obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o
+obj-$(CONFIG_HISI_PMU) += hisilicon/
obj-$(CONFIG_QCOM_L2_PMU) += qcom_l2_pmu.o
obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o
obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
new file mode 100644
index 0000000..2783bb3
--- /dev/null
+++ b/drivers/perf/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c
new file mode 100644
index 0000000..f7e8ca2
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c
@@ -0,0 +1,440 @@
+/*
+ * HiSilicon SoC Hardware event counters support
+ *
+ * Copyright (C) 2017 Hisilicon Limited
+ * Author: Anurup M <anurup.m@huawei.com>
+ * Shaokun Zhang <zhangshaokun@hisilicon.com>
+ *
+ * This code is based on the uncore PMUs like arm-cci and arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+
+#include <asm/local64.h>
+
+#include "hisi_uncore_pmu.h"
+
+#define HISI_GET_EVENTID(ev) (ev->hw.config_base & 0xff)
+#define HISI_MAX_PERIOD(nr) (BIT_ULL(nr) - 1)
+
+/*
+ * PMU format attributes
+ */
+ssize_t hisi_format_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct dev_ext_attribute *eattr;
+
+ eattr = container_of(attr, struct dev_ext_attribute, attr);
+
+ return sprintf(buf, "%s\n", (char *)eattr->var);
+}
+
+/*
+ * PMU event attributes
+ */
+ssize_t hisi_event_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *page)
+{
+ struct dev_ext_attribute *eattr;
+
+ eattr = container_of(attr, struct dev_ext_attribute, attr);
+
+ return sprintf(page, "config=0x%lx\n", (unsigned long)eattr->var);
+}
+
+/*
+ * sysfs cpumask attributes. For uncore PMU, we only have a single CPU to show
+ */
+ssize_t hisi_cpumask_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(dev_get_drvdata(dev));
+
+ return sprintf(buf, "%d\n", hisi_pmu->on_cpu);
+}
+
+static bool hisi_validate_event_group(struct perf_event *event)
+{
+ struct perf_event *sibling, *leader = event->group_leader;
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ /* Include count for the event */
+ int counters = 1;
+
+ /*
+ * We must NOT create groups containing mixed PMUs, although
+ * software events are acceptable
+ */
+ if (leader->pmu != event->pmu && !is_software_event(leader))
+ return false;
+
+ /* Increment counter for the leader */
+ counters++;
+
+ list_for_each_entry(sibling, &event->group_leader->sibling_list,
+ group_entry) {
+ if (is_software_event(sibling))
+ continue;
+ if (sibling->pmu != event->pmu)
+ return false;
+ /* Increment counter for each sibling */
+ counters++;
+ }
+
+ /* The group can not count events more than the counters in the HW */
+ return counters <= hisi_pmu->num_counters;
+}
+
+int hisi_uncore_pmu_counter_valid(struct hisi_pmu *hisi_pmu, int idx)
+{
+ return (idx >= 0 && idx < hisi_pmu->num_counters);
+}
+
+int hisi_uncore_pmu_get_event_idx(struct perf_event *event)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ unsigned long *used_mask = hisi_pmu->pmu_events.used_mask;
+ u32 num_counters = hisi_pmu->num_counters;
+ int idx;
+
+ idx = find_first_zero_bit(used_mask, num_counters);
+ if (idx == num_counters)
+ return -EAGAIN;
+
+ set_bit(idx, used_mask);
+
+ return idx;
+}
+
+static void hisi_uncore_pmu_clear_event_idx(struct hisi_pmu *hisi_pmu, int idx)
+{
+ if (!hisi_uncore_pmu_counter_valid(hisi_pmu, idx)) {
+ dev_err(hisi_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ clear_bit(idx, hisi_pmu->pmu_events.used_mask);
+}
+
+int hisi_uncore_pmu_event_init(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hisi_pmu *hisi_pmu;
+
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ /*
+ * We do not support sampling as the counters are all
+ * shared by all CPU cores in a CPU die(SCCL). Also we
+ * do not support attach to a task(per-process mode)
+ */
+ if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
+ return -EOPNOTSUPP;
+
+ /* counters do not have these bits */
+ if (event->attr.exclude_user ||
+ event->attr.exclude_kernel ||
+ event->attr.exclude_host ||
+ event->attr.exclude_guest ||
+ event->attr.exclude_hv ||
+ event->attr.exclude_idle)
+ return -EINVAL;
+
+ /*
+ * The uncore counters not specific to any CPU, so cannot
+ * support per-task
+ */
+ if (event->cpu < 0)
+ return -EINVAL;
+
+ /*
+ * Validate if the events in group does not exceed the
+ * available counters in hardware.
+ */
+ if (!hisi_validate_event_group(event))
+ return -EINVAL;
+
+ /*
+ * We don't assign an index until we actually place the event onto
+ * hardware. Use -1 to signify that we haven't decided where to put it
+ * yet.
+ */
+ hwc->idx = -1;
+ hwc->config_base = event->attr.config;
+
+ hisi_pmu = to_hisi_pmu(event->pmu);
+ /* Enforce to use the same CPU for all events in this PMU */
+ event->cpu = hisi_pmu->on_cpu;
+
+ return 0;
+}
+
+/*
+ * Set the counter to count the event that we're interested in,
+ * and enable interrupt and counter.
+ */
+static void hisi_uncore_pmu_enable_event(struct perf_event *event)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
+ hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx,
+ HISI_GET_EVENTID(event));
+
+ hisi_pmu->ops->enable_counter_int(hisi_pmu, hwc);
+ hisi_pmu->ops->enable_counter(hisi_pmu, hwc);
+}
+
+/*
+ * Disable counter and interrupt.
+ */
+static void hisi_uncore_pmu_disable_event(struct perf_event *event)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
+ hisi_pmu->ops->disable_counter(hisi_pmu, hwc);
+ hisi_pmu->ops->disable_counter_int(hisi_pmu, hwc);
+}
+
+void hisi_uncore_pmu_set_event_period(struct perf_event *event)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
+ /*
+ * The HiSilicon PMU counters support 32 bits or 48 bits, depending on
+ * the PMU. We reduce it to 2^(counter_bits - 1) to account for the
+ * extreme interrupt latency. So we could hopefully handle the overflow
+ * interrupt before another 2^(counter_bits - 1) events occur and the
+ * counter overtakes its previous value.
+ */
+ u64 val = BIT_ULL(hisi_pmu->counter_bits - 1);
+
+ local64_set(&hwc->prev_count, val);
+ /* Write start value to the hardware event counter */
+ hisi_pmu->ops->write_counter(hisi_pmu, hwc, val);
+}
+
+void hisi_uncore_pmu_event_update(struct perf_event *event)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ u64 delta, prev_raw_count, new_raw_count;
+
+ do {
+ /* Read the count from the counter register */
+ new_raw_count = hisi_pmu->ops->read_counter(hisi_pmu, hwc);
+ prev_raw_count = local64_read(&hwc->prev_count);
+ } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+ new_raw_count) != prev_raw_count);
+ /*
+ * compute the delta
+ */
+ delta = (new_raw_count - prev_raw_count) &
+ HISI_MAX_PERIOD(hisi_pmu->counter_bits);
+ local64_add(delta, &event->count);
+}
+
+void hisi_uncore_pmu_start(struct perf_event *event, int flags)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
+ if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
+ return;
+
+ WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+ hwc->state = 0;
+ hisi_uncore_pmu_set_event_period(event);
+
+ if (flags & PERF_EF_RELOAD) {
+ u64 prev_raw_count = local64_read(&hwc->prev_count);
+
+ hisi_pmu->ops->write_counter(hisi_pmu, hwc, prev_raw_count);
+ }
+
+ hisi_uncore_pmu_enable_event(event);
+ perf_event_update_userpage(event);
+}
+
+void hisi_uncore_pmu_stop(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ hisi_uncore_pmu_disable_event(event);
+ WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
+ hwc->state |= PERF_HES_STOPPED;
+
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ /* Read hardware counter and update the perf counter statistics */
+ hisi_uncore_pmu_event_update(event);
+ hwc->state |= PERF_HES_UPTODATE;
+}
+
+int hisi_uncore_pmu_add(struct perf_event *event, int flags)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx;
+
+ hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
+
+ /* Get an available counter index for counting */
+ idx = hisi_pmu->ops->get_event_idx(event);
+ if (idx < 0)
+ return idx;
+
+ event->hw.idx = idx;
+ hisi_pmu->pmu_events.hw_events[idx] = event;
+
+ if (flags & PERF_EF_START)
+ hisi_uncore_pmu_start(event, PERF_EF_RELOAD);
+
+ return 0;
+}
+
+void hisi_uncore_pmu_del(struct perf_event *event, int flags)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
+ hisi_uncore_pmu_stop(event, PERF_EF_UPDATE);
+ hisi_uncore_pmu_clear_event_idx(hisi_pmu, hwc->idx);
+ perf_event_update_userpage(event);
+ hisi_pmu->pmu_events.hw_events[hwc->idx] = NULL;
+}
+
+void hisi_uncore_pmu_read(struct perf_event *event)
+{
+ /* Read hardware counter and update the perf counter statistics */
+ hisi_uncore_pmu_event_update(event);
+}
+
+void hisi_uncore_pmu_enable(struct pmu *pmu)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
+ int enabled = bitmap_weight(hisi_pmu->pmu_events.used_mask,
+ hisi_pmu->num_counters);
+
+ if (!enabled)
+ return;
+
+ hisi_pmu->ops->start_counters(hisi_pmu);
+}
+
+void hisi_uncore_pmu_disable(struct pmu *pmu)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
+
+ hisi_pmu->ops->stop_counters(hisi_pmu);
+}
+
+/*
+ * Read Super CPU cluster and CPU cluster ID from MPIDR_EL1.
+ * If multi-threading is supported, SCCL_ID is in MPIDR[aff3] and CCL_ID
+ * is in MPIDR[aff2]; if not, SCCL_ID is in MPIDR[aff2] and CCL_ID is
+ * in MPIDR[aff1]. If this changes in future, this shall be updated.
+ */
+void hisi_read_sccl_and_ccl_id(u32 *sccl_id, u32 *ccl_id)
+{
+ u64 mpidr;
+
+ mpidr = read_cpuid_mpidr();
+ if (mpidr & MPIDR_MT_BITMASK) {
+ if (sccl_id)
+ *sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 3);
+ if (ccl_id)
+ *ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+ } else {
+ if (sccl_id)
+ *sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+ if (ccl_id)
+ *ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+ }
+}
+
+int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct hisi_pmu *hisi_pmu;
+
+ hisi_pmu = hlist_entry_safe(node, struct hisi_pmu, node);
+
+ /*
+ * If the CPU is associated with the PMU, set it in online_cpus of
+ * the PMU.
+ */
+ if (cpumask_test_cpu(cpu, &hisi_pmu->associated_cpus))
+ cpumask_set_cpu(cpu, &hisi_pmu->online_cpus);
+ else
+ return 0;
+
+ /* If another CPU is already managing this PMU, simply return. */
+ if (hisi_pmu->on_cpu != -1)
+ return 0;
+
+ /* Use this CPU in cpumask for event counting */
+ hisi_pmu->on_cpu = cpu;
+
+ /* Overflow interrupt also should use the same CPU */
+ WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(cpu)));
+
+ return 0;
+}
+
+int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct hisi_pmu *hisi_pmu;
+ cpumask_t pmu_online_cpus;
+ unsigned int target;
+
+ hisi_pmu = hlist_entry_safe(node, struct hisi_pmu, node);
+
+ /*
+ * If the CPU is online with the PMU, clear it in online_cpus of
+ * the PMU.
+ */
+ if (!cpumask_test_and_clear_cpu(cpu, &hisi_pmu->online_cpus) ||
+ (hisi_pmu->on_cpu != cpu))
+ return 0;
+
+ hisi_pmu->on_cpu = -1;
+
+ /* Any other CPU associated with the PMU is still online */
+ cpumask_and(&pmu_online_cpus, &hisi_pmu->online_cpus, cpu_online_mask);
+ target = cpumask_any_but(&pmu_online_cpus, cpu);
+ if (target >= nr_cpu_ids)
+ return 0;
+
+ perf_pmu_migrate_context(&hisi_pmu->pmu, cpu, target);
+ /* Use this CPU for event counting */
+ hisi_pmu->on_cpu = target;
+ WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(target)));
+
+ return 0;
+}
+
+/*
+ * Check whether the CPU is associated with this uncore PMU by SCCL_ID,
+ * if true, set the associated cpumask of the uncore PMU.
+ */
+void hisi_uncore_pmu_set_cpumask_by_sccl(void *arg)
+{
+ struct hisi_pmu *hisi_pmu = (struct hisi_pmu *)arg;
+ u32 sccl_id;
+
+ hisi_read_sccl_and_ccl_id(&sccl_id, NULL);
+ if (sccl_id == hisi_pmu->sccl_id)
+ cpumask_set_cpu(smp_processor_id(), &hisi_pmu->associated_cpus);
+}
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.h b/drivers/perf/hisilicon/hisi_uncore_pmu.h
new file mode 100644
index 0000000..4cda9ca
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.h
@@ -0,0 +1,107 @@
+/*
+ * HiSilicon SoC Hardware event counters support
+ *
+ * Copyright (C) 2017 Hisilicon Limited
+ * Author: Anurup M <anurup.m@huawei.com>
+ * Shaokun Zhang <zhangshaokun@hisilicon.com>
+ *
+ * This code is based on the uncore PMUs like arm-cci and arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __HISI_UNCORE_PMU_H__
+#define __HISI_UNCORE_PMU_H__
+
+#include <linux/cpumask.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/perf_event.h>
+#include <linux/types.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "hisi_pmu: " fmt
+
+#define HISI_MAX_COUNTERS 0x10
+#define to_hisi_pmu(p) (container_of(p, struct hisi_pmu, pmu))
+
+#define HISI_PMU_ATTR(_name, _func, _config) \
+ (&((struct dev_ext_attribute[]) { \
+ { __ATTR(_name, 0444, _func, NULL), (void *)_config } \
+ })[0].attr.attr)
+
+#define HISI_PMU_FORMAT_ATTR(_name, _config) \
+ HISI_PMU_ATTR(_name, hisi_format_sysfs_show, (void *)_config)
+#define HISI_PMU_EVENT_ATTR(_name, _config) \
+ HISI_PMU_ATTR(_name, hisi_event_sysfs_show, (unsigned long)_config)
+
+struct hisi_pmu;
+
+struct hisi_uncore_ops {
+ void (*write_evtype)(struct hisi_pmu *, int, u32);
+ int (*get_event_idx)(struct perf_event *);
+ u64 (*read_counter)(struct hisi_pmu *, struct hw_perf_event *);
+ void (*write_counter)(struct hisi_pmu *, struct hw_perf_event *, u64);
+ void (*enable_counter)(struct hisi_pmu *, struct hw_perf_event *);
+ void (*disable_counter)(struct hisi_pmu *, struct hw_perf_event *);
+ void (*enable_counter_int)(struct hisi_pmu *, struct hw_perf_event *);
+ void (*disable_counter_int)(struct hisi_pmu *, struct hw_perf_event *);
+ void (*start_counters)(struct hisi_pmu *);
+ void (*stop_counters)(struct hisi_pmu *);
+};
+
+struct hisi_pmu_hwevents {
+ struct perf_event *hw_events[HISI_MAX_COUNTERS];
+ DECLARE_BITMAP(used_mask, HISI_MAX_COUNTERS);
+};
+
+/* Generic pmu struct for different pmu types */
+struct hisi_pmu {
+ struct pmu pmu;
+ const struct hisi_uncore_ops *ops;
+ struct hisi_pmu_hwevents pmu_events;
+ /*
+ * online_cpus: All online CPUs associated with the PMU
+ * associated_cpus: All CPUs associated with the PMU who is
+ * initialised when probe.
+ */
+ cpumask_t online_cpus, associated_cpus;
+ /* CPU used for counting */
+ int on_cpu;
+ int irq;
+ struct device *dev;
+ struct hlist_node node;
+ u32 sccl_id;
+ u32 ccl_id;
+ /* Hardware information for different pmu types */
+ void __iomem *base;
+ /* the ID of the PMU modules */
+ u32 id;
+ int num_counters;
+ int counter_bits;
+};
+
+int hisi_uncore_pmu_counter_valid(struct hisi_pmu *hisi_pmu, int idx);
+int hisi_uncore_pmu_get_event_idx(struct perf_event *event);
+void hisi_uncore_pmu_read(struct perf_event *event);
+int hisi_uncore_pmu_add(struct perf_event *event, int flags);
+void hisi_uncore_pmu_del(struct perf_event *event, int flags);
+void hisi_uncore_pmu_start(struct perf_event *event, int flags);
+void hisi_uncore_pmu_stop(struct perf_event *event, int flags);
+void hisi_uncore_pmu_set_event_period(struct perf_event *event);
+void hisi_uncore_pmu_event_update(struct perf_event *event);
+int hisi_uncore_pmu_event_init(struct perf_event *event);
+void hisi_uncore_pmu_enable(struct pmu *pmu);
+void hisi_uncore_pmu_disable(struct pmu *pmu);
+ssize_t hisi_event_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf);
+ssize_t hisi_format_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf);
+ssize_t hisi_cpumask_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf);
+void hisi_read_sccl_and_ccl_id(u32 *sccl_id, u32 *ccl_id);
+int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node);
+int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node);
+void hisi_uncore_pmu_set_cpumask_by_sccl(void *arg);
+#endif /* __HISI_UNCORE_PMU_H__ */
--
1.9.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver
2017-08-22 8:07 ` Shaokun Zhang
@ 2017-08-22 8:07 ` Shaokun Zhang
-1 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: mark.rutland, will.deacon
Cc: jonathan.cameron, linux-arm-kernel, linux-kernel, linux-doc,
linuxarm, Shaokun Zhang, Anurup M
This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each
L3C has own control, counter and interrupt registers and is an separate
PMU. For each L3C PMU, it has 8-programable counters and each counter
is free-running. Interrupt is supported to handle counter (48-bits)
overflow.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 482 +++++++++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
3 files changed, 484 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
index 2783bb3..4a3d3e6 100644
--- a/drivers/perf/hisilicon/Makefile
+++ b/drivers/perf/hisilicon/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
new file mode 100644
index 0000000..db96e7c
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
@@ -0,0 +1,482 @@
+/*
+ * HiSilicon SoC L3C uncore Hardware event counters support
+ *
+ * Copyright (C) 2017 Hisilicon Limited
+ * Author: Anurup M <anurup.m@huawei.com>
+ * Shaokun Zhang <zhangshaokun@hisilicon.com>
+ *
+ * This code is based on the uncore PMUs like arm-cci and arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/acpi.h>
+#include <linux/bug.h>
+#include <linux/cpuhotplug.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/list.h>
+#include <linux/platform_device.h>
+#include <linux/smp.h>
+
+#include "hisi_uncore_pmu.h"
+
+/* L3C register definition */
+#define L3C_PERF_CTRL 0x0408
+#define L3C_INT_MASK 0x0800
+#define L3C_INT_STATUS 0x0808
+#define L3C_INT_CLEAR 0x080c
+#define L3C_EVENT_CTRL 0x1c00
+#define L3C_EVENT_TYPE0 0x1d00
+/*
+ * Each counter is 48-bits and [48:63] are reserved
+ * which are Read-As-Zero and Writes-Ignored.
+ */
+#define L3C_CNTR0_LOWER 0x1e00
+
+/* L3C has 8-counters */
+#define L3C_NR_COUNTERS 0x8
+
+#define L3C_PERF_CTRL_EN 0x20000
+#define L3C_EVTYPE_NONE 0xff
+
+/*
+ * Select the counter register offset using the counter index
+ */
+static u32 hisi_l3c_pmu_get_counter_offset(int cntr_idx)
+{
+ return (L3C_CNTR0_LOWER + (cntr_idx * 8));
+}
+
+static u64 hisi_l3c_pmu_read_counter(struct hisi_pmu *l3c_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 idx = hwc->idx;
+
+ if (!hisi_uncore_pmu_counter_valid(l3c_pmu, idx)) {
+ dev_err(l3c_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return 0;
+ }
+
+ /* Read 64-bits and the upper 16 bits are RAZ */
+ return readq(l3c_pmu->base + hisi_l3c_pmu_get_counter_offset(idx));
+}
+
+static void hisi_l3c_pmu_write_counter(struct hisi_pmu *l3c_pmu,
+ struct hw_perf_event *hwc, u64 val)
+{
+ u32 idx = hwc->idx;
+
+ if (!hisi_uncore_pmu_counter_valid(l3c_pmu, idx)) {
+ dev_err(l3c_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ /* Write 64-bits and the upper 16 bits are WI */
+ writeq(val, l3c_pmu->base + hisi_l3c_pmu_get_counter_offset(idx));
+}
+
+static void hisi_l3c_pmu_write_evtype(struct hisi_pmu *l3c_pmu, int idx,
+ u32 type)
+{
+ u32 reg, reg_idx, shift, val;
+
+ /*
+ * Select the appropriate event select register(L3C_EVENT_TYPE0/1).
+ * There are 2 event select registers for the 8 hardware counters.
+ * Event code is 8-bits and for the former 4 hardware counters,
+ * L3C_EVENT_TYPE0 is chosen. For the latter 4 hardware counters,
+ * L3C_EVENT_TYPE1 is chosen.
+ */
+ reg = L3C_EVENT_TYPE0 + (idx / 4) * 4;
+ reg_idx = idx % 4;
+ shift = 8 * reg_idx;
+
+ /* Write event code to L3C_EVENT_TYPEx Register */
+ val = readl(l3c_pmu->base + reg);
+ val &= ~(L3C_EVTYPE_NONE << shift);
+ val |= (type << shift);
+ writel(val, l3c_pmu->base + reg);
+}
+
+static void hisi_l3c_pmu_start_counters(struct hisi_pmu *l3c_pmu)
+{
+ u32 val;
+
+ /*
+ * Set perf_enable bit in L3C_PERF_CTRL register to start counting
+ * for all enabled counters.
+ */
+ val = readl(l3c_pmu->base + L3C_PERF_CTRL);
+ val |= L3C_PERF_CTRL_EN;
+ writel(val, l3c_pmu->base + L3C_PERF_CTRL);
+}
+
+static void hisi_l3c_pmu_stop_counters(struct hisi_pmu *l3c_pmu)
+{
+ u32 val;
+
+ /*
+ * Clear perf_enable bit in L3C_PERF_CTRL register to stop counting
+ * for all enabled counters.
+ */
+ val = readl(l3c_pmu->base + L3C_PERF_CTRL);
+ val &= ~(L3C_PERF_CTRL_EN);
+ writel(val, l3c_pmu->base + L3C_PERF_CTRL);
+}
+
+static void hisi_l3c_pmu_enable_counter(struct hisi_pmu *l3c_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Enable counter index in L3C_EVENT_CTRL register */
+ val = readl(l3c_pmu->base + L3C_EVENT_CTRL);
+ val |= (1 << hwc->idx);
+ writel(val, l3c_pmu->base + L3C_EVENT_CTRL);
+}
+
+static void hisi_l3c_pmu_disable_counter(struct hisi_pmu *l3c_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Clear counter index in L3C_EVENT_CTRL register */
+ val = readl(l3c_pmu->base + L3C_EVENT_CTRL);
+ val &= ~(1 << hwc->idx);
+ writel(val, l3c_pmu->base + L3C_EVENT_CTRL);
+}
+
+static void hisi_l3c_pmu_enable_counter_int(struct hisi_pmu *l3c_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ val = readl(l3c_pmu->base + L3C_INT_MASK);
+ /* Write 0 to enable interrupt */
+ val &= ~(1 << hwc->idx);
+ writel(val, l3c_pmu->base + L3C_INT_MASK);
+}
+
+static void hisi_l3c_pmu_disable_counter_int(struct hisi_pmu *l3c_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ val = readl(l3c_pmu->base + L3C_INT_MASK);
+ /* Write 1 to mask interrupt */
+ val |= (1 << hwc->idx);
+ writel(val, l3c_pmu->base + L3C_INT_MASK);
+}
+
+static irqreturn_t hisi_l3c_pmu_isr(int irq, void *dev_id)
+{
+ struct hisi_pmu *l3c_pmu = dev_id;
+ struct perf_event *event;
+ unsigned long overflown;
+ int idx;
+
+ /* Read L3C_INT_STATUS register */
+ overflown = readl(l3c_pmu->base + L3C_INT_STATUS);
+ if (!overflown)
+ return IRQ_NONE;
+
+ /*
+ * Find the counter index which overflowed if the bit was set
+ * and handle it.
+ */
+ for_each_set_bit(idx, &overflown, L3C_NR_COUNTERS) {
+ /* Write 1 to clear the IRQ status flag */
+ writel((1 << idx), l3c_pmu->base + L3C_INT_CLEAR);
+
+ /* Get the corresponding event struct */
+ event = l3c_pmu->pmu_events.hw_events[idx];
+ if (!event)
+ continue;
+
+ hisi_uncore_pmu_event_update(event);
+ hisi_uncore_pmu_set_event_period(event);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int hisi_l3c_pmu_init_irq(struct hisi_pmu *l3c_pmu,
+ struct platform_device *pdev)
+{
+ int irq, ret;
+
+ /* Read and init IRQ */
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "L3C PMU get irq fail; irq:%d\n", irq);
+ return irq;
+ }
+
+ ret = devm_request_irq(&pdev->dev, irq, hisi_l3c_pmu_isr,
+ IRQF_NOBALANCING | IRQF_NO_THREAD,
+ dev_name(&pdev->dev), l3c_pmu);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "Fail to request IRQ:%d ret:%d\n", irq, ret);
+ return ret;
+ }
+
+ l3c_pmu->irq = irq;
+
+ return 0;
+}
+
+/*
+ * Check whether the CPU is associated with this L3C PMU by SCCL_ID
+ * and CCL_ID, if true, set the associated cpumask of the L3C PMU.
+ */
+static void hisi_l3c_pmu_set_cpumask_by_ccl(void *arg)
+{
+ struct hisi_pmu *l3c_pmu = (struct hisi_pmu *)arg;
+ u32 ccl_id, sccl_id;
+
+ hisi_read_sccl_and_ccl_id(&sccl_id, &ccl_id);
+ if (sccl_id == l3c_pmu->sccl_id && ccl_id == l3c_pmu->ccl_id)
+ cpumask_set_cpu(smp_processor_id(), &l3c_pmu->associated_cpus);
+}
+
+static const struct acpi_device_id hisi_l3c_pmu_acpi_match[] = {
+ { "HISI0213", },
+ {},
+};
+MODULE_DEVICE_TABLE(acpi, hisi_l3c_pmu_acpi_match);
+
+static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
+ struct hisi_pmu *l3c_pmu)
+{
+ unsigned long long id;
+ struct resource *res;
+ acpi_status status;
+ int cpu;
+
+ status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
+ "_UID", NULL, &id);
+ if (ACPI_FAILURE(status))
+ return -EINVAL;
+
+ l3c_pmu->id = id;
+
+ /*
+ * Use the SCCL_ID and CCL_ID to identify the L3C PMU, while
+ * SCCL_ID is in MPIDR[aff2] and CCL_ID is in MPIDR[aff1].
+ */
+ if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
+ &l3c_pmu->sccl_id)) {
+ dev_err(&pdev->dev, "Can not read l3c sccl-id!\n");
+ return -EINVAL;
+ }
+
+ if (device_property_read_u32(&pdev->dev, "hisilicon,ccl-id",
+ &l3c_pmu->ccl_id)) {
+ dev_err(&pdev->dev, "Can not read l3c ccl-id!\n");
+ return -EINVAL;
+ }
+
+ /* Initialise the associated cpumask of the PMU */
+ for_each_present_cpu(cpu)
+ smp_call_function_single(cpu, hisi_l3c_pmu_set_cpumask_by_ccl,
+ (void *)l3c_pmu, 1);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ l3c_pmu->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(l3c_pmu->base)) {
+ dev_err(&pdev->dev, "ioremap failed for l3c_pmu resource\n");
+ return PTR_ERR(l3c_pmu->base);
+ }
+
+ return 0;
+}
+
+static struct attribute *hisi_l3c_pmu_format_attr[] = {
+ HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
+ NULL,
+};
+
+static const struct attribute_group hisi_l3c_pmu_format_group = {
+ .name = "format",
+ .attrs = hisi_l3c_pmu_format_attr,
+};
+
+static struct attribute *hisi_l3c_pmu_events_attr[] = {
+ HISI_PMU_EVENT_ATTR(rd_cpipe, 0x00),
+ HISI_PMU_EVENT_ATTR(wr_cpipe, 0x01),
+ HISI_PMU_EVENT_ATTR(rd_hit_cpipe, 0x02),
+ HISI_PMU_EVENT_ATTR(wr_hit_cpipe, 0x03),
+ HISI_PMU_EVENT_ATTR(victim_num, 0x04),
+ HISI_PMU_EVENT_ATTR(rd_spipe, 0x20),
+ HISI_PMU_EVENT_ATTR(wr_spipe, 0x21),
+ HISI_PMU_EVENT_ATTR(rd_hit_spipe, 0x22),
+ HISI_PMU_EVENT_ATTR(wr_hit_spipe, 0x23),
+ HISI_PMU_EVENT_ATTR(back_invalid, 0x29),
+ HISI_PMU_EVENT_ATTR(retry_cpu, 0x40),
+ HISI_PMU_EVENT_ATTR(retry_ring, 0x41),
+ HISI_PMU_EVENT_ATTR(prefetch_drop, 0x42),
+ NULL,
+};
+
+static const struct attribute_group hisi_l3c_pmu_events_group = {
+ .name = "events",
+ .attrs = hisi_l3c_pmu_events_attr,
+};
+
+static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
+
+static struct attribute *hisi_l3c_pmu_cpumask_attrs[] = {
+ &dev_attr_cpumask.attr,
+ NULL,
+};
+
+static const struct attribute_group hisi_l3c_pmu_cpumask_attr_group = {
+ .attrs = hisi_l3c_pmu_cpumask_attrs,
+};
+
+static const struct attribute_group *hisi_l3c_pmu_attr_groups[] = {
+ &hisi_l3c_pmu_format_group,
+ &hisi_l3c_pmu_events_group,
+ &hisi_l3c_pmu_cpumask_attr_group,
+ NULL,
+};
+
+static const struct hisi_uncore_ops hisi_uncore_l3c_ops = {
+ .write_evtype = hisi_l3c_pmu_write_evtype,
+ .get_event_idx = hisi_uncore_pmu_get_event_idx,
+ .start_counters = hisi_l3c_pmu_start_counters,
+ .stop_counters = hisi_l3c_pmu_stop_counters,
+ .enable_counter = hisi_l3c_pmu_enable_counter,
+ .disable_counter = hisi_l3c_pmu_disable_counter,
+ .enable_counter_int = hisi_l3c_pmu_enable_counter_int,
+ .disable_counter_int = hisi_l3c_pmu_disable_counter_int,
+ .write_counter = hisi_l3c_pmu_write_counter,
+ .read_counter = hisi_l3c_pmu_read_counter,
+};
+
+static int hisi_l3c_pmu_dev_probe(struct platform_device *pdev,
+ struct hisi_pmu *l3c_pmu)
+{
+ int ret;
+
+ ret = hisi_l3c_pmu_init_data(pdev, l3c_pmu);
+ if (ret)
+ return ret;
+
+ ret = hisi_l3c_pmu_init_irq(l3c_pmu, pdev);
+ if (ret)
+ return ret;
+
+ l3c_pmu->num_counters = L3C_NR_COUNTERS;
+ l3c_pmu->counter_bits = 48;
+ l3c_pmu->ops = &hisi_uncore_l3c_ops;
+ l3c_pmu->dev = &pdev->dev;
+ l3c_pmu->on_cpu = -1;
+
+ return 0;
+}
+
+static int hisi_l3c_pmu_probe(struct platform_device *pdev)
+{
+ struct hisi_pmu *l3c_pmu;
+ char *name;
+ int ret;
+
+ l3c_pmu = devm_kzalloc(&pdev->dev, sizeof(*l3c_pmu), GFP_KERNEL);
+ if (!l3c_pmu)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, l3c_pmu);
+
+ ret = hisi_l3c_pmu_dev_probe(pdev, l3c_pmu);
+ if (ret)
+ return ret;
+
+ ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
+ &l3c_pmu->node);
+ if (ret) {
+ dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
+ return ret;
+ }
+
+ name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%u_l3c%u",
+ l3c_pmu->sccl_id, l3c_pmu->id);
+ l3c_pmu->pmu = (struct pmu) {
+ .name = name,
+ .task_ctx_nr = perf_invalid_context,
+ .event_init = hisi_uncore_pmu_event_init,
+ .pmu_enable = hisi_uncore_pmu_enable,
+ .pmu_disable = hisi_uncore_pmu_disable,
+ .add = hisi_uncore_pmu_add,
+ .del = hisi_uncore_pmu_del,
+ .start = hisi_uncore_pmu_start,
+ .stop = hisi_uncore_pmu_stop,
+ .read = hisi_uncore_pmu_read,
+ .attr_groups = hisi_l3c_pmu_attr_groups,
+ };
+
+ ret = perf_pmu_register(&l3c_pmu->pmu, name, -1);
+ if (ret) {
+ dev_err(l3c_pmu->dev, "L3C PMU register failed!\n");
+ cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
+ &l3c_pmu->node);
+ }
+
+ return ret;
+}
+
+static int hisi_l3c_pmu_remove(struct platform_device *pdev)
+{
+ struct hisi_pmu *l3c_pmu = platform_get_drvdata(pdev);
+
+ perf_pmu_unregister(&l3c_pmu->pmu);
+ cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
+ &l3c_pmu->node);
+
+ return 0;
+}
+
+static struct platform_driver hisi_l3c_pmu_driver = {
+ .driver = {
+ .name = "hisi_l3c_pmu",
+ .acpi_match_table = ACPI_PTR(hisi_l3c_pmu_acpi_match),
+ },
+ .probe = hisi_l3c_pmu_probe,
+ .remove = hisi_l3c_pmu_remove,
+};
+
+static int __init hisi_l3c_pmu_module_init(void)
+{
+ int ret;
+
+ ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
+ "AP_PERF_ARM_HISI_L3_ONLINE",
+ hisi_uncore_pmu_online_cpu,
+ hisi_uncore_pmu_offline_cpu);
+ if (ret) {
+ pr_err("L3C PMU: Error setup hotplug, ret = %d\n", ret);
+ return ret;
+ }
+
+ ret = platform_driver_register(&hisi_l3c_pmu_driver);
+ if (ret)
+ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE);
+
+ return ret;
+}
+module_init(hisi_l3c_pmu_module_init);
+
+static void __exit hisi_l3c_pmu_module_exit(void)
+{
+ platform_driver_unregister(&hisi_l3c_pmu_driver);
+ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE);
+}
+module_exit(hisi_l3c_pmu_module_exit);
+
+MODULE_DESCRIPTION("HiSilicon SoC L3C uncore PMU driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Anurup M <anurup.m@huawei.com>");
+MODULE_AUTHOR("Shaokun Zhang <zhangshaokun@hisilicon.com>");
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 82b30e6..6858942 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -134,6 +134,7 @@ enum cpuhp_state {
CPUHP_AP_PERF_S390_SF_ONLINE,
CPUHP_AP_PERF_ARM_CCI_ONLINE,
CPUHP_AP_PERF_ARM_CCN_ONLINE,
+ CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
CPUHP_AP_PERF_ARM_L2X0_ONLINE,
CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE,
CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,
--
1.9.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver
@ 2017-08-22 8:07 ` Shaokun Zhang
0 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each
L3C has own control, counter and interrupt registers and is an separate
PMU. For each L3C PMU, it has 8-programable counters and each counter
is free-running. Interrupt is supported to handle counter (48-bits)
overflow.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 482 +++++++++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
3 files changed, 484 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
index 2783bb3..4a3d3e6 100644
--- a/drivers/perf/hisilicon/Makefile
+++ b/drivers/perf/hisilicon/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
new file mode 100644
index 0000000..db96e7c
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
@@ -0,0 +1,482 @@
+/*
+ * HiSilicon SoC L3C uncore Hardware event counters support
+ *
+ * Copyright (C) 2017 Hisilicon Limited
+ * Author: Anurup M <anurup.m@huawei.com>
+ * Shaokun Zhang <zhangshaokun@hisilicon.com>
+ *
+ * This code is based on the uncore PMUs like arm-cci and arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/acpi.h>
+#include <linux/bug.h>
+#include <linux/cpuhotplug.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/list.h>
+#include <linux/platform_device.h>
+#include <linux/smp.h>
+
+#include "hisi_uncore_pmu.h"
+
+/* L3C register definition */
+#define L3C_PERF_CTRL 0x0408
+#define L3C_INT_MASK 0x0800
+#define L3C_INT_STATUS 0x0808
+#define L3C_INT_CLEAR 0x080c
+#define L3C_EVENT_CTRL 0x1c00
+#define L3C_EVENT_TYPE0 0x1d00
+/*
+ * Each counter is 48-bits and [48:63] are reserved
+ * which are Read-As-Zero and Writes-Ignored.
+ */
+#define L3C_CNTR0_LOWER 0x1e00
+
+/* L3C has 8-counters */
+#define L3C_NR_COUNTERS 0x8
+
+#define L3C_PERF_CTRL_EN 0x20000
+#define L3C_EVTYPE_NONE 0xff
+
+/*
+ * Select the counter register offset using the counter index
+ */
+static u32 hisi_l3c_pmu_get_counter_offset(int cntr_idx)
+{
+ return (L3C_CNTR0_LOWER + (cntr_idx * 8));
+}
+
+static u64 hisi_l3c_pmu_read_counter(struct hisi_pmu *l3c_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 idx = hwc->idx;
+
+ if (!hisi_uncore_pmu_counter_valid(l3c_pmu, idx)) {
+ dev_err(l3c_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return 0;
+ }
+
+ /* Read 64-bits and the upper 16 bits are RAZ */
+ return readq(l3c_pmu->base + hisi_l3c_pmu_get_counter_offset(idx));
+}
+
+static void hisi_l3c_pmu_write_counter(struct hisi_pmu *l3c_pmu,
+ struct hw_perf_event *hwc, u64 val)
+{
+ u32 idx = hwc->idx;
+
+ if (!hisi_uncore_pmu_counter_valid(l3c_pmu, idx)) {
+ dev_err(l3c_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ /* Write 64-bits and the upper 16 bits are WI */
+ writeq(val, l3c_pmu->base + hisi_l3c_pmu_get_counter_offset(idx));
+}
+
+static void hisi_l3c_pmu_write_evtype(struct hisi_pmu *l3c_pmu, int idx,
+ u32 type)
+{
+ u32 reg, reg_idx, shift, val;
+
+ /*
+ * Select the appropriate event select register(L3C_EVENT_TYPE0/1).
+ * There are 2 event select registers for the 8 hardware counters.
+ * Event code is 8-bits and for the former 4 hardware counters,
+ * L3C_EVENT_TYPE0 is chosen. For the latter 4 hardware counters,
+ * L3C_EVENT_TYPE1 is chosen.
+ */
+ reg = L3C_EVENT_TYPE0 + (idx / 4) * 4;
+ reg_idx = idx % 4;
+ shift = 8 * reg_idx;
+
+ /* Write event code to L3C_EVENT_TYPEx Register */
+ val = readl(l3c_pmu->base + reg);
+ val &= ~(L3C_EVTYPE_NONE << shift);
+ val |= (type << shift);
+ writel(val, l3c_pmu->base + reg);
+}
+
+static void hisi_l3c_pmu_start_counters(struct hisi_pmu *l3c_pmu)
+{
+ u32 val;
+
+ /*
+ * Set perf_enable bit in L3C_PERF_CTRL register to start counting
+ * for all enabled counters.
+ */
+ val = readl(l3c_pmu->base + L3C_PERF_CTRL);
+ val |= L3C_PERF_CTRL_EN;
+ writel(val, l3c_pmu->base + L3C_PERF_CTRL);
+}
+
+static void hisi_l3c_pmu_stop_counters(struct hisi_pmu *l3c_pmu)
+{
+ u32 val;
+
+ /*
+ * Clear perf_enable bit in L3C_PERF_CTRL register to stop counting
+ * for all enabled counters.
+ */
+ val = readl(l3c_pmu->base + L3C_PERF_CTRL);
+ val &= ~(L3C_PERF_CTRL_EN);
+ writel(val, l3c_pmu->base + L3C_PERF_CTRL);
+}
+
+static void hisi_l3c_pmu_enable_counter(struct hisi_pmu *l3c_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Enable counter index in L3C_EVENT_CTRL register */
+ val = readl(l3c_pmu->base + L3C_EVENT_CTRL);
+ val |= (1 << hwc->idx);
+ writel(val, l3c_pmu->base + L3C_EVENT_CTRL);
+}
+
+static void hisi_l3c_pmu_disable_counter(struct hisi_pmu *l3c_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Clear counter index in L3C_EVENT_CTRL register */
+ val = readl(l3c_pmu->base + L3C_EVENT_CTRL);
+ val &= ~(1 << hwc->idx);
+ writel(val, l3c_pmu->base + L3C_EVENT_CTRL);
+}
+
+static void hisi_l3c_pmu_enable_counter_int(struct hisi_pmu *l3c_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ val = readl(l3c_pmu->base + L3C_INT_MASK);
+ /* Write 0 to enable interrupt */
+ val &= ~(1 << hwc->idx);
+ writel(val, l3c_pmu->base + L3C_INT_MASK);
+}
+
+static void hisi_l3c_pmu_disable_counter_int(struct hisi_pmu *l3c_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ val = readl(l3c_pmu->base + L3C_INT_MASK);
+ /* Write 1 to mask interrupt */
+ val |= (1 << hwc->idx);
+ writel(val, l3c_pmu->base + L3C_INT_MASK);
+}
+
+static irqreturn_t hisi_l3c_pmu_isr(int irq, void *dev_id)
+{
+ struct hisi_pmu *l3c_pmu = dev_id;
+ struct perf_event *event;
+ unsigned long overflown;
+ int idx;
+
+ /* Read L3C_INT_STATUS register */
+ overflown = readl(l3c_pmu->base + L3C_INT_STATUS);
+ if (!overflown)
+ return IRQ_NONE;
+
+ /*
+ * Find the counter index which overflowed if the bit was set
+ * and handle it.
+ */
+ for_each_set_bit(idx, &overflown, L3C_NR_COUNTERS) {
+ /* Write 1 to clear the IRQ status flag */
+ writel((1 << idx), l3c_pmu->base + L3C_INT_CLEAR);
+
+ /* Get the corresponding event struct */
+ event = l3c_pmu->pmu_events.hw_events[idx];
+ if (!event)
+ continue;
+
+ hisi_uncore_pmu_event_update(event);
+ hisi_uncore_pmu_set_event_period(event);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int hisi_l3c_pmu_init_irq(struct hisi_pmu *l3c_pmu,
+ struct platform_device *pdev)
+{
+ int irq, ret;
+
+ /* Read and init IRQ */
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "L3C PMU get irq fail; irq:%d\n", irq);
+ return irq;
+ }
+
+ ret = devm_request_irq(&pdev->dev, irq, hisi_l3c_pmu_isr,
+ IRQF_NOBALANCING | IRQF_NO_THREAD,
+ dev_name(&pdev->dev), l3c_pmu);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "Fail to request IRQ:%d ret:%d\n", irq, ret);
+ return ret;
+ }
+
+ l3c_pmu->irq = irq;
+
+ return 0;
+}
+
+/*
+ * Check whether the CPU is associated with this L3C PMU by SCCL_ID
+ * and CCL_ID, if true, set the associated cpumask of the L3C PMU.
+ */
+static void hisi_l3c_pmu_set_cpumask_by_ccl(void *arg)
+{
+ struct hisi_pmu *l3c_pmu = (struct hisi_pmu *)arg;
+ u32 ccl_id, sccl_id;
+
+ hisi_read_sccl_and_ccl_id(&sccl_id, &ccl_id);
+ if (sccl_id == l3c_pmu->sccl_id && ccl_id == l3c_pmu->ccl_id)
+ cpumask_set_cpu(smp_processor_id(), &l3c_pmu->associated_cpus);
+}
+
+static const struct acpi_device_id hisi_l3c_pmu_acpi_match[] = {
+ { "HISI0213", },
+ {},
+};
+MODULE_DEVICE_TABLE(acpi, hisi_l3c_pmu_acpi_match);
+
+static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
+ struct hisi_pmu *l3c_pmu)
+{
+ unsigned long long id;
+ struct resource *res;
+ acpi_status status;
+ int cpu;
+
+ status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
+ "_UID", NULL, &id);
+ if (ACPI_FAILURE(status))
+ return -EINVAL;
+
+ l3c_pmu->id = id;
+
+ /*
+ * Use the SCCL_ID and CCL_ID to identify the L3C PMU, while
+ * SCCL_ID is in MPIDR[aff2] and CCL_ID is in MPIDR[aff1].
+ */
+ if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
+ &l3c_pmu->sccl_id)) {
+ dev_err(&pdev->dev, "Can not read l3c sccl-id!\n");
+ return -EINVAL;
+ }
+
+ if (device_property_read_u32(&pdev->dev, "hisilicon,ccl-id",
+ &l3c_pmu->ccl_id)) {
+ dev_err(&pdev->dev, "Can not read l3c ccl-id!\n");
+ return -EINVAL;
+ }
+
+ /* Initialise the associated cpumask of the PMU */
+ for_each_present_cpu(cpu)
+ smp_call_function_single(cpu, hisi_l3c_pmu_set_cpumask_by_ccl,
+ (void *)l3c_pmu, 1);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ l3c_pmu->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(l3c_pmu->base)) {
+ dev_err(&pdev->dev, "ioremap failed for l3c_pmu resource\n");
+ return PTR_ERR(l3c_pmu->base);
+ }
+
+ return 0;
+}
+
+static struct attribute *hisi_l3c_pmu_format_attr[] = {
+ HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
+ NULL,
+};
+
+static const struct attribute_group hisi_l3c_pmu_format_group = {
+ .name = "format",
+ .attrs = hisi_l3c_pmu_format_attr,
+};
+
+static struct attribute *hisi_l3c_pmu_events_attr[] = {
+ HISI_PMU_EVENT_ATTR(rd_cpipe, 0x00),
+ HISI_PMU_EVENT_ATTR(wr_cpipe, 0x01),
+ HISI_PMU_EVENT_ATTR(rd_hit_cpipe, 0x02),
+ HISI_PMU_EVENT_ATTR(wr_hit_cpipe, 0x03),
+ HISI_PMU_EVENT_ATTR(victim_num, 0x04),
+ HISI_PMU_EVENT_ATTR(rd_spipe, 0x20),
+ HISI_PMU_EVENT_ATTR(wr_spipe, 0x21),
+ HISI_PMU_EVENT_ATTR(rd_hit_spipe, 0x22),
+ HISI_PMU_EVENT_ATTR(wr_hit_spipe, 0x23),
+ HISI_PMU_EVENT_ATTR(back_invalid, 0x29),
+ HISI_PMU_EVENT_ATTR(retry_cpu, 0x40),
+ HISI_PMU_EVENT_ATTR(retry_ring, 0x41),
+ HISI_PMU_EVENT_ATTR(prefetch_drop, 0x42),
+ NULL,
+};
+
+static const struct attribute_group hisi_l3c_pmu_events_group = {
+ .name = "events",
+ .attrs = hisi_l3c_pmu_events_attr,
+};
+
+static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
+
+static struct attribute *hisi_l3c_pmu_cpumask_attrs[] = {
+ &dev_attr_cpumask.attr,
+ NULL,
+};
+
+static const struct attribute_group hisi_l3c_pmu_cpumask_attr_group = {
+ .attrs = hisi_l3c_pmu_cpumask_attrs,
+};
+
+static const struct attribute_group *hisi_l3c_pmu_attr_groups[] = {
+ &hisi_l3c_pmu_format_group,
+ &hisi_l3c_pmu_events_group,
+ &hisi_l3c_pmu_cpumask_attr_group,
+ NULL,
+};
+
+static const struct hisi_uncore_ops hisi_uncore_l3c_ops = {
+ .write_evtype = hisi_l3c_pmu_write_evtype,
+ .get_event_idx = hisi_uncore_pmu_get_event_idx,
+ .start_counters = hisi_l3c_pmu_start_counters,
+ .stop_counters = hisi_l3c_pmu_stop_counters,
+ .enable_counter = hisi_l3c_pmu_enable_counter,
+ .disable_counter = hisi_l3c_pmu_disable_counter,
+ .enable_counter_int = hisi_l3c_pmu_enable_counter_int,
+ .disable_counter_int = hisi_l3c_pmu_disable_counter_int,
+ .write_counter = hisi_l3c_pmu_write_counter,
+ .read_counter = hisi_l3c_pmu_read_counter,
+};
+
+static int hisi_l3c_pmu_dev_probe(struct platform_device *pdev,
+ struct hisi_pmu *l3c_pmu)
+{
+ int ret;
+
+ ret = hisi_l3c_pmu_init_data(pdev, l3c_pmu);
+ if (ret)
+ return ret;
+
+ ret = hisi_l3c_pmu_init_irq(l3c_pmu, pdev);
+ if (ret)
+ return ret;
+
+ l3c_pmu->num_counters = L3C_NR_COUNTERS;
+ l3c_pmu->counter_bits = 48;
+ l3c_pmu->ops = &hisi_uncore_l3c_ops;
+ l3c_pmu->dev = &pdev->dev;
+ l3c_pmu->on_cpu = -1;
+
+ return 0;
+}
+
+static int hisi_l3c_pmu_probe(struct platform_device *pdev)
+{
+ struct hisi_pmu *l3c_pmu;
+ char *name;
+ int ret;
+
+ l3c_pmu = devm_kzalloc(&pdev->dev, sizeof(*l3c_pmu), GFP_KERNEL);
+ if (!l3c_pmu)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, l3c_pmu);
+
+ ret = hisi_l3c_pmu_dev_probe(pdev, l3c_pmu);
+ if (ret)
+ return ret;
+
+ ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
+ &l3c_pmu->node);
+ if (ret) {
+ dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
+ return ret;
+ }
+
+ name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%u_l3c%u",
+ l3c_pmu->sccl_id, l3c_pmu->id);
+ l3c_pmu->pmu = (struct pmu) {
+ .name = name,
+ .task_ctx_nr = perf_invalid_context,
+ .event_init = hisi_uncore_pmu_event_init,
+ .pmu_enable = hisi_uncore_pmu_enable,
+ .pmu_disable = hisi_uncore_pmu_disable,
+ .add = hisi_uncore_pmu_add,
+ .del = hisi_uncore_pmu_del,
+ .start = hisi_uncore_pmu_start,
+ .stop = hisi_uncore_pmu_stop,
+ .read = hisi_uncore_pmu_read,
+ .attr_groups = hisi_l3c_pmu_attr_groups,
+ };
+
+ ret = perf_pmu_register(&l3c_pmu->pmu, name, -1);
+ if (ret) {
+ dev_err(l3c_pmu->dev, "L3C PMU register failed!\n");
+ cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
+ &l3c_pmu->node);
+ }
+
+ return ret;
+}
+
+static int hisi_l3c_pmu_remove(struct platform_device *pdev)
+{
+ struct hisi_pmu *l3c_pmu = platform_get_drvdata(pdev);
+
+ perf_pmu_unregister(&l3c_pmu->pmu);
+ cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
+ &l3c_pmu->node);
+
+ return 0;
+}
+
+static struct platform_driver hisi_l3c_pmu_driver = {
+ .driver = {
+ .name = "hisi_l3c_pmu",
+ .acpi_match_table = ACPI_PTR(hisi_l3c_pmu_acpi_match),
+ },
+ .probe = hisi_l3c_pmu_probe,
+ .remove = hisi_l3c_pmu_remove,
+};
+
+static int __init hisi_l3c_pmu_module_init(void)
+{
+ int ret;
+
+ ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
+ "AP_PERF_ARM_HISI_L3_ONLINE",
+ hisi_uncore_pmu_online_cpu,
+ hisi_uncore_pmu_offline_cpu);
+ if (ret) {
+ pr_err("L3C PMU: Error setup hotplug, ret = %d\n", ret);
+ return ret;
+ }
+
+ ret = platform_driver_register(&hisi_l3c_pmu_driver);
+ if (ret)
+ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE);
+
+ return ret;
+}
+module_init(hisi_l3c_pmu_module_init);
+
+static void __exit hisi_l3c_pmu_module_exit(void)
+{
+ platform_driver_unregister(&hisi_l3c_pmu_driver);
+ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE);
+}
+module_exit(hisi_l3c_pmu_module_exit);
+
+MODULE_DESCRIPTION("HiSilicon SoC L3C uncore PMU driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Anurup M <anurup.m@huawei.com>");
+MODULE_AUTHOR("Shaokun Zhang <zhangshaokun@hisilicon.com>");
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 82b30e6..6858942 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -134,6 +134,7 @@ enum cpuhp_state {
CPUHP_AP_PERF_S390_SF_ONLINE,
CPUHP_AP_PERF_ARM_CCI_ONLINE,
CPUHP_AP_PERF_ARM_CCN_ONLINE,
+ CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
CPUHP_AP_PERF_ARM_L2X0_ONLINE,
CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE,
CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,
--
1.9.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver
2017-08-22 8:07 ` Shaokun Zhang
@ 2017-08-22 8:07 ` Shaokun Zhang
-1 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: mark.rutland, will.deacon
Cc: jonathan.cameron, linux-arm-kernel, linux-kernel, linux-doc,
linuxarm, Shaokun Zhang, Anurup M
L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
SoC. This patch adds support for HHA PMU driver, Each HHA has own
control, counter and interrupt registers and is an separate PMU. For
each HHA PMU, it has 16-programable counters and each counter is
free-running. Interrupt is supported to handle counter (48-bits)
overflow.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 477 +++++++++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
3 files changed, 479 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
index 4a3d3e6..a72afe8 100644
--- a/drivers/perf/hisilicon/Makefile
+++ b/drivers/perf/hisilicon/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o hisi_uncore_hha_pmu.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
new file mode 100644
index 0000000..4b1ad21
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
@@ -0,0 +1,477 @@
+/*
+ * HiSilicon SoC HHA uncore Hardware event counters support
+ *
+ * Copyright (C) 2017 Hisilicon Limited
+ * Author: Shaokun Zhang <zhangshaokun@hisilicon.com>
+ * Anurup M <anurup.m@huawei.com>
+ *
+ * This code is based on the uncore PMUs like arm-cci and arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/acpi.h>
+#include <linux/bug.h>
+#include <linux/cpuhotplug.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/list.h>
+#include <linux/platform_device.h>
+#include <linux/smp.h>
+
+#include "hisi_uncore_pmu.h"
+
+/* HHA register definition */
+#define HHA_INT_MASK 0x0804
+#define HHA_INT_STATUS 0x0808
+#define HHA_INT_CLEAR 0x080C
+#define HHA_PERF_CTRL 0x1E00
+#define HHA_EVENT_CTRL 0x1E04
+#define HHA_EVENT_TYPE0 0x1E80
+/*
+ * Each counter is 48-bits and [48:63] are reserved
+ * which are Read-As-Zero and Writes-Ignored.
+ */
+#define HHA_CNT0_LOWER 0x1F00
+
+/* HHA has 16-counters */
+#define HHA_NR_COUNTERS 0x10
+
+#define HHA_PERF_CTRL_EN 0x1
+#define HHA_EVTYPE_NONE 0xff
+
+/*
+ * Select the counter register offset using the counter index
+ * each counter is 48-bits.
+ */
+static u32 hisi_hha_pmu_get_counter_offset(int cntr_idx)
+{
+ return (HHA_CNT0_LOWER + (cntr_idx * 8));
+}
+
+static u64 hisi_hha_pmu_read_counter(struct hisi_pmu *hha_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 idx = hwc->idx;
+
+ if (!hisi_uncore_pmu_counter_valid(hha_pmu, idx)) {
+ dev_err(hha_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return 0;
+ }
+
+ /* Read 64 bits and like L3C, top 16 bits are RAZ */
+ return readq(hha_pmu->base + hisi_hha_pmu_get_counter_offset(idx));
+}
+
+static void hisi_hha_pmu_write_counter(struct hisi_pmu *hha_pmu,
+ struct hw_perf_event *hwc, u64 val)
+{
+ u32 idx = hwc->idx;
+
+ if (!hisi_uncore_pmu_counter_valid(hha_pmu, idx)) {
+ dev_err(hha_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ /* Write 64 bits and like L3C, top 16 bits are WI */
+ writeq(val, hha_pmu->base + hisi_hha_pmu_get_counter_offset(idx));
+}
+
+static void hisi_hha_pmu_write_evtype(struct hisi_pmu *hha_pmu, int idx,
+ u32 type)
+{
+ u32 reg, reg_idx, shift, val;
+
+ /*
+ * Select the appropriate event select register(HHA_EVENT_TYPEx).
+ * There are 4 event select registers for the 16 hardware counters.
+ * Event code is 8-bits and for the first 4 hardware counters,
+ * HHA_EVENT_TYPE0 is chosen. For the next 4 hardware counters,
+ * HHA_EVENT_TYPE1 is chosen and so on.
+ */
+ reg = HHA_EVENT_TYPE0 + 4 * (idx / 4);
+ reg_idx = idx % 4;
+ shift = 8 * reg_idx;
+
+ /* Write event code to HHA_EVENT_TYPEx register */
+ val = readl(hha_pmu->base + reg);
+ val &= ~(HHA_EVTYPE_NONE << shift);
+ val |= (type << shift);
+ writel(val, hha_pmu->base + reg);
+}
+
+static void hisi_hha_pmu_start_counters(struct hisi_pmu *hha_pmu)
+{
+ u32 val;
+
+ /*
+ * Set perf_enable bit in HHA_PERF_CTRL to start event
+ * counting for all enabled counters.
+ */
+ val = readl(hha_pmu->base + HHA_PERF_CTRL);
+ val |= HHA_PERF_CTRL_EN;
+ writel(val, hha_pmu->base + HHA_PERF_CTRL);
+}
+
+static void hisi_hha_pmu_stop_counters(struct hisi_pmu *hha_pmu)
+{
+ u32 val;
+
+ /*
+ * Clear perf_enable bit in HHA_PERF_CTRL to stop event
+ * counting for all enabled counters.
+ */
+ val = readl(hha_pmu->base + HHA_PERF_CTRL);
+ val &= ~(HHA_PERF_CTRL_EN);
+ writel(val, hha_pmu->base + HHA_PERF_CTRL);
+}
+
+static void hisi_hha_pmu_enable_counter(struct hisi_pmu *hha_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Enable counter index in HHA_EVENT_CTRL register */
+ val = readl(hha_pmu->base + HHA_EVENT_CTRL);
+ val |= (1 << hwc->idx);
+ writel(val, hha_pmu->base + HHA_EVENT_CTRL);
+}
+
+static void hisi_hha_pmu_disable_counter(struct hisi_pmu *hha_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Clear counter index in HHA_EVENT_CTRL register */
+ val = readl(hha_pmu->base + HHA_EVENT_CTRL);
+ val &= ~(1 << hwc->idx);
+ writel(val, hha_pmu->base + HHA_EVENT_CTRL);
+}
+
+static void hisi_hha_pmu_enable_counter_int(struct hisi_pmu *hha_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Write 0 to enable interrupt */
+ val = readl(hha_pmu->base + HHA_INT_MASK);
+ val &= ~(1 << hwc->idx);
+ writel(val, hha_pmu->base + HHA_INT_MASK);
+}
+
+static void hisi_hha_pmu_disable_counter_int(struct hisi_pmu *hha_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Write 1 to mask interrupt */
+ val = readl(hha_pmu->base + HHA_INT_MASK);
+ val |= (1 << hwc->idx);
+ writel(val, hha_pmu->base + HHA_INT_MASK);
+}
+
+static irqreturn_t hisi_hha_pmu_isr(int irq, void *dev_id)
+{
+ struct hisi_pmu *hha_pmu = dev_id;
+ struct perf_event *event;
+ unsigned long overflown;
+ int idx;
+
+ /* Read HHA_INT_STATUS register */
+ overflown = readl(hha_pmu->base + HHA_INT_STATUS);
+ if (!overflown)
+ return IRQ_NONE;
+
+ /*
+ * Find the counter index which overflowed if the bit was set
+ * and handle it
+ */
+ for_each_set_bit(idx, &overflown, HHA_NR_COUNTERS) {
+ /* Write 1 to clear the IRQ status flag */
+ writel((1 << idx), hha_pmu->base + HHA_INT_CLEAR);
+
+ /* Get the corresponding event struct */
+ event = hha_pmu->pmu_events.hw_events[idx];
+ if (!event)
+ continue;
+
+ hisi_uncore_pmu_event_update(event);
+ hisi_uncore_pmu_set_event_period(event);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int hisi_hha_pmu_init_irq(struct hisi_pmu *hha_pmu,
+ struct platform_device *pdev)
+{
+ int irq, ret;
+
+ /* Read and init IRQ */
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "HHA PMU get irq fail; irq:%d\n", irq);
+ return irq;
+ }
+
+ ret = devm_request_irq(&pdev->dev, irq, hisi_hha_pmu_isr,
+ IRQF_NOBALANCING | IRQF_NO_THREAD,
+ dev_name(&pdev->dev), hha_pmu);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "Fail to request IRQ:%d ret:%d\n", irq, ret);
+ return ret;
+ }
+
+ hha_pmu->irq = irq;
+
+ return 0;
+}
+
+static const struct acpi_device_id hisi_hha_pmu_acpi_match[] = {
+ { "HISI0243", },
+ {},
+};
+MODULE_DEVICE_TABLE(acpi, hisi_hha_pmu_acpi_match);
+
+static int hisi_hha_pmu_init_data(struct platform_device *pdev,
+ struct hisi_pmu *hha_pmu)
+{
+ unsigned long long id;
+ struct resource *res;
+ acpi_status status;
+ int cpu;
+
+ status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
+ "_UID", NULL, &id);
+ if (ACPI_FAILURE(status))
+ return -EINVAL;
+
+ hha_pmu->id = id;
+
+ /*
+ * Use SCCL_ID and UID to identify the HHA PMU, while
+ * SCCL_ID is in MPIDR[aff2].
+ */
+ if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
+ &hha_pmu->sccl_id)) {
+ dev_err(&pdev->dev, "Can not read hha sccl-id!\n");
+ return -EINVAL;
+ }
+
+ /* Initialise the cpumask fo the PMU */
+ for_each_present_cpu(cpu)
+ smp_call_function_single(cpu,
+ hisi_uncore_pmu_set_cpumask_by_sccl,
+ (void *)hha_pmu, 1);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ hha_pmu->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(hha_pmu->base)) {
+ dev_err(&pdev->dev, "ioremap failed for hha_pmu resource\n");
+ return PTR_ERR(hha_pmu->base);
+ }
+
+ return 0;
+}
+
+static struct attribute *hisi_hha_pmu_format_attr[] = {
+ HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
+ NULL,
+};
+
+static const struct attribute_group hisi_hha_pmu_format_group = {
+ .name = "format",
+ .attrs = hisi_hha_pmu_format_attr,
+};
+
+static struct attribute *hisi_hha_pmu_events_attr[] = {
+ HISI_PMU_EVENT_ATTR(rx_ops_num, 0x00),
+ HISI_PMU_EVENT_ATTR(rx_outer, 0x01),
+ HISI_PMU_EVENT_ATTR(rx_sccl, 0x02),
+ HISI_PMU_EVENT_ATTR(rx_ccix, 0x03),
+ HISI_PMU_EVENT_ATTR(rx_wbi, 0x04),
+ HISI_PMU_EVENT_ATTR(rx_wbip, 0x05),
+ HISI_PMU_EVENT_ATTR(rx_wtistash, 0x11),
+ HISI_PMU_EVENT_ATTR(rd_ddr_64b, 0x1c),
+ HISI_PMU_EVENT_ATTR(wr_dr_64b, 0x1d),
+ HISI_PMU_EVENT_ATTR(rd_ddr_128b, 0x1e),
+ HISI_PMU_EVENT_ATTR(wr_ddr_128b, 0x1f),
+ HISI_PMU_EVENT_ATTR(spill_num, 0x20),
+ HISI_PMU_EVENT_ATTR(spill_success, 0x21),
+ HISI_PMU_EVENT_ATTR(bi_num, 0x23),
+ HISI_PMU_EVENT_ATTR(mediated_num, 0x32),
+ HISI_PMU_EVENT_ATTR(tx_snp_num, 0x33),
+ HISI_PMU_EVENT_ATTR(tx_snp_outer, 0x34),
+ HISI_PMU_EVENT_ATTR(tx_snp_ccix, 0x35),
+ HISI_PMU_EVENT_ATTR(rx_snprspdata, 0x38),
+ HISI_PMU_EVENT_ATTR(rx_snprsp_outer, 0x3c),
+ HISI_PMU_EVENT_ATTR(sdir-lookup, 0x40),
+ HISI_PMU_EVENT_ATTR(edir-lookup, 0x41),
+ HISI_PMU_EVENT_ATTR(sdir-hit, 0x42),
+ HISI_PMU_EVENT_ATTR(edir-hit, 0x43),
+ HISI_PMU_EVENT_ATTR(sdir-home-migrate, 0x4c),
+ HISI_PMU_EVENT_ATTR(edir-home-migrate, 0x4d),
+ NULL,
+};
+
+static const struct attribute_group hisi_hha_pmu_events_group = {
+ .name = "events",
+ .attrs = hisi_hha_pmu_events_attr,
+};
+
+static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
+
+static struct attribute *hisi_hha_pmu_cpumask_attrs[] = {
+ &dev_attr_cpumask.attr,
+ NULL,
+};
+
+static const struct attribute_group hisi_hha_pmu_cpumask_attr_group = {
+ .attrs = hisi_hha_pmu_cpumask_attrs,
+};
+
+static const struct attribute_group *hisi_hha_pmu_attr_groups[] = {
+ &hisi_hha_pmu_format_group,
+ &hisi_hha_pmu_events_group,
+ &hisi_hha_pmu_cpumask_attr_group,
+ NULL,
+};
+
+static const struct hisi_uncore_ops hisi_uncore_hha_ops = {
+ .write_evtype = hisi_hha_pmu_write_evtype,
+ .get_event_idx = hisi_uncore_pmu_get_event_idx,
+ .start_counters = hisi_hha_pmu_start_counters,
+ .stop_counters = hisi_hha_pmu_stop_counters,
+ .enable_counter = hisi_hha_pmu_enable_counter,
+ .disable_counter = hisi_hha_pmu_disable_counter,
+ .enable_counter_int = hisi_hha_pmu_enable_counter_int,
+ .disable_counter_int = hisi_hha_pmu_disable_counter_int,
+ .write_counter = hisi_hha_pmu_write_counter,
+ .read_counter = hisi_hha_pmu_read_counter,
+};
+
+static int hisi_hha_pmu_dev_probe(struct platform_device *pdev,
+ struct hisi_pmu *hha_pmu)
+{
+ int ret;
+
+ ret = hisi_hha_pmu_init_data(pdev, hha_pmu);
+ if (ret)
+ return ret;
+
+ ret = hisi_hha_pmu_init_irq(hha_pmu, pdev);
+ if (ret)
+ return ret;
+
+ hha_pmu->num_counters = HHA_NR_COUNTERS;
+ hha_pmu->counter_bits = 48;
+ hha_pmu->ops = &hisi_uncore_hha_ops;
+ hha_pmu->dev = &pdev->dev;
+ hha_pmu->on_cpu = -1;
+
+ return 0;
+}
+
+static int hisi_hha_pmu_probe(struct platform_device *pdev)
+{
+ struct hisi_pmu *hha_pmu;
+ char *name;
+ int ret;
+
+ hha_pmu = devm_kzalloc(&pdev->dev, sizeof(*hha_pmu), GFP_KERNEL);
+ if (!hha_pmu)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, hha_pmu);
+
+ ret = hisi_hha_pmu_dev_probe(pdev, hha_pmu);
+ if (ret)
+ return ret;
+
+ ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
+ &hha_pmu->node);
+ if (ret) {
+ dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
+ return ret;
+ }
+
+ name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%u_hha%u",
+ hha_pmu->sccl_id, hha_pmu->id);
+ hha_pmu->pmu = (struct pmu) {
+ .name = name,
+ .task_ctx_nr = perf_invalid_context,
+ .event_init = hisi_uncore_pmu_event_init,
+ .pmu_enable = hisi_uncore_pmu_enable,
+ .pmu_disable = hisi_uncore_pmu_disable,
+ .add = hisi_uncore_pmu_add,
+ .del = hisi_uncore_pmu_del,
+ .start = hisi_uncore_pmu_start,
+ .stop = hisi_uncore_pmu_stop,
+ .read = hisi_uncore_pmu_read,
+ .attr_groups = hisi_hha_pmu_attr_groups,
+ };
+
+ ret = perf_pmu_register(&hha_pmu->pmu, name, -1);
+ if (ret) {
+ dev_err(hha_pmu->dev, "HHA PMU register failed!\n");
+ cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
+ &hha_pmu->node);
+ }
+
+ return ret;
+}
+
+static int hisi_hha_pmu_remove(struct platform_device *pdev)
+{
+ struct hisi_pmu *hha_pmu = platform_get_drvdata(pdev);
+
+ perf_pmu_unregister(&hha_pmu->pmu);
+ cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
+ &hha_pmu->node);
+
+ return 0;
+}
+
+static struct platform_driver hisi_hha_pmu_driver = {
+ .driver = {
+ .name = "hisi_hha_pmu",
+ .acpi_match_table = ACPI_PTR(hisi_hha_pmu_acpi_match),
+ },
+ .probe = hisi_hha_pmu_probe,
+ .remove = hisi_hha_pmu_remove,
+};
+
+static int __init hisi_hha_pmu_module_init(void)
+{
+ int ret;
+
+ ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
+ "AP_PERF_ARM_HISI_HHA_ONLINE",
+ hisi_uncore_pmu_online_cpu,
+ hisi_uncore_pmu_offline_cpu);
+ if (ret) {
+ pr_err("HHA PMU: Error setup hotplug, ret = %d;\n", ret);
+ return ret;
+ }
+
+ ret = platform_driver_register(&hisi_hha_pmu_driver);
+ if (ret)
+ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE);
+
+ return ret;
+}
+module_init(hisi_hha_pmu_module_init);
+
+static void __exit hisi_hha_pmu_module_exit(void)
+{
+ platform_driver_unregister(&hisi_hha_pmu_driver);
+ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE);
+}
+module_exit(hisi_hha_pmu_module_exit);
+
+MODULE_DESCRIPTION("HiSilicon SoC HHA uncore PMU driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Shaokun Zhang <zhangshaokun@hisilicon.com>");
+MODULE_AUTHOR("Anurup M <anurup.m@huawei.com>");
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 6858942..85657ce 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -134,6 +134,7 @@ enum cpuhp_state {
CPUHP_AP_PERF_S390_SF_ONLINE,
CPUHP_AP_PERF_ARM_CCI_ONLINE,
CPUHP_AP_PERF_ARM_CCN_ONLINE,
+ CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
CPUHP_AP_PERF_ARM_L2X0_ONLINE,
CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE,
--
1.9.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver
@ 2017-08-22 8:07 ` Shaokun Zhang
0 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: linux-arm-kernel
L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
SoC. This patch adds support for HHA PMU driver, Each HHA has own
control, counter and interrupt registers and is an separate PMU. For
each HHA PMU, it has 16-programable counters and each counter is
free-running. Interrupt is supported to handle counter (48-bits)
overflow.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 477 +++++++++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
3 files changed, 479 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
index 4a3d3e6..a72afe8 100644
--- a/drivers/perf/hisilicon/Makefile
+++ b/drivers/perf/hisilicon/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o hisi_uncore_hha_pmu.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
new file mode 100644
index 0000000..4b1ad21
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
@@ -0,0 +1,477 @@
+/*
+ * HiSilicon SoC HHA uncore Hardware event counters support
+ *
+ * Copyright (C) 2017 Hisilicon Limited
+ * Author: Shaokun Zhang <zhangshaokun@hisilicon.com>
+ * Anurup M <anurup.m@huawei.com>
+ *
+ * This code is based on the uncore PMUs like arm-cci and arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/acpi.h>
+#include <linux/bug.h>
+#include <linux/cpuhotplug.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/list.h>
+#include <linux/platform_device.h>
+#include <linux/smp.h>
+
+#include "hisi_uncore_pmu.h"
+
+/* HHA register definition */
+#define HHA_INT_MASK 0x0804
+#define HHA_INT_STATUS 0x0808
+#define HHA_INT_CLEAR 0x080C
+#define HHA_PERF_CTRL 0x1E00
+#define HHA_EVENT_CTRL 0x1E04
+#define HHA_EVENT_TYPE0 0x1E80
+/*
+ * Each counter is 48-bits and [48:63] are reserved
+ * which are Read-As-Zero and Writes-Ignored.
+ */
+#define HHA_CNT0_LOWER 0x1F00
+
+/* HHA has 16-counters */
+#define HHA_NR_COUNTERS 0x10
+
+#define HHA_PERF_CTRL_EN 0x1
+#define HHA_EVTYPE_NONE 0xff
+
+/*
+ * Select the counter register offset using the counter index
+ * each counter is 48-bits.
+ */
+static u32 hisi_hha_pmu_get_counter_offset(int cntr_idx)
+{
+ return (HHA_CNT0_LOWER + (cntr_idx * 8));
+}
+
+static u64 hisi_hha_pmu_read_counter(struct hisi_pmu *hha_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 idx = hwc->idx;
+
+ if (!hisi_uncore_pmu_counter_valid(hha_pmu, idx)) {
+ dev_err(hha_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return 0;
+ }
+
+ /* Read 64 bits and like L3C, top 16 bits are RAZ */
+ return readq(hha_pmu->base + hisi_hha_pmu_get_counter_offset(idx));
+}
+
+static void hisi_hha_pmu_write_counter(struct hisi_pmu *hha_pmu,
+ struct hw_perf_event *hwc, u64 val)
+{
+ u32 idx = hwc->idx;
+
+ if (!hisi_uncore_pmu_counter_valid(hha_pmu, idx)) {
+ dev_err(hha_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ /* Write 64 bits and like L3C, top 16 bits are WI */
+ writeq(val, hha_pmu->base + hisi_hha_pmu_get_counter_offset(idx));
+}
+
+static void hisi_hha_pmu_write_evtype(struct hisi_pmu *hha_pmu, int idx,
+ u32 type)
+{
+ u32 reg, reg_idx, shift, val;
+
+ /*
+ * Select the appropriate event select register(HHA_EVENT_TYPEx).
+ * There are 4 event select registers for the 16 hardware counters.
+ * Event code is 8-bits and for the first 4 hardware counters,
+ * HHA_EVENT_TYPE0 is chosen. For the next 4 hardware counters,
+ * HHA_EVENT_TYPE1 is chosen and so on.
+ */
+ reg = HHA_EVENT_TYPE0 + 4 * (idx / 4);
+ reg_idx = idx % 4;
+ shift = 8 * reg_idx;
+
+ /* Write event code to HHA_EVENT_TYPEx register */
+ val = readl(hha_pmu->base + reg);
+ val &= ~(HHA_EVTYPE_NONE << shift);
+ val |= (type << shift);
+ writel(val, hha_pmu->base + reg);
+}
+
+static void hisi_hha_pmu_start_counters(struct hisi_pmu *hha_pmu)
+{
+ u32 val;
+
+ /*
+ * Set perf_enable bit in HHA_PERF_CTRL to start event
+ * counting for all enabled counters.
+ */
+ val = readl(hha_pmu->base + HHA_PERF_CTRL);
+ val |= HHA_PERF_CTRL_EN;
+ writel(val, hha_pmu->base + HHA_PERF_CTRL);
+}
+
+static void hisi_hha_pmu_stop_counters(struct hisi_pmu *hha_pmu)
+{
+ u32 val;
+
+ /*
+ * Clear perf_enable bit in HHA_PERF_CTRL to stop event
+ * counting for all enabled counters.
+ */
+ val = readl(hha_pmu->base + HHA_PERF_CTRL);
+ val &= ~(HHA_PERF_CTRL_EN);
+ writel(val, hha_pmu->base + HHA_PERF_CTRL);
+}
+
+static void hisi_hha_pmu_enable_counter(struct hisi_pmu *hha_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Enable counter index in HHA_EVENT_CTRL register */
+ val = readl(hha_pmu->base + HHA_EVENT_CTRL);
+ val |= (1 << hwc->idx);
+ writel(val, hha_pmu->base + HHA_EVENT_CTRL);
+}
+
+static void hisi_hha_pmu_disable_counter(struct hisi_pmu *hha_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Clear counter index in HHA_EVENT_CTRL register */
+ val = readl(hha_pmu->base + HHA_EVENT_CTRL);
+ val &= ~(1 << hwc->idx);
+ writel(val, hha_pmu->base + HHA_EVENT_CTRL);
+}
+
+static void hisi_hha_pmu_enable_counter_int(struct hisi_pmu *hha_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Write 0 to enable interrupt */
+ val = readl(hha_pmu->base + HHA_INT_MASK);
+ val &= ~(1 << hwc->idx);
+ writel(val, hha_pmu->base + HHA_INT_MASK);
+}
+
+static void hisi_hha_pmu_disable_counter_int(struct hisi_pmu *hha_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Write 1 to mask interrupt */
+ val = readl(hha_pmu->base + HHA_INT_MASK);
+ val |= (1 << hwc->idx);
+ writel(val, hha_pmu->base + HHA_INT_MASK);
+}
+
+static irqreturn_t hisi_hha_pmu_isr(int irq, void *dev_id)
+{
+ struct hisi_pmu *hha_pmu = dev_id;
+ struct perf_event *event;
+ unsigned long overflown;
+ int idx;
+
+ /* Read HHA_INT_STATUS register */
+ overflown = readl(hha_pmu->base + HHA_INT_STATUS);
+ if (!overflown)
+ return IRQ_NONE;
+
+ /*
+ * Find the counter index which overflowed if the bit was set
+ * and handle it
+ */
+ for_each_set_bit(idx, &overflown, HHA_NR_COUNTERS) {
+ /* Write 1 to clear the IRQ status flag */
+ writel((1 << idx), hha_pmu->base + HHA_INT_CLEAR);
+
+ /* Get the corresponding event struct */
+ event = hha_pmu->pmu_events.hw_events[idx];
+ if (!event)
+ continue;
+
+ hisi_uncore_pmu_event_update(event);
+ hisi_uncore_pmu_set_event_period(event);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int hisi_hha_pmu_init_irq(struct hisi_pmu *hha_pmu,
+ struct platform_device *pdev)
+{
+ int irq, ret;
+
+ /* Read and init IRQ */
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "HHA PMU get irq fail; irq:%d\n", irq);
+ return irq;
+ }
+
+ ret = devm_request_irq(&pdev->dev, irq, hisi_hha_pmu_isr,
+ IRQF_NOBALANCING | IRQF_NO_THREAD,
+ dev_name(&pdev->dev), hha_pmu);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "Fail to request IRQ:%d ret:%d\n", irq, ret);
+ return ret;
+ }
+
+ hha_pmu->irq = irq;
+
+ return 0;
+}
+
+static const struct acpi_device_id hisi_hha_pmu_acpi_match[] = {
+ { "HISI0243", },
+ {},
+};
+MODULE_DEVICE_TABLE(acpi, hisi_hha_pmu_acpi_match);
+
+static int hisi_hha_pmu_init_data(struct platform_device *pdev,
+ struct hisi_pmu *hha_pmu)
+{
+ unsigned long long id;
+ struct resource *res;
+ acpi_status status;
+ int cpu;
+
+ status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
+ "_UID", NULL, &id);
+ if (ACPI_FAILURE(status))
+ return -EINVAL;
+
+ hha_pmu->id = id;
+
+ /*
+ * Use SCCL_ID and UID to identify the HHA PMU, while
+ * SCCL_ID is in MPIDR[aff2].
+ */
+ if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
+ &hha_pmu->sccl_id)) {
+ dev_err(&pdev->dev, "Can not read hha sccl-id!\n");
+ return -EINVAL;
+ }
+
+ /* Initialise the cpumask fo the PMU */
+ for_each_present_cpu(cpu)
+ smp_call_function_single(cpu,
+ hisi_uncore_pmu_set_cpumask_by_sccl,
+ (void *)hha_pmu, 1);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ hha_pmu->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(hha_pmu->base)) {
+ dev_err(&pdev->dev, "ioremap failed for hha_pmu resource\n");
+ return PTR_ERR(hha_pmu->base);
+ }
+
+ return 0;
+}
+
+static struct attribute *hisi_hha_pmu_format_attr[] = {
+ HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
+ NULL,
+};
+
+static const struct attribute_group hisi_hha_pmu_format_group = {
+ .name = "format",
+ .attrs = hisi_hha_pmu_format_attr,
+};
+
+static struct attribute *hisi_hha_pmu_events_attr[] = {
+ HISI_PMU_EVENT_ATTR(rx_ops_num, 0x00),
+ HISI_PMU_EVENT_ATTR(rx_outer, 0x01),
+ HISI_PMU_EVENT_ATTR(rx_sccl, 0x02),
+ HISI_PMU_EVENT_ATTR(rx_ccix, 0x03),
+ HISI_PMU_EVENT_ATTR(rx_wbi, 0x04),
+ HISI_PMU_EVENT_ATTR(rx_wbip, 0x05),
+ HISI_PMU_EVENT_ATTR(rx_wtistash, 0x11),
+ HISI_PMU_EVENT_ATTR(rd_ddr_64b, 0x1c),
+ HISI_PMU_EVENT_ATTR(wr_dr_64b, 0x1d),
+ HISI_PMU_EVENT_ATTR(rd_ddr_128b, 0x1e),
+ HISI_PMU_EVENT_ATTR(wr_ddr_128b, 0x1f),
+ HISI_PMU_EVENT_ATTR(spill_num, 0x20),
+ HISI_PMU_EVENT_ATTR(spill_success, 0x21),
+ HISI_PMU_EVENT_ATTR(bi_num, 0x23),
+ HISI_PMU_EVENT_ATTR(mediated_num, 0x32),
+ HISI_PMU_EVENT_ATTR(tx_snp_num, 0x33),
+ HISI_PMU_EVENT_ATTR(tx_snp_outer, 0x34),
+ HISI_PMU_EVENT_ATTR(tx_snp_ccix, 0x35),
+ HISI_PMU_EVENT_ATTR(rx_snprspdata, 0x38),
+ HISI_PMU_EVENT_ATTR(rx_snprsp_outer, 0x3c),
+ HISI_PMU_EVENT_ATTR(sdir-lookup, 0x40),
+ HISI_PMU_EVENT_ATTR(edir-lookup, 0x41),
+ HISI_PMU_EVENT_ATTR(sdir-hit, 0x42),
+ HISI_PMU_EVENT_ATTR(edir-hit, 0x43),
+ HISI_PMU_EVENT_ATTR(sdir-home-migrate, 0x4c),
+ HISI_PMU_EVENT_ATTR(edir-home-migrate, 0x4d),
+ NULL,
+};
+
+static const struct attribute_group hisi_hha_pmu_events_group = {
+ .name = "events",
+ .attrs = hisi_hha_pmu_events_attr,
+};
+
+static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
+
+static struct attribute *hisi_hha_pmu_cpumask_attrs[] = {
+ &dev_attr_cpumask.attr,
+ NULL,
+};
+
+static const struct attribute_group hisi_hha_pmu_cpumask_attr_group = {
+ .attrs = hisi_hha_pmu_cpumask_attrs,
+};
+
+static const struct attribute_group *hisi_hha_pmu_attr_groups[] = {
+ &hisi_hha_pmu_format_group,
+ &hisi_hha_pmu_events_group,
+ &hisi_hha_pmu_cpumask_attr_group,
+ NULL,
+};
+
+static const struct hisi_uncore_ops hisi_uncore_hha_ops = {
+ .write_evtype = hisi_hha_pmu_write_evtype,
+ .get_event_idx = hisi_uncore_pmu_get_event_idx,
+ .start_counters = hisi_hha_pmu_start_counters,
+ .stop_counters = hisi_hha_pmu_stop_counters,
+ .enable_counter = hisi_hha_pmu_enable_counter,
+ .disable_counter = hisi_hha_pmu_disable_counter,
+ .enable_counter_int = hisi_hha_pmu_enable_counter_int,
+ .disable_counter_int = hisi_hha_pmu_disable_counter_int,
+ .write_counter = hisi_hha_pmu_write_counter,
+ .read_counter = hisi_hha_pmu_read_counter,
+};
+
+static int hisi_hha_pmu_dev_probe(struct platform_device *pdev,
+ struct hisi_pmu *hha_pmu)
+{
+ int ret;
+
+ ret = hisi_hha_pmu_init_data(pdev, hha_pmu);
+ if (ret)
+ return ret;
+
+ ret = hisi_hha_pmu_init_irq(hha_pmu, pdev);
+ if (ret)
+ return ret;
+
+ hha_pmu->num_counters = HHA_NR_COUNTERS;
+ hha_pmu->counter_bits = 48;
+ hha_pmu->ops = &hisi_uncore_hha_ops;
+ hha_pmu->dev = &pdev->dev;
+ hha_pmu->on_cpu = -1;
+
+ return 0;
+}
+
+static int hisi_hha_pmu_probe(struct platform_device *pdev)
+{
+ struct hisi_pmu *hha_pmu;
+ char *name;
+ int ret;
+
+ hha_pmu = devm_kzalloc(&pdev->dev, sizeof(*hha_pmu), GFP_KERNEL);
+ if (!hha_pmu)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, hha_pmu);
+
+ ret = hisi_hha_pmu_dev_probe(pdev, hha_pmu);
+ if (ret)
+ return ret;
+
+ ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
+ &hha_pmu->node);
+ if (ret) {
+ dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
+ return ret;
+ }
+
+ name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%u_hha%u",
+ hha_pmu->sccl_id, hha_pmu->id);
+ hha_pmu->pmu = (struct pmu) {
+ .name = name,
+ .task_ctx_nr = perf_invalid_context,
+ .event_init = hisi_uncore_pmu_event_init,
+ .pmu_enable = hisi_uncore_pmu_enable,
+ .pmu_disable = hisi_uncore_pmu_disable,
+ .add = hisi_uncore_pmu_add,
+ .del = hisi_uncore_pmu_del,
+ .start = hisi_uncore_pmu_start,
+ .stop = hisi_uncore_pmu_stop,
+ .read = hisi_uncore_pmu_read,
+ .attr_groups = hisi_hha_pmu_attr_groups,
+ };
+
+ ret = perf_pmu_register(&hha_pmu->pmu, name, -1);
+ if (ret) {
+ dev_err(hha_pmu->dev, "HHA PMU register failed!\n");
+ cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
+ &hha_pmu->node);
+ }
+
+ return ret;
+}
+
+static int hisi_hha_pmu_remove(struct platform_device *pdev)
+{
+ struct hisi_pmu *hha_pmu = platform_get_drvdata(pdev);
+
+ perf_pmu_unregister(&hha_pmu->pmu);
+ cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
+ &hha_pmu->node);
+
+ return 0;
+}
+
+static struct platform_driver hisi_hha_pmu_driver = {
+ .driver = {
+ .name = "hisi_hha_pmu",
+ .acpi_match_table = ACPI_PTR(hisi_hha_pmu_acpi_match),
+ },
+ .probe = hisi_hha_pmu_probe,
+ .remove = hisi_hha_pmu_remove,
+};
+
+static int __init hisi_hha_pmu_module_init(void)
+{
+ int ret;
+
+ ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
+ "AP_PERF_ARM_HISI_HHA_ONLINE",
+ hisi_uncore_pmu_online_cpu,
+ hisi_uncore_pmu_offline_cpu);
+ if (ret) {
+ pr_err("HHA PMU: Error setup hotplug, ret = %d;\n", ret);
+ return ret;
+ }
+
+ ret = platform_driver_register(&hisi_hha_pmu_driver);
+ if (ret)
+ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE);
+
+ return ret;
+}
+module_init(hisi_hha_pmu_module_init);
+
+static void __exit hisi_hha_pmu_module_exit(void)
+{
+ platform_driver_unregister(&hisi_hha_pmu_driver);
+ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE);
+}
+module_exit(hisi_hha_pmu_module_exit);
+
+MODULE_DESCRIPTION("HiSilicon SoC HHA uncore PMU driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Shaokun Zhang <zhangshaokun@hisilicon.com>");
+MODULE_AUTHOR("Anurup M <anurup.m@huawei.com>");
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 6858942..85657ce 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -134,6 +134,7 @@ enum cpuhp_state {
CPUHP_AP_PERF_S390_SF_ONLINE,
CPUHP_AP_PERF_ARM_CCI_ONLINE,
CPUHP_AP_PERF_ARM_CCN_ONLINE,
+ CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
CPUHP_AP_PERF_ARM_L2X0_ONLINE,
CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE,
--
1.9.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 5/6] perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
2017-08-22 8:07 ` Shaokun Zhang
@ 2017-08-22 8:07 ` Shaokun Zhang
-1 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: mark.rutland, will.deacon
Cc: jonathan.cameron, linux-arm-kernel, linux-kernel, linux-doc,
linuxarm, Shaokun Zhang, Anurup M
This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
DDRC has own control, counter and interrupt registers and is an separate
PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been
mapped to 8-events by hardware, it assumes that counter index is equal
to event code (0 - 7) in DDRC PMU driver. Interrupt is supported to
handle counter (32-bits) overflow.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 467 ++++++++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
3 files changed, 469 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
index a72afe8..2621d51 100644
--- a/drivers/perf/hisilicon/Makefile
+++ b/drivers/perf/hisilicon/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o hisi_uncore_hha_pmu.o
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o hisi_uncore_hha_pmu.o hisi_uncore_ddrc_pmu.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c b/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
new file mode 100644
index 0000000..f7b5568
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
@@ -0,0 +1,467 @@
+/*
+ * HiSilicon SoC DDRC uncore Hardware event counters support
+ *
+ * Copyright (C) 2017 Hisilicon Limited
+ * Author: Shaokun Zhang <zhangshaokun@hisilicon.com>
+ * Anurup M <anurup.m@huawei.com>
+ *
+ * This code is based on the uncore PMUs like arm-cci and arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/acpi.h>
+#include <linux/bug.h>
+#include <linux/cpuhotplug.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/list.h>
+#include <linux/platform_device.h>
+#include <linux/smp.h>
+
+#include "hisi_uncore_pmu.h"
+
+/* DDRC register definition */
+#define DDRC_PERF_CTRL 0x010
+#define DDRC_FLUX_WR 0x380
+#define DDRC_FLUX_RD 0x384
+#define DDRC_FLUX_WCMD 0x388
+#define DDRC_FLUX_RCMD 0x38c
+#define DDRC_PRE_CMD 0x3c0
+#define DDRC_ACT_CMD 0x3c4
+#define DDRC_BNK_CHG 0x3c8
+#define DDRC_RNK_CHG 0x3cc
+#define DDRC_EVENT_CTRL 0x6C0
+#define DDRC_INT_MASK 0x6c8
+#define DDRC_INT_STATUS 0x6cc
+#define DDRC_INT_CLEAR 0x6d0
+
+/* DDRC has 8-counters */
+#define DDRC_NR_COUNTERS 0x8
+#define DDRC_PERF_CTRL_EN 0x2
+
+/*
+ * For DDRC PMU, there are eight-events and every event has been mapped
+ * to fixed-purpose counters which register offset is not consistent.
+ * Therefore there is no write event type and we assume that event
+ * code (0 to 7) is equal to counter index in PMU driver.
+ */
+#define GET_DDRC_EVENTID(hwc) (hwc->config_base & 0x7)
+
+static const u32 ddrc_reg_off[] = {
+ DDRC_FLUX_WR, DDRC_FLUX_RD, DDRC_FLUX_WCMD, DDRC_FLUX_RCMD,
+ DDRC_PRE_CMD, DDRC_ACT_CMD, DDRC_BNK_CHG, DDRC_RNK_CHG
+};
+
+/*
+ * Select the counter register offset using the counter index.
+ * In DDRC there are no programmable counter, the count
+ * is readed form the statistics counter register itself.
+ */
+static u32 hisi_ddrc_pmu_get_counter_offset(int cntr_idx)
+{
+ return ddrc_reg_off[cntr_idx];
+}
+
+static u64 hisi_ddrc_pmu_read_counter(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc)
+{
+ /* Use event code as counter index */
+ u32 idx = GET_DDRC_EVENTID(hwc);
+
+ if (!hisi_uncore_pmu_counter_valid(ddrc_pmu, idx)) {
+ dev_err(ddrc_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return 0;
+ }
+
+ return readl(ddrc_pmu->base + hisi_ddrc_pmu_get_counter_offset(idx));
+}
+
+static void hisi_ddrc_pmu_write_counter(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc, u64 val)
+{
+ u32 idx = GET_DDRC_EVENTID(hwc);
+
+ if (!hisi_uncore_pmu_counter_valid(ddrc_pmu, idx)) {
+ dev_err(ddrc_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ writel((u32)val,
+ ddrc_pmu->base + hisi_ddrc_pmu_get_counter_offset(idx));
+}
+
+/*
+ * For DDRC PMU, event has been mapped to fixed-purpose counter by hardware,
+ * so there is no need to write event type.
+ */
+static void hisi_ddrc_pmu_write_evtype(struct hisi_pmu *hha_pmu, int idx,
+ u32 type)
+{
+}
+
+static void hisi_ddrc_pmu_start_counters(struct hisi_pmu *ddrc_pmu)
+{
+ u32 val;
+
+ /* Set perf_enable in DDRC_PERF_CTRL to start event counting */
+ val = readl(ddrc_pmu->base + DDRC_PERF_CTRL);
+ val |= DDRC_PERF_CTRL_EN;
+ writel(val, ddrc_pmu->base + DDRC_PERF_CTRL);
+}
+
+static void hisi_ddrc_pmu_stop_counters(struct hisi_pmu *ddrc_pmu)
+{
+ u32 val;
+
+ /* Clear perf_enable in DDRC_PERF_CTRL to stop event counting */
+ val = readl(ddrc_pmu->base + DDRC_PERF_CTRL);
+ val &= ~DDRC_PERF_CTRL_EN;
+ writel(val, ddrc_pmu->base + DDRC_PERF_CTRL);
+}
+
+static void hisi_ddrc_pmu_enable_counter(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Set counter index(event code) in DDRC_EVENT_CTRL register */
+ val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL);
+ val |= (1 << GET_DDRC_EVENTID(hwc));
+ writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL);
+}
+
+static void hisi_ddrc_pmu_disable_counter(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Clear counter index(event code) in DDRC_EVENT_CTRL register */
+ val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL);
+ val &= ~(1 << GET_DDRC_EVENTID(hwc));
+ writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL);
+}
+
+static int hisi_ddrc_pmu_get_event_idx(struct perf_event *event)
+{
+ struct hisi_pmu *ddrc_pmu = to_hisi_pmu(event->pmu);
+ unsigned long *used_mask = ddrc_pmu->pmu_events.used_mask;
+ struct hw_perf_event *hwc = &event->hw;
+ /* For DDRC PMU, we use event code as counter index */
+ int idx = GET_DDRC_EVENTID(hwc);
+
+ if (test_bit(idx, used_mask))
+ return -EAGAIN;
+
+ set_bit(idx, used_mask);
+
+ return idx;
+}
+
+static void hisi_ddrc_pmu_enable_counter_int(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Write 0 to enable interrupt */
+ val = readl(ddrc_pmu->base + DDRC_INT_MASK);
+ val &= ~(1 << GET_DDRC_EVENTID(hwc));
+ writel(val, ddrc_pmu->base + DDRC_INT_MASK);
+}
+
+static void hisi_ddrc_pmu_disable_counter_int(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Write 1 to mask interrupt */
+ val = readl(ddrc_pmu->base + DDRC_INT_MASK);
+ val |= (1 << GET_DDRC_EVENTID(hwc));
+ writel(val, ddrc_pmu->base + DDRC_INT_MASK);
+}
+
+static irqreturn_t hisi_ddrc_pmu_isr(int irq, void *dev_id)
+{
+ struct hisi_pmu *ddrc_pmu = dev_id;
+ struct perf_event *event;
+ unsigned long overflown;
+ int idx;
+
+ /* Read the DDRC_INT_STATUS register */
+ overflown = readl(ddrc_pmu->base + DDRC_INT_STATUS);
+ if (!overflown)
+ return IRQ_NONE;
+
+ /*
+ * Find the counter index which overflowed if the bit was set
+ * and handle it
+ */
+ for_each_set_bit(idx, &overflown, DDRC_NR_COUNTERS) {
+ /* Write 1 to clear the IRQ status flag */
+ writel((1 << idx), ddrc_pmu->base + DDRC_INT_CLEAR);
+
+ /* Get the corresponding event struct */
+ event = ddrc_pmu->pmu_events.hw_events[idx];
+ if (!event)
+ continue;
+
+ hisi_uncore_pmu_event_update(event);
+ hisi_uncore_pmu_set_event_period(event);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int hisi_ddrc_pmu_init_irq(struct hisi_pmu *ddrc_pmu,
+ struct platform_device *pdev)
+{
+ int irq, ret;
+
+ /* Read and init IRQ */
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "DDRC PMU get irq fail; irq:%d\n", irq);
+ return irq;
+ }
+
+ ret = devm_request_irq(&pdev->dev, irq, hisi_ddrc_pmu_isr,
+ IRQF_NOBALANCING | IRQF_NO_THREAD,
+ dev_name(&pdev->dev), ddrc_pmu);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "Fail to request IRQ:%d ret:%d\n", irq, ret);
+ return ret;
+ }
+
+ ddrc_pmu->irq = irq;
+
+ return 0;
+}
+
+static const struct acpi_device_id hisi_ddrc_pmu_acpi_match[] = {
+ { "HISI0233", },
+ {},
+};
+MODULE_DEVICE_TABLE(acpi, hisi_ddrc_pmu_acpi_match);
+
+static int hisi_ddrc_pmu_init_data(struct platform_device *pdev,
+ struct hisi_pmu *ddrc_pmu)
+{
+ struct resource *res;
+ int cpu;
+
+ /*
+ * Use the SCCL_ID and DDRC channel ID to identify the
+ * DDRC PMU, while SCCL_ID is in MPIDR[aff2].
+ */
+ if (device_property_read_u32(&pdev->dev, "hisilicon,ch-id",
+ &ddrc_pmu->id)) {
+ dev_err(&pdev->dev, "Can not read ddrc channel-id!\n");
+ return -EINVAL;
+ }
+
+ if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
+ &ddrc_pmu->sccl_id)) {
+ dev_err(&pdev->dev, "Can not read ddrc sccl-id!\n");
+ return -EINVAL;
+ }
+
+ /* Initialise the cpumask of the PMU */
+ for_each_present_cpu(cpu)
+ smp_call_function_single(cpu,
+ hisi_uncore_pmu_set_cpumask_by_sccl,
+ (void *)ddrc_pmu, 1);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ddrc_pmu->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ddrc_pmu->base)) {
+ dev_err(&pdev->dev, "ioremap failed for ddrc_pmu resource\n");
+ return PTR_ERR(ddrc_pmu->base);
+ }
+
+ return 0;
+}
+
+static struct attribute *hisi_ddrc_pmu_format_attr[] = {
+ HISI_PMU_FORMAT_ATTR(event, "config:0-4"),
+ NULL,
+};
+
+static const struct attribute_group hisi_ddrc_pmu_format_group = {
+ .name = "format",
+ .attrs = hisi_ddrc_pmu_format_attr,
+};
+
+static struct attribute *hisi_ddrc_pmu_events_attr[] = {
+ HISI_PMU_EVENT_ATTR(flux_wr, 0x00),
+ HISI_PMU_EVENT_ATTR(flux_rd, 0x01),
+ HISI_PMU_EVENT_ATTR(flux_wcmd, 0x02),
+ HISI_PMU_EVENT_ATTR(flux_rcmd, 0x03),
+ HISI_PMU_EVENT_ATTR(pre_cmd, 0x04),
+ HISI_PMU_EVENT_ATTR(act_cmd, 0x05),
+ HISI_PMU_EVENT_ATTR(rnk_chg, 0x06),
+ HISI_PMU_EVENT_ATTR(rw_chg, 0x07),
+ NULL,
+};
+
+static const struct attribute_group hisi_ddrc_pmu_events_group = {
+ .name = "events",
+ .attrs = hisi_ddrc_pmu_events_attr,
+};
+
+static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
+
+static struct attribute *hisi_ddrc_pmu_cpumask_attrs[] = {
+ &dev_attr_cpumask.attr,
+ NULL,
+};
+
+static const struct attribute_group hisi_ddrc_pmu_cpumask_attr_group = {
+ .attrs = hisi_ddrc_pmu_cpumask_attrs,
+};
+
+static const struct attribute_group *hisi_ddrc_pmu_attr_groups[] = {
+ &hisi_ddrc_pmu_format_group,
+ &hisi_ddrc_pmu_events_group,
+ &hisi_ddrc_pmu_cpumask_attr_group,
+ NULL,
+};
+
+static const struct hisi_uncore_ops hisi_uncore_ddrc_ops = {
+ .write_evtype = hisi_ddrc_pmu_write_evtype,
+ .get_event_idx = hisi_ddrc_pmu_get_event_idx,
+ .start_counters = hisi_ddrc_pmu_start_counters,
+ .stop_counters = hisi_ddrc_pmu_stop_counters,
+ .enable_counter = hisi_ddrc_pmu_enable_counter,
+ .disable_counter = hisi_ddrc_pmu_disable_counter,
+ .enable_counter_int = hisi_ddrc_pmu_enable_counter_int,
+ .disable_counter_int = hisi_ddrc_pmu_disable_counter_int,
+ .write_counter = hisi_ddrc_pmu_write_counter,
+ .read_counter = hisi_ddrc_pmu_read_counter,
+};
+
+static int hisi_ddrc_pmu_dev_probe(struct platform_device *pdev,
+ struct hisi_pmu *ddrc_pmu)
+{
+ int ret;
+
+ ret = hisi_ddrc_pmu_init_data(pdev, ddrc_pmu);
+ if (ret)
+ return ret;
+
+ ret = hisi_ddrc_pmu_init_irq(ddrc_pmu, pdev);
+ if (ret)
+ return ret;
+
+ ddrc_pmu->num_counters = DDRC_NR_COUNTERS;
+ ddrc_pmu->counter_bits = 32;
+ ddrc_pmu->ops = &hisi_uncore_ddrc_ops;
+ ddrc_pmu->dev = &pdev->dev;
+ ddrc_pmu->on_cpu = -1;
+
+ return 0;
+}
+
+static int hisi_ddrc_pmu_probe(struct platform_device *pdev)
+{
+ struct hisi_pmu *ddrc_pmu;
+ char *name;
+ int ret;
+
+ ddrc_pmu = devm_kzalloc(&pdev->dev, sizeof(*ddrc_pmu), GFP_KERNEL);
+ if (!ddrc_pmu)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, ddrc_pmu);
+
+ ret = hisi_ddrc_pmu_dev_probe(pdev, ddrc_pmu);
+ if (ret)
+ return ret;
+
+ ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
+ &ddrc_pmu->node);
+ if (ret) {
+ dev_err(&pdev->dev, "Error %d registering hotplug;\n", ret);
+ return ret;
+ }
+
+ name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%u_ddrc%u",
+ ddrc_pmu->sccl_id, ddrc_pmu->id);
+ ddrc_pmu->pmu = (struct pmu) {
+ .name = name,
+ .task_ctx_nr = perf_invalid_context,
+ .event_init = hisi_uncore_pmu_event_init,
+ .pmu_enable = hisi_uncore_pmu_enable,
+ .pmu_disable = hisi_uncore_pmu_disable,
+ .add = hisi_uncore_pmu_add,
+ .del = hisi_uncore_pmu_del,
+ .start = hisi_uncore_pmu_start,
+ .stop = hisi_uncore_pmu_stop,
+ .read = hisi_uncore_pmu_read,
+ .attr_groups = hisi_ddrc_pmu_attr_groups,
+ };
+
+ ret = perf_pmu_register(&ddrc_pmu->pmu, name, -1);
+ if (ret) {
+ dev_err(ddrc_pmu->dev, "DDRC PMU register failed!\n");
+ cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
+ &ddrc_pmu->node);
+ }
+
+ return ret;
+}
+
+static int hisi_ddrc_pmu_remove(struct platform_device *pdev)
+{
+ struct hisi_pmu *ddrc_pmu = platform_get_drvdata(pdev);
+
+ perf_pmu_unregister(&ddrc_pmu->pmu);
+ cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
+ &ddrc_pmu->node);
+
+ return 0;
+}
+
+static struct platform_driver hisi_ddrc_pmu_driver = {
+ .driver = {
+ .name = "hisi_ddrc_pmu",
+ .acpi_match_table = ACPI_PTR(hisi_ddrc_pmu_acpi_match),
+ },
+ .probe = hisi_ddrc_pmu_probe,
+ .remove = hisi_ddrc_pmu_remove,
+};
+
+static int __init hisi_ddrc_pmu_module_init(void)
+{
+ int ret;
+
+ ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
+ "AP_PERF_ARM_HISI_DDRC_ONLINE",
+ hisi_uncore_pmu_online_cpu,
+ hisi_uncore_pmu_offline_cpu);
+ if (ret) {
+ pr_err("DDRC PMU: setup hotplug, ret = %d\n", ret);
+ return ret;
+ }
+
+ ret = platform_driver_register(&hisi_ddrc_pmu_driver);
+ if (ret)
+ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE);
+
+ return ret;
+}
+module_init(hisi_ddrc_pmu_module_init);
+
+static void __exit hisi_ddrc_pmu_module_exit(void)
+{
+ platform_driver_unregister(&hisi_ddrc_pmu_driver);
+ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE);
+
+}
+module_exit(hisi_ddrc_pmu_module_exit);
+
+MODULE_DESCRIPTION("HiSilicon SoC DDRC uncore PMU driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Shaokun Zhang <zhangshaokun@hisilicon.com>");
+MODULE_AUTHOR("Anurup M <anurup.m@huawei.com>");
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 85657ce..bd5cde6 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -134,6 +134,7 @@ enum cpuhp_state {
CPUHP_AP_PERF_S390_SF_ONLINE,
CPUHP_AP_PERF_ARM_CCI_ONLINE,
CPUHP_AP_PERF_ARM_CCN_ONLINE,
+ CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
CPUHP_AP_PERF_ARM_L2X0_ONLINE,
--
1.9.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 5/6] perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
@ 2017-08-22 8:07 ` Shaokun Zhang
0 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
DDRC has own control, counter and interrupt registers and is an separate
PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been
mapped to 8-events by hardware, it assumes that counter index is equal
to event code (0 - 7) in DDRC PMU driver. Interrupt is supported to
handle counter (32-bits) overflow.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 467 ++++++++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
3 files changed, 469 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
index a72afe8..2621d51 100644
--- a/drivers/perf/hisilicon/Makefile
+++ b/drivers/perf/hisilicon/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o hisi_uncore_hha_pmu.o
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o hisi_uncore_hha_pmu.o hisi_uncore_ddrc_pmu.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c b/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
new file mode 100644
index 0000000..f7b5568
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
@@ -0,0 +1,467 @@
+/*
+ * HiSilicon SoC DDRC uncore Hardware event counters support
+ *
+ * Copyright (C) 2017 Hisilicon Limited
+ * Author: Shaokun Zhang <zhangshaokun@hisilicon.com>
+ * Anurup M <anurup.m@huawei.com>
+ *
+ * This code is based on the uncore PMUs like arm-cci and arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/acpi.h>
+#include <linux/bug.h>
+#include <linux/cpuhotplug.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/list.h>
+#include <linux/platform_device.h>
+#include <linux/smp.h>
+
+#include "hisi_uncore_pmu.h"
+
+/* DDRC register definition */
+#define DDRC_PERF_CTRL 0x010
+#define DDRC_FLUX_WR 0x380
+#define DDRC_FLUX_RD 0x384
+#define DDRC_FLUX_WCMD 0x388
+#define DDRC_FLUX_RCMD 0x38c
+#define DDRC_PRE_CMD 0x3c0
+#define DDRC_ACT_CMD 0x3c4
+#define DDRC_BNK_CHG 0x3c8
+#define DDRC_RNK_CHG 0x3cc
+#define DDRC_EVENT_CTRL 0x6C0
+#define DDRC_INT_MASK 0x6c8
+#define DDRC_INT_STATUS 0x6cc
+#define DDRC_INT_CLEAR 0x6d0
+
+/* DDRC has 8-counters */
+#define DDRC_NR_COUNTERS 0x8
+#define DDRC_PERF_CTRL_EN 0x2
+
+/*
+ * For DDRC PMU, there are eight-events and every event has been mapped
+ * to fixed-purpose counters which register offset is not consistent.
+ * Therefore there is no write event type and we assume that event
+ * code (0 to 7) is equal to counter index in PMU driver.
+ */
+#define GET_DDRC_EVENTID(hwc) (hwc->config_base & 0x7)
+
+static const u32 ddrc_reg_off[] = {
+ DDRC_FLUX_WR, DDRC_FLUX_RD, DDRC_FLUX_WCMD, DDRC_FLUX_RCMD,
+ DDRC_PRE_CMD, DDRC_ACT_CMD, DDRC_BNK_CHG, DDRC_RNK_CHG
+};
+
+/*
+ * Select the counter register offset using the counter index.
+ * In DDRC there are no programmable counter, the count
+ * is readed form the statistics counter register itself.
+ */
+static u32 hisi_ddrc_pmu_get_counter_offset(int cntr_idx)
+{
+ return ddrc_reg_off[cntr_idx];
+}
+
+static u64 hisi_ddrc_pmu_read_counter(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc)
+{
+ /* Use event code as counter index */
+ u32 idx = GET_DDRC_EVENTID(hwc);
+
+ if (!hisi_uncore_pmu_counter_valid(ddrc_pmu, idx)) {
+ dev_err(ddrc_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return 0;
+ }
+
+ return readl(ddrc_pmu->base + hisi_ddrc_pmu_get_counter_offset(idx));
+}
+
+static void hisi_ddrc_pmu_write_counter(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc, u64 val)
+{
+ u32 idx = GET_DDRC_EVENTID(hwc);
+
+ if (!hisi_uncore_pmu_counter_valid(ddrc_pmu, idx)) {
+ dev_err(ddrc_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ writel((u32)val,
+ ddrc_pmu->base + hisi_ddrc_pmu_get_counter_offset(idx));
+}
+
+/*
+ * For DDRC PMU, event has been mapped to fixed-purpose counter by hardware,
+ * so there is no need to write event type.
+ */
+static void hisi_ddrc_pmu_write_evtype(struct hisi_pmu *hha_pmu, int idx,
+ u32 type)
+{
+}
+
+static void hisi_ddrc_pmu_start_counters(struct hisi_pmu *ddrc_pmu)
+{
+ u32 val;
+
+ /* Set perf_enable in DDRC_PERF_CTRL to start event counting */
+ val = readl(ddrc_pmu->base + DDRC_PERF_CTRL);
+ val |= DDRC_PERF_CTRL_EN;
+ writel(val, ddrc_pmu->base + DDRC_PERF_CTRL);
+}
+
+static void hisi_ddrc_pmu_stop_counters(struct hisi_pmu *ddrc_pmu)
+{
+ u32 val;
+
+ /* Clear perf_enable in DDRC_PERF_CTRL to stop event counting */
+ val = readl(ddrc_pmu->base + DDRC_PERF_CTRL);
+ val &= ~DDRC_PERF_CTRL_EN;
+ writel(val, ddrc_pmu->base + DDRC_PERF_CTRL);
+}
+
+static void hisi_ddrc_pmu_enable_counter(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Set counter index(event code) in DDRC_EVENT_CTRL register */
+ val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL);
+ val |= (1 << GET_DDRC_EVENTID(hwc));
+ writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL);
+}
+
+static void hisi_ddrc_pmu_disable_counter(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Clear counter index(event code) in DDRC_EVENT_CTRL register */
+ val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL);
+ val &= ~(1 << GET_DDRC_EVENTID(hwc));
+ writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL);
+}
+
+static int hisi_ddrc_pmu_get_event_idx(struct perf_event *event)
+{
+ struct hisi_pmu *ddrc_pmu = to_hisi_pmu(event->pmu);
+ unsigned long *used_mask = ddrc_pmu->pmu_events.used_mask;
+ struct hw_perf_event *hwc = &event->hw;
+ /* For DDRC PMU, we use event code as counter index */
+ int idx = GET_DDRC_EVENTID(hwc);
+
+ if (test_bit(idx, used_mask))
+ return -EAGAIN;
+
+ set_bit(idx, used_mask);
+
+ return idx;
+}
+
+static void hisi_ddrc_pmu_enable_counter_int(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Write 0 to enable interrupt */
+ val = readl(ddrc_pmu->base + DDRC_INT_MASK);
+ val &= ~(1 << GET_DDRC_EVENTID(hwc));
+ writel(val, ddrc_pmu->base + DDRC_INT_MASK);
+}
+
+static void hisi_ddrc_pmu_disable_counter_int(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc)
+{
+ u32 val;
+
+ /* Write 1 to mask interrupt */
+ val = readl(ddrc_pmu->base + DDRC_INT_MASK);
+ val |= (1 << GET_DDRC_EVENTID(hwc));
+ writel(val, ddrc_pmu->base + DDRC_INT_MASK);
+}
+
+static irqreturn_t hisi_ddrc_pmu_isr(int irq, void *dev_id)
+{
+ struct hisi_pmu *ddrc_pmu = dev_id;
+ struct perf_event *event;
+ unsigned long overflown;
+ int idx;
+
+ /* Read the DDRC_INT_STATUS register */
+ overflown = readl(ddrc_pmu->base + DDRC_INT_STATUS);
+ if (!overflown)
+ return IRQ_NONE;
+
+ /*
+ * Find the counter index which overflowed if the bit was set
+ * and handle it
+ */
+ for_each_set_bit(idx, &overflown, DDRC_NR_COUNTERS) {
+ /* Write 1 to clear the IRQ status flag */
+ writel((1 << idx), ddrc_pmu->base + DDRC_INT_CLEAR);
+
+ /* Get the corresponding event struct */
+ event = ddrc_pmu->pmu_events.hw_events[idx];
+ if (!event)
+ continue;
+
+ hisi_uncore_pmu_event_update(event);
+ hisi_uncore_pmu_set_event_period(event);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int hisi_ddrc_pmu_init_irq(struct hisi_pmu *ddrc_pmu,
+ struct platform_device *pdev)
+{
+ int irq, ret;
+
+ /* Read and init IRQ */
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "DDRC PMU get irq fail; irq:%d\n", irq);
+ return irq;
+ }
+
+ ret = devm_request_irq(&pdev->dev, irq, hisi_ddrc_pmu_isr,
+ IRQF_NOBALANCING | IRQF_NO_THREAD,
+ dev_name(&pdev->dev), ddrc_pmu);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "Fail to request IRQ:%d ret:%d\n", irq, ret);
+ return ret;
+ }
+
+ ddrc_pmu->irq = irq;
+
+ return 0;
+}
+
+static const struct acpi_device_id hisi_ddrc_pmu_acpi_match[] = {
+ { "HISI0233", },
+ {},
+};
+MODULE_DEVICE_TABLE(acpi, hisi_ddrc_pmu_acpi_match);
+
+static int hisi_ddrc_pmu_init_data(struct platform_device *pdev,
+ struct hisi_pmu *ddrc_pmu)
+{
+ struct resource *res;
+ int cpu;
+
+ /*
+ * Use the SCCL_ID and DDRC channel ID to identify the
+ * DDRC PMU, while SCCL_ID is in MPIDR[aff2].
+ */
+ if (device_property_read_u32(&pdev->dev, "hisilicon,ch-id",
+ &ddrc_pmu->id)) {
+ dev_err(&pdev->dev, "Can not read ddrc channel-id!\n");
+ return -EINVAL;
+ }
+
+ if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
+ &ddrc_pmu->sccl_id)) {
+ dev_err(&pdev->dev, "Can not read ddrc sccl-id!\n");
+ return -EINVAL;
+ }
+
+ /* Initialise the cpumask of the PMU */
+ for_each_present_cpu(cpu)
+ smp_call_function_single(cpu,
+ hisi_uncore_pmu_set_cpumask_by_sccl,
+ (void *)ddrc_pmu, 1);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ddrc_pmu->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ddrc_pmu->base)) {
+ dev_err(&pdev->dev, "ioremap failed for ddrc_pmu resource\n");
+ return PTR_ERR(ddrc_pmu->base);
+ }
+
+ return 0;
+}
+
+static struct attribute *hisi_ddrc_pmu_format_attr[] = {
+ HISI_PMU_FORMAT_ATTR(event, "config:0-4"),
+ NULL,
+};
+
+static const struct attribute_group hisi_ddrc_pmu_format_group = {
+ .name = "format",
+ .attrs = hisi_ddrc_pmu_format_attr,
+};
+
+static struct attribute *hisi_ddrc_pmu_events_attr[] = {
+ HISI_PMU_EVENT_ATTR(flux_wr, 0x00),
+ HISI_PMU_EVENT_ATTR(flux_rd, 0x01),
+ HISI_PMU_EVENT_ATTR(flux_wcmd, 0x02),
+ HISI_PMU_EVENT_ATTR(flux_rcmd, 0x03),
+ HISI_PMU_EVENT_ATTR(pre_cmd, 0x04),
+ HISI_PMU_EVENT_ATTR(act_cmd, 0x05),
+ HISI_PMU_EVENT_ATTR(rnk_chg, 0x06),
+ HISI_PMU_EVENT_ATTR(rw_chg, 0x07),
+ NULL,
+};
+
+static const struct attribute_group hisi_ddrc_pmu_events_group = {
+ .name = "events",
+ .attrs = hisi_ddrc_pmu_events_attr,
+};
+
+static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
+
+static struct attribute *hisi_ddrc_pmu_cpumask_attrs[] = {
+ &dev_attr_cpumask.attr,
+ NULL,
+};
+
+static const struct attribute_group hisi_ddrc_pmu_cpumask_attr_group = {
+ .attrs = hisi_ddrc_pmu_cpumask_attrs,
+};
+
+static const struct attribute_group *hisi_ddrc_pmu_attr_groups[] = {
+ &hisi_ddrc_pmu_format_group,
+ &hisi_ddrc_pmu_events_group,
+ &hisi_ddrc_pmu_cpumask_attr_group,
+ NULL,
+};
+
+static const struct hisi_uncore_ops hisi_uncore_ddrc_ops = {
+ .write_evtype = hisi_ddrc_pmu_write_evtype,
+ .get_event_idx = hisi_ddrc_pmu_get_event_idx,
+ .start_counters = hisi_ddrc_pmu_start_counters,
+ .stop_counters = hisi_ddrc_pmu_stop_counters,
+ .enable_counter = hisi_ddrc_pmu_enable_counter,
+ .disable_counter = hisi_ddrc_pmu_disable_counter,
+ .enable_counter_int = hisi_ddrc_pmu_enable_counter_int,
+ .disable_counter_int = hisi_ddrc_pmu_disable_counter_int,
+ .write_counter = hisi_ddrc_pmu_write_counter,
+ .read_counter = hisi_ddrc_pmu_read_counter,
+};
+
+static int hisi_ddrc_pmu_dev_probe(struct platform_device *pdev,
+ struct hisi_pmu *ddrc_pmu)
+{
+ int ret;
+
+ ret = hisi_ddrc_pmu_init_data(pdev, ddrc_pmu);
+ if (ret)
+ return ret;
+
+ ret = hisi_ddrc_pmu_init_irq(ddrc_pmu, pdev);
+ if (ret)
+ return ret;
+
+ ddrc_pmu->num_counters = DDRC_NR_COUNTERS;
+ ddrc_pmu->counter_bits = 32;
+ ddrc_pmu->ops = &hisi_uncore_ddrc_ops;
+ ddrc_pmu->dev = &pdev->dev;
+ ddrc_pmu->on_cpu = -1;
+
+ return 0;
+}
+
+static int hisi_ddrc_pmu_probe(struct platform_device *pdev)
+{
+ struct hisi_pmu *ddrc_pmu;
+ char *name;
+ int ret;
+
+ ddrc_pmu = devm_kzalloc(&pdev->dev, sizeof(*ddrc_pmu), GFP_KERNEL);
+ if (!ddrc_pmu)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, ddrc_pmu);
+
+ ret = hisi_ddrc_pmu_dev_probe(pdev, ddrc_pmu);
+ if (ret)
+ return ret;
+
+ ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
+ &ddrc_pmu->node);
+ if (ret) {
+ dev_err(&pdev->dev, "Error %d registering hotplug;\n", ret);
+ return ret;
+ }
+
+ name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%u_ddrc%u",
+ ddrc_pmu->sccl_id, ddrc_pmu->id);
+ ddrc_pmu->pmu = (struct pmu) {
+ .name = name,
+ .task_ctx_nr = perf_invalid_context,
+ .event_init = hisi_uncore_pmu_event_init,
+ .pmu_enable = hisi_uncore_pmu_enable,
+ .pmu_disable = hisi_uncore_pmu_disable,
+ .add = hisi_uncore_pmu_add,
+ .del = hisi_uncore_pmu_del,
+ .start = hisi_uncore_pmu_start,
+ .stop = hisi_uncore_pmu_stop,
+ .read = hisi_uncore_pmu_read,
+ .attr_groups = hisi_ddrc_pmu_attr_groups,
+ };
+
+ ret = perf_pmu_register(&ddrc_pmu->pmu, name, -1);
+ if (ret) {
+ dev_err(ddrc_pmu->dev, "DDRC PMU register failed!\n");
+ cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
+ &ddrc_pmu->node);
+ }
+
+ return ret;
+}
+
+static int hisi_ddrc_pmu_remove(struct platform_device *pdev)
+{
+ struct hisi_pmu *ddrc_pmu = platform_get_drvdata(pdev);
+
+ perf_pmu_unregister(&ddrc_pmu->pmu);
+ cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
+ &ddrc_pmu->node);
+
+ return 0;
+}
+
+static struct platform_driver hisi_ddrc_pmu_driver = {
+ .driver = {
+ .name = "hisi_ddrc_pmu",
+ .acpi_match_table = ACPI_PTR(hisi_ddrc_pmu_acpi_match),
+ },
+ .probe = hisi_ddrc_pmu_probe,
+ .remove = hisi_ddrc_pmu_remove,
+};
+
+static int __init hisi_ddrc_pmu_module_init(void)
+{
+ int ret;
+
+ ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
+ "AP_PERF_ARM_HISI_DDRC_ONLINE",
+ hisi_uncore_pmu_online_cpu,
+ hisi_uncore_pmu_offline_cpu);
+ if (ret) {
+ pr_err("DDRC PMU: setup hotplug, ret = %d\n", ret);
+ return ret;
+ }
+
+ ret = platform_driver_register(&hisi_ddrc_pmu_driver);
+ if (ret)
+ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE);
+
+ return ret;
+}
+module_init(hisi_ddrc_pmu_module_init);
+
+static void __exit hisi_ddrc_pmu_module_exit(void)
+{
+ platform_driver_unregister(&hisi_ddrc_pmu_driver);
+ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE);
+
+}
+module_exit(hisi_ddrc_pmu_module_exit);
+
+MODULE_DESCRIPTION("HiSilicon SoC DDRC uncore PMU driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Shaokun Zhang <zhangshaokun@hisilicon.com>");
+MODULE_AUTHOR("Anurup M <anurup.m@huawei.com>");
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 85657ce..bd5cde6 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -134,6 +134,7 @@ enum cpuhp_state {
CPUHP_AP_PERF_S390_SF_ONLINE,
CPUHP_AP_PERF_ARM_CCI_ONLINE,
CPUHP_AP_PERF_ARM_CCN_ONLINE,
+ CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
CPUHP_AP_PERF_ARM_L2X0_ONLINE,
--
1.9.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 6/6] arm64: MAINTAINERS: hisi: Add HiSilicon SoC PMU support
2017-08-22 8:07 ` Shaokun Zhang
@ 2017-08-22 8:07 ` Shaokun Zhang
-1 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: mark.rutland, will.deacon
Cc: jonathan.cameron, linux-arm-kernel, linux-kernel, linux-doc,
linuxarm, Shaokun Zhang
Add support HiSilicon SoC uncore PMU driver.
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1c3feff..9d1ad57 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6147,6 +6147,13 @@ S: Maintained
F: drivers/net/ethernet/hisilicon/
F: Documentation/devicetree/bindings/net/hisilicon*.txt
+HISILICON PMU DRIVER
+M: Shaokun Zhang <zhangshaokun@hisilicon.com>
+W: http://www.hisilicon.com
+S: Supported
+F: drivers/perf/hisilicon
+F: Documentation/perf/hisi-pmu.txt
+
HISILICON ROCE DRIVER
M: Lijun Ou <oulijun@huawei.com>
M: Wei Hu(Xavier) <xavier.huwei@huawei.com>
--
1.9.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 6/6] arm64: MAINTAINERS: hisi: Add HiSilicon SoC PMU support
@ 2017-08-22 8:07 ` Shaokun Zhang
0 siblings, 0 replies; 40+ messages in thread
From: Shaokun Zhang @ 2017-08-22 8:07 UTC (permalink / raw)
To: linux-arm-kernel
Add support HiSilicon SoC uncore PMU driver.
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1c3feff..9d1ad57 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6147,6 +6147,13 @@ S: Maintained
F: drivers/net/ethernet/hisilicon/
F: Documentation/devicetree/bindings/net/hisilicon*.txt
+HISILICON PMU DRIVER
+M: Shaokun Zhang <zhangshaokun@hisilicon.com>
+W: http://www.hisilicon.com
+S: Supported
+F: drivers/perf/hisilicon
+F: Documentation/perf/hisi-pmu.txt
+
HISILICON ROCE DRIVER
M: Lijun Ou <oulijun@huawei.com>
M: Wei Hu(Xavier) <xavier.huwei@huawei.com>
--
1.9.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PATCH v5 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver
2017-08-22 8:07 ` Shaokun Zhang
@ 2017-08-29 12:28 ` Zhangshaokun
-1 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-08-29 12:28 UTC (permalink / raw)
To: mark.rutland, will.deacon
Cc: jonathan.cameron, linux-arm-kernel, linux-kernel, linux-doc, linuxarm
Hi Mark/Will,
Do you have any comments on this patch set? Appreciate your comments.
Thanks,
Shaokun
On 2017/8/22 16:07, Shaokun Zhang wrote:
> This patchset adds support for HiSilicon SoC uncore PMUs driver. It
> includes L3C, Hydra Home Agent (HHA) and DDRC.
>
> Changes in v5:
> * remove unnecessary name/num_events member in hisi_pmu
> * refactor hisi_pmu_hwevents structure
> * remove hisi_pmu_alloc function
> * revise cpuhotplug for L3C PMUs
> * add cpuhotplug for HHA/DDRC PMUs
> * fix the name format of uncore PMUs
> * remove unnecessary variants
>
> Changes in v4:
> * remove redundant code and comments
> * reverse the functions order in exit function
> * remove some GPL information
> * revise including header file
> * fix Jonathan's other comments
>
> Changes in v3:
> * rebase to 4.13-rc1
> * add dev_err if ioremap fails for PMUs
>
> Changes in v2:
> * fix kbuild test robot error
> * make hisi_uncore_ops static
>
> Shaokun Zhang (6):
> Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
> perf: hisi: Add support for HiSilicon SoC uncore PMU driver
> perf: hisi: Add support for HiSilicon SoC L3C PMU driver
> perf: hisi: Add support for HiSilicon SoC HHA PMU driver
> perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
> arm64: MAINTAINERS: hisi: Add HiSilicon SoC PMU support
>
> Documentation/perf/hisi-pmu.txt | 53 +++
> MAINTAINERS | 7 +
> drivers/perf/Kconfig | 7 +
> drivers/perf/Makefile | 1 +
> drivers/perf/hisilicon/Makefile | 1 +
> drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 467 +++++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 477 +++++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 482 ++++++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_pmu.c | 440 +++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_pmu.h | 107 ++++++
> include/linux/cpuhotplug.h | 3 +
> 11 files changed, 2045 insertions(+)
> create mode 100644 Documentation/perf/hisi-pmu.txt
> create mode 100644 drivers/perf/hisilicon/Makefile
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver
@ 2017-08-29 12:28 ` Zhangshaokun
0 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-08-29 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mark/Will,
Do you have any comments on this patch set? Appreciate your comments.
Thanks,
Shaokun
On 2017/8/22 16:07, Shaokun Zhang wrote:
> This patchset adds support for HiSilicon SoC uncore PMUs driver. It
> includes L3C, Hydra Home Agent (HHA) and DDRC.
>
> Changes in v5:
> * remove unnecessary name/num_events member in hisi_pmu
> * refactor hisi_pmu_hwevents structure
> * remove hisi_pmu_alloc function
> * revise cpuhotplug for L3C PMUs
> * add cpuhotplug for HHA/DDRC PMUs
> * fix the name format of uncore PMUs
> * remove unnecessary variants
>
> Changes in v4:
> * remove redundant code and comments
> * reverse the functions order in exit function
> * remove some GPL information
> * revise including header file
> * fix Jonathan's other comments
>
> Changes in v3:
> * rebase to 4.13-rc1
> * add dev_err if ioremap fails for PMUs
>
> Changes in v2:
> * fix kbuild test robot error
> * make hisi_uncore_ops static
>
> Shaokun Zhang (6):
> Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
> perf: hisi: Add support for HiSilicon SoC uncore PMU driver
> perf: hisi: Add support for HiSilicon SoC L3C PMU driver
> perf: hisi: Add support for HiSilicon SoC HHA PMU driver
> perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
> arm64: MAINTAINERS: hisi: Add HiSilicon SoC PMU support
>
> Documentation/perf/hisi-pmu.txt | 53 +++
> MAINTAINERS | 7 +
> drivers/perf/Kconfig | 7 +
> drivers/perf/Makefile | 1 +
> drivers/perf/hisilicon/Makefile | 1 +
> drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 467 +++++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 477 +++++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 482 ++++++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_pmu.c | 440 +++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_pmu.h | 107 ++++++
> include/linux/cpuhotplug.h | 3 +
> 11 files changed, 2045 insertions(+)
> create mode 100644 Documentation/perf/hisi-pmu.txt
> create mode 100644 drivers/perf/hisilicon/Makefile
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver
2017-08-22 8:07 ` Shaokun Zhang
@ 2017-09-21 10:40 ` Zhangshaokun
-1 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-09-21 10:40 UTC (permalink / raw)
To: mark.rutland, will.deacon
Cc: jonathan.cameron, linux-arm-kernel, linux-kernel, linux-doc, linuxarm
Hi Mark/Will,
Appreciate any comments from you.
Thanks,
Shaokun
On 2017/8/22 16:07, Shaokun Zhang wrote:
> This patchset adds support for HiSilicon SoC uncore PMUs driver. It
> includes L3C, Hydra Home Agent (HHA) and DDRC.
>
> Changes in v5:
> * remove unnecessary name/num_events member in hisi_pmu
> * refactor hisi_pmu_hwevents structure
> * remove hisi_pmu_alloc function
> * revise cpuhotplug for L3C PMUs
> * add cpuhotplug for HHA/DDRC PMUs
> * fix the name format of uncore PMUs
> * remove unnecessary variants
>
> Changes in v4:
> * remove redundant code and comments
> * reverse the functions order in exit function
> * remove some GPL information
> * revise including header file
> * fix Jonathan's other comments
>
> Changes in v3:
> * rebase to 4.13-rc1
> * add dev_err if ioremap fails for PMUs
>
> Changes in v2:
> * fix kbuild test robot error
> * make hisi_uncore_ops static
>
> Shaokun Zhang (6):
> Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
> perf: hisi: Add support for HiSilicon SoC uncore PMU driver
> perf: hisi: Add support for HiSilicon SoC L3C PMU driver
> perf: hisi: Add support for HiSilicon SoC HHA PMU driver
> perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
> arm64: MAINTAINERS: hisi: Add HiSilicon SoC PMU support
>
> Documentation/perf/hisi-pmu.txt | 53 +++
> MAINTAINERS | 7 +
> drivers/perf/Kconfig | 7 +
> drivers/perf/Makefile | 1 +
> drivers/perf/hisilicon/Makefile | 1 +
> drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 467 +++++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 477 +++++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 482 ++++++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_pmu.c | 440 +++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_pmu.h | 107 ++++++
> include/linux/cpuhotplug.h | 3 +
> 11 files changed, 2045 insertions(+)
> create mode 100644 Documentation/perf/hisi-pmu.txt
> create mode 100644 drivers/perf/hisilicon/Makefile
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver
@ 2017-09-21 10:40 ` Zhangshaokun
0 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-09-21 10:40 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mark/Will,
Appreciate any comments from you.
Thanks,
Shaokun
On 2017/8/22 16:07, Shaokun Zhang wrote:
> This patchset adds support for HiSilicon SoC uncore PMUs driver. It
> includes L3C, Hydra Home Agent (HHA) and DDRC.
>
> Changes in v5:
> * remove unnecessary name/num_events member in hisi_pmu
> * refactor hisi_pmu_hwevents structure
> * remove hisi_pmu_alloc function
> * revise cpuhotplug for L3C PMUs
> * add cpuhotplug for HHA/DDRC PMUs
> * fix the name format of uncore PMUs
> * remove unnecessary variants
>
> Changes in v4:
> * remove redundant code and comments
> * reverse the functions order in exit function
> * remove some GPL information
> * revise including header file
> * fix Jonathan's other comments
>
> Changes in v3:
> * rebase to 4.13-rc1
> * add dev_err if ioremap fails for PMUs
>
> Changes in v2:
> * fix kbuild test robot error
> * make hisi_uncore_ops static
>
> Shaokun Zhang (6):
> Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
> perf: hisi: Add support for HiSilicon SoC uncore PMU driver
> perf: hisi: Add support for HiSilicon SoC L3C PMU driver
> perf: hisi: Add support for HiSilicon SoC HHA PMU driver
> perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
> arm64: MAINTAINERS: hisi: Add HiSilicon SoC PMU support
>
> Documentation/perf/hisi-pmu.txt | 53 +++
> MAINTAINERS | 7 +
> drivers/perf/Kconfig | 7 +
> drivers/perf/Makefile | 1 +
> drivers/perf/hisilicon/Makefile | 1 +
> drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 467 +++++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 477 +++++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 482 ++++++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_pmu.c | 440 +++++++++++++++++++++++
> drivers/perf/hisilicon/hisi_uncore_pmu.h | 107 ++++++
> include/linux/cpuhotplug.h | 3 +
> 11 files changed, 2045 insertions(+)
> create mode 100644 Documentation/perf/hisi-pmu.txt
> create mode 100644 drivers/perf/hisilicon/Makefile
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c
> create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver
2017-09-21 10:40 ` Zhangshaokun
@ 2017-10-09 8:17 ` Zhangshaokun
-1 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-10-09 8:17 UTC (permalink / raw)
To: mark.rutland, will.deacon
Cc: jonathan.cameron, linux-arm-kernel, linux-kernel, linux-doc,
linuxarm, John Garry
Hi All,
Do you have any comments on this patch set?
Thanks,
Shaokun
On 2017/9/21 18:40, Zhangshaokun wrote:
> Hi Mark/Will,
>
> Appreciate any comments from you.
>
> Thanks,
> Shaokun
>
> On 2017/8/22 16:07, Shaokun Zhang wrote:
>> This patchset adds support for HiSilicon SoC uncore PMUs driver. It
>> includes L3C, Hydra Home Agent (HHA) and DDRC.
>>
>> Changes in v5:
>> * remove unnecessary name/num_events member in hisi_pmu
>> * refactor hisi_pmu_hwevents structure
>> * remove hisi_pmu_alloc function
>> * revise cpuhotplug for L3C PMUs
>> * add cpuhotplug for HHA/DDRC PMUs
>> * fix the name format of uncore PMUs
>> * remove unnecessary variants
>>
>> Changes in v4:
>> * remove redundant code and comments
>> * reverse the functions order in exit function
>> * remove some GPL information
>> * revise including header file
>> * fix Jonathan's other comments
>>
>> Changes in v3:
>> * rebase to 4.13-rc1
>> * add dev_err if ioremap fails for PMUs
>>
>> Changes in v2:
>> * fix kbuild test robot error
>> * make hisi_uncore_ops static
>>
>> Shaokun Zhang (6):
>> Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
>> perf: hisi: Add support for HiSilicon SoC uncore PMU driver
>> perf: hisi: Add support for HiSilicon SoC L3C PMU driver
>> perf: hisi: Add support for HiSilicon SoC HHA PMU driver
>> perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
>> arm64: MAINTAINERS: hisi: Add HiSilicon SoC PMU support
>>
>> Documentation/perf/hisi-pmu.txt | 53 +++
>> MAINTAINERS | 7 +
>> drivers/perf/Kconfig | 7 +
>> drivers/perf/Makefile | 1 +
>> drivers/perf/hisilicon/Makefile | 1 +
>> drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 467 +++++++++++++++++++++++++
>> drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 477 +++++++++++++++++++++++++
>> drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 482 ++++++++++++++++++++++++++
>> drivers/perf/hisilicon/hisi_uncore_pmu.c | 440 +++++++++++++++++++++++
>> drivers/perf/hisilicon/hisi_uncore_pmu.h | 107 ++++++
>> include/linux/cpuhotplug.h | 3 +
>> 11 files changed, 2045 insertions(+)
>> create mode 100644 Documentation/perf/hisi-pmu.txt
>> create mode 100644 drivers/perf/hisilicon/Makefile
>> create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
>> create mode 100644 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
>> create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
>> create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c
>> create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h
>>
>
>
> .
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver
@ 2017-10-09 8:17 ` Zhangshaokun
0 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-10-09 8:17 UTC (permalink / raw)
To: linux-arm-kernel
Hi All,
Do you have any comments on this patch set?
Thanks,
Shaokun
On 2017/9/21 18:40, Zhangshaokun wrote:
> Hi Mark/Will,
>
> Appreciate any comments from you.
>
> Thanks,
> Shaokun
>
> On 2017/8/22 16:07, Shaokun Zhang wrote:
>> This patchset adds support for HiSilicon SoC uncore PMUs driver. It
>> includes L3C, Hydra Home Agent (HHA) and DDRC.
>>
>> Changes in v5:
>> * remove unnecessary name/num_events member in hisi_pmu
>> * refactor hisi_pmu_hwevents structure
>> * remove hisi_pmu_alloc function
>> * revise cpuhotplug for L3C PMUs
>> * add cpuhotplug for HHA/DDRC PMUs
>> * fix the name format of uncore PMUs
>> * remove unnecessary variants
>>
>> Changes in v4:
>> * remove redundant code and comments
>> * reverse the functions order in exit function
>> * remove some GPL information
>> * revise including header file
>> * fix Jonathan's other comments
>>
>> Changes in v3:
>> * rebase to 4.13-rc1
>> * add dev_err if ioremap fails for PMUs
>>
>> Changes in v2:
>> * fix kbuild test robot error
>> * make hisi_uncore_ops static
>>
>> Shaokun Zhang (6):
>> Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
>> perf: hisi: Add support for HiSilicon SoC uncore PMU driver
>> perf: hisi: Add support for HiSilicon SoC L3C PMU driver
>> perf: hisi: Add support for HiSilicon SoC HHA PMU driver
>> perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
>> arm64: MAINTAINERS: hisi: Add HiSilicon SoC PMU support
>>
>> Documentation/perf/hisi-pmu.txt | 53 +++
>> MAINTAINERS | 7 +
>> drivers/perf/Kconfig | 7 +
>> drivers/perf/Makefile | 1 +
>> drivers/perf/hisilicon/Makefile | 1 +
>> drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 467 +++++++++++++++++++++++++
>> drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 477 +++++++++++++++++++++++++
>> drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 482 ++++++++++++++++++++++++++
>> drivers/perf/hisilicon/hisi_uncore_pmu.c | 440 +++++++++++++++++++++++
>> drivers/perf/hisilicon/hisi_uncore_pmu.h | 107 ++++++
>> include/linux/cpuhotplug.h | 3 +
>> 11 files changed, 2045 insertions(+)
>> create mode 100644 Documentation/perf/hisi-pmu.txt
>> create mode 100644 drivers/perf/hisilicon/Makefile
>> create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
>> create mode 100644 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
>> create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
>> create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c
>> create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h
>>
>
>
> .
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 2/6] perf: hisi: Add support for HiSilicon SoC uncore PMU driver
2017-08-22 8:07 ` Shaokun Zhang
@ 2017-10-17 15:06 ` Mark Rutland
-1 siblings, 0 replies; 40+ messages in thread
From: Mark Rutland @ 2017-10-17 15:06 UTC (permalink / raw)
To: Shaokun Zhang
Cc: will.deacon, jonathan.cameron, linux-arm-kernel, linux-kernel,
linux-doc, linuxarm, Anurup M
Hi,
Apologies for the delay for this review.
Largely this seems to look OK, but there are a couple of things which
stick out.
On Tue, Aug 22, 2017 at 04:07:53PM +0800, Shaokun Zhang wrote:
> +int hisi_uncore_pmu_event_init(struct perf_event *event)
> +{
> + struct hw_perf_event *hwc = &event->hw;
> + struct hisi_pmu *hisi_pmu;
> +
> + if (event->attr.type != event->pmu->type)
> + return -ENOENT;
> +
> + /*
> + * We do not support sampling as the counters are all
> + * shared by all CPU cores in a CPU die(SCCL). Also we
> + * do not support attach to a task(per-process mode)
> + */
> + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
> + return -EOPNOTSUPP;
> +
> + /* counters do not have these bits */
> + if (event->attr.exclude_user ||
> + event->attr.exclude_kernel ||
> + event->attr.exclude_host ||
> + event->attr.exclude_guest ||
> + event->attr.exclude_hv ||
> + event->attr.exclude_idle)
> + return -EINVAL;
> +
> + /*
> + * The uncore counters not specific to any CPU, so cannot
> + * support per-task
> + */
> + if (event->cpu < 0)
> + return -EINVAL;
> +
> + /*
> + * Validate if the events in group does not exceed the
> + * available counters in hardware.
> + */
> + if (!hisi_validate_event_group(event))
> + return -EINVAL;
> +
> + /*
> + * We don't assign an index until we actually place the event onto
> + * hardware. Use -1 to signify that we haven't decided where to put it
> + * yet.
> + */
> + hwc->idx = -1;
> + hwc->config_base = event->attr.config;
Are all event codes valid?
e.g. is it possible that some value passed by the user would cause a
problem were it written to the hardware?
I see that you only use the low 8 bits of the config field elsewhere, so
it might make sense to sanity check that here rather than having to mask
it elsewhere.
That would make future extension safer, since no-one could be relying on
passing a dodgy value in.
> +
> + hisi_pmu = to_hisi_pmu(event->pmu);
> + /* Enforce to use the same CPU for all events in this PMU */
> + event->cpu = hisi_pmu->on_cpu;
I think you need to check hisi_pmu->on_cpu != -1, otherwise we can
accidentally create a task-bound event if a cluster is offline, and I'm
not sure how the perf core code would handle here.
> +
> + return 0;
> +}
[...]
> +int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
> +{
> + struct hisi_pmu *hisi_pmu;
> +
> + hisi_pmu = hlist_entry_safe(node, struct hisi_pmu, node);
> +
> + /*
> + * If the CPU is associated with the PMU, set it in online_cpus of
> + * the PMU.
> + */
> + if (cpumask_test_cpu(cpu, &hisi_pmu->associated_cpus))
> + cpumask_set_cpu(cpu, &hisi_pmu->online_cpus);
> + else
> + return 0;
This would be a bit nicer as:
if (!cpumask_test_cpu(cpu, &hisi_pmu->associated_cpus))
return 0;
cpumask_set_cpu(cpu, &hisi_pmu->online_cpus);
However, I don't think you need hisi_pmu::online_cpus. That's only used
for the online/offline callbacks, and you can use the
hisi_pmu::associated_cpus mask in hisi_uncore_pmu_offline_cpu(), and
avoid altering any mask here.
> +
> + /* If another CPU is already managing this PMU, simply return. */
> + if (hisi_pmu->on_cpu != -1)
> + return 0;
> +
> + /* Use this CPU in cpumask for event counting */
> + hisi_pmu->on_cpu = cpu;
> +
> + /* Overflow interrupt also should use the same CPU */
> + WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(cpu)));
> +
> + return 0;
> +}
> +
> +int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
> +{
> + struct hisi_pmu *hisi_pmu;
> + cpumask_t pmu_online_cpus;
> + unsigned int target;
> +
> + hisi_pmu = hlist_entry_safe(node, struct hisi_pmu, node);
> +
> + /*
> + * If the CPU is online with the PMU, clear it in online_cpus of
> + * the PMU.
> + */
> + if (!cpumask_test_and_clear_cpu(cpu, &hisi_pmu->online_cpus) ||
> + (hisi_pmu->on_cpu != cpu))
> + return 0;
> +
> + hisi_pmu->on_cpu = -1;
> +
> + /* Any other CPU associated with the PMU is still online */
> + cpumask_and(&pmu_online_cpus, &hisi_pmu->online_cpus, cpu_online_mask);
> + target = cpumask_any_but(&pmu_online_cpus, cpu);
> + if (target >= nr_cpu_ids)
> + return 0;
I think you can get rid of hisi_pmu::online_cpus, and replace the mask
manipulation above with:
/* Nothing to do if this CPU doesn't own the PMU */
if (hisi_pmu->on_cpu != cpu)
return 0;
/* Give up ownership of the PMU */
hisi_pmu->on_cpu = -1;
/* Choose a new CPU to migrate ownership of the PMU to */
cpumask_and(&pmu_online_cpus, &hisi_pmu->associated_cpus,
cpu_online_mask)
target = cpumask_any_but(&pmu_online_cpus, cpu);
if (target >= nr_cpu_ids)
return 0;
> +
> + perf_pmu_migrate_context(&hisi_pmu->pmu, cpu, target);
> + /* Use this CPU for event counting */
> + hisi_pmu->on_cpu = target;
> + WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(target)));
> +
> + return 0;
> +}
> +
> +/*
> + * Check whether the CPU is associated with this uncore PMU by SCCL_ID,
> + * if true, set the associated cpumask of the uncore PMU.
> + */
> +void hisi_uncore_pmu_set_cpumask_by_sccl(void *arg)
Perhaps:
hisi_uncore_pmu_check_associate_cpu(struct hisi_pmu *pmu)
It's not clear to me why the arg is a void pointer.
> +{
> + struct hisi_pmu *hisi_pmu = (struct hisi_pmu *)arg;
This cast shouldn't be necessary.
> + u32 sccl_id;
> +
> + hisi_read_sccl_and_ccl_id(&sccl_id, NULL);
> + if (sccl_id == hisi_pmu->sccl_id)
> + cpumask_set_cpu(smp_processor_id(), &hisi_pmu->associated_cpus);
> +}
[...]
> +/* Generic pmu struct for different pmu types */
> +struct hisi_pmu {
> + struct pmu pmu;
> + const struct hisi_uncore_ops *ops;
> + struct hisi_pmu_hwevents pmu_events;
> + /*
> + * online_cpus: All online CPUs associated with the PMU
> + * associated_cpus: All CPUs associated with the PMU who is
> + * initialised when probe.
> + */
> + cpumask_t online_cpus, associated_cpus;
> + /* CPU used for counting */
> + int on_cpu;
> + int irq;
> + struct device *dev;
> + struct hlist_node node;
> + u32 sccl_id;
> + u32 ccl_id;
> + /* Hardware information for different pmu types */
> + void __iomem *base;
> + /* the ID of the PMU modules */
> + u32 id;
Is this what hte documentation referred to as the index-id?
It might make sense to call it index_id.
> + int num_counters;
> + int counter_bits;
> +};
Thanks,
Mark.
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 2/6] perf: hisi: Add support for HiSilicon SoC uncore PMU driver
@ 2017-10-17 15:06 ` Mark Rutland
0 siblings, 0 replies; 40+ messages in thread
From: Mark Rutland @ 2017-10-17 15:06 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Apologies for the delay for this review.
Largely this seems to look OK, but there are a couple of things which
stick out.
On Tue, Aug 22, 2017 at 04:07:53PM +0800, Shaokun Zhang wrote:
> +int hisi_uncore_pmu_event_init(struct perf_event *event)
> +{
> + struct hw_perf_event *hwc = &event->hw;
> + struct hisi_pmu *hisi_pmu;
> +
> + if (event->attr.type != event->pmu->type)
> + return -ENOENT;
> +
> + /*
> + * We do not support sampling as the counters are all
> + * shared by all CPU cores in a CPU die(SCCL). Also we
> + * do not support attach to a task(per-process mode)
> + */
> + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
> + return -EOPNOTSUPP;
> +
> + /* counters do not have these bits */
> + if (event->attr.exclude_user ||
> + event->attr.exclude_kernel ||
> + event->attr.exclude_host ||
> + event->attr.exclude_guest ||
> + event->attr.exclude_hv ||
> + event->attr.exclude_idle)
> + return -EINVAL;
> +
> + /*
> + * The uncore counters not specific to any CPU, so cannot
> + * support per-task
> + */
> + if (event->cpu < 0)
> + return -EINVAL;
> +
> + /*
> + * Validate if the events in group does not exceed the
> + * available counters in hardware.
> + */
> + if (!hisi_validate_event_group(event))
> + return -EINVAL;
> +
> + /*
> + * We don't assign an index until we actually place the event onto
> + * hardware. Use -1 to signify that we haven't decided where to put it
> + * yet.
> + */
> + hwc->idx = -1;
> + hwc->config_base = event->attr.config;
Are all event codes valid?
e.g. is it possible that some value passed by the user would cause a
problem were it written to the hardware?
I see that you only use the low 8 bits of the config field elsewhere, so
it might make sense to sanity check that here rather than having to mask
it elsewhere.
That would make future extension safer, since no-one could be relying on
passing a dodgy value in.
> +
> + hisi_pmu = to_hisi_pmu(event->pmu);
> + /* Enforce to use the same CPU for all events in this PMU */
> + event->cpu = hisi_pmu->on_cpu;
I think you need to check hisi_pmu->on_cpu != -1, otherwise we can
accidentally create a task-bound event if a cluster is offline, and I'm
not sure how the perf core code would handle here.
> +
> + return 0;
> +}
[...]
> +int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
> +{
> + struct hisi_pmu *hisi_pmu;
> +
> + hisi_pmu = hlist_entry_safe(node, struct hisi_pmu, node);
> +
> + /*
> + * If the CPU is associated with the PMU, set it in online_cpus of
> + * the PMU.
> + */
> + if (cpumask_test_cpu(cpu, &hisi_pmu->associated_cpus))
> + cpumask_set_cpu(cpu, &hisi_pmu->online_cpus);
> + else
> + return 0;
This would be a bit nicer as:
if (!cpumask_test_cpu(cpu, &hisi_pmu->associated_cpus))
return 0;
cpumask_set_cpu(cpu, &hisi_pmu->online_cpus);
However, I don't think you need hisi_pmu::online_cpus. That's only used
for the online/offline callbacks, and you can use the
hisi_pmu::associated_cpus mask in hisi_uncore_pmu_offline_cpu(), and
avoid altering any mask here.
> +
> + /* If another CPU is already managing this PMU, simply return. */
> + if (hisi_pmu->on_cpu != -1)
> + return 0;
> +
> + /* Use this CPU in cpumask for event counting */
> + hisi_pmu->on_cpu = cpu;
> +
> + /* Overflow interrupt also should use the same CPU */
> + WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(cpu)));
> +
> + return 0;
> +}
> +
> +int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
> +{
> + struct hisi_pmu *hisi_pmu;
> + cpumask_t pmu_online_cpus;
> + unsigned int target;
> +
> + hisi_pmu = hlist_entry_safe(node, struct hisi_pmu, node);
> +
> + /*
> + * If the CPU is online with the PMU, clear it in online_cpus of
> + * the PMU.
> + */
> + if (!cpumask_test_and_clear_cpu(cpu, &hisi_pmu->online_cpus) ||
> + (hisi_pmu->on_cpu != cpu))
> + return 0;
> +
> + hisi_pmu->on_cpu = -1;
> +
> + /* Any other CPU associated with the PMU is still online */
> + cpumask_and(&pmu_online_cpus, &hisi_pmu->online_cpus, cpu_online_mask);
> + target = cpumask_any_but(&pmu_online_cpus, cpu);
> + if (target >= nr_cpu_ids)
> + return 0;
I think you can get rid of hisi_pmu::online_cpus, and replace the mask
manipulation above with:
/* Nothing to do if this CPU doesn't own the PMU */
if (hisi_pmu->on_cpu != cpu)
return 0;
/* Give up ownership of the PMU */
hisi_pmu->on_cpu = -1;
/* Choose a new CPU to migrate ownership of the PMU to */
cpumask_and(&pmu_online_cpus, &hisi_pmu->associated_cpus,
cpu_online_mask)
target = cpumask_any_but(&pmu_online_cpus, cpu);
if (target >= nr_cpu_ids)
return 0;
> +
> + perf_pmu_migrate_context(&hisi_pmu->pmu, cpu, target);
> + /* Use this CPU for event counting */
> + hisi_pmu->on_cpu = target;
> + WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(target)));
> +
> + return 0;
> +}
> +
> +/*
> + * Check whether the CPU is associated with this uncore PMU by SCCL_ID,
> + * if true, set the associated cpumask of the uncore PMU.
> + */
> +void hisi_uncore_pmu_set_cpumask_by_sccl(void *arg)
Perhaps:
hisi_uncore_pmu_check_associate_cpu(struct hisi_pmu *pmu)
It's not clear to me why the arg is a void pointer.
> +{
> + struct hisi_pmu *hisi_pmu = (struct hisi_pmu *)arg;
This cast shouldn't be necessary.
> + u32 sccl_id;
> +
> + hisi_read_sccl_and_ccl_id(&sccl_id, NULL);
> + if (sccl_id == hisi_pmu->sccl_id)
> + cpumask_set_cpu(smp_processor_id(), &hisi_pmu->associated_cpus);
> +}
[...]
> +/* Generic pmu struct for different pmu types */
> +struct hisi_pmu {
> + struct pmu pmu;
> + const struct hisi_uncore_ops *ops;
> + struct hisi_pmu_hwevents pmu_events;
> + /*
> + * online_cpus: All online CPUs associated with the PMU
> + * associated_cpus: All CPUs associated with the PMU who is
> + * initialised when probe.
> + */
> + cpumask_t online_cpus, associated_cpus;
> + /* CPU used for counting */
> + int on_cpu;
> + int irq;
> + struct device *dev;
> + struct hlist_node node;
> + u32 sccl_id;
> + u32 ccl_id;
> + /* Hardware information for different pmu types */
> + void __iomem *base;
> + /* the ID of the PMU modules */
> + u32 id;
Is this what hte documentation referred to as the index-id?
It might make sense to call it index_id.
> + int num_counters;
> + int counter_bits;
> +};
Thanks,
Mark.
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver
2017-08-22 8:07 ` Shaokun Zhang
@ 2017-10-17 15:16 ` Mark Rutland
-1 siblings, 0 replies; 40+ messages in thread
From: Mark Rutland @ 2017-10-17 15:16 UTC (permalink / raw)
To: Shaokun Zhang
Cc: will.deacon, jonathan.cameron, linux-arm-kernel, linux-kernel,
linux-doc, linuxarm, Anurup M
On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote:
> +static int hisi_l3c_pmu_init_irq(struct hisi_pmu *l3c_pmu,
> + struct platform_device *pdev)
> +{
> + int irq, ret;
> +
> + /* Read and init IRQ */
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0) {
> + dev_err(&pdev->dev, "L3C PMU get irq fail; irq:%d\n", irq);
> + return irq;
> + }
> +
> + ret = devm_request_irq(&pdev->dev, irq, hisi_l3c_pmu_isr,
> + IRQF_NOBALANCING | IRQF_NO_THREAD,
> + dev_name(&pdev->dev), l3c_pmu);
> + if (ret < 0) {
> + dev_err(&pdev->dev,
> + "Fail to request IRQ:%d ret:%d\n", irq, ret);
> + return ret;
> + }
> +
> + l3c_pmu->irq = irq;
> +
> + return 0;
> +}
> +
> +/*
> + * Check whether the CPU is associated with this L3C PMU by SCCL_ID
> + * and CCL_ID, if true, set the associated cpumask of the L3C PMU.
> + */
> +static void hisi_l3c_pmu_set_cpumask_by_ccl(void *arg)
> +{
> + struct hisi_pmu *l3c_pmu = (struct hisi_pmu *)arg;
> + u32 ccl_id, sccl_id;
> +
> + hisi_read_sccl_and_ccl_id(&sccl_id, &ccl_id);
> + if (sccl_id == l3c_pmu->sccl_id && ccl_id == l3c_pmu->ccl_id)
> + cpumask_set_cpu(smp_processor_id(), &l3c_pmu->associated_cpus);
> +}
The shared code has hisi_uncore_pmu_set_cpumask_by_sccl(), and it would
be nice to place this in the same place.
Otherwise, the same comments apply here.
> +
> +static const struct acpi_device_id hisi_l3c_pmu_acpi_match[] = {
> + { "HISI0213", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(acpi, hisi_l3c_pmu_acpi_match);
> +
> +static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
> + struct hisi_pmu *l3c_pmu)
> +{
> + unsigned long long id;
> + struct resource *res;
> + acpi_status status;
> + int cpu;
> +
> + status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
> + "_UID", NULL, &id);
> + if (ACPI_FAILURE(status))
> + return -EINVAL;
> +
> + l3c_pmu->id = id;
> +
> + /*
> + * Use the SCCL_ID and CCL_ID to identify the L3C PMU, while
> + * SCCL_ID is in MPIDR[aff2] and CCL_ID is in MPIDR[aff1].
> + */
> + if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
> + &l3c_pmu->sccl_id)) {
> + dev_err(&pdev->dev, "Can not read l3c sccl-id!\n");
> + return -EINVAL;
> + }
> +
> + if (device_property_read_u32(&pdev->dev, "hisilicon,ccl-id",
> + &l3c_pmu->ccl_id)) {
> + dev_err(&pdev->dev, "Can not read l3c ccl-id!\n");
> + return -EINVAL;
> + }
> +
> + /* Initialise the associated cpumask of the PMU */
> + for_each_present_cpu(cpu)
> + smp_call_function_single(cpu, hisi_l3c_pmu_set_cpumask_by_ccl,
> + (void *)l3c_pmu, 1);
Ah, so that's why hisi_uncore_pmu_set_cpumask_by_sccl took a void
pointer.
Please drop a comment above hisi_uncore_pmu_set_cpumask_by_sccl to cover
that.
I think you can drop the void cast here; I don't beleive it is
necessary.
Rather than a proble-time smp_call_function_single(), can you follow the
qcom l2's approach of associating CPUs with a PMU instance in the
notifier? That will work even if CPUs are brought online very late.
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + l3c_pmu->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(l3c_pmu->base)) {
> + dev_err(&pdev->dev, "ioremap failed for l3c_pmu resource\n");
> + return PTR_ERR(l3c_pmu->base);
> + }
> +
> + return 0;
> +}
Thanks,
Mark.
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver
@ 2017-10-17 15:16 ` Mark Rutland
0 siblings, 0 replies; 40+ messages in thread
From: Mark Rutland @ 2017-10-17 15:16 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote:
> +static int hisi_l3c_pmu_init_irq(struct hisi_pmu *l3c_pmu,
> + struct platform_device *pdev)
> +{
> + int irq, ret;
> +
> + /* Read and init IRQ */
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0) {
> + dev_err(&pdev->dev, "L3C PMU get irq fail; irq:%d\n", irq);
> + return irq;
> + }
> +
> + ret = devm_request_irq(&pdev->dev, irq, hisi_l3c_pmu_isr,
> + IRQF_NOBALANCING | IRQF_NO_THREAD,
> + dev_name(&pdev->dev), l3c_pmu);
> + if (ret < 0) {
> + dev_err(&pdev->dev,
> + "Fail to request IRQ:%d ret:%d\n", irq, ret);
> + return ret;
> + }
> +
> + l3c_pmu->irq = irq;
> +
> + return 0;
> +}
> +
> +/*
> + * Check whether the CPU is associated with this L3C PMU by SCCL_ID
> + * and CCL_ID, if true, set the associated cpumask of the L3C PMU.
> + */
> +static void hisi_l3c_pmu_set_cpumask_by_ccl(void *arg)
> +{
> + struct hisi_pmu *l3c_pmu = (struct hisi_pmu *)arg;
> + u32 ccl_id, sccl_id;
> +
> + hisi_read_sccl_and_ccl_id(&sccl_id, &ccl_id);
> + if (sccl_id == l3c_pmu->sccl_id && ccl_id == l3c_pmu->ccl_id)
> + cpumask_set_cpu(smp_processor_id(), &l3c_pmu->associated_cpus);
> +}
The shared code has hisi_uncore_pmu_set_cpumask_by_sccl(), and it would
be nice to place this in the same place.
Otherwise, the same comments apply here.
> +
> +static const struct acpi_device_id hisi_l3c_pmu_acpi_match[] = {
> + { "HISI0213", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(acpi, hisi_l3c_pmu_acpi_match);
> +
> +static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
> + struct hisi_pmu *l3c_pmu)
> +{
> + unsigned long long id;
> + struct resource *res;
> + acpi_status status;
> + int cpu;
> +
> + status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
> + "_UID", NULL, &id);
> + if (ACPI_FAILURE(status))
> + return -EINVAL;
> +
> + l3c_pmu->id = id;
> +
> + /*
> + * Use the SCCL_ID and CCL_ID to identify the L3C PMU, while
> + * SCCL_ID is in MPIDR[aff2] and CCL_ID is in MPIDR[aff1].
> + */
> + if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
> + &l3c_pmu->sccl_id)) {
> + dev_err(&pdev->dev, "Can not read l3c sccl-id!\n");
> + return -EINVAL;
> + }
> +
> + if (device_property_read_u32(&pdev->dev, "hisilicon,ccl-id",
> + &l3c_pmu->ccl_id)) {
> + dev_err(&pdev->dev, "Can not read l3c ccl-id!\n");
> + return -EINVAL;
> + }
> +
> + /* Initialise the associated cpumask of the PMU */
> + for_each_present_cpu(cpu)
> + smp_call_function_single(cpu, hisi_l3c_pmu_set_cpumask_by_ccl,
> + (void *)l3c_pmu, 1);
Ah, so that's why hisi_uncore_pmu_set_cpumask_by_sccl took a void
pointer.
Please drop a comment above hisi_uncore_pmu_set_cpumask_by_sccl to cover
that.
I think you can drop the void cast here; I don't beleive it is
necessary.
Rather than a proble-time smp_call_function_single(), can you follow the
qcom l2's approach of associating CPUs with a PMU instance in the
notifier? That will work even if CPUs are brought online very late.
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + l3c_pmu->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(l3c_pmu->base)) {
> + dev_err(&pdev->dev, "ioremap failed for l3c_pmu resource\n");
> + return PTR_ERR(l3c_pmu->base);
> + }
> +
> + return 0;
> +}
Thanks,
Mark.
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver
2017-08-22 8:07 ` Shaokun Zhang
@ 2017-10-17 15:18 ` Mark Rutland
-1 siblings, 0 replies; 40+ messages in thread
From: Mark Rutland @ 2017-10-17 15:18 UTC (permalink / raw)
To: Shaokun Zhang
Cc: will.deacon, jonathan.cameron, linux-arm-kernel, linux-kernel,
linux-doc, linuxarm, Anurup M
On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote:
> L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
> SoC. This patch adds support for HHA PMU driver, Each HHA has own
> control, counter and interrupt registers and is an separate PMU. For
> each HHA PMU, it has 16-programable counters and each counter is
> free-running. Interrupt is supported to handle counter (48-bits)
> overflow.
My comments here are the same as for the L3C PMU driver.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver
@ 2017-10-17 15:18 ` Mark Rutland
0 siblings, 0 replies; 40+ messages in thread
From: Mark Rutland @ 2017-10-17 15:18 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote:
> L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
> SoC. This patch adds support for HHA PMU driver, Each HHA has own
> control, counter and interrupt registers and is an separate PMU. For
> each HHA PMU, it has 16-programable counters and each counter is
> free-running. Interrupt is supported to handle counter (48-bits)
> overflow.
My comments here are the same as for the L3C PMU driver.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 5/6] perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
2017-08-22 8:07 ` Shaokun Zhang
@ 2017-10-17 15:21 ` Mark Rutland
-1 siblings, 0 replies; 40+ messages in thread
From: Mark Rutland @ 2017-10-17 15:21 UTC (permalink / raw)
To: Shaokun Zhang
Cc: will.deacon, jonathan.cameron, linux-arm-kernel, linux-kernel,
linux-doc, linuxarm, Anurup M
On Tue, Aug 22, 2017 at 04:07:56PM +0800, Shaokun Zhang wrote:
> This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
> DDRC has own control, counter and interrupt registers and is an separate
> PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been
> mapped to 8-events by hardware, it assumes that counter index is equal
> to event code (0 - 7) in DDRC PMU driver. Interrupt is supported to
> handle counter (32-bits) overflow.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> Signed-off-by: Anurup M <anurup.m@huawei.com>
I have the same comments for this case as for the other two PMU drivers.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 5/6] perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
@ 2017-10-17 15:21 ` Mark Rutland
0 siblings, 0 replies; 40+ messages in thread
From: Mark Rutland @ 2017-10-17 15:21 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Aug 22, 2017 at 04:07:56PM +0800, Shaokun Zhang wrote:
> This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
> DDRC has own control, counter and interrupt registers and is an separate
> PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been
> mapped to 8-events by hardware, it assumes that counter index is equal
> to event code (0 - 7) in DDRC PMU driver. Interrupt is supported to
> handle counter (32-bits) overflow.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> Signed-off-by: Anurup M <anurup.m@huawei.com>
I have the same comments for this case as for the other two PMU drivers.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 2/6] perf: hisi: Add support for HiSilicon SoC uncore PMU driver
2017-10-17 15:06 ` Mark Rutland
@ 2017-10-18 13:19 ` Zhangshaokun
-1 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-10-18 13:19 UTC (permalink / raw)
To: Mark Rutland
Cc: will.deacon, jonathan.cameron, linux-arm-kernel, linux-kernel,
linux-doc, linuxarm, Anurup M
Hi Mark,
Thanks for your comments.
On 2017/10/17 23:06, Mark Rutland wrote:
> Hi,
>
> Apologies for the delay for this review.
>
> Largely this seems to look OK, but there are a couple of things which
> stick out.
>
> On Tue, Aug 22, 2017 at 04:07:53PM +0800, Shaokun Zhang wrote:
>> +int hisi_uncore_pmu_event_init(struct perf_event *event)
>> +{
>> + struct hw_perf_event *hwc = &event->hw;
>> + struct hisi_pmu *hisi_pmu;
>> +
>> + if (event->attr.type != event->pmu->type)
>> + return -ENOENT;
>> +
>> + /*
>> + * We do not support sampling as the counters are all
>> + * shared by all CPU cores in a CPU die(SCCL). Also we
>> + * do not support attach to a task(per-process mode)
>> + */
>> + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
>> + return -EOPNOTSUPP;
>> +
>> + /* counters do not have these bits */
>> + if (event->attr.exclude_user ||
>> + event->attr.exclude_kernel ||
>> + event->attr.exclude_host ||
>> + event->attr.exclude_guest ||
>> + event->attr.exclude_hv ||
>> + event->attr.exclude_idle)
>> + return -EINVAL;
>> +
>> + /*
>> + * The uncore counters not specific to any CPU, so cannot
>> + * support per-task
>> + */
>> + if (event->cpu < 0)
>> + return -EINVAL;
>> +
>> + /*
>> + * Validate if the events in group does not exceed the
>> + * available counters in hardware.
>> + */
>> + if (!hisi_validate_event_group(event))
>> + return -EINVAL;
>> +
>> + /*
>> + * We don't assign an index until we actually place the event onto
>> + * hardware. Use -1 to signify that we haven't decided where to put it
>> + * yet.
>> + */
>> + hwc->idx = -1;
>> + hwc->config_base = event->attr.config;
>
> Are all event codes valid?
>
No, some event codes are invalid for different PMUs.
> e.g. is it possible that some value passed by the user would cause a
> problem were it written to the hardware?
>
> I see that you only use the low 8 bits of the config field elsewhere, so
> it might make sense to sanity check that here rather than having to mask
> it elsewhere.
Ok, i will add this check for this nice comment.
>
> That would make future extension safer, since no-one could be relying on
> passing a dodgy value in.
>
>> +
>> + hisi_pmu = to_hisi_pmu(event->pmu);
>> + /* Enforce to use the same CPU for all events in this PMU */
>> + event->cpu = hisi_pmu->on_cpu;
>
> I think you need to check hisi_pmu->on_cpu != -1, otherwise we can
> accidentally create a task-bound event if a cluster is offline, and I'm
> not sure how the perf core code would handle here.
>
Ok.
>> +
>> + return 0;
>> +}
>
> [...]
>
>> +int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
>> +{
>> + struct hisi_pmu *hisi_pmu;
>> +
>> + hisi_pmu = hlist_entry_safe(node, struct hisi_pmu, node);
>> +
>> + /*
>> + * If the CPU is associated with the PMU, set it in online_cpus of
>> + * the PMU.
>> + */
>> + if (cpumask_test_cpu(cpu, &hisi_pmu->associated_cpus))
>> + cpumask_set_cpu(cpu, &hisi_pmu->online_cpus);
>> + else
>> + return 0;
>
> This would be a bit nicer as:
>
> if (!cpumask_test_cpu(cpu, &hisi_pmu->associated_cpus))
> return 0;
>
> cpumask_set_cpu(cpu, &hisi_pmu->online_cpus);
>
>
> However, I don't think you need hisi_pmu::online_cpus. That's only used
> for the online/offline callbacks, and you can use the
> hisi_pmu::associated_cpus mask in hisi_uncore_pmu_offline_cpu(), and
> avoid altering any mask here.
>
Ok, shall remove this unnecessary member.
>> +
>> + /* If another CPU is already managing this PMU, simply return. */
>> + if (hisi_pmu->on_cpu != -1)
>> + return 0;
>> +
>> + /* Use this CPU in cpumask for event counting */
>> + hisi_pmu->on_cpu = cpu;
>> +
>> + /* Overflow interrupt also should use the same CPU */
>> + WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(cpu)));
>> +
>> + return 0;
>> +}
>> +
>> +int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
>> +{
>> + struct hisi_pmu *hisi_pmu;
>> + cpumask_t pmu_online_cpus;
>> + unsigned int target;
>> +
>> + hisi_pmu = hlist_entry_safe(node, struct hisi_pmu, node);
>> +
>> + /*
>> + * If the CPU is online with the PMU, clear it in online_cpus of
>> + * the PMU.
>> + */
>> + if (!cpumask_test_and_clear_cpu(cpu, &hisi_pmu->online_cpus) ||
>> + (hisi_pmu->on_cpu != cpu))
>> + return 0;
>> +
>> + hisi_pmu->on_cpu = -1;
>> +
>> + /* Any other CPU associated with the PMU is still online */
>> + cpumask_and(&pmu_online_cpus, &hisi_pmu->online_cpus, cpu_online_mask);
>> + target = cpumask_any_but(&pmu_online_cpus, cpu);
>> + if (target >= nr_cpu_ids)
>> + return 0;
>
> I think you can get rid of hisi_pmu::online_cpus, and replace the mask
> manipulation above with:
>
> /* Nothing to do if this CPU doesn't own the PMU */
> if (hisi_pmu->on_cpu != cpu)
> return 0;
>
> /* Give up ownership of the PMU */
> hisi_pmu->on_cpu = -1;
>
> /* Choose a new CPU to migrate ownership of the PMU to */
> cpumask_and(&pmu_online_cpus, &hisi_pmu->associated_cpus,
> cpu_online_mask)
> target = cpumask_any_but(&pmu_online_cpus, cpu);
> if (target >= nr_cpu_ids)
> return 0;
>
Ok.
>> +
>> + perf_pmu_migrate_context(&hisi_pmu->pmu, cpu, target);
>> + /* Use this CPU for event counting */
>> + hisi_pmu->on_cpu = target;
>> + WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(target)));
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * Check whether the CPU is associated with this uncore PMU by SCCL_ID,
>> + * if true, set the associated cpumask of the uncore PMU.
>> + */
>> +void hisi_uncore_pmu_set_cpumask_by_sccl(void *arg)
>
> Perhaps:
>
> hisi_uncore_pmu_check_associate_cpu(struct hisi_pmu *pmu)
>
> It's not clear to me why the arg is a void pointer.
>
>> +{
>> + struct hisi_pmu *hisi_pmu = (struct hisi_pmu *)arg;
>
> This cast shouldn't be necessary.
>
Ok.
>> + u32 sccl_id;
>> +
>> + hisi_read_sccl_and_ccl_id(&sccl_id, NULL);
>> + if (sccl_id == hisi_pmu->sccl_id)
>> + cpumask_set_cpu(smp_processor_id(), &hisi_pmu->associated_cpus);
>> +}
>
> [...]
>
>> +/* Generic pmu struct for different pmu types */
>> +struct hisi_pmu {
>> + struct pmu pmu;
>> + const struct hisi_uncore_ops *ops;
>> + struct hisi_pmu_hwevents pmu_events;
>> + /*
>> + * online_cpus: All online CPUs associated with the PMU
>> + * associated_cpus: All CPUs associated with the PMU who is
>> + * initialised when probe.
>> + */
>> + cpumask_t online_cpus, associated_cpus;
>> + /* CPU used for counting */
>> + int on_cpu;
>> + int irq;
>> + struct device *dev;
>> + struct hlist_node node;
>> + u32 sccl_id;
>> + u32 ccl_id;
>> + /* Hardware information for different pmu types */
>> + void __iomem *base;
>> + /* the ID of the PMU modules */
>> + u32 id;
>
> Is this what hte documentation referred to as the index-id?
>
Yes, shall change as index_id.
Thanks,
Shaokun
> It might make sense to call it index_id.
>
>> + int num_counters;
>> + int counter_bits;
>> +};
>
> Thanks,
> Mark.
>
> .
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 2/6] perf: hisi: Add support for HiSilicon SoC uncore PMU driver
@ 2017-10-18 13:19 ` Zhangshaokun
0 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-10-18 13:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mark,
Thanks for your comments.
On 2017/10/17 23:06, Mark Rutland wrote:
> Hi,
>
> Apologies for the delay for this review.
>
> Largely this seems to look OK, but there are a couple of things which
> stick out.
>
> On Tue, Aug 22, 2017 at 04:07:53PM +0800, Shaokun Zhang wrote:
>> +int hisi_uncore_pmu_event_init(struct perf_event *event)
>> +{
>> + struct hw_perf_event *hwc = &event->hw;
>> + struct hisi_pmu *hisi_pmu;
>> +
>> + if (event->attr.type != event->pmu->type)
>> + return -ENOENT;
>> +
>> + /*
>> + * We do not support sampling as the counters are all
>> + * shared by all CPU cores in a CPU die(SCCL). Also we
>> + * do not support attach to a task(per-process mode)
>> + */
>> + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
>> + return -EOPNOTSUPP;
>> +
>> + /* counters do not have these bits */
>> + if (event->attr.exclude_user ||
>> + event->attr.exclude_kernel ||
>> + event->attr.exclude_host ||
>> + event->attr.exclude_guest ||
>> + event->attr.exclude_hv ||
>> + event->attr.exclude_idle)
>> + return -EINVAL;
>> +
>> + /*
>> + * The uncore counters not specific to any CPU, so cannot
>> + * support per-task
>> + */
>> + if (event->cpu < 0)
>> + return -EINVAL;
>> +
>> + /*
>> + * Validate if the events in group does not exceed the
>> + * available counters in hardware.
>> + */
>> + if (!hisi_validate_event_group(event))
>> + return -EINVAL;
>> +
>> + /*
>> + * We don't assign an index until we actually place the event onto
>> + * hardware. Use -1 to signify that we haven't decided where to put it
>> + * yet.
>> + */
>> + hwc->idx = -1;
>> + hwc->config_base = event->attr.config;
>
> Are all event codes valid?
>
No, some event codes are invalid for different PMUs.
> e.g. is it possible that some value passed by the user would cause a
> problem were it written to the hardware?
>
> I see that you only use the low 8 bits of the config field elsewhere, so
> it might make sense to sanity check that here rather than having to mask
> it elsewhere.
Ok, i will add this check for this nice comment.
>
> That would make future extension safer, since no-one could be relying on
> passing a dodgy value in.
>
>> +
>> + hisi_pmu = to_hisi_pmu(event->pmu);
>> + /* Enforce to use the same CPU for all events in this PMU */
>> + event->cpu = hisi_pmu->on_cpu;
>
> I think you need to check hisi_pmu->on_cpu != -1, otherwise we can
> accidentally create a task-bound event if a cluster is offline, and I'm
> not sure how the perf core code would handle here.
>
Ok.
>> +
>> + return 0;
>> +}
>
> [...]
>
>> +int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
>> +{
>> + struct hisi_pmu *hisi_pmu;
>> +
>> + hisi_pmu = hlist_entry_safe(node, struct hisi_pmu, node);
>> +
>> + /*
>> + * If the CPU is associated with the PMU, set it in online_cpus of
>> + * the PMU.
>> + */
>> + if (cpumask_test_cpu(cpu, &hisi_pmu->associated_cpus))
>> + cpumask_set_cpu(cpu, &hisi_pmu->online_cpus);
>> + else
>> + return 0;
>
> This would be a bit nicer as:
>
> if (!cpumask_test_cpu(cpu, &hisi_pmu->associated_cpus))
> return 0;
>
> cpumask_set_cpu(cpu, &hisi_pmu->online_cpus);
>
>
> However, I don't think you need hisi_pmu::online_cpus. That's only used
> for the online/offline callbacks, and you can use the
> hisi_pmu::associated_cpus mask in hisi_uncore_pmu_offline_cpu(), and
> avoid altering any mask here.
>
Ok, shall remove this unnecessary member.
>> +
>> + /* If another CPU is already managing this PMU, simply return. */
>> + if (hisi_pmu->on_cpu != -1)
>> + return 0;
>> +
>> + /* Use this CPU in cpumask for event counting */
>> + hisi_pmu->on_cpu = cpu;
>> +
>> + /* Overflow interrupt also should use the same CPU */
>> + WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(cpu)));
>> +
>> + return 0;
>> +}
>> +
>> +int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
>> +{
>> + struct hisi_pmu *hisi_pmu;
>> + cpumask_t pmu_online_cpus;
>> + unsigned int target;
>> +
>> + hisi_pmu = hlist_entry_safe(node, struct hisi_pmu, node);
>> +
>> + /*
>> + * If the CPU is online with the PMU, clear it in online_cpus of
>> + * the PMU.
>> + */
>> + if (!cpumask_test_and_clear_cpu(cpu, &hisi_pmu->online_cpus) ||
>> + (hisi_pmu->on_cpu != cpu))
>> + return 0;
>> +
>> + hisi_pmu->on_cpu = -1;
>> +
>> + /* Any other CPU associated with the PMU is still online */
>> + cpumask_and(&pmu_online_cpus, &hisi_pmu->online_cpus, cpu_online_mask);
>> + target = cpumask_any_but(&pmu_online_cpus, cpu);
>> + if (target >= nr_cpu_ids)
>> + return 0;
>
> I think you can get rid of hisi_pmu::online_cpus, and replace the mask
> manipulation above with:
>
> /* Nothing to do if this CPU doesn't own the PMU */
> if (hisi_pmu->on_cpu != cpu)
> return 0;
>
> /* Give up ownership of the PMU */
> hisi_pmu->on_cpu = -1;
>
> /* Choose a new CPU to migrate ownership of the PMU to */
> cpumask_and(&pmu_online_cpus, &hisi_pmu->associated_cpus,
> cpu_online_mask)
> target = cpumask_any_but(&pmu_online_cpus, cpu);
> if (target >= nr_cpu_ids)
> return 0;
>
Ok.
>> +
>> + perf_pmu_migrate_context(&hisi_pmu->pmu, cpu, target);
>> + /* Use this CPU for event counting */
>> + hisi_pmu->on_cpu = target;
>> + WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(target)));
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * Check whether the CPU is associated with this uncore PMU by SCCL_ID,
>> + * if true, set the associated cpumask of the uncore PMU.
>> + */
>> +void hisi_uncore_pmu_set_cpumask_by_sccl(void *arg)
>
> Perhaps:
>
> hisi_uncore_pmu_check_associate_cpu(struct hisi_pmu *pmu)
>
> It's not clear to me why the arg is a void pointer.
>
>> +{
>> + struct hisi_pmu *hisi_pmu = (struct hisi_pmu *)arg;
>
> This cast shouldn't be necessary.
>
Ok.
>> + u32 sccl_id;
>> +
>> + hisi_read_sccl_and_ccl_id(&sccl_id, NULL);
>> + if (sccl_id == hisi_pmu->sccl_id)
>> + cpumask_set_cpu(smp_processor_id(), &hisi_pmu->associated_cpus);
>> +}
>
> [...]
>
>> +/* Generic pmu struct for different pmu types */
>> +struct hisi_pmu {
>> + struct pmu pmu;
>> + const struct hisi_uncore_ops *ops;
>> + struct hisi_pmu_hwevents pmu_events;
>> + /*
>> + * online_cpus: All online CPUs associated with the PMU
>> + * associated_cpus: All CPUs associated with the PMU who is
>> + * initialised when probe.
>> + */
>> + cpumask_t online_cpus, associated_cpus;
>> + /* CPU used for counting */
>> + int on_cpu;
>> + int irq;
>> + struct device *dev;
>> + struct hlist_node node;
>> + u32 sccl_id;
>> + u32 ccl_id;
>> + /* Hardware information for different pmu types */
>> + void __iomem *base;
>> + /* the ID of the PMU modules */
>> + u32 id;
>
> Is this what hte documentation referred to as the index-id?
>
Yes, shall change as index_id.
Thanks,
Shaokun
> It might make sense to call it index_id.
>
>> + int num_counters;
>> + int counter_bits;
>> +};
>
> Thanks,
> Mark.
>
> .
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver
2017-10-17 15:16 ` Mark Rutland
@ 2017-10-18 13:33 ` Zhangshaokun
-1 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-10-18 13:33 UTC (permalink / raw)
To: Mark Rutland
Cc: will.deacon, jonathan.cameron, linux-arm-kernel, linux-kernel,
linux-doc, linuxarm, Anurup M
Hi Mark,
On 2017/10/17 23:16, Mark Rutland wrote:
> On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote:
>> +static int hisi_l3c_pmu_init_irq(struct hisi_pmu *l3c_pmu,
>> + struct platform_device *pdev)
>> +{
>> + int irq, ret;
>> +
>> + /* Read and init IRQ */
>> + irq = platform_get_irq(pdev, 0);
>> + if (irq < 0) {
>> + dev_err(&pdev->dev, "L3C PMU get irq fail; irq:%d\n", irq);
>> + return irq;
>> + }
>> +
>> + ret = devm_request_irq(&pdev->dev, irq, hisi_l3c_pmu_isr,
>> + IRQF_NOBALANCING | IRQF_NO_THREAD,
>> + dev_name(&pdev->dev), l3c_pmu);
>> + if (ret < 0) {
>> + dev_err(&pdev->dev,
>> + "Fail to request IRQ:%d ret:%d\n", irq, ret);
>> + return ret;
>> + }
>> +
>> + l3c_pmu->irq = irq;
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * Check whether the CPU is associated with this L3C PMU by SCCL_ID
>> + * and CCL_ID, if true, set the associated cpumask of the L3C PMU.
>> + */
>> +static void hisi_l3c_pmu_set_cpumask_by_ccl(void *arg)
>> +{
>> + struct hisi_pmu *l3c_pmu = (struct hisi_pmu *)arg;
>> + u32 ccl_id, sccl_id;
>> +
>> + hisi_read_sccl_and_ccl_id(&sccl_id, &ccl_id);
>> + if (sccl_id == l3c_pmu->sccl_id && ccl_id == l3c_pmu->ccl_id)
>> + cpumask_set_cpu(smp_processor_id(), &l3c_pmu->associated_cpus);
>> +}
>
> The shared code has hisi_uncore_pmu_set_cpumask_by_sccl(), and it would
> be nice to place this in the same place.
>
> Otherwise, the same comments apply here.
>
Ok, shall fix the same issues.
>> +
>> +static const struct acpi_device_id hisi_l3c_pmu_acpi_match[] = {
>> + { "HISI0213", },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(acpi, hisi_l3c_pmu_acpi_match);
>> +
>> +static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
>> + struct hisi_pmu *l3c_pmu)
>> +{
>> + unsigned long long id;
>> + struct resource *res;
>> + acpi_status status;
>> + int cpu;
>> +
>> + status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
>> + "_UID", NULL, &id);
>> + if (ACPI_FAILURE(status))
>> + return -EINVAL;
>> +
>> + l3c_pmu->id = id;
>> +
>> + /*
>> + * Use the SCCL_ID and CCL_ID to identify the L3C PMU, while
>> + * SCCL_ID is in MPIDR[aff2] and CCL_ID is in MPIDR[aff1].
>> + */
>> + if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
>> + &l3c_pmu->sccl_id)) {
>> + dev_err(&pdev->dev, "Can not read l3c sccl-id!\n");
>> + return -EINVAL;
>> + }
>> +
>> + if (device_property_read_u32(&pdev->dev, "hisilicon,ccl-id",
>> + &l3c_pmu->ccl_id)) {
>> + dev_err(&pdev->dev, "Can not read l3c ccl-id!\n");
>> + return -EINVAL;
>> + }
>> +
>> + /* Initialise the associated cpumask of the PMU */
>> + for_each_present_cpu(cpu)
>> + smp_call_function_single(cpu, hisi_l3c_pmu_set_cpumask_by_ccl,
>> + (void *)l3c_pmu, 1);
>
> Ah, so that's why hisi_uncore_pmu_set_cpumask_by_sccl took a void
> pointer.
>
> Please drop a comment above hisi_uncore_pmu_set_cpumask_by_sccl to cover
> that.
>
> I think you can drop the void cast here; I don't beleive it is
> necessary.
>
Ok.
> Rather than a proble-time smp_call_function_single(), can you follow the
> qcom l2's approach of associating CPUs with a PMU instance in the
> notifier? That will work even if CPUs are brought online very late.
>
A good guidance, but HHA and DDRC PMUs are different from L3C PMU, the former
share the same SCCL and the latter share the same SCCL and CCL. I will
try to deal with this difference in online notifier.
Thanks,
Shaokun
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + l3c_pmu->base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(l3c_pmu->base)) {
>> + dev_err(&pdev->dev, "ioremap failed for l3c_pmu resource\n");
>> + return PTR_ERR(l3c_pmu->base);
>> + }
>> +
>> + return 0;
>> +}
>
> Thanks,
> Mark.
>
> .
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver
@ 2017-10-18 13:33 ` Zhangshaokun
0 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-10-18 13:33 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mark,
On 2017/10/17 23:16, Mark Rutland wrote:
> On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote:
>> +static int hisi_l3c_pmu_init_irq(struct hisi_pmu *l3c_pmu,
>> + struct platform_device *pdev)
>> +{
>> + int irq, ret;
>> +
>> + /* Read and init IRQ */
>> + irq = platform_get_irq(pdev, 0);
>> + if (irq < 0) {
>> + dev_err(&pdev->dev, "L3C PMU get irq fail; irq:%d\n", irq);
>> + return irq;
>> + }
>> +
>> + ret = devm_request_irq(&pdev->dev, irq, hisi_l3c_pmu_isr,
>> + IRQF_NOBALANCING | IRQF_NO_THREAD,
>> + dev_name(&pdev->dev), l3c_pmu);
>> + if (ret < 0) {
>> + dev_err(&pdev->dev,
>> + "Fail to request IRQ:%d ret:%d\n", irq, ret);
>> + return ret;
>> + }
>> +
>> + l3c_pmu->irq = irq;
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * Check whether the CPU is associated with this L3C PMU by SCCL_ID
>> + * and CCL_ID, if true, set the associated cpumask of the L3C PMU.
>> + */
>> +static void hisi_l3c_pmu_set_cpumask_by_ccl(void *arg)
>> +{
>> + struct hisi_pmu *l3c_pmu = (struct hisi_pmu *)arg;
>> + u32 ccl_id, sccl_id;
>> +
>> + hisi_read_sccl_and_ccl_id(&sccl_id, &ccl_id);
>> + if (sccl_id == l3c_pmu->sccl_id && ccl_id == l3c_pmu->ccl_id)
>> + cpumask_set_cpu(smp_processor_id(), &l3c_pmu->associated_cpus);
>> +}
>
> The shared code has hisi_uncore_pmu_set_cpumask_by_sccl(), and it would
> be nice to place this in the same place.
>
> Otherwise, the same comments apply here.
>
Ok, shall fix the same issues.
>> +
>> +static const struct acpi_device_id hisi_l3c_pmu_acpi_match[] = {
>> + { "HISI0213", },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(acpi, hisi_l3c_pmu_acpi_match);
>> +
>> +static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
>> + struct hisi_pmu *l3c_pmu)
>> +{
>> + unsigned long long id;
>> + struct resource *res;
>> + acpi_status status;
>> + int cpu;
>> +
>> + status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
>> + "_UID", NULL, &id);
>> + if (ACPI_FAILURE(status))
>> + return -EINVAL;
>> +
>> + l3c_pmu->id = id;
>> +
>> + /*
>> + * Use the SCCL_ID and CCL_ID to identify the L3C PMU, while
>> + * SCCL_ID is in MPIDR[aff2] and CCL_ID is in MPIDR[aff1].
>> + */
>> + if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
>> + &l3c_pmu->sccl_id)) {
>> + dev_err(&pdev->dev, "Can not read l3c sccl-id!\n");
>> + return -EINVAL;
>> + }
>> +
>> + if (device_property_read_u32(&pdev->dev, "hisilicon,ccl-id",
>> + &l3c_pmu->ccl_id)) {
>> + dev_err(&pdev->dev, "Can not read l3c ccl-id!\n");
>> + return -EINVAL;
>> + }
>> +
>> + /* Initialise the associated cpumask of the PMU */
>> + for_each_present_cpu(cpu)
>> + smp_call_function_single(cpu, hisi_l3c_pmu_set_cpumask_by_ccl,
>> + (void *)l3c_pmu, 1);
>
> Ah, so that's why hisi_uncore_pmu_set_cpumask_by_sccl took a void
> pointer.
>
> Please drop a comment above hisi_uncore_pmu_set_cpumask_by_sccl to cover
> that.
>
> I think you can drop the void cast here; I don't beleive it is
> necessary.
>
Ok.
> Rather than a proble-time smp_call_function_single(), can you follow the
> qcom l2's approach of associating CPUs with a PMU instance in the
> notifier? That will work even if CPUs are brought online very late.
>
A good guidance, but HHA and DDRC PMUs are different from L3C PMU, the former
share the same SCCL and the latter share the same SCCL and CCL. I will
try to deal with this difference in online notifier.
Thanks,
Shaokun
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + l3c_pmu->base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(l3c_pmu->base)) {
>> + dev_err(&pdev->dev, "ioremap failed for l3c_pmu resource\n");
>> + return PTR_ERR(l3c_pmu->base);
>> + }
>> +
>> + return 0;
>> +}
>
> Thanks,
> Mark.
>
> .
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver
2017-10-17 15:18 ` Mark Rutland
@ 2017-10-18 13:35 ` Zhangshaokun
-1 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-10-18 13:35 UTC (permalink / raw)
To: Mark Rutland
Cc: will.deacon, jonathan.cameron, linux-arm-kernel, linux-kernel,
linux-doc, linuxarm, Anurup M
Hi Mark,
On 2017/10/17 23:18, Mark Rutland wrote:
> On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote:
>> L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
>> SoC. This patch adds support for HHA PMU driver, Each HHA has own
>> control, counter and interrupt registers and is an separate PMU. For
>> each HHA PMU, it has 16-programable counters and each counter is
>> free-running. Interrupt is supported to handle counter (48-bits)
>> overflow.
>
> My comments here are the same as for the L3C PMU driver.
>
Sure.
Thanks,
Shaokun
> Thanks,
> Mark.
>
> .
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver
@ 2017-10-18 13:35 ` Zhangshaokun
0 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-10-18 13:35 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mark,
On 2017/10/17 23:18, Mark Rutland wrote:
> On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote:
>> L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
>> SoC. This patch adds support for HHA PMU driver, Each HHA has own
>> control, counter and interrupt registers and is an separate PMU. For
>> each HHA PMU, it has 16-programable counters and each counter is
>> free-running. Interrupt is supported to handle counter (48-bits)
>> overflow.
>
> My comments here are the same as for the L3C PMU driver.
>
Sure.
Thanks,
Shaokun
> Thanks,
> Mark.
>
> .
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 5/6] perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
2017-10-17 15:21 ` Mark Rutland
@ 2017-10-18 13:37 ` Zhangshaokun
-1 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-10-18 13:37 UTC (permalink / raw)
To: Mark Rutland
Cc: will.deacon, jonathan.cameron, linux-arm-kernel, linux-kernel,
linux-doc, linuxarm, Anurup M
Hi Mark,
On 2017/10/17 23:21, Mark Rutland wrote:
> On Tue, Aug 22, 2017 at 04:07:56PM +0800, Shaokun Zhang wrote:
>> This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
>> DDRC has own control, counter and interrupt registers and is an separate
>> PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been
>> mapped to 8-events by hardware, it assumes that counter index is equal
>> to event code (0 - 7) in DDRC PMU driver. Interrupt is supported to
>> handle counter (32-bits) overflow.
>>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
>> Signed-off-by: Anurup M <anurup.m@huawei.com>
>
> I have the same comments for this case as for the other two PMU drivers.
>
Sure.
Thanks,
Shaokun
> Thanks,
> Mark.
>
> .
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 5/6] perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
@ 2017-10-18 13:37 ` Zhangshaokun
0 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-10-18 13:37 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mark,
On 2017/10/17 23:21, Mark Rutland wrote:
> On Tue, Aug 22, 2017 at 04:07:56PM +0800, Shaokun Zhang wrote:
>> This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
>> DDRC has own control, counter and interrupt registers and is an separate
>> PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been
>> mapped to 8-events by hardware, it assumes that counter index is equal
>> to event code (0 - 7) in DDRC PMU driver. Interrupt is supported to
>> handle counter (32-bits) overflow.
>>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
>> Signed-off-by: Anurup M <anurup.m@huawei.com>
>
> I have the same comments for this case as for the other two PMU drivers.
>
Sure.
Thanks,
Shaokun
> Thanks,
> Mark.
>
> .
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver
2017-10-18 13:33 ` Zhangshaokun
@ 2017-10-18 13:55 ` Mark Rutland
-1 siblings, 0 replies; 40+ messages in thread
From: Mark Rutland @ 2017-10-18 13:55 UTC (permalink / raw)
To: Zhangshaokun
Cc: will.deacon, jonathan.cameron, linux-arm-kernel, linux-kernel,
linux-doc, linuxarm, Anurup M
On Wed, Oct 18, 2017 at 09:33:30PM +0800, Zhangshaokun wrote:
> On 2017/10/17 23:16, Mark Rutland wrote:
> > On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote:
> >> +static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
> >> + struct hisi_pmu *l3c_pmu)
> >> +{
> >> + unsigned long long id;
> >> + struct resource *res;
> >> + acpi_status status;
> >> + int cpu;
> >> +
> >> + status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
> >> + "_UID", NULL, &id);
> >> + if (ACPI_FAILURE(status))
> >> + return -EINVAL;
> >> +
> >> + l3c_pmu->id = id;
> >> +
> >> + /*
> >> + * Use the SCCL_ID and CCL_ID to identify the L3C PMU, while
> >> + * SCCL_ID is in MPIDR[aff2] and CCL_ID is in MPIDR[aff1].
> >> + */
> >> + if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
> >> + &l3c_pmu->sccl_id)) {
> >> + dev_err(&pdev->dev, "Can not read l3c sccl-id!\n");
> >> + return -EINVAL;
> >> + }
> >> +
> >> + if (device_property_read_u32(&pdev->dev, "hisilicon,ccl-id",
> >> + &l3c_pmu->ccl_id)) {
> >> + dev_err(&pdev->dev, "Can not read l3c ccl-id!\n");
> >> + return -EINVAL;
> >> + }
> >> +
> >> + /* Initialise the associated cpumask of the PMU */
> >> + for_each_present_cpu(cpu)
> >> + smp_call_function_single(cpu, hisi_l3c_pmu_set_cpumask_by_ccl,
> >> + (void *)l3c_pmu, 1);
> > Rather than a proble-time smp_call_function_single(), can you follow the
> > qcom l2's approach of associating CPUs with a PMU instance in the
> > notifier? That will work even if CPUs are brought online very late.
>
> A good guidance, but HHA and DDRC PMUs are different from L3C PMU, the former
> share the same SCCL and the latter share the same SCCL and CCL. I will
> try to deal with this difference in online notifier.
FWIW, I think it makes sense for each PMU to have its own notifier
(perhaps with some shared code that each calls to do the migration).
I just want to avoid the smp_call_function_single() at probe time, as
that doesn't work in some cases.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver
@ 2017-10-18 13:55 ` Mark Rutland
0 siblings, 0 replies; 40+ messages in thread
From: Mark Rutland @ 2017-10-18 13:55 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Oct 18, 2017 at 09:33:30PM +0800, Zhangshaokun wrote:
> On 2017/10/17 23:16, Mark Rutland wrote:
> > On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote:
> >> +static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
> >> + struct hisi_pmu *l3c_pmu)
> >> +{
> >> + unsigned long long id;
> >> + struct resource *res;
> >> + acpi_status status;
> >> + int cpu;
> >> +
> >> + status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
> >> + "_UID", NULL, &id);
> >> + if (ACPI_FAILURE(status))
> >> + return -EINVAL;
> >> +
> >> + l3c_pmu->id = id;
> >> +
> >> + /*
> >> + * Use the SCCL_ID and CCL_ID to identify the L3C PMU, while
> >> + * SCCL_ID is in MPIDR[aff2] and CCL_ID is in MPIDR[aff1].
> >> + */
> >> + if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
> >> + &l3c_pmu->sccl_id)) {
> >> + dev_err(&pdev->dev, "Can not read l3c sccl-id!\n");
> >> + return -EINVAL;
> >> + }
> >> +
> >> + if (device_property_read_u32(&pdev->dev, "hisilicon,ccl-id",
> >> + &l3c_pmu->ccl_id)) {
> >> + dev_err(&pdev->dev, "Can not read l3c ccl-id!\n");
> >> + return -EINVAL;
> >> + }
> >> +
> >> + /* Initialise the associated cpumask of the PMU */
> >> + for_each_present_cpu(cpu)
> >> + smp_call_function_single(cpu, hisi_l3c_pmu_set_cpumask_by_ccl,
> >> + (void *)l3c_pmu, 1);
> > Rather than a proble-time smp_call_function_single(), can you follow the
> > qcom l2's approach of associating CPUs with a PMU instance in the
> > notifier? That will work even if CPUs are brought online very late.
>
> A good guidance, but HHA and DDRC PMUs are different from L3C PMU, the former
> share the same SCCL and the latter share the same SCCL and CCL. I will
> try to deal with this difference in online notifier.
FWIW, I think it makes sense for each PMU to have its own notifier
(perhaps with some shared code that each calls to do the migration).
I just want to avoid the smp_call_function_single() at probe time, as
that doesn't work in some cases.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver
2017-10-18 13:55 ` Mark Rutland
@ 2017-10-18 14:08 ` Zhangshaokun
-1 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-10-18 14:08 UTC (permalink / raw)
To: Mark Rutland
Cc: will.deacon, jonathan.cameron, linux-arm-kernel, linux-kernel,
linux-doc, linuxarm, Anurup M
Hi Mark,
Thanks for your further explanation.
On 2017/10/18 21:55, Mark Rutland wrote:
> On Wed, Oct 18, 2017 at 09:33:30PM +0800, Zhangshaokun wrote:
>> On 2017/10/17 23:16, Mark Rutland wrote:
>>> On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote:
>>>> +static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
>>>> + struct hisi_pmu *l3c_pmu)
>>>> +{
>>>> + unsigned long long id;
>>>> + struct resource *res;
>>>> + acpi_status status;
>>>> + int cpu;
>>>> +
>>>> + status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
>>>> + "_UID", NULL, &id);
>>>> + if (ACPI_FAILURE(status))
>>>> + return -EINVAL;
>>>> +
>>>> + l3c_pmu->id = id;
>>>> +
>>>> + /*
>>>> + * Use the SCCL_ID and CCL_ID to identify the L3C PMU, while
>>>> + * SCCL_ID is in MPIDR[aff2] and CCL_ID is in MPIDR[aff1].
>>>> + */
>>>> + if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
>>>> + &l3c_pmu->sccl_id)) {
>>>> + dev_err(&pdev->dev, "Can not read l3c sccl-id!\n");
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + if (device_property_read_u32(&pdev->dev, "hisilicon,ccl-id",
>>>> + &l3c_pmu->ccl_id)) {
>>>> + dev_err(&pdev->dev, "Can not read l3c ccl-id!\n");
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + /* Initialise the associated cpumask of the PMU */
>>>> + for_each_present_cpu(cpu)
>>>> + smp_call_function_single(cpu, hisi_l3c_pmu_set_cpumask_by_ccl,
>>>> + (void *)l3c_pmu, 1);
>
>>> Rather than a proble-time smp_call_function_single(), can you follow the
>>> qcom l2's approach of associating CPUs with a PMU instance in the
>>> notifier? That will work even if CPUs are brought online very late.
>>
>> A good guidance, but HHA and DDRC PMUs are different from L3C PMU, the former
>> share the same SCCL and the latter share the same SCCL and CCL. I will
>> try to deal with this difference in online notifier.
>
> FWIW, I think it makes sense for each PMU to have its own notifier
> (perhaps with some shared code that each calls to do the migration).
>
> I just want to avoid the smp_call_function_single() at probe time, as
> that doesn't work in some cases.
>
Got it, i shall update the hisi_pmu::associated_cpus only in online
and offline notifiers.
Thanks,
Shaokun
> Thanks,
> Mark.
>
> .
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver
@ 2017-10-18 14:08 ` Zhangshaokun
0 siblings, 0 replies; 40+ messages in thread
From: Zhangshaokun @ 2017-10-18 14:08 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mark,
Thanks for your further explanation.
On 2017/10/18 21:55, Mark Rutland wrote:
> On Wed, Oct 18, 2017 at 09:33:30PM +0800, Zhangshaokun wrote:
>> On 2017/10/17 23:16, Mark Rutland wrote:
>>> On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote:
>>>> +static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
>>>> + struct hisi_pmu *l3c_pmu)
>>>> +{
>>>> + unsigned long long id;
>>>> + struct resource *res;
>>>> + acpi_status status;
>>>> + int cpu;
>>>> +
>>>> + status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
>>>> + "_UID", NULL, &id);
>>>> + if (ACPI_FAILURE(status))
>>>> + return -EINVAL;
>>>> +
>>>> + l3c_pmu->id = id;
>>>> +
>>>> + /*
>>>> + * Use the SCCL_ID and CCL_ID to identify the L3C PMU, while
>>>> + * SCCL_ID is in MPIDR[aff2] and CCL_ID is in MPIDR[aff1].
>>>> + */
>>>> + if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
>>>> + &l3c_pmu->sccl_id)) {
>>>> + dev_err(&pdev->dev, "Can not read l3c sccl-id!\n");
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + if (device_property_read_u32(&pdev->dev, "hisilicon,ccl-id",
>>>> + &l3c_pmu->ccl_id)) {
>>>> + dev_err(&pdev->dev, "Can not read l3c ccl-id!\n");
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + /* Initialise the associated cpumask of the PMU */
>>>> + for_each_present_cpu(cpu)
>>>> + smp_call_function_single(cpu, hisi_l3c_pmu_set_cpumask_by_ccl,
>>>> + (void *)l3c_pmu, 1);
>
>>> Rather than a proble-time smp_call_function_single(), can you follow the
>>> qcom l2's approach of associating CPUs with a PMU instance in the
>>> notifier? That will work even if CPUs are brought online very late.
>>
>> A good guidance, but HHA and DDRC PMUs are different from L3C PMU, the former
>> share the same SCCL and the latter share the same SCCL and CCL. I will
>> try to deal with this difference in online notifier.
>
> FWIW, I think it makes sense for each PMU to have its own notifier
> (perhaps with some shared code that each calls to do the migration).
>
> I just want to avoid the smp_call_function_single() at probe time, as
> that doesn't work in some cases.
>
Got it, i shall update the hisi_pmu::associated_cpus only in online
and offline notifiers.
Thanks,
Shaokun
> Thanks,
> Mark.
>
> .
>
^ permalink raw reply [flat|nested] 40+ messages in thread
end of thread, other threads:[~2017-10-18 14:10 UTC | newest]
Thread overview: 40+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-22 8:07 [PATCH v5 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver Shaokun Zhang
2017-08-22 8:07 ` Shaokun Zhang
2017-08-22 8:07 ` [PATCH v5 1/6] Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver Shaokun Zhang
2017-08-22 8:07 ` Shaokun Zhang
2017-08-22 8:07 ` [PATCH v5 2/6] perf: hisi: Add support for HiSilicon SoC uncore " Shaokun Zhang
2017-08-22 8:07 ` Shaokun Zhang
2017-10-17 15:06 ` Mark Rutland
2017-10-17 15:06 ` Mark Rutland
2017-10-18 13:19 ` Zhangshaokun
2017-10-18 13:19 ` Zhangshaokun
2017-08-22 8:07 ` [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C " Shaokun Zhang
2017-08-22 8:07 ` Shaokun Zhang
2017-10-17 15:16 ` Mark Rutland
2017-10-17 15:16 ` Mark Rutland
2017-10-18 13:33 ` Zhangshaokun
2017-10-18 13:33 ` Zhangshaokun
2017-10-18 13:55 ` Mark Rutland
2017-10-18 13:55 ` Mark Rutland
2017-10-18 14:08 ` Zhangshaokun
2017-10-18 14:08 ` Zhangshaokun
2017-08-22 8:07 ` [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA " Shaokun Zhang
2017-08-22 8:07 ` Shaokun Zhang
2017-10-17 15:18 ` Mark Rutland
2017-10-17 15:18 ` Mark Rutland
2017-10-18 13:35 ` Zhangshaokun
2017-10-18 13:35 ` Zhangshaokun
2017-08-22 8:07 ` [PATCH v5 5/6] perf: hisi: Add support for HiSilicon SoC DDRC " Shaokun Zhang
2017-08-22 8:07 ` Shaokun Zhang
2017-10-17 15:21 ` Mark Rutland
2017-10-17 15:21 ` Mark Rutland
2017-10-18 13:37 ` Zhangshaokun
2017-10-18 13:37 ` Zhangshaokun
2017-08-22 8:07 ` [PATCH v5 6/6] arm64: MAINTAINERS: hisi: Add HiSilicon SoC PMU support Shaokun Zhang
2017-08-22 8:07 ` Shaokun Zhang
2017-08-29 12:28 ` [PATCH v5 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver Zhangshaokun
2017-08-29 12:28 ` Zhangshaokun
2017-09-21 10:40 ` Zhangshaokun
2017-09-21 10:40 ` Zhangshaokun
2017-10-09 8:17 ` Zhangshaokun
2017-10-09 8:17 ` Zhangshaokun
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.