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From: "Stefan O'Rear" <sorear@fastmail.com>
To: "Heiko Stuebner" <heiko@sntech.de>,
	"Palmer Dabbelt" <palmer@dabbelt.com>
Cc: linux-riscv@lists.infradead.org, samuel@sholland.org,
	guoren@kernel.org, christoph.muellner@vrull.eu,
	conor.dooley@microchip.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC 2/2] RISC-V: add T-Head vector errata handling
Date: Thu, 22 Jun 2023 23:06:44 -0400	[thread overview]
Message-ID: <c01ee919-9abb-4796-9ed4-9bb4565dc863@app.fastmail.com> (raw)
In-Reply-To: <9132027.CDJkKcVGEf@diego>

On Thu, Jun 22, 2023, at 4:35 PM, Heiko Stübner wrote:
> Am Donnerstag, 22. Juni 2023, 20:58:37 CEST schrieb Stefan O'Rear:
>> Are you aware of "3.7. Vector Fixed-Point Fields in fcsr" in
>> riscv-v-spec-0.7.1.pdf?
>
> oh wow, thanks a lot for that pointer, now I understand your concern.
>
> So in vector-0.7.1 fcsr[10:9] mirrors vxrm and fcsr[8] mirrors vxsat.
>
>
> On a positive note, the T-Head cores seem to not implement the full
> vector 0.7.1 specification after all, in the documentation I have [0]
> fcsr[31:8] are declared as "0" and uppermost bits are [7:5] for the "frm"
> field.

Given that the pdf you linked does not mention any vector CSRs, I am not
confident that it provides a complete and accurate description of vector
functionality in other registers for the C906 with vector extension.

Assuming that you have access to such a chip, I would be much happier with
the proposed "just a comment" approach if our understanding of the behavior
were confirmed on hardware (specifically: csr_write(CSR_FCSR, 0x700) should
not affect csr_read(CSR_VXRM) or csr_read(CSR_VXSAT)).

-s

> So I guess a code comment should suffice to explain :-)
>
>
> Regards
> Heiko
>
>
> [0] 
> https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
> 16.3.1.3 浮点控制状态寄存器（FCSR） on page 334

WARNING: multiple messages have this Message-ID (diff)
From: "Stefan O'Rear" <sorear@fastmail.com>
To: "Heiko Stuebner" <heiko@sntech.de>,
	"Palmer Dabbelt" <palmer@dabbelt.com>
Cc: linux-riscv@lists.infradead.org, samuel@sholland.org,
	guoren@kernel.org, christoph.muellner@vrull.eu,
	conor.dooley@microchip.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC 2/2] RISC-V: add T-Head vector errata handling
Date: Thu, 22 Jun 2023 23:06:44 -0400	[thread overview]
Message-ID: <c01ee919-9abb-4796-9ed4-9bb4565dc863@app.fastmail.com> (raw)
In-Reply-To: <9132027.CDJkKcVGEf@diego>

On Thu, Jun 22, 2023, at 4:35 PM, Heiko Stübner wrote:
> Am Donnerstag, 22. Juni 2023, 20:58:37 CEST schrieb Stefan O'Rear:
>> Are you aware of "3.7. Vector Fixed-Point Fields in fcsr" in
>> riscv-v-spec-0.7.1.pdf?
>
> oh wow, thanks a lot for that pointer, now I understand your concern.
>
> So in vector-0.7.1 fcsr[10:9] mirrors vxrm and fcsr[8] mirrors vxsat.
>
>
> On a positive note, the T-Head cores seem to not implement the full
> vector 0.7.1 specification after all, in the documentation I have [0]
> fcsr[31:8] are declared as "0" and uppermost bits are [7:5] for the "frm"
> field.

Given that the pdf you linked does not mention any vector CSRs, I am not
confident that it provides a complete and accurate description of vector
functionality in other registers for the C906 with vector extension.

Assuming that you have access to such a chip, I would be much happier with
the proposed "just a comment" approach if our understanding of the behavior
were confirmed on hardware (specifically: csr_write(CSR_FCSR, 0x700) should
not affect csr_read(CSR_VXRM) or csr_read(CSR_VXSAT)).

-s

> So I guess a code comment should suffice to explain :-)
>
>
> Regards
> Heiko
>
>
> [0] 
> https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
> 16.3.1.3 浮点控制状态寄存器（FCSR） on page 334

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  reply	other threads:[~2023-06-23  3:07 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-28 21:54 [PATCH RFC 0/2] RISC-V: T-Head vector handling Heiko Stuebner
2023-02-28 21:54 ` Heiko Stuebner
2023-02-28 21:54 ` [PATCH RFC 1/2] RISC-V: define the elements of the VCSR vector CSR Heiko Stuebner
2023-02-28 21:54   ` Heiko Stuebner
2023-03-01  2:22   ` Guo Ren
2023-03-01  2:22     ` Guo Ren
2023-03-15 18:31   ` Conor Dooley
2023-03-15 18:31     ` Conor Dooley
2023-02-28 21:54 ` [PATCH RFC 2/2] RISC-V: add T-Head vector errata handling Heiko Stuebner
2023-02-28 21:54   ` Heiko Stuebner
2023-03-01  2:12   ` Guo Ren
2023-03-01  2:12     ` Guo Ren
2023-03-15 18:56   ` Conor Dooley
2023-03-15 18:56     ` Conor Dooley
2023-06-13  6:35   ` Stefan O'Rear
2023-06-13  6:35     ` Stefan O'Rear
2023-06-22 17:39     ` Heiko Stübner
2023-06-22 17:39       ` Heiko Stübner
2023-06-22 18:58       ` Stefan O'Rear
2023-06-22 18:58         ` Stefan O'Rear
2023-06-22 20:35         ` Heiko Stübner
2023-06-22 20:35           ` Heiko Stübner
2023-06-23  3:06           ` Stefan O'Rear [this message]
2023-06-23  3:06             ` Stefan O'Rear
2023-06-23 10:22             ` Heiko Stübner
2023-06-23 10:22               ` Heiko Stübner
2023-06-23 23:26               ` Heiko Stübner
2023-06-23 23:26                 ` Heiko Stübner
2023-06-24  3:23                 ` Stefan O'Rear
2023-06-24  3:23                   ` Stefan O'Rear
2023-06-23  9:12   ` Emil Renner Berthing
2023-06-23  9:12     ` Emil Renner Berthing
2023-03-01  2:21 ` [PATCH RFC 0/2] RISC-V: T-Head vector handling Guo Ren
2023-03-01  2:21   ` Guo Ren
2023-03-15  5:29 ` Palmer Dabbelt
2023-03-15  5:29   ` Palmer Dabbelt
2023-03-15  6:31   ` Heiko Stuebner
2023-03-15  6:31     ` Heiko Stuebner
2023-06-12 15:29   ` Palmer Dabbelt
2023-06-12 15:29     ` Palmer Dabbelt
2023-06-12 15:44     ` Heiko Stübner
2023-06-12 15:44       ` Heiko Stübner

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