* [PATCH 1/6] m68k: improve cpu instantiation comments
2021-02-01 0:01 [PATCH 0/6] m68k: Overhaul of MOVEC instruction to support exception/MSP BALATON Zoltan
@ 2021-02-01 0:01 ` BALATON Zoltan
2021-02-01 0:01 ` [PATCH 6/6] m68k: add MSP detection support for stack pointer swap helpers BALATON Zoltan
` (6 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: BALATON Zoltan @ 2021-02-01 0:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Laurent Vivier, Lucien Murray-Pitts
From: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
Improvement in comments for the instantiation functions.
This is to highlight what each cpu class, in the 68000 series, contains
in terms of instructions/features.
Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/m68k/cpu.c | 44 ++++++++++++++++++++++++++++++++++++++++++
target/m68k/cpu.h | 49 ++++++++++++++++++++++++++++-------------------
2 files changed, 73 insertions(+), 20 deletions(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index b811a0bdde..ccf1c490c0 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -103,6 +103,7 @@ static void m5206_cpu_initfn(Object *obj)
m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
}
+/* Base feature set, including isns. for m68k family */
static void m68000_cpu_initfn(Object *obj)
{
M68kCPU *cpu = M68K_CPU(obj);
@@ -135,6 +136,13 @@ static void m680x0_cpu_common(CPUM68KState *env)
m68k_set_feature(env, M68K_FEATURE_MOVEP);
}
+/*
+ * Adds BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST, CAS, CAS2,
+ * CHK2, CMP2, DIVSL, DIVUL, EXTB, PACK, TRAPcc, UNPK.
+ *
+ * 68020/30 only:
+ * CALLM, cpBcc, cpDBcc, cpGEN, cpRESTORE, cpSAVE, cpScc, cpTRAPcc
+ */
static void m68020_cpu_initfn(Object *obj)
{
M68kCPU *cpu = M68K_CPU(obj);
@@ -144,6 +152,14 @@ static void m68020_cpu_initfn(Object *obj)
m68k_set_feature(env, M68K_FEATURE_M68020);
}
+/*
+ * Adds: PFLUSH (*5)
+ * 68030 Only: PFLUSHA (*5), PLOAD (*5), PMOVE
+ * 68030/40 Only: PTEST
+ *
+ * NOTES:
+ * 5. Not valid on MC68EC030
+ */
static void m68030_cpu_initfn(Object *obj)
{
M68kCPU *cpu = M68K_CPU(obj);
@@ -153,6 +169,23 @@ static void m68030_cpu_initfn(Object *obj)
m68k_set_feature(env, M68K_FEATURE_M68030);
}
+/*
+ * Adds: CINV, CPUSH
+ * Adds all with Note *2: FABS, FSABS, FDABS, FADD, FSADD, FDADD, FBcc, FCMP,
+ * FDBcc, FDIV, FSDIV, FDDIV, FMOVE, FSMOVE, FDMOVE,
+ * FMOVEM, FMUL, FSMUL, FDMUL, FNEG, FSNEG, FDNEG, FNOP,
+ * FRESTORE, FSAVE, FScc, FSQRT, FSSQRT, FDSQRT, FSUB,
+ * FSSUB, FDSUB, FTRAPcc, FTST
+ *
+ * Adds with Notes *2, and *3: FACOS, FASIN, FATAN, FATANH, FCOS, FCOSH, FETOX,
+ * FETOXM, FGETEXP, FGETMAN, FINT, FINTRZ, FLOG10,
+ * FLOG2, FLOGN, FLOGNP1, FMOD, FMOVECR, FREM,
+ * FSCALE, FSGLDIV, FSGLMUL, FSIN, FSINCOS, FSINH,
+ * FTAN, FTANH, FTENTOX, FTWOTOX
+ * NOTES:
+ * 2. Not applicable to the MC68EC040, MC68LC040, MC68EC060, and MC68LC060.
+ * 3. These are software-supported instructions on the MC68040 and MC68060.
+ */
static void m68040_cpu_initfn(Object *obj)
{
M68kCPU *cpu = M68K_CPU(obj);
@@ -162,6 +195,17 @@ static void m68040_cpu_initfn(Object *obj)
m68k_set_feature(env, M68K_FEATURE_M68040);
}
+/*
+ * Adds: PLPA
+ * Adds all with Note *2: CAS, CAS2, MULS, MULU, CHK2, CMP2, DIVS, DIVU
+ * All Fxxxx instructions are as per m68040 with exception to; FMOVEM NOTE3
+ *
+ * Does NOT implement MOVEP
+ *
+ * NOTES:
+ * 2. Not applicable to the MC68EC040, MC68LC040, MC68EC060, and MC68LC060.
+ * 3. These are software-supported instructions on the MC68040 and MC68060.
+ */
static void m68060_cpu_initfn(Object *obj)
{
M68kCPU *cpu = M68K_CPU(obj);
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index de5b9875fe..1d59cbb3f4 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -450,39 +450,48 @@ void m68k_switch_sp(CPUM68KState *env);
void do_m68k_semihosting(CPUM68KState *env, int nr);
/*
+ * The 68000 family is defined in six main CPU classes, the 680[012346]0.
+ * Generally each successive CPU adds enhanced data/stack/instructions.
+ * However, some features are only common to one, or a few classes.
+ * The features covers those subsets of instructons.
+ *
+ * CPU32/32+ are basically 680010 compatible with some 68020 class instructons,
+ * and some additional CPU32 instructions. Mostly Supervisor state differences.
+ *
+ * The ColdFire core ISA is a RISC-style reduction of the 68000 series cpu.
* There are 4 ColdFire core ISA revisions: A, A+, B and C.
* Each feature covers the subset of instructions common to the
* ISA revisions mentioned.
*/
enum m68k_features {
- M68K_FEATURE_M68000,
+ M68K_FEATURE_M68000, /* Base m68k instruction set */
M68K_FEATURE_M68020,
M68K_FEATURE_M68030,
M68K_FEATURE_M68040,
M68K_FEATURE_M68060,
- M68K_FEATURE_CF_ISA_A,
- M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
- M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
- M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
+ M68K_FEATURE_CF_ISA_A, /* Base Coldfire set Rev A. */
+ M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
+ M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
+ M68K_FEATURE_BRAL, /* BRA with Long branch. (680[2346]0, ISA A+ or B). */
M68K_FEATURE_CF_FPU,
M68K_FEATURE_CF_MAC,
M68K_FEATURE_CF_EMAC,
- M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
- M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
- M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
- M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */
- M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */
- M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
- M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
- M68K_FEATURE_BCCL, /* Long conditional branches. */
- M68K_FEATURE_BITFIELD, /* Bit field insns. */
- M68K_FEATURE_FPU,
- M68K_FEATURE_CAS,
- M68K_FEATURE_BKPT,
- M68K_FEATURE_RTD,
- M68K_FEATURE_CHK2,
- M68K_FEATURE_MOVEP,
+ M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
+ M68K_FEATURE_USP, /* User Stack Pointer. (680[012346]0, ISA A+, B or C).*/
+ M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
+ M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */
+ M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */
+ M68K_FEATURE_LONG_MULDIV, /* 32 bit mul/div. (680[2346]0, and CPU32) */
+ M68K_FEATURE_QUAD_MULDIV, /* 64 bit mul/div. (680[2346]0, and CPU32) */
+ M68K_FEATURE_BCCL, /* Bcc with Long branches. (680[2346]0, and CPU32) */
+ M68K_FEATURE_BITFIELD, /* BFxxx Bit field insns. (680[2346]0) */
+ M68K_FEATURE_FPU, /* fpu insn. (680[46]0) */
+ M68K_FEATURE_CAS, /* CAS/CAS2[WL] insns. (680[2346]0) */
+ M68K_FEATURE_BKPT, /* BKPT insn. (680[12346]0, and CPU32) */
+ M68K_FEATURE_RTD, /* RTD insn. (680[12346]0, and CPU32) */
+ M68K_FEATURE_CHK2, /* CHK2 insn. (680[2346]0, and CPU32) */
+ M68K_FEATURE_MOVEP, /* MOVEP insn. (680[01234]0, and CPU32) */
};
static inline int m68k_feature(CPUM68KState *env, int feature)
--
2.21.3
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 6/6] m68k: add MSP detection support for stack pointer swap helpers
2021-02-01 0:01 [PATCH 0/6] m68k: Overhaul of MOVEC instruction to support exception/MSP BALATON Zoltan
2021-02-01 0:01 ` [PATCH 1/6] m68k: improve cpu instantiation comments BALATON Zoltan
@ 2021-02-01 0:01 ` BALATON Zoltan
2021-02-01 0:01 ` [PATCH 4/6] m68k: add missing BUSCR/PCR CR defines, and BUSCR/PCR/CAAR CR to m68k_move_to/from BALATON Zoltan
` (5 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: BALATON Zoltan @ 2021-02-01 0:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Laurent Vivier, Lucien Murray-Pitts
From: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
On m68k there are two varities of stack pointers: USP with SSP or ISP/MSP.
Only the 68020/30/40 support the MSP register the stack swap helpers don't
support this feature.
This patch adds this support, as well as comments to CPUM68KState to
make it clear how stacks are handled
Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/m68k/cpu.c | 1 +
target/m68k/cpu.h | 9 ++++++++-
target/m68k/helper.c | 3 ++-
3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 31f96df2a2..5586589301 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -160,6 +160,7 @@ static void m68020_cpu_initfn(Object *obj)
m68k_set_feature(env, M68K_FEATURE_FPU);
m68k_set_feature(env, M68K_FEATURE_CAS);
m68k_set_feature(env, M68K_FEATURE_CHK2);
+ m68k_set_feature(env, M68K_FEATURE_MSP);
}
/*
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 5d2cb012e5..7c3feeaf8a 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -85,7 +85,13 @@ typedef struct CPUM68KState {
uint32_t pc;
uint32_t sr;
- /* SSP and USP. The current_sp is stored in aregs[7], the other here. */
+ /*
+ * The 68020/30/40 support two supervisor stacks, ISP and MSP.
+ * The 68000/10, Coldfire, and CPU32 only have USP/SSP.
+ *
+ * The current_sp is stored in aregs[7], the other here.
+ * The USP, SSP, and if used the additional ISP for 68020/30/40.
+ */
int current_sp;
uint32_t sp[3];
@@ -484,6 +490,7 @@ enum m68k_features {
M68K_FEATURE_CF_EMAC,
M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
M68K_FEATURE_USP, /* User Stack Pointer. (680[012346]0, ISA A+, B or C).*/
+ M68K_FEATURE_MSP, /* Master Stack Pointer. (680[234]0) */
M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */
M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 1efd6e4f65..4185ca94ce 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -463,7 +463,8 @@ void m68k_switch_sp(CPUM68KState *env)
env->sp[env->current_sp] = env->aregs[7];
if (m68k_feature(env, M68K_FEATURE_M68000)) {
if (env->sr & SR_S) {
- if (env->sr & SR_M) {
+ /* SR:Master-Mode bit unimplemented then ISP is not available */
+ if (!m68k_feature(env, M68K_FEATURE_MSP) || env->sr & SR_M) {
new_sp = M68K_SSP;
} else {
new_sp = M68K_ISP;
--
2.21.3
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 4/6] m68k: add missing BUSCR/PCR CR defines, and BUSCR/PCR/CAAR CR to m68k_move_to/from
2021-02-01 0:01 [PATCH 0/6] m68k: Overhaul of MOVEC instruction to support exception/MSP BALATON Zoltan
2021-02-01 0:01 ` [PATCH 1/6] m68k: improve cpu instantiation comments BALATON Zoltan
2021-02-01 0:01 ` [PATCH 6/6] m68k: add MSP detection support for stack pointer swap helpers BALATON Zoltan
@ 2021-02-01 0:01 ` BALATON Zoltan
2021-02-01 7:34 ` Philippe Mathieu-Daudé
2021-02-01 0:01 ` [PATCH 2/6] m68k: cascade m68k_features by m680xx_cpu_initfn() to improve readability BALATON Zoltan
` (4 subsequent siblings)
7 siblings, 1 reply; 10+ messages in thread
From: BALATON Zoltan @ 2021-02-01 0:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Laurent Vivier, Lucien Murray-Pitts
From: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
The BUSCR/PCR CR defines were missing for 68060, and the move_to/from helper
functions were also missing a decode for the 68060 M68K_CR_CAAR CR register.
Added missing defines, and respective decodes for all three CR registers to
the helpers.
Although this patch defines them, the implementation is empty in this patch
and these registers will result in a cpu abort - which is the default prior
to this patch.
This patch aims to reach full coverage of all CR registers within the helpers.
Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/m68k/cpu.h | 4 ++++
target/m68k/helper.c | 10 ++++++++++
2 files changed, 14 insertions(+)
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 2b1cdf241b..ae34c94615 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -393,6 +393,10 @@ typedef enum {
#define M68K_CR_DACR0 0x006
#define M68K_CR_DACR1 0x007
+/* MC68060 */
+#define M68K_CR_BUSCR 0x008
+#define M68K_CR_PCR 0x808
+
#define M68K_FPIAR_SHIFT 0
#define M68K_FPIAR (1 << M68K_FPIAR_SHIFT)
#define M68K_FPSR_SHIFT 1
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 9e81ee53ad..69acdc3b35 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -255,6 +255,11 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
case M68K_CR_DTT1:
env->mmu.ttr[M68K_DTTR1] = val;
return;
+ /* Unimplemented Registers */
+ case M68K_CR_CAAR:
+ case M68K_CR_PCR:
+ case M68K_CR_BUSCR:
+ break;
}
cpu_abort(env_cpu(env),
"Unimplemented control register write 0x%x = 0x%x\n",
@@ -309,6 +314,11 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
/* MC68040/MC68LC040 */
case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */
return env->mmu.ttr[M68K_DTTR1];
+ /* Unimplemented Registers */
+ case M68K_CR_CAAR:
+ case M68K_CR_PCR:
+ case M68K_CR_BUSCR:
+ break;
}
cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n",
reg);
--
2.21.3
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 4/6] m68k: add missing BUSCR/PCR CR defines, and BUSCR/PCR/CAAR CR to m68k_move_to/from
2021-02-01 0:01 ` [PATCH 4/6] m68k: add missing BUSCR/PCR CR defines, and BUSCR/PCR/CAAR CR to m68k_move_to/from BALATON Zoltan
@ 2021-02-01 7:34 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-01 7:34 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel; +Cc: Laurent Vivier, Lucien Murray-Pitts
On 2/1/21 1:01 AM, BALATON Zoltan wrote:
> From: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
>
> The BUSCR/PCR CR defines were missing for 68060, and the move_to/from helper
> functions were also missing a decode for the 68060 M68K_CR_CAAR CR register.
>
> Added missing defines, and respective decodes for all three CR registers to
> the helpers.
>
> Although this patch defines them, the implementation is empty in this patch
> and these registers will result in a cpu abort - which is the default prior
> to this patch.
>
> This patch aims to reach full coverage of all CR registers within the helpers.
>
> Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/m68k/cpu.h | 4 ++++
> target/m68k/helper.c | 10 ++++++++++
> 2 files changed, 14 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/6] m68k: cascade m68k_features by m680xx_cpu_initfn() to improve readability
2021-02-01 0:01 [PATCH 0/6] m68k: Overhaul of MOVEC instruction to support exception/MSP BALATON Zoltan
` (2 preceding siblings ...)
2021-02-01 0:01 ` [PATCH 4/6] m68k: add missing BUSCR/PCR CR defines, and BUSCR/PCR/CAAR CR to m68k_move_to/from BALATON Zoltan
@ 2021-02-01 0:01 ` BALATON Zoltan
2021-02-01 0:01 ` [PATCH 3/6] m68k: improve comments on m68k_move_to/from helpers BALATON Zoltan
` (3 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: BALATON Zoltan @ 2021-02-01 0:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Laurent Vivier, Lucien Murray-Pitts
From: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
The m680XX_cpu_initfn functions have been rearranged to cascade starting from
the base 68000, so that the 68010 then inherits from this, and so on until the
68060.
This makes it simpler to track features since in most cases the m68k were
product enhancements on each other, with only a few instructions being retired.
Because each cpu class inherits the previous CPU class, then for example
the 68020 also has the feature 68010, and 68000 and so on upto the 68060.
- Added 68010 cpu class, and moved correct features into 68000/68010.
- Added m68k_unset_feature to allow removing a feature in the inheritence
Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/m68k/cpu.c | 72 +++++++++++++++++++++++++----------------------
target/m68k/cpu.h | 1 +
2 files changed, 39 insertions(+), 34 deletions(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index ccf1c490c0..5e7aec5b13 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -41,6 +41,11 @@ static void m68k_set_feature(CPUM68KState *env, int feature)
env->features |= (1u << feature);
}
+static void m68k_unset_feature(CPUM68KState *env, int feature)
+{
+ env->features &= (-1u - (1u << feature));
+}
+
static void m68k_cpu_reset(DeviceState *dev)
{
CPUState *s = CPU(dev);
@@ -115,25 +120,18 @@ static void m68000_cpu_initfn(Object *obj)
m68k_set_feature(env, M68K_FEATURE_MOVEP);
}
-/* common features for 68020, 68030 and 68040 */
-static void m680x0_cpu_common(CPUM68KState *env)
+/*
+ * Adds BKPT, MOVE-from-SR *now priv instr, and MOVEC, MOVES, RTD
+ */
+static void m68010_cpu_initfn(Object *obj)
{
- m68k_set_feature(env, M68K_FEATURE_M68000);
- m68k_set_feature(env, M68K_FEATURE_USP);
- m68k_set_feature(env, M68K_FEATURE_WORD_INDEX);
- m68k_set_feature(env, M68K_FEATURE_QUAD_MULDIV);
- m68k_set_feature(env, M68K_FEATURE_BRAL);
- m68k_set_feature(env, M68K_FEATURE_BCCL);
- m68k_set_feature(env, M68K_FEATURE_BITFIELD);
- m68k_set_feature(env, M68K_FEATURE_EXT_FULL);
- m68k_set_feature(env, M68K_FEATURE_SCALED_INDEX);
- m68k_set_feature(env, M68K_FEATURE_LONG_MULDIV);
- m68k_set_feature(env, M68K_FEATURE_FPU);
- m68k_set_feature(env, M68K_FEATURE_CAS);
- m68k_set_feature(env, M68K_FEATURE_BKPT);
+ M68kCPU *cpu = M68K_CPU(obj);
+ CPUM68KState *env = &cpu->env;
+
+ m68000_cpu_initfn(obj);
+ m68k_set_feature(env, M68K_FEATURE_M68010);
m68k_set_feature(env, M68K_FEATURE_RTD);
- m68k_set_feature(env, M68K_FEATURE_CHK2);
- m68k_set_feature(env, M68K_FEATURE_MOVEP);
+ m68k_set_feature(env, M68K_FEATURE_BKPT);
}
/*
@@ -148,8 +146,19 @@ static void m68020_cpu_initfn(Object *obj)
M68kCPU *cpu = M68K_CPU(obj);
CPUM68KState *env = &cpu->env;
- m680x0_cpu_common(env);
+ m68010_cpu_initfn(obj);
+ m68k_unset_feature(env, M68K_FEATURE_M68010);
m68k_set_feature(env, M68K_FEATURE_M68020);
+ m68k_set_feature(env, M68K_FEATURE_QUAD_MULDIV);
+ m68k_set_feature(env, M68K_FEATURE_BRAL);
+ m68k_set_feature(env, M68K_FEATURE_BCCL);
+ m68k_set_feature(env, M68K_FEATURE_BITFIELD);
+ m68k_set_feature(env, M68K_FEATURE_EXT_FULL);
+ m68k_set_feature(env, M68K_FEATURE_SCALED_INDEX);
+ m68k_set_feature(env, M68K_FEATURE_LONG_MULDIV);
+ m68k_set_feature(env, M68K_FEATURE_FPU);
+ m68k_set_feature(env, M68K_FEATURE_CAS);
+ m68k_set_feature(env, M68K_FEATURE_CHK2);
}
/*
@@ -165,7 +174,8 @@ static void m68030_cpu_initfn(Object *obj)
M68kCPU *cpu = M68K_CPU(obj);
CPUM68KState *env = &cpu->env;
- m680x0_cpu_common(env);
+ m68020_cpu_initfn(obj);
+ m68k_unset_feature(env, M68K_FEATURE_M68020);
m68k_set_feature(env, M68K_FEATURE_M68030);
}
@@ -191,7 +201,8 @@ static void m68040_cpu_initfn(Object *obj)
M68kCPU *cpu = M68K_CPU(obj);
CPUM68KState *env = &cpu->env;
- m680x0_cpu_common(env);
+ m68030_cpu_initfn(obj);
+ m68k_unset_feature(env, M68K_FEATURE_M68030);
m68k_set_feature(env, M68K_FEATURE_M68040);
}
@@ -211,21 +222,13 @@ static void m68060_cpu_initfn(Object *obj)
M68kCPU *cpu = M68K_CPU(obj);
CPUM68KState *env = &cpu->env;
- m68k_set_feature(env, M68K_FEATURE_M68000);
- m68k_set_feature(env, M68K_FEATURE_USP);
- m68k_set_feature(env, M68K_FEATURE_WORD_INDEX);
- m68k_set_feature(env, M68K_FEATURE_BRAL);
- m68k_set_feature(env, M68K_FEATURE_BCCL);
- m68k_set_feature(env, M68K_FEATURE_BITFIELD);
- m68k_set_feature(env, M68K_FEATURE_EXT_FULL);
- m68k_set_feature(env, M68K_FEATURE_SCALED_INDEX);
- m68k_set_feature(env, M68K_FEATURE_LONG_MULDIV);
- m68k_set_feature(env, M68K_FEATURE_FPU);
- m68k_set_feature(env, M68K_FEATURE_CAS);
- m68k_set_feature(env, M68K_FEATURE_BKPT);
- m68k_set_feature(env, M68K_FEATURE_RTD);
- m68k_set_feature(env, M68K_FEATURE_CHK2);
+ m68040_cpu_initfn(obj);
+ m68k_unset_feature(env, M68K_FEATURE_M68040);
m68k_set_feature(env, M68K_FEATURE_M68060);
+ m68k_unset_feature(env, M68K_FEATURE_MOVEP);
+
+ /* Implemented as a software feature */
+ m68k_unset_feature(env, M68K_FEATURE_QUAD_MULDIV);
}
static void m5208_cpu_initfn(Object *obj)
@@ -568,6 +571,7 @@ static const TypeInfo m68k_cpus_type_infos[] = {
.class_init = m68k_cpu_class_init,
},
DEFINE_M68K_CPU_TYPE_M68K(m68000),
+ DEFINE_M68K_CPU_TYPE_M68K(m68010),
DEFINE_M68K_CPU_TYPE_M68K(m68020),
DEFINE_M68K_CPU_TYPE_M68K(m68030),
DEFINE_M68K_CPU_TYPE_M68K(m68040),
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 1d59cbb3f4..2b1cdf241b 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -466,6 +466,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr);
enum m68k_features {
M68K_FEATURE_M68000, /* Base m68k instruction set */
+ M68K_FEATURE_M68010,
M68K_FEATURE_M68020,
M68K_FEATURE_M68030,
M68K_FEATURE_M68040,
--
2.21.3
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 3/6] m68k: improve comments on m68k_move_to/from helpers
2021-02-01 0:01 [PATCH 0/6] m68k: Overhaul of MOVEC instruction to support exception/MSP BALATON Zoltan
` (3 preceding siblings ...)
2021-02-01 0:01 ` [PATCH 2/6] m68k: cascade m68k_features by m680xx_cpu_initfn() to improve readability BALATON Zoltan
@ 2021-02-01 0:01 ` BALATON Zoltan
2021-02-01 0:01 ` [PATCH 5/6] m68k: MOVEC insn. should generate exception if wrong CR is accessed BALATON Zoltan
` (2 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: BALATON Zoltan @ 2021-02-01 0:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Laurent Vivier, Lucien Murray-Pitts
From: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
Add more detailed comments to each case of m68k_move_to/from helpers to list
the supported CPUs for that CR as they were wrong in some cases, and
missing some cpu classes in other cases.
Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/m68k/helper.c | 39 ++++++++++++++++++++++++++++++---------
1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 3ff5765795..9e81ee53ad 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -187,13 +187,15 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
{
switch (reg) {
- /* MC680[1234]0 */
+ /* MC680[12346]0 */
case M68K_CR_SFC:
env->sfc = val & 7;
return;
+ /* MC680[12346]0 */
case M68K_CR_DFC:
env->dfc = val & 7;
return;
+ /* MC680[12346]0 */
case M68K_CR_VBR:
env->vbr = val;
return;
@@ -210,25 +212,30 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
}
m68k_switch_sp(env);
return;
- /* MC680[34]0 */
+ /* MC680[46]0 */
case M68K_CR_TC:
env->mmu.tcr = val;
return;
+ /* MC68040 */
case M68K_CR_MMUSR:
env->mmu.mmusr = val;
return;
+ /* MC680[46]0 */
case M68K_CR_SRP:
env->mmu.srp = val;
return;
case M68K_CR_URP:
env->mmu.urp = val;
return;
+ /* MC680[46]0 */
case M68K_CR_USP:
env->sp[M68K_USP] = val;
return;
+ /* MC680[234]0 */
case M68K_CR_MSP:
env->sp[M68K_SSP] = val;
return;
+ /* MC680[234]0 */
case M68K_CR_ISP:
env->sp[M68K_ISP] = val;
return;
@@ -236,12 +243,15 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
case M68K_CR_ITT0:
env->mmu.ttr[M68K_ITTR0] = val;
return;
+ /* MC68040/MC68LC040 */
case M68K_CR_ITT1:
env->mmu.ttr[M68K_ITTR1] = val;
return;
+ /* MC68040/MC68LC040 */
case M68K_CR_DTT0:
env->mmu.ttr[M68K_DTTR0] = val;
return;
+ /* MC68040/MC68LC040 */
case M68K_CR_DTT1:
env->mmu.ttr[M68K_DTTR1] = val;
return;
@@ -254,39 +264,50 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
{
switch (reg) {
- /* MC680[1234]0 */
+ /* MC680[12346]0 */
case M68K_CR_SFC:
return env->sfc;
+ /* MC680[12346]0 */
case M68K_CR_DFC:
return env->dfc;
+ /* MC680[12346]0 */
case M68K_CR_VBR:
return env->vbr;
- /* MC680[234]0 */
+ /* MC680[2346]0 */
case M68K_CR_CACR:
return env->cacr;
- /* MC680[34]0 */
+ /* MC680[46]0 */
case M68K_CR_TC:
return env->mmu.tcr;
+ /* MC68040 */
case M68K_CR_MMUSR:
return env->mmu.mmusr;
+ /* MC680[46]0 */
case M68K_CR_SRP:
return env->mmu.srp;
+ /* MC680[46]0 */
case M68K_CR_USP:
return env->sp[M68K_USP];
+ /* MC680[234]0 */
case M68K_CR_MSP:
return env->sp[M68K_SSP];
+ /* MC680[234]0 */
case M68K_CR_ISP:
return env->sp[M68K_ISP];
/* MC68040/MC68LC040 */
case M68K_CR_URP:
return env->mmu.urp;
- case M68K_CR_ITT0:
+ /* MC68040/MC68LC040 */
+ case M68K_CR_ITT0: /* MC68EC040 only: M68K_CR_IACR0 */
return env->mmu.ttr[M68K_ITTR0];
- case M68K_CR_ITT1:
+ /* MC68040/MC68LC040 */
+ case M68K_CR_ITT1: /* MC68EC040 only: M68K_CR_IACR1 */
return env->mmu.ttr[M68K_ITTR1];
- case M68K_CR_DTT0:
+ /* MC68040/MC68LC040 */
+ case M68K_CR_DTT0: /* MC68EC040 only: M68K_CR_DACR0 */
return env->mmu.ttr[M68K_DTTR0];
- case M68K_CR_DTT1:
+ /* MC68040/MC68LC040 */
+ case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */
return env->mmu.ttr[M68K_DTTR1];
}
cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n",
--
2.21.3
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 5/6] m68k: MOVEC insn. should generate exception if wrong CR is accessed
2021-02-01 0:01 [PATCH 0/6] m68k: Overhaul of MOVEC instruction to support exception/MSP BALATON Zoltan
` (4 preceding siblings ...)
2021-02-01 0:01 ` [PATCH 3/6] m68k: improve comments on m68k_move_to/from helpers BALATON Zoltan
@ 2021-02-01 0:01 ` BALATON Zoltan
2021-02-09 16:53 ` [PATCH 0/6] m68k: Overhaul of MOVEC instruction to support exception/MSP BALATON Zoltan
2021-02-11 20:16 ` Laurent Vivier
7 siblings, 0 replies; 10+ messages in thread
From: BALATON Zoltan @ 2021-02-01 0:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Laurent Vivier, Lucien Murray-Pitts
From: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
Add CPU class detection for each CR type in the m68k_move_to/from helpers,
so that it throws and exception if an unsupported register is requested
for that CPU class.
Reclassified MOVEC insn. as only supported from 68010.
Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/m68k/cpu.c | 1 +
target/m68k/cpu.h | 1 +
target/m68k/helper.c | 188 ++++++++++++++++++++++++++++++----------
target/m68k/translate.c | 2 +-
4 files changed, 146 insertions(+), 46 deletions(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 5e7aec5b13..31f96df2a2 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -132,6 +132,7 @@ static void m68010_cpu_initfn(Object *obj)
m68k_set_feature(env, M68K_FEATURE_M68010);
m68k_set_feature(env, M68K_FEATURE_RTD);
m68k_set_feature(env, M68K_FEATURE_BKPT);
+ m68k_set_feature(env, M68K_FEATURE_MOVEC);
}
/*
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index ae34c94615..5d2cb012e5 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -497,6 +497,7 @@ enum m68k_features {
M68K_FEATURE_RTD, /* RTD insn. (680[12346]0, and CPU32) */
M68K_FEATURE_CHK2, /* CHK2 insn. (680[2346]0, and CPU32) */
M68K_FEATURE_MOVEP, /* MOVEP insn. (680[01234]0, and CPU32) */
+ M68K_FEATURE_MOVEC, /* MOVEC insn. (from 68010) */
};
static inline int m68k_feature(CPUM68KState *env, int feature)
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 69acdc3b35..1efd6e4f65 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -184,6 +184,14 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
}
}
+static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)
+{
+ CPUState *cs = env_cpu(env);
+
+ cs->exception_index = tt;
+ cpu_loop_exit_restore(cs, raddr);
+}
+
void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
{
switch (reg) {
@@ -209,61 +217,104 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
env->cacr = val & 0x80008000;
} else if (m68k_feature(env, M68K_FEATURE_M68060)) {
env->cacr = val & 0xf8e0e000;
+ } else {
+ break;
}
m68k_switch_sp(env);
return;
/* MC680[46]0 */
case M68K_CR_TC:
- env->mmu.tcr = val;
- return;
+ if (m68k_feature(env, M68K_FEATURE_M68040)
+ || m68k_feature(env, M68K_FEATURE_M68060)) {
+ env->mmu.tcr = val;
+ return;
+ }
+ break;
/* MC68040 */
case M68K_CR_MMUSR:
- env->mmu.mmusr = val;
- return;
+ if (m68k_feature(env, M68K_FEATURE_M68040)) {
+ env->mmu.mmusr = val;
+ return;
+ }
+ break;
/* MC680[46]0 */
case M68K_CR_SRP:
- env->mmu.srp = val;
- return;
- case M68K_CR_URP:
- env->mmu.urp = val;
- return;
+ if (m68k_feature(env, M68K_FEATURE_M68040)
+ || m68k_feature(env, M68K_FEATURE_M68060)) {
+ env->mmu.srp = val;
+ return;
+ }
+ break;
/* MC680[46]0 */
+ case M68K_CR_URP:
+ if (m68k_feature(env, M68K_FEATURE_M68040)
+ || m68k_feature(env, M68K_FEATURE_M68060)) {
+ env->mmu.urp = val;
+ return;
+ }
+ break;
+ /* MC680[12346]0 */
case M68K_CR_USP:
env->sp[M68K_USP] = val;
return;
/* MC680[234]0 */
case M68K_CR_MSP:
- env->sp[M68K_SSP] = val;
- return;
+ if (m68k_feature(env, M68K_FEATURE_M68020)
+ || m68k_feature(env, M68K_FEATURE_M68030)
+ || m68k_feature(env, M68K_FEATURE_M68040)) {
+ env->sp[M68K_SSP] = val;
+ return;
+ }
+ break;
/* MC680[234]0 */
case M68K_CR_ISP:
- env->sp[M68K_ISP] = val;
- return;
+ if (m68k_feature(env, M68K_FEATURE_M68020)
+ || m68k_feature(env, M68K_FEATURE_M68030)
+ || m68k_feature(env, M68K_FEATURE_M68040)) {
+ env->sp[M68K_ISP] = val;
+ return;
+ }
+ break;
/* MC68040/MC68LC040 */
- case M68K_CR_ITT0:
- env->mmu.ttr[M68K_ITTR0] = val;
- return;
+ case M68K_CR_ITT0: /* MC68EC040 only: M68K_CR_IACR0 */
+ if (m68k_feature(env, M68K_FEATURE_M68040)) {
+ env->mmu.ttr[M68K_ITTR0] = val;
+ return;
+ }
+ break;
/* MC68040/MC68LC040 */
- case M68K_CR_ITT1:
- env->mmu.ttr[M68K_ITTR1] = val;
- return;
+ case M68K_CR_ITT1: /* MC68EC040 only: M68K_CR_IACR1 */
+ if (m68k_feature(env, M68K_FEATURE_M68040)) {
+ env->mmu.ttr[M68K_ITTR1] = val;
+ return;
+ }
+ break;
/* MC68040/MC68LC040 */
- case M68K_CR_DTT0:
- env->mmu.ttr[M68K_DTTR0] = val;
- return;
+ case M68K_CR_DTT0: /* MC68EC040 only: M68K_CR_DACR0 */
+ if (m68k_feature(env, M68K_FEATURE_M68040)) {
+ env->mmu.ttr[M68K_DTTR0] = val;
+ return;
+ }
+ break;
/* MC68040/MC68LC040 */
- case M68K_CR_DTT1:
- env->mmu.ttr[M68K_DTTR1] = val;
- return;
+ case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */
+ if (m68k_feature(env, M68K_FEATURE_M68040)) {
+ env->mmu.ttr[M68K_DTTR1] = val;
+ return;
+ }
+ break;
/* Unimplemented Registers */
case M68K_CR_CAAR:
case M68K_CR_PCR:
case M68K_CR_BUSCR:
- break;
+ cpu_abort(env_cpu(env),
+ "Unimplemented control register write 0x%x = 0x%x\n",
+ reg, val);
}
- cpu_abort(env_cpu(env),
- "Unimplemented control register write 0x%x = 0x%x\n",
- reg, val);
+
+ /* Invalid control registers will generate an exception. */
+ raise_exception_ra(env, EXCP_ILLEGAL, 0);
+ return;
}
uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
@@ -280,48 +331,95 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
return env->vbr;
/* MC680[2346]0 */
case M68K_CR_CACR:
- return env->cacr;
+ if (m68k_feature(env, M68K_FEATURE_M68020)
+ || m68k_feature(env, M68K_FEATURE_M68030)
+ || m68k_feature(env, M68K_FEATURE_M68040)
+ || m68k_feature(env, M68K_FEATURE_M68060)) {
+ return env->cacr;
+ }
+ break;
/* MC680[46]0 */
case M68K_CR_TC:
- return env->mmu.tcr;
+ if (m68k_feature(env, M68K_FEATURE_M68040)
+ || m68k_feature(env, M68K_FEATURE_M68060)) {
+ return env->mmu.tcr;
+ }
+ break;
/* MC68040 */
case M68K_CR_MMUSR:
- return env->mmu.mmusr;
+ if (m68k_feature(env, M68K_FEATURE_M68040)) {
+ return env->mmu.mmusr;
+ }
+ break;
/* MC680[46]0 */
case M68K_CR_SRP:
- return env->mmu.srp;
+ if (m68k_feature(env, M68K_FEATURE_M68040)
+ || m68k_feature(env, M68K_FEATURE_M68060)) {
+ return env->mmu.srp;
+ }
+ break;
+ /* MC68040/MC68LC040 */
+ case M68K_CR_URP:
+ if (m68k_feature(env, M68K_FEATURE_M68040)
+ || m68k_feature(env, M68K_FEATURE_M68060)) {
+ return env->mmu.urp;
+ }
+ break;
/* MC680[46]0 */
case M68K_CR_USP:
return env->sp[M68K_USP];
/* MC680[234]0 */
case M68K_CR_MSP:
- return env->sp[M68K_SSP];
+ if (m68k_feature(env, M68K_FEATURE_M68020)
+ || m68k_feature(env, M68K_FEATURE_M68030)
+ || m68k_feature(env, M68K_FEATURE_M68040)) {
+ return env->sp[M68K_SSP];
+ }
+ break;
/* MC680[234]0 */
case M68K_CR_ISP:
- return env->sp[M68K_ISP];
- /* MC68040/MC68LC040 */
- case M68K_CR_URP:
- return env->mmu.urp;
+ if (m68k_feature(env, M68K_FEATURE_M68020)
+ || m68k_feature(env, M68K_FEATURE_M68030)
+ || m68k_feature(env, M68K_FEATURE_M68040)) {
+ return env->sp[M68K_ISP];
+ }
+ break;
/* MC68040/MC68LC040 */
case M68K_CR_ITT0: /* MC68EC040 only: M68K_CR_IACR0 */
- return env->mmu.ttr[M68K_ITTR0];
+ if (m68k_feature(env, M68K_FEATURE_M68040)) {
+ return env->mmu.ttr[M68K_ITTR0];
+ }
+ break;
/* MC68040/MC68LC040 */
case M68K_CR_ITT1: /* MC68EC040 only: M68K_CR_IACR1 */
- return env->mmu.ttr[M68K_ITTR1];
+ if (m68k_feature(env, M68K_FEATURE_M68040)) {
+ return env->mmu.ttr[M68K_ITTR1];
+ }
+ break;
/* MC68040/MC68LC040 */
case M68K_CR_DTT0: /* MC68EC040 only: M68K_CR_DACR0 */
- return env->mmu.ttr[M68K_DTTR0];
+ if (m68k_feature(env, M68K_FEATURE_M68040)) {
+ return env->mmu.ttr[M68K_DTTR0];
+ }
+ break;
/* MC68040/MC68LC040 */
case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */
- return env->mmu.ttr[M68K_DTTR1];
+ if (m68k_feature(env, M68K_FEATURE_M68040)) {
+ return env->mmu.ttr[M68K_DTTR1];
+ }
+ break;
/* Unimplemented Registers */
case M68K_CR_CAAR:
case M68K_CR_PCR:
case M68K_CR_BUSCR:
- break;
+ cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n",
+ reg);
}
- cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n",
- reg);
+
+ /* Invalid control registers will generate an exception. */
+ raise_exception_ra(env, EXCP_ILLEGAL, 0);
+
+ return 0;
}
void HELPER(set_macsr)(CPUM68KState *env, uint32_t val)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 133a404919..ac936ebe8f 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -6010,7 +6010,7 @@ void register_m68k_insns (CPUM68KState *env)
BASE(stop, 4e72, ffff);
BASE(rte, 4e73, ffff);
INSN(cf_movec, 4e7b, ffff, CF_ISA_A);
- INSN(m68k_movec, 4e7a, fffe, M68000);
+ INSN(m68k_movec, 4e7a, fffe, MOVEC);
#endif
BASE(nop, 4e71, ffff);
INSN(rtd, 4e74, ffff, RTD);
--
2.21.3
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 0/6] m68k: Overhaul of MOVEC instruction to support exception/MSP
2021-02-01 0:01 [PATCH 0/6] m68k: Overhaul of MOVEC instruction to support exception/MSP BALATON Zoltan
` (5 preceding siblings ...)
2021-02-01 0:01 ` [PATCH 5/6] m68k: MOVEC insn. should generate exception if wrong CR is accessed BALATON Zoltan
@ 2021-02-09 16:53 ` BALATON Zoltan
2021-02-11 20:16 ` Laurent Vivier
7 siblings, 0 replies; 10+ messages in thread
From: BALATON Zoltan @ 2021-02-09 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Laurent Vivier, Lucien Murray-Pitts
On Mon, 1 Feb 2021, BALATON Zoltan wrote:
> Hello,
>
> This is Lucien's m68k series rebased on and fixed up to work with
> current master as per previous discussion:
> https://lists.gnu.org/archive/html/qemu-devel/2020-01/msg02840.html
>
> I've left previous Reviewed-by tags for reference but these should
> probably be reviewed again. I've only lightly tested it so I don't
> know if everything is correct but it does seem to fix the problem my
> original patch tried to fix at least. More testing, review and help to
> finish this so it can be merged at last is welcome.
Ping?
> Regards,
> BALATON Zoltan
>
> Lucien Murray-Pitts (6):
> m68k: improve cpu instantiation comments
> m68k: cascade m68k_features by m680xx_cpu_initfn() to improve
> readability
> m68k: improve comments on m68k_move_to/from helpers
> m68k: add missing BUSCR/PCR CR defines, and BUSCR/PCR/CAAR CR to
> m68k_move_to/from
> m68k: MOVEC insn. should generate exception if wrong CR is accessed
> m68k: add MSP detection support for stack pointer swap helpers
>
> target/m68k/cpu.c | 116 ++++++++++++++------
> target/m68k/cpu.h | 64 +++++++----
> target/m68k/helper.c | 234 +++++++++++++++++++++++++++++++---------
> target/m68k/translate.c | 2 +-
> 4 files changed, 309 insertions(+), 107 deletions(-)
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 0/6] m68k: Overhaul of MOVEC instruction to support exception/MSP
2021-02-01 0:01 [PATCH 0/6] m68k: Overhaul of MOVEC instruction to support exception/MSP BALATON Zoltan
` (6 preceding siblings ...)
2021-02-09 16:53 ` [PATCH 0/6] m68k: Overhaul of MOVEC instruction to support exception/MSP BALATON Zoltan
@ 2021-02-11 20:16 ` Laurent Vivier
7 siblings, 0 replies; 10+ messages in thread
From: Laurent Vivier @ 2021-02-11 20:16 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel; +Cc: Lucien Murray-Pitts
Le 01/02/2021 à 01:01, BALATON Zoltan a écrit :
> Hello,
>
> This is Lucien's m68k series rebased on and fixed up to work with
> current master as per previous discussion:
> https://lists.gnu.org/archive/html/qemu-devel/2020-01/msg02840.html
>
> I've left previous Reviewed-by tags for reference but these should
> probably be reviewed again. I've only lightly tested it so I don't
> know if everything is correct but it does seem to fix the problem my
> original patch tried to fix at least. More testing, review and help to
> finish this so it can be merged at last is welcome.
>
> Regards,
> BALATON Zoltan
>
> Lucien Murray-Pitts (6):
> m68k: improve cpu instantiation comments
> m68k: cascade m68k_features by m680xx_cpu_initfn() to improve
> readability
> m68k: improve comments on m68k_move_to/from helpers
> m68k: add missing BUSCR/PCR CR defines, and BUSCR/PCR/CAAR CR to
> m68k_move_to/from
> m68k: MOVEC insn. should generate exception if wrong CR is accessed
> m68k: add MSP detection support for stack pointer swap helpers
>
> target/m68k/cpu.c | 116 ++++++++++++++------
> target/m68k/cpu.h | 64 +++++++----
> target/m68k/helper.c | 234 +++++++++++++++++++++++++++++++---------
> target/m68k/translate.c | 2 +-
> 4 files changed, 309 insertions(+), 107 deletions(-)
>
Series applied to my m68k-for-6.0 branch.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 10+ messages in thread