[PATCH] MIPS: OCTEON: Add OCTEON II build and configuration option

[PATCH] MIPS: OCTEON: Add OCTEON II build and configuration option

[jiaqingtong97]

From: Jia Qingtong <jiaqingtong97@163.com>

If building for OCTEON II only,we can select compiler options that
give better code, but will not run on earlier chips.

Signed-off-by: Jia Qingtong <jiaqingtong97@163.com>
---
 arch/mips/cavium-octeon/Kconfig | 9 +++++++++
 arch/mips/include/asm/sync.h    | 3 ++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 4984e462be30..3e0759142656 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -1,6 +1,15 @@
 # SPDX-License-Identifier: GPL-2.0
 if CPU_CAVIUM_OCTEON
 
+config CAVIUM_OCTEON2
+	bool "Build the kernel to be used only OCTEON II processor cores"
+	default "n"
+	help
+		This option enables the generation of Octeon2 specific
+		instructions by the compiler, resulting in a kernel that is
+		more efficient, but that will not run on Octeon and
+		OcteonPlus processor cores.
+
 config CAVIUM_CN63XXP1
 	bool "Enable CN63XXP1 errata workarounds"
 	default "n"
diff --git a/arch/mips/include/asm/sync.h b/arch/mips/include/asm/sync.h
index aabd097933fe..fda181c16c5f 100644
--- a/arch/mips/include/asm/sync.h
+++ b/arch/mips/include/asm/sync.h
@@ -155,10 +155,11 @@
  * effective barrier as noted by commit 6b07d38aaa52 ("MIPS: Octeon: Use
  * optimized memory barrier primitives."). Here we specify that the affected
  * sync instructions should be emitted twice.
+ * Cavium OcteonII and later CPUs has fixed above bug.
  * Note that this expression is evaluated by the assembler (not the compiler),
  * and that the assembler evaluates '==' as 0 or -1, not 0 or 1.
  */
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#if defined CONFIG_CPU_CAVIUM_OCTEON && !defined CONFIG_CAVIUM_OCTEON2
 # define __SYNC_rpt(type)	(1 - (type == __SYNC_wmb))
 #else
 # define __SYNC_rpt(type)	1
-- 
2.28.0

Re: [PATCH] MIPS: OCTEON: Add OCTEON II build and configuration option

[Jiaxun Yang]

在 2020/12/19 上午12:28, jiaqingtong97@163.com 写道:
> From: Jia Qingtong <jiaqingtong97@163.com>
>
> If building for OCTEON II only,we can select compiler options that
> give better code, but will not run on earlier chips.


I'd rather add a workaround Kconfig option and default y for it.
In case no other optimization can be enabled for OCTANE2, like

WORKAROUND_OCTANE_BARRIER

Thanks

- Jiaxun

>
> Signed-off-by: Jia Qingtong <jiaqingtong97@163.com>
> ---
>   arch/mips/cavium-octeon/Kconfig | 9 +++++++++
>   arch/mips/include/asm/sync.h    | 3 ++-
>   2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
> index 4984e462be30..3e0759142656 100644
> --- a/arch/mips/cavium-octeon/Kconfig
> +++ b/arch/mips/cavium-octeon/Kconfig
> @@ -1,6 +1,15 @@
>   # SPDX-License-Identifier: GPL-2.0
>   if CPU_CAVIUM_OCTEON
>   
> +config CAVIUM_OCTEON2
> +	bool "Build the kernel to be used only OCTEON II processor cores"
> +	default "n"
> +	help
> +		This option enables the generation of Octeon2 specific
> +		instructions by the compiler, resulting in a kernel that is
> +		more efficient, but that will not run on Octeon and
> +		OcteonPlus processor cores.
> +
>   config CAVIUM_CN63XXP1
>   	bool "Enable CN63XXP1 errata workarounds"
>   	default "n"
> diff --git a/arch/mips/include/asm/sync.h b/arch/mips/include/asm/sync.h
> index aabd097933fe..fda181c16c5f 100644
> --- a/arch/mips/include/asm/sync.h
> +++ b/arch/mips/include/asm/sync.h
> @@ -155,10 +155,11 @@
>    * effective barrier as noted by commit 6b07d38aaa52 ("MIPS: Octeon: Use
>    * optimized memory barrier primitives."). Here we specify that the affected
>    * sync instructions should be emitted twice.
> + * Cavium OcteonII and later CPUs has fixed above bug.
>    * Note that this expression is evaluated by the assembler (not the compiler),
>    * and that the assembler evaluates '==' as 0 or -1, not 0 or 1.
>    */
> -#ifdef CONFIG_CPU_CAVIUM_OCTEON
> +#if defined CONFIG_CPU_CAVIUM_OCTEON && !defined CONFIG_CAVIUM_OCTEON2
>   # define __SYNC_rpt(type)	(1 - (type == __SYNC_wmb))
>   #else
>   # define __SYNC_rpt(type)	1

Re: [PATCH] MIPS: OCTEON: Add OCTEON II build and configuration option

[Thomas Bogendoerfer]

On Sat, Dec 19, 2020 at 02:08:49PM +0800, Jiaxun Yang wrote:
> 
> 
> 在 2020/12/19 上午12:28, jiaqingtong97@163.com 写道:
> > From: Jia Qingtong <jiaqingtong97@163.com>
> > 
> > If building for OCTEON II only,we can select compiler options that
> > give better code, but will not run on earlier chips.
> 
> 
> I'd rather add a workaround Kconfig option and default y for it.
> In case no other optimization can be enabled for OCTANE2, like
> 
> WORKAROUND_OCTANE_BARRIER

please start them with WAR_ like the other workarounds I've converted
to Kconfig. Something like

WAR_OCTEON_BARRIER

But the description talks about different compiler options, which I don't
see in the patch ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

[PATCH v2] MIPS: OCTEON: Add WAR_OCTEON_BARRIER workaround config

[jiaqingtong97]

From: Jia Qingtong <jiaqingtong97@163.com>

Some Cavium Octeon CPUs(Octeon & Octeon Plus) suffer from a bug that
causes a single wmb ordering barrier to be ineffective, requiring
the use of 2 in sequence to provide an effective barrier.
This patch make workaroud as a config for CPUs who didn't suffer
from that bug.

Signed-off-by: Jia Qingtong <jiaqingtong97@163.com>
---
 arch/mips/cavium-octeon/Kconfig | 9 +++++++++
 arch/mips/include/asm/sync.h    | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 4984e462be30..0dc910683df9 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -1,6 +1,15 @@
 # SPDX-License-Identifier: GPL-2.0
 if CPU_CAVIUM_OCTEON
 
+config WAR_OCTEON_BARRIER
+	bool "Enable Octeon & Octeon Plus barrier workaround"
+	default "y"
+	help
+	  Some Cavium Octeon CPUs(Octeon & Octeon Plus)
+	  suffer from a bug that causes a single wmb ordering barrier
+	  to be ineffective, requiring the use of 2 in sequence
+	  to provide an effective barrier.
+
 config CAVIUM_CN63XXP1
 	bool "Enable CN63XXP1 errata workarounds"
 	default "n"
diff --git a/arch/mips/include/asm/sync.h b/arch/mips/include/asm/sync.h
index aabd097933fe..b24a2f82ef19 100644
--- a/arch/mips/include/asm/sync.h
+++ b/arch/mips/include/asm/sync.h
@@ -158,7 +158,7 @@
  * Note that this expression is evaluated by the assembler (not the compiler),
  * and that the assembler evaluates '==' as 0 or -1, not 0 or 1.
  */
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#ifdef CONFIG_WAR_OCTEON_BARRIER
 # define __SYNC_rpt(type)	(1 - (type == __SYNC_wmb))
 #else
 # define __SYNC_rpt(type)	1
-- 
2.28.0