All of lore.kernel.org
 help / color / mirror / Atom feed
* [Intel-gfx] [PATCH] drm/i915/display: Enable second VDSC engine for higher moderates
@ 2021-09-13 14:39 Vandita Kulkarni
  2021-09-13 15:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
                   ` (3 more replies)
  0 siblings, 4 replies; 20+ messages in thread
From: Vandita Kulkarni @ 2021-09-13 14:39 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, manasi.d.navare, Vandita Kulkarni

Each VDSC operates with 1ppc throughput, hence enable the second
VDSC engine when moderate is higher that the current cdclk.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 161c33b2c869..55878f65f724 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -70,6 +70,7 @@
 #include "intel_tc.h"
 #include "intel_vdsc.h"
 #include "intel_vrr.h"
+#include "intel_cdclk.h"
 
 #define DP_DPRX_ESI_LEN 14
 
@@ -1291,10 +1292,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 				       struct drm_connector_state *conn_state,
 				       struct link_config_limits *limits)
 {
+	struct intel_cdclk_state *cdclk_state;
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	const struct drm_display_mode *adjusted_mode =
 		&pipe_config->hw.adjusted_mode;
+	struct intel_atomic_state *state =
+				to_intel_atomic_state(pipe_config->uapi.state);
 	int pipe_bpp;
 	int ret;
 
@@ -1373,12 +1377,16 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 		}
 	}
 
+	cdclk_state = intel_atomic_get_cdclk_state(state);
+	if (IS_ERR(cdclk_state))
+		return PTR_ERR(cdclk_state);
+
 	/*
 	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
-	 * is greater than the maximum Cdclock and if slice count is even
+	 * is greater than the current Cdclock and if slice count is even
 	 * then we need to use 2 VDSC instances.
 	 */
-	if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
+	if (adjusted_mode->crtc_clock > cdclk_state->actual.cdclk ||
 	    pipe_config->bigjoiner) {
 		if (pipe_config->dsc.slice_count < 2) {
 			drm_dbg_kms(&dev_priv->drm,
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-01-11  6:26 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-13 14:39 [Intel-gfx] [PATCH] drm/i915/display: Enable second VDSC engine for higher moderates Vandita Kulkarni
2021-09-13 15:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-09-13 17:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-14  7:19 ` [Intel-gfx] [PATCH] " Lisovskiy, Stanislav
2021-09-14  7:37   ` Kulkarni, Vandita
2021-09-14  7:28 ` Ville Syrjälä
2021-09-14  7:31   ` Kulkarni, Vandita
2021-09-14  7:48     ` Ville Syrjälä
2021-09-14  8:59       ` Lisovskiy, Stanislav
2021-09-14 12:04         ` Jani Nikula
2021-09-14 13:04           ` Lisovskiy, Stanislav
2021-09-14 13:32             ` Lisovskiy, Stanislav
2021-09-14 14:02               ` Jani Nikula
2021-09-14 14:40                 ` Kulkarni, Vandita
2021-09-14 15:10                   ` Jani Nikula
2022-01-10  7:15                     ` Kulkarni, Vandita
2022-01-10 19:36                       ` Navare, Manasi
2022-01-11  4:24                         ` Kulkarni, Vandita
2022-01-11  6:12                           ` Navare, Manasi
2022-01-11  6:26                             ` Kulkarni, Vandita

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.