From: Randy Dunlap <rdunlap@infradead.org> To: Christoph Muellner <christoph.muellner@vrull.eu>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Christoph Muellner <christoph.muellner@vrull.io>, Heiko Stuebner <heiko@sntech.de>, Philipp Tomsich <philipp.tomsich@vrull.eu>, Aaron Durbin <adurbin@rivosinc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH] riscv: Add Zawrs support for spinlocks Date: Thu, 2 Jun 2022 09:24:12 -0700 [thread overview] Message-ID: <cc1a2594-3596-a8e6-077d-183e69e3f4e7@infradead.org> (raw) In-Reply-To: <20220602141032.169907-1-christoph.muellner@vrull.io> Hi-- On 6/2/22 07:10, Christoph Muellner wrote: > The current RISC-V code uses the generic ticket lock implementation, > that calls the macros smp_cond_load_relaxed() and smp_cond_load_acquire(). > Currently, RISC-V uses the generic implementation of these macros. > This patch introduces a RISC-V specific implementation, of these > macros, that peels off the first loop iteration and modifies the waiting > loop such, that it is possible to use the WRS instruction of the Zawrs > ISA extension to stall the CPU. > > The resulting implementation of smp_cond_load_*() will only work for > 32-bit or 64-bit types for RV64 and 32-bit types for RV32. > This is caused by the restrictions of the LR instruction (RISC-V only > has LR.W and LR.D). Compiler assertions guard this new restriction. > > This patch uses the existing RISC-V ISA extension framework > to detect the presents of Zawrs at run-time. > If available a NOP instruction will be replaced by WRS. > A similar patch could add support for the PAUSE instruction of > the Zihintpause ISA extension. > > The whole mechanism is gated by Kconfig setting, which defaults to Y. > > The Zawrs specification can be found here: > https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc > > Note, that the Zawrs extension is not frozen or ratified yet. > Therefore this patch is an RFC and not intended to get merged. > > Signed-off-by: Christoph Muellner <christoph.muellner@vrull.io> > --- > arch/riscv/Kconfig | 10 +++ > arch/riscv/include/asm/barrier.h | 97 ++++++++++++++++++++++++++++ > arch/riscv/include/asm/errata_list.h | 12 +++- > arch/riscv/include/asm/hwcap.h | 3 +- > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 13 ++++ > 6 files changed, 133 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 905e550e0fd3..054872317d4a 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -358,6 +358,16 @@ config RISCV_ISA_C > > If you don't know what to do here, say Y. > > +config RISCV_ISA_ZAWRS > + bool "Zawrs extension support" > + select RISCV_ALTERNATIVE > + default y > + help > + Adds support to dynamically detect the presence of the Zawrs extension > + (wait for reservation set) and enable its usage. > + > + If you don't know what to do here, say Y. > + With this patch, it is possible to enable XIP_KERNEL and RISCV_ISA_ZAWRS at the same time. That causes a kconfig warning: WARNING: unmet direct dependencies detected for RISCV_ALTERNATIVE Depends on [n]: !XIP_KERNEL [=y] Selected by [y]: - RISCV_ISA_ZAWRS [=y] - RISCV_ISA_SVPBMT [=y] && 64BIT [=y] && MMU [=y] because RISCV_ALTERNATIVE depends on !XIP_KERNEL: config RISCV_ALTERNATIVE bool depends on !XIP_KERNEL > config RISCV_ISA_SVPBMT > bool "SVPBMT extension support" > depends on 64BIT && MMU -- ~Randy
WARNING: multiple messages have this Message-ID (diff)
From: Randy Dunlap <rdunlap@infradead.org> To: Christoph Muellner <christoph.muellner@vrull.eu>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Christoph Muellner <christoph.muellner@vrull.io>, Heiko Stuebner <heiko@sntech.de>, Philipp Tomsich <philipp.tomsich@vrull.eu>, Aaron Durbin <adurbin@rivosinc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH] riscv: Add Zawrs support for spinlocks Date: Thu, 2 Jun 2022 09:24:12 -0700 [thread overview] Message-ID: <cc1a2594-3596-a8e6-077d-183e69e3f4e7@infradead.org> (raw) In-Reply-To: <20220602141032.169907-1-christoph.muellner@vrull.io> Hi-- On 6/2/22 07:10, Christoph Muellner wrote: > The current RISC-V code uses the generic ticket lock implementation, > that calls the macros smp_cond_load_relaxed() and smp_cond_load_acquire(). > Currently, RISC-V uses the generic implementation of these macros. > This patch introduces a RISC-V specific implementation, of these > macros, that peels off the first loop iteration and modifies the waiting > loop such, that it is possible to use the WRS instruction of the Zawrs > ISA extension to stall the CPU. > > The resulting implementation of smp_cond_load_*() will only work for > 32-bit or 64-bit types for RV64 and 32-bit types for RV32. > This is caused by the restrictions of the LR instruction (RISC-V only > has LR.W and LR.D). Compiler assertions guard this new restriction. > > This patch uses the existing RISC-V ISA extension framework > to detect the presents of Zawrs at run-time. > If available a NOP instruction will be replaced by WRS. > A similar patch could add support for the PAUSE instruction of > the Zihintpause ISA extension. > > The whole mechanism is gated by Kconfig setting, which defaults to Y. > > The Zawrs specification can be found here: > https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc > > Note, that the Zawrs extension is not frozen or ratified yet. > Therefore this patch is an RFC and not intended to get merged. > > Signed-off-by: Christoph Muellner <christoph.muellner@vrull.io> > --- > arch/riscv/Kconfig | 10 +++ > arch/riscv/include/asm/barrier.h | 97 ++++++++++++++++++++++++++++ > arch/riscv/include/asm/errata_list.h | 12 +++- > arch/riscv/include/asm/hwcap.h | 3 +- > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 13 ++++ > 6 files changed, 133 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 905e550e0fd3..054872317d4a 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -358,6 +358,16 @@ config RISCV_ISA_C > > If you don't know what to do here, say Y. > > +config RISCV_ISA_ZAWRS > + bool "Zawrs extension support" > + select RISCV_ALTERNATIVE > + default y > + help > + Adds support to dynamically detect the presence of the Zawrs extension > + (wait for reservation set) and enable its usage. > + > + If you don't know what to do here, say Y. > + With this patch, it is possible to enable XIP_KERNEL and RISCV_ISA_ZAWRS at the same time. That causes a kconfig warning: WARNING: unmet direct dependencies detected for RISCV_ALTERNATIVE Depends on [n]: !XIP_KERNEL [=y] Selected by [y]: - RISCV_ISA_ZAWRS [=y] - RISCV_ISA_SVPBMT [=y] && 64BIT [=y] && MMU [=y] because RISCV_ALTERNATIVE depends on !XIP_KERNEL: config RISCV_ALTERNATIVE bool depends on !XIP_KERNEL > config RISCV_ISA_SVPBMT > bool "SVPBMT extension support" > depends on 64BIT && MMU -- ~Randy _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-06-02 16:24 UTC|newest] Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-02 14:10 [RFC PATCH] riscv: Add Zawrs support for spinlocks Christoph Muellner 2022-06-02 14:10 ` Christoph Muellner 2022-06-02 14:21 ` Heiko Stübner 2022-06-02 14:21 ` Heiko Stübner 2022-06-02 14:24 ` Christoph Müllner 2022-06-02 14:24 ` Christoph Müllner 2022-06-02 16:24 ` Randy Dunlap [this message] 2022-06-02 16:24 ` Randy Dunlap 2022-06-02 16:32 ` Christoph Müllner 2022-06-02 16:32 ` Christoph Müllner 2022-06-04 22:20 ` kernel test robot 2022-06-14 15:34 ` Atish Patra 2022-06-14 15:34 ` Atish Patra 2022-06-14 16:29 ` Heiko Stübner 2022-06-14 16:29 ` Heiko Stübner
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