* [Intel-gfx] [PATCH v2 0/5] Add module oriented dmesg output
@ 2022-11-18 1:58 ` John.C.Harrison
0 siblings, 0 replies; 51+ messages in thread
From: John.C.Harrison @ 2022-11-18 1:58 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
When trying to analyse bug reports from CI, customers, etc. it can be
difficult to work out exactly what is happening on which GT in a
multi-GT system. So add GT oriented debug/error message wrappers. If
used instead of the drm_ equivalents, you get the same output but with
a GT# prefix on it.
It was also requested to extend this further to submodules in order to
factor out the repeated structure accessing constructs and common
string prefixes. So, add versions for GuC, HuC and GuC CTB as well.
This patch set updates all the gt/uc files to use the new helpers as a
first step. The intention would be to convert all output messages that
have access to a GT structure.
v2: Go back to using lower case names, add more wrapper sets (combined
review feedback). Also, wrap up probe injection and WARN entries.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
John Harrison (5):
drm/i915/gt: Start adding module oriented dmesg output
drm/i915/huc: Add HuC specific debug print wrappers
drm/i915/guc: Add GuC specific debug print wrappers
drm/i915/guc: Add GuC CT specific debug print wrappers
drm/i915/uc: Update the gt/uc code to use gt_err and friends
drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++++----
drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 +--
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +-
.../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++---------
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 ++---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++--
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 +--
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 ++
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 108 ++++-----
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 98 ++++----
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +--
.../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +-
.../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +-
19 files changed, 507 insertions(+), 475 deletions(-)
--
2.37.3
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v2 1/5] drm/i915/gt: Start adding module oriented dmesg output
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
@ 2022-11-18 1:58 ` John.C.Harrison
-1 siblings, 0 replies; 51+ messages in thread
From: John.C.Harrison @ 2022-11-18 1:58 UTC (permalink / raw)
To: Intel-GFX; +Cc: John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
When trying to analyse bug reports from CI, customers, etc. it can be
difficult to work out exactly what is happening on which GT in a
multi-GT system. So add GT oriented debug/error message wrappers. If
used instead of the drm_ equivalents, you get the same output but with
a GT# prefix on it.
v2: Go back to using lower case names (combined review feedback).
Convert intel_gt.c as a first step.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++++++++++++++----------------
drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++++++++++
2 files changed, 81 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 0325f071046ca..349fcfdd14a6d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -90,9 +90,8 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
if (err == -ENODEV)
return 0;
- drm_err(&i915->drm,
- "Failed to setup region(%d) type=%d\n",
- err, INTEL_MEMORY_LOCAL);
+ gt_err(gt, "Failed to setup region(%d) type=%d\n",
+ err, INTEL_MEMORY_LOCAL);
return err;
}
@@ -192,14 +191,14 @@ int intel_gt_init_hw(struct intel_gt *gt)
ret = i915_ppgtt_init_hw(gt);
if (ret) {
- drm_err(&i915->drm, "Enabling PPGTT failed (%d)\n", ret);
+ gt_err(gt, "Enabling PPGTT failed (%d)\n", ret);
goto out;
}
/* We can't enable contexts until all firmware is loaded */
ret = intel_uc_init_hw(>->uc);
if (ret) {
- i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
+ gt_probe_error(gt, "Enabling uc failed (%d)\n", ret);
goto out;
}
@@ -264,7 +263,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
* some errors might have become stuck,
* mask them.
*/
- drm_dbg(>->i915->drm, "EIR stuck: 0x%08x, masking\n", eir);
+ gt_dbg(gt, "EIR stuck: 0x%08x, masking\n", eir);
rmw_set(uncore, EMR, eir);
intel_uncore_write(uncore, GEN2_IIR,
I915_MASTER_ERROR_INTERRUPT);
@@ -298,16 +297,16 @@ static void gen6_check_faults(struct intel_gt *gt)
for_each_engine(engine, gt, id) {
fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
- drm_dbg(&engine->i915->drm, "Unexpected fault\n"
- "\tAddr: 0x%08lx\n"
- "\tAddress space: %s\n"
- "\tSource ID: %d\n"
- "\tType: %d\n",
- fault & PAGE_MASK,
- fault & RING_FAULT_GTTSEL_MASK ?
- "GGTT" : "PPGTT",
- RING_FAULT_SRCID(fault),
- RING_FAULT_FAULT_TYPE(fault));
+ gt_dbg(gt, "Unexpected fault\n"
+ "\tAddr: 0x%08lx\n"
+ "\tAddress space: %s\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ fault & PAGE_MASK,
+ fault & RING_FAULT_GTTSEL_MASK ?
+ "GGTT" : "PPGTT",
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
}
}
}
@@ -334,17 +333,17 @@ static void xehp_check_faults(struct intel_gt *gt)
fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
((u64)fault_data0 << 12);
- drm_dbg(>->i915->drm, "Unexpected fault\n"
- "\tAddr: 0x%08x_%08x\n"
- "\tAddress space: %s\n"
- "\tEngine ID: %d\n"
- "\tSource ID: %d\n"
- "\tType: %d\n",
- upper_32_bits(fault_addr), lower_32_bits(fault_addr),
- fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
- GEN8_RING_FAULT_ENGINE_ID(fault),
- RING_FAULT_SRCID(fault),
- RING_FAULT_FAULT_TYPE(fault));
+ gt_dbg(gt, "Unexpected fault\n"
+ "\tAddr: 0x%08x_%08x\n"
+ "\tAddress space: %s\n"
+ "\tEngine ID: %d\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ upper_32_bits(fault_addr), lower_32_bits(fault_addr),
+ fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+ GEN8_RING_FAULT_ENGINE_ID(fault),
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
}
}
@@ -375,17 +374,17 @@ static void gen8_check_faults(struct intel_gt *gt)
fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
((u64)fault_data0 << 12);
- drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
- "\tAddr: 0x%08x_%08x\n"
- "\tAddress space: %s\n"
- "\tEngine ID: %d\n"
- "\tSource ID: %d\n"
- "\tType: %d\n",
- upper_32_bits(fault_addr), lower_32_bits(fault_addr),
- fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
- GEN8_RING_FAULT_ENGINE_ID(fault),
- RING_FAULT_SRCID(fault),
- RING_FAULT_FAULT_TYPE(fault));
+ gt_dbg(gt, "Unexpected fault\n"
+ "\tAddr: 0x%08x_%08x\n"
+ "\tAddress space: %s\n"
+ "\tEngine ID: %d\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ upper_32_bits(fault_addr), lower_32_bits(fault_addr),
+ fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+ GEN8_RING_FAULT_ENGINE_ID(fault),
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
}
}
@@ -479,7 +478,7 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
if (IS_ERR(obj))
obj = i915_gem_object_create_internal(i915, size);
if (IS_ERR(obj)) {
- drm_err(&i915->drm, "Failed to allocate scratch page\n");
+ gt_err(gt, "Failed to allocate scratch page\n");
return PTR_ERR(obj);
}
@@ -729,8 +728,7 @@ int intel_gt_init(struct intel_gt *gt)
err = intel_gt_init_hwconfig(gt);
if (err)
- drm_err(>->i915->drm, "Failed to retrieve hwconfig table: %pe\n",
- ERR_PTR(err));
+ gt_err(gt, "Failed to retrieve hwconfig table: %pe\n", ERR_PTR(err));
err = __engines_record_defaults(gt);
if (err)
@@ -891,7 +889,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
gt->name = "Primary GT";
gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
- drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
+ gt_dbg(gt, "Setting up %s\n", gt->name);
ret = intel_gt_tile_setup(gt, phys_addr);
if (ret)
return ret;
@@ -916,7 +914,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
gt->info.engine_mask = gtdef->engine_mask;
gt->info.id = i;
- drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
+ gt_dbg(gt, "Setting up %s\n", gt->name);
if (GEM_WARN_ON(range_overflows_t(resource_size_t,
gtdef->mapping_base,
SZ_16M,
@@ -951,7 +949,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
return 0;
err:
- i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
+ gt_probe_error(gt, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
intel_gt_release_all(i915);
return ret;
@@ -1004,8 +1002,7 @@ get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8,
const unsigned int class = engine->class;
struct reg_and_bit rb = { };
- if (drm_WARN_ON_ONCE(&engine->i915->drm,
- class >= num || !regs[class].reg))
+ if (gt_WARN_ON_ONCE(engine->gt, class >= num || !regs[class].reg))
return rb;
rb.reg = regs[class];
@@ -1088,8 +1085,7 @@ static void mmio_invalidate_full(struct intel_gt *gt)
return;
}
- if (drm_WARN_ONCE(&i915->drm, !num,
- "Platform does not implement TLB invalidation!"))
+ if (gt_WARN_ONCE(gt, !num, "Platform does not implement TLB invalidation!"))
return;
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
@@ -1142,8 +1138,8 @@ static void mmio_invalidate_full(struct intel_gt *gt)
if (wait_for_invalidate(gt, rb))
drm_err_ratelimited(>->i915->drm,
- "%s TLB invalidation did not complete in %ums!\n",
- engine->name, TLB_INVAL_TIMEOUT_MS);
+ "GT%d: %s TLB invalidation did not complete in %ums!\n",
+ gt->info.id, engine->name, TLB_INVAL_TIMEOUT_MS);
}
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index e0365d5562484..5bf2d53f4b4d0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -13,6 +13,41 @@
struct drm_i915_private;
struct drm_printer;
+#define gt_err(_gt, _fmt, ...) \
+ drm_err(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
+#define gt_warn(_gt, _fmt, ...) \
+ drm_warn(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
+#define gt_notice(_gt, _fmt, ...) \
+ drm_notice(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
+#define gt_info(_gt, _fmt, ...) \
+ drm_info(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
+#define gt_dbg(_gt, _fmt, ...) \
+ drm_dbg(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
+#define gt_probe_error(_gt, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ gt_dbg(_gt, _fmt, ##__VA_ARGS__); \
+ else \
+ gt_err(_gt, _fmt, ##__VA_ARGS__); \
+ } while (0)
+
+#define gt_WARN_ON(_gt, _condition) \
+ gt_WARN(_gt, _condition, "%s", "gt_WARN_ON(" __stringify(_condition) ")")
+
+#define gt_WARN_ON_ONCE(_gt, _condition) \
+ gt_WARN_ONCE(_gt, _condition, "%s", "gt_WARN_ONCE(" __stringify(_condition) ")")
+
+#define gt_WARN(_gt, _condition, _fmt, ...) \
+ drm_WARN(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
+#define gt_WARN_ONCE(_gt, _condition, _fmt, ...) \
+ drm_WARN_ONCE(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
#define GT_TRACE(gt, fmt, ...) do { \
const struct intel_gt *gt__ __maybe_unused = (gt); \
GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
--
2.37.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH v2 1/5] drm/i915/gt: Start adding module oriented dmesg output
@ 2022-11-18 1:58 ` John.C.Harrison
0 siblings, 0 replies; 51+ messages in thread
From: John.C.Harrison @ 2022-11-18 1:58 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
When trying to analyse bug reports from CI, customers, etc. it can be
difficult to work out exactly what is happening on which GT in a
multi-GT system. So add GT oriented debug/error message wrappers. If
used instead of the drm_ equivalents, you get the same output but with
a GT# prefix on it.
v2: Go back to using lower case names (combined review feedback).
Convert intel_gt.c as a first step.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++++++++++++++----------------
drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++++++++++
2 files changed, 81 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 0325f071046ca..349fcfdd14a6d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -90,9 +90,8 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
if (err == -ENODEV)
return 0;
- drm_err(&i915->drm,
- "Failed to setup region(%d) type=%d\n",
- err, INTEL_MEMORY_LOCAL);
+ gt_err(gt, "Failed to setup region(%d) type=%d\n",
+ err, INTEL_MEMORY_LOCAL);
return err;
}
@@ -192,14 +191,14 @@ int intel_gt_init_hw(struct intel_gt *gt)
ret = i915_ppgtt_init_hw(gt);
if (ret) {
- drm_err(&i915->drm, "Enabling PPGTT failed (%d)\n", ret);
+ gt_err(gt, "Enabling PPGTT failed (%d)\n", ret);
goto out;
}
/* We can't enable contexts until all firmware is loaded */
ret = intel_uc_init_hw(>->uc);
if (ret) {
- i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
+ gt_probe_error(gt, "Enabling uc failed (%d)\n", ret);
goto out;
}
@@ -264,7 +263,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
* some errors might have become stuck,
* mask them.
*/
- drm_dbg(>->i915->drm, "EIR stuck: 0x%08x, masking\n", eir);
+ gt_dbg(gt, "EIR stuck: 0x%08x, masking\n", eir);
rmw_set(uncore, EMR, eir);
intel_uncore_write(uncore, GEN2_IIR,
I915_MASTER_ERROR_INTERRUPT);
@@ -298,16 +297,16 @@ static void gen6_check_faults(struct intel_gt *gt)
for_each_engine(engine, gt, id) {
fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
- drm_dbg(&engine->i915->drm, "Unexpected fault\n"
- "\tAddr: 0x%08lx\n"
- "\tAddress space: %s\n"
- "\tSource ID: %d\n"
- "\tType: %d\n",
- fault & PAGE_MASK,
- fault & RING_FAULT_GTTSEL_MASK ?
- "GGTT" : "PPGTT",
- RING_FAULT_SRCID(fault),
- RING_FAULT_FAULT_TYPE(fault));
+ gt_dbg(gt, "Unexpected fault\n"
+ "\tAddr: 0x%08lx\n"
+ "\tAddress space: %s\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ fault & PAGE_MASK,
+ fault & RING_FAULT_GTTSEL_MASK ?
+ "GGTT" : "PPGTT",
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
}
}
}
@@ -334,17 +333,17 @@ static void xehp_check_faults(struct intel_gt *gt)
fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
((u64)fault_data0 << 12);
- drm_dbg(>->i915->drm, "Unexpected fault\n"
- "\tAddr: 0x%08x_%08x\n"
- "\tAddress space: %s\n"
- "\tEngine ID: %d\n"
- "\tSource ID: %d\n"
- "\tType: %d\n",
- upper_32_bits(fault_addr), lower_32_bits(fault_addr),
- fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
- GEN8_RING_FAULT_ENGINE_ID(fault),
- RING_FAULT_SRCID(fault),
- RING_FAULT_FAULT_TYPE(fault));
+ gt_dbg(gt, "Unexpected fault\n"
+ "\tAddr: 0x%08x_%08x\n"
+ "\tAddress space: %s\n"
+ "\tEngine ID: %d\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ upper_32_bits(fault_addr), lower_32_bits(fault_addr),
+ fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+ GEN8_RING_FAULT_ENGINE_ID(fault),
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
}
}
@@ -375,17 +374,17 @@ static void gen8_check_faults(struct intel_gt *gt)
fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
((u64)fault_data0 << 12);
- drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
- "\tAddr: 0x%08x_%08x\n"
- "\tAddress space: %s\n"
- "\tEngine ID: %d\n"
- "\tSource ID: %d\n"
- "\tType: %d\n",
- upper_32_bits(fault_addr), lower_32_bits(fault_addr),
- fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
- GEN8_RING_FAULT_ENGINE_ID(fault),
- RING_FAULT_SRCID(fault),
- RING_FAULT_FAULT_TYPE(fault));
+ gt_dbg(gt, "Unexpected fault\n"
+ "\tAddr: 0x%08x_%08x\n"
+ "\tAddress space: %s\n"
+ "\tEngine ID: %d\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ upper_32_bits(fault_addr), lower_32_bits(fault_addr),
+ fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+ GEN8_RING_FAULT_ENGINE_ID(fault),
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
}
}
@@ -479,7 +478,7 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
if (IS_ERR(obj))
obj = i915_gem_object_create_internal(i915, size);
if (IS_ERR(obj)) {
- drm_err(&i915->drm, "Failed to allocate scratch page\n");
+ gt_err(gt, "Failed to allocate scratch page\n");
return PTR_ERR(obj);
}
@@ -729,8 +728,7 @@ int intel_gt_init(struct intel_gt *gt)
err = intel_gt_init_hwconfig(gt);
if (err)
- drm_err(>->i915->drm, "Failed to retrieve hwconfig table: %pe\n",
- ERR_PTR(err));
+ gt_err(gt, "Failed to retrieve hwconfig table: %pe\n", ERR_PTR(err));
err = __engines_record_defaults(gt);
if (err)
@@ -891,7 +889,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
gt->name = "Primary GT";
gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
- drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
+ gt_dbg(gt, "Setting up %s\n", gt->name);
ret = intel_gt_tile_setup(gt, phys_addr);
if (ret)
return ret;
@@ -916,7 +914,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
gt->info.engine_mask = gtdef->engine_mask;
gt->info.id = i;
- drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
+ gt_dbg(gt, "Setting up %s\n", gt->name);
if (GEM_WARN_ON(range_overflows_t(resource_size_t,
gtdef->mapping_base,
SZ_16M,
@@ -951,7 +949,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
return 0;
err:
- i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
+ gt_probe_error(gt, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
intel_gt_release_all(i915);
return ret;
@@ -1004,8 +1002,7 @@ get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8,
const unsigned int class = engine->class;
struct reg_and_bit rb = { };
- if (drm_WARN_ON_ONCE(&engine->i915->drm,
- class >= num || !regs[class].reg))
+ if (gt_WARN_ON_ONCE(engine->gt, class >= num || !regs[class].reg))
return rb;
rb.reg = regs[class];
@@ -1088,8 +1085,7 @@ static void mmio_invalidate_full(struct intel_gt *gt)
return;
}
- if (drm_WARN_ONCE(&i915->drm, !num,
- "Platform does not implement TLB invalidation!"))
+ if (gt_WARN_ONCE(gt, !num, "Platform does not implement TLB invalidation!"))
return;
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
@@ -1142,8 +1138,8 @@ static void mmio_invalidate_full(struct intel_gt *gt)
if (wait_for_invalidate(gt, rb))
drm_err_ratelimited(>->i915->drm,
- "%s TLB invalidation did not complete in %ums!\n",
- engine->name, TLB_INVAL_TIMEOUT_MS);
+ "GT%d: %s TLB invalidation did not complete in %ums!\n",
+ gt->info.id, engine->name, TLB_INVAL_TIMEOUT_MS);
}
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index e0365d5562484..5bf2d53f4b4d0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -13,6 +13,41 @@
struct drm_i915_private;
struct drm_printer;
+#define gt_err(_gt, _fmt, ...) \
+ drm_err(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
+#define gt_warn(_gt, _fmt, ...) \
+ drm_warn(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
+#define gt_notice(_gt, _fmt, ...) \
+ drm_notice(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
+#define gt_info(_gt, _fmt, ...) \
+ drm_info(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
+#define gt_dbg(_gt, _fmt, ...) \
+ drm_dbg(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
+#define gt_probe_error(_gt, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ gt_dbg(_gt, _fmt, ##__VA_ARGS__); \
+ else \
+ gt_err(_gt, _fmt, ##__VA_ARGS__); \
+ } while (0)
+
+#define gt_WARN_ON(_gt, _condition) \
+ gt_WARN(_gt, _condition, "%s", "gt_WARN_ON(" __stringify(_condition) ")")
+
+#define gt_WARN_ON_ONCE(_gt, _condition) \
+ gt_WARN_ONCE(_gt, _condition, "%s", "gt_WARN_ONCE(" __stringify(_condition) ")")
+
+#define gt_WARN(_gt, _condition, _fmt, ...) \
+ drm_WARN(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
+#define gt_WARN_ONCE(_gt, _condition, _fmt, ...) \
+ drm_WARN_ONCE(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
#define GT_TRACE(gt, fmt, ...) do { \
const struct intel_gt *gt__ __maybe_unused = (gt); \
GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
--
2.37.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v2 1/5] drm/i915/gt: Start adding module oriented dmesg output
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
@ 2022-11-22 16:47 ` Michal Wajdeczko
-1 siblings, 0 replies; 51+ messages in thread
From: Michal Wajdeczko @ 2022-11-22 16:47 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> When trying to analyse bug reports from CI, customers, etc. it can be
> difficult to work out exactly what is happening on which GT in a
> multi-GT system. So add GT oriented debug/error message wrappers. If
> used instead of the drm_ equivalents, you get the same output but with
> a GT# prefix on it.
>
> v2: Go back to using lower case names (combined review feedback).
> Convert intel_gt.c as a first step.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++++++++++++++----------------
> drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++++++++++
> 2 files changed, 81 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 0325f071046ca..349fcfdd14a6d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -90,9 +90,8 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
> if (err == -ENODEV)
> return 0;
>
> - drm_err(&i915->drm,
> - "Failed to setup region(%d) type=%d\n",
> - err, INTEL_MEMORY_LOCAL);
> + gt_err(gt, "Failed to setup region(%d) type=%d\n",
> + err, INTEL_MEMORY_LOCAL);
> return err;
> }
>
> @@ -192,14 +191,14 @@ int intel_gt_init_hw(struct intel_gt *gt)
>
> ret = i915_ppgtt_init_hw(gt);
> if (ret) {
> - drm_err(&i915->drm, "Enabling PPGTT failed (%d)\n", ret);
> + gt_err(gt, "Enabling PPGTT failed (%d)\n", ret);
> goto out;
> }
>
> /* We can't enable contexts until all firmware is loaded */
> ret = intel_uc_init_hw(>->uc);
> if (ret) {
> - i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
> + gt_probe_error(gt, "Enabling uc failed (%d)\n", ret);
> goto out;
> }
>
> @@ -264,7 +263,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> * some errors might have become stuck,
> * mask them.
> */
> - drm_dbg(>->i915->drm, "EIR stuck: 0x%08x, masking\n", eir);
> + gt_dbg(gt, "EIR stuck: 0x%08x, masking\n", eir);
> rmw_set(uncore, EMR, eir);
> intel_uncore_write(uncore, GEN2_IIR,
> I915_MASTER_ERROR_INTERRUPT);
> @@ -298,16 +297,16 @@ static void gen6_check_faults(struct intel_gt *gt)
> for_each_engine(engine, gt, id) {
> fault = GEN6_RING_FAULT_REG_READ(engine);
> if (fault & RING_FAULT_VALID) {
> - drm_dbg(&engine->i915->drm, "Unexpected fault\n"
> - "\tAddr: 0x%08lx\n"
> - "\tAddress space: %s\n"
> - "\tSource ID: %d\n"
> - "\tType: %d\n",
> - fault & PAGE_MASK,
> - fault & RING_FAULT_GTTSEL_MASK ?
> - "GGTT" : "PPGTT",
> - RING_FAULT_SRCID(fault),
> - RING_FAULT_FAULT_TYPE(fault));
> + gt_dbg(gt, "Unexpected fault\n"
> + "\tAddr: 0x%08lx\n"
> + "\tAddress space: %s\n"
> + "\tSource ID: %d\n"
> + "\tType: %d\n",
> + fault & PAGE_MASK,
> + fault & RING_FAULT_GTTSEL_MASK ?
> + "GGTT" : "PPGTT",
> + RING_FAULT_SRCID(fault),
> + RING_FAULT_FAULT_TYPE(fault));
> }
> }
> }
> @@ -334,17 +333,17 @@ static void xehp_check_faults(struct intel_gt *gt)
> fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
> ((u64)fault_data0 << 12);
>
> - drm_dbg(>->i915->drm, "Unexpected fault\n"
> - "\tAddr: 0x%08x_%08x\n"
> - "\tAddress space: %s\n"
> - "\tEngine ID: %d\n"
> - "\tSource ID: %d\n"
> - "\tType: %d\n",
> - upper_32_bits(fault_addr), lower_32_bits(fault_addr),
> - fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
> - GEN8_RING_FAULT_ENGINE_ID(fault),
> - RING_FAULT_SRCID(fault),
> - RING_FAULT_FAULT_TYPE(fault));
> + gt_dbg(gt, "Unexpected fault\n"
> + "\tAddr: 0x%08x_%08x\n"
> + "\tAddress space: %s\n"
> + "\tEngine ID: %d\n"
> + "\tSource ID: %d\n"
> + "\tType: %d\n",
> + upper_32_bits(fault_addr), lower_32_bits(fault_addr),
> + fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
> + GEN8_RING_FAULT_ENGINE_ID(fault),
> + RING_FAULT_SRCID(fault),
> + RING_FAULT_FAULT_TYPE(fault));
> }
> }
>
> @@ -375,17 +374,17 @@ static void gen8_check_faults(struct intel_gt *gt)
> fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
> ((u64)fault_data0 << 12);
>
> - drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
> - "\tAddr: 0x%08x_%08x\n"
> - "\tAddress space: %s\n"
> - "\tEngine ID: %d\n"
> - "\tSource ID: %d\n"
> - "\tType: %d\n",
> - upper_32_bits(fault_addr), lower_32_bits(fault_addr),
> - fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
> - GEN8_RING_FAULT_ENGINE_ID(fault),
> - RING_FAULT_SRCID(fault),
> - RING_FAULT_FAULT_TYPE(fault));
> + gt_dbg(gt, "Unexpected fault\n"
> + "\tAddr: 0x%08x_%08x\n"
> + "\tAddress space: %s\n"
> + "\tEngine ID: %d\n"
> + "\tSource ID: %d\n"
> + "\tType: %d\n",
> + upper_32_bits(fault_addr), lower_32_bits(fault_addr),
> + fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
> + GEN8_RING_FAULT_ENGINE_ID(fault),
> + RING_FAULT_SRCID(fault),
> + RING_FAULT_FAULT_TYPE(fault));
> }
> }
>
> @@ -479,7 +478,7 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
> if (IS_ERR(obj))
> obj = i915_gem_object_create_internal(i915, size);
> if (IS_ERR(obj)) {
> - drm_err(&i915->drm, "Failed to allocate scratch page\n");
> + gt_err(gt, "Failed to allocate scratch page\n");
> return PTR_ERR(obj);
> }
>
> @@ -729,8 +728,7 @@ int intel_gt_init(struct intel_gt *gt)
>
> err = intel_gt_init_hwconfig(gt);
> if (err)
> - drm_err(>->i915->drm, "Failed to retrieve hwconfig table: %pe\n",
> - ERR_PTR(err));
> + gt_err(gt, "Failed to retrieve hwconfig table: %pe\n", ERR_PTR(err));
>
> err = __engines_record_defaults(gt);
> if (err)
> @@ -891,7 +889,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> gt->name = "Primary GT";
> gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
>
> - drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
> + gt_dbg(gt, "Setting up %s\n", gt->name);
> ret = intel_gt_tile_setup(gt, phys_addr);
> if (ret)
> return ret;
> @@ -916,7 +914,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> gt->info.engine_mask = gtdef->engine_mask;
> gt->info.id = i;
>
> - drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
> + gt_dbg(gt, "Setting up %s\n", gt->name);
> if (GEM_WARN_ON(range_overflows_t(resource_size_t,
> gtdef->mapping_base,
> SZ_16M,
> @@ -951,7 +949,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> return 0;
>
> err:
> - i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
> + gt_probe_error(gt, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
on -ENOMEM error, this gt will be NULL
so likely we should stay with i915 variant
> intel_gt_release_all(i915);
>
> return ret;
> @@ -1004,8 +1002,7 @@ get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8,
> const unsigned int class = engine->class;
> struct reg_and_bit rb = { };
>
> - if (drm_WARN_ON_ONCE(&engine->i915->drm,
> - class >= num || !regs[class].reg))
> + if (gt_WARN_ON_ONCE(engine->gt, class >= num || !regs[class].reg))
> return rb;
>
> rb.reg = regs[class];
> @@ -1088,8 +1085,7 @@ static void mmio_invalidate_full(struct intel_gt *gt)
> return;
> }
>
> - if (drm_WARN_ONCE(&i915->drm, !num,
> - "Platform does not implement TLB invalidation!"))
> + if (gt_WARN_ONCE(gt, !num, "Platform does not implement TLB invalidation!"))
> return;
>
> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> @@ -1142,8 +1138,8 @@ static void mmio_invalidate_full(struct intel_gt *gt)
>
> if (wait_for_invalidate(gt, rb))
> drm_err_ratelimited(>->i915->drm,
> - "%s TLB invalidation did not complete in %ums!\n",
> - engine->name, TLB_INVAL_TIMEOUT_MS);
> + "GT%d: %s TLB invalidation did not complete in %ums!\n",
> + gt->info.id, engine->name, TLB_INVAL_TIMEOUT_MS);
that's inconsistent, we should use gt_err_ratelimited()
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index e0365d5562484..5bf2d53f4b4d0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -13,6 +13,41 @@
> struct drm_i915_private;
> struct drm_printer;
>
> +#define gt_err(_gt, _fmt, ...) \
> + drm_err(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> +#define gt_warn(_gt, _fmt, ...) \
> + drm_warn(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> +#define gt_notice(_gt, _fmt, ...) \
> + drm_notice(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> +#define gt_info(_gt, _fmt, ...) \
> + drm_info(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> +#define gt_dbg(_gt, _fmt, ...) \
> + drm_dbg(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> +#define gt_probe_error(_gt, _fmt, ...) \
> + do { \
> + if (i915_error_injected()) \
> + gt_dbg(_gt, _fmt, ##__VA_ARGS__); \
> + else \
> + gt_err(_gt, _fmt, ##__VA_ARGS__); \
> + } while (0)
> +
> +#define gt_WARN_ON(_gt, _condition) \
> + gt_WARN(_gt, _condition, "%s", "gt_WARN_ON(" __stringify(_condition) ")")
> +
> +#define gt_WARN_ON_ONCE(_gt, _condition) \
> + gt_WARN_ONCE(_gt, _condition, "%s", "gt_WARN_ONCE(" __stringify(_condition) ")")
> +
> +#define gt_WARN(_gt, _condition, _fmt, ...) \
> + drm_WARN(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> +#define gt_WARN_ONCE(_gt, _condition, _fmt, ...) \
> + drm_WARN_ONCE(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> #define GT_TRACE(gt, fmt, ...) do { \
> const struct intel_gt *gt__ __maybe_unused = (gt); \
> GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
btw, shouldn't we also update GT_TRACE macros to include GT.id ?
(naturally not in this series)
Michal
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH v2 1/5] drm/i915/gt: Start adding module oriented dmesg output
@ 2022-11-22 16:47 ` Michal Wajdeczko
0 siblings, 0 replies; 51+ messages in thread
From: Michal Wajdeczko @ 2022-11-22 16:47 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> When trying to analyse bug reports from CI, customers, etc. it can be
> difficult to work out exactly what is happening on which GT in a
> multi-GT system. So add GT oriented debug/error message wrappers. If
> used instead of the drm_ equivalents, you get the same output but with
> a GT# prefix on it.
>
> v2: Go back to using lower case names (combined review feedback).
> Convert intel_gt.c as a first step.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++++++++++++++----------------
> drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++++++++++
> 2 files changed, 81 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 0325f071046ca..349fcfdd14a6d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -90,9 +90,8 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
> if (err == -ENODEV)
> return 0;
>
> - drm_err(&i915->drm,
> - "Failed to setup region(%d) type=%d\n",
> - err, INTEL_MEMORY_LOCAL);
> + gt_err(gt, "Failed to setup region(%d) type=%d\n",
> + err, INTEL_MEMORY_LOCAL);
> return err;
> }
>
> @@ -192,14 +191,14 @@ int intel_gt_init_hw(struct intel_gt *gt)
>
> ret = i915_ppgtt_init_hw(gt);
> if (ret) {
> - drm_err(&i915->drm, "Enabling PPGTT failed (%d)\n", ret);
> + gt_err(gt, "Enabling PPGTT failed (%d)\n", ret);
> goto out;
> }
>
> /* We can't enable contexts until all firmware is loaded */
> ret = intel_uc_init_hw(>->uc);
> if (ret) {
> - i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
> + gt_probe_error(gt, "Enabling uc failed (%d)\n", ret);
> goto out;
> }
>
> @@ -264,7 +263,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> * some errors might have become stuck,
> * mask them.
> */
> - drm_dbg(>->i915->drm, "EIR stuck: 0x%08x, masking\n", eir);
> + gt_dbg(gt, "EIR stuck: 0x%08x, masking\n", eir);
> rmw_set(uncore, EMR, eir);
> intel_uncore_write(uncore, GEN2_IIR,
> I915_MASTER_ERROR_INTERRUPT);
> @@ -298,16 +297,16 @@ static void gen6_check_faults(struct intel_gt *gt)
> for_each_engine(engine, gt, id) {
> fault = GEN6_RING_FAULT_REG_READ(engine);
> if (fault & RING_FAULT_VALID) {
> - drm_dbg(&engine->i915->drm, "Unexpected fault\n"
> - "\tAddr: 0x%08lx\n"
> - "\tAddress space: %s\n"
> - "\tSource ID: %d\n"
> - "\tType: %d\n",
> - fault & PAGE_MASK,
> - fault & RING_FAULT_GTTSEL_MASK ?
> - "GGTT" : "PPGTT",
> - RING_FAULT_SRCID(fault),
> - RING_FAULT_FAULT_TYPE(fault));
> + gt_dbg(gt, "Unexpected fault\n"
> + "\tAddr: 0x%08lx\n"
> + "\tAddress space: %s\n"
> + "\tSource ID: %d\n"
> + "\tType: %d\n",
> + fault & PAGE_MASK,
> + fault & RING_FAULT_GTTSEL_MASK ?
> + "GGTT" : "PPGTT",
> + RING_FAULT_SRCID(fault),
> + RING_FAULT_FAULT_TYPE(fault));
> }
> }
> }
> @@ -334,17 +333,17 @@ static void xehp_check_faults(struct intel_gt *gt)
> fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
> ((u64)fault_data0 << 12);
>
> - drm_dbg(>->i915->drm, "Unexpected fault\n"
> - "\tAddr: 0x%08x_%08x\n"
> - "\tAddress space: %s\n"
> - "\tEngine ID: %d\n"
> - "\tSource ID: %d\n"
> - "\tType: %d\n",
> - upper_32_bits(fault_addr), lower_32_bits(fault_addr),
> - fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
> - GEN8_RING_FAULT_ENGINE_ID(fault),
> - RING_FAULT_SRCID(fault),
> - RING_FAULT_FAULT_TYPE(fault));
> + gt_dbg(gt, "Unexpected fault\n"
> + "\tAddr: 0x%08x_%08x\n"
> + "\tAddress space: %s\n"
> + "\tEngine ID: %d\n"
> + "\tSource ID: %d\n"
> + "\tType: %d\n",
> + upper_32_bits(fault_addr), lower_32_bits(fault_addr),
> + fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
> + GEN8_RING_FAULT_ENGINE_ID(fault),
> + RING_FAULT_SRCID(fault),
> + RING_FAULT_FAULT_TYPE(fault));
> }
> }
>
> @@ -375,17 +374,17 @@ static void gen8_check_faults(struct intel_gt *gt)
> fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
> ((u64)fault_data0 << 12);
>
> - drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
> - "\tAddr: 0x%08x_%08x\n"
> - "\tAddress space: %s\n"
> - "\tEngine ID: %d\n"
> - "\tSource ID: %d\n"
> - "\tType: %d\n",
> - upper_32_bits(fault_addr), lower_32_bits(fault_addr),
> - fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
> - GEN8_RING_FAULT_ENGINE_ID(fault),
> - RING_FAULT_SRCID(fault),
> - RING_FAULT_FAULT_TYPE(fault));
> + gt_dbg(gt, "Unexpected fault\n"
> + "\tAddr: 0x%08x_%08x\n"
> + "\tAddress space: %s\n"
> + "\tEngine ID: %d\n"
> + "\tSource ID: %d\n"
> + "\tType: %d\n",
> + upper_32_bits(fault_addr), lower_32_bits(fault_addr),
> + fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
> + GEN8_RING_FAULT_ENGINE_ID(fault),
> + RING_FAULT_SRCID(fault),
> + RING_FAULT_FAULT_TYPE(fault));
> }
> }
>
> @@ -479,7 +478,7 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
> if (IS_ERR(obj))
> obj = i915_gem_object_create_internal(i915, size);
> if (IS_ERR(obj)) {
> - drm_err(&i915->drm, "Failed to allocate scratch page\n");
> + gt_err(gt, "Failed to allocate scratch page\n");
> return PTR_ERR(obj);
> }
>
> @@ -729,8 +728,7 @@ int intel_gt_init(struct intel_gt *gt)
>
> err = intel_gt_init_hwconfig(gt);
> if (err)
> - drm_err(>->i915->drm, "Failed to retrieve hwconfig table: %pe\n",
> - ERR_PTR(err));
> + gt_err(gt, "Failed to retrieve hwconfig table: %pe\n", ERR_PTR(err));
>
> err = __engines_record_defaults(gt);
> if (err)
> @@ -891,7 +889,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> gt->name = "Primary GT";
> gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
>
> - drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
> + gt_dbg(gt, "Setting up %s\n", gt->name);
> ret = intel_gt_tile_setup(gt, phys_addr);
> if (ret)
> return ret;
> @@ -916,7 +914,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> gt->info.engine_mask = gtdef->engine_mask;
> gt->info.id = i;
>
> - drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
> + gt_dbg(gt, "Setting up %s\n", gt->name);
> if (GEM_WARN_ON(range_overflows_t(resource_size_t,
> gtdef->mapping_base,
> SZ_16M,
> @@ -951,7 +949,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> return 0;
>
> err:
> - i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
> + gt_probe_error(gt, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
on -ENOMEM error, this gt will be NULL
so likely we should stay with i915 variant
> intel_gt_release_all(i915);
>
> return ret;
> @@ -1004,8 +1002,7 @@ get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8,
> const unsigned int class = engine->class;
> struct reg_and_bit rb = { };
>
> - if (drm_WARN_ON_ONCE(&engine->i915->drm,
> - class >= num || !regs[class].reg))
> + if (gt_WARN_ON_ONCE(engine->gt, class >= num || !regs[class].reg))
> return rb;
>
> rb.reg = regs[class];
> @@ -1088,8 +1085,7 @@ static void mmio_invalidate_full(struct intel_gt *gt)
> return;
> }
>
> - if (drm_WARN_ONCE(&i915->drm, !num,
> - "Platform does not implement TLB invalidation!"))
> + if (gt_WARN_ONCE(gt, !num, "Platform does not implement TLB invalidation!"))
> return;
>
> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> @@ -1142,8 +1138,8 @@ static void mmio_invalidate_full(struct intel_gt *gt)
>
> if (wait_for_invalidate(gt, rb))
> drm_err_ratelimited(>->i915->drm,
> - "%s TLB invalidation did not complete in %ums!\n",
> - engine->name, TLB_INVAL_TIMEOUT_MS);
> + "GT%d: %s TLB invalidation did not complete in %ums!\n",
> + gt->info.id, engine->name, TLB_INVAL_TIMEOUT_MS);
that's inconsistent, we should use gt_err_ratelimited()
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index e0365d5562484..5bf2d53f4b4d0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -13,6 +13,41 @@
> struct drm_i915_private;
> struct drm_printer;
>
> +#define gt_err(_gt, _fmt, ...) \
> + drm_err(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> +#define gt_warn(_gt, _fmt, ...) \
> + drm_warn(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> +#define gt_notice(_gt, _fmt, ...) \
> + drm_notice(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> +#define gt_info(_gt, _fmt, ...) \
> + drm_info(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> +#define gt_dbg(_gt, _fmt, ...) \
> + drm_dbg(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> +#define gt_probe_error(_gt, _fmt, ...) \
> + do { \
> + if (i915_error_injected()) \
> + gt_dbg(_gt, _fmt, ##__VA_ARGS__); \
> + else \
> + gt_err(_gt, _fmt, ##__VA_ARGS__); \
> + } while (0)
> +
> +#define gt_WARN_ON(_gt, _condition) \
> + gt_WARN(_gt, _condition, "%s", "gt_WARN_ON(" __stringify(_condition) ")")
> +
> +#define gt_WARN_ON_ONCE(_gt, _condition) \
> + gt_WARN_ONCE(_gt, _condition, "%s", "gt_WARN_ONCE(" __stringify(_condition) ")")
> +
> +#define gt_WARN(_gt, _condition, _fmt, ...) \
> + drm_WARN(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> +#define gt_WARN_ONCE(_gt, _condition, _fmt, ...) \
> + drm_WARN_ONCE(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
> #define GT_TRACE(gt, fmt, ...) do { \
> const struct intel_gt *gt__ __maybe_unused = (gt); \
> GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
btw, shouldn't we also update GT_TRACE macros to include GT.id ?
(naturally not in this series)
Michal
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v2 2/5] drm/i915/huc: Add HuC specific debug print wrappers
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
@ 2022-11-18 1:58 ` John.C.Harrison
-1 siblings, 0 replies; 51+ messages in thread
From: John.C.Harrison @ 2022-11-18 1:58 UTC (permalink / raw)
To: Intel-GFX; +Cc: John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
Create a set of HuC printers and start using them.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 ++++++++++----------------
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 +++++++++++++++++++
2 files changed, 35 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index be855811d85df..0bbbc7192da63 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -107,11 +107,9 @@ static enum hrtimer_restart huc_delayed_load_timer_callback(struct hrtimer *hrti
if (!intel_huc_is_authenticated(huc)) {
if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
- drm_notice(&huc_to_gt(huc)->i915->drm,
- "timed out waiting for MEI GSC init to load HuC\n");
+ huc_notice(huc, "Timed out waiting for MEI GSC init to load FW\n");
else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
- drm_notice(&huc_to_gt(huc)->i915->drm,
- "timed out waiting for MEI PXP init to load HuC\n");
+ huc_notice(huc, "Timed out waiting for MEI PXP init to load FW\n");
else
MISSING_CASE(huc->delayed_load.status);
@@ -174,8 +172,7 @@ static int gsc_notifier(struct notifier_block *nb, unsigned long action, void *d
case BUS_NOTIFY_DRIVER_NOT_BOUND: /* mei driver fails to be bound */
case BUS_NOTIFY_UNBIND_DRIVER: /* mei driver about to be unbound */
- drm_info(&huc_to_gt(huc)->i915->drm,
- "mei driver not bound, disabling HuC load\n");
+ huc_info(huc, "- mei driver not bound, disabling HuC load\n");
gsc_init_error(huc);
break;
}
@@ -193,8 +190,7 @@ void intel_huc_register_gsc_notifier(struct intel_huc *huc, struct bus_type *bus
huc->delayed_load.nb.notifier_call = gsc_notifier;
ret = bus_register_notifier(bus, &huc->delayed_load.nb);
if (ret) {
- drm_err(&huc_to_gt(huc)->i915->drm,
- "failed to register GSC notifier\n");
+ huc_err(huc, "Failed to register GSC notifier\n");
huc->delayed_load.nb.notifier_call = NULL;
gsc_init_error(huc);
}
@@ -284,8 +280,7 @@ static int check_huc_loading_mode(struct intel_huc *huc)
GSC_LOADS_HUC;
if (fw_needs_gsc != hw_uses_gsc) {
- drm_err(>->i915->drm,
- "mismatch between HuC FW (%s) and HW (%s) load modes\n",
+ huc_err(huc, "Mismatch between FW (%s) and HW (%s) load modes\n",
HUC_LOAD_MODE_STRING(fw_needs_gsc),
HUC_LOAD_MODE_STRING(hw_uses_gsc));
return -ENOEXEC;
@@ -294,19 +289,17 @@ static int check_huc_loading_mode(struct intel_huc *huc)
/* make sure we can access the GSC via the mei driver if we need it */
if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) && IS_ENABLED(CONFIG_INTEL_MEI_GSC)) &&
fw_needs_gsc) {
- drm_info(>->i915->drm,
- "Can't load HuC due to missing MEI modules\n");
+ huc_info(huc, "Can't load due to missing MEI modules\n");
return -EIO;
}
- drm_dbg(>->i915->drm, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
+ huc_dbg(huc, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
return 0;
}
int intel_huc_init(struct intel_huc *huc)
{
- struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
int err;
err = check_huc_loading_mode(huc);
@@ -323,7 +316,7 @@ int intel_huc_init(struct intel_huc *huc)
out:
intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
- drm_info(&i915->drm, "HuC init failed with %d\n", err);
+ huc_info(huc, "init failed with %d\n", err);
return err;
}
@@ -366,13 +359,13 @@ int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
delayed_huc_load_complete(huc);
if (ret) {
- drm_err(>->i915->drm, "HuC: Firmware not verified %d\n", ret);
+ huc_err(huc, "firmware not verified %d\n", ret);
intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
return ret;
}
intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
- drm_info(>->i915->drm, "HuC authenticated\n");
+ huc_info(huc, "authenticated\n");
return 0;
}
@@ -407,7 +400,7 @@ int intel_huc_auth(struct intel_huc *huc)
ret = intel_guc_auth_huc(guc, intel_guc_ggtt_offset(guc, huc->fw.rsa_data));
if (ret) {
- DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
+ huc_err(huc, "auth request not acked by GuC: %d\n", ret);
goto fail;
}
@@ -419,7 +412,7 @@ int intel_huc_auth(struct intel_huc *huc)
return 0;
fail:
- i915_probe_error(gt->i915, "HuC: Authentication failed %d\n", ret);
+ huc_probe_error(huc, "authentication failed %d\n", ret);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 52db03620c609..f253c1c19f12f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -16,6 +16,29 @@
struct bus_type;
+#define huc_err(_huc, _fmt, ...) \
+ gt_err(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
+
+#define huc_warn(_huc, _fmt, ...) \
+ gt_warn(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
+
+#define huc_notice(_huc, _fmt, ...) \
+ gt_notice(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
+
+#define huc_info(_huc, _fmt, ...) \
+ gt_info(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
+
+#define huc_dbg(_huc, _fmt, ...) \
+ gt_dbg(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
+
+#define huc_probe_error(_huc, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ huc_dbg(_huc, _fmt, ##__VA_ARGS__); \
+ else \
+ huc_err(_huc, _fmt, ##__VA_ARGS__); \
+ } while (0)
+
enum intel_huc_delayed_load_status {
INTEL_HUC_WAITING_ON_GSC = 0,
INTEL_HUC_WAITING_ON_PXP,
--
2.37.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH v2 2/5] drm/i915/huc: Add HuC specific debug print wrappers
@ 2022-11-18 1:58 ` John.C.Harrison
0 siblings, 0 replies; 51+ messages in thread
From: John.C.Harrison @ 2022-11-18 1:58 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
Create a set of HuC printers and start using them.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 ++++++++++----------------
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 +++++++++++++++++++
2 files changed, 35 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index be855811d85df..0bbbc7192da63 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -107,11 +107,9 @@ static enum hrtimer_restart huc_delayed_load_timer_callback(struct hrtimer *hrti
if (!intel_huc_is_authenticated(huc)) {
if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
- drm_notice(&huc_to_gt(huc)->i915->drm,
- "timed out waiting for MEI GSC init to load HuC\n");
+ huc_notice(huc, "Timed out waiting for MEI GSC init to load FW\n");
else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
- drm_notice(&huc_to_gt(huc)->i915->drm,
- "timed out waiting for MEI PXP init to load HuC\n");
+ huc_notice(huc, "Timed out waiting for MEI PXP init to load FW\n");
else
MISSING_CASE(huc->delayed_load.status);
@@ -174,8 +172,7 @@ static int gsc_notifier(struct notifier_block *nb, unsigned long action, void *d
case BUS_NOTIFY_DRIVER_NOT_BOUND: /* mei driver fails to be bound */
case BUS_NOTIFY_UNBIND_DRIVER: /* mei driver about to be unbound */
- drm_info(&huc_to_gt(huc)->i915->drm,
- "mei driver not bound, disabling HuC load\n");
+ huc_info(huc, "- mei driver not bound, disabling HuC load\n");
gsc_init_error(huc);
break;
}
@@ -193,8 +190,7 @@ void intel_huc_register_gsc_notifier(struct intel_huc *huc, struct bus_type *bus
huc->delayed_load.nb.notifier_call = gsc_notifier;
ret = bus_register_notifier(bus, &huc->delayed_load.nb);
if (ret) {
- drm_err(&huc_to_gt(huc)->i915->drm,
- "failed to register GSC notifier\n");
+ huc_err(huc, "Failed to register GSC notifier\n");
huc->delayed_load.nb.notifier_call = NULL;
gsc_init_error(huc);
}
@@ -284,8 +280,7 @@ static int check_huc_loading_mode(struct intel_huc *huc)
GSC_LOADS_HUC;
if (fw_needs_gsc != hw_uses_gsc) {
- drm_err(>->i915->drm,
- "mismatch between HuC FW (%s) and HW (%s) load modes\n",
+ huc_err(huc, "Mismatch between FW (%s) and HW (%s) load modes\n",
HUC_LOAD_MODE_STRING(fw_needs_gsc),
HUC_LOAD_MODE_STRING(hw_uses_gsc));
return -ENOEXEC;
@@ -294,19 +289,17 @@ static int check_huc_loading_mode(struct intel_huc *huc)
/* make sure we can access the GSC via the mei driver if we need it */
if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) && IS_ENABLED(CONFIG_INTEL_MEI_GSC)) &&
fw_needs_gsc) {
- drm_info(>->i915->drm,
- "Can't load HuC due to missing MEI modules\n");
+ huc_info(huc, "Can't load due to missing MEI modules\n");
return -EIO;
}
- drm_dbg(>->i915->drm, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
+ huc_dbg(huc, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
return 0;
}
int intel_huc_init(struct intel_huc *huc)
{
- struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
int err;
err = check_huc_loading_mode(huc);
@@ -323,7 +316,7 @@ int intel_huc_init(struct intel_huc *huc)
out:
intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
- drm_info(&i915->drm, "HuC init failed with %d\n", err);
+ huc_info(huc, "init failed with %d\n", err);
return err;
}
@@ -366,13 +359,13 @@ int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
delayed_huc_load_complete(huc);
if (ret) {
- drm_err(>->i915->drm, "HuC: Firmware not verified %d\n", ret);
+ huc_err(huc, "firmware not verified %d\n", ret);
intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
return ret;
}
intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
- drm_info(>->i915->drm, "HuC authenticated\n");
+ huc_info(huc, "authenticated\n");
return 0;
}
@@ -407,7 +400,7 @@ int intel_huc_auth(struct intel_huc *huc)
ret = intel_guc_auth_huc(guc, intel_guc_ggtt_offset(guc, huc->fw.rsa_data));
if (ret) {
- DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
+ huc_err(huc, "auth request not acked by GuC: %d\n", ret);
goto fail;
}
@@ -419,7 +412,7 @@ int intel_huc_auth(struct intel_huc *huc)
return 0;
fail:
- i915_probe_error(gt->i915, "HuC: Authentication failed %d\n", ret);
+ huc_probe_error(huc, "authentication failed %d\n", ret);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 52db03620c609..f253c1c19f12f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -16,6 +16,29 @@
struct bus_type;
+#define huc_err(_huc, _fmt, ...) \
+ gt_err(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
+
+#define huc_warn(_huc, _fmt, ...) \
+ gt_warn(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
+
+#define huc_notice(_huc, _fmt, ...) \
+ gt_notice(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
+
+#define huc_info(_huc, _fmt, ...) \
+ gt_info(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
+
+#define huc_dbg(_huc, _fmt, ...) \
+ gt_dbg(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
+
+#define huc_probe_error(_huc, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ huc_dbg(_huc, _fmt, ##__VA_ARGS__); \
+ else \
+ huc_err(_huc, _fmt, ##__VA_ARGS__); \
+ } while (0)
+
enum intel_huc_delayed_load_status {
INTEL_HUC_WAITING_ON_GSC = 0,
INTEL_HUC_WAITING_ON_PXP,
--
2.37.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v2 2/5] drm/i915/huc: Add HuC specific debug print wrappers
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
@ 2022-11-22 17:17 ` Michal Wajdeczko
-1 siblings, 0 replies; 51+ messages in thread
From: Michal Wajdeczko @ 2022-11-22 17:17 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Create a set of HuC printers and start using them.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 ++++++++++----------------
> drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 +++++++++++++++++++
> 2 files changed, 35 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index be855811d85df..0bbbc7192da63 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -107,11 +107,9 @@ static enum hrtimer_restart huc_delayed_load_timer_callback(struct hrtimer *hrti
>
> if (!intel_huc_is_authenticated(huc)) {
> if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
> - drm_notice(&huc_to_gt(huc)->i915->drm,
> - "timed out waiting for MEI GSC init to load HuC\n");
> + huc_notice(huc, "Timed out waiting for MEI GSC init to load FW\n");
> else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
> - drm_notice(&huc_to_gt(huc)->i915->drm,
> - "timed out waiting for MEI PXP init to load HuC\n");
> + huc_notice(huc, "Timed out waiting for MEI PXP init to load FW\n");
> else
> MISSING_CASE(huc->delayed_load.status);
>
> @@ -174,8 +172,7 @@ static int gsc_notifier(struct notifier_block *nb, unsigned long action, void *d
>
> case BUS_NOTIFY_DRIVER_NOT_BOUND: /* mei driver fails to be bound */
> case BUS_NOTIFY_UNBIND_DRIVER: /* mei driver about to be unbound */
> - drm_info(&huc_to_gt(huc)->i915->drm,
> - "mei driver not bound, disabling HuC load\n");
> + huc_info(huc, "- mei driver not bound, disabling HuC load\n");
> gsc_init_error(huc);
> break;
> }
> @@ -193,8 +190,7 @@ void intel_huc_register_gsc_notifier(struct intel_huc *huc, struct bus_type *bus
> huc->delayed_load.nb.notifier_call = gsc_notifier;
> ret = bus_register_notifier(bus, &huc->delayed_load.nb);
> if (ret) {
> - drm_err(&huc_to_gt(huc)->i915->drm,
> - "failed to register GSC notifier\n");
> + huc_err(huc, "Failed to register GSC notifier\n");
> huc->delayed_load.nb.notifier_call = NULL;
> gsc_init_error(huc);
> }
> @@ -284,8 +280,7 @@ static int check_huc_loading_mode(struct intel_huc *huc)
> GSC_LOADS_HUC;
>
> if (fw_needs_gsc != hw_uses_gsc) {
> - drm_err(>->i915->drm,
> - "mismatch between HuC FW (%s) and HW (%s) load modes\n",
> + huc_err(huc, "Mismatch between FW (%s) and HW (%s) load modes\n",
> HUC_LOAD_MODE_STRING(fw_needs_gsc),
> HUC_LOAD_MODE_STRING(hw_uses_gsc));
> return -ENOEXEC;
> @@ -294,19 +289,17 @@ static int check_huc_loading_mode(struct intel_huc *huc)
> /* make sure we can access the GSC via the mei driver if we need it */
> if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) && IS_ENABLED(CONFIG_INTEL_MEI_GSC)) &&
> fw_needs_gsc) {
> - drm_info(>->i915->drm,
> - "Can't load HuC due to missing MEI modules\n");
> + huc_info(huc, "Can't load due to missing MEI modules\n");
> return -EIO;
> }
>
> - drm_dbg(>->i915->drm, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
> + huc_dbg(huc, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
this will give:
"GT0: HuC GSC loads huc=yes"
but maybe better to change that to get:
"GT0: HuC loaded by GSC=yes"
so this should be:
huc_dbg(huc, "loaded by GSC=%s\n", str_yes_no(fw_needs_gsc));
>
> return 0;
> }
>
> int intel_huc_init(struct intel_huc *huc)
> {
> - struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
> int err;
>
> err = check_huc_loading_mode(huc);
> @@ -323,7 +316,7 @@ int intel_huc_init(struct intel_huc *huc)
>
> out:
> intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
> - drm_info(&i915->drm, "HuC init failed with %d\n", err);
> + huc_info(huc, "init failed with %d\n", err);
> return err;
> }
>
> @@ -366,13 +359,13 @@ int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
> delayed_huc_load_complete(huc);
>
> if (ret) {
> - drm_err(>->i915->drm, "HuC: Firmware not verified %d\n", ret);
> + huc_err(huc, "firmware not verified %d\n", ret);
> intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
> return ret;
> }
>
> intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
> - drm_info(>->i915->drm, "HuC authenticated\n");
> + huc_info(huc, "authenticated\n");
> return 0;
> }
>
> @@ -407,7 +400,7 @@ int intel_huc_auth(struct intel_huc *huc)
>
> ret = intel_guc_auth_huc(guc, intel_guc_ggtt_offset(guc, huc->fw.rsa_data));
> if (ret) {
> - DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
> + huc_err(huc, "auth request not acked by GuC: %d\n", ret);
> goto fail;
> }
>
> @@ -419,7 +412,7 @@ int intel_huc_auth(struct intel_huc *huc)
> return 0;
>
> fail:
> - i915_probe_error(gt->i915, "HuC: Authentication failed %d\n", ret);
> + huc_probe_error(huc, "authentication failed %d\n", ret);
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> index 52db03620c609..f253c1c19f12f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> @@ -16,6 +16,29 @@
>
> struct bus_type;
>
> +#define huc_err(_huc, _fmt, ...) \
> + gt_err(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
> +
> +#define huc_warn(_huc, _fmt, ...) \
> + gt_warn(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
> +
> +#define huc_notice(_huc, _fmt, ...) \
> + gt_notice(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
> +
> +#define huc_info(_huc, _fmt, ...) \
> + gt_info(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
> +
> +#define huc_dbg(_huc, _fmt, ...) \
> + gt_dbg(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
> +
> +#define huc_probe_error(_huc, _fmt, ...) \
> + do { \
> + if (i915_error_injected()) \
> + huc_dbg(_huc, _fmt, ##__VA_ARGS__); \
> + else \
> + huc_err(_huc, _fmt, ##__VA_ARGS__); \
> + } while (0)
shouldn't we use gt_probe_error() here ?
#define huc_probe_error(_huc, _fmt, ...) \
gt_probe_error(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
> +
> enum intel_huc_delayed_load_status {
> INTEL_HUC_WAITING_ON_GSC = 0,
> INTEL_HUC_WAITING_ON_PXP,
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH v2 2/5] drm/i915/huc: Add HuC specific debug print wrappers
@ 2022-11-22 17:17 ` Michal Wajdeczko
0 siblings, 0 replies; 51+ messages in thread
From: Michal Wajdeczko @ 2022-11-22 17:17 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Create a set of HuC printers and start using them.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 ++++++++++----------------
> drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 +++++++++++++++++++
> 2 files changed, 35 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index be855811d85df..0bbbc7192da63 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -107,11 +107,9 @@ static enum hrtimer_restart huc_delayed_load_timer_callback(struct hrtimer *hrti
>
> if (!intel_huc_is_authenticated(huc)) {
> if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
> - drm_notice(&huc_to_gt(huc)->i915->drm,
> - "timed out waiting for MEI GSC init to load HuC\n");
> + huc_notice(huc, "Timed out waiting for MEI GSC init to load FW\n");
> else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
> - drm_notice(&huc_to_gt(huc)->i915->drm,
> - "timed out waiting for MEI PXP init to load HuC\n");
> + huc_notice(huc, "Timed out waiting for MEI PXP init to load FW\n");
> else
> MISSING_CASE(huc->delayed_load.status);
>
> @@ -174,8 +172,7 @@ static int gsc_notifier(struct notifier_block *nb, unsigned long action, void *d
>
> case BUS_NOTIFY_DRIVER_NOT_BOUND: /* mei driver fails to be bound */
> case BUS_NOTIFY_UNBIND_DRIVER: /* mei driver about to be unbound */
> - drm_info(&huc_to_gt(huc)->i915->drm,
> - "mei driver not bound, disabling HuC load\n");
> + huc_info(huc, "- mei driver not bound, disabling HuC load\n");
> gsc_init_error(huc);
> break;
> }
> @@ -193,8 +190,7 @@ void intel_huc_register_gsc_notifier(struct intel_huc *huc, struct bus_type *bus
> huc->delayed_load.nb.notifier_call = gsc_notifier;
> ret = bus_register_notifier(bus, &huc->delayed_load.nb);
> if (ret) {
> - drm_err(&huc_to_gt(huc)->i915->drm,
> - "failed to register GSC notifier\n");
> + huc_err(huc, "Failed to register GSC notifier\n");
> huc->delayed_load.nb.notifier_call = NULL;
> gsc_init_error(huc);
> }
> @@ -284,8 +280,7 @@ static int check_huc_loading_mode(struct intel_huc *huc)
> GSC_LOADS_HUC;
>
> if (fw_needs_gsc != hw_uses_gsc) {
> - drm_err(>->i915->drm,
> - "mismatch between HuC FW (%s) and HW (%s) load modes\n",
> + huc_err(huc, "Mismatch between FW (%s) and HW (%s) load modes\n",
> HUC_LOAD_MODE_STRING(fw_needs_gsc),
> HUC_LOAD_MODE_STRING(hw_uses_gsc));
> return -ENOEXEC;
> @@ -294,19 +289,17 @@ static int check_huc_loading_mode(struct intel_huc *huc)
> /* make sure we can access the GSC via the mei driver if we need it */
> if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) && IS_ENABLED(CONFIG_INTEL_MEI_GSC)) &&
> fw_needs_gsc) {
> - drm_info(>->i915->drm,
> - "Can't load HuC due to missing MEI modules\n");
> + huc_info(huc, "Can't load due to missing MEI modules\n");
> return -EIO;
> }
>
> - drm_dbg(>->i915->drm, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
> + huc_dbg(huc, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
this will give:
"GT0: HuC GSC loads huc=yes"
but maybe better to change that to get:
"GT0: HuC loaded by GSC=yes"
so this should be:
huc_dbg(huc, "loaded by GSC=%s\n", str_yes_no(fw_needs_gsc));
>
> return 0;
> }
>
> int intel_huc_init(struct intel_huc *huc)
> {
> - struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
> int err;
>
> err = check_huc_loading_mode(huc);
> @@ -323,7 +316,7 @@ int intel_huc_init(struct intel_huc *huc)
>
> out:
> intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
> - drm_info(&i915->drm, "HuC init failed with %d\n", err);
> + huc_info(huc, "init failed with %d\n", err);
> return err;
> }
>
> @@ -366,13 +359,13 @@ int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
> delayed_huc_load_complete(huc);
>
> if (ret) {
> - drm_err(>->i915->drm, "HuC: Firmware not verified %d\n", ret);
> + huc_err(huc, "firmware not verified %d\n", ret);
> intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
> return ret;
> }
>
> intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
> - drm_info(>->i915->drm, "HuC authenticated\n");
> + huc_info(huc, "authenticated\n");
> return 0;
> }
>
> @@ -407,7 +400,7 @@ int intel_huc_auth(struct intel_huc *huc)
>
> ret = intel_guc_auth_huc(guc, intel_guc_ggtt_offset(guc, huc->fw.rsa_data));
> if (ret) {
> - DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
> + huc_err(huc, "auth request not acked by GuC: %d\n", ret);
> goto fail;
> }
>
> @@ -419,7 +412,7 @@ int intel_huc_auth(struct intel_huc *huc)
> return 0;
>
> fail:
> - i915_probe_error(gt->i915, "HuC: Authentication failed %d\n", ret);
> + huc_probe_error(huc, "authentication failed %d\n", ret);
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> index 52db03620c609..f253c1c19f12f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> @@ -16,6 +16,29 @@
>
> struct bus_type;
>
> +#define huc_err(_huc, _fmt, ...) \
> + gt_err(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
> +
> +#define huc_warn(_huc, _fmt, ...) \
> + gt_warn(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
> +
> +#define huc_notice(_huc, _fmt, ...) \
> + gt_notice(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
> +
> +#define huc_info(_huc, _fmt, ...) \
> + gt_info(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
> +
> +#define huc_dbg(_huc, _fmt, ...) \
> + gt_dbg(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
> +
> +#define huc_probe_error(_huc, _fmt, ...) \
> + do { \
> + if (i915_error_injected()) \
> + huc_dbg(_huc, _fmt, ##__VA_ARGS__); \
> + else \
> + huc_err(_huc, _fmt, ##__VA_ARGS__); \
> + } while (0)
shouldn't we use gt_probe_error() here ?
#define huc_probe_error(_huc, _fmt, ...) \
gt_probe_error(huc_to_gt(_huc), "HuC " _fmt, ##__VA_ARGS__)
> +
> enum intel_huc_delayed_load_status {
> INTEL_HUC_WAITING_ON_GSC = 0,
> INTEL_HUC_WAITING_ON_PXP,
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v2 3/5] drm/i915/guc: Add GuC specific debug print wrappers
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
@ 2022-11-18 1:58 ` John.C.Harrison
-1 siblings, 0 replies; 51+ messages in thread
From: John.C.Harrison @ 2022-11-18 1:58 UTC (permalink / raw)
To: Intel-GFX; +Cc: John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
Create a set of GuC printers and start using them.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 ++++------
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++++++++++
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +--
.../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 +++++---------
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +++---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++++++-----
drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +--
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 +++++++---------
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++++++++----------
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +++++-----
.../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +++----
.../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +--
12 files changed, 179 insertions(+), 190 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 52aede324788e..d9972510ee29b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -94,8 +94,8 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
assert_rpm_wakelock_held(>->i915->runtime_pm);
spin_lock_irq(gt->irq_lock);
- WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
- gt->pm_guc_events);
+ guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
+ gt->pm_guc_events);
gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
spin_unlock_irq(gt->irq_lock);
@@ -339,7 +339,7 @@ static void guc_init_params(struct intel_guc *guc)
params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
- DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
+ guc_dbg(guc, "init param[%2d] = %#x\n", i, params[i]);
}
/*
@@ -451,7 +451,7 @@ int intel_guc_init(struct intel_guc *guc)
intel_uc_fw_fini(&guc->fw);
out:
intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
- i915_probe_error(gt->i915, "failed with %d\n", ret);
+ guc_probe_error(guc, "init failed with %d\n", ret);
return ret;
}
@@ -484,7 +484,6 @@ void intel_guc_fini(struct intel_guc *guc)
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
u32 *response_buf, u32 response_buf_size)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
u32 header;
int i;
@@ -519,8 +518,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
10, 10, &header);
if (unlikely(ret)) {
timeout:
- drm_err(&i915->drm, "mmio request %#x: no reply %x\n",
- request[0], header);
+ guc_err(guc, "mmio request %#x: no reply %x\n", request[0], header);
goto out;
}
@@ -541,8 +539,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
- drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n",
- request[0], reason);
+ guc_dbg(guc, "mmio request %#x: retrying, reason %u\n", request[0], reason);
goto retry;
}
@@ -550,16 +547,14 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
- drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n",
- request[0], error, hint);
+ guc_err(guc, "mmio request %#x: failure %x/%u\n", request[0], error, hint);
ret = -ENXIO;
goto out;
}
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) {
proto:
- drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n",
- request[0], header);
+ guc_err(guc, "mmio request %#x: unexpected reply %#x\n", request[0], header);
ret = -EPROTO;
goto out;
}
@@ -601,9 +596,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
msg = payload[0] & guc->msg_enabled_mask;
if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
- drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC crash dump notification!\n");
+ guc_err(guc, "early notification: Crash dump!\n");
if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
- drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC exception notification!\n");
+ guc_err(guc, "early notification: Exception!\n");
return 0;
}
@@ -657,7 +652,7 @@ int intel_guc_suspend(struct intel_guc *guc)
*/
ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
if (ret)
- DRM_ERROR("GuC suspend: RESET_CLIENT action failed with error %d!\n", ret);
+ guc_err(guc, "suspend: RESET_CLIENT action failed with error %d!\n", ret);
}
/* Signal that the GuC isn't running. */
@@ -832,12 +827,11 @@ static int __guc_action_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 va
static int __guc_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
int err = __guc_action_self_cfg(guc, key, len, value);
if (unlikely(err))
- i915_probe_error(i915, "Unsuccessful self-config (%pe) key %#hx value %#llx\n",
- ERR_PTR(err), key, value);
+ guc_probe_error(guc, "self-config; Unsuccessful (%pe) key %#hx value %#llx\n",
+ ERR_PTR(err), key, value);
return err;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 1bb3f98292866..8c02d22bc7e82 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -24,6 +24,41 @@
struct __guc_ads_blob;
struct intel_guc_state_capture;
+#define guc_err(_guc, _fmt, ...) \
+ gt_err(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
+
+#define guc_warn(_guc, _fmt, ...) \
+ gt_warn(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
+
+#define guc_notice(_guc, _fmt, ...) \
+ gt_notice(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
+
+#define guc_info(_guc, _fmt, ...) \
+ gt_info(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
+
+#define guc_dbg(_guc, _fmt, ...) \
+ gt_dbg(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
+
+#define guc_probe_error(_guc, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ guc_dbg(_guc, _fmt, ##__VA_ARGS__); \
+ else \
+ guc_err(_guc, _fmt, ##__VA_ARGS__); \
+ } while (0)
+
+#define guc_WARN_ON(_guc, _condition) \
+ guc_WARN(_guc, _condition, "%s", "guc_WARN_ON(" __stringify(_condition) ")")
+
+#define guc_WARN_ON_ONCE(_guc, _condition) \
+ guc_WARN_ONCE(_guc, _condition, "%s", "guc_WARN_ON_ONCE(" __stringify(_condition) ")")
+
+#define guc_WARN(_guc, _condition, _fmt, ...) \
+ gt_WARN(guc_to_gt(_guc), _condition, "GuC " _fmt, ##__VA_ARGS__)
+
+#define guc_WARN_ONCE(_guc, _condition, _fmt, ...) \
+ gt_WARN_ONCE(guc_to_gt(_guc), _condition, "GuC " _fmt, ##__VA_ARGS__)
+
/**
* struct intel_guc - Top level structure of GuC.
*
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index a7f737c4792e2..fa9a31176b4a7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -427,7 +427,7 @@ static long guc_mmio_reg_state_create(struct intel_guc *guc)
guc->ads_regset = temp_set.storage;
- drm_dbg(&guc_to_gt(guc)->i915->drm, "Used %zu KB for temporary ADS regset\n",
+ guc_dbg(guc, "used %zu KB for temporary ADS regset\n",
(temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
return total * sizeof(struct guc_mmio_reg);
@@ -621,8 +621,7 @@ static void guc_init_golden_context(struct intel_guc *guc)
engine = find_engine_state(gt, engine_class);
if (!engine) {
- drm_err(>->i915->drm, "No engine state recorded for class %d!\n",
- engine_class);
+ guc_err(guc, "No engine state recorded for class %d!\n", engine_class);
ads_blob_write(guc, ads.eng_state_size[guc_class], 0);
ads_blob_write(guc, ads.golden_context_lrca[guc_class], 0);
continue;
@@ -646,7 +645,6 @@ static int
guc_capture_prep_lists(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0;
struct guc_gt_system_info local_info;
struct iosys_map info_map;
@@ -751,7 +749,7 @@ guc_capture_prep_lists(struct intel_guc *guc)
}
if (guc->ads_capture_size && guc->ads_capture_size != PAGE_ALIGN(total_size))
- drm_warn(&i915->drm, "GuC->ADS->Capture alloc size changed from %d to %d\n",
+ guc_warn(guc, "capture alloc size changed from %d to %d\n",
guc->ads_capture_size, PAGE_ALIGN(total_size));
return PAGE_ALIGN(total_size);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 1d49a7ec0bd8f..a8876178da6ff 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -353,7 +353,6 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
u32 ipver)
{
struct intel_gt *gt = guc_to_gt(guc);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct sseu_dev_info *sseu;
int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0;
const struct __guc_mmio_reg_descr_group *list;
@@ -402,7 +401,7 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
}
}
- drm_dbg(&i915->drm, "GuC-capture found %d-ext-regs.\n", num_tot_regs);
+ guc_dbg(guc, "capture found %d ext-regs.\n", num_tot_regs);
guc->capture->extlists = extlists;
}
@@ -477,7 +476,6 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
struct guc_mmio_reg *ptr, u16 num_entries)
{
u32 i = 0, j = 0;
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists;
struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists;
const struct __guc_mmio_reg_descr_group *match;
@@ -509,8 +507,7 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
}
}
if (i < num_entries)
- drm_dbg(&i915->drm, "GuC-capture: Init reglist short %d out %d.\n",
- (int)i, (int)num_entries);
+ guc_dbg(guc, "capture: Init reglist short %d out %d.\n", i, num_entries);
return 0;
}
@@ -540,12 +537,11 @@ guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
size_t *size, bool is_purpose_est)
{
struct intel_guc_state_capture *gc = guc->capture;
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
int num_regs;
if (!gc->reglists) {
- drm_warn(&i915->drm, "GuC-capture: No reglist on this device\n");
+ guc_warn(guc, "capture: No reglist on this device\n");
return -ENODEV;
}
@@ -557,9 +553,9 @@ guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
if (!is_purpose_est && owner == GUC_CAPTURE_LIST_INDEX_PF &&
!guc_capture_get_one_list(gc->reglists, owner, type, classid)) {
if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL)
- drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist Global!\n");
+ guc_warn(guc, "capture: Missing reglist: Global!\n");
else
- drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist %s(%u):%s(%u)!\n",
+ guc_warn(guc, "capture: Missing reglist: %s(%u):%s(%u)!\n",
__stringify_type(type), type,
__stringify_engclass(classid), classid);
return -ENODATA;
@@ -592,7 +588,6 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classi
{
struct intel_guc_state_capture *gc = guc->capture;
struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct guc_debug_capture_list *listnode;
int ret, num_regs;
u8 *caplist, *tmp;
@@ -623,7 +618,7 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classi
caplist = kzalloc(size, GFP_KERNEL);
if (!caplist) {
- drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached caplist");
+ guc_dbg(guc, "capture: Failed to alloc cached caplist\n");
return -ENOMEM;
}
@@ -653,7 +648,6 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
void **outptr, size_t *size)
{
struct intel_guc_state_capture *gc = guc->capture;
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
int tmp = sizeof(u32) * 4;
void *null_header;
@@ -665,7 +659,7 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
null_header = kzalloc(tmp, GFP_KERNEL);
if (!null_header) {
- drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached nulllist");
+ guc_dbg(guc, "capture: Failed to alloc cached null list\n");
return -ENOMEM;
}
@@ -727,7 +721,6 @@ guc_capture_output_min_size_est(struct intel_guc *guc)
static void check_guc_capture_size(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
int min_size = guc_capture_output_min_size_est(guc);
int spare_size = min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER;
u32 buffer_size = intel_guc_log_section_size_capture(&guc->log);
@@ -741,13 +734,13 @@ static void check_guc_capture_size(struct intel_guc *guc)
* INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE.
*/
if (min_size < 0)
- drm_warn(&i915->drm, "Failed to calculate GuC error state capture buffer minimum size: %d!\n",
+ guc_warn(guc, "error state capture buffer minimum size calculation failed: %d!\n",
min_size);
else if (min_size > buffer_size)
- drm_warn(&i915->drm, "GuC error state capture buffer maybe small: %d < %d\n",
+ guc_warn(guc, "error state capture buffer maybe small: %d < %d\n",
buffer_size, min_size);
else if (spare_size > buffer_size)
- drm_dbg(&i915->drm, "GuC error state capture buffer lacks spare size: %d < %d (min = %d)\n",
+ guc_dbg(guc, "error state capture buffer lacks spare size: %d < %d (min = %d)\n",
buffer_size, spare_size, min_size);
}
@@ -848,7 +841,6 @@ static int
guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *buf,
u32 *dw)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
int tries = 2;
int avail = 0;
u32 *src_data;
@@ -865,7 +857,7 @@ guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *
return 4;
}
if (avail)
- drm_dbg(&i915->drm, "GuC-Cap-Logs not dword aligned, skipping.\n");
+ guc_dbg(guc, "capture: Log not dword aligned, skipping.\n");
buf->rd = 0;
}
@@ -1118,13 +1110,12 @@ static void
__guc_capture_create_prealloc_nodes(struct intel_guc *guc)
{
struct __guc_capture_parsed_output *node = NULL;
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
int i;
for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) {
node = guc_capture_alloc_one_node(guc);
if (!node) {
- drm_warn(&i915->drm, "GuC Capture pre-alloc-cache failure\n");
+ guc_warn(guc, "capture pre-alloc-cache failure\n");
/* dont free the priors, use what we got and cleanup at shutdown */
return;
}
@@ -1169,7 +1160,6 @@ guc_capture_create_prealloc_nodes(struct intel_guc *guc)
static int
guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstate *buf)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct guc_state_capture_group_header_t ghdr = {0};
struct guc_state_capture_header_t hdr = {0};
struct __guc_capture_parsed_output *node = NULL;
@@ -1183,7 +1173,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
if (!i)
return -ENODATA;
if (i % sizeof(u32)) {
- drm_warn(&i915->drm, "GuC Capture new entries unaligned\n");
+ guc_warn(guc, "capture new entries unaligned\n");
ret = -EIO;
goto bailout;
}
@@ -1301,8 +1291,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
break;
}
if (datatype != GUC_CAPTURE_LIST_TYPE_GLOBAL)
- drm_dbg(&i915->drm, "GuC Capture missing global dump: %08x!\n",
- datatype);
+ guc_dbg(guc, "cpture missing global dump: %08x!\n", datatype);
}
node->is_partial = is_partial;
node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner);
@@ -1322,7 +1311,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios);
if (numregs > guc->capture->max_mmio_per_node) {
- drm_dbg(&i915->drm, "GuC Capture list extraction clipped by prealloc!\n");
+ guc_dbg(guc, "capture list extraction clipped by prealloc!\n");
numregs = guc->capture->max_mmio_per_node;
}
node->reginfo[datatype].num_regs = numregs;
@@ -1367,7 +1356,6 @@ static void __guc_capture_process_output(struct intel_guc *guc)
{
unsigned int buffer_size, read_offset, write_offset, full_count;
struct intel_uc *uc = container_of(guc, typeof(*uc), guc);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct guc_log_buffer_state log_buf_state_local;
struct guc_log_buffer_state *log_buf_state;
struct __guc_capture_bufstate buf;
@@ -1403,7 +1391,7 @@ static void __guc_capture_process_output(struct intel_guc *guc)
write_offset = buffer_size;
} else if (unlikely((read_offset > buffer_size) ||
(write_offset > buffer_size))) {
- drm_err(&i915->drm, "invalid GuC log capture buffer state!\n");
+ guc_err(guc, "capture: invalid buffer state!\n");
/* copy whole buffer as offsets are unreliable */
read_offset = 0;
write_offset = buffer_size;
@@ -1586,13 +1574,11 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
struct intel_context *ce)
{
struct __guc_capture_parsed_output *n, *ntmp;
- struct drm_i915_private *i915;
struct intel_guc *guc;
if (!gt || !ee || !ce)
return;
- i915 = gt->i915;
guc = >->uc.guc;
if (!guc->capture)
return;
@@ -1615,7 +1601,7 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
return;
}
}
- drm_dbg(&i915->drm, "GuC capture can't match ee to node\n");
+ guc_dbg(guc, "capture can't match ee to node\n");
}
void intel_guc_capture_process(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 5b86b2e286e07..4a2811aa3d5e1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -103,8 +103,9 @@ static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
return uk_val == INTEL_GUC_LOAD_STATUS_READY;
}
-static int guc_wait_ucode(struct intel_uncore *uncore)
+static int guc_wait_ucode(struct intel_gt *gt)
{
+ struct intel_uncore *uncore = gt->uncore;
u32 status;
int ret;
@@ -127,12 +128,8 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
*/
ret = wait_for(guc_ready(uncore, &status), 200);
if (ret) {
- struct drm_device *drm = &uncore->i915->drm;
-
- drm_info(drm, "GuC load failed: status = 0x%08X\n", status);
- drm_info(drm, "GuC load failed: status: Reset = %d, "
- "BootROM = 0x%02X, UKernel = 0x%02X, "
- "MIA = 0x%02X, Auth = 0x%02X\n",
+ gt_info(gt, "GuC load failed: status = 0x%08X\n", status);
+ gt_info(gt, "GuC load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n",
REG_FIELD_GET(GS_MIA_IN_RESET, status),
REG_FIELD_GET(GS_BOOTROM_MASK, status),
REG_FIELD_GET(GS_UKERNEL_MASK, status),
@@ -140,13 +137,13 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
- drm_info(drm, "GuC firmware signature verification failed\n");
+ gt_info(gt, "GuC firmware signature verification failed\n");
ret = -ENOEXEC;
}
if (REG_FIELD_GET(GS_UKERNEL_MASK, status) == INTEL_GUC_LOAD_STATUS_EXCEPTION) {
- drm_info(drm, "GuC firmware exception. EIP: %#x\n",
- intel_uncore_read(uncore, SOFT_SCRATCH(13)));
+ gt_info(gt, "GuC firmware exception. EIP: %#x\n",
+ intel_uncore_read(uncore, SOFT_SCRATCH(13)));
ret = -ENXIO;
}
}
@@ -194,7 +191,7 @@ int intel_guc_fw_upload(struct intel_guc *guc)
if (ret)
goto out;
- ret = guc_wait_ucode(uncore);
+ ret = guc_wait_ucode(gt);
if (ret)
goto out;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 68331c538b0a7..8c9a020700b52 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -39,7 +39,6 @@ struct guc_log_section {
static void _guc_log_init_sizes(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
static const struct guc_log_section sections[GUC_LOG_SECTIONS_LIMIT] = {
{
GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT,
@@ -82,12 +81,12 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
}
if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units))
- drm_err(&i915->drm, "Mis-aligned GuC log %s size: 0x%X vs 0x%X!",
+ guc_err(guc, "log: Mis-aligned %s size: 0x%X vs 0x%X!\n",
sections[i].name, log->sizes[i].bytes, log->sizes[i].units);
log->sizes[i].count = log->sizes[i].bytes / log->sizes[i].units;
if (!log->sizes[i].count) {
- drm_err(&i915->drm, "Zero GuC log %s size!", sections[i].name);
+ guc_err(guc, "log: zero %s size!\n", sections[i].name);
} else {
/* Size is +1 unit */
log->sizes[i].count--;
@@ -95,14 +94,14 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
/* Clip to field size */
if (log->sizes[i].count > sections[i].max) {
- drm_err(&i915->drm, "GuC log %s size too large: %d vs %d!",
+ guc_err(guc, "log: %s size too large: %d vs %d!\n",
sections[i].name, log->sizes[i].count + 1, sections[i].max + 1);
log->sizes[i].count = sections[i].max;
}
}
if (log->sizes[GUC_LOG_SECTIONS_CRASH].units != log->sizes[GUC_LOG_SECTIONS_DEBUG].units) {
- drm_err(&i915->drm, "Unit mis-match for GuC log crash and debug sections: %d vs %d!",
+ guc_err(guc, "log: Unit mis-match for crash and debug sections: %d vs %d!\n",
log->sizes[GUC_LOG_SECTIONS_CRASH].units,
log->sizes[GUC_LOG_SECTIONS_DEBUG].units);
log->sizes[GUC_LOG_SECTIONS_CRASH].units = log->sizes[GUC_LOG_SECTIONS_DEBUG].units;
@@ -383,7 +382,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
mutex_lock(&log->relay.lock);
- if (WARN_ON(!intel_guc_log_relay_created(log)))
+ if (guc_WARN_ON(log_to_guc(log), !intel_guc_log_relay_created(log)))
goto out_unlock;
/* Get the pointer to shared GuC log buffer */
@@ -451,7 +450,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
write_offset = buffer_size;
} else if (unlikely((read_offset > buffer_size) ||
(write_offset > buffer_size))) {
- DRM_ERROR("invalid log buffer state\n");
+ guc_err(log_to_guc(log), "log: invalid buffer state\n");
/* copy whole buffer as offsets are unreliable */
read_offset = 0;
write_offset = buffer_size;
@@ -520,7 +519,7 @@ void intel_guc_log_init_early(struct intel_guc_log *log)
static int guc_log_relay_create(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
+ struct intel_gt *gt = guc_to_gt(guc);
struct rchan *guc_log_relay_chan;
size_t n_subbufs, subbuf_size;
int ret;
@@ -543,11 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log *log)
n_subbufs = 8;
guc_log_relay_chan = relay_open("guc_log",
- dev_priv->drm.primary->debugfs_root,
+ gt->i915->drm.primary->debugfs_root,
subbuf_size, n_subbufs,
- &relay_callbacks, dev_priv);
+ &relay_callbacks, gt->i915);
if (!guc_log_relay_chan) {
- DRM_ERROR("Couldn't create relay chan for GuC logging\n");
+ guc_err(guc, "log: Failed to create relay chan\n");
ret = -ENOMEM;
return ret;
@@ -596,7 +595,7 @@ static u32 __get_default_log_level(struct intel_guc_log *log)
}
if (i915->params.guc_log_level > GUC_LOG_LEVEL_MAX) {
- DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
+ guc_warn(guc, "log: Incompatible options detected: %s=%d, %s!\n",
"guc_log_level", i915->params.guc_log_level,
"verbosity too high");
return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
@@ -641,15 +640,15 @@ int intel_guc_log_create(struct intel_guc_log *log)
log->buf_addr = vaddr;
log->level = __get_default_log_level(log);
- DRM_DEBUG_DRIVER("guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
- log->level, str_enabled_disabled(log->level),
- str_yes_no(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
- GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
+ guc_dbg(guc, "guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
+ log->level, str_enabled_disabled(log->level),
+ str_yes_no(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
+ GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
return 0;
err:
- DRM_ERROR("Failed to allocate or map GuC log buffer. %d\n", ret);
+ guc_err(guc, "log: Failed to allocate or map buffer: %d\n", ret);
return ret;
}
@@ -687,7 +686,7 @@ int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)
GUC_LOG_LEVEL_IS_ENABLED(level),
GUC_LOG_LEVEL_TO_VERBOSITY(level));
if (ret) {
- DRM_DEBUG_DRIVER("guc_log_control action failed %d\n", ret);
+ guc_dbg(guc, "guc_log_control action failed %d\n", ret);
goto out_unlock;
}
@@ -905,7 +904,7 @@ int intel_guc_log_dump(struct intel_guc_log *log, struct drm_printer *p,
map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
if (IS_ERR(map)) {
- DRM_DEBUG("Failed to pin object\n");
+ guc_dbg(guc, "log: Failed to pin buffer object\n");
drm_puts(p, "(log data unaccessible)\n");
free_page((unsigned long)page);
return PTR_ERR(map);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
index b5855091cf6a9..62f3b97111f64 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
@@ -70,13 +70,12 @@ static int __guc_rc_control(struct intel_guc *guc, bool enable)
ret = guc_action_control_gucrc(guc, enable);
if (ret) {
- i915_probe_error(guc_to_gt(guc)->i915, "Failed to %s GuC RC (%pe)\n",
- str_enable_disable(enable), ERR_PTR(ret));
+ guc_probe_error(guc, "RC: Failed to %s: %pe\n",
+ str_enable_disable(enable), ERR_PTR(ret));
return ret;
}
- drm_info(>->i915->drm, "GuC RC: %s\n",
- str_enabled_disabled(enable));
+ guc_info(guc, "RC %s\n", str_enabled_disabled(enable));
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 63464933cbceb..b9ef0b4a123e1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -171,14 +171,12 @@ static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
static int slpc_query_task_state(struct intel_guc_slpc *slpc)
{
struct intel_guc *guc = slpc_to_guc(slpc);
- struct drm_i915_private *i915 = slpc_to_i915(slpc);
u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
int ret;
ret = guc_action_slpc_query(guc, offset);
if (unlikely(ret))
- i915_probe_error(i915, "Failed to query task state (%pe)\n",
- ERR_PTR(ret));
+ guc_probe_error(guc, "SLPC: Failed to query task state (%pe)\n", ERR_PTR(ret));
drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
@@ -188,15 +186,14 @@ static int slpc_query_task_state(struct intel_guc_slpc *slpc)
static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
{
struct intel_guc *guc = slpc_to_guc(slpc);
- struct drm_i915_private *i915 = slpc_to_i915(slpc);
int ret;
GEM_BUG_ON(id >= SLPC_MAX_PARAM);
ret = guc_action_slpc_set_param(guc, id, value);
if (ret)
- i915_probe_error(i915, "Failed to set param %d to %u (%pe)\n",
- id, value, ERR_PTR(ret));
+ guc_probe_error(guc, "SLPC: Failed to set param %d to %u (%pe)\n",
+ id, value, ERR_PTR(ret));
return ret;
}
@@ -236,8 +233,7 @@ static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
freq);
if (ret)
- drm_notice(&i915->drm,
- "Failed to send set_param for min freq(%d): (%d)\n",
+ guc_notice(guc, "SLPC: Failed to send set_param for min freq(%d): (%d)\n",
freq, ret);
}
@@ -267,7 +263,6 @@ static void slpc_boost_work(struct work_struct *work)
int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
{
struct intel_guc *guc = slpc_to_guc(slpc);
- struct drm_i915_private *i915 = slpc_to_i915(slpc);
u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
int err;
@@ -275,9 +270,8 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&slpc->vaddr);
if (unlikely(err)) {
- i915_probe_error(i915,
- "Failed to allocate SLPC struct (err=%pe)\n",
- ERR_PTR(err));
+ guc_probe_error(guc, "SLPC: Failed to allocate SLPC struct (err=%pe)\n",
+ ERR_PTR(err));
return err;
}
@@ -338,7 +332,6 @@ static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset)
static int slpc_reset(struct intel_guc_slpc *slpc)
{
- struct drm_i915_private *i915 = slpc_to_i915(slpc);
struct intel_guc *guc = slpc_to_guc(slpc);
u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
int ret;
@@ -346,15 +339,14 @@ static int slpc_reset(struct intel_guc_slpc *slpc)
ret = guc_action_slpc_reset(guc, offset);
if (unlikely(ret < 0)) {
- i915_probe_error(i915, "SLPC reset action failed (%pe)\n",
- ERR_PTR(ret));
+ guc_probe_error(guc, "SLPC: Reset action failed (%pe)\n", ERR_PTR(ret));
return ret;
}
if (!ret) {
if (wait_for(slpc_is_running(slpc), SLPC_RESET_TIMEOUT_MS)) {
- i915_probe_error(i915, "SLPC not enabled! State = %s\n",
- slpc_get_state_string(slpc));
+ guc_probe_error(guc, "SLPC: Not enabled! State = %s\n",
+ slpc_get_state_string(slpc));
return -EIO;
}
}
@@ -495,8 +487,8 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
val < slpc->rp1_freq);
if (ret) {
- i915_probe_error(i915, "Failed to toggle efficient freq (%pe)\n",
- ERR_PTR(ret));
+ guc_probe_error(slpc_to_guc(slpc), "SLPC: Failed to toggle efficient freq (%pe)\n",
+ ERR_PTR(ret));
goto out;
}
@@ -611,15 +603,12 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
{
- struct drm_i915_private *i915 = slpc_to_i915(slpc);
int slpc_min_freq;
int ret;
ret = intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq);
if (ret) {
- drm_err(&i915->drm,
- "Failed to get min freq: (%d)\n",
- ret);
+ guc_err(slpc_to_guc(slpc), "SLPC: Failed to get min freq: (%d)\n", ret);
return false;
}
@@ -685,8 +674,7 @@ int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode)
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
ret = slpc_set_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
if (ret)
- drm_err(&i915->drm,
- "Override gucrc mode %d failed %d\n",
+ guc_err(slpc_to_guc(slpc), "SLPC: Override gucrc mode %d failed %d\n",
mode, ret);
}
@@ -702,9 +690,7 @@ int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
ret = slpc_unset_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE);
if (ret)
- drm_err(&i915->drm,
- "Unsetting gucrc mode failed %d\n",
- ret);
+ guc_err(slpc_to_guc(slpc), "SLPC: Unsetting gucrc mode failed %d\n", ret);
}
return ret;
@@ -726,6 +712,7 @@ int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
{
struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ struct intel_guc *guc = slpc_to_guc(slpc);
int ret;
GEM_BUG_ON(!slpc->vma);
@@ -734,8 +721,8 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
ret = slpc_reset(slpc);
if (unlikely(ret < 0)) {
- i915_probe_error(i915, "SLPC Reset event returned (%pe)\n",
- ERR_PTR(ret));
+ guc_probe_error(guc, "SLPC: Reset event returned (%pe)\n",
+ ERR_PTR(ret));
return ret;
}
@@ -753,16 +740,16 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
/* Set SLPC max limit to RP0 */
ret = slpc_use_fused_rp0(slpc);
if (unlikely(ret)) {
- i915_probe_error(i915, "Failed to set SLPC max to RP0 (%pe)\n",
- ERR_PTR(ret));
+ guc_probe_error(guc, "SLPC: Failed to set max to RP0 (%pe)\n",
+ ERR_PTR(ret));
return ret;
}
/* Revert SLPC min/max to softlimits if necessary */
ret = slpc_set_softlimits(slpc);
if (unlikely(ret)) {
- i915_probe_error(i915, "Failed to set SLPC softlimits (%pe)\n",
- ERR_PTR(ret));
+ guc_probe_error(guc, "SLPC: Failed to set softlimits (%pe)\n",
+ ERR_PTR(ret));
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0a42f1807f52c..da8ab18aa4ce7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1443,8 +1443,7 @@ static void guc_init_engine_stats(struct intel_guc *guc)
int ret = guc_action_enable_usage_stats(guc);
if (ret)
- drm_err(>->i915->drm,
- "Failed to enable usage stats: %d!\n", ret);
+ guc_err(guc, "Failed to enable usage stats: %d!\n", ret);
}
}
@@ -3584,8 +3583,7 @@ static int guc_request_alloc(struct i915_request *rq)
intel_context_sched_disable_unpin(ce);
else if (intel_context_is_closed(ce))
if (wait_for(context_close_done(ce), 1500))
- drm_warn(&guc_to_gt(guc)->i915->drm,
- "timed out waiting on context sched close before realloc\n");
+ guc_warn(guc, "timed out waiting on context sched close before realloc\n");
/*
* Call pin_guc_id here rather than in the pinning step as with
* dma_resv, contexts can be repeatedly pinned / unpinned trashing the
@@ -4350,7 +4348,7 @@ static int __guc_action_set_scheduling_policies(struct intel_guc *guc,
return ret;
if (ret != policy->count) {
- drm_warn(&guc_to_gt(guc)->i915->drm, "GuC global scheduler policy processed %d of %d KLVs!",
+ guc_warn(guc, "H2G: global scheduler policy processed %d of %d KLVs!\n",
ret, policy->count);
if (ret > policy->count)
return -EPROTO;
@@ -4383,9 +4381,9 @@ static int guc_init_global_schedule_policy(struct intel_guc *guc)
ret = __guc_action_set_scheduling_policies(guc, &policy);
if (ret)
- i915_probe_error(gt->i915,
- "Failed to configure global scheduling policies: %pe!\n",
- ERR_PTR(ret));
+ guc_probe_error(guc,
+ "Failed to configure global scheduling policies: %pe!\n",
+ ERR_PTR(ret));
}
return ret;
@@ -4484,21 +4482,18 @@ g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)
struct intel_context *ce;
if (unlikely(ctx_id >= GUC_MAX_CONTEXT_ID)) {
- drm_err(&guc_to_gt(guc)->i915->drm,
- "Invalid ctx_id %u\n", ctx_id);
+ guc_err(guc, "Invalid ctx_id %u\n", ctx_id);
return NULL;
}
ce = __get_context(guc, ctx_id);
if (unlikely(!ce)) {
- drm_err(&guc_to_gt(guc)->i915->drm,
- "Context is NULL, ctx_id %u\n", ctx_id);
+ guc_err(guc, "Context is NULL, ctx_id %u\n", ctx_id);
return NULL;
}
if (unlikely(intel_context_is_child(ce))) {
- drm_err(&guc_to_gt(guc)->i915->drm,
- "Context is child, ctx_id %u\n", ctx_id);
+ guc_err(guc, "Context is child, ctx_id %u\n", ctx_id);
return NULL;
}
@@ -4513,7 +4508,7 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
u32 ctx_id;
if (unlikely(len < 1)) {
- drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
+ guc_err(guc, "notification: Invalid length %u for deregister done\n", len);
return -EPROTO;
}
ctx_id = msg[0];
@@ -4565,7 +4560,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
u32 ctx_id;
if (unlikely(len < 2)) {
- drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
+ guc_err(guc, "notification: Invalid length %u for sched done\n", len);
return -EPROTO;
}
ctx_id = msg[0];
@@ -4577,8 +4572,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
if (unlikely(context_destroyed(ce) ||
(!context_pending_enable(ce) &&
!context_pending_disable(ce)))) {
- drm_err(&guc_to_gt(guc)->i915->drm,
- "Bad context sched_state 0x%x, ctx_id %u\n",
+ guc_err(guc, "notification: Bad context sched_state 0x%x, ctx_id %u\n",
ce->guc_state.sched_state, ctx_id);
return -EPROTO;
}
@@ -4666,8 +4660,8 @@ static void guc_handle_context_reset(struct intel_guc *guc,
capture_error_state(guc, ce);
guc_context_replay(ce);
} else {
- drm_info(&guc_to_gt(guc)->i915->drm,
- "Ignoring context reset notification of exiting context 0x%04X on %s",
+ guc_info(guc,
+ "Ignoring context reset notification of exiting context 0x%04X on %s\n",
ce->guc_id.id, ce->engine->name);
}
}
@@ -4680,7 +4674,7 @@ int intel_guc_context_reset_process_msg(struct intel_guc *guc,
int ctx_id;
if (unlikely(len != 1)) {
- drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
+ guc_err(guc, "notification: Invalid length %u for context reset\n", len);
return -EPROTO;
}
@@ -4713,13 +4707,13 @@ int intel_guc_error_capture_process_msg(struct intel_guc *guc,
u32 status;
if (unlikely(len != 1)) {
- drm_dbg(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
+ guc_err(guc, "notification: Invalid length %u for error capture\n", len);
return -EPROTO;
}
status = msg[0] & INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK;
if (status == INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE)
- drm_warn(&guc_to_gt(guc)->i915->drm, "G2H-Error capture no space");
+ guc_warn(guc, "notification: Error capture buffer overflow\n");
intel_guc_capture_process(guc);
@@ -4762,13 +4756,12 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
const u32 *msg, u32 len)
{
struct intel_engine_cs *engine;
- struct intel_gt *gt = guc_to_gt(guc);
u8 guc_class, instance;
u32 reason;
unsigned long flags;
if (unlikely(len != 3)) {
- drm_err(>->i915->drm, "Invalid length %u", len);
+ guc_err(guc, "notification: Invalid length %u for engine failure\n", len);
return -EPROTO;
}
@@ -4778,8 +4771,8 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
engine = intel_guc_lookup_engine(guc, guc_class, instance);
if (unlikely(!engine)) {
- drm_err(>->i915->drm,
- "Invalid engine %d:%d", guc_class, instance);
+ guc_err(guc, "notification: Invalid engine %d:%d for engine failure\n",
+ guc_class, instance);
return -EPROTO;
}
@@ -4787,7 +4780,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
* This is an unexpected failure of a hardware feature. So, log a real
* error message not just the informational that comes with the reset.
*/
- drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X",
+ guc_err(guc, "notification: Engine reset request failed on %d:%d (%s) because 0x%08X\n",
guc_class, instance, engine->name, reason);
spin_lock_irqsave(&guc->submission_state.lock, flags);
@@ -5297,6 +5290,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
unsigned long flags)
{
struct guc_virtual_engine *ve;
+ struct intel_gt *gt;
struct intel_guc *guc;
unsigned int n;
int err;
@@ -5305,10 +5299,11 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
if (!ve)
return ERR_PTR(-ENOMEM);
- guc = &siblings[0]->gt->uc.guc;
+ gt = siblings[0]->gt;
+ guc = >->uc.guc;
ve->base.i915 = siblings[0]->i915;
- ve->base.gt = siblings[0]->gt;
+ ve->base.gt = gt;
ve->base.uncore = siblings[0]->uncore;
ve->base.id = -1;
@@ -5336,8 +5331,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
GEM_BUG_ON(!is_power_of_2(sibling->mask));
if (sibling->mask & ve->base.mask) {
- DRM_DEBUG("duplicate %s entry in load balancer\n",
- sibling->name);
+ guc_dbg(guc, "Duplicate %s entry in load balancer\n", sibling->name);
err = -EINVAL;
goto err_put;
}
@@ -5346,8 +5340,8 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
ve->base.logical_mask |= sibling->logical_mask;
if (n != 0 && ve->base.class != sibling->class) {
- DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n",
- sibling->class, ve->base.class);
+ guc_dbg(guc, "Invalid mixing of engine class, sibling %d, already %d\n",
+ sibling->class, ve->base.class);
err = -EINVAL;
goto err_put;
} else if (n == 0) {
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
index e28518fe8b908..d588c32d65c54 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
@@ -65,7 +65,7 @@ static int intel_guc_scrub_ctbs(void *arg)
ce = intel_context_create(engine);
if (IS_ERR(ce)) {
ret = PTR_ERR(ce);
- drm_err(>->i915->drm, "Failed to create context, %d: %d\n", i, ret);
+ gt_err(gt, "Failed to create context, %d: %d\n", i, ret);
goto err;
}
@@ -86,7 +86,7 @@ static int intel_guc_scrub_ctbs(void *arg)
if (IS_ERR(rq)) {
ret = PTR_ERR(rq);
- drm_err(>->i915->drm, "Failed to create request, %d: %d\n", i, ret);
+ gt_err(gt, "Failed to create request, %d: %d\n", i, ret);
goto err;
}
@@ -96,7 +96,7 @@ static int intel_guc_scrub_ctbs(void *arg)
for (i = 0; i < 3; ++i) {
ret = i915_request_wait(last[i], 0, HZ);
if (ret < 0) {
- drm_err(>->i915->drm, "Last request failed to complete: %d\n", ret);
+ gt_err(gt, "Last request failed to complete: %d\n", ret);
goto err;
}
i915_request_put(last[i]);
@@ -113,7 +113,7 @@ static int intel_guc_scrub_ctbs(void *arg)
/* GT will not idle if G2H are lost */
ret = intel_gt_wait_for_idle(gt, HZ);
if (ret < 0) {
- drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
+ gt_err(gt, "GT failed to idle: %d\n", ret);
goto err;
}
@@ -153,7 +153,7 @@ static int intel_guc_steal_guc_ids(void *arg)
ce = kcalloc(GUC_MAX_CONTEXT_ID, sizeof(*ce), GFP_KERNEL);
if (!ce) {
- drm_err(>->i915->drm, "Context array allocation failed\n");
+ guc_err(guc, "Context array allocation failed\n");
return -ENOMEM;
}
@@ -167,24 +167,24 @@ static int intel_guc_steal_guc_ids(void *arg)
if (IS_ERR(ce[context_index])) {
ret = PTR_ERR(ce[context_index]);
ce[context_index] = NULL;
- drm_err(>->i915->drm, "Failed to create context: %d\n", ret);
+ guc_err(guc, "Failed to create context: %d\n", ret);
goto err_wakeref;
}
ret = igt_spinner_init(&spin, engine->gt);
if (ret) {
- drm_err(>->i915->drm, "Failed to create spinner: %d\n", ret);
+ guc_err(guc, "Failed to create spinner: %d\n", ret);
goto err_contexts;
}
spin_rq = igt_spinner_create_request(&spin, ce[context_index],
MI_ARB_CHECK);
if (IS_ERR(spin_rq)) {
ret = PTR_ERR(spin_rq);
- drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
+ guc_err(guc, "Failed to create spinner request: %d\n", ret);
goto err_contexts;
}
ret = request_add_spin(spin_rq, &spin);
if (ret) {
- drm_err(>->i915->drm, "Failed to add Spinner request: %d\n", ret);
+ guc_err(guc, "Failed to add Spinner request: %d\n", ret);
goto err_spin_rq;
}
@@ -194,7 +194,7 @@ static int intel_guc_steal_guc_ids(void *arg)
if (IS_ERR(ce[context_index])) {
ret = PTR_ERR(ce[context_index--]);
ce[context_index] = NULL;
- drm_err(>->i915->drm, "Failed to create context: %d\n", ret);
+ guc_err(guc, "Failed to create context: %d\n", ret);
goto err_spin_rq;
}
@@ -203,7 +203,7 @@ static int intel_guc_steal_guc_ids(void *arg)
ret = PTR_ERR(rq);
rq = NULL;
if (ret != -EAGAIN) {
- drm_err(>->i915->drm, "Failed to create request, %d: %d\n",
+ guc_err(guc, "Failed to create request, %d: %d\n",
context_index, ret);
goto err_spin_rq;
}
@@ -218,7 +218,7 @@ static int intel_guc_steal_guc_ids(void *arg)
igt_spinner_end(&spin);
ret = intel_selftest_wait_for_rq(spin_rq);
if (ret) {
- drm_err(>->i915->drm, "Spin request failed to complete: %d\n", ret);
+ guc_err(guc, "Spin request failed to complete: %d\n", ret);
i915_request_put(last);
goto err_spin_rq;
}
@@ -230,7 +230,7 @@ static int intel_guc_steal_guc_ids(void *arg)
ret = i915_request_wait(last, 0, HZ * 30);
i915_request_put(last);
if (ret < 0) {
- drm_err(>->i915->drm, "Last request failed to complete: %d\n", ret);
+ guc_err(guc, "Last request failed to complete: %d\n", ret);
goto err_spin_rq;
}
@@ -238,7 +238,7 @@ static int intel_guc_steal_guc_ids(void *arg)
rq = nop_user_request(ce[context_index], NULL);
if (IS_ERR(rq)) {
ret = PTR_ERR(rq);
- drm_err(>->i915->drm, "Failed to steal guc_id, %d: %d\n", context_index, ret);
+ guc_err(guc, "Failed to steal guc_id, %d: %d\n", context_index, ret);
goto err_spin_rq;
}
@@ -246,20 +246,20 @@ static int intel_guc_steal_guc_ids(void *arg)
ret = i915_request_wait(rq, 0, HZ);
i915_request_put(rq);
if (ret < 0) {
- drm_err(>->i915->drm, "Request with stolen guc_id failed to complete: %d\n", ret);
+ guc_err(guc, "Request with stolen guc_id failed to complete: %d\n", ret);
goto err_spin_rq;
}
/* Wait for idle */
ret = intel_gt_wait_for_idle(gt, HZ * 30);
if (ret < 0) {
- drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
+ guc_err(guc, "GT failed to idle: %d\n", ret);
goto err_spin_rq;
}
/* Verify a guc_id was stolen */
if (guc->number_guc_id_stolen == number_guc_id_stolen) {
- drm_err(>->i915->drm, "No guc_id was stolen");
+ guc_err(guc, "No guc_id was stolen\n");
ret = -EINVAL;
} else {
ret = 0;
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
index d91b58f704039..07018ec75c21f 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
@@ -45,7 +45,7 @@ static int intel_hang_guc(void *arg)
ctx = kernel_context(gt->i915, NULL);
if (IS_ERR(ctx)) {
- drm_err(>->i915->drm, "Failed get kernel context: %ld\n", PTR_ERR(ctx));
+ gt_err(gt, "Failed get kernel context: %ld\n", PTR_ERR(ctx));
return PTR_ERR(ctx);
}
@@ -54,7 +54,7 @@ static int intel_hang_guc(void *arg)
ce = intel_context_create(engine);
if (IS_ERR(ce)) {
ret = PTR_ERR(ce);
- drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
+ gt_err(gt, "Failed to create spinner request: %d\n", ret);
goto err;
}
@@ -63,13 +63,13 @@ static int intel_hang_guc(void *arg)
old_beat = engine->props.heartbeat_interval_ms;
ret = intel_engine_set_heartbeat(engine, BEAT_INTERVAL);
if (ret) {
- drm_err(>->i915->drm, "Failed to boost heatbeat interval: %d\n", ret);
+ gt_err(gt, "Failed to boost heatbeat interval: %d\n", ret);
goto err;
}
ret = igt_spinner_init(&spin, engine->gt);
if (ret) {
- drm_err(>->i915->drm, "Failed to create spinner: %d\n", ret);
+ gt_err(gt, "Failed to create spinner: %d\n", ret);
goto err;
}
@@ -77,28 +77,28 @@ static int intel_hang_guc(void *arg)
intel_context_put(ce);
if (IS_ERR(rq)) {
ret = PTR_ERR(rq);
- drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
+ gt_err(gt, "Failed to create spinner request: %d\n", ret);
goto err_spin;
}
ret = request_add_spin(rq, &spin);
if (ret) {
i915_request_put(rq);
- drm_err(>->i915->drm, "Failed to add Spinner request: %d\n", ret);
+ gt_err(gt, "Failed to add Spinner request: %d\n", ret);
goto err_spin;
}
ret = intel_reset_guc(gt);
if (ret) {
i915_request_put(rq);
- drm_err(>->i915->drm, "Failed to reset GuC, ret = %d\n", ret);
+ gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
goto err_spin;
}
guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
if (!(guc_status & GS_MIA_IN_RESET)) {
i915_request_put(rq);
- drm_err(>->i915->drm, "GuC failed to reset: status = 0x%08X\n", guc_status);
+ gt_err(gt, "GuC failed to reset: status = 0x%08X\n", guc_status);
ret = -EIO;
goto err_spin;
}
@@ -107,12 +107,12 @@ static int intel_hang_guc(void *arg)
ret = intel_selftest_wait_for_rq(rq);
i915_request_put(rq);
if (ret) {
- drm_err(>->i915->drm, "Request failed to complete: %d\n", ret);
+ gt_err(gt, "Request failed to complete: %d\n", ret);
goto err_spin;
}
if (i915_reset_count(global) == reset_count) {
- drm_err(>->i915->drm, "Failed to record a GPU reset\n");
+ gt_err(gt, "Failed to record a GPU reset\n");
ret = -EINVAL;
goto err_spin;
}
@@ -132,7 +132,7 @@ static int intel_hang_guc(void *arg)
ret = intel_selftest_wait_for_rq(rq);
i915_request_put(rq);
if (ret) {
- drm_err(>->i915->drm, "No-op failed to complete: %d\n", ret);
+ gt_err(gt, "No-op failed to complete: %d\n", ret);
goto err;
}
}
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
index d17982c36d256..04e28735a2ee6 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
@@ -115,30 +115,30 @@ static int __intel_guc_multi_lrc_basic(struct intel_gt *gt, unsigned int class)
parent = multi_lrc_create_parent(gt, class, 0);
if (IS_ERR(parent)) {
- drm_err(>->i915->drm, "Failed creating contexts: %ld", PTR_ERR(parent));
+ gt_err(gt, "Failed creating contexts: %ld", PTR_ERR(parent));
return PTR_ERR(parent);
} else if (!parent) {
- drm_dbg(>->i915->drm, "Not enough engines in class: %d", class);
+ gt_dbg(gt, "Not enough engines in class: %d", class);
return 0;
}
rq = multi_lrc_nop_request(parent);
if (IS_ERR(rq)) {
ret = PTR_ERR(rq);
- drm_err(>->i915->drm, "Failed creating requests: %d", ret);
+ gt_err(gt, "Failed creating requests: %d", ret);
goto out;
}
ret = intel_selftest_wait_for_rq(rq);
if (ret)
- drm_err(>->i915->drm, "Failed waiting on request: %d", ret);
+ gt_err(gt, "Failed waiting on request: %d", ret);
i915_request_put(rq);
if (ret >= 0) {
ret = intel_gt_wait_for_idle(gt, HZ * 5);
if (ret < 0)
- drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
+ gt_err(gt, "GT failed to idle: %d\n", ret);
}
out:
--
2.37.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH v2 3/5] drm/i915/guc: Add GuC specific debug print wrappers
@ 2022-11-18 1:58 ` John.C.Harrison
0 siblings, 0 replies; 51+ messages in thread
From: John.C.Harrison @ 2022-11-18 1:58 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
Create a set of GuC printers and start using them.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 ++++------
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++++++++++
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +--
.../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 +++++---------
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +++---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++++++-----
drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +--
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 +++++++---------
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++++++++----------
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +++++-----
.../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +++----
.../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +--
12 files changed, 179 insertions(+), 190 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 52aede324788e..d9972510ee29b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -94,8 +94,8 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
assert_rpm_wakelock_held(>->i915->runtime_pm);
spin_lock_irq(gt->irq_lock);
- WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
- gt->pm_guc_events);
+ guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
+ gt->pm_guc_events);
gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
spin_unlock_irq(gt->irq_lock);
@@ -339,7 +339,7 @@ static void guc_init_params(struct intel_guc *guc)
params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
- DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
+ guc_dbg(guc, "init param[%2d] = %#x\n", i, params[i]);
}
/*
@@ -451,7 +451,7 @@ int intel_guc_init(struct intel_guc *guc)
intel_uc_fw_fini(&guc->fw);
out:
intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
- i915_probe_error(gt->i915, "failed with %d\n", ret);
+ guc_probe_error(guc, "init failed with %d\n", ret);
return ret;
}
@@ -484,7 +484,6 @@ void intel_guc_fini(struct intel_guc *guc)
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
u32 *response_buf, u32 response_buf_size)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
u32 header;
int i;
@@ -519,8 +518,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
10, 10, &header);
if (unlikely(ret)) {
timeout:
- drm_err(&i915->drm, "mmio request %#x: no reply %x\n",
- request[0], header);
+ guc_err(guc, "mmio request %#x: no reply %x\n", request[0], header);
goto out;
}
@@ -541,8 +539,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
- drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n",
- request[0], reason);
+ guc_dbg(guc, "mmio request %#x: retrying, reason %u\n", request[0], reason);
goto retry;
}
@@ -550,16 +547,14 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
- drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n",
- request[0], error, hint);
+ guc_err(guc, "mmio request %#x: failure %x/%u\n", request[0], error, hint);
ret = -ENXIO;
goto out;
}
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) {
proto:
- drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n",
- request[0], header);
+ guc_err(guc, "mmio request %#x: unexpected reply %#x\n", request[0], header);
ret = -EPROTO;
goto out;
}
@@ -601,9 +596,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
msg = payload[0] & guc->msg_enabled_mask;
if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
- drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC crash dump notification!\n");
+ guc_err(guc, "early notification: Crash dump!\n");
if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
- drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC exception notification!\n");
+ guc_err(guc, "early notification: Exception!\n");
return 0;
}
@@ -657,7 +652,7 @@ int intel_guc_suspend(struct intel_guc *guc)
*/
ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
if (ret)
- DRM_ERROR("GuC suspend: RESET_CLIENT action failed with error %d!\n", ret);
+ guc_err(guc, "suspend: RESET_CLIENT action failed with error %d!\n", ret);
}
/* Signal that the GuC isn't running. */
@@ -832,12 +827,11 @@ static int __guc_action_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 va
static int __guc_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
int err = __guc_action_self_cfg(guc, key, len, value);
if (unlikely(err))
- i915_probe_error(i915, "Unsuccessful self-config (%pe) key %#hx value %#llx\n",
- ERR_PTR(err), key, value);
+ guc_probe_error(guc, "self-config; Unsuccessful (%pe) key %#hx value %#llx\n",
+ ERR_PTR(err), key, value);
return err;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 1bb3f98292866..8c02d22bc7e82 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -24,6 +24,41 @@
struct __guc_ads_blob;
struct intel_guc_state_capture;
+#define guc_err(_guc, _fmt, ...) \
+ gt_err(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
+
+#define guc_warn(_guc, _fmt, ...) \
+ gt_warn(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
+
+#define guc_notice(_guc, _fmt, ...) \
+ gt_notice(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
+
+#define guc_info(_guc, _fmt, ...) \
+ gt_info(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
+
+#define guc_dbg(_guc, _fmt, ...) \
+ gt_dbg(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
+
+#define guc_probe_error(_guc, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ guc_dbg(_guc, _fmt, ##__VA_ARGS__); \
+ else \
+ guc_err(_guc, _fmt, ##__VA_ARGS__); \
+ } while (0)
+
+#define guc_WARN_ON(_guc, _condition) \
+ guc_WARN(_guc, _condition, "%s", "guc_WARN_ON(" __stringify(_condition) ")")
+
+#define guc_WARN_ON_ONCE(_guc, _condition) \
+ guc_WARN_ONCE(_guc, _condition, "%s", "guc_WARN_ON_ONCE(" __stringify(_condition) ")")
+
+#define guc_WARN(_guc, _condition, _fmt, ...) \
+ gt_WARN(guc_to_gt(_guc), _condition, "GuC " _fmt, ##__VA_ARGS__)
+
+#define guc_WARN_ONCE(_guc, _condition, _fmt, ...) \
+ gt_WARN_ONCE(guc_to_gt(_guc), _condition, "GuC " _fmt, ##__VA_ARGS__)
+
/**
* struct intel_guc - Top level structure of GuC.
*
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index a7f737c4792e2..fa9a31176b4a7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -427,7 +427,7 @@ static long guc_mmio_reg_state_create(struct intel_guc *guc)
guc->ads_regset = temp_set.storage;
- drm_dbg(&guc_to_gt(guc)->i915->drm, "Used %zu KB for temporary ADS regset\n",
+ guc_dbg(guc, "used %zu KB for temporary ADS regset\n",
(temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
return total * sizeof(struct guc_mmio_reg);
@@ -621,8 +621,7 @@ static void guc_init_golden_context(struct intel_guc *guc)
engine = find_engine_state(gt, engine_class);
if (!engine) {
- drm_err(>->i915->drm, "No engine state recorded for class %d!\n",
- engine_class);
+ guc_err(guc, "No engine state recorded for class %d!\n", engine_class);
ads_blob_write(guc, ads.eng_state_size[guc_class], 0);
ads_blob_write(guc, ads.golden_context_lrca[guc_class], 0);
continue;
@@ -646,7 +645,6 @@ static int
guc_capture_prep_lists(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0;
struct guc_gt_system_info local_info;
struct iosys_map info_map;
@@ -751,7 +749,7 @@ guc_capture_prep_lists(struct intel_guc *guc)
}
if (guc->ads_capture_size && guc->ads_capture_size != PAGE_ALIGN(total_size))
- drm_warn(&i915->drm, "GuC->ADS->Capture alloc size changed from %d to %d\n",
+ guc_warn(guc, "capture alloc size changed from %d to %d\n",
guc->ads_capture_size, PAGE_ALIGN(total_size));
return PAGE_ALIGN(total_size);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 1d49a7ec0bd8f..a8876178da6ff 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -353,7 +353,6 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
u32 ipver)
{
struct intel_gt *gt = guc_to_gt(guc);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct sseu_dev_info *sseu;
int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0;
const struct __guc_mmio_reg_descr_group *list;
@@ -402,7 +401,7 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
}
}
- drm_dbg(&i915->drm, "GuC-capture found %d-ext-regs.\n", num_tot_regs);
+ guc_dbg(guc, "capture found %d ext-regs.\n", num_tot_regs);
guc->capture->extlists = extlists;
}
@@ -477,7 +476,6 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
struct guc_mmio_reg *ptr, u16 num_entries)
{
u32 i = 0, j = 0;
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists;
struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists;
const struct __guc_mmio_reg_descr_group *match;
@@ -509,8 +507,7 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
}
}
if (i < num_entries)
- drm_dbg(&i915->drm, "GuC-capture: Init reglist short %d out %d.\n",
- (int)i, (int)num_entries);
+ guc_dbg(guc, "capture: Init reglist short %d out %d.\n", i, num_entries);
return 0;
}
@@ -540,12 +537,11 @@ guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
size_t *size, bool is_purpose_est)
{
struct intel_guc_state_capture *gc = guc->capture;
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
int num_regs;
if (!gc->reglists) {
- drm_warn(&i915->drm, "GuC-capture: No reglist on this device\n");
+ guc_warn(guc, "capture: No reglist on this device\n");
return -ENODEV;
}
@@ -557,9 +553,9 @@ guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
if (!is_purpose_est && owner == GUC_CAPTURE_LIST_INDEX_PF &&
!guc_capture_get_one_list(gc->reglists, owner, type, classid)) {
if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL)
- drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist Global!\n");
+ guc_warn(guc, "capture: Missing reglist: Global!\n");
else
- drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist %s(%u):%s(%u)!\n",
+ guc_warn(guc, "capture: Missing reglist: %s(%u):%s(%u)!\n",
__stringify_type(type), type,
__stringify_engclass(classid), classid);
return -ENODATA;
@@ -592,7 +588,6 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classi
{
struct intel_guc_state_capture *gc = guc->capture;
struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct guc_debug_capture_list *listnode;
int ret, num_regs;
u8 *caplist, *tmp;
@@ -623,7 +618,7 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classi
caplist = kzalloc(size, GFP_KERNEL);
if (!caplist) {
- drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached caplist");
+ guc_dbg(guc, "capture: Failed to alloc cached caplist\n");
return -ENOMEM;
}
@@ -653,7 +648,6 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
void **outptr, size_t *size)
{
struct intel_guc_state_capture *gc = guc->capture;
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
int tmp = sizeof(u32) * 4;
void *null_header;
@@ -665,7 +659,7 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
null_header = kzalloc(tmp, GFP_KERNEL);
if (!null_header) {
- drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached nulllist");
+ guc_dbg(guc, "capture: Failed to alloc cached null list\n");
return -ENOMEM;
}
@@ -727,7 +721,6 @@ guc_capture_output_min_size_est(struct intel_guc *guc)
static void check_guc_capture_size(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
int min_size = guc_capture_output_min_size_est(guc);
int spare_size = min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER;
u32 buffer_size = intel_guc_log_section_size_capture(&guc->log);
@@ -741,13 +734,13 @@ static void check_guc_capture_size(struct intel_guc *guc)
* INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE.
*/
if (min_size < 0)
- drm_warn(&i915->drm, "Failed to calculate GuC error state capture buffer minimum size: %d!\n",
+ guc_warn(guc, "error state capture buffer minimum size calculation failed: %d!\n",
min_size);
else if (min_size > buffer_size)
- drm_warn(&i915->drm, "GuC error state capture buffer maybe small: %d < %d\n",
+ guc_warn(guc, "error state capture buffer maybe small: %d < %d\n",
buffer_size, min_size);
else if (spare_size > buffer_size)
- drm_dbg(&i915->drm, "GuC error state capture buffer lacks spare size: %d < %d (min = %d)\n",
+ guc_dbg(guc, "error state capture buffer lacks spare size: %d < %d (min = %d)\n",
buffer_size, spare_size, min_size);
}
@@ -848,7 +841,6 @@ static int
guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *buf,
u32 *dw)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
int tries = 2;
int avail = 0;
u32 *src_data;
@@ -865,7 +857,7 @@ guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *
return 4;
}
if (avail)
- drm_dbg(&i915->drm, "GuC-Cap-Logs not dword aligned, skipping.\n");
+ guc_dbg(guc, "capture: Log not dword aligned, skipping.\n");
buf->rd = 0;
}
@@ -1118,13 +1110,12 @@ static void
__guc_capture_create_prealloc_nodes(struct intel_guc *guc)
{
struct __guc_capture_parsed_output *node = NULL;
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
int i;
for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) {
node = guc_capture_alloc_one_node(guc);
if (!node) {
- drm_warn(&i915->drm, "GuC Capture pre-alloc-cache failure\n");
+ guc_warn(guc, "capture pre-alloc-cache failure\n");
/* dont free the priors, use what we got and cleanup at shutdown */
return;
}
@@ -1169,7 +1160,6 @@ guc_capture_create_prealloc_nodes(struct intel_guc *guc)
static int
guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstate *buf)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct guc_state_capture_group_header_t ghdr = {0};
struct guc_state_capture_header_t hdr = {0};
struct __guc_capture_parsed_output *node = NULL;
@@ -1183,7 +1173,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
if (!i)
return -ENODATA;
if (i % sizeof(u32)) {
- drm_warn(&i915->drm, "GuC Capture new entries unaligned\n");
+ guc_warn(guc, "capture new entries unaligned\n");
ret = -EIO;
goto bailout;
}
@@ -1301,8 +1291,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
break;
}
if (datatype != GUC_CAPTURE_LIST_TYPE_GLOBAL)
- drm_dbg(&i915->drm, "GuC Capture missing global dump: %08x!\n",
- datatype);
+ guc_dbg(guc, "cpture missing global dump: %08x!\n", datatype);
}
node->is_partial = is_partial;
node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner);
@@ -1322,7 +1311,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios);
if (numregs > guc->capture->max_mmio_per_node) {
- drm_dbg(&i915->drm, "GuC Capture list extraction clipped by prealloc!\n");
+ guc_dbg(guc, "capture list extraction clipped by prealloc!\n");
numregs = guc->capture->max_mmio_per_node;
}
node->reginfo[datatype].num_regs = numregs;
@@ -1367,7 +1356,6 @@ static void __guc_capture_process_output(struct intel_guc *guc)
{
unsigned int buffer_size, read_offset, write_offset, full_count;
struct intel_uc *uc = container_of(guc, typeof(*uc), guc);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct guc_log_buffer_state log_buf_state_local;
struct guc_log_buffer_state *log_buf_state;
struct __guc_capture_bufstate buf;
@@ -1403,7 +1391,7 @@ static void __guc_capture_process_output(struct intel_guc *guc)
write_offset = buffer_size;
} else if (unlikely((read_offset > buffer_size) ||
(write_offset > buffer_size))) {
- drm_err(&i915->drm, "invalid GuC log capture buffer state!\n");
+ guc_err(guc, "capture: invalid buffer state!\n");
/* copy whole buffer as offsets are unreliable */
read_offset = 0;
write_offset = buffer_size;
@@ -1586,13 +1574,11 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
struct intel_context *ce)
{
struct __guc_capture_parsed_output *n, *ntmp;
- struct drm_i915_private *i915;
struct intel_guc *guc;
if (!gt || !ee || !ce)
return;
- i915 = gt->i915;
guc = >->uc.guc;
if (!guc->capture)
return;
@@ -1615,7 +1601,7 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
return;
}
}
- drm_dbg(&i915->drm, "GuC capture can't match ee to node\n");
+ guc_dbg(guc, "capture can't match ee to node\n");
}
void intel_guc_capture_process(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 5b86b2e286e07..4a2811aa3d5e1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -103,8 +103,9 @@ static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
return uk_val == INTEL_GUC_LOAD_STATUS_READY;
}
-static int guc_wait_ucode(struct intel_uncore *uncore)
+static int guc_wait_ucode(struct intel_gt *gt)
{
+ struct intel_uncore *uncore = gt->uncore;
u32 status;
int ret;
@@ -127,12 +128,8 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
*/
ret = wait_for(guc_ready(uncore, &status), 200);
if (ret) {
- struct drm_device *drm = &uncore->i915->drm;
-
- drm_info(drm, "GuC load failed: status = 0x%08X\n", status);
- drm_info(drm, "GuC load failed: status: Reset = %d, "
- "BootROM = 0x%02X, UKernel = 0x%02X, "
- "MIA = 0x%02X, Auth = 0x%02X\n",
+ gt_info(gt, "GuC load failed: status = 0x%08X\n", status);
+ gt_info(gt, "GuC load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n",
REG_FIELD_GET(GS_MIA_IN_RESET, status),
REG_FIELD_GET(GS_BOOTROM_MASK, status),
REG_FIELD_GET(GS_UKERNEL_MASK, status),
@@ -140,13 +137,13 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
- drm_info(drm, "GuC firmware signature verification failed\n");
+ gt_info(gt, "GuC firmware signature verification failed\n");
ret = -ENOEXEC;
}
if (REG_FIELD_GET(GS_UKERNEL_MASK, status) == INTEL_GUC_LOAD_STATUS_EXCEPTION) {
- drm_info(drm, "GuC firmware exception. EIP: %#x\n",
- intel_uncore_read(uncore, SOFT_SCRATCH(13)));
+ gt_info(gt, "GuC firmware exception. EIP: %#x\n",
+ intel_uncore_read(uncore, SOFT_SCRATCH(13)));
ret = -ENXIO;
}
}
@@ -194,7 +191,7 @@ int intel_guc_fw_upload(struct intel_guc *guc)
if (ret)
goto out;
- ret = guc_wait_ucode(uncore);
+ ret = guc_wait_ucode(gt);
if (ret)
goto out;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 68331c538b0a7..8c9a020700b52 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -39,7 +39,6 @@ struct guc_log_section {
static void _guc_log_init_sizes(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
static const struct guc_log_section sections[GUC_LOG_SECTIONS_LIMIT] = {
{
GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT,
@@ -82,12 +81,12 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
}
if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units))
- drm_err(&i915->drm, "Mis-aligned GuC log %s size: 0x%X vs 0x%X!",
+ guc_err(guc, "log: Mis-aligned %s size: 0x%X vs 0x%X!\n",
sections[i].name, log->sizes[i].bytes, log->sizes[i].units);
log->sizes[i].count = log->sizes[i].bytes / log->sizes[i].units;
if (!log->sizes[i].count) {
- drm_err(&i915->drm, "Zero GuC log %s size!", sections[i].name);
+ guc_err(guc, "log: zero %s size!\n", sections[i].name);
} else {
/* Size is +1 unit */
log->sizes[i].count--;
@@ -95,14 +94,14 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
/* Clip to field size */
if (log->sizes[i].count > sections[i].max) {
- drm_err(&i915->drm, "GuC log %s size too large: %d vs %d!",
+ guc_err(guc, "log: %s size too large: %d vs %d!\n",
sections[i].name, log->sizes[i].count + 1, sections[i].max + 1);
log->sizes[i].count = sections[i].max;
}
}
if (log->sizes[GUC_LOG_SECTIONS_CRASH].units != log->sizes[GUC_LOG_SECTIONS_DEBUG].units) {
- drm_err(&i915->drm, "Unit mis-match for GuC log crash and debug sections: %d vs %d!",
+ guc_err(guc, "log: Unit mis-match for crash and debug sections: %d vs %d!\n",
log->sizes[GUC_LOG_SECTIONS_CRASH].units,
log->sizes[GUC_LOG_SECTIONS_DEBUG].units);
log->sizes[GUC_LOG_SECTIONS_CRASH].units = log->sizes[GUC_LOG_SECTIONS_DEBUG].units;
@@ -383,7 +382,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
mutex_lock(&log->relay.lock);
- if (WARN_ON(!intel_guc_log_relay_created(log)))
+ if (guc_WARN_ON(log_to_guc(log), !intel_guc_log_relay_created(log)))
goto out_unlock;
/* Get the pointer to shared GuC log buffer */
@@ -451,7 +450,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
write_offset = buffer_size;
} else if (unlikely((read_offset > buffer_size) ||
(write_offset > buffer_size))) {
- DRM_ERROR("invalid log buffer state\n");
+ guc_err(log_to_guc(log), "log: invalid buffer state\n");
/* copy whole buffer as offsets are unreliable */
read_offset = 0;
write_offset = buffer_size;
@@ -520,7 +519,7 @@ void intel_guc_log_init_early(struct intel_guc_log *log)
static int guc_log_relay_create(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
+ struct intel_gt *gt = guc_to_gt(guc);
struct rchan *guc_log_relay_chan;
size_t n_subbufs, subbuf_size;
int ret;
@@ -543,11 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log *log)
n_subbufs = 8;
guc_log_relay_chan = relay_open("guc_log",
- dev_priv->drm.primary->debugfs_root,
+ gt->i915->drm.primary->debugfs_root,
subbuf_size, n_subbufs,
- &relay_callbacks, dev_priv);
+ &relay_callbacks, gt->i915);
if (!guc_log_relay_chan) {
- DRM_ERROR("Couldn't create relay chan for GuC logging\n");
+ guc_err(guc, "log: Failed to create relay chan\n");
ret = -ENOMEM;
return ret;
@@ -596,7 +595,7 @@ static u32 __get_default_log_level(struct intel_guc_log *log)
}
if (i915->params.guc_log_level > GUC_LOG_LEVEL_MAX) {
- DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
+ guc_warn(guc, "log: Incompatible options detected: %s=%d, %s!\n",
"guc_log_level", i915->params.guc_log_level,
"verbosity too high");
return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
@@ -641,15 +640,15 @@ int intel_guc_log_create(struct intel_guc_log *log)
log->buf_addr = vaddr;
log->level = __get_default_log_level(log);
- DRM_DEBUG_DRIVER("guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
- log->level, str_enabled_disabled(log->level),
- str_yes_no(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
- GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
+ guc_dbg(guc, "guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
+ log->level, str_enabled_disabled(log->level),
+ str_yes_no(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
+ GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
return 0;
err:
- DRM_ERROR("Failed to allocate or map GuC log buffer. %d\n", ret);
+ guc_err(guc, "log: Failed to allocate or map buffer: %d\n", ret);
return ret;
}
@@ -687,7 +686,7 @@ int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)
GUC_LOG_LEVEL_IS_ENABLED(level),
GUC_LOG_LEVEL_TO_VERBOSITY(level));
if (ret) {
- DRM_DEBUG_DRIVER("guc_log_control action failed %d\n", ret);
+ guc_dbg(guc, "guc_log_control action failed %d\n", ret);
goto out_unlock;
}
@@ -905,7 +904,7 @@ int intel_guc_log_dump(struct intel_guc_log *log, struct drm_printer *p,
map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
if (IS_ERR(map)) {
- DRM_DEBUG("Failed to pin object\n");
+ guc_dbg(guc, "log: Failed to pin buffer object\n");
drm_puts(p, "(log data unaccessible)\n");
free_page((unsigned long)page);
return PTR_ERR(map);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
index b5855091cf6a9..62f3b97111f64 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
@@ -70,13 +70,12 @@ static int __guc_rc_control(struct intel_guc *guc, bool enable)
ret = guc_action_control_gucrc(guc, enable);
if (ret) {
- i915_probe_error(guc_to_gt(guc)->i915, "Failed to %s GuC RC (%pe)\n",
- str_enable_disable(enable), ERR_PTR(ret));
+ guc_probe_error(guc, "RC: Failed to %s: %pe\n",
+ str_enable_disable(enable), ERR_PTR(ret));
return ret;
}
- drm_info(>->i915->drm, "GuC RC: %s\n",
- str_enabled_disabled(enable));
+ guc_info(guc, "RC %s\n", str_enabled_disabled(enable));
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 63464933cbceb..b9ef0b4a123e1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -171,14 +171,12 @@ static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
static int slpc_query_task_state(struct intel_guc_slpc *slpc)
{
struct intel_guc *guc = slpc_to_guc(slpc);
- struct drm_i915_private *i915 = slpc_to_i915(slpc);
u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
int ret;
ret = guc_action_slpc_query(guc, offset);
if (unlikely(ret))
- i915_probe_error(i915, "Failed to query task state (%pe)\n",
- ERR_PTR(ret));
+ guc_probe_error(guc, "SLPC: Failed to query task state (%pe)\n", ERR_PTR(ret));
drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
@@ -188,15 +186,14 @@ static int slpc_query_task_state(struct intel_guc_slpc *slpc)
static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
{
struct intel_guc *guc = slpc_to_guc(slpc);
- struct drm_i915_private *i915 = slpc_to_i915(slpc);
int ret;
GEM_BUG_ON(id >= SLPC_MAX_PARAM);
ret = guc_action_slpc_set_param(guc, id, value);
if (ret)
- i915_probe_error(i915, "Failed to set param %d to %u (%pe)\n",
- id, value, ERR_PTR(ret));
+ guc_probe_error(guc, "SLPC: Failed to set param %d to %u (%pe)\n",
+ id, value, ERR_PTR(ret));
return ret;
}
@@ -236,8 +233,7 @@ static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
freq);
if (ret)
- drm_notice(&i915->drm,
- "Failed to send set_param for min freq(%d): (%d)\n",
+ guc_notice(guc, "SLPC: Failed to send set_param for min freq(%d): (%d)\n",
freq, ret);
}
@@ -267,7 +263,6 @@ static void slpc_boost_work(struct work_struct *work)
int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
{
struct intel_guc *guc = slpc_to_guc(slpc);
- struct drm_i915_private *i915 = slpc_to_i915(slpc);
u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
int err;
@@ -275,9 +270,8 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&slpc->vaddr);
if (unlikely(err)) {
- i915_probe_error(i915,
- "Failed to allocate SLPC struct (err=%pe)\n",
- ERR_PTR(err));
+ guc_probe_error(guc, "SLPC: Failed to allocate SLPC struct (err=%pe)\n",
+ ERR_PTR(err));
return err;
}
@@ -338,7 +332,6 @@ static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset)
static int slpc_reset(struct intel_guc_slpc *slpc)
{
- struct drm_i915_private *i915 = slpc_to_i915(slpc);
struct intel_guc *guc = slpc_to_guc(slpc);
u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
int ret;
@@ -346,15 +339,14 @@ static int slpc_reset(struct intel_guc_slpc *slpc)
ret = guc_action_slpc_reset(guc, offset);
if (unlikely(ret < 0)) {
- i915_probe_error(i915, "SLPC reset action failed (%pe)\n",
- ERR_PTR(ret));
+ guc_probe_error(guc, "SLPC: Reset action failed (%pe)\n", ERR_PTR(ret));
return ret;
}
if (!ret) {
if (wait_for(slpc_is_running(slpc), SLPC_RESET_TIMEOUT_MS)) {
- i915_probe_error(i915, "SLPC not enabled! State = %s\n",
- slpc_get_state_string(slpc));
+ guc_probe_error(guc, "SLPC: Not enabled! State = %s\n",
+ slpc_get_state_string(slpc));
return -EIO;
}
}
@@ -495,8 +487,8 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
val < slpc->rp1_freq);
if (ret) {
- i915_probe_error(i915, "Failed to toggle efficient freq (%pe)\n",
- ERR_PTR(ret));
+ guc_probe_error(slpc_to_guc(slpc), "SLPC: Failed to toggle efficient freq (%pe)\n",
+ ERR_PTR(ret));
goto out;
}
@@ -611,15 +603,12 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
{
- struct drm_i915_private *i915 = slpc_to_i915(slpc);
int slpc_min_freq;
int ret;
ret = intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq);
if (ret) {
- drm_err(&i915->drm,
- "Failed to get min freq: (%d)\n",
- ret);
+ guc_err(slpc_to_guc(slpc), "SLPC: Failed to get min freq: (%d)\n", ret);
return false;
}
@@ -685,8 +674,7 @@ int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode)
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
ret = slpc_set_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
if (ret)
- drm_err(&i915->drm,
- "Override gucrc mode %d failed %d\n",
+ guc_err(slpc_to_guc(slpc), "SLPC: Override gucrc mode %d failed %d\n",
mode, ret);
}
@@ -702,9 +690,7 @@ int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
ret = slpc_unset_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE);
if (ret)
- drm_err(&i915->drm,
- "Unsetting gucrc mode failed %d\n",
- ret);
+ guc_err(slpc_to_guc(slpc), "SLPC: Unsetting gucrc mode failed %d\n", ret);
}
return ret;
@@ -726,6 +712,7 @@ int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
{
struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ struct intel_guc *guc = slpc_to_guc(slpc);
int ret;
GEM_BUG_ON(!slpc->vma);
@@ -734,8 +721,8 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
ret = slpc_reset(slpc);
if (unlikely(ret < 0)) {
- i915_probe_error(i915, "SLPC Reset event returned (%pe)\n",
- ERR_PTR(ret));
+ guc_probe_error(guc, "SLPC: Reset event returned (%pe)\n",
+ ERR_PTR(ret));
return ret;
}
@@ -753,16 +740,16 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
/* Set SLPC max limit to RP0 */
ret = slpc_use_fused_rp0(slpc);
if (unlikely(ret)) {
- i915_probe_error(i915, "Failed to set SLPC max to RP0 (%pe)\n",
- ERR_PTR(ret));
+ guc_probe_error(guc, "SLPC: Failed to set max to RP0 (%pe)\n",
+ ERR_PTR(ret));
return ret;
}
/* Revert SLPC min/max to softlimits if necessary */
ret = slpc_set_softlimits(slpc);
if (unlikely(ret)) {
- i915_probe_error(i915, "Failed to set SLPC softlimits (%pe)\n",
- ERR_PTR(ret));
+ guc_probe_error(guc, "SLPC: Failed to set softlimits (%pe)\n",
+ ERR_PTR(ret));
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0a42f1807f52c..da8ab18aa4ce7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1443,8 +1443,7 @@ static void guc_init_engine_stats(struct intel_guc *guc)
int ret = guc_action_enable_usage_stats(guc);
if (ret)
- drm_err(>->i915->drm,
- "Failed to enable usage stats: %d!\n", ret);
+ guc_err(guc, "Failed to enable usage stats: %d!\n", ret);
}
}
@@ -3584,8 +3583,7 @@ static int guc_request_alloc(struct i915_request *rq)
intel_context_sched_disable_unpin(ce);
else if (intel_context_is_closed(ce))
if (wait_for(context_close_done(ce), 1500))
- drm_warn(&guc_to_gt(guc)->i915->drm,
- "timed out waiting on context sched close before realloc\n");
+ guc_warn(guc, "timed out waiting on context sched close before realloc\n");
/*
* Call pin_guc_id here rather than in the pinning step as with
* dma_resv, contexts can be repeatedly pinned / unpinned trashing the
@@ -4350,7 +4348,7 @@ static int __guc_action_set_scheduling_policies(struct intel_guc *guc,
return ret;
if (ret != policy->count) {
- drm_warn(&guc_to_gt(guc)->i915->drm, "GuC global scheduler policy processed %d of %d KLVs!",
+ guc_warn(guc, "H2G: global scheduler policy processed %d of %d KLVs!\n",
ret, policy->count);
if (ret > policy->count)
return -EPROTO;
@@ -4383,9 +4381,9 @@ static int guc_init_global_schedule_policy(struct intel_guc *guc)
ret = __guc_action_set_scheduling_policies(guc, &policy);
if (ret)
- i915_probe_error(gt->i915,
- "Failed to configure global scheduling policies: %pe!\n",
- ERR_PTR(ret));
+ guc_probe_error(guc,
+ "Failed to configure global scheduling policies: %pe!\n",
+ ERR_PTR(ret));
}
return ret;
@@ -4484,21 +4482,18 @@ g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)
struct intel_context *ce;
if (unlikely(ctx_id >= GUC_MAX_CONTEXT_ID)) {
- drm_err(&guc_to_gt(guc)->i915->drm,
- "Invalid ctx_id %u\n", ctx_id);
+ guc_err(guc, "Invalid ctx_id %u\n", ctx_id);
return NULL;
}
ce = __get_context(guc, ctx_id);
if (unlikely(!ce)) {
- drm_err(&guc_to_gt(guc)->i915->drm,
- "Context is NULL, ctx_id %u\n", ctx_id);
+ guc_err(guc, "Context is NULL, ctx_id %u\n", ctx_id);
return NULL;
}
if (unlikely(intel_context_is_child(ce))) {
- drm_err(&guc_to_gt(guc)->i915->drm,
- "Context is child, ctx_id %u\n", ctx_id);
+ guc_err(guc, "Context is child, ctx_id %u\n", ctx_id);
return NULL;
}
@@ -4513,7 +4508,7 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
u32 ctx_id;
if (unlikely(len < 1)) {
- drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
+ guc_err(guc, "notification: Invalid length %u for deregister done\n", len);
return -EPROTO;
}
ctx_id = msg[0];
@@ -4565,7 +4560,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
u32 ctx_id;
if (unlikely(len < 2)) {
- drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
+ guc_err(guc, "notification: Invalid length %u for sched done\n", len);
return -EPROTO;
}
ctx_id = msg[0];
@@ -4577,8 +4572,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
if (unlikely(context_destroyed(ce) ||
(!context_pending_enable(ce) &&
!context_pending_disable(ce)))) {
- drm_err(&guc_to_gt(guc)->i915->drm,
- "Bad context sched_state 0x%x, ctx_id %u\n",
+ guc_err(guc, "notification: Bad context sched_state 0x%x, ctx_id %u\n",
ce->guc_state.sched_state, ctx_id);
return -EPROTO;
}
@@ -4666,8 +4660,8 @@ static void guc_handle_context_reset(struct intel_guc *guc,
capture_error_state(guc, ce);
guc_context_replay(ce);
} else {
- drm_info(&guc_to_gt(guc)->i915->drm,
- "Ignoring context reset notification of exiting context 0x%04X on %s",
+ guc_info(guc,
+ "Ignoring context reset notification of exiting context 0x%04X on %s\n",
ce->guc_id.id, ce->engine->name);
}
}
@@ -4680,7 +4674,7 @@ int intel_guc_context_reset_process_msg(struct intel_guc *guc,
int ctx_id;
if (unlikely(len != 1)) {
- drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
+ guc_err(guc, "notification: Invalid length %u for context reset\n", len);
return -EPROTO;
}
@@ -4713,13 +4707,13 @@ int intel_guc_error_capture_process_msg(struct intel_guc *guc,
u32 status;
if (unlikely(len != 1)) {
- drm_dbg(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
+ guc_err(guc, "notification: Invalid length %u for error capture\n", len);
return -EPROTO;
}
status = msg[0] & INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK;
if (status == INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE)
- drm_warn(&guc_to_gt(guc)->i915->drm, "G2H-Error capture no space");
+ guc_warn(guc, "notification: Error capture buffer overflow\n");
intel_guc_capture_process(guc);
@@ -4762,13 +4756,12 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
const u32 *msg, u32 len)
{
struct intel_engine_cs *engine;
- struct intel_gt *gt = guc_to_gt(guc);
u8 guc_class, instance;
u32 reason;
unsigned long flags;
if (unlikely(len != 3)) {
- drm_err(>->i915->drm, "Invalid length %u", len);
+ guc_err(guc, "notification: Invalid length %u for engine failure\n", len);
return -EPROTO;
}
@@ -4778,8 +4771,8 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
engine = intel_guc_lookup_engine(guc, guc_class, instance);
if (unlikely(!engine)) {
- drm_err(>->i915->drm,
- "Invalid engine %d:%d", guc_class, instance);
+ guc_err(guc, "notification: Invalid engine %d:%d for engine failure\n",
+ guc_class, instance);
return -EPROTO;
}
@@ -4787,7 +4780,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
* This is an unexpected failure of a hardware feature. So, log a real
* error message not just the informational that comes with the reset.
*/
- drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X",
+ guc_err(guc, "notification: Engine reset request failed on %d:%d (%s) because 0x%08X\n",
guc_class, instance, engine->name, reason);
spin_lock_irqsave(&guc->submission_state.lock, flags);
@@ -5297,6 +5290,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
unsigned long flags)
{
struct guc_virtual_engine *ve;
+ struct intel_gt *gt;
struct intel_guc *guc;
unsigned int n;
int err;
@@ -5305,10 +5299,11 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
if (!ve)
return ERR_PTR(-ENOMEM);
- guc = &siblings[0]->gt->uc.guc;
+ gt = siblings[0]->gt;
+ guc = >->uc.guc;
ve->base.i915 = siblings[0]->i915;
- ve->base.gt = siblings[0]->gt;
+ ve->base.gt = gt;
ve->base.uncore = siblings[0]->uncore;
ve->base.id = -1;
@@ -5336,8 +5331,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
GEM_BUG_ON(!is_power_of_2(sibling->mask));
if (sibling->mask & ve->base.mask) {
- DRM_DEBUG("duplicate %s entry in load balancer\n",
- sibling->name);
+ guc_dbg(guc, "Duplicate %s entry in load balancer\n", sibling->name);
err = -EINVAL;
goto err_put;
}
@@ -5346,8 +5340,8 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
ve->base.logical_mask |= sibling->logical_mask;
if (n != 0 && ve->base.class != sibling->class) {
- DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n",
- sibling->class, ve->base.class);
+ guc_dbg(guc, "Invalid mixing of engine class, sibling %d, already %d\n",
+ sibling->class, ve->base.class);
err = -EINVAL;
goto err_put;
} else if (n == 0) {
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
index e28518fe8b908..d588c32d65c54 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
@@ -65,7 +65,7 @@ static int intel_guc_scrub_ctbs(void *arg)
ce = intel_context_create(engine);
if (IS_ERR(ce)) {
ret = PTR_ERR(ce);
- drm_err(>->i915->drm, "Failed to create context, %d: %d\n", i, ret);
+ gt_err(gt, "Failed to create context, %d: %d\n", i, ret);
goto err;
}
@@ -86,7 +86,7 @@ static int intel_guc_scrub_ctbs(void *arg)
if (IS_ERR(rq)) {
ret = PTR_ERR(rq);
- drm_err(>->i915->drm, "Failed to create request, %d: %d\n", i, ret);
+ gt_err(gt, "Failed to create request, %d: %d\n", i, ret);
goto err;
}
@@ -96,7 +96,7 @@ static int intel_guc_scrub_ctbs(void *arg)
for (i = 0; i < 3; ++i) {
ret = i915_request_wait(last[i], 0, HZ);
if (ret < 0) {
- drm_err(>->i915->drm, "Last request failed to complete: %d\n", ret);
+ gt_err(gt, "Last request failed to complete: %d\n", ret);
goto err;
}
i915_request_put(last[i]);
@@ -113,7 +113,7 @@ static int intel_guc_scrub_ctbs(void *arg)
/* GT will not idle if G2H are lost */
ret = intel_gt_wait_for_idle(gt, HZ);
if (ret < 0) {
- drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
+ gt_err(gt, "GT failed to idle: %d\n", ret);
goto err;
}
@@ -153,7 +153,7 @@ static int intel_guc_steal_guc_ids(void *arg)
ce = kcalloc(GUC_MAX_CONTEXT_ID, sizeof(*ce), GFP_KERNEL);
if (!ce) {
- drm_err(>->i915->drm, "Context array allocation failed\n");
+ guc_err(guc, "Context array allocation failed\n");
return -ENOMEM;
}
@@ -167,24 +167,24 @@ static int intel_guc_steal_guc_ids(void *arg)
if (IS_ERR(ce[context_index])) {
ret = PTR_ERR(ce[context_index]);
ce[context_index] = NULL;
- drm_err(>->i915->drm, "Failed to create context: %d\n", ret);
+ guc_err(guc, "Failed to create context: %d\n", ret);
goto err_wakeref;
}
ret = igt_spinner_init(&spin, engine->gt);
if (ret) {
- drm_err(>->i915->drm, "Failed to create spinner: %d\n", ret);
+ guc_err(guc, "Failed to create spinner: %d\n", ret);
goto err_contexts;
}
spin_rq = igt_spinner_create_request(&spin, ce[context_index],
MI_ARB_CHECK);
if (IS_ERR(spin_rq)) {
ret = PTR_ERR(spin_rq);
- drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
+ guc_err(guc, "Failed to create spinner request: %d\n", ret);
goto err_contexts;
}
ret = request_add_spin(spin_rq, &spin);
if (ret) {
- drm_err(>->i915->drm, "Failed to add Spinner request: %d\n", ret);
+ guc_err(guc, "Failed to add Spinner request: %d\n", ret);
goto err_spin_rq;
}
@@ -194,7 +194,7 @@ static int intel_guc_steal_guc_ids(void *arg)
if (IS_ERR(ce[context_index])) {
ret = PTR_ERR(ce[context_index--]);
ce[context_index] = NULL;
- drm_err(>->i915->drm, "Failed to create context: %d\n", ret);
+ guc_err(guc, "Failed to create context: %d\n", ret);
goto err_spin_rq;
}
@@ -203,7 +203,7 @@ static int intel_guc_steal_guc_ids(void *arg)
ret = PTR_ERR(rq);
rq = NULL;
if (ret != -EAGAIN) {
- drm_err(>->i915->drm, "Failed to create request, %d: %d\n",
+ guc_err(guc, "Failed to create request, %d: %d\n",
context_index, ret);
goto err_spin_rq;
}
@@ -218,7 +218,7 @@ static int intel_guc_steal_guc_ids(void *arg)
igt_spinner_end(&spin);
ret = intel_selftest_wait_for_rq(spin_rq);
if (ret) {
- drm_err(>->i915->drm, "Spin request failed to complete: %d\n", ret);
+ guc_err(guc, "Spin request failed to complete: %d\n", ret);
i915_request_put(last);
goto err_spin_rq;
}
@@ -230,7 +230,7 @@ static int intel_guc_steal_guc_ids(void *arg)
ret = i915_request_wait(last, 0, HZ * 30);
i915_request_put(last);
if (ret < 0) {
- drm_err(>->i915->drm, "Last request failed to complete: %d\n", ret);
+ guc_err(guc, "Last request failed to complete: %d\n", ret);
goto err_spin_rq;
}
@@ -238,7 +238,7 @@ static int intel_guc_steal_guc_ids(void *arg)
rq = nop_user_request(ce[context_index], NULL);
if (IS_ERR(rq)) {
ret = PTR_ERR(rq);
- drm_err(>->i915->drm, "Failed to steal guc_id, %d: %d\n", context_index, ret);
+ guc_err(guc, "Failed to steal guc_id, %d: %d\n", context_index, ret);
goto err_spin_rq;
}
@@ -246,20 +246,20 @@ static int intel_guc_steal_guc_ids(void *arg)
ret = i915_request_wait(rq, 0, HZ);
i915_request_put(rq);
if (ret < 0) {
- drm_err(>->i915->drm, "Request with stolen guc_id failed to complete: %d\n", ret);
+ guc_err(guc, "Request with stolen guc_id failed to complete: %d\n", ret);
goto err_spin_rq;
}
/* Wait for idle */
ret = intel_gt_wait_for_idle(gt, HZ * 30);
if (ret < 0) {
- drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
+ guc_err(guc, "GT failed to idle: %d\n", ret);
goto err_spin_rq;
}
/* Verify a guc_id was stolen */
if (guc->number_guc_id_stolen == number_guc_id_stolen) {
- drm_err(>->i915->drm, "No guc_id was stolen");
+ guc_err(guc, "No guc_id was stolen\n");
ret = -EINVAL;
} else {
ret = 0;
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
index d91b58f704039..07018ec75c21f 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
@@ -45,7 +45,7 @@ static int intel_hang_guc(void *arg)
ctx = kernel_context(gt->i915, NULL);
if (IS_ERR(ctx)) {
- drm_err(>->i915->drm, "Failed get kernel context: %ld\n", PTR_ERR(ctx));
+ gt_err(gt, "Failed get kernel context: %ld\n", PTR_ERR(ctx));
return PTR_ERR(ctx);
}
@@ -54,7 +54,7 @@ static int intel_hang_guc(void *arg)
ce = intel_context_create(engine);
if (IS_ERR(ce)) {
ret = PTR_ERR(ce);
- drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
+ gt_err(gt, "Failed to create spinner request: %d\n", ret);
goto err;
}
@@ -63,13 +63,13 @@ static int intel_hang_guc(void *arg)
old_beat = engine->props.heartbeat_interval_ms;
ret = intel_engine_set_heartbeat(engine, BEAT_INTERVAL);
if (ret) {
- drm_err(>->i915->drm, "Failed to boost heatbeat interval: %d\n", ret);
+ gt_err(gt, "Failed to boost heatbeat interval: %d\n", ret);
goto err;
}
ret = igt_spinner_init(&spin, engine->gt);
if (ret) {
- drm_err(>->i915->drm, "Failed to create spinner: %d\n", ret);
+ gt_err(gt, "Failed to create spinner: %d\n", ret);
goto err;
}
@@ -77,28 +77,28 @@ static int intel_hang_guc(void *arg)
intel_context_put(ce);
if (IS_ERR(rq)) {
ret = PTR_ERR(rq);
- drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
+ gt_err(gt, "Failed to create spinner request: %d\n", ret);
goto err_spin;
}
ret = request_add_spin(rq, &spin);
if (ret) {
i915_request_put(rq);
- drm_err(>->i915->drm, "Failed to add Spinner request: %d\n", ret);
+ gt_err(gt, "Failed to add Spinner request: %d\n", ret);
goto err_spin;
}
ret = intel_reset_guc(gt);
if (ret) {
i915_request_put(rq);
- drm_err(>->i915->drm, "Failed to reset GuC, ret = %d\n", ret);
+ gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
goto err_spin;
}
guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
if (!(guc_status & GS_MIA_IN_RESET)) {
i915_request_put(rq);
- drm_err(>->i915->drm, "GuC failed to reset: status = 0x%08X\n", guc_status);
+ gt_err(gt, "GuC failed to reset: status = 0x%08X\n", guc_status);
ret = -EIO;
goto err_spin;
}
@@ -107,12 +107,12 @@ static int intel_hang_guc(void *arg)
ret = intel_selftest_wait_for_rq(rq);
i915_request_put(rq);
if (ret) {
- drm_err(>->i915->drm, "Request failed to complete: %d\n", ret);
+ gt_err(gt, "Request failed to complete: %d\n", ret);
goto err_spin;
}
if (i915_reset_count(global) == reset_count) {
- drm_err(>->i915->drm, "Failed to record a GPU reset\n");
+ gt_err(gt, "Failed to record a GPU reset\n");
ret = -EINVAL;
goto err_spin;
}
@@ -132,7 +132,7 @@ static int intel_hang_guc(void *arg)
ret = intel_selftest_wait_for_rq(rq);
i915_request_put(rq);
if (ret) {
- drm_err(>->i915->drm, "No-op failed to complete: %d\n", ret);
+ gt_err(gt, "No-op failed to complete: %d\n", ret);
goto err;
}
}
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
index d17982c36d256..04e28735a2ee6 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
@@ -115,30 +115,30 @@ static int __intel_guc_multi_lrc_basic(struct intel_gt *gt, unsigned int class)
parent = multi_lrc_create_parent(gt, class, 0);
if (IS_ERR(parent)) {
- drm_err(>->i915->drm, "Failed creating contexts: %ld", PTR_ERR(parent));
+ gt_err(gt, "Failed creating contexts: %ld", PTR_ERR(parent));
return PTR_ERR(parent);
} else if (!parent) {
- drm_dbg(>->i915->drm, "Not enough engines in class: %d", class);
+ gt_dbg(gt, "Not enough engines in class: %d", class);
return 0;
}
rq = multi_lrc_nop_request(parent);
if (IS_ERR(rq)) {
ret = PTR_ERR(rq);
- drm_err(>->i915->drm, "Failed creating requests: %d", ret);
+ gt_err(gt, "Failed creating requests: %d", ret);
goto out;
}
ret = intel_selftest_wait_for_rq(rq);
if (ret)
- drm_err(>->i915->drm, "Failed waiting on request: %d", ret);
+ gt_err(gt, "Failed waiting on request: %d", ret);
i915_request_put(rq);
if (ret >= 0) {
ret = intel_gt_wait_for_idle(gt, HZ * 5);
if (ret < 0)
- drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
+ gt_err(gt, "GT failed to idle: %d\n", ret);
}
out:
--
2.37.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v2 3/5] drm/i915/guc: Add GuC specific debug print wrappers
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
@ 2022-11-22 17:42 ` Michal Wajdeczko
-1 siblings, 0 replies; 51+ messages in thread
From: Michal Wajdeczko @ 2022-11-22 17:42 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Create a set of GuC printers and start using them.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 ++++------
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++++++++++
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +--
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 +++++---------
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +++---
> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++++++-----
> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +--
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 +++++++---------
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++++++++----------
> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +++++-----
> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +++----
> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +--
> 12 files changed, 179 insertions(+), 190 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 52aede324788e..d9972510ee29b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -94,8 +94,8 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
> assert_rpm_wakelock_held(>->i915->runtime_pm);
>
> spin_lock_irq(gt->irq_lock);
> - WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
> - gt->pm_guc_events);
> + guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
> + gt->pm_guc_events);
> gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
> spin_unlock_irq(gt->irq_lock);
>
> @@ -339,7 +339,7 @@ static void guc_init_params(struct intel_guc *guc)
> params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
>
> for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
> - DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
> + guc_dbg(guc, "init param[%2d] = %#x\n", i, params[i]);
> }
>
> /*
> @@ -451,7 +451,7 @@ int intel_guc_init(struct intel_guc *guc)
> intel_uc_fw_fini(&guc->fw);
> out:
> intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
> - i915_probe_error(gt->i915, "failed with %d\n", ret);
> + guc_probe_error(guc, "init failed with %d\n", ret);
> return ret;
> }
>
> @@ -484,7 +484,6 @@ void intel_guc_fini(struct intel_guc *guc)
> int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
> u32 *response_buf, u32 response_buf_size)
> {
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
> u32 header;
> int i;
> @@ -519,8 +518,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
> 10, 10, &header);
> if (unlikely(ret)) {
> timeout:
> - drm_err(&i915->drm, "mmio request %#x: no reply %x\n",
> - request[0], header);
> + guc_err(guc, "mmio request %#x: no reply %x\n", request[0], header);
> goto out;
> }
>
> @@ -541,8 +539,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
> u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
>
> - drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n",
> - request[0], reason);
> + guc_dbg(guc, "mmio request %#x: retrying, reason %u\n", request[0], reason);
> goto retry;
> }
>
> @@ -550,16 +547,14 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
> u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
> u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
>
> - drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n",
> - request[0], error, hint);
> + guc_err(guc, "mmio request %#x: failure %x/%u\n", request[0], error, hint);
> ret = -ENXIO;
> goto out;
> }
>
> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) {
> proto:
> - drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n",
> - request[0], header);
> + guc_err(guc, "mmio request %#x: unexpected reply %#x\n", request[0], header);
> ret = -EPROTO;
> goto out;
> }
> @@ -601,9 +596,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
> msg = payload[0] & guc->msg_enabled_mask;
>
> if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
> - drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC crash dump notification!\n");
> + guc_err(guc, "early notification: Crash dump!\n");
> if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
> - drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC exception notification!\n");
> + guc_err(guc, "early notification: Exception!\n");
>
> return 0;
> }
> @@ -657,7 +652,7 @@ int intel_guc_suspend(struct intel_guc *guc)
> */
> ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
> if (ret)
> - DRM_ERROR("GuC suspend: RESET_CLIENT action failed with error %d!\n", ret);
> + guc_err(guc, "suspend: RESET_CLIENT action failed with error %d!\n", ret);
> }
>
> /* Signal that the GuC isn't running. */
> @@ -832,12 +827,11 @@ static int __guc_action_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 va
>
> static int __guc_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
> {
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> int err = __guc_action_self_cfg(guc, key, len, value);
>
> if (unlikely(err))
> - i915_probe_error(i915, "Unsuccessful self-config (%pe) key %#hx value %#llx\n",
> - ERR_PTR(err), key, value);
> + guc_probe_error(guc, "self-config; Unsuccessful (%pe) key %#hx value %#llx\n",
self-config:
> + ERR_PTR(err), key, value);
> return err;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 1bb3f98292866..8c02d22bc7e82 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -24,6 +24,41 @@
> struct __guc_ads_blob;
> struct intel_guc_state_capture;
>
> +#define guc_err(_guc, _fmt, ...) \
> + gt_err(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
> +
> +#define guc_warn(_guc, _fmt, ...) \
> + gt_warn(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
> +
> +#define guc_notice(_guc, _fmt, ...) \
> + gt_notice(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
> +
> +#define guc_info(_guc, _fmt, ...) \
> + gt_info(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
> +
> +#define guc_dbg(_guc, _fmt, ...) \
> + gt_dbg(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
> +
> +#define guc_probe_error(_guc, _fmt, ...) \
> + do { \
> + if (i915_error_injected()) \
> + guc_dbg(_guc, _fmt, ##__VA_ARGS__); \
> + else \
> + guc_err(_guc, _fmt, ##__VA_ARGS__); \
> + } while (0)
use gt_probe_error ?
> +
> +#define guc_WARN_ON(_guc, _condition) \
> + guc_WARN(_guc, _condition, "%s", "guc_WARN_ON(" __stringify(_condition) ")")
> +
> +#define guc_WARN_ON_ONCE(_guc, _condition) \
> + guc_WARN_ONCE(_guc, _condition, "%s", "guc_WARN_ON_ONCE(" __stringify(_condition) ")")
> +
> +#define guc_WARN(_guc, _condition, _fmt, ...) \
> + gt_WARN(guc_to_gt(_guc), _condition, "GuC " _fmt, ##__VA_ARGS__)
> +
> +#define guc_WARN_ONCE(_guc, _condition, _fmt, ...) \
> + gt_WARN_ONCE(guc_to_gt(_guc), _condition, "GuC " _fmt, ##__VA_ARGS__)
> +
> /**
> * struct intel_guc - Top level structure of GuC.
> *
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index a7f737c4792e2..fa9a31176b4a7 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -427,7 +427,7 @@ static long guc_mmio_reg_state_create(struct intel_guc *guc)
>
> guc->ads_regset = temp_set.storage;
>
> - drm_dbg(&guc_to_gt(guc)->i915->drm, "Used %zu KB for temporary ADS regset\n",
> + guc_dbg(guc, "used %zu KB for temporary ADS regset\n",
> (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
>
> return total * sizeof(struct guc_mmio_reg);
> @@ -621,8 +621,7 @@ static void guc_init_golden_context(struct intel_guc *guc)
>
> engine = find_engine_state(gt, engine_class);
> if (!engine) {
> - drm_err(>->i915->drm, "No engine state recorded for class %d!\n",
> - engine_class);
> + guc_err(guc, "No engine state recorded for class %d!\n", engine_class);
> ads_blob_write(guc, ads.eng_state_size[guc_class], 0);
> ads_blob_write(guc, ads.golden_context_lrca[guc_class], 0);
> continue;
> @@ -646,7 +645,6 @@ static int
> guc_capture_prep_lists(struct intel_guc *guc)
> {
> struct intel_gt *gt = guc_to_gt(guc);
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0;
> struct guc_gt_system_info local_info;
> struct iosys_map info_map;
> @@ -751,7 +749,7 @@ guc_capture_prep_lists(struct intel_guc *guc)
> }
>
> if (guc->ads_capture_size && guc->ads_capture_size != PAGE_ALIGN(total_size))
> - drm_warn(&i915->drm, "GuC->ADS->Capture alloc size changed from %d to %d\n",
> + guc_warn(guc, "capture alloc size changed from %d to %d\n",
> guc->ads_capture_size, PAGE_ALIGN(total_size));
>
> return PAGE_ALIGN(total_size);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index 1d49a7ec0bd8f..a8876178da6ff 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -353,7 +353,6 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
> u32 ipver)
> {
> struct intel_gt *gt = guc_to_gt(guc);
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> struct sseu_dev_info *sseu;
> int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0;
> const struct __guc_mmio_reg_descr_group *list;
> @@ -402,7 +401,7 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
> }
> }
>
> - drm_dbg(&i915->drm, "GuC-capture found %d-ext-regs.\n", num_tot_regs);
> + guc_dbg(guc, "capture found %d ext-regs.\n", num_tot_regs);
> guc->capture->extlists = extlists;
> }
>
> @@ -477,7 +476,6 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
> struct guc_mmio_reg *ptr, u16 num_entries)
> {
> u32 i = 0, j = 0;
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists;
> struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists;
> const struct __guc_mmio_reg_descr_group *match;
> @@ -509,8 +507,7 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
> }
> }
> if (i < num_entries)
> - drm_dbg(&i915->drm, "GuC-capture: Init reglist short %d out %d.\n",
> - (int)i, (int)num_entries);
> + guc_dbg(guc, "capture: Init reglist short %d out %d.\n", i, num_entries);
>
> return 0;
> }
> @@ -540,12 +537,11 @@ guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
> size_t *size, bool is_purpose_est)
> {
> struct intel_guc_state_capture *gc = guc->capture;
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
> int num_regs;
>
> if (!gc->reglists) {
> - drm_warn(&i915->drm, "GuC-capture: No reglist on this device\n");
> + guc_warn(guc, "capture: No reglist on this device\n");
> return -ENODEV;
> }
>
> @@ -557,9 +553,9 @@ guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
> if (!is_purpose_est && owner == GUC_CAPTURE_LIST_INDEX_PF &&
> !guc_capture_get_one_list(gc->reglists, owner, type, classid)) {
> if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL)
> - drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist Global!\n");
> + guc_warn(guc, "capture: Missing reglist: Global!\n");
> else
> - drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist %s(%u):%s(%u)!\n",
> + guc_warn(guc, "capture: Missing reglist: %s(%u):%s(%u)!\n",
> __stringify_type(type), type,
> __stringify_engclass(classid), classid);
> return -ENODATA;
> @@ -592,7 +588,6 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classi
> {
> struct intel_guc_state_capture *gc = guc->capture;
> struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> struct guc_debug_capture_list *listnode;
> int ret, num_regs;
> u8 *caplist, *tmp;
> @@ -623,7 +618,7 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classi
>
> caplist = kzalloc(size, GFP_KERNEL);
> if (!caplist) {
> - drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached caplist");
> + guc_dbg(guc, "capture: Failed to alloc cached caplist\n");
> return -ENOMEM;
> }
>
> @@ -653,7 +648,6 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
> void **outptr, size_t *size)
> {
> struct intel_guc_state_capture *gc = guc->capture;
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> int tmp = sizeof(u32) * 4;
> void *null_header;
>
> @@ -665,7 +659,7 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
>
> null_header = kzalloc(tmp, GFP_KERNEL);
> if (!null_header) {
> - drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached nulllist");
> + guc_dbg(guc, "capture: Failed to alloc cached null list\n");
> return -ENOMEM;
> }
>
> @@ -727,7 +721,6 @@ guc_capture_output_min_size_est(struct intel_guc *guc)
>
> static void check_guc_capture_size(struct intel_guc *guc)
> {
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> int min_size = guc_capture_output_min_size_est(guc);
> int spare_size = min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER;
> u32 buffer_size = intel_guc_log_section_size_capture(&guc->log);
> @@ -741,13 +734,13 @@ static void check_guc_capture_size(struct intel_guc *guc)
> * INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE.
> */
> if (min_size < 0)
> - drm_warn(&i915->drm, "Failed to calculate GuC error state capture buffer minimum size: %d!\n",
> + guc_warn(guc, "error state capture buffer minimum size calculation failed: %d!\n",
> min_size);
> else if (min_size > buffer_size)
> - drm_warn(&i915->drm, "GuC error state capture buffer maybe small: %d < %d\n",
> + guc_warn(guc, "error state capture buffer maybe small: %d < %d\n",
> buffer_size, min_size);
> else if (spare_size > buffer_size)
> - drm_dbg(&i915->drm, "GuC error state capture buffer lacks spare size: %d < %d (min = %d)\n",
> + guc_dbg(guc, "error state capture buffer lacks spare size: %d < %d (min = %d)\n",
> buffer_size, spare_size, min_size);
> }
>
> @@ -848,7 +841,6 @@ static int
> guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *buf,
> u32 *dw)
> {
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> int tries = 2;
> int avail = 0;
> u32 *src_data;
> @@ -865,7 +857,7 @@ guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *
> return 4;
> }
> if (avail)
> - drm_dbg(&i915->drm, "GuC-Cap-Logs not dword aligned, skipping.\n");
> + guc_dbg(guc, "capture: Log not dword aligned, skipping.\n");
> buf->rd = 0;
> }
>
> @@ -1118,13 +1110,12 @@ static void
> __guc_capture_create_prealloc_nodes(struct intel_guc *guc)
> {
> struct __guc_capture_parsed_output *node = NULL;
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> int i;
>
> for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) {
> node = guc_capture_alloc_one_node(guc);
> if (!node) {
> - drm_warn(&i915->drm, "GuC Capture pre-alloc-cache failure\n");
> + guc_warn(guc, "capture pre-alloc-cache failure\n");
> /* dont free the priors, use what we got and cleanup at shutdown */
> return;
> }
> @@ -1169,7 +1160,6 @@ guc_capture_create_prealloc_nodes(struct intel_guc *guc)
> static int
> guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstate *buf)
> {
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> struct guc_state_capture_group_header_t ghdr = {0};
> struct guc_state_capture_header_t hdr = {0};
> struct __guc_capture_parsed_output *node = NULL;
> @@ -1183,7 +1173,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
> if (!i)
> return -ENODATA;
> if (i % sizeof(u32)) {
> - drm_warn(&i915->drm, "GuC Capture new entries unaligned\n");
> + guc_warn(guc, "capture new entries unaligned\n");
> ret = -EIO;
> goto bailout;
> }
> @@ -1301,8 +1291,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
> break;
> }
> if (datatype != GUC_CAPTURE_LIST_TYPE_GLOBAL)
> - drm_dbg(&i915->drm, "GuC Capture missing global dump: %08x!\n",
> - datatype);
> + guc_dbg(guc, "cpture missing global dump: %08x!\n", datatype);
typo
> }
> node->is_partial = is_partial;
> node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner);
> @@ -1322,7 +1311,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
>
> numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios);
> if (numregs > guc->capture->max_mmio_per_node) {
> - drm_dbg(&i915->drm, "GuC Capture list extraction clipped by prealloc!\n");
> + guc_dbg(guc, "capture list extraction clipped by prealloc!\n");
> numregs = guc->capture->max_mmio_per_node;
> }
> node->reginfo[datatype].num_regs = numregs;
> @@ -1367,7 +1356,6 @@ static void __guc_capture_process_output(struct intel_guc *guc)
> {
> unsigned int buffer_size, read_offset, write_offset, full_count;
> struct intel_uc *uc = container_of(guc, typeof(*uc), guc);
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> struct guc_log_buffer_state log_buf_state_local;
> struct guc_log_buffer_state *log_buf_state;
> struct __guc_capture_bufstate buf;
> @@ -1403,7 +1391,7 @@ static void __guc_capture_process_output(struct intel_guc *guc)
> write_offset = buffer_size;
> } else if (unlikely((read_offset > buffer_size) ||
> (write_offset > buffer_size))) {
> - drm_err(&i915->drm, "invalid GuC log capture buffer state!\n");
> + guc_err(guc, "capture: invalid buffer state!\n");
> /* copy whole buffer as offsets are unreliable */
> read_offset = 0;
> write_offset = buffer_size;
> @@ -1586,13 +1574,11 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
> struct intel_context *ce)
> {
> struct __guc_capture_parsed_output *n, *ntmp;
> - struct drm_i915_private *i915;
> struct intel_guc *guc;
>
> if (!gt || !ee || !ce)
> return;
>
> - i915 = gt->i915;
> guc = >->uc.guc;
> if (!guc->capture)
> return;
> @@ -1615,7 +1601,7 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
> return;
> }
> }
> - drm_dbg(&i915->drm, "GuC capture can't match ee to node\n");
> + guc_dbg(guc, "capture can't match ee to node\n");
> }
>
> void intel_guc_capture_process(struct intel_guc *guc)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index 5b86b2e286e07..4a2811aa3d5e1 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -103,8 +103,9 @@ static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
> return uk_val == INTEL_GUC_LOAD_STATUS_READY;
> }
>
> -static int guc_wait_ucode(struct intel_uncore *uncore)
> +static int guc_wait_ucode(struct intel_gt *gt)
> {
> + struct intel_uncore *uncore = gt->uncore;
> u32 status;
> int ret;
>
> @@ -127,12 +128,8 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
> */
> ret = wait_for(guc_ready(uncore, &status), 200);
> if (ret) {
> - struct drm_device *drm = &uncore->i915->drm;
> -
> - drm_info(drm, "GuC load failed: status = 0x%08X\n", status);
> - drm_info(drm, "GuC load failed: status: Reset = %d, "
> - "BootROM = 0x%02X, UKernel = 0x%02X, "
> - "MIA = 0x%02X, Auth = 0x%02X\n",
> + gt_info(gt, "GuC load failed: status = 0x%08X\n", status);
> + gt_info(gt, "GuC load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n",
hmm, these should be guc_info() not gt_info()
so instead of gt we should pass guc to guc_wait_ucode()
> REG_FIELD_GET(GS_MIA_IN_RESET, status),
> REG_FIELD_GET(GS_BOOTROM_MASK, status),
> REG_FIELD_GET(GS_UKERNEL_MASK, status),
> @@ -140,13 +137,13 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
> REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
>
> if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
> - drm_info(drm, "GuC firmware signature verification failed\n");
> + gt_info(gt, "GuC firmware signature verification failed\n");
> ret = -ENOEXEC;
> }
>
> if (REG_FIELD_GET(GS_UKERNEL_MASK, status) == INTEL_GUC_LOAD_STATUS_EXCEPTION) {
> - drm_info(drm, "GuC firmware exception. EIP: %#x\n",
> - intel_uncore_read(uncore, SOFT_SCRATCH(13)));
> + gt_info(gt, "GuC firmware exception. EIP: %#x\n",
> + intel_uncore_read(uncore, SOFT_SCRATCH(13)));
> ret = -ENXIO;
> }
> }
> @@ -194,7 +191,7 @@ int intel_guc_fw_upload(struct intel_guc *guc)
> if (ret)
> goto out;
>
> - ret = guc_wait_ucode(uncore);
> + ret = guc_wait_ucode(gt);
> if (ret)
> goto out;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> index 68331c538b0a7..8c9a020700b52 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> @@ -39,7 +39,6 @@ struct guc_log_section {
> static void _guc_log_init_sizes(struct intel_guc_log *log)
> {
> struct intel_guc *guc = log_to_guc(log);
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> static const struct guc_log_section sections[GUC_LOG_SECTIONS_LIMIT] = {
> {
> GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT,
> @@ -82,12 +81,12 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
> }
>
> if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units))
> - drm_err(&i915->drm, "Mis-aligned GuC log %s size: 0x%X vs 0x%X!",
> + guc_err(guc, "log: Mis-aligned %s size: 0x%X vs 0x%X!\n",
> sections[i].name, log->sizes[i].bytes, log->sizes[i].units);
> log->sizes[i].count = log->sizes[i].bytes / log->sizes[i].units;
>
> if (!log->sizes[i].count) {
> - drm_err(&i915->drm, "Zero GuC log %s size!", sections[i].name);
> + guc_err(guc, "log: zero %s size!\n", sections[i].name);
> } else {
> /* Size is +1 unit */
> log->sizes[i].count--;
> @@ -95,14 +94,14 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
>
> /* Clip to field size */
> if (log->sizes[i].count > sections[i].max) {
> - drm_err(&i915->drm, "GuC log %s size too large: %d vs %d!",
> + guc_err(guc, "log: %s size too large: %d vs %d!\n",
> sections[i].name, log->sizes[i].count + 1, sections[i].max + 1);
> log->sizes[i].count = sections[i].max;
> }
> }
>
> if (log->sizes[GUC_LOG_SECTIONS_CRASH].units != log->sizes[GUC_LOG_SECTIONS_DEBUG].units) {
> - drm_err(&i915->drm, "Unit mis-match for GuC log crash and debug sections: %d vs %d!",
> + guc_err(guc, "log: Unit mis-match for crash and debug sections: %d vs %d!\n",
> log->sizes[GUC_LOG_SECTIONS_CRASH].units,
> log->sizes[GUC_LOG_SECTIONS_DEBUG].units);
> log->sizes[GUC_LOG_SECTIONS_CRASH].units = log->sizes[GUC_LOG_SECTIONS_DEBUG].units;
> @@ -383,7 +382,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
>
> mutex_lock(&log->relay.lock);
>
> - if (WARN_ON(!intel_guc_log_relay_created(log)))
> + if (guc_WARN_ON(log_to_guc(log), !intel_guc_log_relay_created(log)))
hmm, is this WARN_ON really needed here?
> goto out_unlock;
>
> /* Get the pointer to shared GuC log buffer */
> @@ -451,7 +450,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
> write_offset = buffer_size;
> } else if (unlikely((read_offset > buffer_size) ||
> (write_offset > buffer_size))) {
> - DRM_ERROR("invalid log buffer state\n");
> + guc_err(log_to_guc(log), "log: invalid buffer state\n");
> /* copy whole buffer as offsets are unreliable */
> read_offset = 0;
> write_offset = buffer_size;
> @@ -520,7 +519,7 @@ void intel_guc_log_init_early(struct intel_guc_log *log)
> static int guc_log_relay_create(struct intel_guc_log *log)
> {
> struct intel_guc *guc = log_to_guc(log);
> - struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
> + struct intel_gt *gt = guc_to_gt(guc);
> struct rchan *guc_log_relay_chan;
> size_t n_subbufs, subbuf_size;
> int ret;
> @@ -543,11 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log *log)
> n_subbufs = 8;
>
> guc_log_relay_chan = relay_open("guc_log",
> - dev_priv->drm.primary->debugfs_root,
> + gt->i915->drm.primary->debugfs_root,
> subbuf_size, n_subbufs,
> - &relay_callbacks, dev_priv);
> + &relay_callbacks, gt->i915);
> if (!guc_log_relay_chan) {
> - DRM_ERROR("Couldn't create relay chan for GuC logging\n");
> + guc_err(guc, "log: Failed to create relay chan\n");
>
> ret = -ENOMEM;
> return ret;
> @@ -596,7 +595,7 @@ static u32 __get_default_log_level(struct intel_guc_log *log)
> }
>
> if (i915->params.guc_log_level > GUC_LOG_LEVEL_MAX) {
> - DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
> + guc_warn(guc, "log: Incompatible options detected: %s=%d, %s!\n",
> "guc_log_level", i915->params.guc_log_level,
> "verbosity too high");
> return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
> @@ -641,15 +640,15 @@ int intel_guc_log_create(struct intel_guc_log *log)
> log->buf_addr = vaddr;
>
> log->level = __get_default_log_level(log);
> - DRM_DEBUG_DRIVER("guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
> - log->level, str_enabled_disabled(log->level),
> - str_yes_no(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
> - GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
> + guc_dbg(guc, "guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
> + log->level, str_enabled_disabled(log->level),
> + str_yes_no(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
> + GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
>
> return 0;
>
> err:
> - DRM_ERROR("Failed to allocate or map GuC log buffer. %d\n", ret);
> + guc_err(guc, "log: Failed to allocate or map buffer: %d\n", ret);
> return ret;
> }
>
> @@ -687,7 +686,7 @@ int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)
> GUC_LOG_LEVEL_IS_ENABLED(level),
> GUC_LOG_LEVEL_TO_VERBOSITY(level));
> if (ret) {
> - DRM_DEBUG_DRIVER("guc_log_control action failed %d\n", ret);
> + guc_dbg(guc, "guc_log_control action failed %d\n", ret);
> goto out_unlock;
> }
>
> @@ -905,7 +904,7 @@ int intel_guc_log_dump(struct intel_guc_log *log, struct drm_printer *p,
>
> map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
> if (IS_ERR(map)) {
> - DRM_DEBUG("Failed to pin object\n");
> + guc_dbg(guc, "log: Failed to pin buffer object\n");
> drm_puts(p, "(log data unaccessible)\n");
> free_page((unsigned long)page);
> return PTR_ERR(map);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> index b5855091cf6a9..62f3b97111f64 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> @@ -70,13 +70,12 @@ static int __guc_rc_control(struct intel_guc *guc, bool enable)
>
> ret = guc_action_control_gucrc(guc, enable);
> if (ret) {
> - i915_probe_error(guc_to_gt(guc)->i915, "Failed to %s GuC RC (%pe)\n",
> - str_enable_disable(enable), ERR_PTR(ret));
> + guc_probe_error(guc, "RC: Failed to %s: %pe\n",
> + str_enable_disable(enable), ERR_PTR(ret));
in most cases we show error in () so it looks like:
"GT0 GuC RC: Failed to enable (-ENOMEM)"
please don't change that
> return ret;
> }
>
> - drm_info(>->i915->drm, "GuC RC: %s\n",
> - str_enabled_disabled(enable));
> + guc_info(guc, "RC %s\n", str_enabled_disabled(enable));
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index 63464933cbceb..b9ef0b4a123e1 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -171,14 +171,12 @@ static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
> static int slpc_query_task_state(struct intel_guc_slpc *slpc)
> {
> struct intel_guc *guc = slpc_to_guc(slpc);
> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
> u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
> int ret;
>
> ret = guc_action_slpc_query(guc, offset);
> if (unlikely(ret))
> - i915_probe_error(i915, "Failed to query task state (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc, "SLPC: Failed to query task state (%pe)\n", ERR_PTR(ret));
>
> drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
>
> @@ -188,15 +186,14 @@ static int slpc_query_task_state(struct intel_guc_slpc *slpc)
> static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
> {
> struct intel_guc *guc = slpc_to_guc(slpc);
> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
> int ret;
>
> GEM_BUG_ON(id >= SLPC_MAX_PARAM);
>
> ret = guc_action_slpc_set_param(guc, id, value);
> if (ret)
> - i915_probe_error(i915, "Failed to set param %d to %u (%pe)\n",
> - id, value, ERR_PTR(ret));
> + guc_probe_error(guc, "SLPC: Failed to set param %d to %u (%pe)\n",
> + id, value, ERR_PTR(ret));
>
> return ret;
> }
> @@ -236,8 +233,7 @@ static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
> SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
> freq);
> if (ret)
> - drm_notice(&i915->drm,
> - "Failed to send set_param for min freq(%d): (%d)\n",
> + guc_notice(guc, "SLPC: Failed to send set_param for min freq(%d): (%d)\n",
> freq, ret);
> }
>
> @@ -267,7 +263,6 @@ static void slpc_boost_work(struct work_struct *work)
> int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
> {
> struct intel_guc *guc = slpc_to_guc(slpc);
> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
> u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
> int err;
>
> @@ -275,9 +270,8 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>
> err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&slpc->vaddr);
> if (unlikely(err)) {
> - i915_probe_error(i915,
> - "Failed to allocate SLPC struct (err=%pe)\n",
> - ERR_PTR(err));
> + guc_probe_error(guc, "SLPC: Failed to allocate SLPC struct (err=%pe)\n",
while here, drop "err=" just leave "(%pe)"
Michal
> + ERR_PTR(err));
> return err;
> }
>
> @@ -338,7 +332,6 @@ static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset)
>
> static int slpc_reset(struct intel_guc_slpc *slpc)
> {
> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
> struct intel_guc *guc = slpc_to_guc(slpc);
> u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
> int ret;
> @@ -346,15 +339,14 @@ static int slpc_reset(struct intel_guc_slpc *slpc)
> ret = guc_action_slpc_reset(guc, offset);
>
> if (unlikely(ret < 0)) {
> - i915_probe_error(i915, "SLPC reset action failed (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc, "SLPC: Reset action failed (%pe)\n", ERR_PTR(ret));
> return ret;
> }
>
> if (!ret) {
> if (wait_for(slpc_is_running(slpc), SLPC_RESET_TIMEOUT_MS)) {
> - i915_probe_error(i915, "SLPC not enabled! State = %s\n",
> - slpc_get_state_string(slpc));
> + guc_probe_error(guc, "SLPC: Not enabled! State = %s\n",
> + slpc_get_state_string(slpc));
> return -EIO;
> }
> }
> @@ -495,8 +487,8 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
> SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
> val < slpc->rp1_freq);
> if (ret) {
> - i915_probe_error(i915, "Failed to toggle efficient freq (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(slpc_to_guc(slpc), "SLPC: Failed to toggle efficient freq (%pe)\n",
> + ERR_PTR(ret));
> goto out;
> }
>
> @@ -611,15 +603,12 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
>
> static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
> {
> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
> int slpc_min_freq;
> int ret;
>
> ret = intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq);
> if (ret) {
> - drm_err(&i915->drm,
> - "Failed to get min freq: (%d)\n",
> - ret);
> + guc_err(slpc_to_guc(slpc), "SLPC: Failed to get min freq: (%d)\n", ret);
> return false;
> }
>
> @@ -685,8 +674,7 @@ int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode)
> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> ret = slpc_set_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
> if (ret)
> - drm_err(&i915->drm,
> - "Override gucrc mode %d failed %d\n",
> + guc_err(slpc_to_guc(slpc), "SLPC: Override gucrc mode %d failed %d\n",
> mode, ret);
> }
>
> @@ -702,9 +690,7 @@ int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> ret = slpc_unset_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE);
> if (ret)
> - drm_err(&i915->drm,
> - "Unsetting gucrc mode failed %d\n",
> - ret);
> + guc_err(slpc_to_guc(slpc), "SLPC: Unsetting gucrc mode failed %d\n", ret);
> }
>
> return ret;
> @@ -726,6 +712,7 @@ int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
> int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
> {
> struct drm_i915_private *i915 = slpc_to_i915(slpc);
> + struct intel_guc *guc = slpc_to_guc(slpc);
> int ret;
>
> GEM_BUG_ON(!slpc->vma);
> @@ -734,8 +721,8 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>
> ret = slpc_reset(slpc);
> if (unlikely(ret < 0)) {
> - i915_probe_error(i915, "SLPC Reset event returned (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc, "SLPC: Reset event returned (%pe)\n",
> + ERR_PTR(ret));
> return ret;
> }
>
> @@ -753,16 +740,16 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
> /* Set SLPC max limit to RP0 */
> ret = slpc_use_fused_rp0(slpc);
> if (unlikely(ret)) {
> - i915_probe_error(i915, "Failed to set SLPC max to RP0 (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc, "SLPC: Failed to set max to RP0 (%pe)\n",
> + ERR_PTR(ret));
> return ret;
> }
>
> /* Revert SLPC min/max to softlimits if necessary */
> ret = slpc_set_softlimits(slpc);
> if (unlikely(ret)) {
> - i915_probe_error(i915, "Failed to set SLPC softlimits (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc, "SLPC: Failed to set softlimits (%pe)\n",
> + ERR_PTR(ret));
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 0a42f1807f52c..da8ab18aa4ce7 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1443,8 +1443,7 @@ static void guc_init_engine_stats(struct intel_guc *guc)
> int ret = guc_action_enable_usage_stats(guc);
>
> if (ret)
> - drm_err(>->i915->drm,
> - "Failed to enable usage stats: %d!\n", ret);
> + guc_err(guc, "Failed to enable usage stats: %d!\n", ret);
> }
> }
>
> @@ -3584,8 +3583,7 @@ static int guc_request_alloc(struct i915_request *rq)
> intel_context_sched_disable_unpin(ce);
> else if (intel_context_is_closed(ce))
> if (wait_for(context_close_done(ce), 1500))
> - drm_warn(&guc_to_gt(guc)->i915->drm,
> - "timed out waiting on context sched close before realloc\n");
> + guc_warn(guc, "timed out waiting on context sched close before realloc\n");
> /*
> * Call pin_guc_id here rather than in the pinning step as with
> * dma_resv, contexts can be repeatedly pinned / unpinned trashing the
> @@ -4350,7 +4348,7 @@ static int __guc_action_set_scheduling_policies(struct intel_guc *guc,
> return ret;
>
> if (ret != policy->count) {
> - drm_warn(&guc_to_gt(guc)->i915->drm, "GuC global scheduler policy processed %d of %d KLVs!",
> + guc_warn(guc, "H2G: global scheduler policy processed %d of %d KLVs!\n",
> ret, policy->count);
> if (ret > policy->count)
> return -EPROTO;
> @@ -4383,9 +4381,9 @@ static int guc_init_global_schedule_policy(struct intel_guc *guc)
>
> ret = __guc_action_set_scheduling_policies(guc, &policy);
> if (ret)
> - i915_probe_error(gt->i915,
> - "Failed to configure global scheduling policies: %pe!\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc,
> + "Failed to configure global scheduling policies: %pe!\n",
> + ERR_PTR(ret));
> }
>
> return ret;
> @@ -4484,21 +4482,18 @@ g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)
> struct intel_context *ce;
>
> if (unlikely(ctx_id >= GUC_MAX_CONTEXT_ID)) {
> - drm_err(&guc_to_gt(guc)->i915->drm,
> - "Invalid ctx_id %u\n", ctx_id);
> + guc_err(guc, "Invalid ctx_id %u\n", ctx_id);
> return NULL;
> }
>
> ce = __get_context(guc, ctx_id);
> if (unlikely(!ce)) {
> - drm_err(&guc_to_gt(guc)->i915->drm,
> - "Context is NULL, ctx_id %u\n", ctx_id);
> + guc_err(guc, "Context is NULL, ctx_id %u\n", ctx_id);
> return NULL;
> }
>
> if (unlikely(intel_context_is_child(ce))) {
> - drm_err(&guc_to_gt(guc)->i915->drm,
> - "Context is child, ctx_id %u\n", ctx_id);
> + guc_err(guc, "Context is child, ctx_id %u\n", ctx_id);
> return NULL;
> }
>
> @@ -4513,7 +4508,7 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
> u32 ctx_id;
>
> if (unlikely(len < 1)) {
> - drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
> + guc_err(guc, "notification: Invalid length %u for deregister done\n", len);
> return -EPROTO;
> }
> ctx_id = msg[0];
> @@ -4565,7 +4560,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
> u32 ctx_id;
>
> if (unlikely(len < 2)) {
> - drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
> + guc_err(guc, "notification: Invalid length %u for sched done\n", len);
> return -EPROTO;
> }
> ctx_id = msg[0];
> @@ -4577,8 +4572,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
> if (unlikely(context_destroyed(ce) ||
> (!context_pending_enable(ce) &&
> !context_pending_disable(ce)))) {
> - drm_err(&guc_to_gt(guc)->i915->drm,
> - "Bad context sched_state 0x%x, ctx_id %u\n",
> + guc_err(guc, "notification: Bad context sched_state 0x%x, ctx_id %u\n",
> ce->guc_state.sched_state, ctx_id);
> return -EPROTO;
> }
> @@ -4666,8 +4660,8 @@ static void guc_handle_context_reset(struct intel_guc *guc,
> capture_error_state(guc, ce);
> guc_context_replay(ce);
> } else {
> - drm_info(&guc_to_gt(guc)->i915->drm,
> - "Ignoring context reset notification of exiting context 0x%04X on %s",
> + guc_info(guc,
> + "Ignoring context reset notification of exiting context 0x%04X on %s\n",
> ce->guc_id.id, ce->engine->name);
> }
> }
> @@ -4680,7 +4674,7 @@ int intel_guc_context_reset_process_msg(struct intel_guc *guc,
> int ctx_id;
>
> if (unlikely(len != 1)) {
> - drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
> + guc_err(guc, "notification: Invalid length %u for context reset\n", len);
> return -EPROTO;
> }
>
> @@ -4713,13 +4707,13 @@ int intel_guc_error_capture_process_msg(struct intel_guc *guc,
> u32 status;
>
> if (unlikely(len != 1)) {
> - drm_dbg(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
> + guc_err(guc, "notification: Invalid length %u for error capture\n", len);
> return -EPROTO;
> }
>
> status = msg[0] & INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK;
> if (status == INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE)
> - drm_warn(&guc_to_gt(guc)->i915->drm, "G2H-Error capture no space");
> + guc_warn(guc, "notification: Error capture buffer overflow\n");
>
> intel_guc_capture_process(guc);
>
> @@ -4762,13 +4756,12 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> const u32 *msg, u32 len)
> {
> struct intel_engine_cs *engine;
> - struct intel_gt *gt = guc_to_gt(guc);
> u8 guc_class, instance;
> u32 reason;
> unsigned long flags;
>
> if (unlikely(len != 3)) {
> - drm_err(>->i915->drm, "Invalid length %u", len);
> + guc_err(guc, "notification: Invalid length %u for engine failure\n", len);
> return -EPROTO;
> }
>
> @@ -4778,8 +4771,8 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
>
> engine = intel_guc_lookup_engine(guc, guc_class, instance);
> if (unlikely(!engine)) {
> - drm_err(>->i915->drm,
> - "Invalid engine %d:%d", guc_class, instance);
> + guc_err(guc, "notification: Invalid engine %d:%d for engine failure\n",
> + guc_class, instance);
> return -EPROTO;
> }
>
> @@ -4787,7 +4780,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> * This is an unexpected failure of a hardware feature. So, log a real
> * error message not just the informational that comes with the reset.
> */
> - drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X",
> + guc_err(guc, "notification: Engine reset request failed on %d:%d (%s) because 0x%08X\n",
> guc_class, instance, engine->name, reason);
>
> spin_lock_irqsave(&guc->submission_state.lock, flags);
> @@ -5297,6 +5290,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
> unsigned long flags)
> {
> struct guc_virtual_engine *ve;
> + struct intel_gt *gt;
> struct intel_guc *guc;
> unsigned int n;
> int err;
> @@ -5305,10 +5299,11 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
> if (!ve)
> return ERR_PTR(-ENOMEM);
>
> - guc = &siblings[0]->gt->uc.guc;
> + gt = siblings[0]->gt;
> + guc = >->uc.guc;
>
> ve->base.i915 = siblings[0]->i915;
> - ve->base.gt = siblings[0]->gt;
> + ve->base.gt = gt;
> ve->base.uncore = siblings[0]->uncore;
> ve->base.id = -1;
>
> @@ -5336,8 +5331,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
>
> GEM_BUG_ON(!is_power_of_2(sibling->mask));
> if (sibling->mask & ve->base.mask) {
> - DRM_DEBUG("duplicate %s entry in load balancer\n",
> - sibling->name);
> + guc_dbg(guc, "Duplicate %s entry in load balancer\n", sibling->name);
> err = -EINVAL;
> goto err_put;
> }
> @@ -5346,8 +5340,8 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
> ve->base.logical_mask |= sibling->logical_mask;
>
> if (n != 0 && ve->base.class != sibling->class) {
> - DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n",
> - sibling->class, ve->base.class);
> + guc_dbg(guc, "Invalid mixing of engine class, sibling %d, already %d\n",
> + sibling->class, ve->base.class);
> err = -EINVAL;
> goto err_put;
> } else if (n == 0) {
> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> index e28518fe8b908..d588c32d65c54 100644
> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> @@ -65,7 +65,7 @@ static int intel_guc_scrub_ctbs(void *arg)
> ce = intel_context_create(engine);
> if (IS_ERR(ce)) {
> ret = PTR_ERR(ce);
> - drm_err(>->i915->drm, "Failed to create context, %d: %d\n", i, ret);
> + gt_err(gt, "Failed to create context, %d: %d\n", i, ret);
> goto err;
> }
>
> @@ -86,7 +86,7 @@ static int intel_guc_scrub_ctbs(void *arg)
>
> if (IS_ERR(rq)) {
> ret = PTR_ERR(rq);
> - drm_err(>->i915->drm, "Failed to create request, %d: %d\n", i, ret);
> + gt_err(gt, "Failed to create request, %d: %d\n", i, ret);
> goto err;
> }
>
> @@ -96,7 +96,7 @@ static int intel_guc_scrub_ctbs(void *arg)
> for (i = 0; i < 3; ++i) {
> ret = i915_request_wait(last[i], 0, HZ);
> if (ret < 0) {
> - drm_err(>->i915->drm, "Last request failed to complete: %d\n", ret);
> + gt_err(gt, "Last request failed to complete: %d\n", ret);
> goto err;
> }
> i915_request_put(last[i]);
> @@ -113,7 +113,7 @@ static int intel_guc_scrub_ctbs(void *arg)
> /* GT will not idle if G2H are lost */
> ret = intel_gt_wait_for_idle(gt, HZ);
> if (ret < 0) {
> - drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
> + gt_err(gt, "GT failed to idle: %d\n", ret);
> goto err;
> }
>
> @@ -153,7 +153,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>
> ce = kcalloc(GUC_MAX_CONTEXT_ID, sizeof(*ce), GFP_KERNEL);
> if (!ce) {
> - drm_err(>->i915->drm, "Context array allocation failed\n");
> + guc_err(guc, "Context array allocation failed\n");
> return -ENOMEM;
> }
>
> @@ -167,24 +167,24 @@ static int intel_guc_steal_guc_ids(void *arg)
> if (IS_ERR(ce[context_index])) {
> ret = PTR_ERR(ce[context_index]);
> ce[context_index] = NULL;
> - drm_err(>->i915->drm, "Failed to create context: %d\n", ret);
> + guc_err(guc, "Failed to create context: %d\n", ret);
> goto err_wakeref;
> }
> ret = igt_spinner_init(&spin, engine->gt);
> if (ret) {
> - drm_err(>->i915->drm, "Failed to create spinner: %d\n", ret);
> + guc_err(guc, "Failed to create spinner: %d\n", ret);
> goto err_contexts;
> }
> spin_rq = igt_spinner_create_request(&spin, ce[context_index],
> MI_ARB_CHECK);
> if (IS_ERR(spin_rq)) {
> ret = PTR_ERR(spin_rq);
> - drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
> + guc_err(guc, "Failed to create spinner request: %d\n", ret);
> goto err_contexts;
> }
> ret = request_add_spin(spin_rq, &spin);
> if (ret) {
> - drm_err(>->i915->drm, "Failed to add Spinner request: %d\n", ret);
> + guc_err(guc, "Failed to add Spinner request: %d\n", ret);
> goto err_spin_rq;
> }
>
> @@ -194,7 +194,7 @@ static int intel_guc_steal_guc_ids(void *arg)
> if (IS_ERR(ce[context_index])) {
> ret = PTR_ERR(ce[context_index--]);
> ce[context_index] = NULL;
> - drm_err(>->i915->drm, "Failed to create context: %d\n", ret);
> + guc_err(guc, "Failed to create context: %d\n", ret);
> goto err_spin_rq;
> }
>
> @@ -203,7 +203,7 @@ static int intel_guc_steal_guc_ids(void *arg)
> ret = PTR_ERR(rq);
> rq = NULL;
> if (ret != -EAGAIN) {
> - drm_err(>->i915->drm, "Failed to create request, %d: %d\n",
> + guc_err(guc, "Failed to create request, %d: %d\n",
> context_index, ret);
> goto err_spin_rq;
> }
> @@ -218,7 +218,7 @@ static int intel_guc_steal_guc_ids(void *arg)
> igt_spinner_end(&spin);
> ret = intel_selftest_wait_for_rq(spin_rq);
> if (ret) {
> - drm_err(>->i915->drm, "Spin request failed to complete: %d\n", ret);
> + guc_err(guc, "Spin request failed to complete: %d\n", ret);
> i915_request_put(last);
> goto err_spin_rq;
> }
> @@ -230,7 +230,7 @@ static int intel_guc_steal_guc_ids(void *arg)
> ret = i915_request_wait(last, 0, HZ * 30);
> i915_request_put(last);
> if (ret < 0) {
> - drm_err(>->i915->drm, "Last request failed to complete: %d\n", ret);
> + guc_err(guc, "Last request failed to complete: %d\n", ret);
> goto err_spin_rq;
> }
>
> @@ -238,7 +238,7 @@ static int intel_guc_steal_guc_ids(void *arg)
> rq = nop_user_request(ce[context_index], NULL);
> if (IS_ERR(rq)) {
> ret = PTR_ERR(rq);
> - drm_err(>->i915->drm, "Failed to steal guc_id, %d: %d\n", context_index, ret);
> + guc_err(guc, "Failed to steal guc_id, %d: %d\n", context_index, ret);
> goto err_spin_rq;
> }
>
> @@ -246,20 +246,20 @@ static int intel_guc_steal_guc_ids(void *arg)
> ret = i915_request_wait(rq, 0, HZ);
> i915_request_put(rq);
> if (ret < 0) {
> - drm_err(>->i915->drm, "Request with stolen guc_id failed to complete: %d\n", ret);
> + guc_err(guc, "Request with stolen guc_id failed to complete: %d\n", ret);
> goto err_spin_rq;
> }
>
> /* Wait for idle */
> ret = intel_gt_wait_for_idle(gt, HZ * 30);
> if (ret < 0) {
> - drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
> + guc_err(guc, "GT failed to idle: %d\n", ret);
> goto err_spin_rq;
> }
>
> /* Verify a guc_id was stolen */
> if (guc->number_guc_id_stolen == number_guc_id_stolen) {
> - drm_err(>->i915->drm, "No guc_id was stolen");
> + guc_err(guc, "No guc_id was stolen\n");
> ret = -EINVAL;
> } else {
> ret = 0;
> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
> index d91b58f704039..07018ec75c21f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
> @@ -45,7 +45,7 @@ static int intel_hang_guc(void *arg)
>
> ctx = kernel_context(gt->i915, NULL);
> if (IS_ERR(ctx)) {
> - drm_err(>->i915->drm, "Failed get kernel context: %ld\n", PTR_ERR(ctx));
> + gt_err(gt, "Failed get kernel context: %ld\n", PTR_ERR(ctx));
> return PTR_ERR(ctx);
> }
>
> @@ -54,7 +54,7 @@ static int intel_hang_guc(void *arg)
> ce = intel_context_create(engine);
> if (IS_ERR(ce)) {
> ret = PTR_ERR(ce);
> - drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
> + gt_err(gt, "Failed to create spinner request: %d\n", ret);
> goto err;
> }
>
> @@ -63,13 +63,13 @@ static int intel_hang_guc(void *arg)
> old_beat = engine->props.heartbeat_interval_ms;
> ret = intel_engine_set_heartbeat(engine, BEAT_INTERVAL);
> if (ret) {
> - drm_err(>->i915->drm, "Failed to boost heatbeat interval: %d\n", ret);
> + gt_err(gt, "Failed to boost heatbeat interval: %d\n", ret);
> goto err;
> }
>
> ret = igt_spinner_init(&spin, engine->gt);
> if (ret) {
> - drm_err(>->i915->drm, "Failed to create spinner: %d\n", ret);
> + gt_err(gt, "Failed to create spinner: %d\n", ret);
> goto err;
> }
>
> @@ -77,28 +77,28 @@ static int intel_hang_guc(void *arg)
> intel_context_put(ce);
> if (IS_ERR(rq)) {
> ret = PTR_ERR(rq);
> - drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
> + gt_err(gt, "Failed to create spinner request: %d\n", ret);
> goto err_spin;
> }
>
> ret = request_add_spin(rq, &spin);
> if (ret) {
> i915_request_put(rq);
> - drm_err(>->i915->drm, "Failed to add Spinner request: %d\n", ret);
> + gt_err(gt, "Failed to add Spinner request: %d\n", ret);
> goto err_spin;
> }
>
> ret = intel_reset_guc(gt);
> if (ret) {
> i915_request_put(rq);
> - drm_err(>->i915->drm, "Failed to reset GuC, ret = %d\n", ret);
> + gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
> goto err_spin;
> }
>
> guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
> if (!(guc_status & GS_MIA_IN_RESET)) {
> i915_request_put(rq);
> - drm_err(>->i915->drm, "GuC failed to reset: status = 0x%08X\n", guc_status);
> + gt_err(gt, "GuC failed to reset: status = 0x%08X\n", guc_status);
> ret = -EIO;
> goto err_spin;
> }
> @@ -107,12 +107,12 @@ static int intel_hang_guc(void *arg)
> ret = intel_selftest_wait_for_rq(rq);
> i915_request_put(rq);
> if (ret) {
> - drm_err(>->i915->drm, "Request failed to complete: %d\n", ret);
> + gt_err(gt, "Request failed to complete: %d\n", ret);
> goto err_spin;
> }
>
> if (i915_reset_count(global) == reset_count) {
> - drm_err(>->i915->drm, "Failed to record a GPU reset\n");
> + gt_err(gt, "Failed to record a GPU reset\n");
> ret = -EINVAL;
> goto err_spin;
> }
> @@ -132,7 +132,7 @@ static int intel_hang_guc(void *arg)
> ret = intel_selftest_wait_for_rq(rq);
> i915_request_put(rq);
> if (ret) {
> - drm_err(>->i915->drm, "No-op failed to complete: %d\n", ret);
> + gt_err(gt, "No-op failed to complete: %d\n", ret);
> goto err;
> }
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
> index d17982c36d256..04e28735a2ee6 100644
> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
> @@ -115,30 +115,30 @@ static int __intel_guc_multi_lrc_basic(struct intel_gt *gt, unsigned int class)
>
> parent = multi_lrc_create_parent(gt, class, 0);
> if (IS_ERR(parent)) {
> - drm_err(>->i915->drm, "Failed creating contexts: %ld", PTR_ERR(parent));
> + gt_err(gt, "Failed creating contexts: %ld", PTR_ERR(parent));
> return PTR_ERR(parent);
> } else if (!parent) {
> - drm_dbg(>->i915->drm, "Not enough engines in class: %d", class);
> + gt_dbg(gt, "Not enough engines in class: %d", class);
> return 0;
> }
>
> rq = multi_lrc_nop_request(parent);
> if (IS_ERR(rq)) {
> ret = PTR_ERR(rq);
> - drm_err(>->i915->drm, "Failed creating requests: %d", ret);
> + gt_err(gt, "Failed creating requests: %d", ret);
> goto out;
> }
>
> ret = intel_selftest_wait_for_rq(rq);
> if (ret)
> - drm_err(>->i915->drm, "Failed waiting on request: %d", ret);
> + gt_err(gt, "Failed waiting on request: %d", ret);
>
> i915_request_put(rq);
>
> if (ret >= 0) {
> ret = intel_gt_wait_for_idle(gt, HZ * 5);
> if (ret < 0)
> - drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
> + gt_err(gt, "GT failed to idle: %d\n", ret);
> }
>
> out:
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH v2 3/5] drm/i915/guc: Add GuC specific debug print wrappers
@ 2022-11-22 17:42 ` Michal Wajdeczko
0 siblings, 0 replies; 51+ messages in thread
From: Michal Wajdeczko @ 2022-11-22 17:42 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Create a set of GuC printers and start using them.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 ++++------
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++++++++++
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +--
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 +++++---------
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +++---
> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++++++-----
> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +--
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 +++++++---------
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++++++++----------
> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +++++-----
> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +++----
> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +--
> 12 files changed, 179 insertions(+), 190 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 52aede324788e..d9972510ee29b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -94,8 +94,8 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
> assert_rpm_wakelock_held(>->i915->runtime_pm);
>
> spin_lock_irq(gt->irq_lock);
> - WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
> - gt->pm_guc_events);
> + guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
> + gt->pm_guc_events);
> gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
> spin_unlock_irq(gt->irq_lock);
>
> @@ -339,7 +339,7 @@ static void guc_init_params(struct intel_guc *guc)
> params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
>
> for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
> - DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
> + guc_dbg(guc, "init param[%2d] = %#x\n", i, params[i]);
> }
>
> /*
> @@ -451,7 +451,7 @@ int intel_guc_init(struct intel_guc *guc)
> intel_uc_fw_fini(&guc->fw);
> out:
> intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
> - i915_probe_error(gt->i915, "failed with %d\n", ret);
> + guc_probe_error(guc, "init failed with %d\n", ret);
> return ret;
> }
>
> @@ -484,7 +484,6 @@ void intel_guc_fini(struct intel_guc *guc)
> int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
> u32 *response_buf, u32 response_buf_size)
> {
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
> u32 header;
> int i;
> @@ -519,8 +518,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
> 10, 10, &header);
> if (unlikely(ret)) {
> timeout:
> - drm_err(&i915->drm, "mmio request %#x: no reply %x\n",
> - request[0], header);
> + guc_err(guc, "mmio request %#x: no reply %x\n", request[0], header);
> goto out;
> }
>
> @@ -541,8 +539,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
> u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
>
> - drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n",
> - request[0], reason);
> + guc_dbg(guc, "mmio request %#x: retrying, reason %u\n", request[0], reason);
> goto retry;
> }
>
> @@ -550,16 +547,14 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
> u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
> u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
>
> - drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n",
> - request[0], error, hint);
> + guc_err(guc, "mmio request %#x: failure %x/%u\n", request[0], error, hint);
> ret = -ENXIO;
> goto out;
> }
>
> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) {
> proto:
> - drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n",
> - request[0], header);
> + guc_err(guc, "mmio request %#x: unexpected reply %#x\n", request[0], header);
> ret = -EPROTO;
> goto out;
> }
> @@ -601,9 +596,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
> msg = payload[0] & guc->msg_enabled_mask;
>
> if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
> - drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC crash dump notification!\n");
> + guc_err(guc, "early notification: Crash dump!\n");
> if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
> - drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC exception notification!\n");
> + guc_err(guc, "early notification: Exception!\n");
>
> return 0;
> }
> @@ -657,7 +652,7 @@ int intel_guc_suspend(struct intel_guc *guc)
> */
> ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
> if (ret)
> - DRM_ERROR("GuC suspend: RESET_CLIENT action failed with error %d!\n", ret);
> + guc_err(guc, "suspend: RESET_CLIENT action failed with error %d!\n", ret);
> }
>
> /* Signal that the GuC isn't running. */
> @@ -832,12 +827,11 @@ static int __guc_action_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 va
>
> static int __guc_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
> {
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> int err = __guc_action_self_cfg(guc, key, len, value);
>
> if (unlikely(err))
> - i915_probe_error(i915, "Unsuccessful self-config (%pe) key %#hx value %#llx\n",
> - ERR_PTR(err), key, value);
> + guc_probe_error(guc, "self-config; Unsuccessful (%pe) key %#hx value %#llx\n",
self-config:
> + ERR_PTR(err), key, value);
> return err;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 1bb3f98292866..8c02d22bc7e82 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -24,6 +24,41 @@
> struct __guc_ads_blob;
> struct intel_guc_state_capture;
>
> +#define guc_err(_guc, _fmt, ...) \
> + gt_err(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
> +
> +#define guc_warn(_guc, _fmt, ...) \
> + gt_warn(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
> +
> +#define guc_notice(_guc, _fmt, ...) \
> + gt_notice(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
> +
> +#define guc_info(_guc, _fmt, ...) \
> + gt_info(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
> +
> +#define guc_dbg(_guc, _fmt, ...) \
> + gt_dbg(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
> +
> +#define guc_probe_error(_guc, _fmt, ...) \
> + do { \
> + if (i915_error_injected()) \
> + guc_dbg(_guc, _fmt, ##__VA_ARGS__); \
> + else \
> + guc_err(_guc, _fmt, ##__VA_ARGS__); \
> + } while (0)
use gt_probe_error ?
> +
> +#define guc_WARN_ON(_guc, _condition) \
> + guc_WARN(_guc, _condition, "%s", "guc_WARN_ON(" __stringify(_condition) ")")
> +
> +#define guc_WARN_ON_ONCE(_guc, _condition) \
> + guc_WARN_ONCE(_guc, _condition, "%s", "guc_WARN_ON_ONCE(" __stringify(_condition) ")")
> +
> +#define guc_WARN(_guc, _condition, _fmt, ...) \
> + gt_WARN(guc_to_gt(_guc), _condition, "GuC " _fmt, ##__VA_ARGS__)
> +
> +#define guc_WARN_ONCE(_guc, _condition, _fmt, ...) \
> + gt_WARN_ONCE(guc_to_gt(_guc), _condition, "GuC " _fmt, ##__VA_ARGS__)
> +
> /**
> * struct intel_guc - Top level structure of GuC.
> *
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index a7f737c4792e2..fa9a31176b4a7 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -427,7 +427,7 @@ static long guc_mmio_reg_state_create(struct intel_guc *guc)
>
> guc->ads_regset = temp_set.storage;
>
> - drm_dbg(&guc_to_gt(guc)->i915->drm, "Used %zu KB for temporary ADS regset\n",
> + guc_dbg(guc, "used %zu KB for temporary ADS regset\n",
> (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
>
> return total * sizeof(struct guc_mmio_reg);
> @@ -621,8 +621,7 @@ static void guc_init_golden_context(struct intel_guc *guc)
>
> engine = find_engine_state(gt, engine_class);
> if (!engine) {
> - drm_err(>->i915->drm, "No engine state recorded for class %d!\n",
> - engine_class);
> + guc_err(guc, "No engine state recorded for class %d!\n", engine_class);
> ads_blob_write(guc, ads.eng_state_size[guc_class], 0);
> ads_blob_write(guc, ads.golden_context_lrca[guc_class], 0);
> continue;
> @@ -646,7 +645,6 @@ static int
> guc_capture_prep_lists(struct intel_guc *guc)
> {
> struct intel_gt *gt = guc_to_gt(guc);
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0;
> struct guc_gt_system_info local_info;
> struct iosys_map info_map;
> @@ -751,7 +749,7 @@ guc_capture_prep_lists(struct intel_guc *guc)
> }
>
> if (guc->ads_capture_size && guc->ads_capture_size != PAGE_ALIGN(total_size))
> - drm_warn(&i915->drm, "GuC->ADS->Capture alloc size changed from %d to %d\n",
> + guc_warn(guc, "capture alloc size changed from %d to %d\n",
> guc->ads_capture_size, PAGE_ALIGN(total_size));
>
> return PAGE_ALIGN(total_size);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index 1d49a7ec0bd8f..a8876178da6ff 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -353,7 +353,6 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
> u32 ipver)
> {
> struct intel_gt *gt = guc_to_gt(guc);
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> struct sseu_dev_info *sseu;
> int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0;
> const struct __guc_mmio_reg_descr_group *list;
> @@ -402,7 +401,7 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
> }
> }
>
> - drm_dbg(&i915->drm, "GuC-capture found %d-ext-regs.\n", num_tot_regs);
> + guc_dbg(guc, "capture found %d ext-regs.\n", num_tot_regs);
> guc->capture->extlists = extlists;
> }
>
> @@ -477,7 +476,6 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
> struct guc_mmio_reg *ptr, u16 num_entries)
> {
> u32 i = 0, j = 0;
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists;
> struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists;
> const struct __guc_mmio_reg_descr_group *match;
> @@ -509,8 +507,7 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
> }
> }
> if (i < num_entries)
> - drm_dbg(&i915->drm, "GuC-capture: Init reglist short %d out %d.\n",
> - (int)i, (int)num_entries);
> + guc_dbg(guc, "capture: Init reglist short %d out %d.\n", i, num_entries);
>
> return 0;
> }
> @@ -540,12 +537,11 @@ guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
> size_t *size, bool is_purpose_est)
> {
> struct intel_guc_state_capture *gc = guc->capture;
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
> int num_regs;
>
> if (!gc->reglists) {
> - drm_warn(&i915->drm, "GuC-capture: No reglist on this device\n");
> + guc_warn(guc, "capture: No reglist on this device\n");
> return -ENODEV;
> }
>
> @@ -557,9 +553,9 @@ guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
> if (!is_purpose_est && owner == GUC_CAPTURE_LIST_INDEX_PF &&
> !guc_capture_get_one_list(gc->reglists, owner, type, classid)) {
> if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL)
> - drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist Global!\n");
> + guc_warn(guc, "capture: Missing reglist: Global!\n");
> else
> - drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist %s(%u):%s(%u)!\n",
> + guc_warn(guc, "capture: Missing reglist: %s(%u):%s(%u)!\n",
> __stringify_type(type), type,
> __stringify_engclass(classid), classid);
> return -ENODATA;
> @@ -592,7 +588,6 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classi
> {
> struct intel_guc_state_capture *gc = guc->capture;
> struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> struct guc_debug_capture_list *listnode;
> int ret, num_regs;
> u8 *caplist, *tmp;
> @@ -623,7 +618,7 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classi
>
> caplist = kzalloc(size, GFP_KERNEL);
> if (!caplist) {
> - drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached caplist");
> + guc_dbg(guc, "capture: Failed to alloc cached caplist\n");
> return -ENOMEM;
> }
>
> @@ -653,7 +648,6 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
> void **outptr, size_t *size)
> {
> struct intel_guc_state_capture *gc = guc->capture;
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> int tmp = sizeof(u32) * 4;
> void *null_header;
>
> @@ -665,7 +659,7 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
>
> null_header = kzalloc(tmp, GFP_KERNEL);
> if (!null_header) {
> - drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached nulllist");
> + guc_dbg(guc, "capture: Failed to alloc cached null list\n");
> return -ENOMEM;
> }
>
> @@ -727,7 +721,6 @@ guc_capture_output_min_size_est(struct intel_guc *guc)
>
> static void check_guc_capture_size(struct intel_guc *guc)
> {
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> int min_size = guc_capture_output_min_size_est(guc);
> int spare_size = min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER;
> u32 buffer_size = intel_guc_log_section_size_capture(&guc->log);
> @@ -741,13 +734,13 @@ static void check_guc_capture_size(struct intel_guc *guc)
> * INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE.
> */
> if (min_size < 0)
> - drm_warn(&i915->drm, "Failed to calculate GuC error state capture buffer minimum size: %d!\n",
> + guc_warn(guc, "error state capture buffer minimum size calculation failed: %d!\n",
> min_size);
> else if (min_size > buffer_size)
> - drm_warn(&i915->drm, "GuC error state capture buffer maybe small: %d < %d\n",
> + guc_warn(guc, "error state capture buffer maybe small: %d < %d\n",
> buffer_size, min_size);
> else if (spare_size > buffer_size)
> - drm_dbg(&i915->drm, "GuC error state capture buffer lacks spare size: %d < %d (min = %d)\n",
> + guc_dbg(guc, "error state capture buffer lacks spare size: %d < %d (min = %d)\n",
> buffer_size, spare_size, min_size);
> }
>
> @@ -848,7 +841,6 @@ static int
> guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *buf,
> u32 *dw)
> {
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> int tries = 2;
> int avail = 0;
> u32 *src_data;
> @@ -865,7 +857,7 @@ guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *
> return 4;
> }
> if (avail)
> - drm_dbg(&i915->drm, "GuC-Cap-Logs not dword aligned, skipping.\n");
> + guc_dbg(guc, "capture: Log not dword aligned, skipping.\n");
> buf->rd = 0;
> }
>
> @@ -1118,13 +1110,12 @@ static void
> __guc_capture_create_prealloc_nodes(struct intel_guc *guc)
> {
> struct __guc_capture_parsed_output *node = NULL;
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> int i;
>
> for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) {
> node = guc_capture_alloc_one_node(guc);
> if (!node) {
> - drm_warn(&i915->drm, "GuC Capture pre-alloc-cache failure\n");
> + guc_warn(guc, "capture pre-alloc-cache failure\n");
> /* dont free the priors, use what we got and cleanup at shutdown */
> return;
> }
> @@ -1169,7 +1160,6 @@ guc_capture_create_prealloc_nodes(struct intel_guc *guc)
> static int
> guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstate *buf)
> {
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> struct guc_state_capture_group_header_t ghdr = {0};
> struct guc_state_capture_header_t hdr = {0};
> struct __guc_capture_parsed_output *node = NULL;
> @@ -1183,7 +1173,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
> if (!i)
> return -ENODATA;
> if (i % sizeof(u32)) {
> - drm_warn(&i915->drm, "GuC Capture new entries unaligned\n");
> + guc_warn(guc, "capture new entries unaligned\n");
> ret = -EIO;
> goto bailout;
> }
> @@ -1301,8 +1291,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
> break;
> }
> if (datatype != GUC_CAPTURE_LIST_TYPE_GLOBAL)
> - drm_dbg(&i915->drm, "GuC Capture missing global dump: %08x!\n",
> - datatype);
> + guc_dbg(guc, "cpture missing global dump: %08x!\n", datatype);
typo
> }
> node->is_partial = is_partial;
> node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner);
> @@ -1322,7 +1311,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
>
> numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios);
> if (numregs > guc->capture->max_mmio_per_node) {
> - drm_dbg(&i915->drm, "GuC Capture list extraction clipped by prealloc!\n");
> + guc_dbg(guc, "capture list extraction clipped by prealloc!\n");
> numregs = guc->capture->max_mmio_per_node;
> }
> node->reginfo[datatype].num_regs = numregs;
> @@ -1367,7 +1356,6 @@ static void __guc_capture_process_output(struct intel_guc *guc)
> {
> unsigned int buffer_size, read_offset, write_offset, full_count;
> struct intel_uc *uc = container_of(guc, typeof(*uc), guc);
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> struct guc_log_buffer_state log_buf_state_local;
> struct guc_log_buffer_state *log_buf_state;
> struct __guc_capture_bufstate buf;
> @@ -1403,7 +1391,7 @@ static void __guc_capture_process_output(struct intel_guc *guc)
> write_offset = buffer_size;
> } else if (unlikely((read_offset > buffer_size) ||
> (write_offset > buffer_size))) {
> - drm_err(&i915->drm, "invalid GuC log capture buffer state!\n");
> + guc_err(guc, "capture: invalid buffer state!\n");
> /* copy whole buffer as offsets are unreliable */
> read_offset = 0;
> write_offset = buffer_size;
> @@ -1586,13 +1574,11 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
> struct intel_context *ce)
> {
> struct __guc_capture_parsed_output *n, *ntmp;
> - struct drm_i915_private *i915;
> struct intel_guc *guc;
>
> if (!gt || !ee || !ce)
> return;
>
> - i915 = gt->i915;
> guc = >->uc.guc;
> if (!guc->capture)
> return;
> @@ -1615,7 +1601,7 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
> return;
> }
> }
> - drm_dbg(&i915->drm, "GuC capture can't match ee to node\n");
> + guc_dbg(guc, "capture can't match ee to node\n");
> }
>
> void intel_guc_capture_process(struct intel_guc *guc)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index 5b86b2e286e07..4a2811aa3d5e1 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -103,8 +103,9 @@ static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
> return uk_val == INTEL_GUC_LOAD_STATUS_READY;
> }
>
> -static int guc_wait_ucode(struct intel_uncore *uncore)
> +static int guc_wait_ucode(struct intel_gt *gt)
> {
> + struct intel_uncore *uncore = gt->uncore;
> u32 status;
> int ret;
>
> @@ -127,12 +128,8 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
> */
> ret = wait_for(guc_ready(uncore, &status), 200);
> if (ret) {
> - struct drm_device *drm = &uncore->i915->drm;
> -
> - drm_info(drm, "GuC load failed: status = 0x%08X\n", status);
> - drm_info(drm, "GuC load failed: status: Reset = %d, "
> - "BootROM = 0x%02X, UKernel = 0x%02X, "
> - "MIA = 0x%02X, Auth = 0x%02X\n",
> + gt_info(gt, "GuC load failed: status = 0x%08X\n", status);
> + gt_info(gt, "GuC load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n",
hmm, these should be guc_info() not gt_info()
so instead of gt we should pass guc to guc_wait_ucode()
> REG_FIELD_GET(GS_MIA_IN_RESET, status),
> REG_FIELD_GET(GS_BOOTROM_MASK, status),
> REG_FIELD_GET(GS_UKERNEL_MASK, status),
> @@ -140,13 +137,13 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
> REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
>
> if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
> - drm_info(drm, "GuC firmware signature verification failed\n");
> + gt_info(gt, "GuC firmware signature verification failed\n");
> ret = -ENOEXEC;
> }
>
> if (REG_FIELD_GET(GS_UKERNEL_MASK, status) == INTEL_GUC_LOAD_STATUS_EXCEPTION) {
> - drm_info(drm, "GuC firmware exception. EIP: %#x\n",
> - intel_uncore_read(uncore, SOFT_SCRATCH(13)));
> + gt_info(gt, "GuC firmware exception. EIP: %#x\n",
> + intel_uncore_read(uncore, SOFT_SCRATCH(13)));
> ret = -ENXIO;
> }
> }
> @@ -194,7 +191,7 @@ int intel_guc_fw_upload(struct intel_guc *guc)
> if (ret)
> goto out;
>
> - ret = guc_wait_ucode(uncore);
> + ret = guc_wait_ucode(gt);
> if (ret)
> goto out;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> index 68331c538b0a7..8c9a020700b52 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> @@ -39,7 +39,6 @@ struct guc_log_section {
> static void _guc_log_init_sizes(struct intel_guc_log *log)
> {
> struct intel_guc *guc = log_to_guc(log);
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> static const struct guc_log_section sections[GUC_LOG_SECTIONS_LIMIT] = {
> {
> GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT,
> @@ -82,12 +81,12 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
> }
>
> if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units))
> - drm_err(&i915->drm, "Mis-aligned GuC log %s size: 0x%X vs 0x%X!",
> + guc_err(guc, "log: Mis-aligned %s size: 0x%X vs 0x%X!\n",
> sections[i].name, log->sizes[i].bytes, log->sizes[i].units);
> log->sizes[i].count = log->sizes[i].bytes / log->sizes[i].units;
>
> if (!log->sizes[i].count) {
> - drm_err(&i915->drm, "Zero GuC log %s size!", sections[i].name);
> + guc_err(guc, "log: zero %s size!\n", sections[i].name);
> } else {
> /* Size is +1 unit */
> log->sizes[i].count--;
> @@ -95,14 +94,14 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
>
> /* Clip to field size */
> if (log->sizes[i].count > sections[i].max) {
> - drm_err(&i915->drm, "GuC log %s size too large: %d vs %d!",
> + guc_err(guc, "log: %s size too large: %d vs %d!\n",
> sections[i].name, log->sizes[i].count + 1, sections[i].max + 1);
> log->sizes[i].count = sections[i].max;
> }
> }
>
> if (log->sizes[GUC_LOG_SECTIONS_CRASH].units != log->sizes[GUC_LOG_SECTIONS_DEBUG].units) {
> - drm_err(&i915->drm, "Unit mis-match for GuC log crash and debug sections: %d vs %d!",
> + guc_err(guc, "log: Unit mis-match for crash and debug sections: %d vs %d!\n",
> log->sizes[GUC_LOG_SECTIONS_CRASH].units,
> log->sizes[GUC_LOG_SECTIONS_DEBUG].units);
> log->sizes[GUC_LOG_SECTIONS_CRASH].units = log->sizes[GUC_LOG_SECTIONS_DEBUG].units;
> @@ -383,7 +382,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
>
> mutex_lock(&log->relay.lock);
>
> - if (WARN_ON(!intel_guc_log_relay_created(log)))
> + if (guc_WARN_ON(log_to_guc(log), !intel_guc_log_relay_created(log)))
hmm, is this WARN_ON really needed here?
> goto out_unlock;
>
> /* Get the pointer to shared GuC log buffer */
> @@ -451,7 +450,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
> write_offset = buffer_size;
> } else if (unlikely((read_offset > buffer_size) ||
> (write_offset > buffer_size))) {
> - DRM_ERROR("invalid log buffer state\n");
> + guc_err(log_to_guc(log), "log: invalid buffer state\n");
> /* copy whole buffer as offsets are unreliable */
> read_offset = 0;
> write_offset = buffer_size;
> @@ -520,7 +519,7 @@ void intel_guc_log_init_early(struct intel_guc_log *log)
> static int guc_log_relay_create(struct intel_guc_log *log)
> {
> struct intel_guc *guc = log_to_guc(log);
> - struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
> + struct intel_gt *gt = guc_to_gt(guc);
> struct rchan *guc_log_relay_chan;
> size_t n_subbufs, subbuf_size;
> int ret;
> @@ -543,11 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log *log)
> n_subbufs = 8;
>
> guc_log_relay_chan = relay_open("guc_log",
> - dev_priv->drm.primary->debugfs_root,
> + gt->i915->drm.primary->debugfs_root,
> subbuf_size, n_subbufs,
> - &relay_callbacks, dev_priv);
> + &relay_callbacks, gt->i915);
> if (!guc_log_relay_chan) {
> - DRM_ERROR("Couldn't create relay chan for GuC logging\n");
> + guc_err(guc, "log: Failed to create relay chan\n");
>
> ret = -ENOMEM;
> return ret;
> @@ -596,7 +595,7 @@ static u32 __get_default_log_level(struct intel_guc_log *log)
> }
>
> if (i915->params.guc_log_level > GUC_LOG_LEVEL_MAX) {
> - DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
> + guc_warn(guc, "log: Incompatible options detected: %s=%d, %s!\n",
> "guc_log_level", i915->params.guc_log_level,
> "verbosity too high");
> return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
> @@ -641,15 +640,15 @@ int intel_guc_log_create(struct intel_guc_log *log)
> log->buf_addr = vaddr;
>
> log->level = __get_default_log_level(log);
> - DRM_DEBUG_DRIVER("guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
> - log->level, str_enabled_disabled(log->level),
> - str_yes_no(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
> - GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
> + guc_dbg(guc, "guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
> + log->level, str_enabled_disabled(log->level),
> + str_yes_no(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
> + GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
>
> return 0;
>
> err:
> - DRM_ERROR("Failed to allocate or map GuC log buffer. %d\n", ret);
> + guc_err(guc, "log: Failed to allocate or map buffer: %d\n", ret);
> return ret;
> }
>
> @@ -687,7 +686,7 @@ int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)
> GUC_LOG_LEVEL_IS_ENABLED(level),
> GUC_LOG_LEVEL_TO_VERBOSITY(level));
> if (ret) {
> - DRM_DEBUG_DRIVER("guc_log_control action failed %d\n", ret);
> + guc_dbg(guc, "guc_log_control action failed %d\n", ret);
> goto out_unlock;
> }
>
> @@ -905,7 +904,7 @@ int intel_guc_log_dump(struct intel_guc_log *log, struct drm_printer *p,
>
> map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
> if (IS_ERR(map)) {
> - DRM_DEBUG("Failed to pin object\n");
> + guc_dbg(guc, "log: Failed to pin buffer object\n");
> drm_puts(p, "(log data unaccessible)\n");
> free_page((unsigned long)page);
> return PTR_ERR(map);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> index b5855091cf6a9..62f3b97111f64 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> @@ -70,13 +70,12 @@ static int __guc_rc_control(struct intel_guc *guc, bool enable)
>
> ret = guc_action_control_gucrc(guc, enable);
> if (ret) {
> - i915_probe_error(guc_to_gt(guc)->i915, "Failed to %s GuC RC (%pe)\n",
> - str_enable_disable(enable), ERR_PTR(ret));
> + guc_probe_error(guc, "RC: Failed to %s: %pe\n",
> + str_enable_disable(enable), ERR_PTR(ret));
in most cases we show error in () so it looks like:
"GT0 GuC RC: Failed to enable (-ENOMEM)"
please don't change that
> return ret;
> }
>
> - drm_info(>->i915->drm, "GuC RC: %s\n",
> - str_enabled_disabled(enable));
> + guc_info(guc, "RC %s\n", str_enabled_disabled(enable));
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index 63464933cbceb..b9ef0b4a123e1 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -171,14 +171,12 @@ static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
> static int slpc_query_task_state(struct intel_guc_slpc *slpc)
> {
> struct intel_guc *guc = slpc_to_guc(slpc);
> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
> u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
> int ret;
>
> ret = guc_action_slpc_query(guc, offset);
> if (unlikely(ret))
> - i915_probe_error(i915, "Failed to query task state (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc, "SLPC: Failed to query task state (%pe)\n", ERR_PTR(ret));
>
> drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
>
> @@ -188,15 +186,14 @@ static int slpc_query_task_state(struct intel_guc_slpc *slpc)
> static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
> {
> struct intel_guc *guc = slpc_to_guc(slpc);
> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
> int ret;
>
> GEM_BUG_ON(id >= SLPC_MAX_PARAM);
>
> ret = guc_action_slpc_set_param(guc, id, value);
> if (ret)
> - i915_probe_error(i915, "Failed to set param %d to %u (%pe)\n",
> - id, value, ERR_PTR(ret));
> + guc_probe_error(guc, "SLPC: Failed to set param %d to %u (%pe)\n",
> + id, value, ERR_PTR(ret));
>
> return ret;
> }
> @@ -236,8 +233,7 @@ static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
> SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
> freq);
> if (ret)
> - drm_notice(&i915->drm,
> - "Failed to send set_param for min freq(%d): (%d)\n",
> + guc_notice(guc, "SLPC: Failed to send set_param for min freq(%d): (%d)\n",
> freq, ret);
> }
>
> @@ -267,7 +263,6 @@ static void slpc_boost_work(struct work_struct *work)
> int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
> {
> struct intel_guc *guc = slpc_to_guc(slpc);
> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
> u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
> int err;
>
> @@ -275,9 +270,8 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>
> err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&slpc->vaddr);
> if (unlikely(err)) {
> - i915_probe_error(i915,
> - "Failed to allocate SLPC struct (err=%pe)\n",
> - ERR_PTR(err));
> + guc_probe_error(guc, "SLPC: Failed to allocate SLPC struct (err=%pe)\n",
while here, drop "err=" just leave "(%pe)"
Michal
> + ERR_PTR(err));
> return err;
> }
>
> @@ -338,7 +332,6 @@ static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset)
>
> static int slpc_reset(struct intel_guc_slpc *slpc)
> {
> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
> struct intel_guc *guc = slpc_to_guc(slpc);
> u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
> int ret;
> @@ -346,15 +339,14 @@ static int slpc_reset(struct intel_guc_slpc *slpc)
> ret = guc_action_slpc_reset(guc, offset);
>
> if (unlikely(ret < 0)) {
> - i915_probe_error(i915, "SLPC reset action failed (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc, "SLPC: Reset action failed (%pe)\n", ERR_PTR(ret));
> return ret;
> }
>
> if (!ret) {
> if (wait_for(slpc_is_running(slpc), SLPC_RESET_TIMEOUT_MS)) {
> - i915_probe_error(i915, "SLPC not enabled! State = %s\n",
> - slpc_get_state_string(slpc));
> + guc_probe_error(guc, "SLPC: Not enabled! State = %s\n",
> + slpc_get_state_string(slpc));
> return -EIO;
> }
> }
> @@ -495,8 +487,8 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
> SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
> val < slpc->rp1_freq);
> if (ret) {
> - i915_probe_error(i915, "Failed to toggle efficient freq (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(slpc_to_guc(slpc), "SLPC: Failed to toggle efficient freq (%pe)\n",
> + ERR_PTR(ret));
> goto out;
> }
>
> @@ -611,15 +603,12 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
>
> static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
> {
> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
> int slpc_min_freq;
> int ret;
>
> ret = intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq);
> if (ret) {
> - drm_err(&i915->drm,
> - "Failed to get min freq: (%d)\n",
> - ret);
> + guc_err(slpc_to_guc(slpc), "SLPC: Failed to get min freq: (%d)\n", ret);
> return false;
> }
>
> @@ -685,8 +674,7 @@ int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode)
> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> ret = slpc_set_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
> if (ret)
> - drm_err(&i915->drm,
> - "Override gucrc mode %d failed %d\n",
> + guc_err(slpc_to_guc(slpc), "SLPC: Override gucrc mode %d failed %d\n",
> mode, ret);
> }
>
> @@ -702,9 +690,7 @@ int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> ret = slpc_unset_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE);
> if (ret)
> - drm_err(&i915->drm,
> - "Unsetting gucrc mode failed %d\n",
> - ret);
> + guc_err(slpc_to_guc(slpc), "SLPC: Unsetting gucrc mode failed %d\n", ret);
> }
>
> return ret;
> @@ -726,6 +712,7 @@ int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
> int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
> {
> struct drm_i915_private *i915 = slpc_to_i915(slpc);
> + struct intel_guc *guc = slpc_to_guc(slpc);
> int ret;
>
> GEM_BUG_ON(!slpc->vma);
> @@ -734,8 +721,8 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>
> ret = slpc_reset(slpc);
> if (unlikely(ret < 0)) {
> - i915_probe_error(i915, "SLPC Reset event returned (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc, "SLPC: Reset event returned (%pe)\n",
> + ERR_PTR(ret));
> return ret;
> }
>
> @@ -753,16 +740,16 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
> /* Set SLPC max limit to RP0 */
> ret = slpc_use_fused_rp0(slpc);
> if (unlikely(ret)) {
> - i915_probe_error(i915, "Failed to set SLPC max to RP0 (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc, "SLPC: Failed to set max to RP0 (%pe)\n",
> + ERR_PTR(ret));
> return ret;
> }
>
> /* Revert SLPC min/max to softlimits if necessary */
> ret = slpc_set_softlimits(slpc);
> if (unlikely(ret)) {
> - i915_probe_error(i915, "Failed to set SLPC softlimits (%pe)\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc, "SLPC: Failed to set softlimits (%pe)\n",
> + ERR_PTR(ret));
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 0a42f1807f52c..da8ab18aa4ce7 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1443,8 +1443,7 @@ static void guc_init_engine_stats(struct intel_guc *guc)
> int ret = guc_action_enable_usage_stats(guc);
>
> if (ret)
> - drm_err(>->i915->drm,
> - "Failed to enable usage stats: %d!\n", ret);
> + guc_err(guc, "Failed to enable usage stats: %d!\n", ret);
> }
> }
>
> @@ -3584,8 +3583,7 @@ static int guc_request_alloc(struct i915_request *rq)
> intel_context_sched_disable_unpin(ce);
> else if (intel_context_is_closed(ce))
> if (wait_for(context_close_done(ce), 1500))
> - drm_warn(&guc_to_gt(guc)->i915->drm,
> - "timed out waiting on context sched close before realloc\n");
> + guc_warn(guc, "timed out waiting on context sched close before realloc\n");
> /*
> * Call pin_guc_id here rather than in the pinning step as with
> * dma_resv, contexts can be repeatedly pinned / unpinned trashing the
> @@ -4350,7 +4348,7 @@ static int __guc_action_set_scheduling_policies(struct intel_guc *guc,
> return ret;
>
> if (ret != policy->count) {
> - drm_warn(&guc_to_gt(guc)->i915->drm, "GuC global scheduler policy processed %d of %d KLVs!",
> + guc_warn(guc, "H2G: global scheduler policy processed %d of %d KLVs!\n",
> ret, policy->count);
> if (ret > policy->count)
> return -EPROTO;
> @@ -4383,9 +4381,9 @@ static int guc_init_global_schedule_policy(struct intel_guc *guc)
>
> ret = __guc_action_set_scheduling_policies(guc, &policy);
> if (ret)
> - i915_probe_error(gt->i915,
> - "Failed to configure global scheduling policies: %pe!\n",
> - ERR_PTR(ret));
> + guc_probe_error(guc,
> + "Failed to configure global scheduling policies: %pe!\n",
> + ERR_PTR(ret));
> }
>
> return ret;
> @@ -4484,21 +4482,18 @@ g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)
> struct intel_context *ce;
>
> if (unlikely(ctx_id >= GUC_MAX_CONTEXT_ID)) {
> - drm_err(&guc_to_gt(guc)->i915->drm,
> - "Invalid ctx_id %u\n", ctx_id);
> + guc_err(guc, "Invalid ctx_id %u\n", ctx_id);
> return NULL;
> }
>
> ce = __get_context(guc, ctx_id);
> if (unlikely(!ce)) {
> - drm_err(&guc_to_gt(guc)->i915->drm,
> - "Context is NULL, ctx_id %u\n", ctx_id);
> + guc_err(guc, "Context is NULL, ctx_id %u\n", ctx_id);
> return NULL;
> }
>
> if (unlikely(intel_context_is_child(ce))) {
> - drm_err(&guc_to_gt(guc)->i915->drm,
> - "Context is child, ctx_id %u\n", ctx_id);
> + guc_err(guc, "Context is child, ctx_id %u\n", ctx_id);
> return NULL;
> }
>
> @@ -4513,7 +4508,7 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
> u32 ctx_id;
>
> if (unlikely(len < 1)) {
> - drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
> + guc_err(guc, "notification: Invalid length %u for deregister done\n", len);
> return -EPROTO;
> }
> ctx_id = msg[0];
> @@ -4565,7 +4560,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
> u32 ctx_id;
>
> if (unlikely(len < 2)) {
> - drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
> + guc_err(guc, "notification: Invalid length %u for sched done\n", len);
> return -EPROTO;
> }
> ctx_id = msg[0];
> @@ -4577,8 +4572,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
> if (unlikely(context_destroyed(ce) ||
> (!context_pending_enable(ce) &&
> !context_pending_disable(ce)))) {
> - drm_err(&guc_to_gt(guc)->i915->drm,
> - "Bad context sched_state 0x%x, ctx_id %u\n",
> + guc_err(guc, "notification: Bad context sched_state 0x%x, ctx_id %u\n",
> ce->guc_state.sched_state, ctx_id);
> return -EPROTO;
> }
> @@ -4666,8 +4660,8 @@ static void guc_handle_context_reset(struct intel_guc *guc,
> capture_error_state(guc, ce);
> guc_context_replay(ce);
> } else {
> - drm_info(&guc_to_gt(guc)->i915->drm,
> - "Ignoring context reset notification of exiting context 0x%04X on %s",
> + guc_info(guc,
> + "Ignoring context reset notification of exiting context 0x%04X on %s\n",
> ce->guc_id.id, ce->engine->name);
> }
> }
> @@ -4680,7 +4674,7 @@ int intel_guc_context_reset_process_msg(struct intel_guc *guc,
> int ctx_id;
>
> if (unlikely(len != 1)) {
> - drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
> + guc_err(guc, "notification: Invalid length %u for context reset\n", len);
> return -EPROTO;
> }
>
> @@ -4713,13 +4707,13 @@ int intel_guc_error_capture_process_msg(struct intel_guc *guc,
> u32 status;
>
> if (unlikely(len != 1)) {
> - drm_dbg(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
> + guc_err(guc, "notification: Invalid length %u for error capture\n", len);
> return -EPROTO;
> }
>
> status = msg[0] & INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK;
> if (status == INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE)
> - drm_warn(&guc_to_gt(guc)->i915->drm, "G2H-Error capture no space");
> + guc_warn(guc, "notification: Error capture buffer overflow\n");
>
> intel_guc_capture_process(guc);
>
> @@ -4762,13 +4756,12 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> const u32 *msg, u32 len)
> {
> struct intel_engine_cs *engine;
> - struct intel_gt *gt = guc_to_gt(guc);
> u8 guc_class, instance;
> u32 reason;
> unsigned long flags;
>
> if (unlikely(len != 3)) {
> - drm_err(>->i915->drm, "Invalid length %u", len);
> + guc_err(guc, "notification: Invalid length %u for engine failure\n", len);
> return -EPROTO;
> }
>
> @@ -4778,8 +4771,8 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
>
> engine = intel_guc_lookup_engine(guc, guc_class, instance);
> if (unlikely(!engine)) {
> - drm_err(>->i915->drm,
> - "Invalid engine %d:%d", guc_class, instance);
> + guc_err(guc, "notification: Invalid engine %d:%d for engine failure\n",
> + guc_class, instance);
> return -EPROTO;
> }
>
> @@ -4787,7 +4780,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> * This is an unexpected failure of a hardware feature. So, log a real
> * error message not just the informational that comes with the reset.
> */
> - drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X",
> + guc_err(guc, "notification: Engine reset request failed on %d:%d (%s) because 0x%08X\n",
> guc_class, instance, engine->name, reason);
>
> spin_lock_irqsave(&guc->submission_state.lock, flags);
> @@ -5297,6 +5290,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
> unsigned long flags)
> {
> struct guc_virtual_engine *ve;
> + struct intel_gt *gt;
> struct intel_guc *guc;
> unsigned int n;
> int err;
> @@ -5305,10 +5299,11 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
> if (!ve)
> return ERR_PTR(-ENOMEM);
>
> - guc = &siblings[0]->gt->uc.guc;
> + gt = siblings[0]->gt;
> + guc = >->uc.guc;
>
> ve->base.i915 = siblings[0]->i915;
> - ve->base.gt = siblings[0]->gt;
> + ve->base.gt = gt;
> ve->base.uncore = siblings[0]->uncore;
> ve->base.id = -1;
>
> @@ -5336,8 +5331,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
>
> GEM_BUG_ON(!is_power_of_2(sibling->mask));
> if (sibling->mask & ve->base.mask) {
> - DRM_DEBUG("duplicate %s entry in load balancer\n",
> - sibling->name);
> + guc_dbg(guc, "Duplicate %s entry in load balancer\n", sibling->name);
> err = -EINVAL;
> goto err_put;
> }
> @@ -5346,8 +5340,8 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
> ve->base.logical_mask |= sibling->logical_mask;
>
> if (n != 0 && ve->base.class != sibling->class) {
> - DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n",
> - sibling->class, ve->base.class);
> + guc_dbg(guc, "Invalid mixing of engine class, sibling %d, already %d\n",
> + sibling->class, ve->base.class);
> err = -EINVAL;
> goto err_put;
> } else if (n == 0) {
> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> index e28518fe8b908..d588c32d65c54 100644
> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> @@ -65,7 +65,7 @@ static int intel_guc_scrub_ctbs(void *arg)
> ce = intel_context_create(engine);
> if (IS_ERR(ce)) {
> ret = PTR_ERR(ce);
> - drm_err(>->i915->drm, "Failed to create context, %d: %d\n", i, ret);
> + gt_err(gt, "Failed to create context, %d: %d\n", i, ret);
> goto err;
> }
>
> @@ -86,7 +86,7 @@ static int intel_guc_scrub_ctbs(void *arg)
>
> if (IS_ERR(rq)) {
> ret = PTR_ERR(rq);
> - drm_err(>->i915->drm, "Failed to create request, %d: %d\n", i, ret);
> + gt_err(gt, "Failed to create request, %d: %d\n", i, ret);
> goto err;
> }
>
> @@ -96,7 +96,7 @@ static int intel_guc_scrub_ctbs(void *arg)
> for (i = 0; i < 3; ++i) {
> ret = i915_request_wait(last[i], 0, HZ);
> if (ret < 0) {
> - drm_err(>->i915->drm, "Last request failed to complete: %d\n", ret);
> + gt_err(gt, "Last request failed to complete: %d\n", ret);
> goto err;
> }
> i915_request_put(last[i]);
> @@ -113,7 +113,7 @@ static int intel_guc_scrub_ctbs(void *arg)
> /* GT will not idle if G2H are lost */
> ret = intel_gt_wait_for_idle(gt, HZ);
> if (ret < 0) {
> - drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
> + gt_err(gt, "GT failed to idle: %d\n", ret);
> goto err;
> }
>
> @@ -153,7 +153,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>
> ce = kcalloc(GUC_MAX_CONTEXT_ID, sizeof(*ce), GFP_KERNEL);
> if (!ce) {
> - drm_err(>->i915->drm, "Context array allocation failed\n");
> + guc_err(guc, "Context array allocation failed\n");
> return -ENOMEM;
> }
>
> @@ -167,24 +167,24 @@ static int intel_guc_steal_guc_ids(void *arg)
> if (IS_ERR(ce[context_index])) {
> ret = PTR_ERR(ce[context_index]);
> ce[context_index] = NULL;
> - drm_err(>->i915->drm, "Failed to create context: %d\n", ret);
> + guc_err(guc, "Failed to create context: %d\n", ret);
> goto err_wakeref;
> }
> ret = igt_spinner_init(&spin, engine->gt);
> if (ret) {
> - drm_err(>->i915->drm, "Failed to create spinner: %d\n", ret);
> + guc_err(guc, "Failed to create spinner: %d\n", ret);
> goto err_contexts;
> }
> spin_rq = igt_spinner_create_request(&spin, ce[context_index],
> MI_ARB_CHECK);
> if (IS_ERR(spin_rq)) {
> ret = PTR_ERR(spin_rq);
> - drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
> + guc_err(guc, "Failed to create spinner request: %d\n", ret);
> goto err_contexts;
> }
> ret = request_add_spin(spin_rq, &spin);
> if (ret) {
> - drm_err(>->i915->drm, "Failed to add Spinner request: %d\n", ret);
> + guc_err(guc, "Failed to add Spinner request: %d\n", ret);
> goto err_spin_rq;
> }
>
> @@ -194,7 +194,7 @@ static int intel_guc_steal_guc_ids(void *arg)
> if (IS_ERR(ce[context_index])) {
> ret = PTR_ERR(ce[context_index--]);
> ce[context_index] = NULL;
> - drm_err(>->i915->drm, "Failed to create context: %d\n", ret);
> + guc_err(guc, "Failed to create context: %d\n", ret);
> goto err_spin_rq;
> }
>
> @@ -203,7 +203,7 @@ static int intel_guc_steal_guc_ids(void *arg)
> ret = PTR_ERR(rq);
> rq = NULL;
> if (ret != -EAGAIN) {
> - drm_err(>->i915->drm, "Failed to create request, %d: %d\n",
> + guc_err(guc, "Failed to create request, %d: %d\n",
> context_index, ret);
> goto err_spin_rq;
> }
> @@ -218,7 +218,7 @@ static int intel_guc_steal_guc_ids(void *arg)
> igt_spinner_end(&spin);
> ret = intel_selftest_wait_for_rq(spin_rq);
> if (ret) {
> - drm_err(>->i915->drm, "Spin request failed to complete: %d\n", ret);
> + guc_err(guc, "Spin request failed to complete: %d\n", ret);
> i915_request_put(last);
> goto err_spin_rq;
> }
> @@ -230,7 +230,7 @@ static int intel_guc_steal_guc_ids(void *arg)
> ret = i915_request_wait(last, 0, HZ * 30);
> i915_request_put(last);
> if (ret < 0) {
> - drm_err(>->i915->drm, "Last request failed to complete: %d\n", ret);
> + guc_err(guc, "Last request failed to complete: %d\n", ret);
> goto err_spin_rq;
> }
>
> @@ -238,7 +238,7 @@ static int intel_guc_steal_guc_ids(void *arg)
> rq = nop_user_request(ce[context_index], NULL);
> if (IS_ERR(rq)) {
> ret = PTR_ERR(rq);
> - drm_err(>->i915->drm, "Failed to steal guc_id, %d: %d\n", context_index, ret);
> + guc_err(guc, "Failed to steal guc_id, %d: %d\n", context_index, ret);
> goto err_spin_rq;
> }
>
> @@ -246,20 +246,20 @@ static int intel_guc_steal_guc_ids(void *arg)
> ret = i915_request_wait(rq, 0, HZ);
> i915_request_put(rq);
> if (ret < 0) {
> - drm_err(>->i915->drm, "Request with stolen guc_id failed to complete: %d\n", ret);
> + guc_err(guc, "Request with stolen guc_id failed to complete: %d\n", ret);
> goto err_spin_rq;
> }
>
> /* Wait for idle */
> ret = intel_gt_wait_for_idle(gt, HZ * 30);
> if (ret < 0) {
> - drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
> + guc_err(guc, "GT failed to idle: %d\n", ret);
> goto err_spin_rq;
> }
>
> /* Verify a guc_id was stolen */
> if (guc->number_guc_id_stolen == number_guc_id_stolen) {
> - drm_err(>->i915->drm, "No guc_id was stolen");
> + guc_err(guc, "No guc_id was stolen\n");
> ret = -EINVAL;
> } else {
> ret = 0;
> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
> index d91b58f704039..07018ec75c21f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
> @@ -45,7 +45,7 @@ static int intel_hang_guc(void *arg)
>
> ctx = kernel_context(gt->i915, NULL);
> if (IS_ERR(ctx)) {
> - drm_err(>->i915->drm, "Failed get kernel context: %ld\n", PTR_ERR(ctx));
> + gt_err(gt, "Failed get kernel context: %ld\n", PTR_ERR(ctx));
> return PTR_ERR(ctx);
> }
>
> @@ -54,7 +54,7 @@ static int intel_hang_guc(void *arg)
> ce = intel_context_create(engine);
> if (IS_ERR(ce)) {
> ret = PTR_ERR(ce);
> - drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
> + gt_err(gt, "Failed to create spinner request: %d\n", ret);
> goto err;
> }
>
> @@ -63,13 +63,13 @@ static int intel_hang_guc(void *arg)
> old_beat = engine->props.heartbeat_interval_ms;
> ret = intel_engine_set_heartbeat(engine, BEAT_INTERVAL);
> if (ret) {
> - drm_err(>->i915->drm, "Failed to boost heatbeat interval: %d\n", ret);
> + gt_err(gt, "Failed to boost heatbeat interval: %d\n", ret);
> goto err;
> }
>
> ret = igt_spinner_init(&spin, engine->gt);
> if (ret) {
> - drm_err(>->i915->drm, "Failed to create spinner: %d\n", ret);
> + gt_err(gt, "Failed to create spinner: %d\n", ret);
> goto err;
> }
>
> @@ -77,28 +77,28 @@ static int intel_hang_guc(void *arg)
> intel_context_put(ce);
> if (IS_ERR(rq)) {
> ret = PTR_ERR(rq);
> - drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
> + gt_err(gt, "Failed to create spinner request: %d\n", ret);
> goto err_spin;
> }
>
> ret = request_add_spin(rq, &spin);
> if (ret) {
> i915_request_put(rq);
> - drm_err(>->i915->drm, "Failed to add Spinner request: %d\n", ret);
> + gt_err(gt, "Failed to add Spinner request: %d\n", ret);
> goto err_spin;
> }
>
> ret = intel_reset_guc(gt);
> if (ret) {
> i915_request_put(rq);
> - drm_err(>->i915->drm, "Failed to reset GuC, ret = %d\n", ret);
> + gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
> goto err_spin;
> }
>
> guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
> if (!(guc_status & GS_MIA_IN_RESET)) {
> i915_request_put(rq);
> - drm_err(>->i915->drm, "GuC failed to reset: status = 0x%08X\n", guc_status);
> + gt_err(gt, "GuC failed to reset: status = 0x%08X\n", guc_status);
> ret = -EIO;
> goto err_spin;
> }
> @@ -107,12 +107,12 @@ static int intel_hang_guc(void *arg)
> ret = intel_selftest_wait_for_rq(rq);
> i915_request_put(rq);
> if (ret) {
> - drm_err(>->i915->drm, "Request failed to complete: %d\n", ret);
> + gt_err(gt, "Request failed to complete: %d\n", ret);
> goto err_spin;
> }
>
> if (i915_reset_count(global) == reset_count) {
> - drm_err(>->i915->drm, "Failed to record a GPU reset\n");
> + gt_err(gt, "Failed to record a GPU reset\n");
> ret = -EINVAL;
> goto err_spin;
> }
> @@ -132,7 +132,7 @@ static int intel_hang_guc(void *arg)
> ret = intel_selftest_wait_for_rq(rq);
> i915_request_put(rq);
> if (ret) {
> - drm_err(>->i915->drm, "No-op failed to complete: %d\n", ret);
> + gt_err(gt, "No-op failed to complete: %d\n", ret);
> goto err;
> }
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
> index d17982c36d256..04e28735a2ee6 100644
> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
> @@ -115,30 +115,30 @@ static int __intel_guc_multi_lrc_basic(struct intel_gt *gt, unsigned int class)
>
> parent = multi_lrc_create_parent(gt, class, 0);
> if (IS_ERR(parent)) {
> - drm_err(>->i915->drm, "Failed creating contexts: %ld", PTR_ERR(parent));
> + gt_err(gt, "Failed creating contexts: %ld", PTR_ERR(parent));
> return PTR_ERR(parent);
> } else if (!parent) {
> - drm_dbg(>->i915->drm, "Not enough engines in class: %d", class);
> + gt_dbg(gt, "Not enough engines in class: %d", class);
> return 0;
> }
>
> rq = multi_lrc_nop_request(parent);
> if (IS_ERR(rq)) {
> ret = PTR_ERR(rq);
> - drm_err(>->i915->drm, "Failed creating requests: %d", ret);
> + gt_err(gt, "Failed creating requests: %d", ret);
> goto out;
> }
>
> ret = intel_selftest_wait_for_rq(rq);
> if (ret)
> - drm_err(>->i915->drm, "Failed waiting on request: %d", ret);
> + gt_err(gt, "Failed waiting on request: %d", ret);
>
> i915_request_put(rq);
>
> if (ret >= 0) {
> ret = intel_gt_wait_for_idle(gt, HZ * 5);
> if (ret < 0)
> - drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
> + gt_err(gt, "GT failed to idle: %d\n", ret);
> }
>
> out:
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v2 3/5] drm/i915/guc: Add GuC specific debug print wrappers
2022-11-22 17:42 ` [Intel-gfx] " Michal Wajdeczko
@ 2022-11-23 0:56 ` John Harrison
-1 siblings, 0 replies; 51+ messages in thread
From: John Harrison @ 2022-11-23 0:56 UTC (permalink / raw)
To: Michal Wajdeczko, Intel-GFX; +Cc: DRI-Devel
On 11/22/2022 09:42, Michal Wajdeczko wrote:
> On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> Create a set of GuC printers and start using them.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 ++++------
>> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++++++++++
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +--
>> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 +++++---------
>> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +++---
>> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++++++-----
>> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +--
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 +++++++---------
>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++++++++----------
>> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +++++-----
>> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +++----
>> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +--
>> 12 files changed, 179 insertions(+), 190 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> index 52aede324788e..d9972510ee29b 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> @@ -94,8 +94,8 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
>> assert_rpm_wakelock_held(>->i915->runtime_pm);
>>
>> spin_lock_irq(gt->irq_lock);
>> - WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
>> - gt->pm_guc_events);
>> + guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
>> + gt->pm_guc_events);
>> gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
>> spin_unlock_irq(gt->irq_lock);
>>
>> @@ -339,7 +339,7 @@ static void guc_init_params(struct intel_guc *guc)
>> params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
>>
>> for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
>> - DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
>> + guc_dbg(guc, "init param[%2d] = %#x\n", i, params[i]);
>> }
>>
>> /*
>> @@ -451,7 +451,7 @@ int intel_guc_init(struct intel_guc *guc)
>> intel_uc_fw_fini(&guc->fw);
>> out:
>> intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
>> - i915_probe_error(gt->i915, "failed with %d\n", ret);
>> + guc_probe_error(guc, "init failed with %d\n", ret);
>> return ret;
>> }
>>
>> @@ -484,7 +484,6 @@ void intel_guc_fini(struct intel_guc *guc)
>> int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
>> u32 *response_buf, u32 response_buf_size)
>> {
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
>> u32 header;
>> int i;
>> @@ -519,8 +518,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
>> 10, 10, &header);
>> if (unlikely(ret)) {
>> timeout:
>> - drm_err(&i915->drm, "mmio request %#x: no reply %x\n",
>> - request[0], header);
>> + guc_err(guc, "mmio request %#x: no reply %x\n", request[0], header);
>> goto out;
>> }
>>
>> @@ -541,8 +539,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
>> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
>> u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
>>
>> - drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n",
>> - request[0], reason);
>> + guc_dbg(guc, "mmio request %#x: retrying, reason %u\n", request[0], reason);
>> goto retry;
>> }
>>
>> @@ -550,16 +547,14 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
>> u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
>> u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
>>
>> - drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n",
>> - request[0], error, hint);
>> + guc_err(guc, "mmio request %#x: failure %x/%u\n", request[0], error, hint);
>> ret = -ENXIO;
>> goto out;
>> }
>>
>> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) {
>> proto:
>> - drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n",
>> - request[0], header);
>> + guc_err(guc, "mmio request %#x: unexpected reply %#x\n", request[0], header);
>> ret = -EPROTO;
>> goto out;
>> }
>> @@ -601,9 +596,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
>> msg = payload[0] & guc->msg_enabled_mask;
>>
>> if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
>> - drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC crash dump notification!\n");
>> + guc_err(guc, "early notification: Crash dump!\n");
>> if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
>> - drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC exception notification!\n");
>> + guc_err(guc, "early notification: Exception!\n");
>>
>> return 0;
>> }
>> @@ -657,7 +652,7 @@ int intel_guc_suspend(struct intel_guc *guc)
>> */
>> ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
>> if (ret)
>> - DRM_ERROR("GuC suspend: RESET_CLIENT action failed with error %d!\n", ret);
>> + guc_err(guc, "suspend: RESET_CLIENT action failed with error %d!\n", ret);
>> }
>>
>> /* Signal that the GuC isn't running. */
>> @@ -832,12 +827,11 @@ static int __guc_action_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 va
>>
>> static int __guc_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
>> {
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> int err = __guc_action_self_cfg(guc, key, len, value);
>>
>> if (unlikely(err))
>> - i915_probe_error(i915, "Unsuccessful self-config (%pe) key %#hx value %#llx\n",
>> - ERR_PTR(err), key, value);
>> + guc_probe_error(guc, "self-config; Unsuccessful (%pe) key %#hx value %#llx\n",
> self-config:
>
>> + ERR_PTR(err), key, value);
>> return err;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> index 1bb3f98292866..8c02d22bc7e82 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> @@ -24,6 +24,41 @@
>> struct __guc_ads_blob;
>> struct intel_guc_state_capture;
>>
>> +#define guc_err(_guc, _fmt, ...) \
>> + gt_err(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
>> +
>> +#define guc_warn(_guc, _fmt, ...) \
>> + gt_warn(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
>> +
>> +#define guc_notice(_guc, _fmt, ...) \
>> + gt_notice(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
>> +
>> +#define guc_info(_guc, _fmt, ...) \
>> + gt_info(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
>> +
>> +#define guc_dbg(_guc, _fmt, ...) \
>> + gt_dbg(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
>> +
>> +#define guc_probe_error(_guc, _fmt, ...) \
>> + do { \
>> + if (i915_error_injected()) \
>> + guc_dbg(_guc, _fmt, ##__VA_ARGS__); \
>> + else \
>> + guc_err(_guc, _fmt, ##__VA_ARGS__); \
>> + } while (0)
> use gt_probe_error ?
Brain fade, I think. For some reason I was thinking that wouldn't work,
but it clearly does.
>
>> +
>> +#define guc_WARN_ON(_guc, _condition) \
>> + guc_WARN(_guc, _condition, "%s", "guc_WARN_ON(" __stringify(_condition) ")")
>> +
>> +#define guc_WARN_ON_ONCE(_guc, _condition) \
>> + guc_WARN_ONCE(_guc, _condition, "%s", "guc_WARN_ON_ONCE(" __stringify(_condition) ")")
>> +
>> +#define guc_WARN(_guc, _condition, _fmt, ...) \
>> + gt_WARN(guc_to_gt(_guc), _condition, "GuC " _fmt, ##__VA_ARGS__)
>> +
>> +#define guc_WARN_ONCE(_guc, _condition, _fmt, ...) \
>> + gt_WARN_ONCE(guc_to_gt(_guc), _condition, "GuC " _fmt, ##__VA_ARGS__)
>> +
>> /**
>> * struct intel_guc - Top level structure of GuC.
>> *
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> index a7f737c4792e2..fa9a31176b4a7 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> @@ -427,7 +427,7 @@ static long guc_mmio_reg_state_create(struct intel_guc *guc)
>>
>> guc->ads_regset = temp_set.storage;
>>
>> - drm_dbg(&guc_to_gt(guc)->i915->drm, "Used %zu KB for temporary ADS regset\n",
>> + guc_dbg(guc, "used %zu KB for temporary ADS regset\n",
>> (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
>>
>> return total * sizeof(struct guc_mmio_reg);
>> @@ -621,8 +621,7 @@ static void guc_init_golden_context(struct intel_guc *guc)
>>
>> engine = find_engine_state(gt, engine_class);
>> if (!engine) {
>> - drm_err(>->i915->drm, "No engine state recorded for class %d!\n",
>> - engine_class);
>> + guc_err(guc, "No engine state recorded for class %d!\n", engine_class);
>> ads_blob_write(guc, ads.eng_state_size[guc_class], 0);
>> ads_blob_write(guc, ads.golden_context_lrca[guc_class], 0);
>> continue;
>> @@ -646,7 +645,6 @@ static int
>> guc_capture_prep_lists(struct intel_guc *guc)
>> {
>> struct intel_gt *gt = guc_to_gt(guc);
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0;
>> struct guc_gt_system_info local_info;
>> struct iosys_map info_map;
>> @@ -751,7 +749,7 @@ guc_capture_prep_lists(struct intel_guc *guc)
>> }
>>
>> if (guc->ads_capture_size && guc->ads_capture_size != PAGE_ALIGN(total_size))
>> - drm_warn(&i915->drm, "GuC->ADS->Capture alloc size changed from %d to %d\n",
>> + guc_warn(guc, "capture alloc size changed from %d to %d\n",
>> guc->ads_capture_size, PAGE_ALIGN(total_size));
>>
>> return PAGE_ALIGN(total_size);
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>> index 1d49a7ec0bd8f..a8876178da6ff 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>> @@ -353,7 +353,6 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
>> u32 ipver)
>> {
>> struct intel_gt *gt = guc_to_gt(guc);
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> struct sseu_dev_info *sseu;
>> int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0;
>> const struct __guc_mmio_reg_descr_group *list;
>> @@ -402,7 +401,7 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
>> }
>> }
>>
>> - drm_dbg(&i915->drm, "GuC-capture found %d-ext-regs.\n", num_tot_regs);
>> + guc_dbg(guc, "capture found %d ext-regs.\n", num_tot_regs);
>> guc->capture->extlists = extlists;
>> }
>>
>> @@ -477,7 +476,6 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
>> struct guc_mmio_reg *ptr, u16 num_entries)
>> {
>> u32 i = 0, j = 0;
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists;
>> struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists;
>> const struct __guc_mmio_reg_descr_group *match;
>> @@ -509,8 +507,7 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
>> }
>> }
>> if (i < num_entries)
>> - drm_dbg(&i915->drm, "GuC-capture: Init reglist short %d out %d.\n",
>> - (int)i, (int)num_entries);
>> + guc_dbg(guc, "capture: Init reglist short %d out %d.\n", i, num_entries);
>>
>> return 0;
>> }
>> @@ -540,12 +537,11 @@ guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
>> size_t *size, bool is_purpose_est)
>> {
>> struct intel_guc_state_capture *gc = guc->capture;
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
>> int num_regs;
>>
>> if (!gc->reglists) {
>> - drm_warn(&i915->drm, "GuC-capture: No reglist on this device\n");
>> + guc_warn(guc, "capture: No reglist on this device\n");
>> return -ENODEV;
>> }
>>
>> @@ -557,9 +553,9 @@ guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
>> if (!is_purpose_est && owner == GUC_CAPTURE_LIST_INDEX_PF &&
>> !guc_capture_get_one_list(gc->reglists, owner, type, classid)) {
>> if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL)
>> - drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist Global!\n");
>> + guc_warn(guc, "capture: Missing reglist: Global!\n");
>> else
>> - drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist %s(%u):%s(%u)!\n",
>> + guc_warn(guc, "capture: Missing reglist: %s(%u):%s(%u)!\n",
>> __stringify_type(type), type,
>> __stringify_engclass(classid), classid);
>> return -ENODATA;
>> @@ -592,7 +588,6 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classi
>> {
>> struct intel_guc_state_capture *gc = guc->capture;
>> struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> struct guc_debug_capture_list *listnode;
>> int ret, num_regs;
>> u8 *caplist, *tmp;
>> @@ -623,7 +618,7 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classi
>>
>> caplist = kzalloc(size, GFP_KERNEL);
>> if (!caplist) {
>> - drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached caplist");
>> + guc_dbg(guc, "capture: Failed to alloc cached caplist\n");
>> return -ENOMEM;
>> }
>>
>> @@ -653,7 +648,6 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
>> void **outptr, size_t *size)
>> {
>> struct intel_guc_state_capture *gc = guc->capture;
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> int tmp = sizeof(u32) * 4;
>> void *null_header;
>>
>> @@ -665,7 +659,7 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
>>
>> null_header = kzalloc(tmp, GFP_KERNEL);
>> if (!null_header) {
>> - drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached nulllist");
>> + guc_dbg(guc, "capture: Failed to alloc cached null list\n");
>> return -ENOMEM;
>> }
>>
>> @@ -727,7 +721,6 @@ guc_capture_output_min_size_est(struct intel_guc *guc)
>>
>> static void check_guc_capture_size(struct intel_guc *guc)
>> {
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> int min_size = guc_capture_output_min_size_est(guc);
>> int spare_size = min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER;
>> u32 buffer_size = intel_guc_log_section_size_capture(&guc->log);
>> @@ -741,13 +734,13 @@ static void check_guc_capture_size(struct intel_guc *guc)
>> * INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE.
>> */
>> if (min_size < 0)
>> - drm_warn(&i915->drm, "Failed to calculate GuC error state capture buffer minimum size: %d!\n",
>> + guc_warn(guc, "error state capture buffer minimum size calculation failed: %d!\n",
>> min_size);
>> else if (min_size > buffer_size)
>> - drm_warn(&i915->drm, "GuC error state capture buffer maybe small: %d < %d\n",
>> + guc_warn(guc, "error state capture buffer maybe small: %d < %d\n",
>> buffer_size, min_size);
>> else if (spare_size > buffer_size)
>> - drm_dbg(&i915->drm, "GuC error state capture buffer lacks spare size: %d < %d (min = %d)\n",
>> + guc_dbg(guc, "error state capture buffer lacks spare size: %d < %d (min = %d)\n",
>> buffer_size, spare_size, min_size);
>> }
>>
>> @@ -848,7 +841,6 @@ static int
>> guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *buf,
>> u32 *dw)
>> {
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> int tries = 2;
>> int avail = 0;
>> u32 *src_data;
>> @@ -865,7 +857,7 @@ guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *
>> return 4;
>> }
>> if (avail)
>> - drm_dbg(&i915->drm, "GuC-Cap-Logs not dword aligned, skipping.\n");
>> + guc_dbg(guc, "capture: Log not dword aligned, skipping.\n");
>> buf->rd = 0;
>> }
>>
>> @@ -1118,13 +1110,12 @@ static void
>> __guc_capture_create_prealloc_nodes(struct intel_guc *guc)
>> {
>> struct __guc_capture_parsed_output *node = NULL;
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> int i;
>>
>> for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) {
>> node = guc_capture_alloc_one_node(guc);
>> if (!node) {
>> - drm_warn(&i915->drm, "GuC Capture pre-alloc-cache failure\n");
>> + guc_warn(guc, "capture pre-alloc-cache failure\n");
>> /* dont free the priors, use what we got and cleanup at shutdown */
>> return;
>> }
>> @@ -1169,7 +1160,6 @@ guc_capture_create_prealloc_nodes(struct intel_guc *guc)
>> static int
>> guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstate *buf)
>> {
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> struct guc_state_capture_group_header_t ghdr = {0};
>> struct guc_state_capture_header_t hdr = {0};
>> struct __guc_capture_parsed_output *node = NULL;
>> @@ -1183,7 +1173,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
>> if (!i)
>> return -ENODATA;
>> if (i % sizeof(u32)) {
>> - drm_warn(&i915->drm, "GuC Capture new entries unaligned\n");
>> + guc_warn(guc, "capture new entries unaligned\n");
>> ret = -EIO;
>> goto bailout;
>> }
>> @@ -1301,8 +1291,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
>> break;
>> }
>> if (datatype != GUC_CAPTURE_LIST_TYPE_GLOBAL)
>> - drm_dbg(&i915->drm, "GuC Capture missing global dump: %08x!\n",
>> - datatype);
>> + guc_dbg(guc, "cpture missing global dump: %08x!\n", datatype);
> typo
>
>> }
>> node->is_partial = is_partial;
>> node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner);
>> @@ -1322,7 +1311,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
>>
>> numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios);
>> if (numregs > guc->capture->max_mmio_per_node) {
>> - drm_dbg(&i915->drm, "GuC Capture list extraction clipped by prealloc!\n");
>> + guc_dbg(guc, "capture list extraction clipped by prealloc!\n");
>> numregs = guc->capture->max_mmio_per_node;
>> }
>> node->reginfo[datatype].num_regs = numregs;
>> @@ -1367,7 +1356,6 @@ static void __guc_capture_process_output(struct intel_guc *guc)
>> {
>> unsigned int buffer_size, read_offset, write_offset, full_count;
>> struct intel_uc *uc = container_of(guc, typeof(*uc), guc);
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> struct guc_log_buffer_state log_buf_state_local;
>> struct guc_log_buffer_state *log_buf_state;
>> struct __guc_capture_bufstate buf;
>> @@ -1403,7 +1391,7 @@ static void __guc_capture_process_output(struct intel_guc *guc)
>> write_offset = buffer_size;
>> } else if (unlikely((read_offset > buffer_size) ||
>> (write_offset > buffer_size))) {
>> - drm_err(&i915->drm, "invalid GuC log capture buffer state!\n");
>> + guc_err(guc, "capture: invalid buffer state!\n");
>> /* copy whole buffer as offsets are unreliable */
>> read_offset = 0;
>> write_offset = buffer_size;
>> @@ -1586,13 +1574,11 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
>> struct intel_context *ce)
>> {
>> struct __guc_capture_parsed_output *n, *ntmp;
>> - struct drm_i915_private *i915;
>> struct intel_guc *guc;
>>
>> if (!gt || !ee || !ce)
>> return;
>>
>> - i915 = gt->i915;
>> guc = >->uc.guc;
>> if (!guc->capture)
>> return;
>> @@ -1615,7 +1601,7 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
>> return;
>> }
>> }
>> - drm_dbg(&i915->drm, "GuC capture can't match ee to node\n");
>> + guc_dbg(guc, "capture can't match ee to node\n");
>> }
>>
>> void intel_guc_capture_process(struct intel_guc *guc)
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> index 5b86b2e286e07..4a2811aa3d5e1 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> @@ -103,8 +103,9 @@ static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
>> return uk_val == INTEL_GUC_LOAD_STATUS_READY;
>> }
>>
>> -static int guc_wait_ucode(struct intel_uncore *uncore)
>> +static int guc_wait_ucode(struct intel_gt *gt)
>> {
>> + struct intel_uncore *uncore = gt->uncore;
>> u32 status;
>> int ret;
>>
>> @@ -127,12 +128,8 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
>> */
>> ret = wait_for(guc_ready(uncore, &status), 200);
>> if (ret) {
>> - struct drm_device *drm = &uncore->i915->drm;
>> -
>> - drm_info(drm, "GuC load failed: status = 0x%08X\n", status);
>> - drm_info(drm, "GuC load failed: status: Reset = %d, "
>> - "BootROM = 0x%02X, UKernel = 0x%02X, "
>> - "MIA = 0x%02X, Auth = 0x%02X\n",
>> + gt_info(gt, "GuC load failed: status = 0x%08X\n", status);
>> + gt_info(gt, "GuC load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n",
> hmm, these should be guc_info() not gt_info()
>
> so instead of gt we should pass guc to guc_wait_ucode()
I was trying to not re-work any actual code if possible. But yeah, it
makes sense to switch the parameter here. The calling function is all
'guc' object based anyway.
>
>> REG_FIELD_GET(GS_MIA_IN_RESET, status),
>> REG_FIELD_GET(GS_BOOTROM_MASK, status),
>> REG_FIELD_GET(GS_UKERNEL_MASK, status),
>> @@ -140,13 +137,13 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
>> REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
>>
>> if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
>> - drm_info(drm, "GuC firmware signature verification failed\n");
>> + gt_info(gt, "GuC firmware signature verification failed\n");
>> ret = -ENOEXEC;
>> }
>>
>> if (REG_FIELD_GET(GS_UKERNEL_MASK, status) == INTEL_GUC_LOAD_STATUS_EXCEPTION) {
>> - drm_info(drm, "GuC firmware exception. EIP: %#x\n",
>> - intel_uncore_read(uncore, SOFT_SCRATCH(13)));
>> + gt_info(gt, "GuC firmware exception. EIP: %#x\n",
>> + intel_uncore_read(uncore, SOFT_SCRATCH(13)));
>> ret = -ENXIO;
>> }
>> }
>> @@ -194,7 +191,7 @@ int intel_guc_fw_upload(struct intel_guc *guc)
>> if (ret)
>> goto out;
>>
>> - ret = guc_wait_ucode(uncore);
>> + ret = guc_wait_ucode(gt);
>> if (ret)
>> goto out;
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> index 68331c538b0a7..8c9a020700b52 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> @@ -39,7 +39,6 @@ struct guc_log_section {
>> static void _guc_log_init_sizes(struct intel_guc_log *log)
>> {
>> struct intel_guc *guc = log_to_guc(log);
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> static const struct guc_log_section sections[GUC_LOG_SECTIONS_LIMIT] = {
>> {
>> GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT,
>> @@ -82,12 +81,12 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
>> }
>>
>> if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units))
>> - drm_err(&i915->drm, "Mis-aligned GuC log %s size: 0x%X vs 0x%X!",
>> + guc_err(guc, "log: Mis-aligned %s size: 0x%X vs 0x%X!\n",
>> sections[i].name, log->sizes[i].bytes, log->sizes[i].units);
>> log->sizes[i].count = log->sizes[i].bytes / log->sizes[i].units;
>>
>> if (!log->sizes[i].count) {
>> - drm_err(&i915->drm, "Zero GuC log %s size!", sections[i].name);
>> + guc_err(guc, "log: zero %s size!\n", sections[i].name);
>> } else {
>> /* Size is +1 unit */
>> log->sizes[i].count--;
>> @@ -95,14 +94,14 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
>>
>> /* Clip to field size */
>> if (log->sizes[i].count > sections[i].max) {
>> - drm_err(&i915->drm, "GuC log %s size too large: %d vs %d!",
>> + guc_err(guc, "log: %s size too large: %d vs %d!\n",
>> sections[i].name, log->sizes[i].count + 1, sections[i].max + 1);
>> log->sizes[i].count = sections[i].max;
>> }
>> }
>>
>> if (log->sizes[GUC_LOG_SECTIONS_CRASH].units != log->sizes[GUC_LOG_SECTIONS_DEBUG].units) {
>> - drm_err(&i915->drm, "Unit mis-match for GuC log crash and debug sections: %d vs %d!",
>> + guc_err(guc, "log: Unit mis-match for crash and debug sections: %d vs %d!\n",
>> log->sizes[GUC_LOG_SECTIONS_CRASH].units,
>> log->sizes[GUC_LOG_SECTIONS_DEBUG].units);
>> log->sizes[GUC_LOG_SECTIONS_CRASH].units = log->sizes[GUC_LOG_SECTIONS_DEBUG].units;
>> @@ -383,7 +382,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
>>
>> mutex_lock(&log->relay.lock);
>>
>> - if (WARN_ON(!intel_guc_log_relay_created(log)))
>> + if (guc_WARN_ON(log_to_guc(log), !intel_guc_log_relay_created(log)))
> hmm, is this WARN_ON really needed here?
Well, it is an internal driver error if it occurs. All code paths that
lead here should already have validated that relay logging has been
started. So if the buffer has not been allocated then something bad has
happened. Seems like that's what a WARN is meant to be used for.
John.
>
>> goto out_unlock;
>>
>> /* Get the pointer to shared GuC log buffer */
>> @@ -451,7 +450,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
>> write_offset = buffer_size;
>> } else if (unlikely((read_offset > buffer_size) ||
>> (write_offset > buffer_size))) {
>> - DRM_ERROR("invalid log buffer state\n");
>> + guc_err(log_to_guc(log), "log: invalid buffer state\n");
>> /* copy whole buffer as offsets are unreliable */
>> read_offset = 0;
>> write_offset = buffer_size;
>> @@ -520,7 +519,7 @@ void intel_guc_log_init_early(struct intel_guc_log *log)
>> static int guc_log_relay_create(struct intel_guc_log *log)
>> {
>> struct intel_guc *guc = log_to_guc(log);
>> - struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
>> + struct intel_gt *gt = guc_to_gt(guc);
>> struct rchan *guc_log_relay_chan;
>> size_t n_subbufs, subbuf_size;
>> int ret;
>> @@ -543,11 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log *log)
>> n_subbufs = 8;
>>
>> guc_log_relay_chan = relay_open("guc_log",
>> - dev_priv->drm.primary->debugfs_root,
>> + gt->i915->drm.primary->debugfs_root,
>> subbuf_size, n_subbufs,
>> - &relay_callbacks, dev_priv);
>> + &relay_callbacks, gt->i915);
>> if (!guc_log_relay_chan) {
>> - DRM_ERROR("Couldn't create relay chan for GuC logging\n");
>> + guc_err(guc, "log: Failed to create relay chan\n");
>>
>> ret = -ENOMEM;
>> return ret;
>> @@ -596,7 +595,7 @@ static u32 __get_default_log_level(struct intel_guc_log *log)
>> }
>>
>> if (i915->params.guc_log_level > GUC_LOG_LEVEL_MAX) {
>> - DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
>> + guc_warn(guc, "log: Incompatible options detected: %s=%d, %s!\n",
>> "guc_log_level", i915->params.guc_log_level,
>> "verbosity too high");
>> return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
>> @@ -641,15 +640,15 @@ int intel_guc_log_create(struct intel_guc_log *log)
>> log->buf_addr = vaddr;
>>
>> log->level = __get_default_log_level(log);
>> - DRM_DEBUG_DRIVER("guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
>> - log->level, str_enabled_disabled(log->level),
>> - str_yes_no(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
>> - GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
>> + guc_dbg(guc, "guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
>> + log->level, str_enabled_disabled(log->level),
>> + str_yes_no(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
>> + GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
>>
>> return 0;
>>
>> err:
>> - DRM_ERROR("Failed to allocate or map GuC log buffer. %d\n", ret);
>> + guc_err(guc, "log: Failed to allocate or map buffer: %d\n", ret);
>> return ret;
>> }
>>
>> @@ -687,7 +686,7 @@ int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)
>> GUC_LOG_LEVEL_IS_ENABLED(level),
>> GUC_LOG_LEVEL_TO_VERBOSITY(level));
>> if (ret) {
>> - DRM_DEBUG_DRIVER("guc_log_control action failed %d\n", ret);
>> + guc_dbg(guc, "guc_log_control action failed %d\n", ret);
>> goto out_unlock;
>> }
>>
>> @@ -905,7 +904,7 @@ int intel_guc_log_dump(struct intel_guc_log *log, struct drm_printer *p,
>>
>> map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
>> if (IS_ERR(map)) {
>> - DRM_DEBUG("Failed to pin object\n");
>> + guc_dbg(guc, "log: Failed to pin buffer object\n");
>> drm_puts(p, "(log data unaccessible)\n");
>> free_page((unsigned long)page);
>> return PTR_ERR(map);
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
>> index b5855091cf6a9..62f3b97111f64 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
>> @@ -70,13 +70,12 @@ static int __guc_rc_control(struct intel_guc *guc, bool enable)
>>
>> ret = guc_action_control_gucrc(guc, enable);
>> if (ret) {
>> - i915_probe_error(guc_to_gt(guc)->i915, "Failed to %s GuC RC (%pe)\n",
>> - str_enable_disable(enable), ERR_PTR(ret));
>> + guc_probe_error(guc, "RC: Failed to %s: %pe\n",
>> + str_enable_disable(enable), ERR_PTR(ret));
> in most cases we show error in () so it looks like:
>
> "GT0 GuC RC: Failed to enable (-ENOMEM)"
>
> please don't change that
>
>> return ret;
>> }
>>
>> - drm_info(>->i915->drm, "GuC RC: %s\n",
>> - str_enabled_disabled(enable));
>> + guc_info(guc, "RC %s\n", str_enabled_disabled(enable));
>>
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> index 63464933cbceb..b9ef0b4a123e1 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> @@ -171,14 +171,12 @@ static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
>> static int slpc_query_task_state(struct intel_guc_slpc *slpc)
>> {
>> struct intel_guc *guc = slpc_to_guc(slpc);
>> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
>> int ret;
>>
>> ret = guc_action_slpc_query(guc, offset);
>> if (unlikely(ret))
>> - i915_probe_error(i915, "Failed to query task state (%pe)\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(guc, "SLPC: Failed to query task state (%pe)\n", ERR_PTR(ret));
>>
>> drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
>>
>> @@ -188,15 +186,14 @@ static int slpc_query_task_state(struct intel_guc_slpc *slpc)
>> static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
>> {
>> struct intel_guc *guc = slpc_to_guc(slpc);
>> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> int ret;
>>
>> GEM_BUG_ON(id >= SLPC_MAX_PARAM);
>>
>> ret = guc_action_slpc_set_param(guc, id, value);
>> if (ret)
>> - i915_probe_error(i915, "Failed to set param %d to %u (%pe)\n",
>> - id, value, ERR_PTR(ret));
>> + guc_probe_error(guc, "SLPC: Failed to set param %d to %u (%pe)\n",
>> + id, value, ERR_PTR(ret));
>>
>> return ret;
>> }
>> @@ -236,8 +233,7 @@ static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
>> SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
>> freq);
>> if (ret)
>> - drm_notice(&i915->drm,
>> - "Failed to send set_param for min freq(%d): (%d)\n",
>> + guc_notice(guc, "SLPC: Failed to send set_param for min freq(%d): (%d)\n",
>> freq, ret);
>> }
>>
>> @@ -267,7 +263,6 @@ static void slpc_boost_work(struct work_struct *work)
>> int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>> {
>> struct intel_guc *guc = slpc_to_guc(slpc);
>> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
>> int err;
>>
>> @@ -275,9 +270,8 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>>
>> err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&slpc->vaddr);
>> if (unlikely(err)) {
>> - i915_probe_error(i915,
>> - "Failed to allocate SLPC struct (err=%pe)\n",
>> - ERR_PTR(err));
>> + guc_probe_error(guc, "SLPC: Failed to allocate SLPC struct (err=%pe)\n",
> while here, drop "err=" just leave "(%pe)"
>
> Michal
>
>> + ERR_PTR(err));
>> return err;
>> }
>>
>> @@ -338,7 +332,6 @@ static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset)
>>
>> static int slpc_reset(struct intel_guc_slpc *slpc)
>> {
>> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> struct intel_guc *guc = slpc_to_guc(slpc);
>> u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
>> int ret;
>> @@ -346,15 +339,14 @@ static int slpc_reset(struct intel_guc_slpc *slpc)
>> ret = guc_action_slpc_reset(guc, offset);
>>
>> if (unlikely(ret < 0)) {
>> - i915_probe_error(i915, "SLPC reset action failed (%pe)\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(guc, "SLPC: Reset action failed (%pe)\n", ERR_PTR(ret));
>> return ret;
>> }
>>
>> if (!ret) {
>> if (wait_for(slpc_is_running(slpc), SLPC_RESET_TIMEOUT_MS)) {
>> - i915_probe_error(i915, "SLPC not enabled! State = %s\n",
>> - slpc_get_state_string(slpc));
>> + guc_probe_error(guc, "SLPC: Not enabled! State = %s\n",
>> + slpc_get_state_string(slpc));
>> return -EIO;
>> }
>> }
>> @@ -495,8 +487,8 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
>> SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
>> val < slpc->rp1_freq);
>> if (ret) {
>> - i915_probe_error(i915, "Failed to toggle efficient freq (%pe)\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(slpc_to_guc(slpc), "SLPC: Failed to toggle efficient freq (%pe)\n",
>> + ERR_PTR(ret));
>> goto out;
>> }
>>
>> @@ -611,15 +603,12 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
>>
>> static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
>> {
>> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> int slpc_min_freq;
>> int ret;
>>
>> ret = intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq);
>> if (ret) {
>> - drm_err(&i915->drm,
>> - "Failed to get min freq: (%d)\n",
>> - ret);
>> + guc_err(slpc_to_guc(slpc), "SLPC: Failed to get min freq: (%d)\n", ret);
>> return false;
>> }
>>
>> @@ -685,8 +674,7 @@ int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode)
>> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
>> ret = slpc_set_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
>> if (ret)
>> - drm_err(&i915->drm,
>> - "Override gucrc mode %d failed %d\n",
>> + guc_err(slpc_to_guc(slpc), "SLPC: Override gucrc mode %d failed %d\n",
>> mode, ret);
>> }
>>
>> @@ -702,9 +690,7 @@ int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
>> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
>> ret = slpc_unset_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE);
>> if (ret)
>> - drm_err(&i915->drm,
>> - "Unsetting gucrc mode failed %d\n",
>> - ret);
>> + guc_err(slpc_to_guc(slpc), "SLPC: Unsetting gucrc mode failed %d\n", ret);
>> }
>>
>> return ret;
>> @@ -726,6 +712,7 @@ int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
>> int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>> {
>> struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> + struct intel_guc *guc = slpc_to_guc(slpc);
>> int ret;
>>
>> GEM_BUG_ON(!slpc->vma);
>> @@ -734,8 +721,8 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>>
>> ret = slpc_reset(slpc);
>> if (unlikely(ret < 0)) {
>> - i915_probe_error(i915, "SLPC Reset event returned (%pe)\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(guc, "SLPC: Reset event returned (%pe)\n",
>> + ERR_PTR(ret));
>> return ret;
>> }
>>
>> @@ -753,16 +740,16 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>> /* Set SLPC max limit to RP0 */
>> ret = slpc_use_fused_rp0(slpc);
>> if (unlikely(ret)) {
>> - i915_probe_error(i915, "Failed to set SLPC max to RP0 (%pe)\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(guc, "SLPC: Failed to set max to RP0 (%pe)\n",
>> + ERR_PTR(ret));
>> return ret;
>> }
>>
>> /* Revert SLPC min/max to softlimits if necessary */
>> ret = slpc_set_softlimits(slpc);
>> if (unlikely(ret)) {
>> - i915_probe_error(i915, "Failed to set SLPC softlimits (%pe)\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(guc, "SLPC: Failed to set softlimits (%pe)\n",
>> + ERR_PTR(ret));
>> return ret;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> index 0a42f1807f52c..da8ab18aa4ce7 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> @@ -1443,8 +1443,7 @@ static void guc_init_engine_stats(struct intel_guc *guc)
>> int ret = guc_action_enable_usage_stats(guc);
>>
>> if (ret)
>> - drm_err(>->i915->drm,
>> - "Failed to enable usage stats: %d!\n", ret);
>> + guc_err(guc, "Failed to enable usage stats: %d!\n", ret);
>> }
>> }
>>
>> @@ -3584,8 +3583,7 @@ static int guc_request_alloc(struct i915_request *rq)
>> intel_context_sched_disable_unpin(ce);
>> else if (intel_context_is_closed(ce))
>> if (wait_for(context_close_done(ce), 1500))
>> - drm_warn(&guc_to_gt(guc)->i915->drm,
>> - "timed out waiting on context sched close before realloc\n");
>> + guc_warn(guc, "timed out waiting on context sched close before realloc\n");
>> /*
>> * Call pin_guc_id here rather than in the pinning step as with
>> * dma_resv, contexts can be repeatedly pinned / unpinned trashing the
>> @@ -4350,7 +4348,7 @@ static int __guc_action_set_scheduling_policies(struct intel_guc *guc,
>> return ret;
>>
>> if (ret != policy->count) {
>> - drm_warn(&guc_to_gt(guc)->i915->drm, "GuC global scheduler policy processed %d of %d KLVs!",
>> + guc_warn(guc, "H2G: global scheduler policy processed %d of %d KLVs!\n",
>> ret, policy->count);
>> if (ret > policy->count)
>> return -EPROTO;
>> @@ -4383,9 +4381,9 @@ static int guc_init_global_schedule_policy(struct intel_guc *guc)
>>
>> ret = __guc_action_set_scheduling_policies(guc, &policy);
>> if (ret)
>> - i915_probe_error(gt->i915,
>> - "Failed to configure global scheduling policies: %pe!\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(guc,
>> + "Failed to configure global scheduling policies: %pe!\n",
>> + ERR_PTR(ret));
>> }
>>
>> return ret;
>> @@ -4484,21 +4482,18 @@ g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)
>> struct intel_context *ce;
>>
>> if (unlikely(ctx_id >= GUC_MAX_CONTEXT_ID)) {
>> - drm_err(&guc_to_gt(guc)->i915->drm,
>> - "Invalid ctx_id %u\n", ctx_id);
>> + guc_err(guc, "Invalid ctx_id %u\n", ctx_id);
>> return NULL;
>> }
>>
>> ce = __get_context(guc, ctx_id);
>> if (unlikely(!ce)) {
>> - drm_err(&guc_to_gt(guc)->i915->drm,
>> - "Context is NULL, ctx_id %u\n", ctx_id);
>> + guc_err(guc, "Context is NULL, ctx_id %u\n", ctx_id);
>> return NULL;
>> }
>>
>> if (unlikely(intel_context_is_child(ce))) {
>> - drm_err(&guc_to_gt(guc)->i915->drm,
>> - "Context is child, ctx_id %u\n", ctx_id);
>> + guc_err(guc, "Context is child, ctx_id %u\n", ctx_id);
>> return NULL;
>> }
>>
>> @@ -4513,7 +4508,7 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
>> u32 ctx_id;
>>
>> if (unlikely(len < 1)) {
>> - drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
>> + guc_err(guc, "notification: Invalid length %u for deregister done\n", len);
>> return -EPROTO;
>> }
>> ctx_id = msg[0];
>> @@ -4565,7 +4560,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
>> u32 ctx_id;
>>
>> if (unlikely(len < 2)) {
>> - drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
>> + guc_err(guc, "notification: Invalid length %u for sched done\n", len);
>> return -EPROTO;
>> }
>> ctx_id = msg[0];
>> @@ -4577,8 +4572,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
>> if (unlikely(context_destroyed(ce) ||
>> (!context_pending_enable(ce) &&
>> !context_pending_disable(ce)))) {
>> - drm_err(&guc_to_gt(guc)->i915->drm,
>> - "Bad context sched_state 0x%x, ctx_id %u\n",
>> + guc_err(guc, "notification: Bad context sched_state 0x%x, ctx_id %u\n",
>> ce->guc_state.sched_state, ctx_id);
>> return -EPROTO;
>> }
>> @@ -4666,8 +4660,8 @@ static void guc_handle_context_reset(struct intel_guc *guc,
>> capture_error_state(guc, ce);
>> guc_context_replay(ce);
>> } else {
>> - drm_info(&guc_to_gt(guc)->i915->drm,
>> - "Ignoring context reset notification of exiting context 0x%04X on %s",
>> + guc_info(guc,
>> + "Ignoring context reset notification of exiting context 0x%04X on %s\n",
>> ce->guc_id.id, ce->engine->name);
>> }
>> }
>> @@ -4680,7 +4674,7 @@ int intel_guc_context_reset_process_msg(struct intel_guc *guc,
>> int ctx_id;
>>
>> if (unlikely(len != 1)) {
>> - drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
>> + guc_err(guc, "notification: Invalid length %u for context reset\n", len);
>> return -EPROTO;
>> }
>>
>> @@ -4713,13 +4707,13 @@ int intel_guc_error_capture_process_msg(struct intel_guc *guc,
>> u32 status;
>>
>> if (unlikely(len != 1)) {
>> - drm_dbg(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
>> + guc_err(guc, "notification: Invalid length %u for error capture\n", len);
>> return -EPROTO;
>> }
>>
>> status = msg[0] & INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK;
>> if (status == INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE)
>> - drm_warn(&guc_to_gt(guc)->i915->drm, "G2H-Error capture no space");
>> + guc_warn(guc, "notification: Error capture buffer overflow\n");
>>
>> intel_guc_capture_process(guc);
>>
>> @@ -4762,13 +4756,12 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
>> const u32 *msg, u32 len)
>> {
>> struct intel_engine_cs *engine;
>> - struct intel_gt *gt = guc_to_gt(guc);
>> u8 guc_class, instance;
>> u32 reason;
>> unsigned long flags;
>>
>> if (unlikely(len != 3)) {
>> - drm_err(>->i915->drm, "Invalid length %u", len);
>> + guc_err(guc, "notification: Invalid length %u for engine failure\n", len);
>> return -EPROTO;
>> }
>>
>> @@ -4778,8 +4771,8 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
>>
>> engine = intel_guc_lookup_engine(guc, guc_class, instance);
>> if (unlikely(!engine)) {
>> - drm_err(>->i915->drm,
>> - "Invalid engine %d:%d", guc_class, instance);
>> + guc_err(guc, "notification: Invalid engine %d:%d for engine failure\n",
>> + guc_class, instance);
>> return -EPROTO;
>> }
>>
>> @@ -4787,7 +4780,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
>> * This is an unexpected failure of a hardware feature. So, log a real
>> * error message not just the informational that comes with the reset.
>> */
>> - drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X",
>> + guc_err(guc, "notification: Engine reset request failed on %d:%d (%s) because 0x%08X\n",
>> guc_class, instance, engine->name, reason);
>>
>> spin_lock_irqsave(&guc->submission_state.lock, flags);
>> @@ -5297,6 +5290,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
>> unsigned long flags)
>> {
>> struct guc_virtual_engine *ve;
>> + struct intel_gt *gt;
>> struct intel_guc *guc;
>> unsigned int n;
>> int err;
>> @@ -5305,10 +5299,11 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
>> if (!ve)
>> return ERR_PTR(-ENOMEM);
>>
>> - guc = &siblings[0]->gt->uc.guc;
>> + gt = siblings[0]->gt;
>> + guc = >->uc.guc;
>>
>> ve->base.i915 = siblings[0]->i915;
>> - ve->base.gt = siblings[0]->gt;
>> + ve->base.gt = gt;
>> ve->base.uncore = siblings[0]->uncore;
>> ve->base.id = -1;
>>
>> @@ -5336,8 +5331,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
>>
>> GEM_BUG_ON(!is_power_of_2(sibling->mask));
>> if (sibling->mask & ve->base.mask) {
>> - DRM_DEBUG("duplicate %s entry in load balancer\n",
>> - sibling->name);
>> + guc_dbg(guc, "Duplicate %s entry in load balancer\n", sibling->name);
>> err = -EINVAL;
>> goto err_put;
>> }
>> @@ -5346,8 +5340,8 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
>> ve->base.logical_mask |= sibling->logical_mask;
>>
>> if (n != 0 && ve->base.class != sibling->class) {
>> - DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n",
>> - sibling->class, ve->base.class);
>> + guc_dbg(guc, "Invalid mixing of engine class, sibling %d, already %d\n",
>> + sibling->class, ve->base.class);
>> err = -EINVAL;
>> goto err_put;
>> } else if (n == 0) {
>> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
>> index e28518fe8b908..d588c32d65c54 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
>> @@ -65,7 +65,7 @@ static int intel_guc_scrub_ctbs(void *arg)
>> ce = intel_context_create(engine);
>> if (IS_ERR(ce)) {
>> ret = PTR_ERR(ce);
>> - drm_err(>->i915->drm, "Failed to create context, %d: %d\n", i, ret);
>> + gt_err(gt, "Failed to create context, %d: %d\n", i, ret);
>> goto err;
>> }
>>
>> @@ -86,7 +86,7 @@ static int intel_guc_scrub_ctbs(void *arg)
>>
>> if (IS_ERR(rq)) {
>> ret = PTR_ERR(rq);
>> - drm_err(>->i915->drm, "Failed to create request, %d: %d\n", i, ret);
>> + gt_err(gt, "Failed to create request, %d: %d\n", i, ret);
>> goto err;
>> }
>>
>> @@ -96,7 +96,7 @@ static int intel_guc_scrub_ctbs(void *arg)
>> for (i = 0; i < 3; ++i) {
>> ret = i915_request_wait(last[i], 0, HZ);
>> if (ret < 0) {
>> - drm_err(>->i915->drm, "Last request failed to complete: %d\n", ret);
>> + gt_err(gt, "Last request failed to complete: %d\n", ret);
>> goto err;
>> }
>> i915_request_put(last[i]);
>> @@ -113,7 +113,7 @@ static int intel_guc_scrub_ctbs(void *arg)
>> /* GT will not idle if G2H are lost */
>> ret = intel_gt_wait_for_idle(gt, HZ);
>> if (ret < 0) {
>> - drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
>> + gt_err(gt, "GT failed to idle: %d\n", ret);
>> goto err;
>> }
>>
>> @@ -153,7 +153,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>>
>> ce = kcalloc(GUC_MAX_CONTEXT_ID, sizeof(*ce), GFP_KERNEL);
>> if (!ce) {
>> - drm_err(>->i915->drm, "Context array allocation failed\n");
>> + guc_err(guc, "Context array allocation failed\n");
>> return -ENOMEM;
>> }
>>
>> @@ -167,24 +167,24 @@ static int intel_guc_steal_guc_ids(void *arg)
>> if (IS_ERR(ce[context_index])) {
>> ret = PTR_ERR(ce[context_index]);
>> ce[context_index] = NULL;
>> - drm_err(>->i915->drm, "Failed to create context: %d\n", ret);
>> + guc_err(guc, "Failed to create context: %d\n", ret);
>> goto err_wakeref;
>> }
>> ret = igt_spinner_init(&spin, engine->gt);
>> if (ret) {
>> - drm_err(>->i915->drm, "Failed to create spinner: %d\n", ret);
>> + guc_err(guc, "Failed to create spinner: %d\n", ret);
>> goto err_contexts;
>> }
>> spin_rq = igt_spinner_create_request(&spin, ce[context_index],
>> MI_ARB_CHECK);
>> if (IS_ERR(spin_rq)) {
>> ret = PTR_ERR(spin_rq);
>> - drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
>> + guc_err(guc, "Failed to create spinner request: %d\n", ret);
>> goto err_contexts;
>> }
>> ret = request_add_spin(spin_rq, &spin);
>> if (ret) {
>> - drm_err(>->i915->drm, "Failed to add Spinner request: %d\n", ret);
>> + guc_err(guc, "Failed to add Spinner request: %d\n", ret);
>> goto err_spin_rq;
>> }
>>
>> @@ -194,7 +194,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>> if (IS_ERR(ce[context_index])) {
>> ret = PTR_ERR(ce[context_index--]);
>> ce[context_index] = NULL;
>> - drm_err(>->i915->drm, "Failed to create context: %d\n", ret);
>> + guc_err(guc, "Failed to create context: %d\n", ret);
>> goto err_spin_rq;
>> }
>>
>> @@ -203,7 +203,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>> ret = PTR_ERR(rq);
>> rq = NULL;
>> if (ret != -EAGAIN) {
>> - drm_err(>->i915->drm, "Failed to create request, %d: %d\n",
>> + guc_err(guc, "Failed to create request, %d: %d\n",
>> context_index, ret);
>> goto err_spin_rq;
>> }
>> @@ -218,7 +218,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>> igt_spinner_end(&spin);
>> ret = intel_selftest_wait_for_rq(spin_rq);
>> if (ret) {
>> - drm_err(>->i915->drm, "Spin request failed to complete: %d\n", ret);
>> + guc_err(guc, "Spin request failed to complete: %d\n", ret);
>> i915_request_put(last);
>> goto err_spin_rq;
>> }
>> @@ -230,7 +230,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>> ret = i915_request_wait(last, 0, HZ * 30);
>> i915_request_put(last);
>> if (ret < 0) {
>> - drm_err(>->i915->drm, "Last request failed to complete: %d\n", ret);
>> + guc_err(guc, "Last request failed to complete: %d\n", ret);
>> goto err_spin_rq;
>> }
>>
>> @@ -238,7 +238,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>> rq = nop_user_request(ce[context_index], NULL);
>> if (IS_ERR(rq)) {
>> ret = PTR_ERR(rq);
>> - drm_err(>->i915->drm, "Failed to steal guc_id, %d: %d\n", context_index, ret);
>> + guc_err(guc, "Failed to steal guc_id, %d: %d\n", context_index, ret);
>> goto err_spin_rq;
>> }
>>
>> @@ -246,20 +246,20 @@ static int intel_guc_steal_guc_ids(void *arg)
>> ret = i915_request_wait(rq, 0, HZ);
>> i915_request_put(rq);
>> if (ret < 0) {
>> - drm_err(>->i915->drm, "Request with stolen guc_id failed to complete: %d\n", ret);
>> + guc_err(guc, "Request with stolen guc_id failed to complete: %d\n", ret);
>> goto err_spin_rq;
>> }
>>
>> /* Wait for idle */
>> ret = intel_gt_wait_for_idle(gt, HZ * 30);
>> if (ret < 0) {
>> - drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
>> + guc_err(guc, "GT failed to idle: %d\n", ret);
>> goto err_spin_rq;
>> }
>>
>> /* Verify a guc_id was stolen */
>> if (guc->number_guc_id_stolen == number_guc_id_stolen) {
>> - drm_err(>->i915->drm, "No guc_id was stolen");
>> + guc_err(guc, "No guc_id was stolen\n");
>> ret = -EINVAL;
>> } else {
>> ret = 0;
>> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
>> index d91b58f704039..07018ec75c21f 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
>> @@ -45,7 +45,7 @@ static int intel_hang_guc(void *arg)
>>
>> ctx = kernel_context(gt->i915, NULL);
>> if (IS_ERR(ctx)) {
>> - drm_err(>->i915->drm, "Failed get kernel context: %ld\n", PTR_ERR(ctx));
>> + gt_err(gt, "Failed get kernel context: %ld\n", PTR_ERR(ctx));
>> return PTR_ERR(ctx);
>> }
>>
>> @@ -54,7 +54,7 @@ static int intel_hang_guc(void *arg)
>> ce = intel_context_create(engine);
>> if (IS_ERR(ce)) {
>> ret = PTR_ERR(ce);
>> - drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
>> + gt_err(gt, "Failed to create spinner request: %d\n", ret);
>> goto err;
>> }
>>
>> @@ -63,13 +63,13 @@ static int intel_hang_guc(void *arg)
>> old_beat = engine->props.heartbeat_interval_ms;
>> ret = intel_engine_set_heartbeat(engine, BEAT_INTERVAL);
>> if (ret) {
>> - drm_err(>->i915->drm, "Failed to boost heatbeat interval: %d\n", ret);
>> + gt_err(gt, "Failed to boost heatbeat interval: %d\n", ret);
>> goto err;
>> }
>>
>> ret = igt_spinner_init(&spin, engine->gt);
>> if (ret) {
>> - drm_err(>->i915->drm, "Failed to create spinner: %d\n", ret);
>> + gt_err(gt, "Failed to create spinner: %d\n", ret);
>> goto err;
>> }
>>
>> @@ -77,28 +77,28 @@ static int intel_hang_guc(void *arg)
>> intel_context_put(ce);
>> if (IS_ERR(rq)) {
>> ret = PTR_ERR(rq);
>> - drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
>> + gt_err(gt, "Failed to create spinner request: %d\n", ret);
>> goto err_spin;
>> }
>>
>> ret = request_add_spin(rq, &spin);
>> if (ret) {
>> i915_request_put(rq);
>> - drm_err(>->i915->drm, "Failed to add Spinner request: %d\n", ret);
>> + gt_err(gt, "Failed to add Spinner request: %d\n", ret);
>> goto err_spin;
>> }
>>
>> ret = intel_reset_guc(gt);
>> if (ret) {
>> i915_request_put(rq);
>> - drm_err(>->i915->drm, "Failed to reset GuC, ret = %d\n", ret);
>> + gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
>> goto err_spin;
>> }
>>
>> guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
>> if (!(guc_status & GS_MIA_IN_RESET)) {
>> i915_request_put(rq);
>> - drm_err(>->i915->drm, "GuC failed to reset: status = 0x%08X\n", guc_status);
>> + gt_err(gt, "GuC failed to reset: status = 0x%08X\n", guc_status);
>> ret = -EIO;
>> goto err_spin;
>> }
>> @@ -107,12 +107,12 @@ static int intel_hang_guc(void *arg)
>> ret = intel_selftest_wait_for_rq(rq);
>> i915_request_put(rq);
>> if (ret) {
>> - drm_err(>->i915->drm, "Request failed to complete: %d\n", ret);
>> + gt_err(gt, "Request failed to complete: %d\n", ret);
>> goto err_spin;
>> }
>>
>> if (i915_reset_count(global) == reset_count) {
>> - drm_err(>->i915->drm, "Failed to record a GPU reset\n");
>> + gt_err(gt, "Failed to record a GPU reset\n");
>> ret = -EINVAL;
>> goto err_spin;
>> }
>> @@ -132,7 +132,7 @@ static int intel_hang_guc(void *arg)
>> ret = intel_selftest_wait_for_rq(rq);
>> i915_request_put(rq);
>> if (ret) {
>> - drm_err(>->i915->drm, "No-op failed to complete: %d\n", ret);
>> + gt_err(gt, "No-op failed to complete: %d\n", ret);
>> goto err;
>> }
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
>> index d17982c36d256..04e28735a2ee6 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
>> @@ -115,30 +115,30 @@ static int __intel_guc_multi_lrc_basic(struct intel_gt *gt, unsigned int class)
>>
>> parent = multi_lrc_create_parent(gt, class, 0);
>> if (IS_ERR(parent)) {
>> - drm_err(>->i915->drm, "Failed creating contexts: %ld", PTR_ERR(parent));
>> + gt_err(gt, "Failed creating contexts: %ld", PTR_ERR(parent));
>> return PTR_ERR(parent);
>> } else if (!parent) {
>> - drm_dbg(>->i915->drm, "Not enough engines in class: %d", class);
>> + gt_dbg(gt, "Not enough engines in class: %d", class);
>> return 0;
>> }
>>
>> rq = multi_lrc_nop_request(parent);
>> if (IS_ERR(rq)) {
>> ret = PTR_ERR(rq);
>> - drm_err(>->i915->drm, "Failed creating requests: %d", ret);
>> + gt_err(gt, "Failed creating requests: %d", ret);
>> goto out;
>> }
>>
>> ret = intel_selftest_wait_for_rq(rq);
>> if (ret)
>> - drm_err(>->i915->drm, "Failed waiting on request: %d", ret);
>> + gt_err(gt, "Failed waiting on request: %d", ret);
>>
>> i915_request_put(rq);
>>
>> if (ret >= 0) {
>> ret = intel_gt_wait_for_idle(gt, HZ * 5);
>> if (ret < 0)
>> - drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
>> + gt_err(gt, "GT failed to idle: %d\n", ret);
>> }
>>
>> out:
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH v2 3/5] drm/i915/guc: Add GuC specific debug print wrappers
@ 2022-11-23 0:56 ` John Harrison
0 siblings, 0 replies; 51+ messages in thread
From: John Harrison @ 2022-11-23 0:56 UTC (permalink / raw)
To: Michal Wajdeczko, Intel-GFX; +Cc: DRI-Devel
On 11/22/2022 09:42, Michal Wajdeczko wrote:
> On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> Create a set of GuC printers and start using them.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 ++++------
>> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++++++++++
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +--
>> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 +++++---------
>> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +++---
>> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++++++-----
>> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +--
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 +++++++---------
>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++++++++----------
>> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +++++-----
>> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +++----
>> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +--
>> 12 files changed, 179 insertions(+), 190 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> index 52aede324788e..d9972510ee29b 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> @@ -94,8 +94,8 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
>> assert_rpm_wakelock_held(>->i915->runtime_pm);
>>
>> spin_lock_irq(gt->irq_lock);
>> - WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
>> - gt->pm_guc_events);
>> + guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
>> + gt->pm_guc_events);
>> gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
>> spin_unlock_irq(gt->irq_lock);
>>
>> @@ -339,7 +339,7 @@ static void guc_init_params(struct intel_guc *guc)
>> params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
>>
>> for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
>> - DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
>> + guc_dbg(guc, "init param[%2d] = %#x\n", i, params[i]);
>> }
>>
>> /*
>> @@ -451,7 +451,7 @@ int intel_guc_init(struct intel_guc *guc)
>> intel_uc_fw_fini(&guc->fw);
>> out:
>> intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
>> - i915_probe_error(gt->i915, "failed with %d\n", ret);
>> + guc_probe_error(guc, "init failed with %d\n", ret);
>> return ret;
>> }
>>
>> @@ -484,7 +484,6 @@ void intel_guc_fini(struct intel_guc *guc)
>> int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
>> u32 *response_buf, u32 response_buf_size)
>> {
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
>> u32 header;
>> int i;
>> @@ -519,8 +518,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
>> 10, 10, &header);
>> if (unlikely(ret)) {
>> timeout:
>> - drm_err(&i915->drm, "mmio request %#x: no reply %x\n",
>> - request[0], header);
>> + guc_err(guc, "mmio request %#x: no reply %x\n", request[0], header);
>> goto out;
>> }
>>
>> @@ -541,8 +539,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
>> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
>> u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
>>
>> - drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n",
>> - request[0], reason);
>> + guc_dbg(guc, "mmio request %#x: retrying, reason %u\n", request[0], reason);
>> goto retry;
>> }
>>
>> @@ -550,16 +547,14 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
>> u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
>> u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
>>
>> - drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n",
>> - request[0], error, hint);
>> + guc_err(guc, "mmio request %#x: failure %x/%u\n", request[0], error, hint);
>> ret = -ENXIO;
>> goto out;
>> }
>>
>> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) {
>> proto:
>> - drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n",
>> - request[0], header);
>> + guc_err(guc, "mmio request %#x: unexpected reply %#x\n", request[0], header);
>> ret = -EPROTO;
>> goto out;
>> }
>> @@ -601,9 +596,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
>> msg = payload[0] & guc->msg_enabled_mask;
>>
>> if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
>> - drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC crash dump notification!\n");
>> + guc_err(guc, "early notification: Crash dump!\n");
>> if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
>> - drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC exception notification!\n");
>> + guc_err(guc, "early notification: Exception!\n");
>>
>> return 0;
>> }
>> @@ -657,7 +652,7 @@ int intel_guc_suspend(struct intel_guc *guc)
>> */
>> ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
>> if (ret)
>> - DRM_ERROR("GuC suspend: RESET_CLIENT action failed with error %d!\n", ret);
>> + guc_err(guc, "suspend: RESET_CLIENT action failed with error %d!\n", ret);
>> }
>>
>> /* Signal that the GuC isn't running. */
>> @@ -832,12 +827,11 @@ static int __guc_action_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 va
>>
>> static int __guc_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
>> {
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> int err = __guc_action_self_cfg(guc, key, len, value);
>>
>> if (unlikely(err))
>> - i915_probe_error(i915, "Unsuccessful self-config (%pe) key %#hx value %#llx\n",
>> - ERR_PTR(err), key, value);
>> + guc_probe_error(guc, "self-config; Unsuccessful (%pe) key %#hx value %#llx\n",
> self-config:
>
>> + ERR_PTR(err), key, value);
>> return err;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> index 1bb3f98292866..8c02d22bc7e82 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> @@ -24,6 +24,41 @@
>> struct __guc_ads_blob;
>> struct intel_guc_state_capture;
>>
>> +#define guc_err(_guc, _fmt, ...) \
>> + gt_err(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
>> +
>> +#define guc_warn(_guc, _fmt, ...) \
>> + gt_warn(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
>> +
>> +#define guc_notice(_guc, _fmt, ...) \
>> + gt_notice(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
>> +
>> +#define guc_info(_guc, _fmt, ...) \
>> + gt_info(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
>> +
>> +#define guc_dbg(_guc, _fmt, ...) \
>> + gt_dbg(guc_to_gt(_guc), "GuC " _fmt, ##__VA_ARGS__)
>> +
>> +#define guc_probe_error(_guc, _fmt, ...) \
>> + do { \
>> + if (i915_error_injected()) \
>> + guc_dbg(_guc, _fmt, ##__VA_ARGS__); \
>> + else \
>> + guc_err(_guc, _fmt, ##__VA_ARGS__); \
>> + } while (0)
> use gt_probe_error ?
Brain fade, I think. For some reason I was thinking that wouldn't work,
but it clearly does.
>
>> +
>> +#define guc_WARN_ON(_guc, _condition) \
>> + guc_WARN(_guc, _condition, "%s", "guc_WARN_ON(" __stringify(_condition) ")")
>> +
>> +#define guc_WARN_ON_ONCE(_guc, _condition) \
>> + guc_WARN_ONCE(_guc, _condition, "%s", "guc_WARN_ON_ONCE(" __stringify(_condition) ")")
>> +
>> +#define guc_WARN(_guc, _condition, _fmt, ...) \
>> + gt_WARN(guc_to_gt(_guc), _condition, "GuC " _fmt, ##__VA_ARGS__)
>> +
>> +#define guc_WARN_ONCE(_guc, _condition, _fmt, ...) \
>> + gt_WARN_ONCE(guc_to_gt(_guc), _condition, "GuC " _fmt, ##__VA_ARGS__)
>> +
>> /**
>> * struct intel_guc - Top level structure of GuC.
>> *
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> index a7f737c4792e2..fa9a31176b4a7 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> @@ -427,7 +427,7 @@ static long guc_mmio_reg_state_create(struct intel_guc *guc)
>>
>> guc->ads_regset = temp_set.storage;
>>
>> - drm_dbg(&guc_to_gt(guc)->i915->drm, "Used %zu KB for temporary ADS regset\n",
>> + guc_dbg(guc, "used %zu KB for temporary ADS regset\n",
>> (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
>>
>> return total * sizeof(struct guc_mmio_reg);
>> @@ -621,8 +621,7 @@ static void guc_init_golden_context(struct intel_guc *guc)
>>
>> engine = find_engine_state(gt, engine_class);
>> if (!engine) {
>> - drm_err(>->i915->drm, "No engine state recorded for class %d!\n",
>> - engine_class);
>> + guc_err(guc, "No engine state recorded for class %d!\n", engine_class);
>> ads_blob_write(guc, ads.eng_state_size[guc_class], 0);
>> ads_blob_write(guc, ads.golden_context_lrca[guc_class], 0);
>> continue;
>> @@ -646,7 +645,6 @@ static int
>> guc_capture_prep_lists(struct intel_guc *guc)
>> {
>> struct intel_gt *gt = guc_to_gt(guc);
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0;
>> struct guc_gt_system_info local_info;
>> struct iosys_map info_map;
>> @@ -751,7 +749,7 @@ guc_capture_prep_lists(struct intel_guc *guc)
>> }
>>
>> if (guc->ads_capture_size && guc->ads_capture_size != PAGE_ALIGN(total_size))
>> - drm_warn(&i915->drm, "GuC->ADS->Capture alloc size changed from %d to %d\n",
>> + guc_warn(guc, "capture alloc size changed from %d to %d\n",
>> guc->ads_capture_size, PAGE_ALIGN(total_size));
>>
>> return PAGE_ALIGN(total_size);
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>> index 1d49a7ec0bd8f..a8876178da6ff 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>> @@ -353,7 +353,6 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
>> u32 ipver)
>> {
>> struct intel_gt *gt = guc_to_gt(guc);
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> struct sseu_dev_info *sseu;
>> int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0;
>> const struct __guc_mmio_reg_descr_group *list;
>> @@ -402,7 +401,7 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
>> }
>> }
>>
>> - drm_dbg(&i915->drm, "GuC-capture found %d-ext-regs.\n", num_tot_regs);
>> + guc_dbg(guc, "capture found %d ext-regs.\n", num_tot_regs);
>> guc->capture->extlists = extlists;
>> }
>>
>> @@ -477,7 +476,6 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
>> struct guc_mmio_reg *ptr, u16 num_entries)
>> {
>> u32 i = 0, j = 0;
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists;
>> struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists;
>> const struct __guc_mmio_reg_descr_group *match;
>> @@ -509,8 +507,7 @@ guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
>> }
>> }
>> if (i < num_entries)
>> - drm_dbg(&i915->drm, "GuC-capture: Init reglist short %d out %d.\n",
>> - (int)i, (int)num_entries);
>> + guc_dbg(guc, "capture: Init reglist short %d out %d.\n", i, num_entries);
>>
>> return 0;
>> }
>> @@ -540,12 +537,11 @@ guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
>> size_t *size, bool is_purpose_est)
>> {
>> struct intel_guc_state_capture *gc = guc->capture;
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
>> int num_regs;
>>
>> if (!gc->reglists) {
>> - drm_warn(&i915->drm, "GuC-capture: No reglist on this device\n");
>> + guc_warn(guc, "capture: No reglist on this device\n");
>> return -ENODEV;
>> }
>>
>> @@ -557,9 +553,9 @@ guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
>> if (!is_purpose_est && owner == GUC_CAPTURE_LIST_INDEX_PF &&
>> !guc_capture_get_one_list(gc->reglists, owner, type, classid)) {
>> if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL)
>> - drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist Global!\n");
>> + guc_warn(guc, "capture: Missing reglist: Global!\n");
>> else
>> - drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist %s(%u):%s(%u)!\n",
>> + guc_warn(guc, "capture: Missing reglist: %s(%u):%s(%u)!\n",
>> __stringify_type(type), type,
>> __stringify_engclass(classid), classid);
>> return -ENODATA;
>> @@ -592,7 +588,6 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classi
>> {
>> struct intel_guc_state_capture *gc = guc->capture;
>> struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> struct guc_debug_capture_list *listnode;
>> int ret, num_regs;
>> u8 *caplist, *tmp;
>> @@ -623,7 +618,7 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classi
>>
>> caplist = kzalloc(size, GFP_KERNEL);
>> if (!caplist) {
>> - drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached caplist");
>> + guc_dbg(guc, "capture: Failed to alloc cached caplist\n");
>> return -ENOMEM;
>> }
>>
>> @@ -653,7 +648,6 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
>> void **outptr, size_t *size)
>> {
>> struct intel_guc_state_capture *gc = guc->capture;
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> int tmp = sizeof(u32) * 4;
>> void *null_header;
>>
>> @@ -665,7 +659,7 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
>>
>> null_header = kzalloc(tmp, GFP_KERNEL);
>> if (!null_header) {
>> - drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached nulllist");
>> + guc_dbg(guc, "capture: Failed to alloc cached null list\n");
>> return -ENOMEM;
>> }
>>
>> @@ -727,7 +721,6 @@ guc_capture_output_min_size_est(struct intel_guc *guc)
>>
>> static void check_guc_capture_size(struct intel_guc *guc)
>> {
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> int min_size = guc_capture_output_min_size_est(guc);
>> int spare_size = min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER;
>> u32 buffer_size = intel_guc_log_section_size_capture(&guc->log);
>> @@ -741,13 +734,13 @@ static void check_guc_capture_size(struct intel_guc *guc)
>> * INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE.
>> */
>> if (min_size < 0)
>> - drm_warn(&i915->drm, "Failed to calculate GuC error state capture buffer minimum size: %d!\n",
>> + guc_warn(guc, "error state capture buffer minimum size calculation failed: %d!\n",
>> min_size);
>> else if (min_size > buffer_size)
>> - drm_warn(&i915->drm, "GuC error state capture buffer maybe small: %d < %d\n",
>> + guc_warn(guc, "error state capture buffer maybe small: %d < %d\n",
>> buffer_size, min_size);
>> else if (spare_size > buffer_size)
>> - drm_dbg(&i915->drm, "GuC error state capture buffer lacks spare size: %d < %d (min = %d)\n",
>> + guc_dbg(guc, "error state capture buffer lacks spare size: %d < %d (min = %d)\n",
>> buffer_size, spare_size, min_size);
>> }
>>
>> @@ -848,7 +841,6 @@ static int
>> guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *buf,
>> u32 *dw)
>> {
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> int tries = 2;
>> int avail = 0;
>> u32 *src_data;
>> @@ -865,7 +857,7 @@ guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *
>> return 4;
>> }
>> if (avail)
>> - drm_dbg(&i915->drm, "GuC-Cap-Logs not dword aligned, skipping.\n");
>> + guc_dbg(guc, "capture: Log not dword aligned, skipping.\n");
>> buf->rd = 0;
>> }
>>
>> @@ -1118,13 +1110,12 @@ static void
>> __guc_capture_create_prealloc_nodes(struct intel_guc *guc)
>> {
>> struct __guc_capture_parsed_output *node = NULL;
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> int i;
>>
>> for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) {
>> node = guc_capture_alloc_one_node(guc);
>> if (!node) {
>> - drm_warn(&i915->drm, "GuC Capture pre-alloc-cache failure\n");
>> + guc_warn(guc, "capture pre-alloc-cache failure\n");
>> /* dont free the priors, use what we got and cleanup at shutdown */
>> return;
>> }
>> @@ -1169,7 +1160,6 @@ guc_capture_create_prealloc_nodes(struct intel_guc *guc)
>> static int
>> guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstate *buf)
>> {
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> struct guc_state_capture_group_header_t ghdr = {0};
>> struct guc_state_capture_header_t hdr = {0};
>> struct __guc_capture_parsed_output *node = NULL;
>> @@ -1183,7 +1173,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
>> if (!i)
>> return -ENODATA;
>> if (i % sizeof(u32)) {
>> - drm_warn(&i915->drm, "GuC Capture new entries unaligned\n");
>> + guc_warn(guc, "capture new entries unaligned\n");
>> ret = -EIO;
>> goto bailout;
>> }
>> @@ -1301,8 +1291,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
>> break;
>> }
>> if (datatype != GUC_CAPTURE_LIST_TYPE_GLOBAL)
>> - drm_dbg(&i915->drm, "GuC Capture missing global dump: %08x!\n",
>> - datatype);
>> + guc_dbg(guc, "cpture missing global dump: %08x!\n", datatype);
> typo
>
>> }
>> node->is_partial = is_partial;
>> node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner);
>> @@ -1322,7 +1311,7 @@ guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstat
>>
>> numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios);
>> if (numregs > guc->capture->max_mmio_per_node) {
>> - drm_dbg(&i915->drm, "GuC Capture list extraction clipped by prealloc!\n");
>> + guc_dbg(guc, "capture list extraction clipped by prealloc!\n");
>> numregs = guc->capture->max_mmio_per_node;
>> }
>> node->reginfo[datatype].num_regs = numregs;
>> @@ -1367,7 +1356,6 @@ static void __guc_capture_process_output(struct intel_guc *guc)
>> {
>> unsigned int buffer_size, read_offset, write_offset, full_count;
>> struct intel_uc *uc = container_of(guc, typeof(*uc), guc);
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> struct guc_log_buffer_state log_buf_state_local;
>> struct guc_log_buffer_state *log_buf_state;
>> struct __guc_capture_bufstate buf;
>> @@ -1403,7 +1391,7 @@ static void __guc_capture_process_output(struct intel_guc *guc)
>> write_offset = buffer_size;
>> } else if (unlikely((read_offset > buffer_size) ||
>> (write_offset > buffer_size))) {
>> - drm_err(&i915->drm, "invalid GuC log capture buffer state!\n");
>> + guc_err(guc, "capture: invalid buffer state!\n");
>> /* copy whole buffer as offsets are unreliable */
>> read_offset = 0;
>> write_offset = buffer_size;
>> @@ -1586,13 +1574,11 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
>> struct intel_context *ce)
>> {
>> struct __guc_capture_parsed_output *n, *ntmp;
>> - struct drm_i915_private *i915;
>> struct intel_guc *guc;
>>
>> if (!gt || !ee || !ce)
>> return;
>>
>> - i915 = gt->i915;
>> guc = >->uc.guc;
>> if (!guc->capture)
>> return;
>> @@ -1615,7 +1601,7 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
>> return;
>> }
>> }
>> - drm_dbg(&i915->drm, "GuC capture can't match ee to node\n");
>> + guc_dbg(guc, "capture can't match ee to node\n");
>> }
>>
>> void intel_guc_capture_process(struct intel_guc *guc)
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> index 5b86b2e286e07..4a2811aa3d5e1 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> @@ -103,8 +103,9 @@ static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
>> return uk_val == INTEL_GUC_LOAD_STATUS_READY;
>> }
>>
>> -static int guc_wait_ucode(struct intel_uncore *uncore)
>> +static int guc_wait_ucode(struct intel_gt *gt)
>> {
>> + struct intel_uncore *uncore = gt->uncore;
>> u32 status;
>> int ret;
>>
>> @@ -127,12 +128,8 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
>> */
>> ret = wait_for(guc_ready(uncore, &status), 200);
>> if (ret) {
>> - struct drm_device *drm = &uncore->i915->drm;
>> -
>> - drm_info(drm, "GuC load failed: status = 0x%08X\n", status);
>> - drm_info(drm, "GuC load failed: status: Reset = %d, "
>> - "BootROM = 0x%02X, UKernel = 0x%02X, "
>> - "MIA = 0x%02X, Auth = 0x%02X\n",
>> + gt_info(gt, "GuC load failed: status = 0x%08X\n", status);
>> + gt_info(gt, "GuC load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n",
> hmm, these should be guc_info() not gt_info()
>
> so instead of gt we should pass guc to guc_wait_ucode()
I was trying to not re-work any actual code if possible. But yeah, it
makes sense to switch the parameter here. The calling function is all
'guc' object based anyway.
>
>> REG_FIELD_GET(GS_MIA_IN_RESET, status),
>> REG_FIELD_GET(GS_BOOTROM_MASK, status),
>> REG_FIELD_GET(GS_UKERNEL_MASK, status),
>> @@ -140,13 +137,13 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
>> REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
>>
>> if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
>> - drm_info(drm, "GuC firmware signature verification failed\n");
>> + gt_info(gt, "GuC firmware signature verification failed\n");
>> ret = -ENOEXEC;
>> }
>>
>> if (REG_FIELD_GET(GS_UKERNEL_MASK, status) == INTEL_GUC_LOAD_STATUS_EXCEPTION) {
>> - drm_info(drm, "GuC firmware exception. EIP: %#x\n",
>> - intel_uncore_read(uncore, SOFT_SCRATCH(13)));
>> + gt_info(gt, "GuC firmware exception. EIP: %#x\n",
>> + intel_uncore_read(uncore, SOFT_SCRATCH(13)));
>> ret = -ENXIO;
>> }
>> }
>> @@ -194,7 +191,7 @@ int intel_guc_fw_upload(struct intel_guc *guc)
>> if (ret)
>> goto out;
>>
>> - ret = guc_wait_ucode(uncore);
>> + ret = guc_wait_ucode(gt);
>> if (ret)
>> goto out;
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> index 68331c538b0a7..8c9a020700b52 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>> @@ -39,7 +39,6 @@ struct guc_log_section {
>> static void _guc_log_init_sizes(struct intel_guc_log *log)
>> {
>> struct intel_guc *guc = log_to_guc(log);
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> static const struct guc_log_section sections[GUC_LOG_SECTIONS_LIMIT] = {
>> {
>> GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT,
>> @@ -82,12 +81,12 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
>> }
>>
>> if (!IS_ALIGNED(log->sizes[i].bytes, log->sizes[i].units))
>> - drm_err(&i915->drm, "Mis-aligned GuC log %s size: 0x%X vs 0x%X!",
>> + guc_err(guc, "log: Mis-aligned %s size: 0x%X vs 0x%X!\n",
>> sections[i].name, log->sizes[i].bytes, log->sizes[i].units);
>> log->sizes[i].count = log->sizes[i].bytes / log->sizes[i].units;
>>
>> if (!log->sizes[i].count) {
>> - drm_err(&i915->drm, "Zero GuC log %s size!", sections[i].name);
>> + guc_err(guc, "log: zero %s size!\n", sections[i].name);
>> } else {
>> /* Size is +1 unit */
>> log->sizes[i].count--;
>> @@ -95,14 +94,14 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
>>
>> /* Clip to field size */
>> if (log->sizes[i].count > sections[i].max) {
>> - drm_err(&i915->drm, "GuC log %s size too large: %d vs %d!",
>> + guc_err(guc, "log: %s size too large: %d vs %d!\n",
>> sections[i].name, log->sizes[i].count + 1, sections[i].max + 1);
>> log->sizes[i].count = sections[i].max;
>> }
>> }
>>
>> if (log->sizes[GUC_LOG_SECTIONS_CRASH].units != log->sizes[GUC_LOG_SECTIONS_DEBUG].units) {
>> - drm_err(&i915->drm, "Unit mis-match for GuC log crash and debug sections: %d vs %d!",
>> + guc_err(guc, "log: Unit mis-match for crash and debug sections: %d vs %d!\n",
>> log->sizes[GUC_LOG_SECTIONS_CRASH].units,
>> log->sizes[GUC_LOG_SECTIONS_DEBUG].units);
>> log->sizes[GUC_LOG_SECTIONS_CRASH].units = log->sizes[GUC_LOG_SECTIONS_DEBUG].units;
>> @@ -383,7 +382,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
>>
>> mutex_lock(&log->relay.lock);
>>
>> - if (WARN_ON(!intel_guc_log_relay_created(log)))
>> + if (guc_WARN_ON(log_to_guc(log), !intel_guc_log_relay_created(log)))
> hmm, is this WARN_ON really needed here?
Well, it is an internal driver error if it occurs. All code paths that
lead here should already have validated that relay logging has been
started. So if the buffer has not been allocated then something bad has
happened. Seems like that's what a WARN is meant to be used for.
John.
>
>> goto out_unlock;
>>
>> /* Get the pointer to shared GuC log buffer */
>> @@ -451,7 +450,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
>> write_offset = buffer_size;
>> } else if (unlikely((read_offset > buffer_size) ||
>> (write_offset > buffer_size))) {
>> - DRM_ERROR("invalid log buffer state\n");
>> + guc_err(log_to_guc(log), "log: invalid buffer state\n");
>> /* copy whole buffer as offsets are unreliable */
>> read_offset = 0;
>> write_offset = buffer_size;
>> @@ -520,7 +519,7 @@ void intel_guc_log_init_early(struct intel_guc_log *log)
>> static int guc_log_relay_create(struct intel_guc_log *log)
>> {
>> struct intel_guc *guc = log_to_guc(log);
>> - struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
>> + struct intel_gt *gt = guc_to_gt(guc);
>> struct rchan *guc_log_relay_chan;
>> size_t n_subbufs, subbuf_size;
>> int ret;
>> @@ -543,11 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log *log)
>> n_subbufs = 8;
>>
>> guc_log_relay_chan = relay_open("guc_log",
>> - dev_priv->drm.primary->debugfs_root,
>> + gt->i915->drm.primary->debugfs_root,
>> subbuf_size, n_subbufs,
>> - &relay_callbacks, dev_priv);
>> + &relay_callbacks, gt->i915);
>> if (!guc_log_relay_chan) {
>> - DRM_ERROR("Couldn't create relay chan for GuC logging\n");
>> + guc_err(guc, "log: Failed to create relay chan\n");
>>
>> ret = -ENOMEM;
>> return ret;
>> @@ -596,7 +595,7 @@ static u32 __get_default_log_level(struct intel_guc_log *log)
>> }
>>
>> if (i915->params.guc_log_level > GUC_LOG_LEVEL_MAX) {
>> - DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
>> + guc_warn(guc, "log: Incompatible options detected: %s=%d, %s!\n",
>> "guc_log_level", i915->params.guc_log_level,
>> "verbosity too high");
>> return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
>> @@ -641,15 +640,15 @@ int intel_guc_log_create(struct intel_guc_log *log)
>> log->buf_addr = vaddr;
>>
>> log->level = __get_default_log_level(log);
>> - DRM_DEBUG_DRIVER("guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
>> - log->level, str_enabled_disabled(log->level),
>> - str_yes_no(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
>> - GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
>> + guc_dbg(guc, "guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
>> + log->level, str_enabled_disabled(log->level),
>> + str_yes_no(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
>> + GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
>>
>> return 0;
>>
>> err:
>> - DRM_ERROR("Failed to allocate or map GuC log buffer. %d\n", ret);
>> + guc_err(guc, "log: Failed to allocate or map buffer: %d\n", ret);
>> return ret;
>> }
>>
>> @@ -687,7 +686,7 @@ int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)
>> GUC_LOG_LEVEL_IS_ENABLED(level),
>> GUC_LOG_LEVEL_TO_VERBOSITY(level));
>> if (ret) {
>> - DRM_DEBUG_DRIVER("guc_log_control action failed %d\n", ret);
>> + guc_dbg(guc, "guc_log_control action failed %d\n", ret);
>> goto out_unlock;
>> }
>>
>> @@ -905,7 +904,7 @@ int intel_guc_log_dump(struct intel_guc_log *log, struct drm_printer *p,
>>
>> map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
>> if (IS_ERR(map)) {
>> - DRM_DEBUG("Failed to pin object\n");
>> + guc_dbg(guc, "log: Failed to pin buffer object\n");
>> drm_puts(p, "(log data unaccessible)\n");
>> free_page((unsigned long)page);
>> return PTR_ERR(map);
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
>> index b5855091cf6a9..62f3b97111f64 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
>> @@ -70,13 +70,12 @@ static int __guc_rc_control(struct intel_guc *guc, bool enable)
>>
>> ret = guc_action_control_gucrc(guc, enable);
>> if (ret) {
>> - i915_probe_error(guc_to_gt(guc)->i915, "Failed to %s GuC RC (%pe)\n",
>> - str_enable_disable(enable), ERR_PTR(ret));
>> + guc_probe_error(guc, "RC: Failed to %s: %pe\n",
>> + str_enable_disable(enable), ERR_PTR(ret));
> in most cases we show error in () so it looks like:
>
> "GT0 GuC RC: Failed to enable (-ENOMEM)"
>
> please don't change that
>
>> return ret;
>> }
>>
>> - drm_info(>->i915->drm, "GuC RC: %s\n",
>> - str_enabled_disabled(enable));
>> + guc_info(guc, "RC %s\n", str_enabled_disabled(enable));
>>
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> index 63464933cbceb..b9ef0b4a123e1 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> @@ -171,14 +171,12 @@ static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
>> static int slpc_query_task_state(struct intel_guc_slpc *slpc)
>> {
>> struct intel_guc *guc = slpc_to_guc(slpc);
>> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
>> int ret;
>>
>> ret = guc_action_slpc_query(guc, offset);
>> if (unlikely(ret))
>> - i915_probe_error(i915, "Failed to query task state (%pe)\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(guc, "SLPC: Failed to query task state (%pe)\n", ERR_PTR(ret));
>>
>> drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
>>
>> @@ -188,15 +186,14 @@ static int slpc_query_task_state(struct intel_guc_slpc *slpc)
>> static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
>> {
>> struct intel_guc *guc = slpc_to_guc(slpc);
>> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> int ret;
>>
>> GEM_BUG_ON(id >= SLPC_MAX_PARAM);
>>
>> ret = guc_action_slpc_set_param(guc, id, value);
>> if (ret)
>> - i915_probe_error(i915, "Failed to set param %d to %u (%pe)\n",
>> - id, value, ERR_PTR(ret));
>> + guc_probe_error(guc, "SLPC: Failed to set param %d to %u (%pe)\n",
>> + id, value, ERR_PTR(ret));
>>
>> return ret;
>> }
>> @@ -236,8 +233,7 @@ static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
>> SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
>> freq);
>> if (ret)
>> - drm_notice(&i915->drm,
>> - "Failed to send set_param for min freq(%d): (%d)\n",
>> + guc_notice(guc, "SLPC: Failed to send set_param for min freq(%d): (%d)\n",
>> freq, ret);
>> }
>>
>> @@ -267,7 +263,6 @@ static void slpc_boost_work(struct work_struct *work)
>> int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>> {
>> struct intel_guc *guc = slpc_to_guc(slpc);
>> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
>> int err;
>>
>> @@ -275,9 +270,8 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>>
>> err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&slpc->vaddr);
>> if (unlikely(err)) {
>> - i915_probe_error(i915,
>> - "Failed to allocate SLPC struct (err=%pe)\n",
>> - ERR_PTR(err));
>> + guc_probe_error(guc, "SLPC: Failed to allocate SLPC struct (err=%pe)\n",
> while here, drop "err=" just leave "(%pe)"
>
> Michal
>
>> + ERR_PTR(err));
>> return err;
>> }
>>
>> @@ -338,7 +332,6 @@ static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset)
>>
>> static int slpc_reset(struct intel_guc_slpc *slpc)
>> {
>> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> struct intel_guc *guc = slpc_to_guc(slpc);
>> u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
>> int ret;
>> @@ -346,15 +339,14 @@ static int slpc_reset(struct intel_guc_slpc *slpc)
>> ret = guc_action_slpc_reset(guc, offset);
>>
>> if (unlikely(ret < 0)) {
>> - i915_probe_error(i915, "SLPC reset action failed (%pe)\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(guc, "SLPC: Reset action failed (%pe)\n", ERR_PTR(ret));
>> return ret;
>> }
>>
>> if (!ret) {
>> if (wait_for(slpc_is_running(slpc), SLPC_RESET_TIMEOUT_MS)) {
>> - i915_probe_error(i915, "SLPC not enabled! State = %s\n",
>> - slpc_get_state_string(slpc));
>> + guc_probe_error(guc, "SLPC: Not enabled! State = %s\n",
>> + slpc_get_state_string(slpc));
>> return -EIO;
>> }
>> }
>> @@ -495,8 +487,8 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
>> SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
>> val < slpc->rp1_freq);
>> if (ret) {
>> - i915_probe_error(i915, "Failed to toggle efficient freq (%pe)\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(slpc_to_guc(slpc), "SLPC: Failed to toggle efficient freq (%pe)\n",
>> + ERR_PTR(ret));
>> goto out;
>> }
>>
>> @@ -611,15 +603,12 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
>>
>> static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
>> {
>> - struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> int slpc_min_freq;
>> int ret;
>>
>> ret = intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq);
>> if (ret) {
>> - drm_err(&i915->drm,
>> - "Failed to get min freq: (%d)\n",
>> - ret);
>> + guc_err(slpc_to_guc(slpc), "SLPC: Failed to get min freq: (%d)\n", ret);
>> return false;
>> }
>>
>> @@ -685,8 +674,7 @@ int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode)
>> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
>> ret = slpc_set_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
>> if (ret)
>> - drm_err(&i915->drm,
>> - "Override gucrc mode %d failed %d\n",
>> + guc_err(slpc_to_guc(slpc), "SLPC: Override gucrc mode %d failed %d\n",
>> mode, ret);
>> }
>>
>> @@ -702,9 +690,7 @@ int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
>> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
>> ret = slpc_unset_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE);
>> if (ret)
>> - drm_err(&i915->drm,
>> - "Unsetting gucrc mode failed %d\n",
>> - ret);
>> + guc_err(slpc_to_guc(slpc), "SLPC: Unsetting gucrc mode failed %d\n", ret);
>> }
>>
>> return ret;
>> @@ -726,6 +712,7 @@ int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
>> int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>> {
>> struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> + struct intel_guc *guc = slpc_to_guc(slpc);
>> int ret;
>>
>> GEM_BUG_ON(!slpc->vma);
>> @@ -734,8 +721,8 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>>
>> ret = slpc_reset(slpc);
>> if (unlikely(ret < 0)) {
>> - i915_probe_error(i915, "SLPC Reset event returned (%pe)\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(guc, "SLPC: Reset event returned (%pe)\n",
>> + ERR_PTR(ret));
>> return ret;
>> }
>>
>> @@ -753,16 +740,16 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>> /* Set SLPC max limit to RP0 */
>> ret = slpc_use_fused_rp0(slpc);
>> if (unlikely(ret)) {
>> - i915_probe_error(i915, "Failed to set SLPC max to RP0 (%pe)\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(guc, "SLPC: Failed to set max to RP0 (%pe)\n",
>> + ERR_PTR(ret));
>> return ret;
>> }
>>
>> /* Revert SLPC min/max to softlimits if necessary */
>> ret = slpc_set_softlimits(slpc);
>> if (unlikely(ret)) {
>> - i915_probe_error(i915, "Failed to set SLPC softlimits (%pe)\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(guc, "SLPC: Failed to set softlimits (%pe)\n",
>> + ERR_PTR(ret));
>> return ret;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> index 0a42f1807f52c..da8ab18aa4ce7 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> @@ -1443,8 +1443,7 @@ static void guc_init_engine_stats(struct intel_guc *guc)
>> int ret = guc_action_enable_usage_stats(guc);
>>
>> if (ret)
>> - drm_err(>->i915->drm,
>> - "Failed to enable usage stats: %d!\n", ret);
>> + guc_err(guc, "Failed to enable usage stats: %d!\n", ret);
>> }
>> }
>>
>> @@ -3584,8 +3583,7 @@ static int guc_request_alloc(struct i915_request *rq)
>> intel_context_sched_disable_unpin(ce);
>> else if (intel_context_is_closed(ce))
>> if (wait_for(context_close_done(ce), 1500))
>> - drm_warn(&guc_to_gt(guc)->i915->drm,
>> - "timed out waiting on context sched close before realloc\n");
>> + guc_warn(guc, "timed out waiting on context sched close before realloc\n");
>> /*
>> * Call pin_guc_id here rather than in the pinning step as with
>> * dma_resv, contexts can be repeatedly pinned / unpinned trashing the
>> @@ -4350,7 +4348,7 @@ static int __guc_action_set_scheduling_policies(struct intel_guc *guc,
>> return ret;
>>
>> if (ret != policy->count) {
>> - drm_warn(&guc_to_gt(guc)->i915->drm, "GuC global scheduler policy processed %d of %d KLVs!",
>> + guc_warn(guc, "H2G: global scheduler policy processed %d of %d KLVs!\n",
>> ret, policy->count);
>> if (ret > policy->count)
>> return -EPROTO;
>> @@ -4383,9 +4381,9 @@ static int guc_init_global_schedule_policy(struct intel_guc *guc)
>>
>> ret = __guc_action_set_scheduling_policies(guc, &policy);
>> if (ret)
>> - i915_probe_error(gt->i915,
>> - "Failed to configure global scheduling policies: %pe!\n",
>> - ERR_PTR(ret));
>> + guc_probe_error(guc,
>> + "Failed to configure global scheduling policies: %pe!\n",
>> + ERR_PTR(ret));
>> }
>>
>> return ret;
>> @@ -4484,21 +4482,18 @@ g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)
>> struct intel_context *ce;
>>
>> if (unlikely(ctx_id >= GUC_MAX_CONTEXT_ID)) {
>> - drm_err(&guc_to_gt(guc)->i915->drm,
>> - "Invalid ctx_id %u\n", ctx_id);
>> + guc_err(guc, "Invalid ctx_id %u\n", ctx_id);
>> return NULL;
>> }
>>
>> ce = __get_context(guc, ctx_id);
>> if (unlikely(!ce)) {
>> - drm_err(&guc_to_gt(guc)->i915->drm,
>> - "Context is NULL, ctx_id %u\n", ctx_id);
>> + guc_err(guc, "Context is NULL, ctx_id %u\n", ctx_id);
>> return NULL;
>> }
>>
>> if (unlikely(intel_context_is_child(ce))) {
>> - drm_err(&guc_to_gt(guc)->i915->drm,
>> - "Context is child, ctx_id %u\n", ctx_id);
>> + guc_err(guc, "Context is child, ctx_id %u\n", ctx_id);
>> return NULL;
>> }
>>
>> @@ -4513,7 +4508,7 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
>> u32 ctx_id;
>>
>> if (unlikely(len < 1)) {
>> - drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
>> + guc_err(guc, "notification: Invalid length %u for deregister done\n", len);
>> return -EPROTO;
>> }
>> ctx_id = msg[0];
>> @@ -4565,7 +4560,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
>> u32 ctx_id;
>>
>> if (unlikely(len < 2)) {
>> - drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
>> + guc_err(guc, "notification: Invalid length %u for sched done\n", len);
>> return -EPROTO;
>> }
>> ctx_id = msg[0];
>> @@ -4577,8 +4572,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
>> if (unlikely(context_destroyed(ce) ||
>> (!context_pending_enable(ce) &&
>> !context_pending_disable(ce)))) {
>> - drm_err(&guc_to_gt(guc)->i915->drm,
>> - "Bad context sched_state 0x%x, ctx_id %u\n",
>> + guc_err(guc, "notification: Bad context sched_state 0x%x, ctx_id %u\n",
>> ce->guc_state.sched_state, ctx_id);
>> return -EPROTO;
>> }
>> @@ -4666,8 +4660,8 @@ static void guc_handle_context_reset(struct intel_guc *guc,
>> capture_error_state(guc, ce);
>> guc_context_replay(ce);
>> } else {
>> - drm_info(&guc_to_gt(guc)->i915->drm,
>> - "Ignoring context reset notification of exiting context 0x%04X on %s",
>> + guc_info(guc,
>> + "Ignoring context reset notification of exiting context 0x%04X on %s\n",
>> ce->guc_id.id, ce->engine->name);
>> }
>> }
>> @@ -4680,7 +4674,7 @@ int intel_guc_context_reset_process_msg(struct intel_guc *guc,
>> int ctx_id;
>>
>> if (unlikely(len != 1)) {
>> - drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
>> + guc_err(guc, "notification: Invalid length %u for context reset\n", len);
>> return -EPROTO;
>> }
>>
>> @@ -4713,13 +4707,13 @@ int intel_guc_error_capture_process_msg(struct intel_guc *guc,
>> u32 status;
>>
>> if (unlikely(len != 1)) {
>> - drm_dbg(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
>> + guc_err(guc, "notification: Invalid length %u for error capture\n", len);
>> return -EPROTO;
>> }
>>
>> status = msg[0] & INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK;
>> if (status == INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE)
>> - drm_warn(&guc_to_gt(guc)->i915->drm, "G2H-Error capture no space");
>> + guc_warn(guc, "notification: Error capture buffer overflow\n");
>>
>> intel_guc_capture_process(guc);
>>
>> @@ -4762,13 +4756,12 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
>> const u32 *msg, u32 len)
>> {
>> struct intel_engine_cs *engine;
>> - struct intel_gt *gt = guc_to_gt(guc);
>> u8 guc_class, instance;
>> u32 reason;
>> unsigned long flags;
>>
>> if (unlikely(len != 3)) {
>> - drm_err(>->i915->drm, "Invalid length %u", len);
>> + guc_err(guc, "notification: Invalid length %u for engine failure\n", len);
>> return -EPROTO;
>> }
>>
>> @@ -4778,8 +4771,8 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
>>
>> engine = intel_guc_lookup_engine(guc, guc_class, instance);
>> if (unlikely(!engine)) {
>> - drm_err(>->i915->drm,
>> - "Invalid engine %d:%d", guc_class, instance);
>> + guc_err(guc, "notification: Invalid engine %d:%d for engine failure\n",
>> + guc_class, instance);
>> return -EPROTO;
>> }
>>
>> @@ -4787,7 +4780,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
>> * This is an unexpected failure of a hardware feature. So, log a real
>> * error message not just the informational that comes with the reset.
>> */
>> - drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X",
>> + guc_err(guc, "notification: Engine reset request failed on %d:%d (%s) because 0x%08X\n",
>> guc_class, instance, engine->name, reason);
>>
>> spin_lock_irqsave(&guc->submission_state.lock, flags);
>> @@ -5297,6 +5290,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
>> unsigned long flags)
>> {
>> struct guc_virtual_engine *ve;
>> + struct intel_gt *gt;
>> struct intel_guc *guc;
>> unsigned int n;
>> int err;
>> @@ -5305,10 +5299,11 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
>> if (!ve)
>> return ERR_PTR(-ENOMEM);
>>
>> - guc = &siblings[0]->gt->uc.guc;
>> + gt = siblings[0]->gt;
>> + guc = >->uc.guc;
>>
>> ve->base.i915 = siblings[0]->i915;
>> - ve->base.gt = siblings[0]->gt;
>> + ve->base.gt = gt;
>> ve->base.uncore = siblings[0]->uncore;
>> ve->base.id = -1;
>>
>> @@ -5336,8 +5331,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
>>
>> GEM_BUG_ON(!is_power_of_2(sibling->mask));
>> if (sibling->mask & ve->base.mask) {
>> - DRM_DEBUG("duplicate %s entry in load balancer\n",
>> - sibling->name);
>> + guc_dbg(guc, "Duplicate %s entry in load balancer\n", sibling->name);
>> err = -EINVAL;
>> goto err_put;
>> }
>> @@ -5346,8 +5340,8 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
>> ve->base.logical_mask |= sibling->logical_mask;
>>
>> if (n != 0 && ve->base.class != sibling->class) {
>> - DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n",
>> - sibling->class, ve->base.class);
>> + guc_dbg(guc, "Invalid mixing of engine class, sibling %d, already %d\n",
>> + sibling->class, ve->base.class);
>> err = -EINVAL;
>> goto err_put;
>> } else if (n == 0) {
>> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
>> index e28518fe8b908..d588c32d65c54 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
>> @@ -65,7 +65,7 @@ static int intel_guc_scrub_ctbs(void *arg)
>> ce = intel_context_create(engine);
>> if (IS_ERR(ce)) {
>> ret = PTR_ERR(ce);
>> - drm_err(>->i915->drm, "Failed to create context, %d: %d\n", i, ret);
>> + gt_err(gt, "Failed to create context, %d: %d\n", i, ret);
>> goto err;
>> }
>>
>> @@ -86,7 +86,7 @@ static int intel_guc_scrub_ctbs(void *arg)
>>
>> if (IS_ERR(rq)) {
>> ret = PTR_ERR(rq);
>> - drm_err(>->i915->drm, "Failed to create request, %d: %d\n", i, ret);
>> + gt_err(gt, "Failed to create request, %d: %d\n", i, ret);
>> goto err;
>> }
>>
>> @@ -96,7 +96,7 @@ static int intel_guc_scrub_ctbs(void *arg)
>> for (i = 0; i < 3; ++i) {
>> ret = i915_request_wait(last[i], 0, HZ);
>> if (ret < 0) {
>> - drm_err(>->i915->drm, "Last request failed to complete: %d\n", ret);
>> + gt_err(gt, "Last request failed to complete: %d\n", ret);
>> goto err;
>> }
>> i915_request_put(last[i]);
>> @@ -113,7 +113,7 @@ static int intel_guc_scrub_ctbs(void *arg)
>> /* GT will not idle if G2H are lost */
>> ret = intel_gt_wait_for_idle(gt, HZ);
>> if (ret < 0) {
>> - drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
>> + gt_err(gt, "GT failed to idle: %d\n", ret);
>> goto err;
>> }
>>
>> @@ -153,7 +153,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>>
>> ce = kcalloc(GUC_MAX_CONTEXT_ID, sizeof(*ce), GFP_KERNEL);
>> if (!ce) {
>> - drm_err(>->i915->drm, "Context array allocation failed\n");
>> + guc_err(guc, "Context array allocation failed\n");
>> return -ENOMEM;
>> }
>>
>> @@ -167,24 +167,24 @@ static int intel_guc_steal_guc_ids(void *arg)
>> if (IS_ERR(ce[context_index])) {
>> ret = PTR_ERR(ce[context_index]);
>> ce[context_index] = NULL;
>> - drm_err(>->i915->drm, "Failed to create context: %d\n", ret);
>> + guc_err(guc, "Failed to create context: %d\n", ret);
>> goto err_wakeref;
>> }
>> ret = igt_spinner_init(&spin, engine->gt);
>> if (ret) {
>> - drm_err(>->i915->drm, "Failed to create spinner: %d\n", ret);
>> + guc_err(guc, "Failed to create spinner: %d\n", ret);
>> goto err_contexts;
>> }
>> spin_rq = igt_spinner_create_request(&spin, ce[context_index],
>> MI_ARB_CHECK);
>> if (IS_ERR(spin_rq)) {
>> ret = PTR_ERR(spin_rq);
>> - drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
>> + guc_err(guc, "Failed to create spinner request: %d\n", ret);
>> goto err_contexts;
>> }
>> ret = request_add_spin(spin_rq, &spin);
>> if (ret) {
>> - drm_err(>->i915->drm, "Failed to add Spinner request: %d\n", ret);
>> + guc_err(guc, "Failed to add Spinner request: %d\n", ret);
>> goto err_spin_rq;
>> }
>>
>> @@ -194,7 +194,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>> if (IS_ERR(ce[context_index])) {
>> ret = PTR_ERR(ce[context_index--]);
>> ce[context_index] = NULL;
>> - drm_err(>->i915->drm, "Failed to create context: %d\n", ret);
>> + guc_err(guc, "Failed to create context: %d\n", ret);
>> goto err_spin_rq;
>> }
>>
>> @@ -203,7 +203,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>> ret = PTR_ERR(rq);
>> rq = NULL;
>> if (ret != -EAGAIN) {
>> - drm_err(>->i915->drm, "Failed to create request, %d: %d\n",
>> + guc_err(guc, "Failed to create request, %d: %d\n",
>> context_index, ret);
>> goto err_spin_rq;
>> }
>> @@ -218,7 +218,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>> igt_spinner_end(&spin);
>> ret = intel_selftest_wait_for_rq(spin_rq);
>> if (ret) {
>> - drm_err(>->i915->drm, "Spin request failed to complete: %d\n", ret);
>> + guc_err(guc, "Spin request failed to complete: %d\n", ret);
>> i915_request_put(last);
>> goto err_spin_rq;
>> }
>> @@ -230,7 +230,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>> ret = i915_request_wait(last, 0, HZ * 30);
>> i915_request_put(last);
>> if (ret < 0) {
>> - drm_err(>->i915->drm, "Last request failed to complete: %d\n", ret);
>> + guc_err(guc, "Last request failed to complete: %d\n", ret);
>> goto err_spin_rq;
>> }
>>
>> @@ -238,7 +238,7 @@ static int intel_guc_steal_guc_ids(void *arg)
>> rq = nop_user_request(ce[context_index], NULL);
>> if (IS_ERR(rq)) {
>> ret = PTR_ERR(rq);
>> - drm_err(>->i915->drm, "Failed to steal guc_id, %d: %d\n", context_index, ret);
>> + guc_err(guc, "Failed to steal guc_id, %d: %d\n", context_index, ret);
>> goto err_spin_rq;
>> }
>>
>> @@ -246,20 +246,20 @@ static int intel_guc_steal_guc_ids(void *arg)
>> ret = i915_request_wait(rq, 0, HZ);
>> i915_request_put(rq);
>> if (ret < 0) {
>> - drm_err(>->i915->drm, "Request with stolen guc_id failed to complete: %d\n", ret);
>> + guc_err(guc, "Request with stolen guc_id failed to complete: %d\n", ret);
>> goto err_spin_rq;
>> }
>>
>> /* Wait for idle */
>> ret = intel_gt_wait_for_idle(gt, HZ * 30);
>> if (ret < 0) {
>> - drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
>> + guc_err(guc, "GT failed to idle: %d\n", ret);
>> goto err_spin_rq;
>> }
>>
>> /* Verify a guc_id was stolen */
>> if (guc->number_guc_id_stolen == number_guc_id_stolen) {
>> - drm_err(>->i915->drm, "No guc_id was stolen");
>> + guc_err(guc, "No guc_id was stolen\n");
>> ret = -EINVAL;
>> } else {
>> ret = 0;
>> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
>> index d91b58f704039..07018ec75c21f 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
>> @@ -45,7 +45,7 @@ static int intel_hang_guc(void *arg)
>>
>> ctx = kernel_context(gt->i915, NULL);
>> if (IS_ERR(ctx)) {
>> - drm_err(>->i915->drm, "Failed get kernel context: %ld\n", PTR_ERR(ctx));
>> + gt_err(gt, "Failed get kernel context: %ld\n", PTR_ERR(ctx));
>> return PTR_ERR(ctx);
>> }
>>
>> @@ -54,7 +54,7 @@ static int intel_hang_guc(void *arg)
>> ce = intel_context_create(engine);
>> if (IS_ERR(ce)) {
>> ret = PTR_ERR(ce);
>> - drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
>> + gt_err(gt, "Failed to create spinner request: %d\n", ret);
>> goto err;
>> }
>>
>> @@ -63,13 +63,13 @@ static int intel_hang_guc(void *arg)
>> old_beat = engine->props.heartbeat_interval_ms;
>> ret = intel_engine_set_heartbeat(engine, BEAT_INTERVAL);
>> if (ret) {
>> - drm_err(>->i915->drm, "Failed to boost heatbeat interval: %d\n", ret);
>> + gt_err(gt, "Failed to boost heatbeat interval: %d\n", ret);
>> goto err;
>> }
>>
>> ret = igt_spinner_init(&spin, engine->gt);
>> if (ret) {
>> - drm_err(>->i915->drm, "Failed to create spinner: %d\n", ret);
>> + gt_err(gt, "Failed to create spinner: %d\n", ret);
>> goto err;
>> }
>>
>> @@ -77,28 +77,28 @@ static int intel_hang_guc(void *arg)
>> intel_context_put(ce);
>> if (IS_ERR(rq)) {
>> ret = PTR_ERR(rq);
>> - drm_err(>->i915->drm, "Failed to create spinner request: %d\n", ret);
>> + gt_err(gt, "Failed to create spinner request: %d\n", ret);
>> goto err_spin;
>> }
>>
>> ret = request_add_spin(rq, &spin);
>> if (ret) {
>> i915_request_put(rq);
>> - drm_err(>->i915->drm, "Failed to add Spinner request: %d\n", ret);
>> + gt_err(gt, "Failed to add Spinner request: %d\n", ret);
>> goto err_spin;
>> }
>>
>> ret = intel_reset_guc(gt);
>> if (ret) {
>> i915_request_put(rq);
>> - drm_err(>->i915->drm, "Failed to reset GuC, ret = %d\n", ret);
>> + gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
>> goto err_spin;
>> }
>>
>> guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
>> if (!(guc_status & GS_MIA_IN_RESET)) {
>> i915_request_put(rq);
>> - drm_err(>->i915->drm, "GuC failed to reset: status = 0x%08X\n", guc_status);
>> + gt_err(gt, "GuC failed to reset: status = 0x%08X\n", guc_status);
>> ret = -EIO;
>> goto err_spin;
>> }
>> @@ -107,12 +107,12 @@ static int intel_hang_guc(void *arg)
>> ret = intel_selftest_wait_for_rq(rq);
>> i915_request_put(rq);
>> if (ret) {
>> - drm_err(>->i915->drm, "Request failed to complete: %d\n", ret);
>> + gt_err(gt, "Request failed to complete: %d\n", ret);
>> goto err_spin;
>> }
>>
>> if (i915_reset_count(global) == reset_count) {
>> - drm_err(>->i915->drm, "Failed to record a GPU reset\n");
>> + gt_err(gt, "Failed to record a GPU reset\n");
>> ret = -EINVAL;
>> goto err_spin;
>> }
>> @@ -132,7 +132,7 @@ static int intel_hang_guc(void *arg)
>> ret = intel_selftest_wait_for_rq(rq);
>> i915_request_put(rq);
>> if (ret) {
>> - drm_err(>->i915->drm, "No-op failed to complete: %d\n", ret);
>> + gt_err(gt, "No-op failed to complete: %d\n", ret);
>> goto err;
>> }
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
>> index d17982c36d256..04e28735a2ee6 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c
>> @@ -115,30 +115,30 @@ static int __intel_guc_multi_lrc_basic(struct intel_gt *gt, unsigned int class)
>>
>> parent = multi_lrc_create_parent(gt, class, 0);
>> if (IS_ERR(parent)) {
>> - drm_err(>->i915->drm, "Failed creating contexts: %ld", PTR_ERR(parent));
>> + gt_err(gt, "Failed creating contexts: %ld", PTR_ERR(parent));
>> return PTR_ERR(parent);
>> } else if (!parent) {
>> - drm_dbg(>->i915->drm, "Not enough engines in class: %d", class);
>> + gt_dbg(gt, "Not enough engines in class: %d", class);
>> return 0;
>> }
>>
>> rq = multi_lrc_nop_request(parent);
>> if (IS_ERR(rq)) {
>> ret = PTR_ERR(rq);
>> - drm_err(>->i915->drm, "Failed creating requests: %d", ret);
>> + gt_err(gt, "Failed creating requests: %d", ret);
>> goto out;
>> }
>>
>> ret = intel_selftest_wait_for_rq(rq);
>> if (ret)
>> - drm_err(>->i915->drm, "Failed waiting on request: %d", ret);
>> + gt_err(gt, "Failed waiting on request: %d", ret);
>>
>> i915_request_put(rq);
>>
>> if (ret >= 0) {
>> ret = intel_gt_wait_for_idle(gt, HZ * 5);
>> if (ret < 0)
>> - drm_err(>->i915->drm, "GT failed to idle: %d\n", ret);
>> + gt_err(gt, "GT failed to idle: %d\n", ret);
>> }
>>
>> out:
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
@ 2022-11-18 1:58 ` John.C.Harrison
-1 siblings, 0 replies; 51+ messages in thread
From: John.C.Harrison @ 2022-11-18 1:58 UTC (permalink / raw)
To: Intel-GFX; +Cc: John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
Re-work the existing GuC CT printers and extend as required to match
the new wrapping scheme.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++++-----------
1 file changed, 113 insertions(+), 109 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 2b22065e87bf9..9d404fb377637 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -18,31 +18,49 @@ static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
return container_of(ct, struct intel_guc, ct);
}
-static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
-{
- return guc_to_gt(ct_to_guc(ct));
-}
-
static inline struct drm_i915_private *ct_to_i915(struct intel_guc_ct *ct)
{
- return ct_to_gt(ct)->i915;
-}
+ struct intel_guc *guc = ct_to_guc(ct);
+ struct intel_gt *gt = guc_to_gt(guc);
-static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
-{
- return &ct_to_i915(ct)->drm;
+ return gt->i915;
}
-#define CT_ERROR(_ct, _fmt, ...) \
- drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+#define ct_err(_ct, _fmt, ...) \
+ guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_warn(_ct, _fmt, ...) \
+ guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_notice(_ct, _fmt, ...) \
+ guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_info(_ct, _fmt, ...) \
+ guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
#ifdef CONFIG_DRM_I915_DEBUG_GUC
-#define CT_DEBUG(_ct, _fmt, ...) \
- drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+#define ct_dbg(_ct, _fmt, ...) \
+ guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
#else
-#define CT_DEBUG(...) do { } while (0)
+#define ct_dbg(...) do { } while (0)
#endif
-#define CT_PROBE_ERROR(_ct, _fmt, ...) \
- i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+
+#define ct_probe_error(_ct, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
+ else \
+ ct_err(_ct, _fmt, ##__VA_ARGS__); \
+ } while (0)
+
+#define ct_WARN_ON(_ct, _condition) \
+ ct_WARN(_ct, _condition, "%s", "ct_WARN_ON(" __stringify(_condition) ")")
+
+#define ct_WARN(_ct, _condition, _fmt, ...) \
+ guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
+ guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
/**
* DOC: CTB Blob
@@ -170,7 +188,7 @@ static int ct_control_enable(struct intel_guc_ct *ct, bool enable)
err = guc_action_control_ctb(ct_to_guc(ct), enable ?
GUC_CTB_CONTROL_ENABLE : GUC_CTB_CONTROL_DISABLE);
if (unlikely(err))
- CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
+ ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
str_enable_disable(enable), ERR_PTR(err));
return err;
@@ -201,7 +219,7 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
size);
if (unlikely(err))
failed:
- CT_PROBE_ERROR(ct, "Failed to register %s buffer (%pe)\n",
+ ct_probe_error(ct, "Failed to register %s buffer (%pe)\n",
send ? "SEND" : "RECV", ERR_PTR(err));
return err;
@@ -235,21 +253,21 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE + CTB_G2H_BUFFER_SIZE;
err = intel_guc_allocate_and_map_vma(guc, blob_size, &ct->vma, &blob);
if (unlikely(err)) {
- CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data (%pe)\n",
+ ct_probe_error(ct, "Failed to allocate %u for CTB data (%pe)\n",
blob_size, ERR_PTR(err));
return err;
}
- CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
+ ct_dbg(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
/* store pointers to desc and cmds for send ctb */
desc = blob;
cmds = blob + 2 * CTB_DESC_SIZE;
cmds_size = CTB_H2G_BUFFER_SIZE;
resv_space = 0;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
- resv_space);
+ ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
+ ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
+ resv_space);
guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
@@ -258,9 +276,9 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
cmds_size = CTB_G2H_BUFFER_SIZE;
resv_space = G2H_ROOM_BUFFER_SIZE;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
- resv_space);
+ ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
+ ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
+ resv_space);
guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
@@ -338,7 +356,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
return 0;
err_out:
- CT_PROBE_ERROR(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
+ ct_probe_error(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
return err;
}
@@ -387,14 +405,12 @@ static int ct_write(struct intel_guc_ct *ct,
#ifdef CONFIG_DRM_I915_DEBUG_GUC
if (unlikely(tail != READ_ONCE(desc->tail))) {
- CT_ERROR(ct, "Tail was modified %u != %u\n",
- desc->tail, tail);
+ ct_err(ct, "Tail was modified %u != %u\n", desc->tail, tail);
desc->status |= GUC_CTB_STATUS_MISMATCH;
goto corrupted;
}
if (unlikely(READ_ONCE(desc->head) >= size)) {
- CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
- desc->head, size);
+ ct_err(ct, "Invalid head offset %u >= %u)\n", desc->head, size);
desc->status |= GUC_CTB_STATUS_OVERFLOW;
goto corrupted;
}
@@ -415,8 +431,8 @@ static int ct_write(struct intel_guc_ct *ct,
FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |
GUC_HXG_EVENT_MSG_0_DATA0, action[0]);
- CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
- tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
+ ct_dbg(ct, "writing (tail %u) %*ph %*ph %*ph\n",
+ tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
cmds[tail] = header;
tail = (tail + 1) % size;
@@ -447,8 +463,8 @@ static int ct_write(struct intel_guc_ct *ct,
return 0;
corrupted:
- CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
- desc->head, desc->tail, desc->status);
+ ct_err(ct, "Corrupted descriptor on write head=%u tail=%u status=%#x\n",
+ desc->head, desc->tail, desc->status);
ctb->broken = true;
return -EPIPE;
}
@@ -507,17 +523,14 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
- CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
- ktime_ms_delta(ktime_get(), ct->stall_time),
- send->status, recv->status);
- CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
- atomic_read(&ct->ctbs.send.space) * 4);
- CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
- CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
- CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
- atomic_read(&ct->ctbs.recv.space) * 4);
- CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
- CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
+ ct_err(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
+ ktime_ms_delta(ktime_get(), ct->stall_time), send->status, recv->status);
+ ct_err(ct, "H2G Space: %u (Bytes)\n", atomic_read(&ct->ctbs.send.space) * 4);
+ ct_err(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
+ ct_err(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
+ ct_err(ct, "G2H Space: %u (Bytes)\n", atomic_read(&ct->ctbs.recv.space) * 4);
+ ct_err(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
+ ct_err(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
ct->ctbs.send.broken = true;
}
@@ -563,8 +576,7 @@ static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
head = READ_ONCE(desc->head);
if (unlikely(head > ctb->size)) {
- CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
- head, ctb->size);
+ ct_err(ct, "Invalid head offset %u >= %u)\n", head, ctb->size);
desc->status |= GUC_CTB_STATUS_OVERFLOW;
ctb->broken = true;
return false;
@@ -715,17 +727,17 @@ static int ct_send(struct intel_guc_ct *ct,
/* wait_for_ct_request_update returns -ENODEV on reset/suspend in progress.
* In this case, output is debug rather than error info
*/
- CT_DEBUG(ct, "Request %#x (fence %u) cancelled as CTB is disabled\n",
- action[0], request.fence);
+ ct_dbg(ct, "Request %#x (fence %u) cancelled as CTB is disabled\n",
+ action[0], request.fence);
else
- CT_ERROR(ct, "No response for request %#x (fence %u)\n",
- action[0], request.fence);
+ ct_err(ct, "No response for request %#x (fence %u)\n",
+ action[0], request.fence);
goto unlink;
}
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, *status) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
- CT_DEBUG(ct, "retrying request %#x (%u)\n", *action,
- FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
+ ct_dbg(ct, "retrying request %#x (%u)\n", *action,
+ FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
send_again = true;
goto unlink;
}
@@ -737,12 +749,12 @@ static int ct_send(struct intel_guc_ct *ct,
if (response_buf) {
/* There shall be no data in the status */
- WARN_ON(FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, request.status));
+ ct_WARN_ON(ct, FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, request.status));
/* Return actual response len */
err = request.response_len;
} else {
/* There shall be no response payload */
- WARN_ON(request.response_len);
+ ct_WARN_ON(ct, request.response_len);
/* Return data decoded from the status dword */
err = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, *status);
}
@@ -771,7 +783,7 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
struct intel_guc *guc = ct_to_guc(ct);
struct intel_uc *uc = container_of(guc, struct intel_uc, guc);
- WARN(!uc->reset_in_progress, "Unexpected send: action=%#x\n", *action);
+ ct_WARN(ct, !uc->reset_in_progress, "Unexpected send: action=%#x\n", *action);
return -ENODEV;
}
@@ -784,11 +796,11 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
ret = ct_send(ct, action, len, response_buf, response_buf_size, &status);
if (unlikely(ret < 0)) {
if (ret != -ENODEV)
- CT_ERROR(ct, "Sending action %#x failed (%pe) status=%#X\n",
- action[0], ERR_PTR(ret), status);
+ ct_err(ct, "sending action %#x failed (%pe) status=%#X\n",
+ action[0], ERR_PTR(ret), status);
} else if (unlikely(ret)) {
- CT_DEBUG(ct, "send action %#x returned %d (%#x)\n",
- action[0], ret, ret);
+ ct_dbg(ct, "send action %#x returned %d (%#x)\n",
+ action[0], ret, ret);
}
return ret;
@@ -838,7 +850,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
* contexts/engines being reset. But should never happen as
* no contexts should be active when CLIENT_RESET is sent.
*/
- CT_ERROR(ct, "Unexpected G2H after GuC has stopped!\n");
+ ct_err(ct, "Unexpected G2H after GuC has stopped!\n");
status &= ~GUC_CTB_STATUS_UNUSED;
}
@@ -850,15 +862,13 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
#ifdef CONFIG_DRM_I915_DEBUG_GUC
if (unlikely(head != READ_ONCE(desc->head))) {
- CT_ERROR(ct, "Head was modified %u != %u\n",
- desc->head, head);
+ ct_err(ct, "Head was modified %u != %u\n", desc->head, head);
desc->status |= GUC_CTB_STATUS_MISMATCH;
goto corrupted;
}
#endif
if (unlikely(tail >= size)) {
- CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
- tail, size);
+ ct_err(ct, "Invalid tail offset %u >= %u)\n", tail, size);
desc->status |= GUC_CTB_STATUS_OVERFLOW;
goto corrupted;
}
@@ -873,7 +883,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
/* beware of buffer wrap case */
if (unlikely(available < 0))
available += size;
- CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
+ ct_dbg(ct, "read available %d (%u:%u:%u)\n", available, head, tail, size);
GEM_BUG_ON(available < 0);
header = cmds[head];
@@ -882,24 +892,24 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
/* message len with header */
len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, header) + GUC_CTB_MSG_MIN_LEN;
if (unlikely(len > (u32)available)) {
- CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
- 4, &header,
- 4 * (head + available - 1 > size ?
- size - head : available - 1), &cmds[head],
- 4 * (head + available - 1 > size ?
- available - 1 - size + head : 0), &cmds[0]);
+ ct_err(ct, "Incomplete message %*ph %*ph %*ph\n",
+ 4, &header,
+ 4 * (head + available - 1 > size ?
+ size - head : available - 1), &cmds[head],
+ 4 * (head + available - 1 > size ?
+ available - 1 - size + head : 0), &cmds[0]);
desc->status |= GUC_CTB_STATUS_UNDERFLOW;
goto corrupted;
}
*msg = ct_alloc_msg(len);
if (!*msg) {
- CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
- 4, &header,
- 4 * (head + available - 1 > size ?
- size - head : available - 1), &cmds[head],
- 4 * (head + available - 1 > size ?
- available - 1 - size + head : 0), &cmds[0]);
+ ct_err(ct, "No memory for message %*ph %*ph %*ph\n",
+ 4, &header,
+ 4 * (head + available - 1 > size ?
+ size - head : available - 1), &cmds[head],
+ 4 * (head + available - 1 > size ?
+ available - 1 - size + head : 0), &cmds[0]);
return available;
}
@@ -909,7 +919,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
(*msg)->msg[i] = cmds[head];
head = (head + 1) % size;
}
- CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
+ ct_dbg(ct, "received %*ph\n", 4 * len, (*msg)->msg);
/* update local copies */
ctb->head = head;
@@ -920,8 +930,8 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
return available - len;
corrupted:
- CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
- desc->head, desc->tail, desc->status);
+ ct_err(ct, "Corrupted descriptor on read head=%u tail=%u status=%#x\n",
+ desc->head, desc->tail, desc->status);
ctb->broken = true;
return -EPIPE;
}
@@ -944,18 +954,17 @@ static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *r
FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_NO_RESPONSE_RETRY &&
FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_RESPONSE_FAILURE);
- CT_DEBUG(ct, "response fence %u status %#x\n", fence, hxg[0]);
+ ct_dbg(ct, "response fence %u status %#x\n", fence, hxg[0]);
spin_lock_irqsave(&ct->requests.lock, flags);
list_for_each_entry(req, &ct->requests.pending, link) {
if (unlikely(fence != req->fence)) {
- CT_DEBUG(ct, "request %u awaits response\n",
- req->fence);
+ ct_dbg(ct, "request %u awaits response\n", req->fence);
continue;
}
if (unlikely(datalen > req->response_len)) {
- CT_ERROR(ct, "Response %u too long (datalen %u > %u)\n",
- req->fence, datalen, req->response_len);
+ ct_err(ct, "response %u too long (datalen %u > %u)\n",
+ req->fence, datalen, req->response_len);
datalen = min(datalen, req->response_len);
err = -EMSGSIZE;
}
@@ -967,12 +976,11 @@ static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *r
break;
}
if (!found) {
- CT_ERROR(ct, "Unsolicited response (fence %u)\n", fence);
- CT_ERROR(ct, "Could not find fence=%u, last_fence=%u\n", fence,
- ct->requests.last_fence);
+ ct_err(ct, "Unsolicited response (fence %u)\n", fence);
+ ct_err(ct, "Could not find fence=%u, last_fence=%u\n", fence,
+ ct->requests.last_fence);
list_for_each_entry(req, &ct->requests.pending, link)
- CT_ERROR(ct, "request %u awaits response\n",
- req->fence);
+ ct_err(ct, "request %u awaits response\n", req->fence);
err = -ENOKEY;
}
spin_unlock_irqrestore(&ct->requests.lock, flags);
@@ -998,7 +1006,7 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, hxg[0]);
len = hxg_len - GUC_HXG_MSG_MIN_LEN;
- CT_DEBUG(ct, "request %x %*ph\n", action, 4 * len, payload);
+ ct_dbg(ct, "request %x %*ph\n", action, 4 * len, payload);
switch (action) {
case INTEL_GUC_ACTION_DEFAULT:
@@ -1016,9 +1024,6 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
break;
case INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION:
ret = intel_guc_error_capture_process_msg(guc, payload, len);
- if (unlikely(ret))
- CT_ERROR(ct, "error capture notification failed %x %*ph\n",
- action, 4 * len, payload);
break;
case INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION:
ret = intel_guc_engine_failure_process_msg(guc, payload, len);
@@ -1028,11 +1033,11 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
ret = 0;
break;
case INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED:
- CT_ERROR(ct, "Received GuC crash dump notification!\n");
+ guc_err(guc, "notification: Crash dump!\n");
ret = 0;
break;
case INTEL_GUC_ACTION_NOTIFY_EXCEPTION:
- CT_ERROR(ct, "Received GuC exception notification!\n");
+ guc_err(guc, "notification: Exception!\n");
ret = 0;
break;
default:
@@ -1041,8 +1046,7 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
}
if (unlikely(ret)) {
- CT_ERROR(ct, "Failed to process request %04x (%pe)\n",
- action, ERR_PTR(ret));
+ ct_err(ct, "Failed to process request %04x (%pe)\n", action, ERR_PTR(ret));
return ret;
}
@@ -1070,8 +1074,8 @@ static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
err = ct_process_request(ct, request);
if (unlikely(err)) {
- CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
- ERR_PTR(err), 4 * request->size, request->msg);
+ ct_err(ct, "Failed to process message (%pe) %*ph\n",
+ ERR_PTR(err), 4 * request->size, request->msg);
ct_free_msg(request);
}
@@ -1149,8 +1153,8 @@ static int ct_handle_hxg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg)
if (unlikely(err)) {
failed:
- CT_ERROR(ct, "Failed to handle HXG message (%pe) %*ph\n",
- ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
+ ct_err(ct, "Failed to handle HXG message (%pe) %*ph\n",
+ ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
}
return err;
}
@@ -1166,8 +1170,8 @@ static void ct_handle_msg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg)
err = -EOPNOTSUPP;
if (unlikely(err)) {
- CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
- ERR_PTR(err), 4 * msg->size, msg->msg);
+ ct_err(ct, "Failed to handle message (%pe) %*ph\n",
+ ERR_PTR(err), 4 * msg->size, msg->msg);
ct_free_msg(msg);
}
}
@@ -1198,7 +1202,7 @@ static void ct_try_receive_message(struct intel_guc_ct *ct)
{
int ret;
- if (GEM_WARN_ON(!ct->enabled))
+ if (ct_WARN_ON(ct, !ct->enabled))
return;
ret = ct_receive(ct);
@@ -1220,7 +1224,7 @@ static void ct_receive_tasklet_func(struct tasklet_struct *t)
void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
{
if (unlikely(!ct->enabled)) {
- WARN(1, "Unexpected GuC event received while CT disabled!\n");
+ ct_warn(ct, "Unexpected event received while disabled!\n");
return;
}
--
2.37.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
@ 2022-11-18 1:58 ` John.C.Harrison
0 siblings, 0 replies; 51+ messages in thread
From: John.C.Harrison @ 2022-11-18 1:58 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
Re-work the existing GuC CT printers and extend as required to match
the new wrapping scheme.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++++-----------
1 file changed, 113 insertions(+), 109 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 2b22065e87bf9..9d404fb377637 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -18,31 +18,49 @@ static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
return container_of(ct, struct intel_guc, ct);
}
-static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
-{
- return guc_to_gt(ct_to_guc(ct));
-}
-
static inline struct drm_i915_private *ct_to_i915(struct intel_guc_ct *ct)
{
- return ct_to_gt(ct)->i915;
-}
+ struct intel_guc *guc = ct_to_guc(ct);
+ struct intel_gt *gt = guc_to_gt(guc);
-static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
-{
- return &ct_to_i915(ct)->drm;
+ return gt->i915;
}
-#define CT_ERROR(_ct, _fmt, ...) \
- drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+#define ct_err(_ct, _fmt, ...) \
+ guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_warn(_ct, _fmt, ...) \
+ guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_notice(_ct, _fmt, ...) \
+ guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_info(_ct, _fmt, ...) \
+ guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
+
#ifdef CONFIG_DRM_I915_DEBUG_GUC
-#define CT_DEBUG(_ct, _fmt, ...) \
- drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+#define ct_dbg(_ct, _fmt, ...) \
+ guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
#else
-#define CT_DEBUG(...) do { } while (0)
+#define ct_dbg(...) do { } while (0)
#endif
-#define CT_PROBE_ERROR(_ct, _fmt, ...) \
- i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+
+#define ct_probe_error(_ct, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
+ else \
+ ct_err(_ct, _fmt, ##__VA_ARGS__); \
+ } while (0)
+
+#define ct_WARN_ON(_ct, _condition) \
+ ct_WARN(_ct, _condition, "%s", "ct_WARN_ON(" __stringify(_condition) ")")
+
+#define ct_WARN(_ct, _condition, _fmt, ...) \
+ guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
+
+#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
+ guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
/**
* DOC: CTB Blob
@@ -170,7 +188,7 @@ static int ct_control_enable(struct intel_guc_ct *ct, bool enable)
err = guc_action_control_ctb(ct_to_guc(ct), enable ?
GUC_CTB_CONTROL_ENABLE : GUC_CTB_CONTROL_DISABLE);
if (unlikely(err))
- CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
+ ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
str_enable_disable(enable), ERR_PTR(err));
return err;
@@ -201,7 +219,7 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
size);
if (unlikely(err))
failed:
- CT_PROBE_ERROR(ct, "Failed to register %s buffer (%pe)\n",
+ ct_probe_error(ct, "Failed to register %s buffer (%pe)\n",
send ? "SEND" : "RECV", ERR_PTR(err));
return err;
@@ -235,21 +253,21 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE + CTB_G2H_BUFFER_SIZE;
err = intel_guc_allocate_and_map_vma(guc, blob_size, &ct->vma, &blob);
if (unlikely(err)) {
- CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data (%pe)\n",
+ ct_probe_error(ct, "Failed to allocate %u for CTB data (%pe)\n",
blob_size, ERR_PTR(err));
return err;
}
- CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
+ ct_dbg(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
/* store pointers to desc and cmds for send ctb */
desc = blob;
cmds = blob + 2 * CTB_DESC_SIZE;
cmds_size = CTB_H2G_BUFFER_SIZE;
resv_space = 0;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
- resv_space);
+ ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
+ ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
+ resv_space);
guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
@@ -258,9 +276,9 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
cmds_size = CTB_G2H_BUFFER_SIZE;
resv_space = G2H_ROOM_BUFFER_SIZE;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
- resv_space);
+ ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
+ ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
+ resv_space);
guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
@@ -338,7 +356,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
return 0;
err_out:
- CT_PROBE_ERROR(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
+ ct_probe_error(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
return err;
}
@@ -387,14 +405,12 @@ static int ct_write(struct intel_guc_ct *ct,
#ifdef CONFIG_DRM_I915_DEBUG_GUC
if (unlikely(tail != READ_ONCE(desc->tail))) {
- CT_ERROR(ct, "Tail was modified %u != %u\n",
- desc->tail, tail);
+ ct_err(ct, "Tail was modified %u != %u\n", desc->tail, tail);
desc->status |= GUC_CTB_STATUS_MISMATCH;
goto corrupted;
}
if (unlikely(READ_ONCE(desc->head) >= size)) {
- CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
- desc->head, size);
+ ct_err(ct, "Invalid head offset %u >= %u)\n", desc->head, size);
desc->status |= GUC_CTB_STATUS_OVERFLOW;
goto corrupted;
}
@@ -415,8 +431,8 @@ static int ct_write(struct intel_guc_ct *ct,
FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |
GUC_HXG_EVENT_MSG_0_DATA0, action[0]);
- CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
- tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
+ ct_dbg(ct, "writing (tail %u) %*ph %*ph %*ph\n",
+ tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
cmds[tail] = header;
tail = (tail + 1) % size;
@@ -447,8 +463,8 @@ static int ct_write(struct intel_guc_ct *ct,
return 0;
corrupted:
- CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
- desc->head, desc->tail, desc->status);
+ ct_err(ct, "Corrupted descriptor on write head=%u tail=%u status=%#x\n",
+ desc->head, desc->tail, desc->status);
ctb->broken = true;
return -EPIPE;
}
@@ -507,17 +523,14 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
- CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
- ktime_ms_delta(ktime_get(), ct->stall_time),
- send->status, recv->status);
- CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
- atomic_read(&ct->ctbs.send.space) * 4);
- CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
- CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
- CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
- atomic_read(&ct->ctbs.recv.space) * 4);
- CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
- CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
+ ct_err(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
+ ktime_ms_delta(ktime_get(), ct->stall_time), send->status, recv->status);
+ ct_err(ct, "H2G Space: %u (Bytes)\n", atomic_read(&ct->ctbs.send.space) * 4);
+ ct_err(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
+ ct_err(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
+ ct_err(ct, "G2H Space: %u (Bytes)\n", atomic_read(&ct->ctbs.recv.space) * 4);
+ ct_err(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
+ ct_err(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
ct->ctbs.send.broken = true;
}
@@ -563,8 +576,7 @@ static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
head = READ_ONCE(desc->head);
if (unlikely(head > ctb->size)) {
- CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
- head, ctb->size);
+ ct_err(ct, "Invalid head offset %u >= %u)\n", head, ctb->size);
desc->status |= GUC_CTB_STATUS_OVERFLOW;
ctb->broken = true;
return false;
@@ -715,17 +727,17 @@ static int ct_send(struct intel_guc_ct *ct,
/* wait_for_ct_request_update returns -ENODEV on reset/suspend in progress.
* In this case, output is debug rather than error info
*/
- CT_DEBUG(ct, "Request %#x (fence %u) cancelled as CTB is disabled\n",
- action[0], request.fence);
+ ct_dbg(ct, "Request %#x (fence %u) cancelled as CTB is disabled\n",
+ action[0], request.fence);
else
- CT_ERROR(ct, "No response for request %#x (fence %u)\n",
- action[0], request.fence);
+ ct_err(ct, "No response for request %#x (fence %u)\n",
+ action[0], request.fence);
goto unlink;
}
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, *status) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
- CT_DEBUG(ct, "retrying request %#x (%u)\n", *action,
- FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
+ ct_dbg(ct, "retrying request %#x (%u)\n", *action,
+ FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
send_again = true;
goto unlink;
}
@@ -737,12 +749,12 @@ static int ct_send(struct intel_guc_ct *ct,
if (response_buf) {
/* There shall be no data in the status */
- WARN_ON(FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, request.status));
+ ct_WARN_ON(ct, FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, request.status));
/* Return actual response len */
err = request.response_len;
} else {
/* There shall be no response payload */
- WARN_ON(request.response_len);
+ ct_WARN_ON(ct, request.response_len);
/* Return data decoded from the status dword */
err = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, *status);
}
@@ -771,7 +783,7 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
struct intel_guc *guc = ct_to_guc(ct);
struct intel_uc *uc = container_of(guc, struct intel_uc, guc);
- WARN(!uc->reset_in_progress, "Unexpected send: action=%#x\n", *action);
+ ct_WARN(ct, !uc->reset_in_progress, "Unexpected send: action=%#x\n", *action);
return -ENODEV;
}
@@ -784,11 +796,11 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
ret = ct_send(ct, action, len, response_buf, response_buf_size, &status);
if (unlikely(ret < 0)) {
if (ret != -ENODEV)
- CT_ERROR(ct, "Sending action %#x failed (%pe) status=%#X\n",
- action[0], ERR_PTR(ret), status);
+ ct_err(ct, "sending action %#x failed (%pe) status=%#X\n",
+ action[0], ERR_PTR(ret), status);
} else if (unlikely(ret)) {
- CT_DEBUG(ct, "send action %#x returned %d (%#x)\n",
- action[0], ret, ret);
+ ct_dbg(ct, "send action %#x returned %d (%#x)\n",
+ action[0], ret, ret);
}
return ret;
@@ -838,7 +850,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
* contexts/engines being reset. But should never happen as
* no contexts should be active when CLIENT_RESET is sent.
*/
- CT_ERROR(ct, "Unexpected G2H after GuC has stopped!\n");
+ ct_err(ct, "Unexpected G2H after GuC has stopped!\n");
status &= ~GUC_CTB_STATUS_UNUSED;
}
@@ -850,15 +862,13 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
#ifdef CONFIG_DRM_I915_DEBUG_GUC
if (unlikely(head != READ_ONCE(desc->head))) {
- CT_ERROR(ct, "Head was modified %u != %u\n",
- desc->head, head);
+ ct_err(ct, "Head was modified %u != %u\n", desc->head, head);
desc->status |= GUC_CTB_STATUS_MISMATCH;
goto corrupted;
}
#endif
if (unlikely(tail >= size)) {
- CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
- tail, size);
+ ct_err(ct, "Invalid tail offset %u >= %u)\n", tail, size);
desc->status |= GUC_CTB_STATUS_OVERFLOW;
goto corrupted;
}
@@ -873,7 +883,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
/* beware of buffer wrap case */
if (unlikely(available < 0))
available += size;
- CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
+ ct_dbg(ct, "read available %d (%u:%u:%u)\n", available, head, tail, size);
GEM_BUG_ON(available < 0);
header = cmds[head];
@@ -882,24 +892,24 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
/* message len with header */
len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, header) + GUC_CTB_MSG_MIN_LEN;
if (unlikely(len > (u32)available)) {
- CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
- 4, &header,
- 4 * (head + available - 1 > size ?
- size - head : available - 1), &cmds[head],
- 4 * (head + available - 1 > size ?
- available - 1 - size + head : 0), &cmds[0]);
+ ct_err(ct, "Incomplete message %*ph %*ph %*ph\n",
+ 4, &header,
+ 4 * (head + available - 1 > size ?
+ size - head : available - 1), &cmds[head],
+ 4 * (head + available - 1 > size ?
+ available - 1 - size + head : 0), &cmds[0]);
desc->status |= GUC_CTB_STATUS_UNDERFLOW;
goto corrupted;
}
*msg = ct_alloc_msg(len);
if (!*msg) {
- CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
- 4, &header,
- 4 * (head + available - 1 > size ?
- size - head : available - 1), &cmds[head],
- 4 * (head + available - 1 > size ?
- available - 1 - size + head : 0), &cmds[0]);
+ ct_err(ct, "No memory for message %*ph %*ph %*ph\n",
+ 4, &header,
+ 4 * (head + available - 1 > size ?
+ size - head : available - 1), &cmds[head],
+ 4 * (head + available - 1 > size ?
+ available - 1 - size + head : 0), &cmds[0]);
return available;
}
@@ -909,7 +919,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
(*msg)->msg[i] = cmds[head];
head = (head + 1) % size;
}
- CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
+ ct_dbg(ct, "received %*ph\n", 4 * len, (*msg)->msg);
/* update local copies */
ctb->head = head;
@@ -920,8 +930,8 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
return available - len;
corrupted:
- CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
- desc->head, desc->tail, desc->status);
+ ct_err(ct, "Corrupted descriptor on read head=%u tail=%u status=%#x\n",
+ desc->head, desc->tail, desc->status);
ctb->broken = true;
return -EPIPE;
}
@@ -944,18 +954,17 @@ static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *r
FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_NO_RESPONSE_RETRY &&
FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_RESPONSE_FAILURE);
- CT_DEBUG(ct, "response fence %u status %#x\n", fence, hxg[0]);
+ ct_dbg(ct, "response fence %u status %#x\n", fence, hxg[0]);
spin_lock_irqsave(&ct->requests.lock, flags);
list_for_each_entry(req, &ct->requests.pending, link) {
if (unlikely(fence != req->fence)) {
- CT_DEBUG(ct, "request %u awaits response\n",
- req->fence);
+ ct_dbg(ct, "request %u awaits response\n", req->fence);
continue;
}
if (unlikely(datalen > req->response_len)) {
- CT_ERROR(ct, "Response %u too long (datalen %u > %u)\n",
- req->fence, datalen, req->response_len);
+ ct_err(ct, "response %u too long (datalen %u > %u)\n",
+ req->fence, datalen, req->response_len);
datalen = min(datalen, req->response_len);
err = -EMSGSIZE;
}
@@ -967,12 +976,11 @@ static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *r
break;
}
if (!found) {
- CT_ERROR(ct, "Unsolicited response (fence %u)\n", fence);
- CT_ERROR(ct, "Could not find fence=%u, last_fence=%u\n", fence,
- ct->requests.last_fence);
+ ct_err(ct, "Unsolicited response (fence %u)\n", fence);
+ ct_err(ct, "Could not find fence=%u, last_fence=%u\n", fence,
+ ct->requests.last_fence);
list_for_each_entry(req, &ct->requests.pending, link)
- CT_ERROR(ct, "request %u awaits response\n",
- req->fence);
+ ct_err(ct, "request %u awaits response\n", req->fence);
err = -ENOKEY;
}
spin_unlock_irqrestore(&ct->requests.lock, flags);
@@ -998,7 +1006,7 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, hxg[0]);
len = hxg_len - GUC_HXG_MSG_MIN_LEN;
- CT_DEBUG(ct, "request %x %*ph\n", action, 4 * len, payload);
+ ct_dbg(ct, "request %x %*ph\n", action, 4 * len, payload);
switch (action) {
case INTEL_GUC_ACTION_DEFAULT:
@@ -1016,9 +1024,6 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
break;
case INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION:
ret = intel_guc_error_capture_process_msg(guc, payload, len);
- if (unlikely(ret))
- CT_ERROR(ct, "error capture notification failed %x %*ph\n",
- action, 4 * len, payload);
break;
case INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION:
ret = intel_guc_engine_failure_process_msg(guc, payload, len);
@@ -1028,11 +1033,11 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
ret = 0;
break;
case INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED:
- CT_ERROR(ct, "Received GuC crash dump notification!\n");
+ guc_err(guc, "notification: Crash dump!\n");
ret = 0;
break;
case INTEL_GUC_ACTION_NOTIFY_EXCEPTION:
- CT_ERROR(ct, "Received GuC exception notification!\n");
+ guc_err(guc, "notification: Exception!\n");
ret = 0;
break;
default:
@@ -1041,8 +1046,7 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
}
if (unlikely(ret)) {
- CT_ERROR(ct, "Failed to process request %04x (%pe)\n",
- action, ERR_PTR(ret));
+ ct_err(ct, "Failed to process request %04x (%pe)\n", action, ERR_PTR(ret));
return ret;
}
@@ -1070,8 +1074,8 @@ static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
err = ct_process_request(ct, request);
if (unlikely(err)) {
- CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
- ERR_PTR(err), 4 * request->size, request->msg);
+ ct_err(ct, "Failed to process message (%pe) %*ph\n",
+ ERR_PTR(err), 4 * request->size, request->msg);
ct_free_msg(request);
}
@@ -1149,8 +1153,8 @@ static int ct_handle_hxg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg)
if (unlikely(err)) {
failed:
- CT_ERROR(ct, "Failed to handle HXG message (%pe) %*ph\n",
- ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
+ ct_err(ct, "Failed to handle HXG message (%pe) %*ph\n",
+ ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
}
return err;
}
@@ -1166,8 +1170,8 @@ static void ct_handle_msg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg)
err = -EOPNOTSUPP;
if (unlikely(err)) {
- CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
- ERR_PTR(err), 4 * msg->size, msg->msg);
+ ct_err(ct, "Failed to handle message (%pe) %*ph\n",
+ ERR_PTR(err), 4 * msg->size, msg->msg);
ct_free_msg(msg);
}
}
@@ -1198,7 +1202,7 @@ static void ct_try_receive_message(struct intel_guc_ct *ct)
{
int ret;
- if (GEM_WARN_ON(!ct->enabled))
+ if (ct_WARN_ON(ct, !ct->enabled))
return;
ret = ct_receive(ct);
@@ -1220,7 +1224,7 @@ static void ct_receive_tasklet_func(struct tasklet_struct *t)
void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
{
if (unlikely(!ct->enabled)) {
- WARN(1, "Unexpected GuC event received while CT disabled!\n");
+ ct_warn(ct, "Unexpected event received while disabled!\n");
return;
}
--
2.37.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
(?)
@ 2022-11-22 17:54 ` Michal Wajdeczko
2022-11-23 1:25 ` John Harrison
-1 siblings, 1 reply; 51+ messages in thread
From: Michal Wajdeczko @ 2022-11-22 17:54 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Re-work the existing GuC CT printers and extend as required to match
> the new wrapping scheme.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++++-----------
> 1 file changed, 113 insertions(+), 109 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index 2b22065e87bf9..9d404fb377637 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -18,31 +18,49 @@ static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
> return container_of(ct, struct intel_guc, ct);
> }
>
> -static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
> -{
> - return guc_to_gt(ct_to_guc(ct));
> -}
> -
> static inline struct drm_i915_private *ct_to_i915(struct intel_guc_ct *ct)
> {
> - return ct_to_gt(ct)->i915;
> -}
> + struct intel_guc *guc = ct_to_guc(ct);
> + struct intel_gt *gt = guc_to_gt(guc);
>
> -static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
> -{
> - return &ct_to_i915(ct)->drm;
> + return gt->i915;
> }
>
> -#define CT_ERROR(_ct, _fmt, ...) \
> - drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
> +#define ct_err(_ct, _fmt, ...) \
> + guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
> +
> +#define ct_warn(_ct, _fmt, ...) \
> + guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
> +
> +#define ct_notice(_ct, _fmt, ...) \
> + guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
> +
> +#define ct_info(_ct, _fmt, ...) \
> + guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
> +
> #ifdef CONFIG_DRM_I915_DEBUG_GUC
> -#define CT_DEBUG(_ct, _fmt, ...) \
> - drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
> +#define ct_dbg(_ct, _fmt, ...) \
> + guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
> #else
> -#define CT_DEBUG(...) do { } while (0)
> +#define ct_dbg(...) do { } while (0)
> #endif
> -#define CT_PROBE_ERROR(_ct, _fmt, ...) \
> - i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
> +
> +#define ct_probe_error(_ct, _fmt, ...) \
> + do { \
> + if (i915_error_injected()) \
> + ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
> + else \
> + ct_err(_ct, _fmt, ##__VA_ARGS__); \
> + } while (0)
guc_probe_error ?
> +
> +#define ct_WARN_ON(_ct, _condition) \
> + ct_WARN(_ct, _condition, "%s", "ct_WARN_ON(" __stringify(_condition) ")")
> +
> +#define ct_WARN(_ct, _condition, _fmt, ...) \
> + guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
> +
> +#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
> + guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
>
> /**
> * DOC: CTB Blob
> @@ -170,7 +188,7 @@ static int ct_control_enable(struct intel_guc_ct *ct, bool enable)
> err = guc_action_control_ctb(ct_to_guc(ct), enable ?
> GUC_CTB_CONTROL_ENABLE : GUC_CTB_CONTROL_DISABLE);
> if (unlikely(err))
> - CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
> + ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
> str_enable_disable(enable), ERR_PTR(err));
btw, shouldn't we change all messages to start with lowercase ?
was:
"CT0: Failed to control/%s CTB (%pe)"
is:
"GT0: GuC CT Failed to control/%s CTB (%pe)"
unless we keep colon (as suggested by Tvrtko) as then:
"GT0: GuC CT: Failed to control/%s CTB (%pe)"
Michal
>
> return err;
> @@ -201,7 +219,7 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
> size);
> if (unlikely(err))
> failed:
> - CT_PROBE_ERROR(ct, "Failed to register %s buffer (%pe)\n",
> + ct_probe_error(ct, "Failed to register %s buffer (%pe)\n",
> send ? "SEND" : "RECV", ERR_PTR(err));
>
> return err;
> @@ -235,21 +253,21 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
> blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE + CTB_G2H_BUFFER_SIZE;
> err = intel_guc_allocate_and_map_vma(guc, blob_size, &ct->vma, &blob);
> if (unlikely(err)) {
> - CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data (%pe)\n",
> + ct_probe_error(ct, "Failed to allocate %u for CTB data (%pe)\n",
> blob_size, ERR_PTR(err));
> return err;
> }
>
> - CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
> + ct_dbg(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
>
> /* store pointers to desc and cmds for send ctb */
> desc = blob;
> cmds = blob + 2 * CTB_DESC_SIZE;
> cmds_size = CTB_H2G_BUFFER_SIZE;
> resv_space = 0;
> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
> - resv_space);
> + ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
> + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
> + resv_space);
>
> guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
>
> @@ -258,9 +276,9 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
> cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
> cmds_size = CTB_G2H_BUFFER_SIZE;
> resv_space = G2H_ROOM_BUFFER_SIZE;
> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
> - resv_space);
> + ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
> + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
> + resv_space);
>
> guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
>
> @@ -338,7 +356,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> return 0;
>
> err_out:
> - CT_PROBE_ERROR(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
> + ct_probe_error(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
> return err;
> }
>
> @@ -387,14 +405,12 @@ static int ct_write(struct intel_guc_ct *ct,
>
> #ifdef CONFIG_DRM_I915_DEBUG_GUC
> if (unlikely(tail != READ_ONCE(desc->tail))) {
> - CT_ERROR(ct, "Tail was modified %u != %u\n",
> - desc->tail, tail);
> + ct_err(ct, "Tail was modified %u != %u\n", desc->tail, tail);
> desc->status |= GUC_CTB_STATUS_MISMATCH;
> goto corrupted;
> }
> if (unlikely(READ_ONCE(desc->head) >= size)) {
> - CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
> - desc->head, size);
> + ct_err(ct, "Invalid head offset %u >= %u)\n", desc->head, size);
> desc->status |= GUC_CTB_STATUS_OVERFLOW;
> goto corrupted;
> }
> @@ -415,8 +431,8 @@ static int ct_write(struct intel_guc_ct *ct,
> FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |
> GUC_HXG_EVENT_MSG_0_DATA0, action[0]);
>
> - CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
> - tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
> + ct_dbg(ct, "writing (tail %u) %*ph %*ph %*ph\n",
> + tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>
> cmds[tail] = header;
> tail = (tail + 1) % size;
> @@ -447,8 +463,8 @@ static int ct_write(struct intel_guc_ct *ct,
> return 0;
>
> corrupted:
> - CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
> - desc->head, desc->tail, desc->status);
> + ct_err(ct, "Corrupted descriptor on write head=%u tail=%u status=%#x\n",
> + desc->head, desc->tail, desc->status);
> ctb->broken = true;
> return -EPIPE;
> }
> @@ -507,17 +523,14 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
> struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
> struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
>
> - CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
> - ktime_ms_delta(ktime_get(), ct->stall_time),
> - send->status, recv->status);
> - CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
> - atomic_read(&ct->ctbs.send.space) * 4);
> - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
> - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
> - CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
> - atomic_read(&ct->ctbs.recv.space) * 4);
> - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
> - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
> + ct_err(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
> + ktime_ms_delta(ktime_get(), ct->stall_time), send->status, recv->status);
> + ct_err(ct, "H2G Space: %u (Bytes)\n", atomic_read(&ct->ctbs.send.space) * 4);
> + ct_err(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
> + ct_err(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
> + ct_err(ct, "G2H Space: %u (Bytes)\n", atomic_read(&ct->ctbs.recv.space) * 4);
> + ct_err(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
> + ct_err(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
>
> ct->ctbs.send.broken = true;
> }
> @@ -563,8 +576,7 @@ static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
>
> head = READ_ONCE(desc->head);
> if (unlikely(head > ctb->size)) {
> - CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
> - head, ctb->size);
> + ct_err(ct, "Invalid head offset %u >= %u)\n", head, ctb->size);
> desc->status |= GUC_CTB_STATUS_OVERFLOW;
> ctb->broken = true;
> return false;
> @@ -715,17 +727,17 @@ static int ct_send(struct intel_guc_ct *ct,
> /* wait_for_ct_request_update returns -ENODEV on reset/suspend in progress.
> * In this case, output is debug rather than error info
> */
> - CT_DEBUG(ct, "Request %#x (fence %u) cancelled as CTB is disabled\n",
> - action[0], request.fence);
> + ct_dbg(ct, "Request %#x (fence %u) cancelled as CTB is disabled\n",
> + action[0], request.fence);
> else
> - CT_ERROR(ct, "No response for request %#x (fence %u)\n",
> - action[0], request.fence);
> + ct_err(ct, "No response for request %#x (fence %u)\n",
> + action[0], request.fence);
> goto unlink;
> }
>
> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, *status) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
> - CT_DEBUG(ct, "retrying request %#x (%u)\n", *action,
> - FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
> + ct_dbg(ct, "retrying request %#x (%u)\n", *action,
> + FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
> send_again = true;
> goto unlink;
> }
> @@ -737,12 +749,12 @@ static int ct_send(struct intel_guc_ct *ct,
>
> if (response_buf) {
> /* There shall be no data in the status */
> - WARN_ON(FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, request.status));
> + ct_WARN_ON(ct, FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, request.status));
> /* Return actual response len */
> err = request.response_len;
> } else {
> /* There shall be no response payload */
> - WARN_ON(request.response_len);
> + ct_WARN_ON(ct, request.response_len);
> /* Return data decoded from the status dword */
> err = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, *status);
> }
> @@ -771,7 +783,7 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
> struct intel_guc *guc = ct_to_guc(ct);
> struct intel_uc *uc = container_of(guc, struct intel_uc, guc);
>
> - WARN(!uc->reset_in_progress, "Unexpected send: action=%#x\n", *action);
> + ct_WARN(ct, !uc->reset_in_progress, "Unexpected send: action=%#x\n", *action);
> return -ENODEV;
> }
>
> @@ -784,11 +796,11 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
> ret = ct_send(ct, action, len, response_buf, response_buf_size, &status);
> if (unlikely(ret < 0)) {
> if (ret != -ENODEV)
> - CT_ERROR(ct, "Sending action %#x failed (%pe) status=%#X\n",
> - action[0], ERR_PTR(ret), status);
> + ct_err(ct, "sending action %#x failed (%pe) status=%#X\n",
> + action[0], ERR_PTR(ret), status);
> } else if (unlikely(ret)) {
> - CT_DEBUG(ct, "send action %#x returned %d (%#x)\n",
> - action[0], ret, ret);
> + ct_dbg(ct, "send action %#x returned %d (%#x)\n",
> + action[0], ret, ret);
> }
>
> return ret;
> @@ -838,7 +850,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> * contexts/engines being reset. But should never happen as
> * no contexts should be active when CLIENT_RESET is sent.
> */
> - CT_ERROR(ct, "Unexpected G2H after GuC has stopped!\n");
> + ct_err(ct, "Unexpected G2H after GuC has stopped!\n");
> status &= ~GUC_CTB_STATUS_UNUSED;
> }
>
> @@ -850,15 +862,13 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>
> #ifdef CONFIG_DRM_I915_DEBUG_GUC
> if (unlikely(head != READ_ONCE(desc->head))) {
> - CT_ERROR(ct, "Head was modified %u != %u\n",
> - desc->head, head);
> + ct_err(ct, "Head was modified %u != %u\n", desc->head, head);
> desc->status |= GUC_CTB_STATUS_MISMATCH;
> goto corrupted;
> }
> #endif
> if (unlikely(tail >= size)) {
> - CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
> - tail, size);
> + ct_err(ct, "Invalid tail offset %u >= %u)\n", tail, size);
> desc->status |= GUC_CTB_STATUS_OVERFLOW;
> goto corrupted;
> }
> @@ -873,7 +883,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> /* beware of buffer wrap case */
> if (unlikely(available < 0))
> available += size;
> - CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
> + ct_dbg(ct, "read available %d (%u:%u:%u)\n", available, head, tail, size);
> GEM_BUG_ON(available < 0);
>
> header = cmds[head];
> @@ -882,24 +892,24 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> /* message len with header */
> len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, header) + GUC_CTB_MSG_MIN_LEN;
> if (unlikely(len > (u32)available)) {
> - CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
> - 4, &header,
> - 4 * (head + available - 1 > size ?
> - size - head : available - 1), &cmds[head],
> - 4 * (head + available - 1 > size ?
> - available - 1 - size + head : 0), &cmds[0]);
> + ct_err(ct, "Incomplete message %*ph %*ph %*ph\n",
> + 4, &header,
> + 4 * (head + available - 1 > size ?
> + size - head : available - 1), &cmds[head],
> + 4 * (head + available - 1 > size ?
> + available - 1 - size + head : 0), &cmds[0]);
> desc->status |= GUC_CTB_STATUS_UNDERFLOW;
> goto corrupted;
> }
>
> *msg = ct_alloc_msg(len);
> if (!*msg) {
> - CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
> - 4, &header,
> - 4 * (head + available - 1 > size ?
> - size - head : available - 1), &cmds[head],
> - 4 * (head + available - 1 > size ?
> - available - 1 - size + head : 0), &cmds[0]);
> + ct_err(ct, "No memory for message %*ph %*ph %*ph\n",
> + 4, &header,
> + 4 * (head + available - 1 > size ?
> + size - head : available - 1), &cmds[head],
> + 4 * (head + available - 1 > size ?
> + available - 1 - size + head : 0), &cmds[0]);
> return available;
> }
>
> @@ -909,7 +919,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> (*msg)->msg[i] = cmds[head];
> head = (head + 1) % size;
> }
> - CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
> + ct_dbg(ct, "received %*ph\n", 4 * len, (*msg)->msg);
>
> /* update local copies */
> ctb->head = head;
> @@ -920,8 +930,8 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> return available - len;
>
> corrupted:
> - CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
> - desc->head, desc->tail, desc->status);
> + ct_err(ct, "Corrupted descriptor on read head=%u tail=%u status=%#x\n",
> + desc->head, desc->tail, desc->status);
> ctb->broken = true;
> return -EPIPE;
> }
> @@ -944,18 +954,17 @@ static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *r
> FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_NO_RESPONSE_RETRY &&
> FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_RESPONSE_FAILURE);
>
> - CT_DEBUG(ct, "response fence %u status %#x\n", fence, hxg[0]);
> + ct_dbg(ct, "response fence %u status %#x\n", fence, hxg[0]);
>
> spin_lock_irqsave(&ct->requests.lock, flags);
> list_for_each_entry(req, &ct->requests.pending, link) {
> if (unlikely(fence != req->fence)) {
> - CT_DEBUG(ct, "request %u awaits response\n",
> - req->fence);
> + ct_dbg(ct, "request %u awaits response\n", req->fence);
> continue;
> }
> if (unlikely(datalen > req->response_len)) {
> - CT_ERROR(ct, "Response %u too long (datalen %u > %u)\n",
> - req->fence, datalen, req->response_len);
> + ct_err(ct, "response %u too long (datalen %u > %u)\n",
> + req->fence, datalen, req->response_len);
> datalen = min(datalen, req->response_len);
> err = -EMSGSIZE;
> }
> @@ -967,12 +976,11 @@ static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *r
> break;
> }
> if (!found) {
> - CT_ERROR(ct, "Unsolicited response (fence %u)\n", fence);
> - CT_ERROR(ct, "Could not find fence=%u, last_fence=%u\n", fence,
> - ct->requests.last_fence);
> + ct_err(ct, "Unsolicited response (fence %u)\n", fence);
> + ct_err(ct, "Could not find fence=%u, last_fence=%u\n", fence,
> + ct->requests.last_fence);
> list_for_each_entry(req, &ct->requests.pending, link)
> - CT_ERROR(ct, "request %u awaits response\n",
> - req->fence);
> + ct_err(ct, "request %u awaits response\n", req->fence);
> err = -ENOKEY;
> }
> spin_unlock_irqrestore(&ct->requests.lock, flags);
> @@ -998,7 +1006,7 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
> action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, hxg[0]);
> len = hxg_len - GUC_HXG_MSG_MIN_LEN;
>
> - CT_DEBUG(ct, "request %x %*ph\n", action, 4 * len, payload);
> + ct_dbg(ct, "request %x %*ph\n", action, 4 * len, payload);
>
> switch (action) {
> case INTEL_GUC_ACTION_DEFAULT:
> @@ -1016,9 +1024,6 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
> break;
> case INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION:
> ret = intel_guc_error_capture_process_msg(guc, payload, len);
> - if (unlikely(ret))
> - CT_ERROR(ct, "error capture notification failed %x %*ph\n",
> - action, 4 * len, payload);
> break;
> case INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION:
> ret = intel_guc_engine_failure_process_msg(guc, payload, len);
> @@ -1028,11 +1033,11 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
> ret = 0;
> break;
> case INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED:
> - CT_ERROR(ct, "Received GuC crash dump notification!\n");
> + guc_err(guc, "notification: Crash dump!\n");
> ret = 0;
> break;
> case INTEL_GUC_ACTION_NOTIFY_EXCEPTION:
> - CT_ERROR(ct, "Received GuC exception notification!\n");
> + guc_err(guc, "notification: Exception!\n");
> ret = 0;
> break;
> default:
> @@ -1041,8 +1046,7 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
> }
>
> if (unlikely(ret)) {
> - CT_ERROR(ct, "Failed to process request %04x (%pe)\n",
> - action, ERR_PTR(ret));
> + ct_err(ct, "Failed to process request %04x (%pe)\n", action, ERR_PTR(ret));
> return ret;
> }
>
> @@ -1070,8 +1074,8 @@ static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
>
> err = ct_process_request(ct, request);
> if (unlikely(err)) {
> - CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
> - ERR_PTR(err), 4 * request->size, request->msg);
> + ct_err(ct, "Failed to process message (%pe) %*ph\n",
> + ERR_PTR(err), 4 * request->size, request->msg);
> ct_free_msg(request);
> }
>
> @@ -1149,8 +1153,8 @@ static int ct_handle_hxg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg)
>
> if (unlikely(err)) {
> failed:
> - CT_ERROR(ct, "Failed to handle HXG message (%pe) %*ph\n",
> - ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
> + ct_err(ct, "Failed to handle HXG message (%pe) %*ph\n",
> + ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
> }
> return err;
> }
> @@ -1166,8 +1170,8 @@ static void ct_handle_msg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg)
> err = -EOPNOTSUPP;
>
> if (unlikely(err)) {
> - CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
> - ERR_PTR(err), 4 * msg->size, msg->msg);
> + ct_err(ct, "Failed to handle message (%pe) %*ph\n",
> + ERR_PTR(err), 4 * msg->size, msg->msg);
> ct_free_msg(msg);
> }
> }
> @@ -1198,7 +1202,7 @@ static void ct_try_receive_message(struct intel_guc_ct *ct)
> {
> int ret;
>
> - if (GEM_WARN_ON(!ct->enabled))
> + if (ct_WARN_ON(ct, !ct->enabled))
> return;
>
> ret = ct_receive(ct);
> @@ -1220,7 +1224,7 @@ static void ct_receive_tasklet_func(struct tasklet_struct *t)
> void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
> {
> if (unlikely(!ct->enabled)) {
> - WARN(1, "Unexpected GuC event received while CT disabled!\n");
> + ct_warn(ct, "Unexpected event received while disabled!\n");
> return;
> }
>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2022-11-22 17:54 ` Michal Wajdeczko
@ 2022-11-23 1:25 ` John Harrison
2022-11-23 20:45 ` Michal Wajdeczko
0 siblings, 1 reply; 51+ messages in thread
From: John Harrison @ 2022-11-23 1:25 UTC (permalink / raw)
To: Michal Wajdeczko, Intel-GFX; +Cc: DRI-Devel
On 11/22/2022 09:54, Michal Wajdeczko wrote:
> On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> Re-work the existing GuC CT printers and extend as required to match
>> the new wrapping scheme.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++++-----------
>> 1 file changed, 113 insertions(+), 109 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> index 2b22065e87bf9..9d404fb377637 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> @@ -18,31 +18,49 @@ static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
>> return container_of(ct, struct intel_guc, ct);
>> }
>>
>> -static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
>> -{
>> - return guc_to_gt(ct_to_guc(ct));
>> -}
>> -
>> static inline struct drm_i915_private *ct_to_i915(struct intel_guc_ct *ct)
>> {
>> - return ct_to_gt(ct)->i915;
>> -}
>> + struct intel_guc *guc = ct_to_guc(ct);
>> + struct intel_gt *gt = guc_to_gt(guc);
>>
>> -static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
>> -{
>> - return &ct_to_i915(ct)->drm;
>> + return gt->i915;
>> }
>>
>> -#define CT_ERROR(_ct, _fmt, ...) \
>> - drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>> +#define ct_err(_ct, _fmt, ...) \
>> + guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>> +
>> +#define ct_warn(_ct, _fmt, ...) \
>> + guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>> +
>> +#define ct_notice(_ct, _fmt, ...) \
>> + guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>> +
>> +#define ct_info(_ct, _fmt, ...) \
>> + guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>> +
>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>> -#define CT_DEBUG(_ct, _fmt, ...) \
>> - drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>> +#define ct_dbg(_ct, _fmt, ...) \
>> + guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>> #else
>> -#define CT_DEBUG(...) do { } while (0)
>> +#define ct_dbg(...) do { } while (0)
>> #endif
>> -#define CT_PROBE_ERROR(_ct, _fmt, ...) \
>> - i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
>> +
>> +#define ct_probe_error(_ct, _fmt, ...) \
>> + do { \
>> + if (i915_error_injected()) \
>> + ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
>> + else \
>> + ct_err(_ct, _fmt, ##__VA_ARGS__); \
>> + } while (0)
> guc_probe_error ?
>
>> +
>> +#define ct_WARN_ON(_ct, _condition) \
>> + ct_WARN(_ct, _condition, "%s", "ct_WARN_ON(" __stringify(_condition) ")")
>> +
>> +#define ct_WARN(_ct, _condition, _fmt, ...) \
>> + guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
>> +
>> +#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
>> + guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
>>
>> /**
>> * DOC: CTB Blob
>> @@ -170,7 +188,7 @@ static int ct_control_enable(struct intel_guc_ct *ct, bool enable)
>> err = guc_action_control_ctb(ct_to_guc(ct), enable ?
>> GUC_CTB_CONTROL_ENABLE : GUC_CTB_CONTROL_DISABLE);
>> if (unlikely(err))
>> - CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
>> + ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
>> str_enable_disable(enable), ERR_PTR(err));
> btw, shouldn't we change all messages to start with lowercase ?
>
> was:
> "CT0: Failed to control/%s CTB (%pe)"
> is:
> "GT0: GuC CT Failed to control/%s CTB (%pe)"
>
> unless we keep colon (as suggested by Tvrtko) as then:
>
> "GT0: GuC CT: Failed to control/%s CTB (%pe)"
Blanket added the colon makes it messy when a string actually wants to
start with the prefix. The rule I've been using is lower case word when
the prefix was part of the string, upper case word when the prefix is
just being added as a prefix. I originally just had the prefix as raw
with no trailing space, so the individual print could decide to add a
colon, a space, or whatever as appropriate. But that just makes for
messy code with some files having every string look like ": Stuff
happened" and other files have every string look like " failed to ...".
The current version seems to be the most readable from the point of view
of writing the code and of reading the dmesg results.
And to be clear, the 'CT0' you have in your 'was' example only exists in
the internal tree. It never made it to upstream. It is also just plain
wrong. Each GT has two CTs - send and receive. So having 'CT1' meaning
some random CT on GT1 (as opposed to the read channel on GT0, for
example) was very confusing.
John.
>
> Michal
>
>>
>> return err;
>> @@ -201,7 +219,7 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
>> size);
>> if (unlikely(err))
>> failed:
>> - CT_PROBE_ERROR(ct, "Failed to register %s buffer (%pe)\n",
>> + ct_probe_error(ct, "Failed to register %s buffer (%pe)\n",
>> send ? "SEND" : "RECV", ERR_PTR(err));
>>
>> return err;
>> @@ -235,21 +253,21 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>> blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE + CTB_G2H_BUFFER_SIZE;
>> err = intel_guc_allocate_and_map_vma(guc, blob_size, &ct->vma, &blob);
>> if (unlikely(err)) {
>> - CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data (%pe)\n",
>> + ct_probe_error(ct, "Failed to allocate %u for CTB data (%pe)\n",
>> blob_size, ERR_PTR(err));
>> return err;
>> }
>>
>> - CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
>> + ct_dbg(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
>>
>> /* store pointers to desc and cmds for send ctb */
>> desc = blob;
>> cmds = blob + 2 * CTB_DESC_SIZE;
>> cmds_size = CTB_H2G_BUFFER_SIZE;
>> resv_space = 0;
>> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
>> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>> - resv_space);
>> + ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
>> + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>> + resv_space);
>>
>> guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
>>
>> @@ -258,9 +276,9 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>> cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
>> cmds_size = CTB_G2H_BUFFER_SIZE;
>> resv_space = G2H_ROOM_BUFFER_SIZE;
>> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
>> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>> - resv_space);
>> + ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
>> + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>> + resv_space);
>>
>> guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space);
>>
>> @@ -338,7 +356,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>> return 0;
>>
>> err_out:
>> - CT_PROBE_ERROR(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
>> + ct_probe_error(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
>> return err;
>> }
>>
>> @@ -387,14 +405,12 @@ static int ct_write(struct intel_guc_ct *ct,
>>
>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>> if (unlikely(tail != READ_ONCE(desc->tail))) {
>> - CT_ERROR(ct, "Tail was modified %u != %u\n",
>> - desc->tail, tail);
>> + ct_err(ct, "Tail was modified %u != %u\n", desc->tail, tail);
>> desc->status |= GUC_CTB_STATUS_MISMATCH;
>> goto corrupted;
>> }
>> if (unlikely(READ_ONCE(desc->head) >= size)) {
>> - CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
>> - desc->head, size);
>> + ct_err(ct, "Invalid head offset %u >= %u)\n", desc->head, size);
>> desc->status |= GUC_CTB_STATUS_OVERFLOW;
>> goto corrupted;
>> }
>> @@ -415,8 +431,8 @@ static int ct_write(struct intel_guc_ct *ct,
>> FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |
>> GUC_HXG_EVENT_MSG_0_DATA0, action[0]);
>>
>> - CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
>> - tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>> + ct_dbg(ct, "writing (tail %u) %*ph %*ph %*ph\n",
>> + tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>>
>> cmds[tail] = header;
>> tail = (tail + 1) % size;
>> @@ -447,8 +463,8 @@ static int ct_write(struct intel_guc_ct *ct,
>> return 0;
>>
>> corrupted:
>> - CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>> - desc->head, desc->tail, desc->status);
>> + ct_err(ct, "Corrupted descriptor on write head=%u tail=%u status=%#x\n",
>> + desc->head, desc->tail, desc->status);
>> ctb->broken = true;
>> return -EPIPE;
>> }
>> @@ -507,17 +523,14 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
>> struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
>> struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
>>
>> - CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
>> - ktime_ms_delta(ktime_get(), ct->stall_time),
>> - send->status, recv->status);
>> - CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
>> - atomic_read(&ct->ctbs.send.space) * 4);
>> - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
>> - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
>> - CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
>> - atomic_read(&ct->ctbs.recv.space) * 4);
>> - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
>> - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
>> + ct_err(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n",
>> + ktime_ms_delta(ktime_get(), ct->stall_time), send->status, recv->status);
>> + ct_err(ct, "H2G Space: %u (Bytes)\n", atomic_read(&ct->ctbs.send.space) * 4);
>> + ct_err(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
>> + ct_err(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
>> + ct_err(ct, "G2H Space: %u (Bytes)\n", atomic_read(&ct->ctbs.recv.space) * 4);
>> + ct_err(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
>> + ct_err(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
>>
>> ct->ctbs.send.broken = true;
>> }
>> @@ -563,8 +576,7 @@ static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
>>
>> head = READ_ONCE(desc->head);
>> if (unlikely(head > ctb->size)) {
>> - CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
>> - head, ctb->size);
>> + ct_err(ct, "Invalid head offset %u >= %u)\n", head, ctb->size);
>> desc->status |= GUC_CTB_STATUS_OVERFLOW;
>> ctb->broken = true;
>> return false;
>> @@ -715,17 +727,17 @@ static int ct_send(struct intel_guc_ct *ct,
>> /* wait_for_ct_request_update returns -ENODEV on reset/suspend in progress.
>> * In this case, output is debug rather than error info
>> */
>> - CT_DEBUG(ct, "Request %#x (fence %u) cancelled as CTB is disabled\n",
>> - action[0], request.fence);
>> + ct_dbg(ct, "Request %#x (fence %u) cancelled as CTB is disabled\n",
>> + action[0], request.fence);
>> else
>> - CT_ERROR(ct, "No response for request %#x (fence %u)\n",
>> - action[0], request.fence);
>> + ct_err(ct, "No response for request %#x (fence %u)\n",
>> + action[0], request.fence);
>> goto unlink;
>> }
>>
>> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, *status) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
>> - CT_DEBUG(ct, "retrying request %#x (%u)\n", *action,
>> - FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
>> + ct_dbg(ct, "retrying request %#x (%u)\n", *action,
>> + FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
>> send_again = true;
>> goto unlink;
>> }
>> @@ -737,12 +749,12 @@ static int ct_send(struct intel_guc_ct *ct,
>>
>> if (response_buf) {
>> /* There shall be no data in the status */
>> - WARN_ON(FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, request.status));
>> + ct_WARN_ON(ct, FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, request.status));
>> /* Return actual response len */
>> err = request.response_len;
>> } else {
>> /* There shall be no response payload */
>> - WARN_ON(request.response_len);
>> + ct_WARN_ON(ct, request.response_len);
>> /* Return data decoded from the status dword */
>> err = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, *status);
>> }
>> @@ -771,7 +783,7 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
>> struct intel_guc *guc = ct_to_guc(ct);
>> struct intel_uc *uc = container_of(guc, struct intel_uc, guc);
>>
>> - WARN(!uc->reset_in_progress, "Unexpected send: action=%#x\n", *action);
>> + ct_WARN(ct, !uc->reset_in_progress, "Unexpected send: action=%#x\n", *action);
>> return -ENODEV;
>> }
>>
>> @@ -784,11 +796,11 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
>> ret = ct_send(ct, action, len, response_buf, response_buf_size, &status);
>> if (unlikely(ret < 0)) {
>> if (ret != -ENODEV)
>> - CT_ERROR(ct, "Sending action %#x failed (%pe) status=%#X\n",
>> - action[0], ERR_PTR(ret), status);
>> + ct_err(ct, "sending action %#x failed (%pe) status=%#X\n",
>> + action[0], ERR_PTR(ret), status);
>> } else if (unlikely(ret)) {
>> - CT_DEBUG(ct, "send action %#x returned %d (%#x)\n",
>> - action[0], ret, ret);
>> + ct_dbg(ct, "send action %#x returned %d (%#x)\n",
>> + action[0], ret, ret);
>> }
>>
>> return ret;
>> @@ -838,7 +850,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>> * contexts/engines being reset. But should never happen as
>> * no contexts should be active when CLIENT_RESET is sent.
>> */
>> - CT_ERROR(ct, "Unexpected G2H after GuC has stopped!\n");
>> + ct_err(ct, "Unexpected G2H after GuC has stopped!\n");
>> status &= ~GUC_CTB_STATUS_UNUSED;
>> }
>>
>> @@ -850,15 +862,13 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>>
>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>> if (unlikely(head != READ_ONCE(desc->head))) {
>> - CT_ERROR(ct, "Head was modified %u != %u\n",
>> - desc->head, head);
>> + ct_err(ct, "Head was modified %u != %u\n", desc->head, head);
>> desc->status |= GUC_CTB_STATUS_MISMATCH;
>> goto corrupted;
>> }
>> #endif
>> if (unlikely(tail >= size)) {
>> - CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
>> - tail, size);
>> + ct_err(ct, "Invalid tail offset %u >= %u)\n", tail, size);
>> desc->status |= GUC_CTB_STATUS_OVERFLOW;
>> goto corrupted;
>> }
>> @@ -873,7 +883,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>> /* beware of buffer wrap case */
>> if (unlikely(available < 0))
>> available += size;
>> - CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
>> + ct_dbg(ct, "read available %d (%u:%u:%u)\n", available, head, tail, size);
>> GEM_BUG_ON(available < 0);
>>
>> header = cmds[head];
>> @@ -882,24 +892,24 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>> /* message len with header */
>> len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, header) + GUC_CTB_MSG_MIN_LEN;
>> if (unlikely(len > (u32)available)) {
>> - CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
>> - 4, &header,
>> - 4 * (head + available - 1 > size ?
>> - size - head : available - 1), &cmds[head],
>> - 4 * (head + available - 1 > size ?
>> - available - 1 - size + head : 0), &cmds[0]);
>> + ct_err(ct, "Incomplete message %*ph %*ph %*ph\n",
>> + 4, &header,
>> + 4 * (head + available - 1 > size ?
>> + size - head : available - 1), &cmds[head],
>> + 4 * (head + available - 1 > size ?
>> + available - 1 - size + head : 0), &cmds[0]);
>> desc->status |= GUC_CTB_STATUS_UNDERFLOW;
>> goto corrupted;
>> }
>>
>> *msg = ct_alloc_msg(len);
>> if (!*msg) {
>> - CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
>> - 4, &header,
>> - 4 * (head + available - 1 > size ?
>> - size - head : available - 1), &cmds[head],
>> - 4 * (head + available - 1 > size ?
>> - available - 1 - size + head : 0), &cmds[0]);
>> + ct_err(ct, "No memory for message %*ph %*ph %*ph\n",
>> + 4, &header,
>> + 4 * (head + available - 1 > size ?
>> + size - head : available - 1), &cmds[head],
>> + 4 * (head + available - 1 > size ?
>> + available - 1 - size + head : 0), &cmds[0]);
>> return available;
>> }
>>
>> @@ -909,7 +919,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>> (*msg)->msg[i] = cmds[head];
>> head = (head + 1) % size;
>> }
>> - CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
>> + ct_dbg(ct, "received %*ph\n", 4 * len, (*msg)->msg);
>>
>> /* update local copies */
>> ctb->head = head;
>> @@ -920,8 +930,8 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>> return available - len;
>>
>> corrupted:
>> - CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>> - desc->head, desc->tail, desc->status);
>> + ct_err(ct, "Corrupted descriptor on read head=%u tail=%u status=%#x\n",
>> + desc->head, desc->tail, desc->status);
>> ctb->broken = true;
>> return -EPIPE;
>> }
>> @@ -944,18 +954,17 @@ static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *r
>> FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_NO_RESPONSE_RETRY &&
>> FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_RESPONSE_FAILURE);
>>
>> - CT_DEBUG(ct, "response fence %u status %#x\n", fence, hxg[0]);
>> + ct_dbg(ct, "response fence %u status %#x\n", fence, hxg[0]);
>>
>> spin_lock_irqsave(&ct->requests.lock, flags);
>> list_for_each_entry(req, &ct->requests.pending, link) {
>> if (unlikely(fence != req->fence)) {
>> - CT_DEBUG(ct, "request %u awaits response\n",
>> - req->fence);
>> + ct_dbg(ct, "request %u awaits response\n", req->fence);
>> continue;
>> }
>> if (unlikely(datalen > req->response_len)) {
>> - CT_ERROR(ct, "Response %u too long (datalen %u > %u)\n",
>> - req->fence, datalen, req->response_len);
>> + ct_err(ct, "response %u too long (datalen %u > %u)\n",
>> + req->fence, datalen, req->response_len);
>> datalen = min(datalen, req->response_len);
>> err = -EMSGSIZE;
>> }
>> @@ -967,12 +976,11 @@ static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *r
>> break;
>> }
>> if (!found) {
>> - CT_ERROR(ct, "Unsolicited response (fence %u)\n", fence);
>> - CT_ERROR(ct, "Could not find fence=%u, last_fence=%u\n", fence,
>> - ct->requests.last_fence);
>> + ct_err(ct, "Unsolicited response (fence %u)\n", fence);
>> + ct_err(ct, "Could not find fence=%u, last_fence=%u\n", fence,
>> + ct->requests.last_fence);
>> list_for_each_entry(req, &ct->requests.pending, link)
>> - CT_ERROR(ct, "request %u awaits response\n",
>> - req->fence);
>> + ct_err(ct, "request %u awaits response\n", req->fence);
>> err = -ENOKEY;
>> }
>> spin_unlock_irqrestore(&ct->requests.lock, flags);
>> @@ -998,7 +1006,7 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
>> action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, hxg[0]);
>> len = hxg_len - GUC_HXG_MSG_MIN_LEN;
>>
>> - CT_DEBUG(ct, "request %x %*ph\n", action, 4 * len, payload);
>> + ct_dbg(ct, "request %x %*ph\n", action, 4 * len, payload);
>>
>> switch (action) {
>> case INTEL_GUC_ACTION_DEFAULT:
>> @@ -1016,9 +1024,6 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
>> break;
>> case INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION:
>> ret = intel_guc_error_capture_process_msg(guc, payload, len);
>> - if (unlikely(ret))
>> - CT_ERROR(ct, "error capture notification failed %x %*ph\n",
>> - action, 4 * len, payload);
>> break;
>> case INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION:
>> ret = intel_guc_engine_failure_process_msg(guc, payload, len);
>> @@ -1028,11 +1033,11 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
>> ret = 0;
>> break;
>> case INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED:
>> - CT_ERROR(ct, "Received GuC crash dump notification!\n");
>> + guc_err(guc, "notification: Crash dump!\n");
>> ret = 0;
>> break;
>> case INTEL_GUC_ACTION_NOTIFY_EXCEPTION:
>> - CT_ERROR(ct, "Received GuC exception notification!\n");
>> + guc_err(guc, "notification: Exception!\n");
>> ret = 0;
>> break;
>> default:
>> @@ -1041,8 +1046,7 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
>> }
>>
>> if (unlikely(ret)) {
>> - CT_ERROR(ct, "Failed to process request %04x (%pe)\n",
>> - action, ERR_PTR(ret));
>> + ct_err(ct, "Failed to process request %04x (%pe)\n", action, ERR_PTR(ret));
>> return ret;
>> }
>>
>> @@ -1070,8 +1074,8 @@ static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
>>
>> err = ct_process_request(ct, request);
>> if (unlikely(err)) {
>> - CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
>> - ERR_PTR(err), 4 * request->size, request->msg);
>> + ct_err(ct, "Failed to process message (%pe) %*ph\n",
>> + ERR_PTR(err), 4 * request->size, request->msg);
>> ct_free_msg(request);
>> }
>>
>> @@ -1149,8 +1153,8 @@ static int ct_handle_hxg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg)
>>
>> if (unlikely(err)) {
>> failed:
>> - CT_ERROR(ct, "Failed to handle HXG message (%pe) %*ph\n",
>> - ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
>> + ct_err(ct, "Failed to handle HXG message (%pe) %*ph\n",
>> + ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
>> }
>> return err;
>> }
>> @@ -1166,8 +1170,8 @@ static void ct_handle_msg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg)
>> err = -EOPNOTSUPP;
>>
>> if (unlikely(err)) {
>> - CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
>> - ERR_PTR(err), 4 * msg->size, msg->msg);
>> + ct_err(ct, "Failed to handle message (%pe) %*ph\n",
>> + ERR_PTR(err), 4 * msg->size, msg->msg);
>> ct_free_msg(msg);
>> }
>> }
>> @@ -1198,7 +1202,7 @@ static void ct_try_receive_message(struct intel_guc_ct *ct)
>> {
>> int ret;
>>
>> - if (GEM_WARN_ON(!ct->enabled))
>> + if (ct_WARN_ON(ct, !ct->enabled))
>> return;
>>
>> ret = ct_receive(ct);
>> @@ -1220,7 +1224,7 @@ static void ct_receive_tasklet_func(struct tasklet_struct *t)
>> void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
>> {
>> if (unlikely(!ct->enabled)) {
>> - WARN(1, "Unexpected GuC event received while CT disabled!\n");
>> + ct_warn(ct, "Unexpected event received while disabled!\n");
>> return;
>> }
>>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2022-11-23 1:25 ` John Harrison
@ 2022-11-23 20:45 ` Michal Wajdeczko
2022-12-01 0:41 ` John Harrison
0 siblings, 1 reply; 51+ messages in thread
From: Michal Wajdeczko @ 2022-11-23 20:45 UTC (permalink / raw)
To: John Harrison, Intel-GFX; +Cc: DRI-Devel
On 23.11.2022 02:25, John Harrison wrote:
> On 11/22/2022 09:54, Michal Wajdeczko wrote:
>> On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>
>>> Re-work the existing GuC CT printers and extend as required to match
>>> the new wrapping scheme.
>>>
>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++++-----------
>>> 1 file changed, 113 insertions(+), 109 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> index 2b22065e87bf9..9d404fb377637 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> @@ -18,31 +18,49 @@ static inline struct intel_guc *ct_to_guc(struct
>>> intel_guc_ct *ct)
>>> return container_of(ct, struct intel_guc, ct);
>>> }
>>> -static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
>>> -{
>>> - return guc_to_gt(ct_to_guc(ct));
>>> -}
>>> -
>>> static inline struct drm_i915_private *ct_to_i915(struct
>>> intel_guc_ct *ct)
>>> {
>>> - return ct_to_gt(ct)->i915;
>>> -}
>>> + struct intel_guc *guc = ct_to_guc(ct);
>>> + struct intel_gt *gt = guc_to_gt(guc);
>>> -static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
>>> -{
>>> - return &ct_to_i915(ct)->drm;
>>> + return gt->i915;
>>> }
>>> -#define CT_ERROR(_ct, _fmt, ...) \
>>> - drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>> +#define ct_err(_ct, _fmt, ...) \
>>> + guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_warn(_ct, _fmt, ...) \
>>> + guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_notice(_ct, _fmt, ...) \
>>> + guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_info(_ct, _fmt, ...) \
>>> + guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>> -#define CT_DEBUG(_ct, _fmt, ...) \
>>> - drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>> +#define ct_dbg(_ct, _fmt, ...) \
>>> + guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>> #else
>>> -#define CT_DEBUG(...) do { } while (0)
>>> +#define ct_dbg(...) do { } while (0)
>>> #endif
>>> -#define CT_PROBE_ERROR(_ct, _fmt, ...) \
>>> - i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_probe_error(_ct, _fmt, ...) \
>>> + do { \
>>> + if (i915_error_injected()) \
>>> + ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
>>> + else \
>>> + ct_err(_ct, _fmt, ##__VA_ARGS__); \
>>> + } while (0)
>> guc_probe_error ?
>>
>>> +
>>> +#define ct_WARN_ON(_ct, _condition) \
>>> + ct_WARN(_ct, _condition, "%s", "ct_WARN_ON("
>>> __stringify(_condition) ")")
>>> +
>>> +#define ct_WARN(_ct, _condition, _fmt, ...) \
>>> + guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
>>> +
>>> +#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
>>> + guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt,
>>> ##__VA_ARGS__)
>>> /**
>>> * DOC: CTB Blob
>>> @@ -170,7 +188,7 @@ static int ct_control_enable(struct intel_guc_ct
>>> *ct, bool enable)
>>> err = guc_action_control_ctb(ct_to_guc(ct), enable ?
>>> GUC_CTB_CONTROL_ENABLE :
>>> GUC_CTB_CONTROL_DISABLE);
>>> if (unlikely(err))
>>> - CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
>>> + ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
>>> str_enable_disable(enable), ERR_PTR(err));
>> btw, shouldn't we change all messages to start with lowercase ?
>>
>> was:
>> "CT0: Failed to control/%s CTB (%pe)"
>> is:
>> "GT0: GuC CT Failed to control/%s CTB (%pe)"
>>
>> unless we keep colon (as suggested by Tvrtko) as then:
>>
>> "GT0: GuC CT: Failed to control/%s CTB (%pe)"
> Blanket added the colon makes it messy when a string actually wants to
> start with the prefix. The rule I've been using is lower case word when
> the prefix was part of the string, upper case word when the prefix is
Hmm, I'm not sure that we should attempt to have such a flexible rule as
we shouldn't rely too much on actual format of the prefix as it could be
changed any time. All we should know about final log message is that it
_will_ properly identify the "GT" or "GuC" that this log is related to.
So I would suggest to be just consistent and probably always start with
upper case, as that seems to be mostly used in kernel error logs, and
just make sure that any prefix will honor that (by including colon, or
braces), so this will always work like:
"[drm] *ERROR* GT0: Failed to foo (-EIO)"
"[drm] *ERROR* GT0: GUC: Failed to foo (-EIO)"
"[drm] *ERROR* GT0: GUC: CT: Failed to foo (-EIO)"
or
"[drm] *ERROR* GT0: Failed to foo (-EIO)"
"[drm] *ERROR* GT0: [GUC] Failed to foo (-EIO)"
"[drm] *ERROR* GT0: [GUC] CT: Failed to foo (-EIO)"
and even for:
"[drm] *ERROR* GT(root) Failed to foo (-EIO)"
"[drm] *ERROR* GuC(media) Failed to foo (-EIO)"
"[drm] *ERROR* GT0 [GuC:CT] Failed to foo (-EIO)"
> just being added as a prefix. I originally just had the prefix as raw
> with no trailing space, so the individual print could decide to add a
> colon, a space, or whatever as appropriate. But that just makes for
> messy code with some files having every string look like ": Stuff
> happened" and other files have every string look like " failed to ...".
> The current version seems to be the most readable from the point of view
> of writing the code and of reading the dmesg results.
>
> And to be clear, the 'CT0' you have in your 'was' example only exists in
> the internal tree. It never made it to upstream. It is also just plain
> wrong. Each GT has two CTs - send and receive. So having 'CT1' meaning
> some random CT on GT1 (as opposed to the read channel on GT0, for
> example) was very confusing.
I don't think I was wrong, it might be you confusing CT with CTB.
Note that we only support _single_ CT (Command Transport) and this
single CT includes _pair_ of CTBs (Command Transport Buffers).
And logs/macros are CT oriented, not CTB.
Regarding those my internal changes that were printing "CT%u": they were
added exactly for the same reason as your series: to know which GT
traffic we are tracing. And were done locally on CT level only as there
was no helpers that would automatically append "GT%u" prefix - helpers
that you're defining right now ;)
Michal
>
> John.
>
>
>>
>> Michal
>>
>>> return err;
>>> @@ -201,7 +219,7 @@ static int ct_register_buffer(struct intel_guc_ct
>>> *ct, bool send,
>>> size);
>>> if (unlikely(err))
>>> failed:
>>> - CT_PROBE_ERROR(ct, "Failed to register %s buffer (%pe)\n",
>>> + ct_probe_error(ct, "Failed to register %s buffer (%pe)\n",
>>> send ? "SEND" : "RECV", ERR_PTR(err));
>>> return err;
>>> @@ -235,21 +253,21 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>>> blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE +
>>> CTB_G2H_BUFFER_SIZE;
>>> err = intel_guc_allocate_and_map_vma(guc, blob_size, &ct->vma,
>>> &blob);
>>> if (unlikely(err)) {
>>> - CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data
>>> (%pe)\n",
>>> + ct_probe_error(ct, "Failed to allocate %u for CTB data
>>> (%pe)\n",
>>> blob_size, ERR_PTR(err));
>>> return err;
>>> }
>>> - CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc,
>>> ct->vma), blob_size);
>>> + ct_dbg(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc,
>>> ct->vma), blob_size);
>>> /* store pointers to desc and cmds for send ctb */
>>> desc = blob;
>>> cmds = blob + 2 * CTB_DESC_SIZE;
>>> cmds_size = CTB_H2G_BUFFER_SIZE;
>>> resv_space = 0;
>>> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
>>> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>>> - resv_space);
>>> + ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
>>> + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>>> + resv_space);
>>> guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size,
>>> resv_space);
>>> @@ -258,9 +276,9 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>>> cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
>>> cmds_size = CTB_G2H_BUFFER_SIZE;
>>> resv_space = G2H_ROOM_BUFFER_SIZE;
>>> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
>>> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>>> - resv_space);
>>> + ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
>>> + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>>> + resv_space);
>>> guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size,
>>> resv_space);
>>> @@ -338,7 +356,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>>> return 0;
>>> err_out:
>>> - CT_PROBE_ERROR(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
>>> + ct_probe_error(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
>>> return err;
>>> }
>>> @@ -387,14 +405,12 @@ static int ct_write(struct intel_guc_ct *ct,
>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>> if (unlikely(tail != READ_ONCE(desc->tail))) {
>>> - CT_ERROR(ct, "Tail was modified %u != %u\n",
>>> - desc->tail, tail);
>>> + ct_err(ct, "Tail was modified %u != %u\n", desc->tail, tail);
>>> desc->status |= GUC_CTB_STATUS_MISMATCH;
>>> goto corrupted;
>>> }
>>> if (unlikely(READ_ONCE(desc->head) >= size)) {
>>> - CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
>>> - desc->head, size);
>>> + ct_err(ct, "Invalid head offset %u >= %u)\n", desc->head,
>>> size);
>>> desc->status |= GUC_CTB_STATUS_OVERFLOW;
>>> goto corrupted;
>>> }
>>> @@ -415,8 +431,8 @@ static int ct_write(struct intel_guc_ct *ct,
>>> FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |
>>> GUC_HXG_EVENT_MSG_0_DATA0, action[0]);
>>> - CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
>>> - tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>>> + ct_dbg(ct, "writing (tail %u) %*ph %*ph %*ph\n",
>>> + tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>>> cmds[tail] = header;
>>> tail = (tail + 1) % size;
>>> @@ -447,8 +463,8 @@ static int ct_write(struct intel_guc_ct *ct,
>>> return 0;
>>> corrupted:
>>> - CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>>> - desc->head, desc->tail, desc->status);
>>> + ct_err(ct, "Corrupted descriptor on write head=%u tail=%u
>>> status=%#x\n",
>>> + desc->head, desc->tail, desc->status);
>>> ctb->broken = true;
>>> return -EPIPE;
>>> }
>>> @@ -507,17 +523,14 @@ static inline bool ct_deadlocked(struct
>>> intel_guc_ct *ct)
>>> struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
>>> struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
>>> - CT_ERROR(ct, "Communication stalled for %lld ms, desc
>>> status=%#x,%#x\n",
>>> - ktime_ms_delta(ktime_get(), ct->stall_time),
>>> - send->status, recv->status);
>>> - CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
>>> - atomic_read(&ct->ctbs.send.space) * 4);
>>> - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
>>> - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
>>> - CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
>>> - atomic_read(&ct->ctbs.recv.space) * 4);
>>> - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
>>> - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
>>> + ct_err(ct, "Communication stalled for %lld ms, desc
>>> status=%#x,%#x\n",
>>> + ktime_ms_delta(ktime_get(), ct->stall_time),
>>> send->status, recv->status);
>>> + ct_err(ct, "H2G Space: %u (Bytes)\n",
>>> atomic_read(&ct->ctbs.send.space) * 4);
>>> + ct_err(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
>>> + ct_err(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
>>> + ct_err(ct, "G2H Space: %u (Bytes)\n",
>>> atomic_read(&ct->ctbs.recv.space) * 4);
>>> + ct_err(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
>>> + ct_err(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
>>> ct->ctbs.send.broken = true;
>>> }
>>> @@ -563,8 +576,7 @@ static inline bool h2g_has_room(struct
>>> intel_guc_ct *ct, u32 len_dw)
>>> head = READ_ONCE(desc->head);
>>> if (unlikely(head > ctb->size)) {
>>> - CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
>>> - head, ctb->size);
>>> + ct_err(ct, "Invalid head offset %u >= %u)\n", head, ctb->size);
>>> desc->status |= GUC_CTB_STATUS_OVERFLOW;
>>> ctb->broken = true;
>>> return false;
>>> @@ -715,17 +727,17 @@ static int ct_send(struct intel_guc_ct *ct,
>>> /* wait_for_ct_request_update returns -ENODEV on
>>> reset/suspend in progress.
>>> * In this case, output is debug rather than error info
>>> */
>>> - CT_DEBUG(ct, "Request %#x (fence %u) cancelled as CTB is
>>> disabled\n",
>>> - action[0], request.fence);
>>> + ct_dbg(ct, "Request %#x (fence %u) cancelled as CTB is
>>> disabled\n",
>>> + action[0], request.fence);
>>> else
>>> - CT_ERROR(ct, "No response for request %#x (fence %u)\n",
>>> - action[0], request.fence);
>>> + ct_err(ct, "No response for request %#x (fence %u)\n",
>>> + action[0], request.fence);
>>> goto unlink;
>>> }
>>> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, *status) ==
>>> GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
>>> - CT_DEBUG(ct, "retrying request %#x (%u)\n", *action,
>>> - FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
>>> + ct_dbg(ct, "retrying request %#x (%u)\n", *action,
>>> + FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
>>> send_again = true;
>>> goto unlink;
>>> }
>>> @@ -737,12 +749,12 @@ static int ct_send(struct intel_guc_ct *ct,
>>> if (response_buf) {
>>> /* There shall be no data in the status */
>>> - WARN_ON(FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0,
>>> request.status));
>>> + ct_WARN_ON(ct, FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0,
>>> request.status));
>>> /* Return actual response len */
>>> err = request.response_len;
>>> } else {
>>> /* There shall be no response payload */
>>> - WARN_ON(request.response_len);
>>> + ct_WARN_ON(ct, request.response_len);
>>> /* Return data decoded from the status dword */
>>> err = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, *status);
>>> }
>>> @@ -771,7 +783,7 @@ int intel_guc_ct_send(struct intel_guc_ct *ct,
>>> const u32 *action, u32 len,
>>> struct intel_guc *guc = ct_to_guc(ct);
>>> struct intel_uc *uc = container_of(guc, struct intel_uc, guc);
>>> - WARN(!uc->reset_in_progress, "Unexpected send:
>>> action=%#x\n", *action);
>>> + ct_WARN(ct, !uc->reset_in_progress, "Unexpected send:
>>> action=%#x\n", *action);
>>> return -ENODEV;
>>> }
>>> @@ -784,11 +796,11 @@ int intel_guc_ct_send(struct intel_guc_ct
>>> *ct, const u32 *action, u32 len,
>>> ret = ct_send(ct, action, len, response_buf, response_buf_size,
>>> &status);
>>> if (unlikely(ret < 0)) {
>>> if (ret != -ENODEV)
>>> - CT_ERROR(ct, "Sending action %#x failed (%pe)
>>> status=%#X\n",
>>> - action[0], ERR_PTR(ret), status);
>>> + ct_err(ct, "sending action %#x failed (%pe) status=%#X\n",
>>> + action[0], ERR_PTR(ret), status);
>>> } else if (unlikely(ret)) {
>>> - CT_DEBUG(ct, "send action %#x returned %d (%#x)\n",
>>> - action[0], ret, ret);
>>> + ct_dbg(ct, "send action %#x returned %d (%#x)\n",
>>> + action[0], ret, ret);
>>> }
>>> return ret;
>>> @@ -838,7 +850,7 @@ static int ct_read(struct intel_guc_ct *ct,
>>> struct ct_incoming_msg **msg)
>>> * contexts/engines being reset. But should never
>>> happen as
>>> * no contexts should be active when CLIENT_RESET is sent.
>>> */
>>> - CT_ERROR(ct, "Unexpected G2H after GuC has stopped!\n");
>>> + ct_err(ct, "Unexpected G2H after GuC has stopped!\n");
>>> status &= ~GUC_CTB_STATUS_UNUSED;
>>> }
>>> @@ -850,15 +862,13 @@ static int ct_read(struct intel_guc_ct *ct,
>>> struct ct_incoming_msg **msg)
>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>> if (unlikely(head != READ_ONCE(desc->head))) {
>>> - CT_ERROR(ct, "Head was modified %u != %u\n",
>>> - desc->head, head);
>>> + ct_err(ct, "Head was modified %u != %u\n", desc->head, head);
>>> desc->status |= GUC_CTB_STATUS_MISMATCH;
>>> goto corrupted;
>>> }
>>> #endif
>>> if (unlikely(tail >= size)) {
>>> - CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
>>> - tail, size);
>>> + ct_err(ct, "Invalid tail offset %u >= %u)\n", tail, size);
>>> desc->status |= GUC_CTB_STATUS_OVERFLOW;
>>> goto corrupted;
>>> }
>>> @@ -873,7 +883,7 @@ static int ct_read(struct intel_guc_ct *ct,
>>> struct ct_incoming_msg **msg)
>>> /* beware of buffer wrap case */
>>> if (unlikely(available < 0))
>>> available += size;
>>> - CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail,
>>> size);
>>> + ct_dbg(ct, "read available %d (%u:%u:%u)\n", available, head,
>>> tail, size);
>>> GEM_BUG_ON(available < 0);
>>> header = cmds[head];
>>> @@ -882,24 +892,24 @@ static int ct_read(struct intel_guc_ct *ct,
>>> struct ct_incoming_msg **msg)
>>> /* message len with header */
>>> len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, header) +
>>> GUC_CTB_MSG_MIN_LEN;
>>> if (unlikely(len > (u32)available)) {
>>> - CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
>>> - 4, &header,
>>> - 4 * (head + available - 1 > size ?
>>> - size - head : available - 1), &cmds[head],
>>> - 4 * (head + available - 1 > size ?
>>> - available - 1 - size + head : 0), &cmds[0]);
>>> + ct_err(ct, "Incomplete message %*ph %*ph %*ph\n",
>>> + 4, &header,
>>> + 4 * (head + available - 1 > size ?
>>> + size - head : available - 1), &cmds[head],
>>> + 4 * (head + available - 1 > size ?
>>> + available - 1 - size + head : 0), &cmds[0]);
>>> desc->status |= GUC_CTB_STATUS_UNDERFLOW;
>>> goto corrupted;
>>> }
>>> *msg = ct_alloc_msg(len);
>>> if (!*msg) {
>>> - CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
>>> - 4, &header,
>>> - 4 * (head + available - 1 > size ?
>>> - size - head : available - 1), &cmds[head],
>>> - 4 * (head + available - 1 > size ?
>>> - available - 1 - size + head : 0), &cmds[0]);
>>> + ct_err(ct, "No memory for message %*ph %*ph %*ph\n",
>>> + 4, &header,
>>> + 4 * (head + available - 1 > size ?
>>> + size - head : available - 1), &cmds[head],
>>> + 4 * (head + available - 1 > size ?
>>> + available - 1 - size + head : 0), &cmds[0]);
>>> return available;
>>> }
>>> @@ -909,7 +919,7 @@ static int ct_read(struct intel_guc_ct *ct,
>>> struct ct_incoming_msg **msg)
>>> (*msg)->msg[i] = cmds[head];
>>> head = (head + 1) % size;
>>> }
>>> - CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
>>> + ct_dbg(ct, "received %*ph\n", 4 * len, (*msg)->msg);
>>> /* update local copies */
>>> ctb->head = head;
>>> @@ -920,8 +930,8 @@ static int ct_read(struct intel_guc_ct *ct,
>>> struct ct_incoming_msg **msg)
>>> return available - len;
>>> corrupted:
>>> - CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>>> - desc->head, desc->tail, desc->status);
>>> + ct_err(ct, "Corrupted descriptor on read head=%u tail=%u
>>> status=%#x\n",
>>> + desc->head, desc->tail, desc->status);
>>> ctb->broken = true;
>>> return -EPIPE;
>>> }
>>> @@ -944,18 +954,17 @@ static int ct_handle_response(struct
>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>> FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) !=
>>> GUC_HXG_TYPE_NO_RESPONSE_RETRY &&
>>> FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) !=
>>> GUC_HXG_TYPE_RESPONSE_FAILURE);
>>> - CT_DEBUG(ct, "response fence %u status %#x\n", fence, hxg[0]);
>>> + ct_dbg(ct, "response fence %u status %#x\n", fence, hxg[0]);
>>> spin_lock_irqsave(&ct->requests.lock, flags);
>>> list_for_each_entry(req, &ct->requests.pending, link) {
>>> if (unlikely(fence != req->fence)) {
>>> - CT_DEBUG(ct, "request %u awaits response\n",
>>> - req->fence);
>>> + ct_dbg(ct, "request %u awaits response\n", req->fence);
>>> continue;
>>> }
>>> if (unlikely(datalen > req->response_len)) {
>>> - CT_ERROR(ct, "Response %u too long (datalen %u > %u)\n",
>>> - req->fence, datalen, req->response_len);
>>> + ct_err(ct, "response %u too long (datalen %u > %u)\n",
>>> + req->fence, datalen, req->response_len);
>>> datalen = min(datalen, req->response_len);
>>> err = -EMSGSIZE;
>>> }
>>> @@ -967,12 +976,11 @@ static int ct_handle_response(struct
>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>> break;
>>> }
>>> if (!found) {
>>> - CT_ERROR(ct, "Unsolicited response (fence %u)\n", fence);
>>> - CT_ERROR(ct, "Could not find fence=%u, last_fence=%u\n", fence,
>>> - ct->requests.last_fence);
>>> + ct_err(ct, "Unsolicited response (fence %u)\n", fence);
>>> + ct_err(ct, "Could not find fence=%u, last_fence=%u\n", fence,
>>> + ct->requests.last_fence);
>>> list_for_each_entry(req, &ct->requests.pending, link)
>>> - CT_ERROR(ct, "request %u awaits response\n",
>>> - req->fence);
>>> + ct_err(ct, "request %u awaits response\n", req->fence);
>>> err = -ENOKEY;
>>> }
>>> spin_unlock_irqrestore(&ct->requests.lock, flags);
>>> @@ -998,7 +1006,7 @@ static int ct_process_request(struct
>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>> action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, hxg[0]);
>>> len = hxg_len - GUC_HXG_MSG_MIN_LEN;
>>> - CT_DEBUG(ct, "request %x %*ph\n", action, 4 * len, payload);
>>> + ct_dbg(ct, "request %x %*ph\n", action, 4 * len, payload);
>>> switch (action) {
>>> case INTEL_GUC_ACTION_DEFAULT:
>>> @@ -1016,9 +1024,6 @@ static int ct_process_request(struct
>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>> break;
>>> case INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION:
>>> ret = intel_guc_error_capture_process_msg(guc, payload, len);
>>> - if (unlikely(ret))
>>> - CT_ERROR(ct, "error capture notification failed %x %*ph\n",
>>> - action, 4 * len, payload);
>>> break;
>>> case INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION:
>>> ret = intel_guc_engine_failure_process_msg(guc, payload, len);
>>> @@ -1028,11 +1033,11 @@ static int ct_process_request(struct
>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>> ret = 0;
>>> break;
>>> case INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED:
>>> - CT_ERROR(ct, "Received GuC crash dump notification!\n");
>>> + guc_err(guc, "notification: Crash dump!\n");
>>> ret = 0;
>>> break;
>>> case INTEL_GUC_ACTION_NOTIFY_EXCEPTION:
>>> - CT_ERROR(ct, "Received GuC exception notification!\n");
>>> + guc_err(guc, "notification: Exception!\n");
>>> ret = 0;
>>> break;
>>> default:
>>> @@ -1041,8 +1046,7 @@ static int ct_process_request(struct
>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>> }
>>> if (unlikely(ret)) {
>>> - CT_ERROR(ct, "Failed to process request %04x (%pe)\n",
>>> - action, ERR_PTR(ret));
>>> + ct_err(ct, "Failed to process request %04x (%pe)\n", action,
>>> ERR_PTR(ret));
>>> return ret;
>>> }
>>> @@ -1070,8 +1074,8 @@ static bool
>>> ct_process_incoming_requests(struct intel_guc_ct *ct)
>>> err = ct_process_request(ct, request);
>>> if (unlikely(err)) {
>>> - CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
>>> - ERR_PTR(err), 4 * request->size, request->msg);
>>> + ct_err(ct, "Failed to process message (%pe) %*ph\n",
>>> + ERR_PTR(err), 4 * request->size, request->msg);
>>> ct_free_msg(request);
>>> }
>>> @@ -1149,8 +1153,8 @@ static int ct_handle_hxg(struct intel_guc_ct
>>> *ct, struct ct_incoming_msg *msg)
>>> if (unlikely(err)) {
>>> failed:
>>> - CT_ERROR(ct, "Failed to handle HXG message (%pe) %*ph\n",
>>> - ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
>>> + ct_err(ct, "Failed to handle HXG message (%pe) %*ph\n",
>>> + ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
>>> }
>>> return err;
>>> }
>>> @@ -1166,8 +1170,8 @@ static void ct_handle_msg(struct intel_guc_ct
>>> *ct, struct ct_incoming_msg *msg)
>>> err = -EOPNOTSUPP;
>>> if (unlikely(err)) {
>>> - CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
>>> - ERR_PTR(err), 4 * msg->size, msg->msg);
>>> + ct_err(ct, "Failed to handle message (%pe) %*ph\n",
>>> + ERR_PTR(err), 4 * msg->size, msg->msg);
>>> ct_free_msg(msg);
>>> }
>>> }
>>> @@ -1198,7 +1202,7 @@ static void ct_try_receive_message(struct
>>> intel_guc_ct *ct)
>>> {
>>> int ret;
>>> - if (GEM_WARN_ON(!ct->enabled))
>>> + if (ct_WARN_ON(ct, !ct->enabled))
>>> return;
>>> ret = ct_receive(ct);
>>> @@ -1220,7 +1224,7 @@ static void ct_receive_tasklet_func(struct
>>> tasklet_struct *t)
>>> void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
>>> {
>>> if (unlikely(!ct->enabled)) {
>>> - WARN(1, "Unexpected GuC event received while CT disabled!\n");
>>> + ct_warn(ct, "Unexpected event received while disabled!\n");
>>> return;
>>> }
>>>
>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2022-11-23 20:45 ` Michal Wajdeczko
@ 2022-12-01 0:41 ` John Harrison
2022-12-01 11:56 ` Michal Wajdeczko
0 siblings, 1 reply; 51+ messages in thread
From: John Harrison @ 2022-12-01 0:41 UTC (permalink / raw)
To: Michal Wajdeczko, Intel-GFX; +Cc: DRI-Devel
On 11/23/2022 12:45, Michal Wajdeczko wrote:
> On 23.11.2022 02:25, John Harrison wrote:
>> On 11/22/2022 09:54, Michal Wajdeczko wrote:
>>> On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
>>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>>
>>>> Re-work the existing GuC CT printers and extend as required to match
>>>> the new wrapping scheme.
>>>>
>>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++++-----------
>>>> 1 file changed, 113 insertions(+), 109 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>> index 2b22065e87bf9..9d404fb377637 100644
>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>> @@ -18,31 +18,49 @@ static inline struct intel_guc *ct_to_guc(struct
>>>> intel_guc_ct *ct)
>>>> return container_of(ct, struct intel_guc, ct);
>>>> }
>>>> -static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
>>>> -{
>>>> - return guc_to_gt(ct_to_guc(ct));
>>>> -}
>>>> -
>>>> static inline struct drm_i915_private *ct_to_i915(struct
>>>> intel_guc_ct *ct)
>>>> {
>>>> - return ct_to_gt(ct)->i915;
>>>> -}
>>>> + struct intel_guc *guc = ct_to_guc(ct);
>>>> + struct intel_gt *gt = guc_to_gt(guc);
>>>> -static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
>>>> -{
>>>> - return &ct_to_i915(ct)->drm;
>>>> + return gt->i915;
>>>> }
>>>> -#define CT_ERROR(_ct, _fmt, ...) \
>>>> - drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>>> +#define ct_err(_ct, _fmt, ...) \
>>>> + guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>> +
>>>> +#define ct_warn(_ct, _fmt, ...) \
>>>> + guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>> +
>>>> +#define ct_notice(_ct, _fmt, ...) \
>>>> + guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>> +
>>>> +#define ct_info(_ct, _fmt, ...) \
>>>> + guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>> +
>>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>>> -#define CT_DEBUG(_ct, _fmt, ...) \
>>>> - drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>>> +#define ct_dbg(_ct, _fmt, ...) \
>>>> + guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>> #else
>>>> -#define CT_DEBUG(...) do { } while (0)
>>>> +#define ct_dbg(...) do { } while (0)
>>>> #endif
>>>> -#define CT_PROBE_ERROR(_ct, _fmt, ...) \
>>>> - i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
>>>> +
>>>> +#define ct_probe_error(_ct, _fmt, ...) \
>>>> + do { \
>>>> + if (i915_error_injected()) \
>>>> + ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
>>>> + else \
>>>> + ct_err(_ct, _fmt, ##__VA_ARGS__); \
>>>> + } while (0)
>>> guc_probe_error ?
>>>
>>>> +
>>>> +#define ct_WARN_ON(_ct, _condition) \
>>>> + ct_WARN(_ct, _condition, "%s", "ct_WARN_ON("
>>>> __stringify(_condition) ")")
>>>> +
>>>> +#define ct_WARN(_ct, _condition, _fmt, ...) \
>>>> + guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
>>>> +
>>>> +#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
>>>> + guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt,
>>>> ##__VA_ARGS__)
>>>> /**
>>>> * DOC: CTB Blob
>>>> @@ -170,7 +188,7 @@ static int ct_control_enable(struct intel_guc_ct
>>>> *ct, bool enable)
>>>> err = guc_action_control_ctb(ct_to_guc(ct), enable ?
>>>> GUC_CTB_CONTROL_ENABLE :
>>>> GUC_CTB_CONTROL_DISABLE);
>>>> if (unlikely(err))
>>>> - CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
>>>> + ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
>>>> str_enable_disable(enable), ERR_PTR(err));
>>> btw, shouldn't we change all messages to start with lowercase ?
>>>
>>> was:
>>> "CT0: Failed to control/%s CTB (%pe)"
>>> is:
>>> "GT0: GuC CT Failed to control/%s CTB (%pe)"
>>>
>>> unless we keep colon (as suggested by Tvrtko) as then:
>>>
>>> "GT0: GuC CT: Failed to control/%s CTB (%pe)"
>> Blanket added the colon makes it messy when a string actually wants to
>> start with the prefix. The rule I've been using is lower case word when
>> the prefix was part of the string, upper case word when the prefix is
> Hmm, I'm not sure that we should attempt to have such a flexible rule as
> we shouldn't rely too much on actual format of the prefix as it could be
> changed any time. All we should know about final log message is that it
> _will_ properly identify the "GT" or "GuC" that this log is related to.
>
> So I would suggest to be just consistent and probably always start with
> upper case, as that seems to be mostly used in kernel error logs, and
> just make sure that any prefix will honor that (by including colon, or
> braces), so this will always work like:
>
> "[drm] *ERROR* GT0: Failed to foo (-EIO)"
> "[drm] *ERROR* GT0: GUC: Failed to foo (-EIO)"
> "[drm] *ERROR* GT0: GUC: CT: Failed to foo (-EIO)"
>
> or
>
> "[drm] *ERROR* GT0: Failed to foo (-EIO)"
> "[drm] *ERROR* GT0: [GUC] Failed to foo (-EIO)"
> "[drm] *ERROR* GT0: [GUC] CT: Failed to foo (-EIO)"
>
> and even for:
>
> "[drm] *ERROR* GT(root) Failed to foo (-EIO)"
> "[drm] *ERROR* GuC(media) Failed to foo (-EIO)"
> "[drm] *ERROR* GT0 [GuC:CT] Failed to foo (-EIO)"
All of which are hideous/complex/verbose/inconsistent. 'GT0: GUC: CT:'?
Really? Or 'GT0: [GUC] CT:'? Why the random mix of separators? And how
would you implement '[GUC:CT]' without having a CT definition that is
entirely self contained and does chain on to the GuC level version?
This is pointless bikeshedding. If you want to re-write every single
debug print (yet again) and invent much more complicated macro
definitions then feel free to take over the patch set. If not can we
just approve the v3 version and move on to doing some actual work?
John.
>
>
>> just being added as a prefix. I originally just had the prefix as raw
>> with no trailing space, so the individual print could decide to add a
>> colon, a space, or whatever as appropriate. But that just makes for
>> messy code with some files having every string look like ": Stuff
>> happened" and other files have every string look like " failed to ...".
>> The current version seems to be the most readable from the point of view
>> of writing the code and of reading the dmesg results.
>>
>> And to be clear, the 'CT0' you have in your 'was' example only exists in
>> the internal tree. It never made it to upstream. It is also just plain
>> wrong. Each GT has two CTs - send and receive. So having 'CT1' meaning
>> some random CT on GT1 (as opposed to the read channel on GT0, for
>> example) was very confusing.
> I don't think I was wrong, it might be you confusing CT with CTB.
>
> Note that we only support _single_ CT (Command Transport) and this
> single CT includes _pair_ of CTBs (Command Transport Buffers).
>
> And logs/macros are CT oriented, not CTB.
The GuC spec does not make any distinction. In fact, there is no CT in
the spec. There is just CTB. So at best it is ambiguous as to what CT0 /
CT1 refers to.
>
> Regarding those my internal changes that were printing "CT%u": they were
> added exactly for the same reason as your series: to know which GT
> traffic we are tracing. And were done locally on CT level only as there
> was no helpers that would automatically append "GT%u" prefix - helpers
> that you're defining right now ;)
>
> Michal
>
>> John.
>>
>>
>>> Michal
>>>
>>>> return err;
>>>> @@ -201,7 +219,7 @@ static int ct_register_buffer(struct intel_guc_ct
>>>> *ct, bool send,
>>>> size);
>>>> if (unlikely(err))
>>>> failed:
>>>> - CT_PROBE_ERROR(ct, "Failed to register %s buffer (%pe)\n",
>>>> + ct_probe_error(ct, "Failed to register %s buffer (%pe)\n",
>>>> send ? "SEND" : "RECV", ERR_PTR(err));
>>>> return err;
>>>> @@ -235,21 +253,21 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>>>> blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE +
>>>> CTB_G2H_BUFFER_SIZE;
>>>> err = intel_guc_allocate_and_map_vma(guc, blob_size, &ct->vma,
>>>> &blob);
>>>> if (unlikely(err)) {
>>>> - CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data
>>>> (%pe)\n",
>>>> + ct_probe_error(ct, "Failed to allocate %u for CTB data
>>>> (%pe)\n",
>>>> blob_size, ERR_PTR(err));
>>>> return err;
>>>> }
>>>> - CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc,
>>>> ct->vma), blob_size);
>>>> + ct_dbg(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc,
>>>> ct->vma), blob_size);
>>>> /* store pointers to desc and cmds for send ctb */
>>>> desc = blob;
>>>> cmds = blob + 2 * CTB_DESC_SIZE;
>>>> cmds_size = CTB_H2G_BUFFER_SIZE;
>>>> resv_space = 0;
>>>> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
>>>> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>>>> - resv_space);
>>>> + ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
>>>> + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>>>> + resv_space);
>>>> guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size,
>>>> resv_space);
>>>> @@ -258,9 +276,9 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>>>> cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
>>>> cmds_size = CTB_G2H_BUFFER_SIZE;
>>>> resv_space = G2H_ROOM_BUFFER_SIZE;
>>>> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
>>>> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>>>> - resv_space);
>>>> + ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
>>>> + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>>>> + resv_space);
>>>> guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size,
>>>> resv_space);
>>>> @@ -338,7 +356,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>>>> return 0;
>>>> err_out:
>>>> - CT_PROBE_ERROR(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
>>>> + ct_probe_error(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
>>>> return err;
>>>> }
>>>> @@ -387,14 +405,12 @@ static int ct_write(struct intel_guc_ct *ct,
>>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>>> if (unlikely(tail != READ_ONCE(desc->tail))) {
>>>> - CT_ERROR(ct, "Tail was modified %u != %u\n",
>>>> - desc->tail, tail);
>>>> + ct_err(ct, "Tail was modified %u != %u\n", desc->tail, tail);
>>>> desc->status |= GUC_CTB_STATUS_MISMATCH;
>>>> goto corrupted;
>>>> }
>>>> if (unlikely(READ_ONCE(desc->head) >= size)) {
>>>> - CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
>>>> - desc->head, size);
>>>> + ct_err(ct, "Invalid head offset %u >= %u)\n", desc->head,
>>>> size);
>>>> desc->status |= GUC_CTB_STATUS_OVERFLOW;
>>>> goto corrupted;
>>>> }
>>>> @@ -415,8 +431,8 @@ static int ct_write(struct intel_guc_ct *ct,
>>>> FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |
>>>> GUC_HXG_EVENT_MSG_0_DATA0, action[0]);
>>>> - CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
>>>> - tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>>>> + ct_dbg(ct, "writing (tail %u) %*ph %*ph %*ph\n",
>>>> + tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>>>> cmds[tail] = header;
>>>> tail = (tail + 1) % size;
>>>> @@ -447,8 +463,8 @@ static int ct_write(struct intel_guc_ct *ct,
>>>> return 0;
>>>> corrupted:
>>>> - CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>>>> - desc->head, desc->tail, desc->status);
>>>> + ct_err(ct, "Corrupted descriptor on write head=%u tail=%u
>>>> status=%#x\n",
>>>> + desc->head, desc->tail, desc->status);
>>>> ctb->broken = true;
>>>> return -EPIPE;
>>>> }
>>>> @@ -507,17 +523,14 @@ static inline bool ct_deadlocked(struct
>>>> intel_guc_ct *ct)
>>>> struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
>>>> struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
>>>> - CT_ERROR(ct, "Communication stalled for %lld ms, desc
>>>> status=%#x,%#x\n",
>>>> - ktime_ms_delta(ktime_get(), ct->stall_time),
>>>> - send->status, recv->status);
>>>> - CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
>>>> - atomic_read(&ct->ctbs.send.space) * 4);
>>>> - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
>>>> - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
>>>> - CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
>>>> - atomic_read(&ct->ctbs.recv.space) * 4);
>>>> - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
>>>> - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
>>>> + ct_err(ct, "Communication stalled for %lld ms, desc
>>>> status=%#x,%#x\n",
>>>> + ktime_ms_delta(ktime_get(), ct->stall_time),
>>>> send->status, recv->status);
>>>> + ct_err(ct, "H2G Space: %u (Bytes)\n",
>>>> atomic_read(&ct->ctbs.send.space) * 4);
>>>> + ct_err(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
>>>> + ct_err(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
>>>> + ct_err(ct, "G2H Space: %u (Bytes)\n",
>>>> atomic_read(&ct->ctbs.recv.space) * 4);
>>>> + ct_err(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
>>>> + ct_err(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
>>>> ct->ctbs.send.broken = true;
>>>> }
>>>> @@ -563,8 +576,7 @@ static inline bool h2g_has_room(struct
>>>> intel_guc_ct *ct, u32 len_dw)
>>>> head = READ_ONCE(desc->head);
>>>> if (unlikely(head > ctb->size)) {
>>>> - CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
>>>> - head, ctb->size);
>>>> + ct_err(ct, "Invalid head offset %u >= %u)\n", head, ctb->size);
>>>> desc->status |= GUC_CTB_STATUS_OVERFLOW;
>>>> ctb->broken = true;
>>>> return false;
>>>> @@ -715,17 +727,17 @@ static int ct_send(struct intel_guc_ct *ct,
>>>> /* wait_for_ct_request_update returns -ENODEV on
>>>> reset/suspend in progress.
>>>> * In this case, output is debug rather than error info
>>>> */
>>>> - CT_DEBUG(ct, "Request %#x (fence %u) cancelled as CTB is
>>>> disabled\n",
>>>> - action[0], request.fence);
>>>> + ct_dbg(ct, "Request %#x (fence %u) cancelled as CTB is
>>>> disabled\n",
>>>> + action[0], request.fence);
>>>> else
>>>> - CT_ERROR(ct, "No response for request %#x (fence %u)\n",
>>>> - action[0], request.fence);
>>>> + ct_err(ct, "No response for request %#x (fence %u)\n",
>>>> + action[0], request.fence);
>>>> goto unlink;
>>>> }
>>>> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, *status) ==
>>>> GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
>>>> - CT_DEBUG(ct, "retrying request %#x (%u)\n", *action,
>>>> - FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
>>>> + ct_dbg(ct, "retrying request %#x (%u)\n", *action,
>>>> + FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
>>>> send_again = true;
>>>> goto unlink;
>>>> }
>>>> @@ -737,12 +749,12 @@ static int ct_send(struct intel_guc_ct *ct,
>>>> if (response_buf) {
>>>> /* There shall be no data in the status */
>>>> - WARN_ON(FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0,
>>>> request.status));
>>>> + ct_WARN_ON(ct, FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0,
>>>> request.status));
>>>> /* Return actual response len */
>>>> err = request.response_len;
>>>> } else {
>>>> /* There shall be no response payload */
>>>> - WARN_ON(request.response_len);
>>>> + ct_WARN_ON(ct, request.response_len);
>>>> /* Return data decoded from the status dword */
>>>> err = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, *status);
>>>> }
>>>> @@ -771,7 +783,7 @@ int intel_guc_ct_send(struct intel_guc_ct *ct,
>>>> const u32 *action, u32 len,
>>>> struct intel_guc *guc = ct_to_guc(ct);
>>>> struct intel_uc *uc = container_of(guc, struct intel_uc, guc);
>>>> - WARN(!uc->reset_in_progress, "Unexpected send:
>>>> action=%#x\n", *action);
>>>> + ct_WARN(ct, !uc->reset_in_progress, "Unexpected send:
>>>> action=%#x\n", *action);
>>>> return -ENODEV;
>>>> }
>>>> @@ -784,11 +796,11 @@ int intel_guc_ct_send(struct intel_guc_ct
>>>> *ct, const u32 *action, u32 len,
>>>> ret = ct_send(ct, action, len, response_buf, response_buf_size,
>>>> &status);
>>>> if (unlikely(ret < 0)) {
>>>> if (ret != -ENODEV)
>>>> - CT_ERROR(ct, "Sending action %#x failed (%pe)
>>>> status=%#X\n",
>>>> - action[0], ERR_PTR(ret), status);
>>>> + ct_err(ct, "sending action %#x failed (%pe) status=%#X\n",
>>>> + action[0], ERR_PTR(ret), status);
>>>> } else if (unlikely(ret)) {
>>>> - CT_DEBUG(ct, "send action %#x returned %d (%#x)\n",
>>>> - action[0], ret, ret);
>>>> + ct_dbg(ct, "send action %#x returned %d (%#x)\n",
>>>> + action[0], ret, ret);
>>>> }
>>>> return ret;
>>>> @@ -838,7 +850,7 @@ static int ct_read(struct intel_guc_ct *ct,
>>>> struct ct_incoming_msg **msg)
>>>> * contexts/engines being reset. But should never
>>>> happen as
>>>> * no contexts should be active when CLIENT_RESET is sent.
>>>> */
>>>> - CT_ERROR(ct, "Unexpected G2H after GuC has stopped!\n");
>>>> + ct_err(ct, "Unexpected G2H after GuC has stopped!\n");
>>>> status &= ~GUC_CTB_STATUS_UNUSED;
>>>> }
>>>> @@ -850,15 +862,13 @@ static int ct_read(struct intel_guc_ct *ct,
>>>> struct ct_incoming_msg **msg)
>>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>>> if (unlikely(head != READ_ONCE(desc->head))) {
>>>> - CT_ERROR(ct, "Head was modified %u != %u\n",
>>>> - desc->head, head);
>>>> + ct_err(ct, "Head was modified %u != %u\n", desc->head, head);
>>>> desc->status |= GUC_CTB_STATUS_MISMATCH;
>>>> goto corrupted;
>>>> }
>>>> #endif
>>>> if (unlikely(tail >= size)) {
>>>> - CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
>>>> - tail, size);
>>>> + ct_err(ct, "Invalid tail offset %u >= %u)\n", tail, size);
>>>> desc->status |= GUC_CTB_STATUS_OVERFLOW;
>>>> goto corrupted;
>>>> }
>>>> @@ -873,7 +883,7 @@ static int ct_read(struct intel_guc_ct *ct,
>>>> struct ct_incoming_msg **msg)
>>>> /* beware of buffer wrap case */
>>>> if (unlikely(available < 0))
>>>> available += size;
>>>> - CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail,
>>>> size);
>>>> + ct_dbg(ct, "read available %d (%u:%u:%u)\n", available, head,
>>>> tail, size);
>>>> GEM_BUG_ON(available < 0);
>>>> header = cmds[head];
>>>> @@ -882,24 +892,24 @@ static int ct_read(struct intel_guc_ct *ct,
>>>> struct ct_incoming_msg **msg)
>>>> /* message len with header */
>>>> len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, header) +
>>>> GUC_CTB_MSG_MIN_LEN;
>>>> if (unlikely(len > (u32)available)) {
>>>> - CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
>>>> - 4, &header,
>>>> - 4 * (head + available - 1 > size ?
>>>> - size - head : available - 1), &cmds[head],
>>>> - 4 * (head + available - 1 > size ?
>>>> - available - 1 - size + head : 0), &cmds[0]);
>>>> + ct_err(ct, "Incomplete message %*ph %*ph %*ph\n",
>>>> + 4, &header,
>>>> + 4 * (head + available - 1 > size ?
>>>> + size - head : available - 1), &cmds[head],
>>>> + 4 * (head + available - 1 > size ?
>>>> + available - 1 - size + head : 0), &cmds[0]);
>>>> desc->status |= GUC_CTB_STATUS_UNDERFLOW;
>>>> goto corrupted;
>>>> }
>>>> *msg = ct_alloc_msg(len);
>>>> if (!*msg) {
>>>> - CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
>>>> - 4, &header,
>>>> - 4 * (head + available - 1 > size ?
>>>> - size - head : available - 1), &cmds[head],
>>>> - 4 * (head + available - 1 > size ?
>>>> - available - 1 - size + head : 0), &cmds[0]);
>>>> + ct_err(ct, "No memory for message %*ph %*ph %*ph\n",
>>>> + 4, &header,
>>>> + 4 * (head + available - 1 > size ?
>>>> + size - head : available - 1), &cmds[head],
>>>> + 4 * (head + available - 1 > size ?
>>>> + available - 1 - size + head : 0), &cmds[0]);
>>>> return available;
>>>> }
>>>> @@ -909,7 +919,7 @@ static int ct_read(struct intel_guc_ct *ct,
>>>> struct ct_incoming_msg **msg)
>>>> (*msg)->msg[i] = cmds[head];
>>>> head = (head + 1) % size;
>>>> }
>>>> - CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
>>>> + ct_dbg(ct, "received %*ph\n", 4 * len, (*msg)->msg);
>>>> /* update local copies */
>>>> ctb->head = head;
>>>> @@ -920,8 +930,8 @@ static int ct_read(struct intel_guc_ct *ct,
>>>> struct ct_incoming_msg **msg)
>>>> return available - len;
>>>> corrupted:
>>>> - CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>>>> - desc->head, desc->tail, desc->status);
>>>> + ct_err(ct, "Corrupted descriptor on read head=%u tail=%u
>>>> status=%#x\n",
>>>> + desc->head, desc->tail, desc->status);
>>>> ctb->broken = true;
>>>> return -EPIPE;
>>>> }
>>>> @@ -944,18 +954,17 @@ static int ct_handle_response(struct
>>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>>> FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) !=
>>>> GUC_HXG_TYPE_NO_RESPONSE_RETRY &&
>>>> FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) !=
>>>> GUC_HXG_TYPE_RESPONSE_FAILURE);
>>>> - CT_DEBUG(ct, "response fence %u status %#x\n", fence, hxg[0]);
>>>> + ct_dbg(ct, "response fence %u status %#x\n", fence, hxg[0]);
>>>> spin_lock_irqsave(&ct->requests.lock, flags);
>>>> list_for_each_entry(req, &ct->requests.pending, link) {
>>>> if (unlikely(fence != req->fence)) {
>>>> - CT_DEBUG(ct, "request %u awaits response\n",
>>>> - req->fence);
>>>> + ct_dbg(ct, "request %u awaits response\n", req->fence);
>>>> continue;
>>>> }
>>>> if (unlikely(datalen > req->response_len)) {
>>>> - CT_ERROR(ct, "Response %u too long (datalen %u > %u)\n",
>>>> - req->fence, datalen, req->response_len);
>>>> + ct_err(ct, "response %u too long (datalen %u > %u)\n",
>>>> + req->fence, datalen, req->response_len);
>>>> datalen = min(datalen, req->response_len);
>>>> err = -EMSGSIZE;
>>>> }
>>>> @@ -967,12 +976,11 @@ static int ct_handle_response(struct
>>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>>> break;
>>>> }
>>>> if (!found) {
>>>> - CT_ERROR(ct, "Unsolicited response (fence %u)\n", fence);
>>>> - CT_ERROR(ct, "Could not find fence=%u, last_fence=%u\n", fence,
>>>> - ct->requests.last_fence);
>>>> + ct_err(ct, "Unsolicited response (fence %u)\n", fence);
>>>> + ct_err(ct, "Could not find fence=%u, last_fence=%u\n", fence,
>>>> + ct->requests.last_fence);
>>>> list_for_each_entry(req, &ct->requests.pending, link)
>>>> - CT_ERROR(ct, "request %u awaits response\n",
>>>> - req->fence);
>>>> + ct_err(ct, "request %u awaits response\n", req->fence);
>>>> err = -ENOKEY;
>>>> }
>>>> spin_unlock_irqrestore(&ct->requests.lock, flags);
>>>> @@ -998,7 +1006,7 @@ static int ct_process_request(struct
>>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>>> action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, hxg[0]);
>>>> len = hxg_len - GUC_HXG_MSG_MIN_LEN;
>>>> - CT_DEBUG(ct, "request %x %*ph\n", action, 4 * len, payload);
>>>> + ct_dbg(ct, "request %x %*ph\n", action, 4 * len, payload);
>>>> switch (action) {
>>>> case INTEL_GUC_ACTION_DEFAULT:
>>>> @@ -1016,9 +1024,6 @@ static int ct_process_request(struct
>>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>>> break;
>>>> case INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION:
>>>> ret = intel_guc_error_capture_process_msg(guc, payload, len);
>>>> - if (unlikely(ret))
>>>> - CT_ERROR(ct, "error capture notification failed %x %*ph\n",
>>>> - action, 4 * len, payload);
>>>> break;
>>>> case INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION:
>>>> ret = intel_guc_engine_failure_process_msg(guc, payload, len);
>>>> @@ -1028,11 +1033,11 @@ static int ct_process_request(struct
>>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>>> ret = 0;
>>>> break;
>>>> case INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED:
>>>> - CT_ERROR(ct, "Received GuC crash dump notification!\n");
>>>> + guc_err(guc, "notification: Crash dump!\n");
>>>> ret = 0;
>>>> break;
>>>> case INTEL_GUC_ACTION_NOTIFY_EXCEPTION:
>>>> - CT_ERROR(ct, "Received GuC exception notification!\n");
>>>> + guc_err(guc, "notification: Exception!\n");
>>>> ret = 0;
>>>> break;
>>>> default:
>>>> @@ -1041,8 +1046,7 @@ static int ct_process_request(struct
>>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>>> }
>>>> if (unlikely(ret)) {
>>>> - CT_ERROR(ct, "Failed to process request %04x (%pe)\n",
>>>> - action, ERR_PTR(ret));
>>>> + ct_err(ct, "Failed to process request %04x (%pe)\n", action,
>>>> ERR_PTR(ret));
>>>> return ret;
>>>> }
>>>> @@ -1070,8 +1074,8 @@ static bool
>>>> ct_process_incoming_requests(struct intel_guc_ct *ct)
>>>> err = ct_process_request(ct, request);
>>>> if (unlikely(err)) {
>>>> - CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
>>>> - ERR_PTR(err), 4 * request->size, request->msg);
>>>> + ct_err(ct, "Failed to process message (%pe) %*ph\n",
>>>> + ERR_PTR(err), 4 * request->size, request->msg);
>>>> ct_free_msg(request);
>>>> }
>>>> @@ -1149,8 +1153,8 @@ static int ct_handle_hxg(struct intel_guc_ct
>>>> *ct, struct ct_incoming_msg *msg)
>>>> if (unlikely(err)) {
>>>> failed:
>>>> - CT_ERROR(ct, "Failed to handle HXG message (%pe) %*ph\n",
>>>> - ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
>>>> + ct_err(ct, "Failed to handle HXG message (%pe) %*ph\n",
>>>> + ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
>>>> }
>>>> return err;
>>>> }
>>>> @@ -1166,8 +1170,8 @@ static void ct_handle_msg(struct intel_guc_ct
>>>> *ct, struct ct_incoming_msg *msg)
>>>> err = -EOPNOTSUPP;
>>>> if (unlikely(err)) {
>>>> - CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
>>>> - ERR_PTR(err), 4 * msg->size, msg->msg);
>>>> + ct_err(ct, "Failed to handle message (%pe) %*ph\n",
>>>> + ERR_PTR(err), 4 * msg->size, msg->msg);
>>>> ct_free_msg(msg);
>>>> }
>>>> }
>>>> @@ -1198,7 +1202,7 @@ static void ct_try_receive_message(struct
>>>> intel_guc_ct *ct)
>>>> {
>>>> int ret;
>>>> - if (GEM_WARN_ON(!ct->enabled))
>>>> + if (ct_WARN_ON(ct, !ct->enabled))
>>>> return;
>>>> ret = ct_receive(ct);
>>>> @@ -1220,7 +1224,7 @@ static void ct_receive_tasklet_func(struct
>>>> tasklet_struct *t)
>>>> void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
>>>> {
>>>> if (unlikely(!ct->enabled)) {
>>>> - WARN(1, "Unexpected GuC event received while CT disabled!\n");
>>>> + ct_warn(ct, "Unexpected event received while disabled!\n");
>>>> return;
>>>> }
>>>>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2022-12-01 0:41 ` John Harrison
@ 2022-12-01 11:56 ` Michal Wajdeczko
2022-12-01 12:01 ` Tvrtko Ursulin
0 siblings, 1 reply; 51+ messages in thread
From: Michal Wajdeczko @ 2022-12-01 11:56 UTC (permalink / raw)
To: John Harrison, Intel-GFX; +Cc: DRI-Devel
On 01.12.2022 01:41, John Harrison wrote:
> On 11/23/2022 12:45, Michal Wajdeczko wrote:
>> On 23.11.2022 02:25, John Harrison wrote:
>>> On 11/22/2022 09:54, Michal Wajdeczko wrote:
>>>> On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
>>>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>>>
>>>>> Re-work the existing GuC CT printers and extend as required to match
>>>>> the new wrapping scheme.
>>>>>
>>>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222
>>>>> +++++++++++-----------
>>>>> 1 file changed, 113 insertions(+), 109 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>> index 2b22065e87bf9..9d404fb377637 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>> @@ -18,31 +18,49 @@ static inline struct intel_guc *ct_to_guc(struct
>>>>> intel_guc_ct *ct)
>>>>> return container_of(ct, struct intel_guc, ct);
>>>>> }
>>>>> -static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
>>>>> -{
>>>>> - return guc_to_gt(ct_to_guc(ct));
>>>>> -}
>>>>> -
>>>>> static inline struct drm_i915_private *ct_to_i915(struct
>>>>> intel_guc_ct *ct)
>>>>> {
>>>>> - return ct_to_gt(ct)->i915;
>>>>> -}
>>>>> + struct intel_guc *guc = ct_to_guc(ct);
>>>>> + struct intel_gt *gt = guc_to_gt(guc);
>>>>> -static inline struct drm_device *ct_to_drm(struct intel_guc_ct
>>>>> *ct)
>>>>> -{
>>>>> - return &ct_to_i915(ct)->drm;
>>>>> + return gt->i915;
>>>>> }
>>>>> -#define CT_ERROR(_ct, _fmt, ...) \
>>>>> - drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>>>> +#define ct_err(_ct, _fmt, ...) \
>>>>> + guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>> +
>>>>> +#define ct_warn(_ct, _fmt, ...) \
>>>>> + guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>> +
>>>>> +#define ct_notice(_ct, _fmt, ...) \
>>>>> + guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>> +
>>>>> +#define ct_info(_ct, _fmt, ...) \
>>>>> + guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>> +
>>>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>>>> -#define CT_DEBUG(_ct, _fmt, ...) \
>>>>> - drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>>>> +#define ct_dbg(_ct, _fmt, ...) \
>>>>> + guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>> #else
>>>>> -#define CT_DEBUG(...) do { } while (0)
>>>>> +#define ct_dbg(...) do { } while (0)
>>>>> #endif
>>>>> -#define CT_PROBE_ERROR(_ct, _fmt, ...) \
>>>>> - i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
>>>>> +
>>>>> +#define ct_probe_error(_ct, _fmt, ...) \
>>>>> + do { \
>>>>> + if (i915_error_injected()) \
>>>>> + ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
>>>>> + else \
>>>>> + ct_err(_ct, _fmt, ##__VA_ARGS__); \
>>>>> + } while (0)
>>>> guc_probe_error ?
>>>>
>>>>> +
>>>>> +#define ct_WARN_ON(_ct, _condition) \
>>>>> + ct_WARN(_ct, _condition, "%s", "ct_WARN_ON("
>>>>> __stringify(_condition) ")")
>>>>> +
>>>>> +#define ct_WARN(_ct, _condition, _fmt, ...) \
>>>>> + guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
>>>>> +
>>>>> +#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
>>>>> + guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt,
>>>>> ##__VA_ARGS__)
>>>>> /**
>>>>> * DOC: CTB Blob
>>>>> @@ -170,7 +188,7 @@ static int ct_control_enable(struct intel_guc_ct
>>>>> *ct, bool enable)
>>>>> err = guc_action_control_ctb(ct_to_guc(ct), enable ?
>>>>> GUC_CTB_CONTROL_ENABLE :
>>>>> GUC_CTB_CONTROL_DISABLE);
>>>>> if (unlikely(err))
>>>>> - CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
>>>>> + ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
>>>>> str_enable_disable(enable), ERR_PTR(err));
>>>> btw, shouldn't we change all messages to start with lowercase ?
>>>>
>>>> was:
>>>> "CT0: Failed to control/%s CTB (%pe)"
>>>> is:
>>>> "GT0: GuC CT Failed to control/%s CTB (%pe)"
>>>>
>>>> unless we keep colon (as suggested by Tvrtko) as then:
>>>>
>>>> "GT0: GuC CT: Failed to control/%s CTB (%pe)"
>>> Blanket added the colon makes it messy when a string actually wants to
>>> start with the prefix. The rule I've been using is lower case word when
>>> the prefix was part of the string, upper case word when the prefix is
>> Hmm, I'm not sure that we should attempt to have such a flexible rule as
>> we shouldn't rely too much on actual format of the prefix as it could be
>> changed any time. All we should know about final log message is that it
>> _will_ properly identify the "GT" or "GuC" that this log is related to.
>>
>> So I would suggest to be just consistent and probably always start with
>> upper case, as that seems to be mostly used in kernel error logs, and
>> just make sure that any prefix will honor that (by including colon, or
>> braces), so this will always work like:
>>
>> "[drm] *ERROR* GT0: Failed to foo (-EIO)"
>> "[drm] *ERROR* GT0: GUC: Failed to foo (-EIO)"
>> "[drm] *ERROR* GT0: GUC: CT: Failed to foo (-EIO)"
>>
>> or
>>
>> "[drm] *ERROR* GT0: Failed to foo (-EIO)"
>> "[drm] *ERROR* GT0: [GUC] Failed to foo (-EIO)"
>> "[drm] *ERROR* GT0: [GUC] CT: Failed to foo (-EIO)"
>>
>> and even for:
>>
>> "[drm] *ERROR* GT(root) Failed to foo (-EIO)"
>> "[drm] *ERROR* GuC(media) Failed to foo (-EIO)"
>> "[drm] *ERROR* GT0 [GuC:CT] Failed to foo (-EIO)"
> All of which are hideous/complex/verbose/inconsistent. 'GT0: GUC: CT:'?
> Really? Or 'GT0: [GUC] CT:'? Why the random mix of separators? And how
> would you implement '[GUC:CT]' without having a CT definition that is
> entirely self contained and does chain on to the GuC level version?
you missed the point, as those were just examples of different possible
prefixes that one could define, to show that actual message shall not
make any assumption how such prefix will look like or how it will end
(like with or w/o colon, with "GuC" or "GT" tag or whatever)
>
> This is pointless bikeshedding. If you want to re-write every single
> debug print (yet again) and invent much more complicated macro
the opposite, I want clear understanding how messages should be written
to *avoid* rewriting them if (for some reason) we decide to change or
update the prefix in the future
> definitions then feel free to take over the patch set. If not can we
> just approve the v3 version and move on to doing some actual work?
if everyone is happy that there is inconsistency in use between gt_xxx
messages where we shall be using messages starting with upper case
(since prefix ends with colon) and guc/ct_xxx messages where we shall be
using lower case message (since there is a known prefix without colon,
either "GuC" or "CT") then I'll be also fine, but for now that bothers
me a little, hence asking for clarifications/agreement
and while for dbg level messages it doesn't matter, I assume we should
be consistent for err/warn/info messages (as those will eventually show
up to the end user) so let maintainers decide here what is expectation here
>
> John.
>
>
>>
>>
>>> just being added as a prefix. I originally just had the prefix as raw
>>> with no trailing space, so the individual print could decide to add a
>>> colon, a space, or whatever as appropriate. But that just makes for
>>> messy code with some files having every string look like ": Stuff
>>> happened" and other files have every string look like " failed to ...".
>>> The current version seems to be the most readable from the point of view
>>> of writing the code and of reading the dmesg results.
>>>
>>> And to be clear, the 'CT0' you have in your 'was' example only exists in
>>> the internal tree. It never made it to upstream. It is also just plain
>>> wrong. Each GT has two CTs - send and receive. So having 'CT1' meaning
>>> some random CT on GT1 (as opposed to the read channel on GT0, for
>>> example) was very confusing.
>> I don't think I was wrong, it might be you confusing CT with CTB.
>>
>> Note that we only support _single_ CT (Command Transport) and this
>> single CT includes _pair_ of CTBs (Command Transport Buffers).
>>
>> And logs/macros are CT oriented, not CTB.
> The GuC spec does not make any distinction. In fact, there is no CT in
but "CT" concept is already there, we do have intel_guc_ct, right?
https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h#L22
https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h#L56
> the spec. There is just CTB. So at best it is ambiguous as to what CT0 /
> CT1 refers to.
>
>>
>> Regarding those my internal changes that were printing "CT%u": they were
>> added exactly for the same reason as your series: to know which GT
>> traffic we are tracing. And were done locally on CT level only as there
>> was no helpers that would automatically append "GT%u" prefix - helpers
>> that you're defining right now ;)
>>
>> Michal
>>
>>> John.
>>>
>>>
>>>> Michal
>>>>
>>>>> return err;
>>>>> @@ -201,7 +219,7 @@ static int ct_register_buffer(struct intel_guc_ct
>>>>> *ct, bool send,
>>>>> size);
>>>>> if (unlikely(err))
>>>>> failed:
>>>>> - CT_PROBE_ERROR(ct, "Failed to register %s buffer (%pe)\n",
>>>>> + ct_probe_error(ct, "Failed to register %s buffer (%pe)\n",
>>>>> send ? "SEND" : "RECV", ERR_PTR(err));
>>>>> return err;
>>>>> @@ -235,21 +253,21 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>>>>> blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE +
>>>>> CTB_G2H_BUFFER_SIZE;
>>>>> err = intel_guc_allocate_and_map_vma(guc, blob_size, &ct->vma,
>>>>> &blob);
>>>>> if (unlikely(err)) {
>>>>> - CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data
>>>>> (%pe)\n",
>>>>> + ct_probe_error(ct, "Failed to allocate %u for CTB data
>>>>> (%pe)\n",
>>>>> blob_size, ERR_PTR(err));
>>>>> return err;
>>>>> }
>>>>> - CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc,
>>>>> ct->vma), blob_size);
>>>>> + ct_dbg(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc,
>>>>> ct->vma), blob_size);
>>>>> /* store pointers to desc and cmds for send ctb */
>>>>> desc = blob;
>>>>> cmds = blob + 2 * CTB_DESC_SIZE;
>>>>> cmds_size = CTB_H2G_BUFFER_SIZE;
>>>>> resv_space = 0;
>>>>> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
>>>>> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>>>>> - resv_space);
>>>>> + ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
>>>>> + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>>>>> + resv_space);
>>>>> guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size,
>>>>> resv_space);
>>>>> @@ -258,9 +276,9 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>>>>> cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
>>>>> cmds_size = CTB_G2H_BUFFER_SIZE;
>>>>> resv_space = G2H_ROOM_BUFFER_SIZE;
>>>>> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
>>>>> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>>>>> - resv_space);
>>>>> + ct_dbg(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv",
>>>>> + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
>>>>> + resv_space);
>>>>> guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size,
>>>>> resv_space);
>>>>> @@ -338,7 +356,7 @@ int intel_guc_ct_enable(struct intel_guc_ct
>>>>> *ct)
>>>>> return 0;
>>>>> err_out:
>>>>> - CT_PROBE_ERROR(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
>>>>> + ct_probe_error(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
>>>>> return err;
>>>>> }
>>>>> @@ -387,14 +405,12 @@ static int ct_write(struct intel_guc_ct *ct,
>>>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>>>> if (unlikely(tail != READ_ONCE(desc->tail))) {
>>>>> - CT_ERROR(ct, "Tail was modified %u != %u\n",
>>>>> - desc->tail, tail);
>>>>> + ct_err(ct, "Tail was modified %u != %u\n", desc->tail, tail);
>>>>> desc->status |= GUC_CTB_STATUS_MISMATCH;
>>>>> goto corrupted;
>>>>> }
>>>>> if (unlikely(READ_ONCE(desc->head) >= size)) {
>>>>> - CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
>>>>> - desc->head, size);
>>>>> + ct_err(ct, "Invalid head offset %u >= %u)\n", desc->head,
>>>>> size);
>>>>> desc->status |= GUC_CTB_STATUS_OVERFLOW;
>>>>> goto corrupted;
>>>>> }
>>>>> @@ -415,8 +431,8 @@ static int ct_write(struct intel_guc_ct *ct,
>>>>> FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |
>>>>> GUC_HXG_EVENT_MSG_0_DATA0, action[0]);
>>>>> - CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
>>>>> - tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>>>>> + ct_dbg(ct, "writing (tail %u) %*ph %*ph %*ph\n",
>>>>> + tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]);
>>>>> cmds[tail] = header;
>>>>> tail = (tail + 1) % size;
>>>>> @@ -447,8 +463,8 @@ static int ct_write(struct intel_guc_ct *ct,
>>>>> return 0;
>>>>> corrupted:
>>>>> - CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>>>>> - desc->head, desc->tail, desc->status);
>>>>> + ct_err(ct, "Corrupted descriptor on write head=%u tail=%u
>>>>> status=%#x\n",
>>>>> + desc->head, desc->tail, desc->status);
>>>>> ctb->broken = true;
>>>>> return -EPIPE;
>>>>> }
>>>>> @@ -507,17 +523,14 @@ static inline bool ct_deadlocked(struct
>>>>> intel_guc_ct *ct)
>>>>> struct guc_ct_buffer_desc *send = ct->ctbs.send.desc;
>>>>> struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc;
>>>>> - CT_ERROR(ct, "Communication stalled for %lld ms, desc
>>>>> status=%#x,%#x\n",
>>>>> - ktime_ms_delta(ktime_get(), ct->stall_time),
>>>>> - send->status, recv->status);
>>>>> - CT_ERROR(ct, "H2G Space: %u (Bytes)\n",
>>>>> - atomic_read(&ct->ctbs.send.space) * 4);
>>>>> - CT_ERROR(ct, "Head: %u (Dwords)\n",
>>>>> ct->ctbs.send.desc->head);
>>>>> - CT_ERROR(ct, "Tail: %u (Dwords)\n",
>>>>> ct->ctbs.send.desc->tail);
>>>>> - CT_ERROR(ct, "G2H Space: %u (Bytes)\n",
>>>>> - atomic_read(&ct->ctbs.recv.space) * 4);
>>>>> - CT_ERROR(ct, "Head: %u\n (Dwords)",
>>>>> ct->ctbs.recv.desc->head);
>>>>> - CT_ERROR(ct, "Tail: %u\n (Dwords)",
>>>>> ct->ctbs.recv.desc->tail);
>>>>> + ct_err(ct, "Communication stalled for %lld ms, desc
>>>>> status=%#x,%#x\n",
>>>>> + ktime_ms_delta(ktime_get(), ct->stall_time),
>>>>> send->status, recv->status);
>>>>> + ct_err(ct, "H2G Space: %u (Bytes)\n",
>>>>> atomic_read(&ct->ctbs.send.space) * 4);
>>>>> + ct_err(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head);
>>>>> + ct_err(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail);
>>>>> + ct_err(ct, "G2H Space: %u (Bytes)\n",
>>>>> atomic_read(&ct->ctbs.recv.space) * 4);
>>>>> + ct_err(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
>>>>> + ct_err(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
>>>>> ct->ctbs.send.broken = true;
>>>>> }
>>>>> @@ -563,8 +576,7 @@ static inline bool h2g_has_room(struct
>>>>> intel_guc_ct *ct, u32 len_dw)
>>>>> head = READ_ONCE(desc->head);
>>>>> if (unlikely(head > ctb->size)) {
>>>>> - CT_ERROR(ct, "Invalid head offset %u >= %u)\n",
>>>>> - head, ctb->size);
>>>>> + ct_err(ct, "Invalid head offset %u >= %u)\n", head,
>>>>> ctb->size);
>>>>> desc->status |= GUC_CTB_STATUS_OVERFLOW;
>>>>> ctb->broken = true;
>>>>> return false;
>>>>> @@ -715,17 +727,17 @@ static int ct_send(struct intel_guc_ct *ct,
>>>>> /* wait_for_ct_request_update returns -ENODEV on
>>>>> reset/suspend in progress.
>>>>> * In this case, output is debug rather than error info
>>>>> */
>>>>> - CT_DEBUG(ct, "Request %#x (fence %u) cancelled as CTB is
>>>>> disabled\n",
>>>>> - action[0], request.fence);
>>>>> + ct_dbg(ct, "Request %#x (fence %u) cancelled as CTB is
>>>>> disabled\n",
>>>>> + action[0], request.fence);
>>>>> else
>>>>> - CT_ERROR(ct, "No response for request %#x (fence %u)\n",
>>>>> - action[0], request.fence);
>>>>> + ct_err(ct, "No response for request %#x (fence %u)\n",
>>>>> + action[0], request.fence);
>>>>> goto unlink;
>>>>> }
>>>>> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, *status) ==
>>>>> GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
>>>>> - CT_DEBUG(ct, "retrying request %#x (%u)\n", *action,
>>>>> - FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
>>>>> + ct_dbg(ct, "retrying request %#x (%u)\n", *action,
>>>>> + FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status));
>>>>> send_again = true;
>>>>> goto unlink;
>>>>> }
>>>>> @@ -737,12 +749,12 @@ static int ct_send(struct intel_guc_ct *ct,
>>>>> if (response_buf) {
>>>>> /* There shall be no data in the status */
>>>>> - WARN_ON(FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0,
>>>>> request.status));
>>>>> + ct_WARN_ON(ct, FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0,
>>>>> request.status));
>>>>> /* Return actual response len */
>>>>> err = request.response_len;
>>>>> } else {
>>>>> /* There shall be no response payload */
>>>>> - WARN_ON(request.response_len);
>>>>> + ct_WARN_ON(ct, request.response_len);
>>>>> /* Return data decoded from the status dword */
>>>>> err = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, *status);
>>>>> }
>>>>> @@ -771,7 +783,7 @@ int intel_guc_ct_send(struct intel_guc_ct *ct,
>>>>> const u32 *action, u32 len,
>>>>> struct intel_guc *guc = ct_to_guc(ct);
>>>>> struct intel_uc *uc = container_of(guc, struct intel_uc,
>>>>> guc);
>>>>> - WARN(!uc->reset_in_progress, "Unexpected send:
>>>>> action=%#x\n", *action);
>>>>> + ct_WARN(ct, !uc->reset_in_progress, "Unexpected send:
>>>>> action=%#x\n", *action);
>>>>> return -ENODEV;
>>>>> }
>>>>> @@ -784,11 +796,11 @@ int intel_guc_ct_send(struct intel_guc_ct
>>>>> *ct, const u32 *action, u32 len,
>>>>> ret = ct_send(ct, action, len, response_buf, response_buf_size,
>>>>> &status);
>>>>> if (unlikely(ret < 0)) {
>>>>> if (ret != -ENODEV)
>>>>> - CT_ERROR(ct, "Sending action %#x failed (%pe)
>>>>> status=%#X\n",
>>>>> - action[0], ERR_PTR(ret), status);
>>>>> + ct_err(ct, "sending action %#x failed (%pe)
>>>>> status=%#X\n",
>>>>> + action[0], ERR_PTR(ret), status);
>>>>> } else if (unlikely(ret)) {
>>>>> - CT_DEBUG(ct, "send action %#x returned %d (%#x)\n",
>>>>> - action[0], ret, ret);
>>>>> + ct_dbg(ct, "send action %#x returned %d (%#x)\n",
>>>>> + action[0], ret, ret);
>>>>> }
>>>>> return ret;
>>>>> @@ -838,7 +850,7 @@ static int ct_read(struct intel_guc_ct *ct,
>>>>> struct ct_incoming_msg **msg)
>>>>> * contexts/engines being reset. But should never
>>>>> happen as
>>>>> * no contexts should be active when CLIENT_RESET is
>>>>> sent.
>>>>> */
>>>>> - CT_ERROR(ct, "Unexpected G2H after GuC has stopped!\n");
>>>>> + ct_err(ct, "Unexpected G2H after GuC has stopped!\n");
>>>>> status &= ~GUC_CTB_STATUS_UNUSED;
>>>>> }
>>>>> @@ -850,15 +862,13 @@ static int ct_read(struct intel_guc_ct *ct,
>>>>> struct ct_incoming_msg **msg)
>>>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>>>> if (unlikely(head != READ_ONCE(desc->head))) {
>>>>> - CT_ERROR(ct, "Head was modified %u != %u\n",
>>>>> - desc->head, head);
>>>>> + ct_err(ct, "Head was modified %u != %u\n", desc->head, head);
>>>>> desc->status |= GUC_CTB_STATUS_MISMATCH;
>>>>> goto corrupted;
>>>>> }
>>>>> #endif
>>>>> if (unlikely(tail >= size)) {
>>>>> - CT_ERROR(ct, "Invalid tail offset %u >= %u)\n",
>>>>> - tail, size);
>>>>> + ct_err(ct, "Invalid tail offset %u >= %u)\n", tail, size);
>>>>> desc->status |= GUC_CTB_STATUS_OVERFLOW;
>>>>> goto corrupted;
>>>>> }
>>>>> @@ -873,7 +883,7 @@ static int ct_read(struct intel_guc_ct *ct,
>>>>> struct ct_incoming_msg **msg)
>>>>> /* beware of buffer wrap case */
>>>>> if (unlikely(available < 0))
>>>>> available += size;
>>>>> - CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail,
>>>>> size);
>>>>> + ct_dbg(ct, "read available %d (%u:%u:%u)\n", available, head,
>>>>> tail, size);
>>>>> GEM_BUG_ON(available < 0);
>>>>> header = cmds[head];
>>>>> @@ -882,24 +892,24 @@ static int ct_read(struct intel_guc_ct *ct,
>>>>> struct ct_incoming_msg **msg)
>>>>> /* message len with header */
>>>>> len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, header) +
>>>>> GUC_CTB_MSG_MIN_LEN;
>>>>> if (unlikely(len > (u32)available)) {
>>>>> - CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n",
>>>>> - 4, &header,
>>>>> - 4 * (head + available - 1 > size ?
>>>>> - size - head : available - 1), &cmds[head],
>>>>> - 4 * (head + available - 1 > size ?
>>>>> - available - 1 - size + head : 0), &cmds[0]);
>>>>> + ct_err(ct, "Incomplete message %*ph %*ph %*ph\n",
>>>>> + 4, &header,
>>>>> + 4 * (head + available - 1 > size ?
>>>>> + size - head : available - 1), &cmds[head],
>>>>> + 4 * (head + available - 1 > size ?
>>>>> + available - 1 - size + head : 0), &cmds[0]);
>>>>> desc->status |= GUC_CTB_STATUS_UNDERFLOW;
>>>>> goto corrupted;
>>>>> }
>>>>> *msg = ct_alloc_msg(len);
>>>>> if (!*msg) {
>>>>> - CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n",
>>>>> - 4, &header,
>>>>> - 4 * (head + available - 1 > size ?
>>>>> - size - head : available - 1), &cmds[head],
>>>>> - 4 * (head + available - 1 > size ?
>>>>> - available - 1 - size + head : 0), &cmds[0]);
>>>>> + ct_err(ct, "No memory for message %*ph %*ph %*ph\n",
>>>>> + 4, &header,
>>>>> + 4 * (head + available - 1 > size ?
>>>>> + size - head : available - 1), &cmds[head],
>>>>> + 4 * (head + available - 1 > size ?
>>>>> + available - 1 - size + head : 0), &cmds[0]);
>>>>> return available;
>>>>> }
>>>>> @@ -909,7 +919,7 @@ static int ct_read(struct intel_guc_ct *ct,
>>>>> struct ct_incoming_msg **msg)
>>>>> (*msg)->msg[i] = cmds[head];
>>>>> head = (head + 1) % size;
>>>>> }
>>>>> - CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
>>>>> + ct_dbg(ct, "received %*ph\n", 4 * len, (*msg)->msg);
>>>>> /* update local copies */
>>>>> ctb->head = head;
>>>>> @@ -920,8 +930,8 @@ static int ct_read(struct intel_guc_ct *ct,
>>>>> struct ct_incoming_msg **msg)
>>>>> return available - len;
>>>>> corrupted:
>>>>> - CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>>>>> - desc->head, desc->tail, desc->status);
>>>>> + ct_err(ct, "Corrupted descriptor on read head=%u tail=%u
>>>>> status=%#x\n",
>>>>> + desc->head, desc->tail, desc->status);
>>>>> ctb->broken = true;
>>>>> return -EPIPE;
>>>>> }
>>>>> @@ -944,18 +954,17 @@ static int ct_handle_response(struct
>>>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>>>> FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) !=
>>>>> GUC_HXG_TYPE_NO_RESPONSE_RETRY &&
>>>>> FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) !=
>>>>> GUC_HXG_TYPE_RESPONSE_FAILURE);
>>>>> - CT_DEBUG(ct, "response fence %u status %#x\n", fence, hxg[0]);
>>>>> + ct_dbg(ct, "response fence %u status %#x\n", fence, hxg[0]);
>>>>> spin_lock_irqsave(&ct->requests.lock, flags);
>>>>> list_for_each_entry(req, &ct->requests.pending, link) {
>>>>> if (unlikely(fence != req->fence)) {
>>>>> - CT_DEBUG(ct, "request %u awaits response\n",
>>>>> - req->fence);
>>>>> + ct_dbg(ct, "request %u awaits response\n", req->fence);
>>>>> continue;
>>>>> }
>>>>> if (unlikely(datalen > req->response_len)) {
>>>>> - CT_ERROR(ct, "Response %u too long (datalen %u > %u)\n",
>>>>> - req->fence, datalen, req->response_len);
>>>>> + ct_err(ct, "response %u too long (datalen %u > %u)\n",
>>>>> + req->fence, datalen, req->response_len);
>>>>> datalen = min(datalen, req->response_len);
>>>>> err = -EMSGSIZE;
>>>>> }
>>>>> @@ -967,12 +976,11 @@ static int ct_handle_response(struct
>>>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>>>> break;
>>>>> }
>>>>> if (!found) {
>>>>> - CT_ERROR(ct, "Unsolicited response (fence %u)\n", fence);
>>>>> - CT_ERROR(ct, "Could not find fence=%u, last_fence=%u\n",
>>>>> fence,
>>>>> - ct->requests.last_fence);
>>>>> + ct_err(ct, "Unsolicited response (fence %u)\n", fence);
>>>>> + ct_err(ct, "Could not find fence=%u, last_fence=%u\n", fence,
>>>>> + ct->requests.last_fence);
>>>>> list_for_each_entry(req, &ct->requests.pending, link)
>>>>> - CT_ERROR(ct, "request %u awaits response\n",
>>>>> - req->fence);
>>>>> + ct_err(ct, "request %u awaits response\n", req->fence);
>>>>> err = -ENOKEY;
>>>>> }
>>>>> spin_unlock_irqrestore(&ct->requests.lock, flags);
>>>>> @@ -998,7 +1006,7 @@ static int ct_process_request(struct
>>>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>>>> action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, hxg[0]);
>>>>> len = hxg_len - GUC_HXG_MSG_MIN_LEN;
>>>>> - CT_DEBUG(ct, "request %x %*ph\n", action, 4 * len, payload);
>>>>> + ct_dbg(ct, "request %x %*ph\n", action, 4 * len, payload);
>>>>> switch (action) {
>>>>> case INTEL_GUC_ACTION_DEFAULT:
>>>>> @@ -1016,9 +1024,6 @@ static int ct_process_request(struct
>>>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>>>> break;
>>>>> case INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION:
>>>>> ret = intel_guc_error_capture_process_msg(guc, payload,
>>>>> len);
>>>>> - if (unlikely(ret))
>>>>> - CT_ERROR(ct, "error capture notification failed %x
>>>>> %*ph\n",
>>>>> - action, 4 * len, payload);
>>>>> break;
>>>>> case INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION:
>>>>> ret = intel_guc_engine_failure_process_msg(guc, payload,
>>>>> len);
>>>>> @@ -1028,11 +1033,11 @@ static int ct_process_request(struct
>>>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>>>> ret = 0;
>>>>> break;
>>>>> case INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED:
>>>>> - CT_ERROR(ct, "Received GuC crash dump notification!\n");
>>>>> + guc_err(guc, "notification: Crash dump!\n");
>>>>> ret = 0;
>>>>> break;
>>>>> case INTEL_GUC_ACTION_NOTIFY_EXCEPTION:
>>>>> - CT_ERROR(ct, "Received GuC exception notification!\n");
>>>>> + guc_err(guc, "notification: Exception!\n");
>>>>> ret = 0;
>>>>> break;
>>>>> default:
>>>>> @@ -1041,8 +1046,7 @@ static int ct_process_request(struct
>>>>> intel_guc_ct *ct, struct ct_incoming_msg *r
>>>>> }
>>>>> if (unlikely(ret)) {
>>>>> - CT_ERROR(ct, "Failed to process request %04x (%pe)\n",
>>>>> - action, ERR_PTR(ret));
>>>>> + ct_err(ct, "Failed to process request %04x (%pe)\n", action,
>>>>> ERR_PTR(ret));
>>>>> return ret;
>>>>> }
>>>>> @@ -1070,8 +1074,8 @@ static bool
>>>>> ct_process_incoming_requests(struct intel_guc_ct *ct)
>>>>> err = ct_process_request(ct, request);
>>>>> if (unlikely(err)) {
>>>>> - CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
>>>>> - ERR_PTR(err), 4 * request->size, request->msg);
>>>>> + ct_err(ct, "Failed to process message (%pe) %*ph\n",
>>>>> + ERR_PTR(err), 4 * request->size, request->msg);
>>>>> ct_free_msg(request);
>>>>> }
>>>>> @@ -1149,8 +1153,8 @@ static int ct_handle_hxg(struct intel_guc_ct
>>>>> *ct, struct ct_incoming_msg *msg)
>>>>> if (unlikely(err)) {
>>>>> failed:
>>>>> - CT_ERROR(ct, "Failed to handle HXG message (%pe) %*ph\n",
>>>>> - ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
>>>>> + ct_err(ct, "Failed to handle HXG message (%pe) %*ph\n",
>>>>> + ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg);
>>>>> }
>>>>> return err;
>>>>> }
>>>>> @@ -1166,8 +1170,8 @@ static void ct_handle_msg(struct intel_guc_ct
>>>>> *ct, struct ct_incoming_msg *msg)
>>>>> err = -EOPNOTSUPP;
>>>>> if (unlikely(err)) {
>>>>> - CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
>>>>> - ERR_PTR(err), 4 * msg->size, msg->msg);
>>>>> + ct_err(ct, "Failed to handle message (%pe) %*ph\n",
>>>>> + ERR_PTR(err), 4 * msg->size, msg->msg);
>>>>> ct_free_msg(msg);
>>>>> }
>>>>> }
>>>>> @@ -1198,7 +1202,7 @@ static void ct_try_receive_message(struct
>>>>> intel_guc_ct *ct)
>>>>> {
>>>>> int ret;
>>>>> - if (GEM_WARN_ON(!ct->enabled))
>>>>> + if (ct_WARN_ON(ct, !ct->enabled))
>>>>> return;
>>>>> ret = ct_receive(ct);
>>>>> @@ -1220,7 +1224,7 @@ static void ct_receive_tasklet_func(struct
>>>>> tasklet_struct *t)
>>>>> void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
>>>>> {
>>>>> if (unlikely(!ct->enabled)) {
>>>>> - WARN(1, "Unexpected GuC event received while CT
>>>>> disabled!\n");
>>>>> + ct_warn(ct, "Unexpected event received while disabled!\n");
>>>>> return;
>>>>> }
>>>>>
>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2022-12-01 11:56 ` Michal Wajdeczko
@ 2022-12-01 12:01 ` Tvrtko Ursulin
2022-12-02 20:14 ` John Harrison
0 siblings, 1 reply; 51+ messages in thread
From: Tvrtko Ursulin @ 2022-12-01 12:01 UTC (permalink / raw)
To: Michal Wajdeczko, John Harrison, Intel-GFX; +Cc: DRI-Devel
On 01/12/2022 11:56, Michal Wajdeczko wrote:
> On 01.12.2022 01:41, John Harrison wrote:
>> On 11/23/2022 12:45, Michal Wajdeczko wrote:
>>> On 23.11.2022 02:25, John Harrison wrote:
>>>> On 11/22/2022 09:54, Michal Wajdeczko wrote:
>>>>> On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
>>>>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>>>>
>>>>>> Re-work the existing GuC CT printers and extend as required to match
>>>>>> the new wrapping scheme.
>>>>>>
>>>>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>>>>> ---
>>>>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222
>>>>>> +++++++++++-----------
>>>>>> 1 file changed, 113 insertions(+), 109 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>>> index 2b22065e87bf9..9d404fb377637 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>>> @@ -18,31 +18,49 @@ static inline struct intel_guc *ct_to_guc(struct
>>>>>> intel_guc_ct *ct)
>>>>>> return container_of(ct, struct intel_guc, ct);
>>>>>> }
>>>>>> -static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
>>>>>> -{
>>>>>> - return guc_to_gt(ct_to_guc(ct));
>>>>>> -}
>>>>>> -
>>>>>> static inline struct drm_i915_private *ct_to_i915(struct
>>>>>> intel_guc_ct *ct)
>>>>>> {
>>>>>> - return ct_to_gt(ct)->i915;
>>>>>> -}
>>>>>> + struct intel_guc *guc = ct_to_guc(ct);
>>>>>> + struct intel_gt *gt = guc_to_gt(guc);
>>>>>> -static inline struct drm_device *ct_to_drm(struct intel_guc_ct
>>>>>> *ct)
>>>>>> -{
>>>>>> - return &ct_to_i915(ct)->drm;
>>>>>> + return gt->i915;
>>>>>> }
>>>>>> -#define CT_ERROR(_ct, _fmt, ...) \
>>>>>> - drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>>>>> +#define ct_err(_ct, _fmt, ...) \
>>>>>> + guc_err(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>>> +
>>>>>> +#define ct_warn(_ct, _fmt, ...) \
>>>>>> + guc_warn(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>>> +
>>>>>> +#define ct_notice(_ct, _fmt, ...) \
>>>>>> + guc_notice(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>>> +
>>>>>> +#define ct_info(_ct, _fmt, ...) \
>>>>>> + guc_info(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>>> +
>>>>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>>>>> -#define CT_DEBUG(_ct, _fmt, ...) \
>>>>>> - drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>>>>> +#define ct_dbg(_ct, _fmt, ...) \
>>>>>> + guc_dbg(ct_to_guc(_ct), "CT " _fmt, ##__VA_ARGS__)
>>>>>> #else
>>>>>> -#define CT_DEBUG(...) do { } while (0)
>>>>>> +#define ct_dbg(...) do { } while (0)
>>>>>> #endif
>>>>>> -#define CT_PROBE_ERROR(_ct, _fmt, ...) \
>>>>>> - i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
>>>>>> +
>>>>>> +#define ct_probe_error(_ct, _fmt, ...) \
>>>>>> + do { \
>>>>>> + if (i915_error_injected()) \
>>>>>> + ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
>>>>>> + else \
>>>>>> + ct_err(_ct, _fmt, ##__VA_ARGS__); \
>>>>>> + } while (0)
>>>>> guc_probe_error ?
>>>>>
>>>>>> +
>>>>>> +#define ct_WARN_ON(_ct, _condition) \
>>>>>> + ct_WARN(_ct, _condition, "%s", "ct_WARN_ON("
>>>>>> __stringify(_condition) ")")
>>>>>> +
>>>>>> +#define ct_WARN(_ct, _condition, _fmt, ...) \
>>>>>> + guc_WARN(ct_to_guc(_ct), _condition, "CT " _fmt, ##__VA_ARGS__)
>>>>>> +
>>>>>> +#define ct_WARN_ONCE(_ct, _condition, _fmt, ...) \
>>>>>> + guc_WARN_ONCE(ct_to_guc(_ct), _condition, "CT " _fmt,
>>>>>> ##__VA_ARGS__)
>>>>>> /**
>>>>>> * DOC: CTB Blob
>>>>>> @@ -170,7 +188,7 @@ static int ct_control_enable(struct intel_guc_ct
>>>>>> *ct, bool enable)
>>>>>> err = guc_action_control_ctb(ct_to_guc(ct), enable ?
>>>>>> GUC_CTB_CONTROL_ENABLE :
>>>>>> GUC_CTB_CONTROL_DISABLE);
>>>>>> if (unlikely(err))
>>>>>> - CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
>>>>>> + ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
>>>>>> str_enable_disable(enable), ERR_PTR(err));
>>>>> btw, shouldn't we change all messages to start with lowercase ?
>>>>>
>>>>> was:
>>>>> "CT0: Failed to control/%s CTB (%pe)"
>>>>> is:
>>>>> "GT0: GuC CT Failed to control/%s CTB (%pe)"
>>>>>
>>>>> unless we keep colon (as suggested by Tvrtko) as then:
>>>>>
>>>>> "GT0: GuC CT: Failed to control/%s CTB (%pe)"
>>>> Blanket added the colon makes it messy when a string actually wants to
>>>> start with the prefix. The rule I've been using is lower case word when
>>>> the prefix was part of the string, upper case word when the prefix is
>>> Hmm, I'm not sure that we should attempt to have such a flexible rule as
>>> we shouldn't rely too much on actual format of the prefix as it could be
>>> changed any time. All we should know about final log message is that it
>>> _will_ properly identify the "GT" or "GuC" that this log is related to.
>>>
>>> So I would suggest to be just consistent and probably always start with
>>> upper case, as that seems to be mostly used in kernel error logs, and
>>> just make sure that any prefix will honor that (by including colon, or
>>> braces), so this will always work like:
>>>
>>> "[drm] *ERROR* GT0: Failed to foo (-EIO)"
>>> "[drm] *ERROR* GT0: GUC: Failed to foo (-EIO)"
>>> "[drm] *ERROR* GT0: GUC: CT: Failed to foo (-EIO)"
>>>
>>> or
>>>
>>> "[drm] *ERROR* GT0: Failed to foo (-EIO)"
>>> "[drm] *ERROR* GT0: [GUC] Failed to foo (-EIO)"
>>> "[drm] *ERROR* GT0: [GUC] CT: Failed to foo (-EIO)"
>>>
>>> and even for:
>>>
>>> "[drm] *ERROR* GT(root) Failed to foo (-EIO)"
>>> "[drm] *ERROR* GuC(media) Failed to foo (-EIO)"
>>> "[drm] *ERROR* GT0 [GuC:CT] Failed to foo (-EIO)"
>> All of which are hideous/complex/verbose/inconsistent. 'GT0: GUC: CT:'?
>> Really? Or 'GT0: [GUC] CT:'? Why the random mix of separators? And how
>> would you implement '[GUC:CT]' without having a CT definition that is
>> entirely self contained and does chain on to the GuC level version?
>
> you missed the point, as those were just examples of different possible
> prefixes that one could define, to show that actual message shall not
> make any assumption how such prefix will look like or how it will end
> (like with or w/o colon, with "GuC" or "GT" tag or whatever)
>
>>
>> This is pointless bikeshedding. If you want to re-write every single
>> debug print (yet again) and invent much more complicated macro
>
> the opposite, I want clear understanding how messages should be written
> to *avoid* rewriting them if (for some reason) we decide to change or
> update the prefix in the future
>
>> definitions then feel free to take over the patch set. If not can we
>> just approve the v3 version and move on to doing some actual work?
>
> if everyone is happy that there is inconsistency in use between gt_xxx
> messages where we shall be using messages starting with upper case
> (since prefix ends with colon) and guc/ct_xxx messages where we shall be
> using lower case message (since there is a known prefix without colon,
> either "GuC" or "CT") then I'll be also fine, but for now that bothers
> me a little, hence asking for clarifications/agreement
>
> and while for dbg level messages it doesn't matter, I assume we should
> be consistent for err/warn/info messages (as those will eventually show
> up to the end user) so let maintainers decide here what is expectation here
Could we have some examples pasted here, of the end result of this
series, for all message "categories" (origins, macros, whatever)?
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2022-12-01 12:01 ` Tvrtko Ursulin
@ 2022-12-02 20:14 ` John Harrison
2022-12-05 13:16 ` Tvrtko Ursulin
0 siblings, 1 reply; 51+ messages in thread
From: John Harrison @ 2022-12-02 20:14 UTC (permalink / raw)
To: Tvrtko Ursulin, Michal Wajdeczko, Intel-GFX; +Cc: DRI-Devel
On 12/1/2022 04:01, Tvrtko Ursulin wrote:
> On 01/12/2022 11:56, Michal Wajdeczko wrote:
>> On 01.12.2022 01:41, John Harrison wrote:
>>> On 11/23/2022 12:45, Michal Wajdeczko wrote:
>>>> On 23.11.2022 02:25, John Harrison wrote:
>>>>> On 11/22/2022 09:54, Michal Wajdeczko wrote:
>>>>>> On 18.11.2022 02:58, John.C.Harrison@Intel.com wrote:
>>>>>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>>>>>
>>>>>>> Re-work the existing GuC CT printers and extend as required to
>>>>>>> match
>>>>>>> the new wrapping scheme.
>>>>>>>
>>>>>>>
>>>>>>> [snip]...
>>>>>>>
>>>>>>> /**
>>>>>>> * DOC: CTB Blob
>>>>>>> @@ -170,7 +188,7 @@ static int ct_control_enable(struct
>>>>>>> intel_guc_ct
>>>>>>> *ct, bool enable)
>>>>>>> err = guc_action_control_ctb(ct_to_guc(ct), enable ?
>>>>>>> GUC_CTB_CONTROL_ENABLE :
>>>>>>> GUC_CTB_CONTROL_DISABLE);
>>>>>>> if (unlikely(err))
>>>>>>> - CT_PROBE_ERROR(ct, "Failed to control/%s CTB (%pe)\n",
>>>>>>> + ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
>>>>>>> str_enable_disable(enable), ERR_PTR(err));
>>>>>> btw, shouldn't we change all messages to start with lowercase ?
>>>>>>
>>>>>> was:
>>>>>> "CT0: Failed to control/%s CTB (%pe)"
>>>>>> is:
>>>>>> "GT0: GuC CT Failed to control/%s CTB (%pe)"
>>>>>>
>>>>>> unless we keep colon (as suggested by Tvrtko) as then:
>>>>>>
>>>>>> "GT0: GuC CT: Failed to control/%s CTB (%pe)"
>>>>> Blanket added the colon makes it messy when a string actually
>>>>> wants to
>>>>> start with the prefix. The rule I've been using is lower case word
>>>>> when
>>>>> the prefix was part of the string, upper case word when the prefix is
>>>> Hmm, I'm not sure that we should attempt to have such a flexible
>>>> rule as
>>>> we shouldn't rely too much on actual format of the prefix as it
>>>> could be
>>>> changed any time. All we should know about final log message is
>>>> that it
>>>> _will_ properly identify the "GT" or "GuC" that this log is related
>>>> to.
>>>>
>>>> So I would suggest to be just consistent and probably always start
>>>> with
>>>> upper case, as that seems to be mostly used in kernel error logs, and
>>>> just make sure that any prefix will honor that (by including colon, or
>>>> braces), so this will always work like:
>>>>
>>>> "[drm] *ERROR* GT0: Failed to foo (-EIO)"
>>>> "[drm] *ERROR* GT0: GUC: Failed to foo (-EIO)"
>>>> "[drm] *ERROR* GT0: GUC: CT: Failed to foo (-EIO)"
>>>>
>>>> or
>>>>
>>>> "[drm] *ERROR* GT0: Failed to foo (-EIO)"
>>>> "[drm] *ERROR* GT0: [GUC] Failed to foo (-EIO)"
>>>> "[drm] *ERROR* GT0: [GUC] CT: Failed to foo (-EIO)"
>>>>
>>>> and even for:
>>>>
>>>> "[drm] *ERROR* GT(root) Failed to foo (-EIO)"
>>>> "[drm] *ERROR* GuC(media) Failed to foo (-EIO)"
>>>> "[drm] *ERROR* GT0 [GuC:CT] Failed to foo (-EIO)"
>>> All of which are hideous/complex/verbose/inconsistent. 'GT0: GUC: CT:'?
>>> Really? Or 'GT0: [GUC] CT:'? Why the random mix of separators? And how
>>> would you implement '[GUC:CT]' without having a CT definition that is
>>> entirely self contained and does chain on to the GuC level version?
>>
>> you missed the point, as those were just examples of different possible
>> prefixes that one could define, to show that actual message shall not
>> make any assumption how such prefix will look like or how it will end
>> (like with or w/o colon, with "GuC" or "GT" tag or whatever)
The point is that none of those are ever likely to happen so are
meaningless to prepare for.
>>
>>>
>>> This is pointless bikeshedding. If you want to re-write every single
>>> debug print (yet again) and invent much more complicated macro
>>
>> the opposite, I want clear understanding how messages should be written
>> to *avoid* rewriting them if (for some reason) we decide to change or
>> update the prefix in the future
You say that like there is any consistency or regulation at all on how
messages are currently written.
>>
>>> definitions then feel free to take over the patch set. If not can we
>>> just approve the v3 version and move on to doing some actual work?
>>
>> if everyone is happy that there is inconsistency in use between gt_xxx
>> messages where we shall be using messages starting with upper case
>> (since prefix ends with colon) and guc/ct_xxx messages where we shall be
>> using lower case message (since there is a known prefix without colon,
>> either "GuC" or "CT") then I'll be also fine, but for now that bothers
>> me a little, hence asking for clarifications/agreement
>>
I don't think anyone is happy with anything.
Personally, I don't like the idea of adding fixed prefixes for every
subsystem just for the sake of doing so. Having a wrapper that abstracts
out the messy structure mangling of getting from a 'ct' object back to a
'gt' object maybe has use. But with regards to fixed prefixes, all I
ever wanted was to add GT# (because that adds useful information that is
other completely lacking) and, ideally, a display prefix for all of the
display prints (because they completely swamp all other output in CI
dmesg logs, so being able to trivially filter them out would be
incredibly useful). Beyond that, it seems like adding work and forced
formatting just for the sake of it. If a print wants to say 'Error
received on CT read channel' then why should it be forced to be 'GuC CT
Error received on read channel' which is coded as 'Error received on
read channel' ? To me, that seems less clear both in dmesg and in code.
And for the record, I didn't want to add the GT thing as message
'prefix' either. I would rather have just extended the PCI address that
is printed by the dev level printer. But that would have been a much
more invasive change at many levels outside of i915. As in, "i915
0000:00:02.0: [drm]" -> "i915 0000:00:02.0:GT0 [drm]".
And here we are a month down the road and arguing over whether a three
level deep prefix should have a colon or braces around each level's
forced message prefix!? Meanwhile, it is still impossible to know which
GT produced a given error in a multi-GT system and the ability to filter
out display messages has been completely nacked for reasons I don't
understand at all before I even got to suggest it.
>> and while for dbg level messages it doesn't matter, I assume we should
>> be consistent for err/warn/info messages (as those will eventually show
>> up to the end user) so let maintainers decide here what is
>> expectation here
>
> Could we have some examples pasted here, of the end result of this
> series, for all message "categories" (origins, macros, whatever)?
GT initialisation:
gt_err(gt, "Failed to allocate scratch page\n");
i915 0000:00:02.0: [drm] GT0: Failed to allocate scratch page
G2H notification handler:
guc_err(guc, "notification: Invalid length %u for deregister done\n", len);
i915 0000:00:02.0: [drm] GT0: GuC notification: Invalid length 0 for
deregister done
CTB initialisation:
ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
str_enable_disable(enable), ERR_PTR(err));
i915 0000:00:02.0: [drm] GT0: GuC CT Failed to control/enable CTB (EINVAL)
Random meaningless (to me) message that is apparently a display thing:
drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling PORT
PLL B
I'm sure you can extrapolate to all other forms of dbg, notice, info,
etc. without me having to manually type each one out, given that they
are all identical.
Personally, I think the above should be just:
gt_err(gt, "Failed to allocate scratch page\n");
i915 0000:00:02.0: [drm] GT0: Failed to allocate scratch page
gt_err(guc_to_gt(guc), "G2H: Invalid length for deregister done: %u\n",
len);
i915 0000:00:02.0: [drm] GT0: G2H: Invalid length for deregister done: 0
gt_probe_error(ct_to_gt(ct), "Failed to %s CT %d buffer (%pe)\n",
str_enable_disable(enable), send ? "SEND" : "RECV", ERR_PTR(err));
i915 0000:00:02.0: [drm] GT0: Failed to enable CT SEND buffer (EINVAL)
drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915-KMS]] disabling
PORT PLL B
But presumably that requires finishing the plan of splitting out the
display code into a separate driver. So for now, something like this
would still be a massive improvement:
kms_dbg(dev_priv, "disabling %s\n", pll->info->name);
i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] KMS: disabling
PORT PLL B
John.
>
> Regards,
>
> Tvrtko
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2022-12-02 20:14 ` John Harrison
@ 2022-12-05 13:16 ` Tvrtko Ursulin
2022-12-05 18:44 ` Michal Wajdeczko
0 siblings, 1 reply; 51+ messages in thread
From: Tvrtko Ursulin @ 2022-12-05 13:16 UTC (permalink / raw)
To: John Harrison, Michal Wajdeczko, Intel-GFX; +Cc: DRI-Devel
On 02/12/2022 20:14, John Harrison wrote:
>>> and while for dbg level messages it doesn't matter, I assume we should
>>> be consistent for err/warn/info messages (as those will eventually show
>>> up to the end user) so let maintainers decide here what is
>>> expectation here
>>
>> Could we have some examples pasted here, of the end result of this
>> series, for all message "categories" (origins, macros, whatever)?
>
> GT initialisation:
> gt_err(gt, "Failed to allocate scratch page\n");
> i915 0000:00:02.0: [drm] GT0: Failed to allocate scratch page
>
> G2H notification handler:
> guc_err(guc, "notification: Invalid length %u for deregister done\n", len);
> i915 0000:00:02.0: [drm] GT0: GuC notification: Invalid length 0 for
> deregister done
I'm not liking the inconsistency between gt_err and guc_err where with latter callers either need to start the message with lower case because of the unstructured "GuC " prefix added. Which then reads bad if callers do guc_err(guc, "Error X happend").
Looks like Michal was pointing out the same thing, AFAIU at least when re-reading the thread now.
Why wouldn't this work:
guc_err(guc, "Invalid length %u for deregister done notification\n", len);
i915 0000:00:02.0: [drm] GT0: GuC: Invalid length 0 for deregister done notification
Or if the use case for adding custom prefixes is strong then maybe consider:
guc_err(guc, "notification", "Invalid length 0 for deregister done");
i915 0000:00:02.0: [drm] GT0: GuC notification: Invalid length 0 for deregister done
guc_err(guc, "", "Error X");
i915 0000:00:02.0: [drm] GT0: GuC: Error X
> CTB initialisation:
> ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
> str_enable_disable(enable), ERR_PTR(err));
> i915 0000:00:02.0: [drm] GT0: GuC CT Failed to control/enable CTB (EINVAL)
Okay same as above.
> Random meaningless (to me) message that is apparently a display thing:
> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling PORT
> PLL B
Plan is to not touch outside gt/.
> I'm sure you can extrapolate to all other forms of dbg, notice, info,
> etc. without me having to manually type each one out, given that they
> are all identical.
>
> Personally, I think the above should be just:
> gt_err(gt, "Failed to allocate scratch page\n");
> i915 0000:00:02.0: [drm] GT0: Failed to allocate scratch page
>
> gt_err(guc_to_gt(guc), "G2H: Invalid length for deregister done: %u\n",
> len);
> i915 0000:00:02.0: [drm] GT0: G2H: Invalid length for deregister done: 0
>
> gt_probe_error(ct_to_gt(ct), "Failed to %s CT %d buffer (%pe)\n",
> str_enable_disable(enable), send ? "SEND" : "RECV", ERR_PTR(err));
> i915 0000:00:02.0: [drm] GT0: Failed to enable CT SEND buffer (EINVAL)
We could but it seems we agreed some weeks ago to consolidate the existing CT_ERROR macros and such in this exercise. At least no objections were raised to that plan.
If now we want to go back on that, and if you want to have guc_to_gt(guc) in all gt/uc/ call sites that's fine by me, but please get some acks and consensus from people who work in that area. And under that option someone would also need to convert the CT code to new macros.
Regards,
Tvrtko
> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915-KMS]] disabling
> PORT PLL B
> But presumably that requires finishing the plan of splitting out the
> display code into a separate driver. So for now, something like this
> would still be a massive improvement:
> kms_dbg(dev_priv, "disabling %s\n", pll->info->name);
> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] KMS: disabling
> PORT PLL B
>
> John.
>
>>
>> Regards,
>>
>> Tvrtko
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2022-12-05 13:16 ` Tvrtko Ursulin
@ 2022-12-05 18:44 ` Michal Wajdeczko
2022-12-06 11:06 ` Tvrtko Ursulin
0 siblings, 1 reply; 51+ messages in thread
From: Michal Wajdeczko @ 2022-12-05 18:44 UTC (permalink / raw)
To: Tvrtko Ursulin, John Harrison, Intel-GFX; +Cc: DRI-Devel
On 05.12.2022 14:16, Tvrtko Ursulin wrote:
>
> On 02/12/2022 20:14, John Harrison wrote:
>
>>>> and while for dbg level messages it doesn't matter, I assume we should
>>>> be consistent for err/warn/info messages (as those will eventually show
>>>> up to the end user) so let maintainers decide here what is
>>>> expectation here
>>>
>>> Could we have some examples pasted here, of the end result of this
>>> series, for all message "categories" (origins, macros, whatever)?
>>
>> GT initialisation:
>> gt_err(gt, "Failed to allocate scratch page\n");
>> i915 0000:00:02.0: [drm] GT0: Failed to allocate scratch page
>>
>> G2H notification handler:
>> guc_err(guc, "notification: Invalid length %u for deregister done\n",
>> len);
>> i915 0000:00:02.0: [drm] GT0: GuC notification: Invalid length 0 for
>> deregister done
please note that today this message is coded as:
drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
-> i915 0000:00:02.0: [drm] Invalid length %u
which makes this rather an example of meaningless log
>
> I'm not liking the inconsistency between gt_err and guc_err where with
> latter callers either need to start the message with lower case because
> of the unstructured "GuC " prefix added. Which then reads bad if callers
> do guc_err(guc, "Error X happend").
>
> Looks like Michal was pointing out the same thing, AFAIU at least when
> re-reading the thread now.
>
> Why wouldn't this work:
>
> guc_err(guc, "Invalid length %u for deregister done notification\n", len);
> i915 0000:00:02.0: [drm] GT0: GuC: Invalid length 0 for deregister done
> notification
+1
>
> Or if the use case for adding custom prefixes is strong then maybe
> consider:
>
> guc_err(guc, "notification", "Invalid length 0 for deregister done");
> i915 0000:00:02.0: [drm] GT0: GuC notification: Invalid length 0 for
> deregister done
>
> guc_err(guc, "", "Error X");
> i915 0000:00:02.0: [drm] GT0: GuC: Error X
-1
this will make logging macros too different from others (unless we
hide/use prefixes inside macros only, but I'm not sure there is any ROI)
>
>> CTB initialisation:
>> ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
>> str_enable_disable(enable), ERR_PTR(err));
>> i915 0000:00:02.0: [drm] GT0: GuC CT Failed to control/enable CTB
>> (EINVAL)
>
> Okay same as above.
>
>> Random meaningless (to me) message that is apparently a display thing:
>> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling
>> PORT PLL B
>
> Plan is to not touch outside gt/.
>
>> I'm sure you can extrapolate to all other forms of dbg, notice, info,
>> etc. without me having to manually type each one out, given that they
>> are all identical.
>>
>> Personally, I think the above should be just:
>> gt_err(gt, "Failed to allocate scratch page\n");
>> i915 0000:00:02.0: [drm] GT0: Failed to allocate scratch page
>>
>> gt_err(guc_to_gt(guc), "G2H: Invalid length for deregister done:
>> %u\n", len);
>> i915 0000:00:02.0: [drm] GT0: G2H: Invalid length for deregister done: 0
that's probably should be:
"Invalid length for G2H deregister done: %u\n
and it will still just look fine if we auto append the 'GuC' prefix:
i915 0000:00:02.0: [drm] GT0: GuC: Invalid length for G2H deregister
>>
>> gt_probe_error(ct_to_gt(ct), "Failed to %s CT %d buffer (%pe)\n",
>> str_enable_disable(enable), send ? "SEND" : "RECV", ERR_PTR(err));
>> i915 0000:00:02.0: [drm] GT0: Failed to enable CT SEND buffer (EINVAL)
having "GuC/CT" prefix here will also look fine:
i915 0000:00:02.0: [drm] GT0: GuC: Failed to enable CT SEND buffer
i915 0000:00:02.0: [drm] GT0: GuC: CT: Failed to enable SEND buffer
i915 0000:00:02.0: [drm] GT0: CT: Failed to enable SEND buffer
>
> We could but it seems we agreed some weeks ago to consolidate the
> existing CT_ERROR macros and such in this exercise. At least no
> objections were raised to that plan.
>
> If now we want to go back on that, and if you want to have
> guc_to_gt(guc) in all gt/uc/ call sites that's fine by me, but please
> get some acks and consensus from people who work in that area. And under
> that option someone would also need to convert the CT code to new macros.
while the main goal of this series was to have GT# appended to the log
messages but we also wanted to simplify the use of the logging macros by
passing the component pointer directly (with extra *bonus* that allows
to auto append component specific prefix, if any, like CT macros do)
IMHO adding guc_xxx() macros with "GuC:" prefix will do the trick and
since many of the existing GuC related logs are already broken or
incomplete, we might fix them accordingly.
In other words in addition to gt_xxx() I still want additional guc_xxx()
macros (as it will allow us to fix related messages) and ct_xxx() macros
(as we already have CT_xxx so no need to change anything)
Michal
>
> Regards,
>
> Tvrtko
>
>> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915-KMS]]
>> disabling PORT PLL B
>> But presumably that requires finishing the plan of splitting out the
>> display code into a separate driver. So for now, something like this
>> would still be a massive improvement:
>> kms_dbg(dev_priv, "disabling %s\n", pll->info->name);
>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] KMS:
>> disabling PORT PLL B
>>
>> John.
>>
>>>
>>> Regards,
>>>
>>> Tvrtko
>>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2022-12-05 18:44 ` Michal Wajdeczko
@ 2022-12-06 11:06 ` Tvrtko Ursulin
2023-01-06 18:57 ` John Harrison
0 siblings, 1 reply; 51+ messages in thread
From: Tvrtko Ursulin @ 2022-12-06 11:06 UTC (permalink / raw)
To: Michal Wajdeczko, John Harrison, Intel-GFX; +Cc: DRI-Devel
On 05/12/2022 18:44, Michal Wajdeczko wrote:
> On 05.12.2022 14:16, Tvrtko Ursulin wrote:
>>
>> On 02/12/2022 20:14, John Harrison wrote:
>>
>>>>> and while for dbg level messages it doesn't matter, I assume we should
>>>>> be consistent for err/warn/info messages (as those will eventually show
>>>>> up to the end user) so let maintainers decide here what is
>>>>> expectation here
>>>>
>>>> Could we have some examples pasted here, of the end result of this
>>>> series, for all message "categories" (origins, macros, whatever)?
>>>
>>> GT initialisation:
>>> gt_err(gt, "Failed to allocate scratch page\n");
>>> i915 0000:00:02.0: [drm] GT0: Failed to allocate scratch page
>>>
>>> G2H notification handler:
>>> guc_err(guc, "notification: Invalid length %u for deregister done\n",
>>> len);
>>> i915 0000:00:02.0: [drm] GT0: GuC notification: Invalid length 0 for
>>> deregister done
>
> please note that today this message is coded as:
>
> drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
> -> i915 0000:00:02.0: [drm] Invalid length %u
>
> which makes this rather an example of meaningless log
Okay, so log text needs improving anyway which is orthogonal.
>> I'm not liking the inconsistency between gt_err and guc_err where with
>> latter callers either need to start the message with lower case because
>> of the unstructured "GuC " prefix added. Which then reads bad if callers
>> do guc_err(guc, "Error X happend").
>>
>> Looks like Michal was pointing out the same thing, AFAIU at least when
>> re-reading the thread now.
>>
>> Why wouldn't this work:
>>
>> guc_err(guc, "Invalid length %u for deregister done notification\n", len);
>> i915 0000:00:02.0: [drm] GT0: GuC: Invalid length 0 for deregister done
>> notification
>
> +1
>
>>
>> Or if the use case for adding custom prefixes is strong then maybe
>> consider:
>>
>> guc_err(guc, "notification", "Invalid length 0 for deregister done");
>> i915 0000:00:02.0: [drm] GT0: GuC notification: Invalid length 0 for
>> deregister done
>>
>> guc_err(guc, "", "Error X");
>> i915 0000:00:02.0: [drm] GT0: GuC: Error X
>
> -1
>
> this will make logging macros too different from others (unless we
> hide/use prefixes inside macros only, but I'm not sure there is any ROI)
Yeah I said if the use case is strong, no strong opinion either way.
>>> CTB initialisation:
>>> ct_probe_error(ct, "Failed to control/%s CTB (%pe)\n",
>>> str_enable_disable(enable), ERR_PTR(err));
>>> i915 0000:00:02.0: [drm] GT0: GuC CT Failed to control/enable CTB
>>> (EINVAL)
>>
>> Okay same as above.
>>
>>> Random meaningless (to me) message that is apparently a display thing:
>>> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
>>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling
>>> PORT PLL B
>>
>> Plan is to not touch outside gt/.
>>
>>> I'm sure you can extrapolate to all other forms of dbg, notice, info,
>>> etc. without me having to manually type each one out, given that they
>>> are all identical.
>>>
>>> Personally, I think the above should be just:
>>> gt_err(gt, "Failed to allocate scratch page\n");
>>> i915 0000:00:02.0: [drm] GT0: Failed to allocate scratch page
>>>
>>> gt_err(guc_to_gt(guc), "G2H: Invalid length for deregister done:
>>> %u\n", len);
>>> i915 0000:00:02.0: [drm] GT0: G2H: Invalid length for deregister done: 0
>
> that's probably should be:
>
> "Invalid length for G2H deregister done: %u\n
>
> and it will still just look fine if we auto append the 'GuC' prefix:
>
> i915 0000:00:02.0: [drm] GT0: GuC: Invalid length for G2H deregister
>
>>>
>>> gt_probe_error(ct_to_gt(ct), "Failed to %s CT %d buffer (%pe)\n",
>>> str_enable_disable(enable), send ? "SEND" : "RECV", ERR_PTR(err));
>>> i915 0000:00:02.0: [drm] GT0: Failed to enable CT SEND buffer (EINVAL)
>
> having "GuC/CT" prefix here will also look fine:
>
> i915 0000:00:02.0: [drm] GT0: GuC: Failed to enable CT SEND buffer
> i915 0000:00:02.0: [drm] GT0: GuC: CT: Failed to enable SEND buffer
> i915 0000:00:02.0: [drm] GT0: CT: Failed to enable SEND buffer
Works for me.
>> We could but it seems we agreed some weeks ago to consolidate the
>> existing CT_ERROR macros and such in this exercise. At least no
>> objections were raised to that plan.
>>
>> If now we want to go back on that, and if you want to have
>> guc_to_gt(guc) in all gt/uc/ call sites that's fine by me, but please
>> get some acks and consensus from people who work in that area. And under
>> that option someone would also need to convert the CT code to new macros.
>
> while the main goal of this series was to have GT# appended to the log
> messages but we also wanted to simplify the use of the logging macros by
> passing the component pointer directly (with extra *bonus* that allows
> to auto append component specific prefix, if any, like CT macros do)
>
> IMHO adding guc_xxx() macros with "GuC:" prefix will do the trick and
> since many of the existing GuC related logs are already broken or
> incomplete, we might fix them accordingly.
>
> In other words in addition to gt_xxx() I still want additional guc_xxx()
> macros (as it will allow us to fix related messages) and ct_xxx() macros
> (as we already have CT_xxx so no need to change anything)
Both approaches are fine by me as long as it's logical and consistent
and we manage not to leave the conversion half-done for too long.
Maybe as a way forward work could be split? If John wants to deal with
gt_xxx macros, avoid touching GuC (putting his original motivation
aside) and you want to convert the gt/uc folder? Assuming John you are
okay with "GuC:" and "CT:" prefixes.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2022-12-06 11:06 ` Tvrtko Ursulin
@ 2023-01-06 18:57 ` John Harrison
0 siblings, 0 replies; 51+ messages in thread
From: John Harrison @ 2023-01-06 18:57 UTC (permalink / raw)
To: Tvrtko Ursulin, Michal Wajdeczko, Intel-GFX; +Cc: Ewins, Jon, DRI-Devel
On 12/6/2022 03:06, Tvrtko Ursulin wrote:
> On 05/12/2022 18:44, Michal Wajdeczko wrote:
>> On 05.12.2022 14:16, Tvrtko Ursulin wrote:
>>> On 02/12/2022 20:14, John Harrison wrote:
>>> [snip]
>>>
>>>> Random meaningless (to me) message that is apparently a display thing:
>>>> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
>>>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling
>>>> PORT PLL B
>>>
>>> Plan is to not touch outside gt/.
For some unexplicable reason that means it is almost impossible to see
the actual problems in most CI dmesg logs because they are swamped with
irrelevant display messages that cannot be filtered out. For example, I
recently manually grep'd out all the display spam from a bug report log.
The dmesg file went from 12MB to 700KB. That is a significant problem
that makes bug triage way harder than it needs to be.
>
> Maybe as a way forward work could be split? If John wants to deal with
> gt_xxx macros, avoid touching GuC (putting his original motivation
> aside) and you want to convert the gt/uc folder? Assuming John you are
> okay with "GuC:" and "CT:" prefixes.
Meaning just repost patch #1 only and expand to more intel_gt_* files?
Sure, if someone will actually reply to that patch with some kind of r-b
first so I know I'm not still wasting my time on a huge re-write that
will to be redone multiple times when someone objects to the use of a
colon or the lack of spaces, braces or whatever.
John.
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
@ 2023-01-06 18:57 ` John Harrison
0 siblings, 0 replies; 51+ messages in thread
From: John Harrison @ 2023-01-06 18:57 UTC (permalink / raw)
To: Tvrtko Ursulin, Michal Wajdeczko, Intel-GFX; +Cc: DRI-Devel
On 12/6/2022 03:06, Tvrtko Ursulin wrote:
> On 05/12/2022 18:44, Michal Wajdeczko wrote:
>> On 05.12.2022 14:16, Tvrtko Ursulin wrote:
>>> On 02/12/2022 20:14, John Harrison wrote:
>>> [snip]
>>>
>>>> Random meaningless (to me) message that is apparently a display thing:
>>>> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
>>>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling
>>>> PORT PLL B
>>>
>>> Plan is to not touch outside gt/.
For some unexplicable reason that means it is almost impossible to see
the actual problems in most CI dmesg logs because they are swamped with
irrelevant display messages that cannot be filtered out. For example, I
recently manually grep'd out all the display spam from a bug report log.
The dmesg file went from 12MB to 700KB. That is a significant problem
that makes bug triage way harder than it needs to be.
>
> Maybe as a way forward work could be split? If John wants to deal with
> gt_xxx macros, avoid touching GuC (putting his original motivation
> aside) and you want to convert the gt/uc folder? Assuming John you are
> okay with "GuC:" and "CT:" prefixes.
Meaning just repost patch #1 only and expand to more intel_gt_* files?
Sure, if someone will actually reply to that patch with some kind of r-b
first so I know I'm not still wasting my time on a huge re-write that
will to be redone multiple times when someone objects to the use of a
colon or the lack of spaces, braces or whatever.
John.
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2023-01-06 18:57 ` John Harrison
@ 2023-01-09 9:38 ` Jani Nikula
-1 siblings, 0 replies; 51+ messages in thread
From: Jani Nikula @ 2023-01-09 9:38 UTC (permalink / raw)
To: John Harrison, Tvrtko Ursulin, Michal Wajdeczko, Intel-GFX
Cc: Ewins, Jon, DRI-Devel
On Fri, 06 Jan 2023, John Harrison <john.c.harrison@intel.com> wrote:
> On 12/6/2022 03:06, Tvrtko Ursulin wrote:
>> On 05/12/2022 18:44, Michal Wajdeczko wrote:
>>> On 05.12.2022 14:16, Tvrtko Ursulin wrote:
>>>> On 02/12/2022 20:14, John Harrison wrote:
>>>> [snip]
>>>>
>>>>> Random meaningless (to me) message that is apparently a display thing:
>>>>> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
>>>>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling
>>>>> PORT PLL B
>>>>
>>>> Plan is to not touch outside gt/.
> For some unexplicable reason that means it is almost impossible to see
> the actual problems in most CI dmesg logs because they are swamped with
> irrelevant display messages that cannot be filtered out. For example, I
> recently manually grep'd out all the display spam from a bug report log.
> The dmesg file went from 12MB to 700KB. That is a significant problem
> that makes bug triage way harder than it needs to be.
You can adjust drm.debug module parameter to get rid of almost all
display debugs. They're logged using the appropriate debug categories.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
@ 2023-01-09 9:38 ` Jani Nikula
0 siblings, 0 replies; 51+ messages in thread
From: Jani Nikula @ 2023-01-09 9:38 UTC (permalink / raw)
To: John Harrison, Tvrtko Ursulin, Michal Wajdeczko, Intel-GFX; +Cc: DRI-Devel
On Fri, 06 Jan 2023, John Harrison <john.c.harrison@intel.com> wrote:
> On 12/6/2022 03:06, Tvrtko Ursulin wrote:
>> On 05/12/2022 18:44, Michal Wajdeczko wrote:
>>> On 05.12.2022 14:16, Tvrtko Ursulin wrote:
>>>> On 02/12/2022 20:14, John Harrison wrote:
>>>> [snip]
>>>>
>>>>> Random meaningless (to me) message that is apparently a display thing:
>>>>> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
>>>>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling
>>>>> PORT PLL B
>>>>
>>>> Plan is to not touch outside gt/.
> For some unexplicable reason that means it is almost impossible to see
> the actual problems in most CI dmesg logs because they are swamped with
> irrelevant display messages that cannot be filtered out. For example, I
> recently manually grep'd out all the display spam from a bug report log.
> The dmesg file went from 12MB to 700KB. That is a significant problem
> that makes bug triage way harder than it needs to be.
You can adjust drm.debug module parameter to get rid of almost all
display debugs. They're logged using the appropriate debug categories.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2023-01-09 9:38 ` Jani Nikula
@ 2023-01-09 20:33 ` John Harrison
-1 siblings, 0 replies; 51+ messages in thread
From: John Harrison @ 2023-01-09 20:33 UTC (permalink / raw)
To: Jani Nikula, Tvrtko Ursulin, Michal Wajdeczko, Intel-GFX
Cc: Ewins, Jon, DRI-Devel
On 1/9/2023 01:38, Jani Nikula wrote:
> On Fri, 06 Jan 2023, John Harrison <john.c.harrison@intel.com> wrote:
>> On 12/6/2022 03:06, Tvrtko Ursulin wrote:
>>> On 05/12/2022 18:44, Michal Wajdeczko wrote:
>>>> On 05.12.2022 14:16, Tvrtko Ursulin wrote:
>>>>> On 02/12/2022 20:14, John Harrison wrote:
>>>>> [snip]
>>>>>
>>>>>> Random meaningless (to me) message that is apparently a display thing:
>>>>>> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
>>>>>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling
>>>>>> PORT PLL B
>>>>> Plan is to not touch outside gt/.
>> For some unexplicable reason that means it is almost impossible to see
>> the actual problems in most CI dmesg logs because they are swamped with
>> irrelevant display messages that cannot be filtered out. For example, I
>> recently manually grep'd out all the display spam from a bug report log.
>> The dmesg file went from 12MB to 700KB. That is a significant problem
>> that makes bug triage way harder than it needs to be.
> You can adjust drm.debug module parameter to get rid of almost all
> display debugs. They're logged using the appropriate debug categories.
No, you can't. See above comment about 'most CI dmesg logs'. This is
when trying to triage bugs created by the CI systems. In that case, the
log already exists and it was generated at full debug and it is tens if
not hundreds of MBs in size. And there is no single tag attached to the
display messages to run 'grep -v' on. They are just a random collection
of disparate function names.
John.
>
>
> BR,
> Jani.
>
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
@ 2023-01-09 20:33 ` John Harrison
0 siblings, 0 replies; 51+ messages in thread
From: John Harrison @ 2023-01-09 20:33 UTC (permalink / raw)
To: Jani Nikula, Tvrtko Ursulin, Michal Wajdeczko, Intel-GFX; +Cc: DRI-Devel
On 1/9/2023 01:38, Jani Nikula wrote:
> On Fri, 06 Jan 2023, John Harrison <john.c.harrison@intel.com> wrote:
>> On 12/6/2022 03:06, Tvrtko Ursulin wrote:
>>> On 05/12/2022 18:44, Michal Wajdeczko wrote:
>>>> On 05.12.2022 14:16, Tvrtko Ursulin wrote:
>>>>> On 02/12/2022 20:14, John Harrison wrote:
>>>>> [snip]
>>>>>
>>>>>> Random meaningless (to me) message that is apparently a display thing:
>>>>>> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
>>>>>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling
>>>>>> PORT PLL B
>>>>> Plan is to not touch outside gt/.
>> For some unexplicable reason that means it is almost impossible to see
>> the actual problems in most CI dmesg logs because they are swamped with
>> irrelevant display messages that cannot be filtered out. For example, I
>> recently manually grep'd out all the display spam from a bug report log.
>> The dmesg file went from 12MB to 700KB. That is a significant problem
>> that makes bug triage way harder than it needs to be.
> You can adjust drm.debug module parameter to get rid of almost all
> display debugs. They're logged using the appropriate debug categories.
No, you can't. See above comment about 'most CI dmesg logs'. This is
when trying to triage bugs created by the CI systems. In that case, the
log already exists and it was generated at full debug and it is tens if
not hundreds of MBs in size. And there is no single tag attached to the
display messages to run 'grep -v' on. They are just a random collection
of disparate function names.
John.
>
>
> BR,
> Jani.
>
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2023-01-06 18:57 ` John Harrison
@ 2023-01-09 9:39 ` Tvrtko Ursulin
-1 siblings, 0 replies; 51+ messages in thread
From: Tvrtko Ursulin @ 2023-01-09 9:39 UTC (permalink / raw)
To: John Harrison, Michal Wajdeczko, Intel-GFX; +Cc: Ewins, Jon, DRI-Devel
On 06/01/2023 18:57, John Harrison wrote:
> On 12/6/2022 03:06, Tvrtko Ursulin wrote:
>> On 05/12/2022 18:44, Michal Wajdeczko wrote:
>>> On 05.12.2022 14:16, Tvrtko Ursulin wrote:
>>>> On 02/12/2022 20:14, John Harrison wrote:
>>>> [snip]
>>>>
>>>>> Random meaningless (to me) message that is apparently a display thing:
>>>>> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
>>>>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling
>>>>> PORT PLL B
>>>>
>>>> Plan is to not touch outside gt/.
> For some unexplicable reason that means it is almost impossible to see
> the actual problems in most CI dmesg logs because they are swamped with
> irrelevant display messages that cannot be filtered out. For example, I
> recently manually grep'd out all the display spam from a bug report log.
> The dmesg file went from 12MB to 700KB. That is a significant problem
> that makes bug triage way harder than it needs to be.
I didn't get this part, how it would reduce the amount of spam by adding
new macros? Anyway, that's something to split out and discuss with
display folks.
>> Maybe as a way forward work could be split? If John wants to deal with
>> gt_xxx macros, avoid touching GuC (putting his original motivation
>> aside) and you want to convert the gt/uc folder? Assuming John you are
>> okay with "GuC:" and "CT:" prefixes.
> Meaning just repost patch #1 only and expand to more intel_gt_* files?
> Sure, if someone will actually reply to that patch with some kind of r-b
> first so I know I'm not still wasting my time on a huge re-write that
> will to be redone multiple times when someone objects to the use of a
> colon or the lack of spaces, braces or whatever.
First patch looks good to me (ack in principle) apart that Michal found
one potential null pointer dereference if I understood it right. That
other comment about the ratelimited call is maybe okay to leave for
later, *if* it will be a single instance, otherwise needs a gt logger as
well. I can r-b once you re-send with the first issue fixed.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
@ 2023-01-09 9:39 ` Tvrtko Ursulin
0 siblings, 0 replies; 51+ messages in thread
From: Tvrtko Ursulin @ 2023-01-09 9:39 UTC (permalink / raw)
To: John Harrison, Michal Wajdeczko, Intel-GFX; +Cc: DRI-Devel
On 06/01/2023 18:57, John Harrison wrote:
> On 12/6/2022 03:06, Tvrtko Ursulin wrote:
>> On 05/12/2022 18:44, Michal Wajdeczko wrote:
>>> On 05.12.2022 14:16, Tvrtko Ursulin wrote:
>>>> On 02/12/2022 20:14, John Harrison wrote:
>>>> [snip]
>>>>
>>>>> Random meaningless (to me) message that is apparently a display thing:
>>>>> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
>>>>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling
>>>>> PORT PLL B
>>>>
>>>> Plan is to not touch outside gt/.
> For some unexplicable reason that means it is almost impossible to see
> the actual problems in most CI dmesg logs because they are swamped with
> irrelevant display messages that cannot be filtered out. For example, I
> recently manually grep'd out all the display spam from a bug report log.
> The dmesg file went from 12MB to 700KB. That is a significant problem
> that makes bug triage way harder than it needs to be.
I didn't get this part, how it would reduce the amount of spam by adding
new macros? Anyway, that's something to split out and discuss with
display folks.
>> Maybe as a way forward work could be split? If John wants to deal with
>> gt_xxx macros, avoid touching GuC (putting his original motivation
>> aside) and you want to convert the gt/uc folder? Assuming John you are
>> okay with "GuC:" and "CT:" prefixes.
> Meaning just repost patch #1 only and expand to more intel_gt_* files?
> Sure, if someone will actually reply to that patch with some kind of r-b
> first so I know I'm not still wasting my time on a huge re-write that
> will to be redone multiple times when someone objects to the use of a
> colon or the lack of spaces, braces or whatever.
First patch looks good to me (ack in principle) apart that Michal found
one potential null pointer dereference if I understood it right. That
other comment about the ratelimited call is maybe okay to leave for
later, *if* it will be a single instance, otherwise needs a gt logger as
well. I can r-b once you re-send with the first issue fixed.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
2023-01-09 9:39 ` Tvrtko Ursulin
@ 2023-01-09 20:36 ` John Harrison
-1 siblings, 0 replies; 51+ messages in thread
From: John Harrison @ 2023-01-09 20:36 UTC (permalink / raw)
To: Tvrtko Ursulin, Michal Wajdeczko, Intel-GFX; +Cc: Ewins, Jon, DRI-Devel
On 1/9/2023 01:39, Tvrtko Ursulin wrote:
> On 06/01/2023 18:57, John Harrison wrote:
>> On 12/6/2022 03:06, Tvrtko Ursulin wrote:
>>> On 05/12/2022 18:44, Michal Wajdeczko wrote:
>>>> On 05.12.2022 14:16, Tvrtko Ursulin wrote:
>>>>> On 02/12/2022 20:14, John Harrison wrote:
>>>>> [snip]
>>>>>
>>>>>> Random meaningless (to me) message that is apparently a display
>>>>>> thing:
>>>>>> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
>>>>>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling
>>>>>> PORT PLL B
>>>>>
>>>>> Plan is to not touch outside gt/.
>> For some unexplicable reason that means it is almost impossible to
>> see the actual problems in most CI dmesg logs because they are
>> swamped with irrelevant display messages that cannot be filtered out.
>> For example, I recently manually grep'd out all the display spam from
>> a bug report log. The dmesg file went from 12MB to 700KB. That is a
>> significant problem that makes bug triage way harder than it needs to
>> be.
>
> I didn't get this part, how it would reduce the amount of spam by
> adding new macros? Anyway, that's something to split out and discuss
> with display folks.
It will allow someone to trivially filter out everything with that tag.
Which then makes it orders of magnitude easy to scan through the log to
see what happened.
>
>>> Maybe as a way forward work could be split? If John wants to deal
>>> with gt_xxx macros, avoid touching GuC (putting his original
>>> motivation aside) and you want to convert the gt/uc folder? Assuming
>>> John you are okay with "GuC:" and "CT:" prefixes.
>> Meaning just repost patch #1 only and expand to more intel_gt_*
>> files? Sure, if someone will actually reply to that patch with some
>> kind of r-b first so I know I'm not still wasting my time on a huge
>> re-write that will to be redone multiple times when someone objects
>> to the use of a colon or the lack of spaces, braces or whatever.
>
> First patch looks good to me (ack in principle) apart that Michal
> found one potential null pointer dereference if I understood it right.
> That other comment about the ratelimited call is maybe okay to leave
> for later, *if* it will be a single instance, otherwise needs a gt
> logger as well. I can r-b once you re-send with the first issue fixed.
I've already fixed those two issues locally. I'm not going to touch the
TRACE macros.
Okay. I'll extend it further and repost.
John.
>
> Regards,
>
> Tvrtko
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers
@ 2023-01-09 20:36 ` John Harrison
0 siblings, 0 replies; 51+ messages in thread
From: John Harrison @ 2023-01-09 20:36 UTC (permalink / raw)
To: Tvrtko Ursulin, Michal Wajdeczko, Intel-GFX; +Cc: DRI-Devel
On 1/9/2023 01:39, Tvrtko Ursulin wrote:
> On 06/01/2023 18:57, John Harrison wrote:
>> On 12/6/2022 03:06, Tvrtko Ursulin wrote:
>>> On 05/12/2022 18:44, Michal Wajdeczko wrote:
>>>> On 05.12.2022 14:16, Tvrtko Ursulin wrote:
>>>>> On 02/12/2022 20:14, John Harrison wrote:
>>>>> [snip]
>>>>>
>>>>>> Random meaningless (to me) message that is apparently a display
>>>>>> thing:
>>>>>> drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
>>>>>> i915 0000:00:02.0: [drm:intel_disable_shared_dpll [i915]] disabling
>>>>>> PORT PLL B
>>>>>
>>>>> Plan is to not touch outside gt/.
>> For some unexplicable reason that means it is almost impossible to
>> see the actual problems in most CI dmesg logs because they are
>> swamped with irrelevant display messages that cannot be filtered out.
>> For example, I recently manually grep'd out all the display spam from
>> a bug report log. The dmesg file went from 12MB to 700KB. That is a
>> significant problem that makes bug triage way harder than it needs to
>> be.
>
> I didn't get this part, how it would reduce the amount of spam by
> adding new macros? Anyway, that's something to split out and discuss
> with display folks.
It will allow someone to trivially filter out everything with that tag.
Which then makes it orders of magnitude easy to scan through the log to
see what happened.
>
>>> Maybe as a way forward work could be split? If John wants to deal
>>> with gt_xxx macros, avoid touching GuC (putting his original
>>> motivation aside) and you want to convert the gt/uc folder? Assuming
>>> John you are okay with "GuC:" and "CT:" prefixes.
>> Meaning just repost patch #1 only and expand to more intel_gt_*
>> files? Sure, if someone will actually reply to that patch with some
>> kind of r-b first so I know I'm not still wasting my time on a huge
>> re-write that will to be redone multiple times when someone objects
>> to the use of a colon or the lack of spaces, braces or whatever.
>
> First patch looks good to me (ack in principle) apart that Michal
> found one potential null pointer dereference if I understood it right.
> That other comment about the ratelimited call is maybe okay to leave
> for later, *if* it will be a single instance, otherwise needs a gt
> logger as well. I can r-b once you re-send with the first issue fixed.
I've already fixed those two issues locally. I'm not going to touch the
TRACE macros.
Okay. I'll extend it further and repost.
John.
>
> Regards,
>
> Tvrtko
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v2 5/5] drm/i915/uc: Update the gt/uc code to use gt_err and friends
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
@ 2022-11-18 1:58 ` John.C.Harrison
-1 siblings, 0 replies; 51+ messages in thread
From: John.C.Harrison @ 2022-11-18 1:58 UTC (permalink / raw)
To: Intel-GFX; +Cc: John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
Use the new module oriented output message helpers where possible.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 108 +++++++++++------------
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 98 ++++++++++----------
2 files changed, 99 insertions(+), 107 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 1d28286e6f066..269be95625342 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -65,29 +65,29 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
ret = intel_reset_guc(gt);
if (ret) {
- DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
+ gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
return ret;
}
guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
- WARN(!(guc_status & GS_MIA_IN_RESET),
- "GuC status: 0x%x, MIA core expected to be in reset\n",
- guc_status);
+ gt_WARN(gt, !(guc_status & GS_MIA_IN_RESET),
+ "GuC status: 0x%x, MIA core expected to be in reset\n",
+ guc_status);
return ret;
}
static void __confirm_options(struct intel_uc *uc)
{
- struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
+ struct intel_gt *gt = uc_to_gt(uc);
+ struct drm_i915_private *i915 = gt->i915;
- drm_dbg(&i915->drm,
- "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
- i915->params.enable_guc,
- str_yes_no(intel_uc_wants_guc(uc)),
- str_yes_no(intel_uc_wants_guc_submission(uc)),
- str_yes_no(intel_uc_wants_huc(uc)),
- str_yes_no(intel_uc_wants_guc_slpc(uc)));
+ gt_dbg(gt, "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
+ i915->params.enable_guc,
+ str_yes_no(intel_uc_wants_guc(uc)),
+ str_yes_no(intel_uc_wants_guc_submission(uc)),
+ str_yes_no(intel_uc_wants_huc(uc)),
+ str_yes_no(intel_uc_wants_guc_slpc(uc)));
if (i915->params.enable_guc == 0) {
GEM_BUG_ON(intel_uc_wants_guc(uc));
@@ -98,26 +98,22 @@ static void __confirm_options(struct intel_uc *uc)
}
if (!intel_uc_supports_guc(uc))
- drm_info(&i915->drm,
- "Incompatible option enable_guc=%d - %s\n",
- i915->params.enable_guc, "GuC is not supported!");
+ gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+ i915->params.enable_guc, "GuC is not supported!");
if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC &&
!intel_uc_supports_huc(uc))
- drm_info(&i915->drm,
- "Incompatible option enable_guc=%d - %s\n",
- i915->params.enable_guc, "HuC is not supported!");
+ gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+ i915->params.enable_guc, "HuC is not supported!");
if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION &&
!intel_uc_supports_guc_submission(uc))
- drm_info(&i915->drm,
- "Incompatible option enable_guc=%d - %s\n",
- i915->params.enable_guc, "GuC submission is N/A");
+ gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+ i915->params.enable_guc, "GuC submission is N/A");
if (i915->params.enable_guc & ~ENABLE_GUC_MASK)
- drm_info(&i915->drm,
- "Incompatible option enable_guc=%d - %s\n",
- i915->params.enable_guc, "undocumented flag");
+ gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+ i915->params.enable_guc, "undocumented flag");
}
void intel_uc_init_early(struct intel_uc *uc)
@@ -249,15 +245,13 @@ static int guc_enable_communication(struct intel_guc *guc)
intel_guc_ct_event_handler(&guc->ct);
spin_unlock_irq(gt->irq_lock);
- drm_dbg(&i915->drm, "GuC communication enabled\n");
+ guc_dbg(guc, "communication enabled\n");
return 0;
}
static void guc_disable_communication(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
/*
* Events generated during or after CT disable are logged by guc in
* via mmio. Make sure the register is clear before disabling CT since
@@ -277,7 +271,7 @@ static void guc_disable_communication(struct intel_guc *guc)
*/
guc_get_mmio_msg(guc);
- drm_dbg(&i915->drm, "GuC communication disabled\n");
+ guc_dbg(guc, "communication disabled\n");
}
static void __uc_fetch_firmwares(struct intel_uc *uc)
@@ -290,8 +284,8 @@ static void __uc_fetch_firmwares(struct intel_uc *uc)
if (err) {
/* Make sure we transition out of transient "SELECTED" state */
if (intel_uc_wants_huc(uc)) {
- drm_dbg(&uc_to_gt(uc)->i915->drm,
- "Failed to fetch GuC: %d disabling HuC\n", err);
+ gt_dbg(uc_to_gt(uc),
+ "Failed to fetch GuC: %d disabling HuC\n", err);
intel_uc_fw_change_status(&uc->huc.fw,
INTEL_UC_FIRMWARE_ERROR);
}
@@ -364,7 +358,7 @@ static int uc_init_wopcm(struct intel_uc *uc)
int err;
if (unlikely(!base || !size)) {
- i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
+ gt_probe_error(gt, "Unsuccessful WOPCM partitioning\n");
return -E2BIG;
}
@@ -395,13 +389,13 @@ static int uc_init_wopcm(struct intel_uc *uc)
return 0;
err_out:
- i915_probe_error(gt->i915, "Failed to init uC WOPCM registers!\n");
- i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
- i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
- intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
- i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
- i915_mmio_reg_offset(GUC_WOPCM_SIZE),
- intel_uncore_read(uncore, GUC_WOPCM_SIZE));
+ gt_probe_error(gt, "Failed to init uC WOPCM registers!\n");
+ gt_probe_error(gt, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
+ i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
+ intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
+ gt_probe_error(gt, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
+ i915_mmio_reg_offset(GUC_WOPCM_SIZE),
+ intel_uncore_read(uncore, GUC_WOPCM_SIZE));
return err;
}
@@ -433,18 +427,19 @@ static int __uc_check_hw(struct intel_uc *uc)
static void print_fw_ver(struct intel_uc *uc, struct intel_uc_fw *fw)
{
- struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
+ struct intel_gt *gt = uc_to_gt(uc);
- drm_info(&i915->drm, "%s firmware %s version %u.%u.%u\n",
- intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
- fw->file_selected.major_ver,
- fw->file_selected.minor_ver,
- fw->file_selected.patch_ver);
+ gt_info(gt, "%s firmware %s version %u.%u.%u\n",
+ intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
+ fw->file_selected.major_ver,
+ fw->file_selected.minor_ver,
+ fw->file_selected.patch_ver);
}
static int __uc_init_hw(struct intel_uc *uc)
{
- struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
+ struct intel_gt *gt = uc_to_gt(uc);
+ struct drm_i915_private *i915 = gt->i915;
struct intel_guc *guc = &uc->guc;
struct intel_huc *huc = &uc->huc;
int ret, attempts;
@@ -496,8 +491,8 @@ static int __uc_init_hw(struct intel_uc *uc)
if (ret == 0)
break;
- DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
- "retry %d more time(s)\n", ret, attempts);
+ gt_dbg(gt, "GuC fw load failed: %d; will reset and retry %d more time(s)\n",
+ ret, attempts);
}
/* Did we succeded or run out of retries? */
@@ -531,10 +526,10 @@ static int __uc_init_hw(struct intel_uc *uc)
intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
}
- drm_info(&i915->drm, "GuC submission %s\n",
- str_enabled_disabled(intel_uc_uses_guc_submission(uc)));
- drm_info(&i915->drm, "GuC SLPC %s\n",
- str_enabled_disabled(intel_uc_uses_guc_slpc(uc)));
+ gt_info(gt, "GuC submission %s\n",
+ str_enabled_disabled(intel_uc_uses_guc_submission(uc)));
+ gt_info(gt, "GuC SLPC %s\n",
+ str_enabled_disabled(intel_uc_uses_guc_slpc(uc)));
return 0;
@@ -552,12 +547,12 @@ static int __uc_init_hw(struct intel_uc *uc)
__uc_sanitize(uc);
if (!ret) {
- drm_notice(&i915->drm, "GuC is uninitialized\n");
+ gt_notice(gt, "GuC is uninitialized\n");
/* We want to run without GuC submission */
return 0;
}
- i915_probe_error(i915, "GuC initialization failed %d\n", ret);
+ gt_probe_error(gt, "GuC initialization failed %d\n", ret);
/* We want to keep KMS alive */
return -EIO;
@@ -656,6 +651,7 @@ void intel_uc_runtime_suspend(struct intel_uc *uc)
void intel_uc_suspend(struct intel_uc *uc)
{
struct intel_guc *guc = &uc->guc;
+ struct intel_gt *gt = uc_to_gt(uc);
intel_wakeref_t wakeref;
int err;
@@ -664,10 +660,10 @@ void intel_uc_suspend(struct intel_uc *uc)
return;
}
- with_intel_runtime_pm(&uc_to_gt(uc)->i915->runtime_pm, wakeref) {
+ with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
err = intel_guc_suspend(guc);
if (err)
- DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
+ guc_dbg(guc, "failed to suspend, err=%d\n", err);
}
}
@@ -695,7 +691,7 @@ static int __uc_resume(struct intel_uc *uc, bool enable_communication)
err = intel_guc_resume(guc);
if (err) {
- DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
+ guc_dbg(guc, "failed to resume, err=%d\n", err);
return err;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 0c80ba51a4bdc..9f10b66599376 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -11,6 +11,7 @@
#include <drm/drm_print.h>
#include "gem/i915_gem_lmem.h"
+#include "gt/intel_gt.h"
#include "intel_uc_fw.h"
#include "intel_uc_fw_abi.h"
#include "i915_drv.h"
@@ -37,11 +38,10 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
enum intel_uc_fw_status status)
{
uc_fw->__status = status;
- drm_dbg(&__uc_fw_to_gt(uc_fw)->i915->drm,
- "%s firmware -> %s\n",
- intel_uc_fw_type_repr(uc_fw->type),
- status == INTEL_UC_FIRMWARE_SELECTED ?
- uc_fw->file_selected.path : intel_uc_fw_status_repr(status));
+ gt_dbg(__uc_fw_to_gt(uc_fw), "%s firmware -> %s\n",
+ intel_uc_fw_type_repr(uc_fw->type),
+ status == INTEL_UC_FIRMWARE_SELECTED ?
+ uc_fw->file_selected.path : intel_uc_fw_status_repr(status));
}
#endif
@@ -482,15 +482,14 @@ static int check_ccs_header(struct intel_gt *gt,
const struct firmware *fw,
struct intel_uc_fw *uc_fw)
{
- struct drm_i915_private *i915 = gt->i915;
struct uc_css_header *css;
size_t size;
/* Check the size of the blob before examining buffer contents */
if (unlikely(fw->size < sizeof(struct uc_css_header))) {
- drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu < %zu\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- fw->size, sizeof(struct uc_css_header));
+ gt_warn(gt, "%s firmware %s: invalid size: %zu < %zu\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ fw->size, sizeof(struct uc_css_header));
return -ENODATA;
}
@@ -500,10 +499,9 @@ static int check_ccs_header(struct intel_gt *gt,
size = (css->header_size_dw - css->key_size_dw - css->modulus_size_dw -
css->exponent_size_dw) * sizeof(u32);
if (unlikely(size != sizeof(struct uc_css_header))) {
- drm_warn(&i915->drm,
- "%s firmware %s: unexpected header size: %zu != %zu\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- fw->size, sizeof(struct uc_css_header));
+ gt_warn(gt, "%s firmware %s: unexpected header size: %zu != %zu\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ fw->size, sizeof(struct uc_css_header));
return -EPROTO;
}
@@ -516,18 +514,18 @@ static int check_ccs_header(struct intel_gt *gt,
/* At least, it should have header, uCode and RSA. Size of all three. */
size = sizeof(struct uc_css_header) + uc_fw->ucode_size + uc_fw->rsa_size;
if (unlikely(fw->size < size)) {
- drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu < %zu\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- fw->size, size);
+ gt_warn(gt, "%s firmware %s: invalid size: %zu < %zu\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ fw->size, size);
return -ENOEXEC;
}
/* Sanity check whether this fw is not larger than whole WOPCM memory */
size = __intel_uc_fw_get_upload_size(uc_fw);
if (unlikely(size >= gt->wopcm.size)) {
- drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu > %zu\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- size, (size_t)gt->wopcm.size);
+ gt_warn(gt, "%s firmware %s: invalid size: %zu > %zu\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ size, (size_t)gt->wopcm.size);
return -E2BIG;
}
@@ -578,10 +576,9 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
memcpy(&file_ideal, &uc_fw->file_wanted, sizeof(file_ideal));
if (!err && fw->size > INTEL_UC_RSVD_GGTT_PER_FW) {
- drm_err(&i915->drm,
- "%s firmware %s: size (%zuKB) exceeds max supported size (%uKB)\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- fw->size / SZ_1K, INTEL_UC_RSVD_GGTT_PER_FW / SZ_1K);
+ gt_err(gt, "%s firmware %s: size (%zuKB) exceeds max supported size (%uKB)\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ fw->size / SZ_1K, INTEL_UC_RSVD_GGTT_PER_FW / SZ_1K);
/* try to find another blob to load */
release_firmware(fw);
@@ -624,10 +621,10 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
if (uc_fw->file_wanted.major_ver) {
/* Check the file's major version was as it claimed */
if (uc_fw->file_selected.major_ver != uc_fw->file_wanted.major_ver) {
- drm_notice(&i915->drm, "%s firmware %s: unexpected version: %u.%u != %u.%u\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- uc_fw->file_selected.major_ver, uc_fw->file_selected.minor_ver,
- uc_fw->file_wanted.major_ver, uc_fw->file_wanted.minor_ver);
+ gt_notice(gt, "%s firmware %s: unexpected version: %u.%u != %u.%u\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ uc_fw->file_selected.major_ver, uc_fw->file_selected.minor_ver,
+ uc_fw->file_wanted.major_ver, uc_fw->file_wanted.minor_ver);
if (!intel_uc_fw_is_overridden(uc_fw)) {
err = -ENOEXEC;
goto fail;
@@ -642,16 +639,14 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
/* Preserve the version that was really wanted */
memcpy(&uc_fw->file_wanted, &file_ideal, sizeof(uc_fw->file_wanted));
- drm_notice(&i915->drm,
- "%s firmware %s (%d.%d) is recommended, but only %s (%d.%d) was found\n",
- intel_uc_fw_type_repr(uc_fw->type),
- uc_fw->file_wanted.path,
- uc_fw->file_wanted.major_ver, uc_fw->file_wanted.minor_ver,
- uc_fw->file_selected.path,
- uc_fw->file_selected.major_ver, uc_fw->file_selected.minor_ver);
- drm_info(&i915->drm,
- "Consider updating your linux-firmware pkg or downloading from %s\n",
- INTEL_UC_FIRMWARE_URL);
+ gt_notice(gt, "%s firmware %s (%d.%d) is recommended, but only %s (%d.%d) was found\n",
+ intel_uc_fw_type_repr(uc_fw->type),
+ uc_fw->file_wanted.path,
+ uc_fw->file_wanted.major_ver, uc_fw->file_wanted.minor_ver,
+ uc_fw->file_selected.path,
+ uc_fw->file_selected.major_ver, uc_fw->file_selected.minor_ver);
+ gt_info(gt, "Consider updating your linux-firmware pkg or downloading from %s\n",
+ INTEL_UC_FIRMWARE_URL);
}
if (HAS_LMEM(i915)) {
@@ -679,10 +674,10 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
INTEL_UC_FIRMWARE_MISSING :
INTEL_UC_FIRMWARE_ERROR);
- i915_probe_error(i915, "%s firmware %s: fetch failed with error %d\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path, err);
- drm_info(&i915->drm, "%s firmware(s) can be downloaded from %s\n",
- intel_uc_fw_type_repr(uc_fw->type), INTEL_UC_FIRMWARE_URL);
+ gt_probe_error(gt, "%s firmware %s: fetch failed with error %d\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path, err);
+ gt_info(gt, "%s firmware(s) can be downloaded from %s\n",
+ intel_uc_fw_type_repr(uc_fw->type), INTEL_UC_FIRMWARE_URL);
release_firmware(fw); /* OK even if fw is NULL */
return err;
@@ -788,9 +783,9 @@ static int uc_fw_xfer(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags)
/* Wait for DMA to finish */
ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100);
if (ret)
- drm_err(>->i915->drm, "DMA for %s fw failed, DMA_CTRL=%u\n",
- intel_uc_fw_type_repr(uc_fw->type),
- intel_uncore_read_fw(uncore, DMA_CTRL));
+ gt_err(gt, "DMA for %s fw failed, DMA_CTRL=%u\n",
+ intel_uc_fw_type_repr(uc_fw->type),
+ intel_uncore_read_fw(uncore, DMA_CTRL));
/* Disable the bits once DMA is over */
intel_uncore_write_fw(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
@@ -836,9 +831,9 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags)
return 0;
fail:
- i915_probe_error(gt->i915, "Failed to load %s firmware %s (%d)\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- err);
+ gt_probe_error(gt, "Failed to load %s firmware %s (%d)\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ err);
intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
return err;
}
@@ -914,6 +909,7 @@ static void uc_fw_rsa_data_destroy(struct intel_uc_fw *uc_fw)
int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
{
+ struct intel_gt *gt = __uc_fw_to_gt(uc_fw);
int err;
/* this should happen before the load! */
@@ -924,15 +920,15 @@ int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
err = i915_gem_object_pin_pages_unlocked(uc_fw->obj);
if (err) {
- DRM_DEBUG_DRIVER("%s fw pin-pages err=%d\n",
- intel_uc_fw_type_repr(uc_fw->type), err);
+ gt_dbg(gt, "%s fw pin-pages err=%d\n",
+ intel_uc_fw_type_repr(uc_fw->type), err);
goto out;
}
err = uc_fw_rsa_data_create(uc_fw);
if (err) {
- DRM_DEBUG_DRIVER("%s fw rsa data creation failed, err=%d\n",
- intel_uc_fw_type_repr(uc_fw->type), err);
+ gt_dbg(gt, "%s fw rsa data creation failed, err=%d\n",
+ intel_uc_fw_type_repr(uc_fw->type), err);
goto out_unpin;
}
--
2.37.3
^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH v2 5/5] drm/i915/uc: Update the gt/uc code to use gt_err and friends
@ 2022-11-18 1:58 ` John.C.Harrison
0 siblings, 0 replies; 51+ messages in thread
From: John.C.Harrison @ 2022-11-18 1:58 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
Use the new module oriented output message helpers where possible.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 108 +++++++++++------------
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 98 ++++++++++----------
2 files changed, 99 insertions(+), 107 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 1d28286e6f066..269be95625342 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -65,29 +65,29 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
ret = intel_reset_guc(gt);
if (ret) {
- DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
+ gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
return ret;
}
guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
- WARN(!(guc_status & GS_MIA_IN_RESET),
- "GuC status: 0x%x, MIA core expected to be in reset\n",
- guc_status);
+ gt_WARN(gt, !(guc_status & GS_MIA_IN_RESET),
+ "GuC status: 0x%x, MIA core expected to be in reset\n",
+ guc_status);
return ret;
}
static void __confirm_options(struct intel_uc *uc)
{
- struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
+ struct intel_gt *gt = uc_to_gt(uc);
+ struct drm_i915_private *i915 = gt->i915;
- drm_dbg(&i915->drm,
- "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
- i915->params.enable_guc,
- str_yes_no(intel_uc_wants_guc(uc)),
- str_yes_no(intel_uc_wants_guc_submission(uc)),
- str_yes_no(intel_uc_wants_huc(uc)),
- str_yes_no(intel_uc_wants_guc_slpc(uc)));
+ gt_dbg(gt, "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
+ i915->params.enable_guc,
+ str_yes_no(intel_uc_wants_guc(uc)),
+ str_yes_no(intel_uc_wants_guc_submission(uc)),
+ str_yes_no(intel_uc_wants_huc(uc)),
+ str_yes_no(intel_uc_wants_guc_slpc(uc)));
if (i915->params.enable_guc == 0) {
GEM_BUG_ON(intel_uc_wants_guc(uc));
@@ -98,26 +98,22 @@ static void __confirm_options(struct intel_uc *uc)
}
if (!intel_uc_supports_guc(uc))
- drm_info(&i915->drm,
- "Incompatible option enable_guc=%d - %s\n",
- i915->params.enable_guc, "GuC is not supported!");
+ gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+ i915->params.enable_guc, "GuC is not supported!");
if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC &&
!intel_uc_supports_huc(uc))
- drm_info(&i915->drm,
- "Incompatible option enable_guc=%d - %s\n",
- i915->params.enable_guc, "HuC is not supported!");
+ gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+ i915->params.enable_guc, "HuC is not supported!");
if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION &&
!intel_uc_supports_guc_submission(uc))
- drm_info(&i915->drm,
- "Incompatible option enable_guc=%d - %s\n",
- i915->params.enable_guc, "GuC submission is N/A");
+ gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+ i915->params.enable_guc, "GuC submission is N/A");
if (i915->params.enable_guc & ~ENABLE_GUC_MASK)
- drm_info(&i915->drm,
- "Incompatible option enable_guc=%d - %s\n",
- i915->params.enable_guc, "undocumented flag");
+ gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
+ i915->params.enable_guc, "undocumented flag");
}
void intel_uc_init_early(struct intel_uc *uc)
@@ -249,15 +245,13 @@ static int guc_enable_communication(struct intel_guc *guc)
intel_guc_ct_event_handler(&guc->ct);
spin_unlock_irq(gt->irq_lock);
- drm_dbg(&i915->drm, "GuC communication enabled\n");
+ guc_dbg(guc, "communication enabled\n");
return 0;
}
static void guc_disable_communication(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
/*
* Events generated during or after CT disable are logged by guc in
* via mmio. Make sure the register is clear before disabling CT since
@@ -277,7 +271,7 @@ static void guc_disable_communication(struct intel_guc *guc)
*/
guc_get_mmio_msg(guc);
- drm_dbg(&i915->drm, "GuC communication disabled\n");
+ guc_dbg(guc, "communication disabled\n");
}
static void __uc_fetch_firmwares(struct intel_uc *uc)
@@ -290,8 +284,8 @@ static void __uc_fetch_firmwares(struct intel_uc *uc)
if (err) {
/* Make sure we transition out of transient "SELECTED" state */
if (intel_uc_wants_huc(uc)) {
- drm_dbg(&uc_to_gt(uc)->i915->drm,
- "Failed to fetch GuC: %d disabling HuC\n", err);
+ gt_dbg(uc_to_gt(uc),
+ "Failed to fetch GuC: %d disabling HuC\n", err);
intel_uc_fw_change_status(&uc->huc.fw,
INTEL_UC_FIRMWARE_ERROR);
}
@@ -364,7 +358,7 @@ static int uc_init_wopcm(struct intel_uc *uc)
int err;
if (unlikely(!base || !size)) {
- i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
+ gt_probe_error(gt, "Unsuccessful WOPCM partitioning\n");
return -E2BIG;
}
@@ -395,13 +389,13 @@ static int uc_init_wopcm(struct intel_uc *uc)
return 0;
err_out:
- i915_probe_error(gt->i915, "Failed to init uC WOPCM registers!\n");
- i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
- i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
- intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
- i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
- i915_mmio_reg_offset(GUC_WOPCM_SIZE),
- intel_uncore_read(uncore, GUC_WOPCM_SIZE));
+ gt_probe_error(gt, "Failed to init uC WOPCM registers!\n");
+ gt_probe_error(gt, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
+ i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
+ intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
+ gt_probe_error(gt, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
+ i915_mmio_reg_offset(GUC_WOPCM_SIZE),
+ intel_uncore_read(uncore, GUC_WOPCM_SIZE));
return err;
}
@@ -433,18 +427,19 @@ static int __uc_check_hw(struct intel_uc *uc)
static void print_fw_ver(struct intel_uc *uc, struct intel_uc_fw *fw)
{
- struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
+ struct intel_gt *gt = uc_to_gt(uc);
- drm_info(&i915->drm, "%s firmware %s version %u.%u.%u\n",
- intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
- fw->file_selected.major_ver,
- fw->file_selected.minor_ver,
- fw->file_selected.patch_ver);
+ gt_info(gt, "%s firmware %s version %u.%u.%u\n",
+ intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
+ fw->file_selected.major_ver,
+ fw->file_selected.minor_ver,
+ fw->file_selected.patch_ver);
}
static int __uc_init_hw(struct intel_uc *uc)
{
- struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
+ struct intel_gt *gt = uc_to_gt(uc);
+ struct drm_i915_private *i915 = gt->i915;
struct intel_guc *guc = &uc->guc;
struct intel_huc *huc = &uc->huc;
int ret, attempts;
@@ -496,8 +491,8 @@ static int __uc_init_hw(struct intel_uc *uc)
if (ret == 0)
break;
- DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
- "retry %d more time(s)\n", ret, attempts);
+ gt_dbg(gt, "GuC fw load failed: %d; will reset and retry %d more time(s)\n",
+ ret, attempts);
}
/* Did we succeded or run out of retries? */
@@ -531,10 +526,10 @@ static int __uc_init_hw(struct intel_uc *uc)
intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
}
- drm_info(&i915->drm, "GuC submission %s\n",
- str_enabled_disabled(intel_uc_uses_guc_submission(uc)));
- drm_info(&i915->drm, "GuC SLPC %s\n",
- str_enabled_disabled(intel_uc_uses_guc_slpc(uc)));
+ gt_info(gt, "GuC submission %s\n",
+ str_enabled_disabled(intel_uc_uses_guc_submission(uc)));
+ gt_info(gt, "GuC SLPC %s\n",
+ str_enabled_disabled(intel_uc_uses_guc_slpc(uc)));
return 0;
@@ -552,12 +547,12 @@ static int __uc_init_hw(struct intel_uc *uc)
__uc_sanitize(uc);
if (!ret) {
- drm_notice(&i915->drm, "GuC is uninitialized\n");
+ gt_notice(gt, "GuC is uninitialized\n");
/* We want to run without GuC submission */
return 0;
}
- i915_probe_error(i915, "GuC initialization failed %d\n", ret);
+ gt_probe_error(gt, "GuC initialization failed %d\n", ret);
/* We want to keep KMS alive */
return -EIO;
@@ -656,6 +651,7 @@ void intel_uc_runtime_suspend(struct intel_uc *uc)
void intel_uc_suspend(struct intel_uc *uc)
{
struct intel_guc *guc = &uc->guc;
+ struct intel_gt *gt = uc_to_gt(uc);
intel_wakeref_t wakeref;
int err;
@@ -664,10 +660,10 @@ void intel_uc_suspend(struct intel_uc *uc)
return;
}
- with_intel_runtime_pm(&uc_to_gt(uc)->i915->runtime_pm, wakeref) {
+ with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
err = intel_guc_suspend(guc);
if (err)
- DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
+ guc_dbg(guc, "failed to suspend, err=%d\n", err);
}
}
@@ -695,7 +691,7 @@ static int __uc_resume(struct intel_uc *uc, bool enable_communication)
err = intel_guc_resume(guc);
if (err) {
- DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
+ guc_dbg(guc, "failed to resume, err=%d\n", err);
return err;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 0c80ba51a4bdc..9f10b66599376 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -11,6 +11,7 @@
#include <drm/drm_print.h>
#include "gem/i915_gem_lmem.h"
+#include "gt/intel_gt.h"
#include "intel_uc_fw.h"
#include "intel_uc_fw_abi.h"
#include "i915_drv.h"
@@ -37,11 +38,10 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
enum intel_uc_fw_status status)
{
uc_fw->__status = status;
- drm_dbg(&__uc_fw_to_gt(uc_fw)->i915->drm,
- "%s firmware -> %s\n",
- intel_uc_fw_type_repr(uc_fw->type),
- status == INTEL_UC_FIRMWARE_SELECTED ?
- uc_fw->file_selected.path : intel_uc_fw_status_repr(status));
+ gt_dbg(__uc_fw_to_gt(uc_fw), "%s firmware -> %s\n",
+ intel_uc_fw_type_repr(uc_fw->type),
+ status == INTEL_UC_FIRMWARE_SELECTED ?
+ uc_fw->file_selected.path : intel_uc_fw_status_repr(status));
}
#endif
@@ -482,15 +482,14 @@ static int check_ccs_header(struct intel_gt *gt,
const struct firmware *fw,
struct intel_uc_fw *uc_fw)
{
- struct drm_i915_private *i915 = gt->i915;
struct uc_css_header *css;
size_t size;
/* Check the size of the blob before examining buffer contents */
if (unlikely(fw->size < sizeof(struct uc_css_header))) {
- drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu < %zu\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- fw->size, sizeof(struct uc_css_header));
+ gt_warn(gt, "%s firmware %s: invalid size: %zu < %zu\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ fw->size, sizeof(struct uc_css_header));
return -ENODATA;
}
@@ -500,10 +499,9 @@ static int check_ccs_header(struct intel_gt *gt,
size = (css->header_size_dw - css->key_size_dw - css->modulus_size_dw -
css->exponent_size_dw) * sizeof(u32);
if (unlikely(size != sizeof(struct uc_css_header))) {
- drm_warn(&i915->drm,
- "%s firmware %s: unexpected header size: %zu != %zu\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- fw->size, sizeof(struct uc_css_header));
+ gt_warn(gt, "%s firmware %s: unexpected header size: %zu != %zu\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ fw->size, sizeof(struct uc_css_header));
return -EPROTO;
}
@@ -516,18 +514,18 @@ static int check_ccs_header(struct intel_gt *gt,
/* At least, it should have header, uCode and RSA. Size of all three. */
size = sizeof(struct uc_css_header) + uc_fw->ucode_size + uc_fw->rsa_size;
if (unlikely(fw->size < size)) {
- drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu < %zu\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- fw->size, size);
+ gt_warn(gt, "%s firmware %s: invalid size: %zu < %zu\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ fw->size, size);
return -ENOEXEC;
}
/* Sanity check whether this fw is not larger than whole WOPCM memory */
size = __intel_uc_fw_get_upload_size(uc_fw);
if (unlikely(size >= gt->wopcm.size)) {
- drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu > %zu\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- size, (size_t)gt->wopcm.size);
+ gt_warn(gt, "%s firmware %s: invalid size: %zu > %zu\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ size, (size_t)gt->wopcm.size);
return -E2BIG;
}
@@ -578,10 +576,9 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
memcpy(&file_ideal, &uc_fw->file_wanted, sizeof(file_ideal));
if (!err && fw->size > INTEL_UC_RSVD_GGTT_PER_FW) {
- drm_err(&i915->drm,
- "%s firmware %s: size (%zuKB) exceeds max supported size (%uKB)\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- fw->size / SZ_1K, INTEL_UC_RSVD_GGTT_PER_FW / SZ_1K);
+ gt_err(gt, "%s firmware %s: size (%zuKB) exceeds max supported size (%uKB)\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ fw->size / SZ_1K, INTEL_UC_RSVD_GGTT_PER_FW / SZ_1K);
/* try to find another blob to load */
release_firmware(fw);
@@ -624,10 +621,10 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
if (uc_fw->file_wanted.major_ver) {
/* Check the file's major version was as it claimed */
if (uc_fw->file_selected.major_ver != uc_fw->file_wanted.major_ver) {
- drm_notice(&i915->drm, "%s firmware %s: unexpected version: %u.%u != %u.%u\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- uc_fw->file_selected.major_ver, uc_fw->file_selected.minor_ver,
- uc_fw->file_wanted.major_ver, uc_fw->file_wanted.minor_ver);
+ gt_notice(gt, "%s firmware %s: unexpected version: %u.%u != %u.%u\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ uc_fw->file_selected.major_ver, uc_fw->file_selected.minor_ver,
+ uc_fw->file_wanted.major_ver, uc_fw->file_wanted.minor_ver);
if (!intel_uc_fw_is_overridden(uc_fw)) {
err = -ENOEXEC;
goto fail;
@@ -642,16 +639,14 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
/* Preserve the version that was really wanted */
memcpy(&uc_fw->file_wanted, &file_ideal, sizeof(uc_fw->file_wanted));
- drm_notice(&i915->drm,
- "%s firmware %s (%d.%d) is recommended, but only %s (%d.%d) was found\n",
- intel_uc_fw_type_repr(uc_fw->type),
- uc_fw->file_wanted.path,
- uc_fw->file_wanted.major_ver, uc_fw->file_wanted.minor_ver,
- uc_fw->file_selected.path,
- uc_fw->file_selected.major_ver, uc_fw->file_selected.minor_ver);
- drm_info(&i915->drm,
- "Consider updating your linux-firmware pkg or downloading from %s\n",
- INTEL_UC_FIRMWARE_URL);
+ gt_notice(gt, "%s firmware %s (%d.%d) is recommended, but only %s (%d.%d) was found\n",
+ intel_uc_fw_type_repr(uc_fw->type),
+ uc_fw->file_wanted.path,
+ uc_fw->file_wanted.major_ver, uc_fw->file_wanted.minor_ver,
+ uc_fw->file_selected.path,
+ uc_fw->file_selected.major_ver, uc_fw->file_selected.minor_ver);
+ gt_info(gt, "Consider updating your linux-firmware pkg or downloading from %s\n",
+ INTEL_UC_FIRMWARE_URL);
}
if (HAS_LMEM(i915)) {
@@ -679,10 +674,10 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
INTEL_UC_FIRMWARE_MISSING :
INTEL_UC_FIRMWARE_ERROR);
- i915_probe_error(i915, "%s firmware %s: fetch failed with error %d\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path, err);
- drm_info(&i915->drm, "%s firmware(s) can be downloaded from %s\n",
- intel_uc_fw_type_repr(uc_fw->type), INTEL_UC_FIRMWARE_URL);
+ gt_probe_error(gt, "%s firmware %s: fetch failed with error %d\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path, err);
+ gt_info(gt, "%s firmware(s) can be downloaded from %s\n",
+ intel_uc_fw_type_repr(uc_fw->type), INTEL_UC_FIRMWARE_URL);
release_firmware(fw); /* OK even if fw is NULL */
return err;
@@ -788,9 +783,9 @@ static int uc_fw_xfer(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags)
/* Wait for DMA to finish */
ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100);
if (ret)
- drm_err(>->i915->drm, "DMA for %s fw failed, DMA_CTRL=%u\n",
- intel_uc_fw_type_repr(uc_fw->type),
- intel_uncore_read_fw(uncore, DMA_CTRL));
+ gt_err(gt, "DMA for %s fw failed, DMA_CTRL=%u\n",
+ intel_uc_fw_type_repr(uc_fw->type),
+ intel_uncore_read_fw(uncore, DMA_CTRL));
/* Disable the bits once DMA is over */
intel_uncore_write_fw(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
@@ -836,9 +831,9 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags)
return 0;
fail:
- i915_probe_error(gt->i915, "Failed to load %s firmware %s (%d)\n",
- intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
- err);
+ gt_probe_error(gt, "Failed to load %s firmware %s (%d)\n",
+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+ err);
intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
return err;
}
@@ -914,6 +909,7 @@ static void uc_fw_rsa_data_destroy(struct intel_uc_fw *uc_fw)
int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
{
+ struct intel_gt *gt = __uc_fw_to_gt(uc_fw);
int err;
/* this should happen before the load! */
@@ -924,15 +920,15 @@ int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
err = i915_gem_object_pin_pages_unlocked(uc_fw->obj);
if (err) {
- DRM_DEBUG_DRIVER("%s fw pin-pages err=%d\n",
- intel_uc_fw_type_repr(uc_fw->type), err);
+ gt_dbg(gt, "%s fw pin-pages err=%d\n",
+ intel_uc_fw_type_repr(uc_fw->type), err);
goto out;
}
err = uc_fw_rsa_data_create(uc_fw);
if (err) {
- DRM_DEBUG_DRIVER("%s fw rsa data creation failed, err=%d\n",
- intel_uc_fw_type_repr(uc_fw->type), err);
+ gt_dbg(gt, "%s fw rsa data creation failed, err=%d\n",
+ intel_uc_fw_type_repr(uc_fw->type), err);
goto out_unpin;
}
--
2.37.3
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add module oriented dmesg output
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
` (5 preceding siblings ...)
(?)
@ 2022-11-18 2:24 ` Patchwork
-1 siblings, 0 replies; 51+ messages in thread
From: Patchwork @ 2022-11-18 2:24 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
== Series Details ==
Series: Add module oriented dmesg output
URL : https://patchwork.freedesktop.org/series/111050/
State : warning
== Summary ==
Error: dim checkpatch failed
910945e13c6a drm/i915/gt: Start adding module oriented dmesg output
-:229: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible side-effects?
#229: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:16:
+#define gt_err(_gt, _fmt, ...) \
+ drm_err(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
-:232: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible side-effects?
#232: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:19:
+#define gt_warn(_gt, _fmt, ...) \
+ drm_warn(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
-:235: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible side-effects?
#235: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:22:
+#define gt_notice(_gt, _fmt, ...) \
+ drm_notice(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
-:238: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible side-effects?
#238: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:25:
+#define gt_info(_gt, _fmt, ...) \
+ drm_info(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
-:241: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible side-effects?
#241: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:28:
+#define gt_dbg(_gt, _fmt, ...) \
+ drm_dbg(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
-:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible side-effects?
#244: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:31:
+#define gt_probe_error(_gt, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ gt_dbg(_gt, _fmt, ##__VA_ARGS__); \
+ else \
+ gt_err(_gt, _fmt, ##__VA_ARGS__); \
+ } while (0)
-:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_fmt' - possible side-effects?
#244: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:31:
+#define gt_probe_error(_gt, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ gt_dbg(_gt, _fmt, ##__VA_ARGS__); \
+ else \
+ gt_err(_gt, _fmt, ##__VA_ARGS__); \
+ } while (0)
-:258: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible side-effects?
#258: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:45:
+#define gt_WARN(_gt, _condition, _fmt, ...) \
+ drm_WARN(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
-:261: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible side-effects?
#261: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:48:
+#define gt_WARN_ONCE(_gt, _condition, _fmt, ...) \
+ drm_WARN_ONCE(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
total: 0 errors, 0 warnings, 9 checks, 227 lines checked
0824d2802a9d drm/i915/huc: Add HuC specific debug print wrappers
-:146: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_huc' - possible side-effects?
#146: FILE: drivers/gpu/drm/i915/gt/uc/intel_huc.h:34:
+#define huc_probe_error(_huc, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ huc_dbg(_huc, _fmt, ##__VA_ARGS__); \
+ else \
+ huc_err(_huc, _fmt, ##__VA_ARGS__); \
+ } while (0)
-:146: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_fmt' - possible side-effects?
#146: FILE: drivers/gpu/drm/i915/gt/uc/intel_huc.h:34:
+#define huc_probe_error(_huc, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ huc_dbg(_huc, _fmt, ##__VA_ARGS__); \
+ else \
+ huc_err(_huc, _fmt, ##__VA_ARGS__); \
+ } while (0)
total: 0 errors, 0 warnings, 2 checks, 129 lines checked
d0ae6abfafaa drm/i915/guc: Add GuC specific debug print wrappers
-:149: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_guc' - possible side-effects?
#149: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc.h:42:
+#define guc_probe_error(_guc, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ guc_dbg(_guc, _fmt, ##__VA_ARGS__); \
+ else \
+ guc_err(_guc, _fmt, ##__VA_ARGS__); \
+ } while (0)
-:149: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_fmt' - possible side-effects?
#149: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc.h:42:
+#define guc_probe_error(_guc, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ guc_dbg(_guc, _fmt, ##__VA_ARGS__); \
+ else \
+ guc_err(_guc, _fmt, ##__VA_ARGS__); \
+ } while (0)
-:290: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#290: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:621:
if (!caplist) {
+ guc_dbg(guc, "capture: Failed to alloc cached caplist\n");
-:307: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#307: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:662:
if (!null_header) {
+ guc_dbg(guc, "capture: Failed to alloc cached null list\n");
-:1097: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#1097: FILE: drivers/gpu/drm/i915/gt/uc/selftest_guc.c:156:
if (!ce) {
+ guc_err(guc, "Context array allocation failed\n");
total: 0 errors, 3 warnings, 2 checks, 1171 lines checked
1bf39890e43c drm/i915/guc: Add GuC CT specific debug print wrappers
-:63: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_ct' - possible side-effects?
#63: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:48:
+#define ct_probe_error(_ct, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
+ else \
+ ct_err(_ct, _fmt, ##__VA_ARGS__); \
+ } while (0)
-:63: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_fmt' - possible side-effects?
#63: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:48:
+#define ct_probe_error(_ct, _fmt, ...) \
+ do { \
+ if (i915_error_injected()) \
+ ct_dbg(_ct, _fmt, ##__VA_ARGS__); \
+ else \
+ ct_err(_ct, _fmt, ##__VA_ARGS__); \
+ } while (0)
total: 0 errors, 0 warnings, 2 checks, 468 lines checked
8693a06e71a3 drm/i915/uc: Update the gt/uc code to use gt_err and friends
^ permalink raw reply [flat|nested] 51+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add module oriented dmesg output
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
` (6 preceding siblings ...)
(?)
@ 2022-11-18 2:24 ` Patchwork
-1 siblings, 0 replies; 51+ messages in thread
From: Patchwork @ 2022-11-18 2:24 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
== Series Details ==
Series: Add module oriented dmesg output
URL : https://patchwork.freedesktop.org/series/111050/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 51+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Add module oriented dmesg output
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
` (7 preceding siblings ...)
(?)
@ 2022-11-18 2:45 ` Patchwork
-1 siblings, 0 replies; 51+ messages in thread
From: Patchwork @ 2022-11-18 2:45 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 9508 bytes --]
== Series Details ==
Series: Add module oriented dmesg output
URL : https://patchwork.freedesktop.org/series/111050/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12397 -> Patchwork_111050v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/index.html
Participating hosts (31 -> 37)
------------------------------
Additional (11): bat-dg1-7 bat-dg1-6 bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 bat-adln-1 bat-rplp-1 bat-rpls-2 bat-dg2-11 bat-jsl-1
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_111050v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hugepages:
- {bat-rpls-2}: NOTRUN -> [DMESG-WARN][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-rpls-2/igt@i915_selftest@live@hugepages.html
* igt@i915_selftest@live@slpc:
- {bat-rpls-2}: NOTRUN -> [DMESG-FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-rpls-2/igt@i915_selftest@live@slpc.html
Known issues
------------
Here are the changes found in Patchwork_111050v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap@basic:
- bat-dg1-6: NOTRUN -> [SKIP][3] ([i915#4083])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@gem_mmap@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][4] ([i915#4079]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@gem_render_tiled_blits@basic.html
- fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([i915#7056])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/fi-apl-guc/igt@gem_render_tiled_blits@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/fi-apl-guc/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#4077]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@gem_tiled_fence_blits@basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#1155])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-6: NOTRUN -> [SKIP][9] ([i915#6621])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@i915_pm_rps@basic-api.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][10] ([i915#4215])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#4212]) +7 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_chamelium@hdmi-crc-fast:
- bat-dg1-6: NOTRUN -> [SKIP][12] ([fdo#111827]) +8 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4103] / [i915#4213])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-6: NOTRUN -> [SKIP][14] ([fdo#109285])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@sprite_plane_onoff:
- bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#1072] / [i915#4078]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-6: NOTRUN -> [SKIP][16] ([i915#3555])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-6: NOTRUN -> [SKIP][17] ([i915#3708] / [i915#4077]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-userptr:
- bat-dg1-6: NOTRUN -> [SKIP][18] ([i915#3708] / [i915#4873])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@prime_vgem@basic-userptr.html
* igt@prime_vgem@basic-write:
- bat-dg1-6: NOTRUN -> [SKIP][19] ([i915#3708]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/bat-dg1-6/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-bxt-dsi: [DMESG-FAIL][20] ([i915#5334]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4303]: https://gitlab.freedesktop.org/drm/intel/issues/4303
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#6559]: https://gitlab.freedesktop.org/drm/intel/issues/6559
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7056]: https://gitlab.freedesktop.org/drm/intel/issues/7056
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7498]: https://gitlab.freedesktop.org/drm/intel/issues/7498
Build changes
-------------
* Linux: CI_DRM_12397 -> Patchwork_111050v1
CI-20190529: 20190529
CI_DRM_12397: a9ef9d744f7292d5bc02fc19734e1156a240ead6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7066: 2470b918175f314fef2e4e8ef0aa8acafb4ff945 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111050v1: a9ef9d744f7292d5bc02fc19734e1156a240ead6 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4ad66a7ebba8 drm/i915/uc: Update the gt/uc code to use gt_err and friends
04da248367fb drm/i915/guc: Add GuC CT specific debug print wrappers
6e3ec7581642 drm/i915/guc: Add GuC specific debug print wrappers
39cca4650223 drm/i915/huc: Add HuC specific debug print wrappers
e005fd235ffa drm/i915/gt: Start adding module oriented dmesg output
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/index.html
[-- Attachment #2: Type: text/html, Size: 9264 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH v2 0/5] Add module oriented dmesg output
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
@ 2022-11-18 10:52 ` Jani Nikula
-1 siblings, 0 replies; 51+ messages in thread
From: Jani Nikula @ 2022-11-18 10:52 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX; +Cc: Tvrtko Ursulin, DRI-Devel
On Thu, 17 Nov 2022, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> When trying to analyse bug reports from CI, customers, etc. it can be
> difficult to work out exactly what is happening on which GT in a
> multi-GT system. So add GT oriented debug/error message wrappers. If
> used instead of the drm_ equivalents, you get the same output but with
> a GT# prefix on it.
>
> It was also requested to extend this further to submodules in order to
> factor out the repeated structure accessing constructs and common
> string prefixes. So, add versions for GuC, HuC and GuC CTB as well.
>
> This patch set updates all the gt/uc files to use the new helpers as a
> first step. The intention would be to convert all output messages that
> have access to a GT structure.
>
> v2: Go back to using lower case names, add more wrapper sets (combined
> review feedback). Also, wrap up probe injection and WARN entries.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
For adding the wrappers in general, I'm going to disagree and
commit. I'll leave it up to Tvrtko and Joonas.
Regarding the placement of the macros, I insist you add individual
header files for the wrappers and include them only where needed.
We have a fairly serious problem with everything including everything in
i915 that I've been slowly trying to tackle. Touch one thing, rebuild
everything. About a third of our headers cause the rebuild of the entire
driver when modified. We need to reduce the surface of things that cause
rebuilds.
For example, intel_gt.h is included by 97 files, intel_guc.h by 332
files, and intel_huc.h by 329 files (counting recursively).
There's absolutely no reason any of the display code, for example, needs
to have these logging macros in their build. Long term, the headers
should be reorganized to reduce the interdependencies, and this is what
I've been doing in i915_drv.h and display/ in general. But the least we
can do is not make the problem worse.
BR,
Jani.
>
>
> John Harrison (5):
> drm/i915/gt: Start adding module oriented dmesg output
> drm/i915/huc: Add HuC specific debug print wrappers
> drm/i915/guc: Add GuC specific debug print wrappers
> drm/i915/guc: Add GuC CT specific debug print wrappers
> drm/i915/uc: Update the gt/uc code to use gt_err and friends
>
> drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++++----
> drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 +--
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +-
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 ++--
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++---------
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++-
> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 ++---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++--
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 +--
> drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 ++
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 108 ++++-----
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 98 ++++----
> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +--
> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +-
> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +-
> 19 files changed, 507 insertions(+), 475 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/5] Add module oriented dmesg output
@ 2022-11-18 10:52 ` Jani Nikula
0 siblings, 0 replies; 51+ messages in thread
From: Jani Nikula @ 2022-11-18 10:52 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
On Thu, 17 Nov 2022, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> When trying to analyse bug reports from CI, customers, etc. it can be
> difficult to work out exactly what is happening on which GT in a
> multi-GT system. So add GT oriented debug/error message wrappers. If
> used instead of the drm_ equivalents, you get the same output but with
> a GT# prefix on it.
>
> It was also requested to extend this further to submodules in order to
> factor out the repeated structure accessing constructs and common
> string prefixes. So, add versions for GuC, HuC and GuC CTB as well.
>
> This patch set updates all the gt/uc files to use the new helpers as a
> first step. The intention would be to convert all output messages that
> have access to a GT structure.
>
> v2: Go back to using lower case names, add more wrapper sets (combined
> review feedback). Also, wrap up probe injection and WARN entries.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
For adding the wrappers in general, I'm going to disagree and
commit. I'll leave it up to Tvrtko and Joonas.
Regarding the placement of the macros, I insist you add individual
header files for the wrappers and include them only where needed.
We have a fairly serious problem with everything including everything in
i915 that I've been slowly trying to tackle. Touch one thing, rebuild
everything. About a third of our headers cause the rebuild of the entire
driver when modified. We need to reduce the surface of things that cause
rebuilds.
For example, intel_gt.h is included by 97 files, intel_guc.h by 332
files, and intel_huc.h by 329 files (counting recursively).
There's absolutely no reason any of the display code, for example, needs
to have these logging macros in their build. Long term, the headers
should be reorganized to reduce the interdependencies, and this is what
I've been doing in i915_drv.h and display/ in general. But the least we
can do is not make the problem worse.
BR,
Jani.
>
>
> John Harrison (5):
> drm/i915/gt: Start adding module oriented dmesg output
> drm/i915/huc: Add HuC specific debug print wrappers
> drm/i915/guc: Add GuC specific debug print wrappers
> drm/i915/guc: Add GuC CT specific debug print wrappers
> drm/i915/uc: Update the gt/uc code to use gt_err and friends
>
> drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++++----
> drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 +--
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +-
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 ++--
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++---------
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++-
> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 ++---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++--
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 +--
> drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 ++
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 108 ++++-----
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 98 ++++----
> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +--
> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +-
> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +-
> 19 files changed, 507 insertions(+), 475 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/5] Add module oriented dmesg output
2022-11-18 10:52 ` Jani Nikula
@ 2022-11-21 18:21 ` John Harrison
-1 siblings, 0 replies; 51+ messages in thread
From: John Harrison @ 2022-11-21 18:21 UTC (permalink / raw)
To: Jani Nikula, Intel-GFX, Michal Wajdeczko; +Cc: Tvrtko Ursulin, DRI-Devel
On 11/18/2022 02:52, Jani Nikula wrote:
> On Thu, 17 Nov 2022, John.C.Harrison@Intel.com wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> When trying to analyse bug reports from CI, customers, etc. it can be
>> difficult to work out exactly what is happening on which GT in a
>> multi-GT system. So add GT oriented debug/error message wrappers. If
>> used instead of the drm_ equivalents, you get the same output but with
>> a GT# prefix on it.
>>
>> It was also requested to extend this further to submodules in order to
>> factor out the repeated structure accessing constructs and common
>> string prefixes. So, add versions for GuC, HuC and GuC CTB as well.
>>
>> This patch set updates all the gt/uc files to use the new helpers as a
>> first step. The intention would be to convert all output messages that
>> have access to a GT structure.
>>
>> v2: Go back to using lower case names, add more wrapper sets (combined
>> review feedback). Also, wrap up probe injection and WARN entries.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> For adding the wrappers in general, I'm going to disagree and
> commit. I'll leave it up to Tvrtko and Joonas.
>
> Regarding the placement of the macros, I insist you add individual
> header files for the wrappers and include them only where needed.
>
> We have a fairly serious problem with everything including everything in
> i915 that I've been slowly trying to tackle. Touch one thing, rebuild
> everything. About a third of our headers cause the rebuild of the entire
> driver when modified. We need to reduce the surface of things that cause
> rebuilds.
>
> For example, intel_gt.h is included by 97 files, intel_guc.h by 332
> files, and intel_huc.h by 329 files (counting recursively).
>
> There's absolutely no reason any of the display code, for example, needs
> to have these logging macros in their build. Long term, the headers
> should be reorganized to reduce the interdependencies, and this is what
> I've been doing in i915_drv.h and display/ in general. But the least we
> can do is not make the problem worse.
@Tvrtko/@Michal W, any other review comments or feedback? I'd rather not
spend time fixing up the header file issue and reposting only to have
someone point out another issue that could have been resolved at the
same time.
John.
> BR,
> Jani.
>
>>
>> John Harrison (5):
>> drm/i915/gt: Start adding module oriented dmesg output
>> drm/i915/huc: Add HuC specific debug print wrappers
>> drm/i915/guc: Add GuC specific debug print wrappers
>> drm/i915/guc: Add GuC CT specific debug print wrappers
>> drm/i915/uc: Update the gt/uc code to use gt_err and friends
>>
>> drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++++----
>> drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++
>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 +--
>> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +-
>> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 ++--
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++---------
>> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 ++---
>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++--
>> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 +--
>> drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 ++
>> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 108 ++++-----
>> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 98 ++++----
>> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +--
>> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +-
>> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +-
>> 19 files changed, 507 insertions(+), 475 deletions(-)
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/5] Add module oriented dmesg output
@ 2022-11-21 18:21 ` John Harrison
0 siblings, 0 replies; 51+ messages in thread
From: John Harrison @ 2022-11-21 18:21 UTC (permalink / raw)
To: Jani Nikula, Intel-GFX, Michal Wajdeczko; +Cc: DRI-Devel
On 11/18/2022 02:52, Jani Nikula wrote:
> On Thu, 17 Nov 2022, John.C.Harrison@Intel.com wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> When trying to analyse bug reports from CI, customers, etc. it can be
>> difficult to work out exactly what is happening on which GT in a
>> multi-GT system. So add GT oriented debug/error message wrappers. If
>> used instead of the drm_ equivalents, you get the same output but with
>> a GT# prefix on it.
>>
>> It was also requested to extend this further to submodules in order to
>> factor out the repeated structure accessing constructs and common
>> string prefixes. So, add versions for GuC, HuC and GuC CTB as well.
>>
>> This patch set updates all the gt/uc files to use the new helpers as a
>> first step. The intention would be to convert all output messages that
>> have access to a GT structure.
>>
>> v2: Go back to using lower case names, add more wrapper sets (combined
>> review feedback). Also, wrap up probe injection and WARN entries.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> For adding the wrappers in general, I'm going to disagree and
> commit. I'll leave it up to Tvrtko and Joonas.
>
> Regarding the placement of the macros, I insist you add individual
> header files for the wrappers and include them only where needed.
>
> We have a fairly serious problem with everything including everything in
> i915 that I've been slowly trying to tackle. Touch one thing, rebuild
> everything. About a third of our headers cause the rebuild of the entire
> driver when modified. We need to reduce the surface of things that cause
> rebuilds.
>
> For example, intel_gt.h is included by 97 files, intel_guc.h by 332
> files, and intel_huc.h by 329 files (counting recursively).
>
> There's absolutely no reason any of the display code, for example, needs
> to have these logging macros in their build. Long term, the headers
> should be reorganized to reduce the interdependencies, and this is what
> I've been doing in i915_drv.h and display/ in general. But the least we
> can do is not make the problem worse.
@Tvrtko/@Michal W, any other review comments or feedback? I'd rather not
spend time fixing up the header file issue and reposting only to have
someone point out another issue that could have been resolved at the
same time.
John.
> BR,
> Jani.
>
>>
>> John Harrison (5):
>> drm/i915/gt: Start adding module oriented dmesg output
>> drm/i915/huc: Add HuC specific debug print wrappers
>> drm/i915/guc: Add GuC specific debug print wrappers
>> drm/i915/guc: Add GuC CT specific debug print wrappers
>> drm/i915/uc: Update the gt/uc code to use gt_err and friends
>>
>> drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++++----
>> drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++
>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 +--
>> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +-
>> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 ++--
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++---------
>> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 ++---
>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++--
>> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 +--
>> drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 ++
>> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 108 ++++-----
>> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 98 ++++----
>> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +--
>> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +-
>> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +-
>> 19 files changed, 507 insertions(+), 475 deletions(-)
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/5] Add module oriented dmesg output
2022-11-21 18:21 ` John Harrison
(?)
@ 2022-11-22 8:14 ` Tvrtko Ursulin
-1 siblings, 0 replies; 51+ messages in thread
From: Tvrtko Ursulin @ 2022-11-22 8:14 UTC (permalink / raw)
To: John Harrison, Jani Nikula, Intel-GFX, Michal Wajdeczko; +Cc: DRI-Devel
On 21/11/2022 18:21, John Harrison wrote:
> On 11/18/2022 02:52, Jani Nikula wrote:
>> On Thu, 17 Nov 2022, John.C.Harrison@Intel.com wrote:
>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>
>>> When trying to analyse bug reports from CI, customers, etc. it can be
>>> difficult to work out exactly what is happening on which GT in a
>>> multi-GT system. So add GT oriented debug/error message wrappers. If
>>> used instead of the drm_ equivalents, you get the same output but with
>>> a GT# prefix on it.
>>>
>>> It was also requested to extend this further to submodules in order to
>>> factor out the repeated structure accessing constructs and common
>>> string prefixes. So, add versions for GuC, HuC and GuC CTB as well.
>>>
>>> This patch set updates all the gt/uc files to use the new helpers as a
>>> first step. The intention would be to convert all output messages that
>>> have access to a GT structure.
>>>
>>> v2: Go back to using lower case names, add more wrapper sets (combined
>>> review feedback). Also, wrap up probe injection and WARN entries.
>>>
>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> For adding the wrappers in general, I'm going to disagree and
>> commit. I'll leave it up to Tvrtko and Joonas.
>>
>> Regarding the placement of the macros, I insist you add individual
>> header files for the wrappers and include them only where needed.
>>
>> We have a fairly serious problem with everything including everything in
>> i915 that I've been slowly trying to tackle. Touch one thing, rebuild
>> everything. About a third of our headers cause the rebuild of the entire
>> driver when modified. We need to reduce the surface of things that cause
>> rebuilds.
>>
>> For example, intel_gt.h is included by 97 files, intel_guc.h by 332
>> files, and intel_huc.h by 329 files (counting recursively).
>>
>> There's absolutely no reason any of the display code, for example, needs
>> to have these logging macros in their build. Long term, the headers
>> should be reorganized to reduce the interdependencies, and this is what
>> I've been doing in i915_drv.h and display/ in general. But the least we
>> can do is not make the problem worse.
> @Tvrtko/@Michal W, any other review comments or feedback? I'd rather not
> spend time fixing up the header file issue and reposting only to have
> someone point out another issue that could have been resolved at the
> same time.
I read through the patches when you posted them and it looked nice and
clean to me. I think I spotted one instance of a debug build only
message getting upgraded to production build, and one loss of stack
trace on a warning, but it wasn't a concern to me AFAIR.
Regards,
Tvrtko
>
> John.
>
>> BR,
>> Jani.
>>
>>>
>>> John Harrison (5):
>>> drm/i915/gt: Start adding module oriented dmesg output
>>> drm/i915/huc: Add HuC specific debug print wrappers
>>> drm/i915/guc: Add GuC specific debug print wrappers
>>> drm/i915/guc: Add GuC CT specific debug print wrappers
>>> drm/i915/uc: Update the gt/uc code to use gt_err and friends
>>>
>>> drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++++----
>>> drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++
>>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 +--
>>> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +-
>>> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 ++--
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++---------
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +-
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++-
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +-
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 ++---
>>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++--
>>> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 +--
>>> drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 ++
>>> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 108 ++++-----
>>> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 98 ++++----
>>> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +--
>>> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +-
>>> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +-
>>> 19 files changed, 507 insertions(+), 475 deletions(-)
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/5] Add module oriented dmesg output
2022-11-18 10:52 ` Jani Nikula
(?)
(?)
@ 2022-11-22 16:35 ` Michal Wajdeczko
2022-11-22 18:21 ` Jani Nikula
-1 siblings, 1 reply; 51+ messages in thread
From: Michal Wajdeczko @ 2022-11-22 16:35 UTC (permalink / raw)
To: Jani Nikula, John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
On 18.11.2022 11:52, Jani Nikula wrote:
> On Thu, 17 Nov 2022, John.C.Harrison@Intel.com wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> When trying to analyse bug reports from CI, customers, etc. it can be
>> difficult to work out exactly what is happening on which GT in a
>> multi-GT system. So add GT oriented debug/error message wrappers. If
>> used instead of the drm_ equivalents, you get the same output but with
>> a GT# prefix on it.
>>
>> It was also requested to extend this further to submodules in order to
>> factor out the repeated structure accessing constructs and common
>> string prefixes. So, add versions for GuC, HuC and GuC CTB as well.
>>
>> This patch set updates all the gt/uc files to use the new helpers as a
>> first step. The intention would be to convert all output messages that
>> have access to a GT structure.
>>
>> v2: Go back to using lower case names, add more wrapper sets (combined
>> review feedback). Also, wrap up probe injection and WARN entries.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>
> For adding the wrappers in general, I'm going to disagree and
> commit. I'll leave it up to Tvrtko and Joonas.
>
> Regarding the placement of the macros, I insist you add individual
> header files for the wrappers and include them only where needed.
do you mean:
intel_gt_print.h
intel_guc_print.h
intel_huc_print.h
with just macros or also with all functions that work with drm_printer?
>
> We have a fairly serious problem with everything including everything in
> i915 that I've been slowly trying to tackle. Touch one thing, rebuild
> everything. About a third of our headers cause the rebuild of the entire
> driver when modified. We need to reduce the surface of things that cause
> rebuilds.
>
> For example, intel_gt.h is included by 97 files, intel_guc.h by 332
> files, and intel_huc.h by 329 files (counting recursively).
>
> There's absolutely no reason any of the display code, for example, needs
> to have these logging macros in their build. Long term, the headers
> should be reorganized to reduce the interdependencies, and this is what
> I've been doing in i915_drv.h and display/ in general. But the least we
> can do is not make the problem worse.
to solve this we should really consider splitting out GuC and HuC
definitions to dedicated _types.h files and only include them in
i915_drv.h (and print macros are orthogonal for this problem)
Michal
>
> BR,
> Jani.
>
>>
>>
>> John Harrison (5):
>> drm/i915/gt: Start adding module oriented dmesg output
>> drm/i915/huc: Add HuC specific debug print wrappers
>> drm/i915/guc: Add GuC specific debug print wrappers
>> drm/i915/guc: Add GuC CT specific debug print wrappers
>> drm/i915/uc: Update the gt/uc code to use gt_err and friends
>>
>> drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++++----
>> drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++
>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 +--
>> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +-
>> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 ++--
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++---------
>> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 ++---
>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++--
>> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 +--
>> drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 ++
>> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 108 ++++-----
>> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 98 ++++----
>> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +--
>> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +-
>> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +-
>> 19 files changed, 507 insertions(+), 475 deletions(-)
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/5] Add module oriented dmesg output
2022-11-22 16:35 ` Michal Wajdeczko
@ 2022-11-22 18:21 ` Jani Nikula
0 siblings, 0 replies; 51+ messages in thread
From: Jani Nikula @ 2022-11-22 18:21 UTC (permalink / raw)
To: Michal Wajdeczko, John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
On Tue, 22 Nov 2022, Michal Wajdeczko <michal.wajdeczko@intel.com> wrote:
> On 18.11.2022 11:52, Jani Nikula wrote:
>> On Thu, 17 Nov 2022, John.C.Harrison@Intel.com wrote:
>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>
>>> When trying to analyse bug reports from CI, customers, etc. it can be
>>> difficult to work out exactly what is happening on which GT in a
>>> multi-GT system. So add GT oriented debug/error message wrappers. If
>>> used instead of the drm_ equivalents, you get the same output but with
>>> a GT# prefix on it.
>>>
>>> It was also requested to extend this further to submodules in order to
>>> factor out the repeated structure accessing constructs and common
>>> string prefixes. So, add versions for GuC, HuC and GuC CTB as well.
>>>
>>> This patch set updates all the gt/uc files to use the new helpers as a
>>> first step. The intention would be to convert all output messages that
>>> have access to a GT structure.
>>>
>>> v2: Go back to using lower case names, add more wrapper sets (combined
>>> review feedback). Also, wrap up probe injection and WARN entries.
>>>
>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>
>> For adding the wrappers in general, I'm going to disagree and
>> commit. I'll leave it up to Tvrtko and Joonas.
>>
>> Regarding the placement of the macros, I insist you add individual
>> header files for the wrappers and include them only where needed.
>
> do you mean:
>
> intel_gt_print.h
> intel_guc_print.h
> intel_huc_print.h
>
> with just macros or also with all functions that work with drm_printer?
At least for the macros being added now. If adding others does not
require you to pull in a bunch of additional header dependencies, you
can add more. And that can be separate patches.
>
>>
>> We have a fairly serious problem with everything including everything in
>> i915 that I've been slowly trying to tackle. Touch one thing, rebuild
>> everything. About a third of our headers cause the rebuild of the entire
>> driver when modified. We need to reduce the surface of things that cause
>> rebuilds.
>>
>> For example, intel_gt.h is included by 97 files, intel_guc.h by 332
>> files, and intel_huc.h by 329 files (counting recursively).
>>
>> There's absolutely no reason any of the display code, for example, needs
>> to have these logging macros in their build. Long term, the headers
>> should be reorganized to reduce the interdependencies, and this is what
>> I've been doing in i915_drv.h and display/ in general. But the least we
>> can do is not make the problem worse.
>
> to solve this we should really consider splitting out GuC and HuC
> definitions to dedicated _types.h files and only include them in
> i915_drv.h (and print macros are orthogonal for this problem)
It's an orthogonal problem, but IMO with the current headers there's no
reason to make the problem worse by adding somewhat independent new
stuff to the headers.
---
I've looked at untangling this a bunch of times, but I've always felt
that it's really not my area of expertise, and it would inevitably
conflict with someone else's work in progress and someone else's idea of
how the headers should be refactored.
There are chains like this:
i915_drv.h:47:#include "gt/intel_gt_types.h"
gt/intel_gt_types.h:19:#include "uc/intel_uc.h"
gt/uc/intel_uc.h:9:#include "intel_guc.h"
gt/uc/intel_guc.h:15:#include "intel_guc_fwif.h"
gt/uc/intel_guc_fwif.h:14:#include "abi/guc_actions_abi.h"
gt/uc/intel_guc_fwif.h:15:#include "abi/guc_actions_slpc_abi.h"
gt/uc/intel_guc_fwif.h:16:#include "abi/guc_errors_abi.h"
gt/uc/intel_guc_fwif.h:17:#include "abi/guc_communication_mmio_abi.h"
gt/uc/intel_guc_fwif.h:18:#include "abi/guc_communication_ctb_abi.h"
gt/uc/intel_guc_fwif.h:19:#include "abi/guc_klvs_abi.h"
gt/uc/intel_guc_fwif.h:20:#include "abi/guc_messages_abi.h"
They need to be broken up at some point. There are a bunch of headers
where only minimal amount of info is actually needed in other headers,
and the rest is used in a limited number of .c files only.
It's a lot of tedious work to refactor and nobody's going to notice the
impact directly, they'll just be less grumpy about the build being slow
and the organization of the headers being messy. And if they don't build
the driver a lot (like me) or don't refactor the driver a lot (like me)
maybe they'll never notice.
BR,
Jani.
>
> Michal
>
>>
>> BR,
>> Jani.
>>
>>>
>>>
>>> John Harrison (5):
>>> drm/i915/gt: Start adding module oriented dmesg output
>>> drm/i915/huc: Add HuC specific debug print wrappers
>>> drm/i915/guc: Add GuC specific debug print wrappers
>>> drm/i915/guc: Add GuC CT specific debug print wrappers
>>> drm/i915/uc: Update the gt/uc code to use gt_err and friends
>>>
>>> drivers/gpu/drm/i915/gt/intel_gt.c | 96 ++++----
>>> drivers/gpu/drm/i915/gt/intel_gt.h | 35 +++
>>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 32 +--
>>> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 35 +++
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 +-
>>> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 48 ++--
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++++++++---------
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +-
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 37 ++-
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +-
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 ++---
>>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++--
>>> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 +--
>>> drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 ++
>>> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 108 ++++-----
>>> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 98 ++++----
>>> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +--
>>> .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +-
>>> .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +-
>>> 19 files changed, 507 insertions(+), 475 deletions(-)
>>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 51+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Add module oriented dmesg output
2022-11-18 1:58 ` [Intel-gfx] " John.C.Harrison
` (9 preceding siblings ...)
(?)
@ 2022-11-18 19:37 ` Patchwork
-1 siblings, 0 replies; 51+ messages in thread
From: Patchwork @ 2022-11-18 19:37 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 32356 bytes --]
== Series Details ==
Series: Add module oriented dmesg output
URL : https://patchwork.freedesktop.org/series/111050/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12397_full -> Patchwork_111050v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_111050v1_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_mmap_write_crc@main:
- {shard-dg1}: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-dg1-17/igt@kms_mmap_write_crc@main.html
Known issues
------------
Here are the changes found in Patchwork_111050v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][2] -> [SKIP][3] ([i915#4525]) +1 similar issue
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb5/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2842])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl10/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#5566] / [i915#716])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-glk1/igt@gen9_exec_parse@allowed-single.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-glk7/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#3989] / [i915#454])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb5/igt@i915_pm_dc@dc6-dpms.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-skl: [PASS][11] -> [WARN][12] ([i915#1804])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-skl9/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl4/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][13] ([i915#3763])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl10/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3886])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl10/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271]) +61 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl10/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs.html
* igt@kms_chamelium@hdmi-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +2 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl10/igt@kms_chamelium@hdmi-crc-multiple.html
* igt@kms_chamelium@hdmi-crc-single:
- shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-apl6/igt@kms_chamelium@hdmi-crc-single.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#79])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [PASS][20] -> [FAIL][21] ([i915#79])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][22] ([i915#2587] / [i915#2672]) +5 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][23] ([i915#3555])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][24] ([i915#2672]) +4 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#2672] / [i915#3555])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271]) +5 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-apl6/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1:
- shard-iclb: [PASS][27] -> [SKIP][28] ([i915#5235]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
* igt@kms_psr2_su@page_flip-p010:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#109642] / [fdo#111068] / [i915#658])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb7/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][30] -> [SKIP][31] ([fdo#109441]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-skl: [PASS][32] -> [SKIP][33] ([fdo#109271])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-skl1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@perf@non-zero-reason:
- shard-skl: NOTRUN -> [TIMEOUT][34] ([i915#6943])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl1/igt@perf@non-zero-reason.html
* igt@perf@oa-exponents:
- shard-glk: [PASS][35] -> [INCOMPLETE][36] ([i915#5213])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-glk9/igt@perf@oa-exponents.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-glk1/igt@perf@oa-exponents.html
* igt@perf_pmu@interrupts:
- shard-skl: [PASS][37] -> [FAIL][38] ([i915#7318])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-skl9/igt@perf_pmu@interrupts.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl6/igt@perf_pmu@interrupts.html
* igt@sysfs_clients@busy:
- shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#2994])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-apl6/igt@sysfs_clients@busy.html
* igt@sysfs_clients@split-10:
- shard-skl: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#2994])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl10/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@fbdev@eof:
- {shard-rkl}: [SKIP][41] ([i915#2582]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-5/igt@fbdev@eof.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-6/igt@fbdev@eof.html
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][43] ([i915#658]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb7/igt@feature_discovery@psr2.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_bad_reloc@negative-reloc:
- {shard-rkl}: [SKIP][45] ([i915#3281]) -> [PASS][46] +14 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-6/igt@gem_bad_reloc@negative-reloc.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-5/igt@gem_bad_reloc@negative-reloc.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-rkl}: [FAIL][47] ([i915#6268]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-1/igt@gem_ctx_exec@basic-nohangcheck.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-5/igt@gem_ctx_exec@basic-nohangcheck.html
- shard-tglb: [FAIL][49] ([i915#6268]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-tglb2/igt@gem_ctx_exec@basic-nohangcheck.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-tglb6/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@suspend:
- {shard-rkl}: [FAIL][51] ([i915#7052]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-3/igt@gem_eio@suspend.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-1/igt@gem_eio@suspend.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][53] ([i915#4525]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_endless@dispatch@bcs0:
- {shard-rkl}: [SKIP][55] ([i915#6247]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-5/igt@gem_exec_endless@dispatch@bcs0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-3/igt@gem_exec_endless@dispatch@bcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][57] ([i915#2846]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-glk7/igt@gem_exec_fair@basic-deadline.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-glk9/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][59] ([i915#2842]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- {shard-rkl}: [SKIP][61] ([i915#3282]) -> [PASS][62] +6 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gen9_exec_parse@bb-start-cmd:
- {shard-rkl}: [SKIP][63] ([i915#2527]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-4/igt@gen9_exec_parse@bb-start-cmd.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-5/igt@gen9_exec_parse@bb-start-cmd.html
* igt@i915_pipe_stress@stress-xrgb8888-ytiled:
- {shard-rkl}: [SKIP][65] ([i915#4098]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-5/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-6/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}: [WARN][67] ([i915#2681]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-3/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rpm@cursor:
- {shard-rkl}: [SKIP][69] ([i915#1849]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-3/igt@i915_pm_rpm@cursor.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-6/igt@i915_pm_rpm@cursor.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [DMESG-FAIL][71] ([i915#5334]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-apl8/igt@i915_selftest@live@gt_heartbeat.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-apl6/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- {shard-rkl}: [SKIP][73] ([i915#1845] / [i915#4098]) -> [PASS][74] +13 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-5/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-snb: [DMESG-WARN][75] ([i915#5090]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-snb6/igt@kms_fbcon_fbt@fbc-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-snb6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-apl: [DMESG-WARN][77] ([i915#180]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-apl8/igt@kms_flip@flip-vs-suspend@b-dp1.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-apl6/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [FAIL][79] ([i915#2122]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- {shard-rkl}: [SKIP][81] ([i915#1849] / [i915#4098]) -> [PASS][82] +14 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-glk: [FAIL][83] ([i915#2546]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-glk6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
- shard-apl: [FAIL][85] ([i915#1188]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-apl7/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-apl7/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
* igt@kms_psr@primary_page_flip:
- {shard-rkl}: [SKIP][87] ([i915#1072]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-3/igt@kms_psr@primary_page_flip.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-6/igt@kms_psr@primary_page_flip.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][89] ([fdo#109441]) -> [PASS][90] +2 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb5/igt@kms_psr@psr2_basic.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb2/igt@kms_psr@psr2_basic.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-tglb: [SKIP][91] ([i915#5519]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-tglb3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-tglb8/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
- {shard-rkl}: [SKIP][93] ([i915#5461]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@perf@gen12-unprivileged-single-ctx-counters:
- {shard-rkl}: [SKIP][95] ([fdo#109289]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-5/igt@perf@gen12-unprivileged-single-ctx-counters.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-4/igt@perf@gen12-unprivileged-single-ctx-counters.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- {shard-rkl}: [SKIP][97] ([i915#2436]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-6/igt@perf@gen8-unprivileged-single-ctx-counters.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-5/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf_pmu@idle@rcs0:
- {shard-dg1}: [FAIL][99] ([i915#4349]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-dg1-12/igt@perf_pmu@idle@rcs0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-dg1-15/igt@perf_pmu@idle@rcs0.html
* igt@prime_vgem@coherency-gtt:
- {shard-rkl}: [SKIP][101] ([fdo#109295] / [fdo#111656] / [i915#3708]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-rkl-1/igt@prime_vgem@coherency-gtt.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-rkl-5/igt@prime_vgem@coherency-gtt.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][103] ([i915#4525]) -> [FAIL][104] ([i915#6117])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_pread@exhaustion:
- shard-apl: [INCOMPLETE][105] ([i915#7248]) -> [WARN][106] ([i915#2658]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-apl1/igt@gem_pread@exhaustion.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-apl3/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-tglb: [WARN][107] ([i915#2658]) -> [INCOMPLETE][108] ([i915#7248])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-tglb5/igt@gem_pwrite@basic-exhaustion.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-tglb1/igt@gem_pwrite@basic-exhaustion.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][109] ([i915#658]) -> [SKIP][110] ([i915#588])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb3/igt@i915_pm_dc@dc3co-vpb-simulation.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][111] ([i915#658]) -> [SKIP][112] ([i915#2920])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb5/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][113] ([fdo#111068] / [i915#658]) -> [SKIP][114] ([i915#2920])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-iclb: [SKIP][115] ([i915#2920]) -> [SKIP][116] ([i915#658])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2532]: https://gitlab.freedesktop.org/drm/intel/issues/2532
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3692]: https://gitlab.freedesktop.org/drm/intel/issues/3692
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3763]: https://gitlab.freedesktop.org/drm/intel/issues/3763
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4998]: https://gitlab.freedesktop.org/drm/intel/issues/4998
[i915#5090]: https://gitlab.freedesktop.org/drm/intel/issues/5090
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6943]: https://gitlab.freedesktop.org/drm/intel/issues/6943
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
[i915#7318]: https://gitlab.freedesktop.org/drm/intel/issues/7318
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12397 -> Patchwork_111050v1
CI-20190529: 20190529
CI_DRM_12397: a9ef9d744f7292d5bc02fc19734e1156a240ead6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7066: 2470b918175f314fef2e4e8ef0aa8acafb4ff945 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111050v1: a9ef9d744f7292d5bc02fc19734e1156a240ead6 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/index.html
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