* [PATCH 01/14] drm: add MIPI DSI encoder and connector types
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
2013-08-13 13:29 ` [PATCH 02/14] drm/i915: add more VLV IOSF sideband ports accessors Jani Nikula
` (12 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
From: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_crtc.c | 2 ++
include/uapi/drm/drm_mode.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index fc83bb9..8768c5f 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -209,6 +209,7 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] =
{ DRM_MODE_CONNECTOR_TV, "TV", 0 },
{ DRM_MODE_CONNECTOR_eDP, "eDP", 0 },
{ DRM_MODE_CONNECTOR_VIRTUAL, "Virtual", 0},
+ { DRM_MODE_CONNECTOR_DSI, "DSI", 0},
};
static const struct drm_prop_enum_list drm_encoder_enum_list[] =
@@ -218,6 +219,7 @@ static const struct drm_prop_enum_list drm_encoder_enum_list[] =
{ DRM_MODE_ENCODER_LVDS, "LVDS" },
{ DRM_MODE_ENCODER_TVDAC, "TV" },
{ DRM_MODE_ENCODER_VIRTUAL, "Virtual" },
+ { DRM_MODE_ENCODER_DSI, "DSI" },
};
const char *drm_get_encoder_name(const struct drm_encoder *encoder)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 53db7ce..589114e 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -165,6 +165,7 @@ struct drm_mode_get_plane_res {
#define DRM_MODE_ENCODER_LVDS 3
#define DRM_MODE_ENCODER_TVDAC 4
#define DRM_MODE_ENCODER_VIRTUAL 5
+#define DRM_MODE_ENCODER_DSI 6
struct drm_mode_get_encoder {
__u32 encoder_id;
@@ -203,6 +204,7 @@ struct drm_mode_get_encoder {
#define DRM_MODE_CONNECTOR_TV 13
#define DRM_MODE_CONNECTOR_eDP 14
#define DRM_MODE_CONNECTOR_VIRTUAL 15
+#define DRM_MODE_CONNECTOR_DSI 16
struct drm_mode_get_connector {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 02/14] drm/i915: add more VLV IOSF sideband ports accessors
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
2013-08-13 13:29 ` [PATCH 01/14] drm: add MIPI DSI encoder and connector types Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
2013-08-13 13:29 ` [PATCH 03/14] drm/i915: add VLV pipeconf bit definition for DSI PLL lock Jani Nikula
` (11 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
For GPIO NC, CCK, CCU, and GPS CORE.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 8 +++++
drivers/gpu/drm/i915/i915_reg.h | 4 +++
drivers/gpu/drm/i915/intel_sideband.c | 56 +++++++++++++++++++++++++++++++++
3 files changed, 68 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dcae809..6db95a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2164,6 +2164,14 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 17f6252..a30e876 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -360,6 +360,10 @@
#define IOSF_PORT_PUNIT 0x4
#define IOSF_PORT_NC 0x11
#define IOSF_PORT_DPIO 0x12
+#define IOSF_PORT_GPIO_NC 0x13
+#define IOSF_PORT_CCK 0x14
+#define IOSF_PORT_CCU 0xA9
+#define IOSF_PORT_GPS_CORE 0x48
#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 9a0e6c5..0a41670 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -101,6 +101,62 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
return val;
}
+u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+ u32 val = 0;
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
+ PUNIT_OPCODE_REG_READ, reg, &val);
+ return val;
+}
+
+void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
+ PUNIT_OPCODE_REG_WRITE, reg, &val);
+}
+
+u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+ u32 val = 0;
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
+ PUNIT_OPCODE_REG_READ, reg, &val);
+ return val;
+}
+
+void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
+ PUNIT_OPCODE_REG_WRITE, reg, &val);
+}
+
+u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+ u32 val = 0;
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
+ PUNIT_OPCODE_REG_READ, reg, &val);
+ return val;
+}
+
+void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
+ PUNIT_OPCODE_REG_WRITE, reg, &val);
+}
+
+u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+ u32 val = 0;
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
+ PUNIT_OPCODE_REG_READ, reg, &val);
+ return val;
+}
+
+void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
+ PUNIT_OPCODE_REG_WRITE, reg, &val);
+}
+
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg)
{
u32 val = 0;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 03/14] drm/i915: add VLV pipeconf bit definition for DSI PLL lock
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
2013-08-13 13:29 ` [PATCH 01/14] drm: add MIPI DSI encoder and connector types Jani Nikula
2013-08-13 13:29 ` [PATCH 02/14] drm/i915: add more VLV IOSF sideband ports accessors Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
2013-08-13 13:29 ` [PATCH 04/14] drm/i915: add MIPI DSI register definitions Jani Nikula
` (10 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a30e876..aced53a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2972,6 +2972,7 @@
#define PIPECONF_DISABLE 0
#define PIPECONF_DOUBLE_WIDE (1<<30)
#define I965_PIPECONF_ACTIVE (1<<30)
+#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv only */
#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
#define PIPECONF_SINGLE_WIDE 0
#define PIPECONF_PIPE_UNLOCKED 0
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 04/14] drm/i915: add MIPI DSI register definitions
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
` (2 preceding siblings ...)
2013-08-13 13:29 ` [PATCH 03/14] drm/i915: add VLV pipeconf bit definition for DSI PLL lock Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
2013-08-14 13:59 ` Ville Syrjälä
2013-08-15 13:38 ` Damien Lespiau
2013-08-13 13:29 ` [PATCH 05/14] drm/i915: add MIPI DSI output type and subtypes Jani Nikula
` (9 subsequent siblings)
13 siblings, 2 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
Add definitions for VLV MIPI DSI registers.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 409 +++++++++++++++++++++++++++++++++++++++
1 file changed, 409 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aced53a..32e32b6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5104,4 +5104,413 @@
#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
+/* VLV MIPI registers */
+
+/* XXX: This register seems very messy. MIPIB has only enable and delay. */
+#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
+#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
+#define MIPI_PORT_CTRL(pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL)
+#define DPI_ENABLE (1 << 31) /* A + B */
+#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
+#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
+#define DUAL_LINK_MODE_MASK (1 << 26)
+#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
+#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
+#define FLOPPED_HSTX (1 << 23)
+#define DE_INVERT (1 << 19) /* XXX */
+#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
+#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
+#define AFE_LATCHOUT (1 << 17)
+#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
+#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
+#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11
+#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
+#define CSB_SHIFT 9
+#define CSB_MASK (3 << 9)
+#define CSB_20MHZ (0 << 9)
+#define CSB_10MHZ (1 << 9)
+#define CSB_40MHZ (2 << 9)
+#define BANDGAP_MASK (1 << 8)
+#define BANDGAP_PNW_CIRCUIT (0 << 8)
+#define BANDGAP_LNC_CIRCUIT (1 << 8)
+#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
+#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
+#define TEARING_EFFECT_DELAY (1 << 4) /* A + B */
+#define TEARING_EFFECT_SHIFT 2 /* A + B */
+#define TEARING_EFFECT_MASK (3 << 2)
+#define TEARING_EFFECT_OFF (0 << 2)
+#define TEARING_EFFECT_DSI (1 << 2)
+#define TEARING_EFFECT_GPIO (2 << 2)
+#define LANE_CONFIGURATION_SHIFT 0
+#define LANE_CONFIGURATION_MASK (3 << 0)
+#define LANE_CONFIGURATION_4LANE (0 << 0)
+#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
+#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
+
+#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
+#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
+#define MIPI_TEARING_CTRL(pipe) _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)
+#define TEARING_EFFECT_DELAY_SHIFT 0
+#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
+
+/* XXX */
+#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
+
+/* MIPI DSI Controller and D-PHY registers */
+
+#define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000)
+#define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800)
+#define MIPI_DEVICE_READY(pipe) _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY)
+#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
+#define ULPS_STATE_MASK (3 << 1)
+#define ULPS_STATE_ENTER (2 << 1) /* XXX */
+#define ULPS_STATE_EXIT (1 << 1) /* XXX */
+#define DEVICE_READY (1 << 0)
+
+#define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004)
+#define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804)
+#define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT)
+#define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008)
+#define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + 0xb808)
+#define MIPI_INTR_EN(pipe) _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN)
+#define TEARING_EFFECT (1 << 31)
+#define SPL_PKT_SENT_INTERRUPT (1 << 30)
+#define GEN_READ_DATA_AVAIL (1 << 29)
+#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
+#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
+#define RX_PROT_VIOLATION (1 << 26)
+#define RX_INVALID_TX_LENGTH (1 << 25)
+#define ACK_WITH_NO_ERROR (1 << 24)
+#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
+#define LP_RX_TIMEOUT (1 << 22)
+#define HS_TX_TIMEOUT (1 << 21)
+#define DPI_FIFO_UNDERRUN (1 << 20)
+#define LOW_CONTENTION (1 << 19)
+#define HIGH_CONTENTION (1 << 18)
+#define TXDSI_VC_ID_INVALID (1 << 17)
+#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
+#define TXCHECKSUM_ERROR (1 << 15)
+#define TXECC_MULTIBIT_ERROR (1 << 14)
+#define TXECC_SINGLE_BIT_ERROR (1 << 13)
+#define TXFALSE_CONTROL_ERROR (1 << 12)
+#define RXDSI_VC_ID_INVALID (1 << 11)
+#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
+#define RXCHECKSUM_ERROR (1 << 9)
+#define RXECC_MULTIBIT_ERROR (1 << 8)
+#define RXECC_SINGLE_BIT_ERROR (1 << 7)
+#define RXFALSE_CONTROL_ERROR (1 << 6)
+#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
+#define RX_LP_TX_SYNC_ERROR (1 << 4)
+#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
+#define RXEOT_SYNC_ERROR (1 << 2)
+#define RXSOT_SYNC_ERROR (1 << 1)
+#define RXSOT_ERROR (1 << 0)
+
+#define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c)
+#define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c)
+#define MIPI_DSI_FUNC_PRG(pipe) _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG)
+#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
+#define CMD_MODE_NOT_SUPPORTED (0 << 13)
+#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
+#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
+#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
+#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
+#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
+#define VID_MODE_FORMAT_MASK (0xf << 7)
+#define VID_MODE_NOT_SUPPORTED (0 << 7)
+#define VID_MODE_FORMAT_RGB565 (1 << 7)
+#define VID_MODE_FORMAT_RGB666 (2 << 7)
+#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
+#define VID_MODE_FORMAT_RGB888 (4 << 7)
+#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
+#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
+#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
+#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
+#define DATA_LANES_PRG_REG_SHIFT 0
+#define DATA_LANES_PRG_REG_MASK (7 << 0)
+
+#define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010)
+#define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810)
+#define MIPI_HS_TX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT)
+#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
+
+#define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014)
+#define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814)
+#define MIPI_LP_RX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT)
+#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
+
+#define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018)
+#define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818)
+#define MIPI_TURN_AROUND_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)
+#define TURN_AROUND_TIMEOUT_MASK 0x3f
+
+#define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c)
+#define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c)
+#define MIPI_DEVICE_RESET_TIMER(pipe) _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)
+#define DEVICE_RESET_TIMER_MASK 0xffff
+
+#define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb020)
+#define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb820)
+#define MIPI_DPI_RESOLUTION(pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION)
+#define VERTICAL_ADDRESS_SHIFT 16
+#define VERTICAL_ADDRESS_MASK (0xffff << 16)
+#define HORIZONTAL_ADDRESS_SHIFT 0
+#define HORIZONTAL_ADDRESS_MASK 0xffff
+
+/* XXX */
+#define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024)
+#define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824)
+#define MIPI_DBI_FIFO_THROTTLE(pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)
+#define DBI_FIFO_EMPTY_HALF (0 << 0)
+#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
+#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
+
+/* regs below are bits 15:0 */
+#define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028)
+#define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828)
+#define MIPI_HSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)
+
+#define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c)
+#define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c)
+#define MIPI_HBP_COUNT(pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT)
+
+#define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030)
+#define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830)
+#define MIPI_HFP_COUNT(pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT)
+
+#define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034)
+#define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834)
+#define MIPI_HACTIVE_AREA_COUNT(pipe) _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)
+
+#define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038)
+#define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838)
+#define MIPI_VSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)
+
+#define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c)
+#define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c)
+#define MIPI_VBP_COUNT(pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT)
+
+#define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040)
+#define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840)
+#define MIPI_VFP_COUNT(pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT)
+
+#define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044)
+#define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844)
+#define MIPI_HIGH_LOW_SWITCH_COUNT(pipe) _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)
+/* regs above are bits 15:0 */
+
+#define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048)
+#define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848)
+#define MIPI_DPI_CONTROL(pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL)
+#define DPI_HS_MODE (1 << 6)
+#define BACKLIGHT_OFF (1 << 5)
+#define BACKLIGHT_ON (1 << 4)
+#define COLOR_MODE_OFF (1 << 3)
+#define COLOR_MODE_ON (1 << 2)
+#define TURN_ON (1 << 1)
+#define SHUTDOWN (1 << 0)
+
+#define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + 0xb04c)
+#define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + 0xb84c)
+#define MIPI_DPI_DATA(pipe) _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA)
+#define COMMAND_BYTE_SHIFT 0
+#define COMMAND_BYTE_MASK (0x3f << 0)
+
+#define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050)
+#define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850)
+#define MIPI_INIT_COUNT(pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT)
+#define MASTER_INIT_TIMER_SHIFT 0
+#define MASTER_INIT_TIMER_MASK (0xffff << 0)
+
+#define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054)
+#define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854)
+#define MIPI_MAX_RETURN_PKT_SIZE(pipe) _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)
+#define MAX_RETURN_PKT_SIZE_SHIFT 0
+#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
+
+#define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058)
+#define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858)
+#define MIPI_VIDEO_MODE_FORMAT(pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)
+#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
+#define DISABLE_VIDEO_BTA (1 << 3)
+#define IP_TG_CONFIG (1 << 2)
+#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
+#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
+#define VIDEO_MODE_BURST (3 << 0)
+
+#define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c)
+#define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c)
+#define MIPI_EOT_DISABLE(pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE)
+#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
+#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
+#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
+#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
+#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
+#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
+#define CLOCKSTOP (1 << 1)
+#define EOT_DISABLE (1 << 0)
+
+#define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060)
+#define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860)
+#define MIPI_LP_BYTECLK(pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK)
+#define LP_BYTECLK_SHIFT 0
+#define LP_BYTECLK_MASK (0xffff << 0)
+
+/* bits 31:0 */
+#define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064)
+#define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864)
+#define MIPI_LP_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA)
+
+/* bits 31:0 */
+#define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068)
+#define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868)
+#define MIPI_HS_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA)
+
+#define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c)
+#define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c)
+#define MIPI_LP_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL)
+#define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070)
+#define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870)
+#define MIPI_HS_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL)
+#define LONG_PACKET_WORD_COUNT_SHIFT 8
+#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
+#define SHORT_PACKET_PARAM_SHIFT 8
+#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
+#define VIRTUAL_CHANNEL_SHIFT 6
+#define VIRTUAL_CHANNEL_MASK (3 << 6)
+#define DATA_TYPE_SHIFT 0
+#define DATA_TYPE_MASK (3f << 0)
+/* data type values, see include/video/mipi_display.h */
+
+#define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074)
+#define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874)
+#define MIPI_GEN_FIFO_STAT(pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT)
+#define DPI_FIFO_EMPTY (1 << 28)
+#define DBI_FIFO_EMPTY (1 << 27)
+#define LP_CTRL_FIFO_EMPTY (1 << 26)
+#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
+#define LP_CTRL_FIFO_FULL (1 << 24)
+#define HS_CTRL_FIFO_EMPTY (1 << 18)
+#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
+#define HS_CTRL_FIFO_FULL (1 << 16)
+#define LP_DATA_FIFO_EMPTY (1 << 10)
+#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
+#define LP_DATA_FIFO_FULL (1 << 8)
+#define HS_DATA_FIFO_EMPTY (1 << 2)
+#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
+#define HS_DATA_FIFO_FULL (1 << 0)
+
+#define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb078)
+#define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb878)
+#define MIPI_HS_LP_DBI_ENABLE(pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)
+#define DBI_HS_LP_MODE_MASK (1 << 0)
+#define DBI_LP_MODE (1 << 0)
+#define DBI_HS_MODE (0 << 0)
+
+#define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080)
+#define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880)
+#define MIPI_DPHY_PARAM(pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM)
+#define EXIT_ZERO_COUNT_SHIFT 24
+#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
+#define TRAIL_COUNT_SHIFT 16
+#define TRAIL_COUNT_MASK (0x1f << 16)
+#define CLK_ZERO_COUNT_SHIFT 8
+#define CLK_ZERO_COUNT_MASK (0xff << 8)
+#define PREPARE_COUNT_SHIFT 0
+#define PREPARE_COUNT_MASK (0x3f << 0)
+
+/* bits 31:0 */
+#define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084)
+#define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884)
+#define MIPI_DBI_BW_CTRL(pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL)
+
+#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb088)
+#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb888)
+#define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe) _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)
+#define LP_HS_SSW_CNT_SHIFT 16
+#define LP_HS_SSW_CNT_MASK (0xffff << 16)
+#define HS_LP_PWR_SW_CNT_SHIFT 0
+#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
+
+#define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb08c)
+#define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb88c)
+#define MIPI_STOP_STATE_STALL(pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)
+#define STOP_STATE_STALL_COUNTER_SHIFT 0
+#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
+
+#define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb090)
+#define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb890)
+#define MIPI_INTR_STAT_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)
+#define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094)
+#define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894)
+#define MIPI_INTR_EN_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1)
+#define RX_CONTENTION_DETECTED (1 << 0)
+
+/* XXX: only pipe A ?!? */
+#define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100)
+#define DBI_TYPEC_ENABLE (1 << 31)
+#define DBI_TYPEC_WIP (1 << 30)
+#define DBI_TYPEC_OPTION_SHIFT 28
+#define DBI_TYPEC_OPTION_MASK (3 << 28)
+#define DBI_TYPEC_FREQ_SHIFT 24
+#define DBI_TYPEC_FREQ_MASK (0xf << 24)
+#define DBI_TYPEC_OVERRIDE (1 << 8)
+#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
+#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
+
+
+/* MIPI adapter registers */
+
+#define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104)
+#define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904)
+#define MIPI_CTRL(pipe) _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL)
+#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
+#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
+#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
+#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
+#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
+#define READ_REQUEST_PRIORITY_SHIFT 3
+#define READ_REQUEST_PRIORITY_MASK (3 << 3)
+#define READ_REQUEST_PRIORITY_LOW (0 << 3)
+#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
+#define RGB_FLIP_TO_BGR (1 << 2)
+
+#define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108)
+#define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908)
+#define MIPI_DATA_ADDRESS(pipe) _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS)
+#define DATA_MEM_ADDRESS_SHIFT 5
+#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
+#define DATA_VALID (1 << 0)
+
+#define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c)
+#define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c)
+#define MIPI_DATA_LENGTH(pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH)
+#define DATA_LENGTH_SHIFT 0
+#define DATA_LENGTH_MASK (0xfffff << 0)
+
+#define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb110)
+#define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb910)
+#define MIPI_COMMAND_ADDRESS(pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)
+#define COMMAND_MEM_ADDRESS_SHIFT 5
+#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
+#define AUTO_PWG_ENABLE (1 << 2)
+#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
+#define COMMAND_VALID (1 << 0)
+
+#define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb114)
+#define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb914)
+#define MIPI_COMMAND_LENGTH(pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH)
+#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
+#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
+
+#define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118)
+#define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918)
+#define MIPI_READ_DATA_RETURN(pipe, n) \
+ (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
+
+#define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb138)
+#define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb938)
+#define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
+#define READ_DATA_VALID(n) (1 << (n))
+
#endif /* _I915_REG_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 04/14] drm/i915: add MIPI DSI register definitions
2013-08-13 13:29 ` [PATCH 04/14] drm/i915: add MIPI DSI register definitions Jani Nikula
@ 2013-08-14 13:59 ` Ville Syrjälä
2013-08-15 8:02 ` Jani Nikula
2013-08-15 13:38 ` Damien Lespiau
1 sibling, 1 reply; 20+ messages in thread
From: Ville Syrjälä @ 2013-08-14 13:59 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, yogesh.mohan.marimuthu
On Tue, Aug 13, 2013 at 04:29:43PM +0300, Jani Nikula wrote:
> Add definitions for VLV MIPI DSI registers.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 409 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 409 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index aced53a..32e32b6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5104,4 +5104,413 @@
> #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
> #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
>
> +/* VLV MIPI registers */
> +
> +/* XXX: This register seems very messy. MIPIB has only enable and delay. */
> +#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
> +#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
> +#define MIPI_PORT_CTRL(pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL)
> +#define DPI_ENABLE (1 << 31) /* A + B */
> +#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
> +#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
> +#define DUAL_LINK_MODE_MASK (1 << 26)
> +#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
> +#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
25 is "Dither Enable" according to my docs.
> +#define FLOPPED_HSTX (1 << 23)
> +#define DE_INVERT (1 << 19) /* XXX */
One doc has DE_INVERT (and HS/VS invert and border enable bits),
another has the FLISDSI stuff. I guess that's the XXX here.
> +#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
> +#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
> +#define AFE_LATCHOUT (1 << 17)
16 is "LPOutput Hold"
> +#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
> +#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
> +#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11
> +#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
> +#define CSB_SHIFT 9
> +#define CSB_MASK (3 << 9)
> +#define CSB_20MHZ (0 << 9)
> +#define CSB_10MHZ (1 << 9)
> +#define CSB_40MHZ (2 << 9)
> +#define BANDGAP_MASK (1 << 8)
> +#define BANDGAP_PNW_CIRCUIT (0 << 8)
> +#define BANDGAP_LNC_CIRCUIT (1 << 8)
> +#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
> +#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
> +#define TEARING_EFFECT_DELAY (1 << 4) /* A + B */
> +#define TEARING_EFFECT_SHIFT 2 /* A + B */
> +#define TEARING_EFFECT_MASK (3 << 2)
> +#define TEARING_EFFECT_OFF (0 << 2)
> +#define TEARING_EFFECT_DSI (1 << 2)
> +#define TEARING_EFFECT_GPIO (2 << 2)
> +#define LANE_CONFIGURATION_SHIFT 0
> +#define LANE_CONFIGURATION_MASK (3 << 0)
> +#define LANE_CONFIGURATION_4LANE (0 << 0)
> +#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
> +#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
> +
> +#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
> +#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
> +#define MIPI_TEARING_CTRL(pipe) _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)
> +#define TEARING_EFFECT_DELAY_SHIFT 0
> +#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
> +
> +/* XXX */
> +#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
Is the XXX here because the spec says the contents are all "reserved"?
> +
> +/* MIPI DSI Controller and D-PHY registers */
> +
> +#define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000)
> +#define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800)
> +#define MIPI_DEVICE_READY(pipe) _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY)
> +#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
> +#define ULPS_STATE_MASK (3 << 1)
> +#define ULPS_STATE_ENTER (2 << 1) /* XXX */
> +#define ULPS_STATE_EXIT (1 << 1) /* XXX */
Maybe we should have the (0 << 1) "normal operation" listed here as well?
> +#define DEVICE_READY (1 << 0)
> +
> +#define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004)
> +#define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804)
> +#define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT)
> +#define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008)
> +#define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + 0xb808)
> +#define MIPI_INTR_EN(pipe) _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN)
> +#define TEARING_EFFECT (1 << 31)
> +#define SPL_PKT_SENT_INTERRUPT (1 << 30)
> +#define GEN_READ_DATA_AVAIL (1 << 29)
> +#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
> +#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
> +#define RX_PROT_VIOLATION (1 << 26)
> +#define RX_INVALID_TX_LENGTH (1 << 25)
> +#define ACK_WITH_NO_ERROR (1 << 24)
> +#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
> +#define LP_RX_TIMEOUT (1 << 22)
> +#define HS_TX_TIMEOUT (1 << 21)
> +#define DPI_FIFO_UNDERRUN (1 << 20)
> +#define LOW_CONTENTION (1 << 19)
> +#define HIGH_CONTENTION (1 << 18)
> +#define TXDSI_VC_ID_INVALID (1 << 17)
> +#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
> +#define TXCHECKSUM_ERROR (1 << 15)
> +#define TXECC_MULTIBIT_ERROR (1 << 14)
> +#define TXECC_SINGLE_BIT_ERROR (1 << 13)
> +#define TXFALSE_CONTROL_ERROR (1 << 12)
> +#define RXDSI_VC_ID_INVALID (1 << 11)
> +#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
> +#define RXCHECKSUM_ERROR (1 << 9)
> +#define RXECC_MULTIBIT_ERROR (1 << 8)
> +#define RXECC_SINGLE_BIT_ERROR (1 << 7)
> +#define RXFALSE_CONTROL_ERROR (1 << 6)
> +#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
> +#define RX_LP_TX_SYNC_ERROR (1 << 4)
> +#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
> +#define RXEOT_SYNC_ERROR (1 << 2)
> +#define RXSOT_SYNC_ERROR (1 << 1)
> +#define RXSOT_ERROR (1 << 0)
> +
> +#define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c)
> +#define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c)
> +#define MIPI_DSI_FUNC_PRG(pipe) _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG)
> +#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
> +#define CMD_MODE_NOT_SUPPORTED (0 << 13)
> +#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
> +#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
> +#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
> +#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
> +#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
> +#define VID_MODE_FORMAT_MASK (0xf << 7)
> +#define VID_MODE_NOT_SUPPORTED (0 << 7)
> +#define VID_MODE_FORMAT_RGB565 (1 << 7)
> +#define VID_MODE_FORMAT_RGB666 (2 << 7)
> +#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
> +#define VID_MODE_FORMAT_RGB888 (4 << 7)
> +#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
> +#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
> +#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
> +#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
> +#define DATA_LANES_PRG_REG_SHIFT 0
> +#define DATA_LANES_PRG_REG_MASK (7 << 0)
> +
> +#define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010)
> +#define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810)
> +#define MIPI_HS_TX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT)
> +#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
> +
> +#define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014)
> +#define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814)
> +#define MIPI_LP_RX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT)
> +#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
> +
> +#define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018)
> +#define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818)
> +#define MIPI_TURN_AROUND_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)
> +#define TURN_AROUND_TIMEOUT_MASK 0x3f
> +
> +#define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c)
> +#define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c)
> +#define MIPI_DEVICE_RESET_TIMER(pipe) _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)
> +#define DEVICE_RESET_TIMER_MASK 0xffff
> +
> +#define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb020)
> +#define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb820)
> +#define MIPI_DPI_RESOLUTION(pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION)
> +#define VERTICAL_ADDRESS_SHIFT 16
> +#define VERTICAL_ADDRESS_MASK (0xffff << 16)
> +#define HORIZONTAL_ADDRESS_SHIFT 0
> +#define HORIZONTAL_ADDRESS_MASK 0xffff
> +
> +/* XXX */
> +#define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024)
> +#define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824)
Is the XXX about the register name here? Spec lists it as
MIPIA_DBI_RESOLUTION, which doesn't make much sense based on the
contents.
> +#define MIPI_DBI_FIFO_THROTTLE(pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)
> +#define DBI_FIFO_EMPTY_HALF (0 << 0)
> +#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
> +#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
> +
> +/* regs below are bits 15:0 */
> +#define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028)
> +#define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828)
> +#define MIPI_HSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)
> +
> +#define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c)
> +#define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c)
> +#define MIPI_HBP_COUNT(pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT)
> +
> +#define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030)
> +#define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830)
> +#define MIPI_HFP_COUNT(pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT)
> +
> +#define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034)
> +#define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834)
> +#define MIPI_HACTIVE_AREA_COUNT(pipe) _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)
> +
> +#define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038)
> +#define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838)
> +#define MIPI_VSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)
> +
> +#define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c)
> +#define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c)
> +#define MIPI_VBP_COUNT(pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT)
> +
> +#define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040)
> +#define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840)
> +#define MIPI_VFP_COUNT(pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT)
> +
> +#define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044)
> +#define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844)
> +#define MIPI_HIGH_LOW_SWITCH_COUNT(pipe) _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)
> +/* regs above are bits 15:0 */
> +
> +#define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048)
> +#define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848)
> +#define MIPI_DPI_CONTROL(pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL)
> +#define DPI_HS_MODE (1 << 6)
Spec says 0=HS 1=LP, so this seems a bit backwards.
> +#define BACKLIGHT_OFF (1 << 5)
> +#define BACKLIGHT_ON (1 << 4)
> +#define COLOR_MODE_OFF (1 << 3)
> +#define COLOR_MODE_ON (1 << 2)
> +#define TURN_ON (1 << 1)
> +#define SHUTDOWN (1 << 0)
> +
> +#define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + 0xb04c)
> +#define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + 0xb84c)
> +#define MIPI_DPI_DATA(pipe) _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA)
> +#define COMMAND_BYTE_SHIFT 0
> +#define COMMAND_BYTE_MASK (0x3f << 0)
> +
> +#define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050)
> +#define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850)
> +#define MIPI_INIT_COUNT(pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT)
> +#define MASTER_INIT_TIMER_SHIFT 0
> +#define MASTER_INIT_TIMER_MASK (0xffff << 0)
> +
> +#define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054)
> +#define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854)
> +#define MIPI_MAX_RETURN_PKT_SIZE(pipe) _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)
> +#define MAX_RETURN_PKT_SIZE_SHIFT 0
> +#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
> +
> +#define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058)
> +#define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858)
> +#define MIPI_VIDEO_MODE_FORMAT(pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)
> +#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
> +#define DISABLE_VIDEO_BTA (1 << 3)
> +#define IP_TG_CONFIG (1 << 2)
> +#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
> +#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
> +#define VIDEO_MODE_BURST (3 << 0)
> +
> +#define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c)
> +#define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c)
> +#define MIPI_EOT_DISABLE(pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE)
> +#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
> +#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
> +#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
> +#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
> +#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
> +#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
> +#define CLOCKSTOP (1 << 1)
> +#define EOT_DISABLE (1 << 0)
> +
> +#define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060)
> +#define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860)
> +#define MIPI_LP_BYTECLK(pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK)
> +#define LP_BYTECLK_SHIFT 0
> +#define LP_BYTECLK_MASK (0xffff << 0)
> +
> +/* bits 31:0 */
> +#define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064)
> +#define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864)
> +#define MIPI_LP_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA)
> +
> +/* bits 31:0 */
> +#define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068)
> +#define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868)
> +#define MIPI_HS_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA)
> +
> +#define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c)
> +#define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c)
> +#define MIPI_LP_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL)
> +#define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070)
> +#define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870)
> +#define MIPI_HS_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL)
> +#define LONG_PACKET_WORD_COUNT_SHIFT 8
> +#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
> +#define SHORT_PACKET_PARAM_SHIFT 8
> +#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
> +#define VIRTUAL_CHANNEL_SHIFT 6
> +#define VIRTUAL_CHANNEL_MASK (3 << 6)
> +#define DATA_TYPE_SHIFT 0
> +#define DATA_TYPE_MASK (3f << 0)
> +/* data type values, see include/video/mipi_display.h */
> +
> +#define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074)
> +#define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874)
> +#define MIPI_GEN_FIFO_STAT(pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT)
> +#define DPI_FIFO_EMPTY (1 << 28)
> +#define DBI_FIFO_EMPTY (1 << 27)
> +#define LP_CTRL_FIFO_EMPTY (1 << 26)
> +#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
> +#define LP_CTRL_FIFO_FULL (1 << 24)
> +#define HS_CTRL_FIFO_EMPTY (1 << 18)
> +#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
> +#define HS_CTRL_FIFO_FULL (1 << 16)
> +#define LP_DATA_FIFO_EMPTY (1 << 10)
> +#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
> +#define LP_DATA_FIFO_FULL (1 << 8)
> +#define HS_DATA_FIFO_EMPTY (1 << 2)
> +#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
> +#define HS_DATA_FIFO_FULL (1 << 0)
> +
> +#define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb078)
> +#define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb878)
> +#define MIPI_HS_LP_DBI_ENABLE(pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)
> +#define DBI_HS_LP_MODE_MASK (1 << 0)
> +#define DBI_LP_MODE (1 << 0)
> +#define DBI_HS_MODE (0 << 0)
> +
> +#define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080)
> +#define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880)
> +#define MIPI_DPHY_PARAM(pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM)
> +#define EXIT_ZERO_COUNT_SHIFT 24
> +#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
> +#define TRAIL_COUNT_SHIFT 16
> +#define TRAIL_COUNT_MASK (0x1f << 16)
> +#define CLK_ZERO_COUNT_SHIFT 8
> +#define CLK_ZERO_COUNT_MASK (0xff << 8)
> +#define PREPARE_COUNT_SHIFT 0
> +#define PREPARE_COUNT_MASK (0x3f << 0)
> +
> +/* bits 31:0 */
> +#define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084)
> +#define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884)
> +#define MIPI_DBI_BW_CTRL(pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL)
> +
> +#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb088)
> +#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb888)
> +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe) _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)
> +#define LP_HS_SSW_CNT_SHIFT 16
> +#define LP_HS_SSW_CNT_MASK (0xffff << 16)
> +#define HS_LP_PWR_SW_CNT_SHIFT 0
> +#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
> +
> +#define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb08c)
> +#define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb88c)
> +#define MIPI_STOP_STATE_STALL(pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)
> +#define STOP_STATE_STALL_COUNTER_SHIFT 0
> +#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
> +
> +#define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb090)
> +#define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb890)
> +#define MIPI_INTR_STAT_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)
> +#define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094)
> +#define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894)
> +#define MIPI_INTR_EN_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1)
> +#define RX_CONTENTION_DETECTED (1 << 0)
> +
> +/* XXX: only pipe A ?!? */
> +#define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100)
> +#define DBI_TYPEC_ENABLE (1 << 31)
> +#define DBI_TYPEC_WIP (1 << 30)
> +#define DBI_TYPEC_OPTION_SHIFT 28
> +#define DBI_TYPEC_OPTION_MASK (3 << 28)
> +#define DBI_TYPEC_FREQ_SHIFT 24
> +#define DBI_TYPEC_FREQ_MASK (0xf << 24)
> +#define DBI_TYPEC_OVERRIDE (1 << 8)
> +#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
> +#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
> +
> +
> +/* MIPI adapter registers */
> +
> +#define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104)
> +#define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904)
> +#define MIPI_CTRL(pipe) _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL)
> +#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
> +#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
> +#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
> +#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
> +#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
> +#define READ_REQUEST_PRIORITY_SHIFT 3
> +#define READ_REQUEST_PRIORITY_MASK (3 << 3)
> +#define READ_REQUEST_PRIORITY_LOW (0 << 3)
> +#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
> +#define RGB_FLIP_TO_BGR (1 << 2)
> +
> +#define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108)
> +#define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908)
> +#define MIPI_DATA_ADDRESS(pipe) _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS)
> +#define DATA_MEM_ADDRESS_SHIFT 5
> +#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
> +#define DATA_VALID (1 << 0)
> +
> +#define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c)
> +#define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c)
> +#define MIPI_DATA_LENGTH(pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH)
> +#define DATA_LENGTH_SHIFT 0
> +#define DATA_LENGTH_MASK (0xfffff << 0)
> +
> +#define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb110)
> +#define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb910)
> +#define MIPI_COMMAND_ADDRESS(pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)
> +#define COMMAND_MEM_ADDRESS_SHIFT 5
> +#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
> +#define AUTO_PWG_ENABLE (1 << 2)
> +#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
> +#define COMMAND_VALID (1 << 0)
> +
> +#define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb114)
> +#define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb914)
> +#define MIPI_COMMAND_LENGTH(pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH)
> +#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
> +#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
> +
> +#define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118)
> +#define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918)
> +#define MIPI_READ_DATA_RETURN(pipe, n) \
> + (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
> +
> +#define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb138)
> +#define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb938)
> +#define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
> +#define READ_DATA_VALID(n) (1 << (n))
> +
> #endif /* _I915_REG_H_ */
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 04/14] drm/i915: add MIPI DSI register definitions
2013-08-14 13:59 ` Ville Syrjälä
@ 2013-08-15 8:02 ` Jani Nikula
0 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-15 8:02 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, yogesh.mohan.marimuthu
On Wed, 14 Aug 2013, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Aug 13, 2013 at 04:29:43PM +0300, Jani Nikula wrote:
>> Add definitions for VLV MIPI DSI registers.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 409 +++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 409 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index aced53a..32e32b6 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5104,4 +5104,413 @@
>> #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
>> #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
>>
>> +/* VLV MIPI registers */
>> +
>> +/* XXX: This register seems very messy. MIPIB has only enable and delay. */
>> +#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
>> +#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
>> +#define MIPI_PORT_CTRL(pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL)
>> +#define DPI_ENABLE (1 << 31) /* A + B */
>> +#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
>> +#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
>> +#define DUAL_LINK_MODE_MASK (1 << 26)
>> +#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
>> +#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
>
> 25 is "Dither Enable" according to my docs.
Fixed.
>> +#define FLOPPED_HSTX (1 << 23)
>> +#define DE_INVERT (1 << 19) /* XXX */
>
> One doc has DE_INVERT (and HS/VS invert and border enable bits),
> another has the FLISDSI stuff. I guess that's the XXX here.
Yeah, and as you can see the two are overlapping. I'd like to keep it
like this as a memory aid.
>> +#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
>> +#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
>> +#define AFE_LATCHOUT (1 << 17)
>
> 16 is "LPOutput Hold"
Added.
>> +#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
>> +#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
>> +#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11
>> +#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
>> +#define CSB_SHIFT 9
>> +#define CSB_MASK (3 << 9)
>> +#define CSB_20MHZ (0 << 9)
>> +#define CSB_10MHZ (1 << 9)
>> +#define CSB_40MHZ (2 << 9)
>> +#define BANDGAP_MASK (1 << 8)
>> +#define BANDGAP_PNW_CIRCUIT (0 << 8)
>> +#define BANDGAP_LNC_CIRCUIT (1 << 8)
>> +#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
>> +#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
>> +#define TEARING_EFFECT_DELAY (1 << 4) /* A + B */
>> +#define TEARING_EFFECT_SHIFT 2 /* A + B */
>> +#define TEARING_EFFECT_MASK (3 << 2)
>> +#define TEARING_EFFECT_OFF (0 << 2)
>> +#define TEARING_EFFECT_DSI (1 << 2)
>> +#define TEARING_EFFECT_GPIO (2 << 2)
>> +#define LANE_CONFIGURATION_SHIFT 0
>> +#define LANE_CONFIGURATION_MASK (3 << 0)
>> +#define LANE_CONFIGURATION_4LANE (0 << 0)
>> +#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
>> +#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
>> +
>> +#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
>> +#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
>> +#define MIPI_TEARING_CTRL(pipe) _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)
>> +#define TEARING_EFFECT_DELAY_SHIFT 0
>> +#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
>> +
>> +/* XXX */
>> +#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
>
> Is the XXX here because the spec says the contents are all "reserved"?
Yes; do you prefer adding that to the comment, or dropping the register
altogether?
>> +
>> +/* MIPI DSI Controller and D-PHY registers */
>> +
>> +#define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000)
>> +#define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800)
>> +#define MIPI_DEVICE_READY(pipe) _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY)
>> +#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
>> +#define ULPS_STATE_MASK (3 << 1)
>> +#define ULPS_STATE_ENTER (2 << 1) /* XXX */
>> +#define ULPS_STATE_EXIT (1 << 1) /* XXX */
>
> Maybe we should have the (0 << 1) "normal operation" listed here as well?
Added.
>> +#define DEVICE_READY (1 << 0)
>> +
>> +#define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004)
>> +#define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804)
>> +#define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT)
>> +#define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008)
>> +#define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + 0xb808)
>> +#define MIPI_INTR_EN(pipe) _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN)
>> +#define TEARING_EFFECT (1 << 31)
>> +#define SPL_PKT_SENT_INTERRUPT (1 << 30)
>> +#define GEN_READ_DATA_AVAIL (1 << 29)
>> +#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
>> +#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
>> +#define RX_PROT_VIOLATION (1 << 26)
>> +#define RX_INVALID_TX_LENGTH (1 << 25)
>> +#define ACK_WITH_NO_ERROR (1 << 24)
>> +#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
>> +#define LP_RX_TIMEOUT (1 << 22)
>> +#define HS_TX_TIMEOUT (1 << 21)
>> +#define DPI_FIFO_UNDERRUN (1 << 20)
>> +#define LOW_CONTENTION (1 << 19)
>> +#define HIGH_CONTENTION (1 << 18)
>> +#define TXDSI_VC_ID_INVALID (1 << 17)
>> +#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
>> +#define TXCHECKSUM_ERROR (1 << 15)
>> +#define TXECC_MULTIBIT_ERROR (1 << 14)
>> +#define TXECC_SINGLE_BIT_ERROR (1 << 13)
>> +#define TXFALSE_CONTROL_ERROR (1 << 12)
>> +#define RXDSI_VC_ID_INVALID (1 << 11)
>> +#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
>> +#define RXCHECKSUM_ERROR (1 << 9)
>> +#define RXECC_MULTIBIT_ERROR (1 << 8)
>> +#define RXECC_SINGLE_BIT_ERROR (1 << 7)
>> +#define RXFALSE_CONTROL_ERROR (1 << 6)
>> +#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
>> +#define RX_LP_TX_SYNC_ERROR (1 << 4)
>> +#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
>> +#define RXEOT_SYNC_ERROR (1 << 2)
>> +#define RXSOT_SYNC_ERROR (1 << 1)
>> +#define RXSOT_ERROR (1 << 0)
>> +
>> +#define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c)
>> +#define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c)
>> +#define MIPI_DSI_FUNC_PRG(pipe) _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG)
>> +#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
>> +#define CMD_MODE_NOT_SUPPORTED (0 << 13)
>> +#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
>> +#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
>> +#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
>> +#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
>> +#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
>> +#define VID_MODE_FORMAT_MASK (0xf << 7)
>> +#define VID_MODE_NOT_SUPPORTED (0 << 7)
>> +#define VID_MODE_FORMAT_RGB565 (1 << 7)
>> +#define VID_MODE_FORMAT_RGB666 (2 << 7)
>> +#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
>> +#define VID_MODE_FORMAT_RGB888 (4 << 7)
>> +#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
>> +#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
>> +#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
>> +#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
>> +#define DATA_LANES_PRG_REG_SHIFT 0
>> +#define DATA_LANES_PRG_REG_MASK (7 << 0)
>> +
>> +#define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010)
>> +#define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810)
>> +#define MIPI_HS_TX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT)
>> +#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
>> +
>> +#define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014)
>> +#define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814)
>> +#define MIPI_LP_RX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT)
>> +#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
>> +
>> +#define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018)
>> +#define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818)
>> +#define MIPI_TURN_AROUND_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)
>> +#define TURN_AROUND_TIMEOUT_MASK 0x3f
>> +
>> +#define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c)
>> +#define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c)
>> +#define MIPI_DEVICE_RESET_TIMER(pipe) _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)
>> +#define DEVICE_RESET_TIMER_MASK 0xffff
>> +
>> +#define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb020)
>> +#define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb820)
>> +#define MIPI_DPI_RESOLUTION(pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION)
>> +#define VERTICAL_ADDRESS_SHIFT 16
>> +#define VERTICAL_ADDRESS_MASK (0xffff << 16)
>> +#define HORIZONTAL_ADDRESS_SHIFT 0
>> +#define HORIZONTAL_ADDRESS_MASK 0xffff
>> +
>> +/* XXX */
>> +#define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024)
>> +#define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824)
>
> Is the XXX about the register name here? Spec lists it as
> MIPIA_DBI_RESOLUTION, which doesn't make much sense based on the
> contents.
Yes. I dropped the XXX comment. Another spec names the reg as
DBI_FIFO_THROTTLE, which I'm inclided to trust as it matches the
contents.
>> +#define MIPI_DBI_FIFO_THROTTLE(pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)
>> +#define DBI_FIFO_EMPTY_HALF (0 << 0)
>> +#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
>> +#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
>> +
>> +/* regs below are bits 15:0 */
>> +#define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028)
>> +#define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828)
>> +#define MIPI_HSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)
>> +
>> +#define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c)
>> +#define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c)
>> +#define MIPI_HBP_COUNT(pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT)
>> +
>> +#define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030)
>> +#define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830)
>> +#define MIPI_HFP_COUNT(pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT)
>> +
>> +#define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034)
>> +#define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834)
>> +#define MIPI_HACTIVE_AREA_COUNT(pipe) _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)
>> +
>> +#define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038)
>> +#define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838)
>> +#define MIPI_VSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)
>> +
>> +#define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c)
>> +#define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c)
>> +#define MIPI_VBP_COUNT(pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT)
>> +
>> +#define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040)
>> +#define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840)
>> +#define MIPI_VFP_COUNT(pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT)
>> +
>> +#define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044)
>> +#define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844)
>> +#define MIPI_HIGH_LOW_SWITCH_COUNT(pipe) _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)
>> +/* regs above are bits 15:0 */
>> +
>> +#define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048)
>> +#define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848)
>> +#define MIPI_DPI_CONTROL(pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL)
>> +#define DPI_HS_MODE (1 << 6)
>
> Spec says 0=HS 1=LP, so this seems a bit backwards.
*blush* Fixed.
Thanks for the review,
Jani.
>> +#define BACKLIGHT_OFF (1 << 5)
>> +#define BACKLIGHT_ON (1 << 4)
>> +#define COLOR_MODE_OFF (1 << 3)
>> +#define COLOR_MODE_ON (1 << 2)
>> +#define TURN_ON (1 << 1)
>> +#define SHUTDOWN (1 << 0)
>> +
>> +#define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + 0xb04c)
>> +#define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + 0xb84c)
>> +#define MIPI_DPI_DATA(pipe) _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA)
>> +#define COMMAND_BYTE_SHIFT 0
>> +#define COMMAND_BYTE_MASK (0x3f << 0)
>> +
>> +#define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050)
>> +#define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850)
>> +#define MIPI_INIT_COUNT(pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT)
>> +#define MASTER_INIT_TIMER_SHIFT 0
>> +#define MASTER_INIT_TIMER_MASK (0xffff << 0)
>> +
>> +#define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054)
>> +#define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854)
>> +#define MIPI_MAX_RETURN_PKT_SIZE(pipe) _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)
>> +#define MAX_RETURN_PKT_SIZE_SHIFT 0
>> +#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
>> +
>> +#define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058)
>> +#define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858)
>> +#define MIPI_VIDEO_MODE_FORMAT(pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)
>> +#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
>> +#define DISABLE_VIDEO_BTA (1 << 3)
>> +#define IP_TG_CONFIG (1 << 2)
>> +#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
>> +#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
>> +#define VIDEO_MODE_BURST (3 << 0)
>> +
>> +#define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c)
>> +#define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c)
>> +#define MIPI_EOT_DISABLE(pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE)
>> +#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
>> +#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
>> +#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
>> +#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
>> +#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
>> +#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
>> +#define CLOCKSTOP (1 << 1)
>> +#define EOT_DISABLE (1 << 0)
>> +
>> +#define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060)
>> +#define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860)
>> +#define MIPI_LP_BYTECLK(pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK)
>> +#define LP_BYTECLK_SHIFT 0
>> +#define LP_BYTECLK_MASK (0xffff << 0)
>> +
>> +/* bits 31:0 */
>> +#define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064)
>> +#define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864)
>> +#define MIPI_LP_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA)
>> +
>> +/* bits 31:0 */
>> +#define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068)
>> +#define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868)
>> +#define MIPI_HS_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA)
>> +
>> +#define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c)
>> +#define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c)
>> +#define MIPI_LP_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL)
>> +#define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070)
>> +#define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870)
>> +#define MIPI_HS_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL)
>> +#define LONG_PACKET_WORD_COUNT_SHIFT 8
>> +#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
>> +#define SHORT_PACKET_PARAM_SHIFT 8
>> +#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
>> +#define VIRTUAL_CHANNEL_SHIFT 6
>> +#define VIRTUAL_CHANNEL_MASK (3 << 6)
>> +#define DATA_TYPE_SHIFT 0
>> +#define DATA_TYPE_MASK (3f << 0)
>> +/* data type values, see include/video/mipi_display.h */
>> +
>> +#define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074)
>> +#define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874)
>> +#define MIPI_GEN_FIFO_STAT(pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT)
>> +#define DPI_FIFO_EMPTY (1 << 28)
>> +#define DBI_FIFO_EMPTY (1 << 27)
>> +#define LP_CTRL_FIFO_EMPTY (1 << 26)
>> +#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
>> +#define LP_CTRL_FIFO_FULL (1 << 24)
>> +#define HS_CTRL_FIFO_EMPTY (1 << 18)
>> +#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
>> +#define HS_CTRL_FIFO_FULL (1 << 16)
>> +#define LP_DATA_FIFO_EMPTY (1 << 10)
>> +#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
>> +#define LP_DATA_FIFO_FULL (1 << 8)
>> +#define HS_DATA_FIFO_EMPTY (1 << 2)
>> +#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
>> +#define HS_DATA_FIFO_FULL (1 << 0)
>> +
>> +#define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb078)
>> +#define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb878)
>> +#define MIPI_HS_LP_DBI_ENABLE(pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)
>> +#define DBI_HS_LP_MODE_MASK (1 << 0)
>> +#define DBI_LP_MODE (1 << 0)
>> +#define DBI_HS_MODE (0 << 0)
>> +
>> +#define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080)
>> +#define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880)
>> +#define MIPI_DPHY_PARAM(pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM)
>> +#define EXIT_ZERO_COUNT_SHIFT 24
>> +#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
>> +#define TRAIL_COUNT_SHIFT 16
>> +#define TRAIL_COUNT_MASK (0x1f << 16)
>> +#define CLK_ZERO_COUNT_SHIFT 8
>> +#define CLK_ZERO_COUNT_MASK (0xff << 8)
>> +#define PREPARE_COUNT_SHIFT 0
>> +#define PREPARE_COUNT_MASK (0x3f << 0)
>> +
>> +/* bits 31:0 */
>> +#define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084)
>> +#define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884)
>> +#define MIPI_DBI_BW_CTRL(pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL)
>> +
>> +#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb088)
>> +#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb888)
>> +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe) _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)
>> +#define LP_HS_SSW_CNT_SHIFT 16
>> +#define LP_HS_SSW_CNT_MASK (0xffff << 16)
>> +#define HS_LP_PWR_SW_CNT_SHIFT 0
>> +#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
>> +
>> +#define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb08c)
>> +#define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb88c)
>> +#define MIPI_STOP_STATE_STALL(pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)
>> +#define STOP_STATE_STALL_COUNTER_SHIFT 0
>> +#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
>> +
>> +#define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb090)
>> +#define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb890)
>> +#define MIPI_INTR_STAT_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)
>> +#define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094)
>> +#define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894)
>> +#define MIPI_INTR_EN_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1)
>> +#define RX_CONTENTION_DETECTED (1 << 0)
>> +
>> +/* XXX: only pipe A ?!? */
>> +#define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100)
>> +#define DBI_TYPEC_ENABLE (1 << 31)
>> +#define DBI_TYPEC_WIP (1 << 30)
>> +#define DBI_TYPEC_OPTION_SHIFT 28
>> +#define DBI_TYPEC_OPTION_MASK (3 << 28)
>> +#define DBI_TYPEC_FREQ_SHIFT 24
>> +#define DBI_TYPEC_FREQ_MASK (0xf << 24)
>> +#define DBI_TYPEC_OVERRIDE (1 << 8)
>> +#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
>> +#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
>> +
>> +
>> +/* MIPI adapter registers */
>> +
>> +#define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104)
>> +#define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904)
>> +#define MIPI_CTRL(pipe) _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL)
>> +#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
>> +#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
>> +#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
>> +#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
>> +#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
>> +#define READ_REQUEST_PRIORITY_SHIFT 3
>> +#define READ_REQUEST_PRIORITY_MASK (3 << 3)
>> +#define READ_REQUEST_PRIORITY_LOW (0 << 3)
>> +#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
>> +#define RGB_FLIP_TO_BGR (1 << 2)
>> +
>> +#define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108)
>> +#define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908)
>> +#define MIPI_DATA_ADDRESS(pipe) _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS)
>> +#define DATA_MEM_ADDRESS_SHIFT 5
>> +#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
>> +#define DATA_VALID (1 << 0)
>> +
>> +#define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c)
>> +#define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c)
>> +#define MIPI_DATA_LENGTH(pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH)
>> +#define DATA_LENGTH_SHIFT 0
>> +#define DATA_LENGTH_MASK (0xfffff << 0)
>> +
>> +#define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb110)
>> +#define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb910)
>> +#define MIPI_COMMAND_ADDRESS(pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)
>> +#define COMMAND_MEM_ADDRESS_SHIFT 5
>> +#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
>> +#define AUTO_PWG_ENABLE (1 << 2)
>> +#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
>> +#define COMMAND_VALID (1 << 0)
>> +
>> +#define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb114)
>> +#define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb914)
>> +#define MIPI_COMMAND_LENGTH(pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH)
>> +#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
>> +#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
>> +
>> +#define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118)
>> +#define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918)
>> +#define MIPI_READ_DATA_RETURN(pipe, n) \
>> + (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
>> +
>> +#define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb138)
>> +#define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb938)
>> +#define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
>> +#define READ_DATA_VALID(n) (1 << (n))
>> +
>> #endif /* _I915_REG_H_ */
>> --
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 04/14] drm/i915: add MIPI DSI register definitions
2013-08-13 13:29 ` [PATCH 04/14] drm/i915: add MIPI DSI register definitions Jani Nikula
2013-08-14 13:59 ` Ville Syrjälä
@ 2013-08-15 13:38 ` Damien Lespiau
2013-08-15 14:08 ` Daniel Vetter
1 sibling, 1 reply; 20+ messages in thread
From: Damien Lespiau @ 2013-08-15 13:38 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, yogesh.mohan.marimuthu
On Tue, Aug 13, 2013 at 04:29:43PM +0300, Jani Nikula wrote:
> Add definitions for VLV MIPI DSI registers.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 409 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 409 insertions(+)
I wonder if it'd be the right time to spawn another header instead of
adding more to i915_reg.h? or people are fine with that big i915_reg.h?
--
Damien
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 04/14] drm/i915: add MIPI DSI register definitions
2013-08-15 13:38 ` Damien Lespiau
@ 2013-08-15 14:08 ` Daniel Vetter
0 siblings, 0 replies; 20+ messages in thread
From: Daniel Vetter @ 2013-08-15 14:08 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Jani Nikula, intel-gfx, yogesh.mohan.marimuthu
On Thu, Aug 15, 2013 at 3:38 PM, Damien Lespiau
<damien.lespiau@intel.com> wrote:
> On Tue, Aug 13, 2013 at 04:29:43PM +0300, Jani Nikula wrote:
>> Add definitions for VLV MIPI DSI registers.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 409 +++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 409 insertions(+)
>
> I wonder if it'd be the right time to spawn another header instead of
> adding more to i915_reg.h? or people are fine with that big i915_reg.h?
cscope can still keep track of it, so imo it's ok. Stuff we care more
about (function declarations, structs, ...) are already in other
files, so personally I don't mind really.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 05/14] drm/i915: add MIPI DSI output type and subtypes
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
` (3 preceding siblings ...)
2013-08-13 13:29 ` [PATCH 04/14] drm/i915: add MIPI DSI register definitions Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
2013-08-13 13:29 ` [PATCH 06/14] drm/i915: add structs for MIPI DSI output Jani Nikula
` (8 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_drv.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 01455aa..a31abc6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -93,13 +93,17 @@
#define INTEL_OUTPUT_HDMI 6
#define INTEL_OUTPUT_DISPLAYPORT 7
#define INTEL_OUTPUT_EDP 8
-#define INTEL_OUTPUT_UNKNOWN 9
+#define INTEL_OUTPUT_DSI 9
+#define INTEL_OUTPUT_UNKNOWN 10
#define INTEL_DVO_CHIP_NONE 0
#define INTEL_DVO_CHIP_LVDS 1
#define INTEL_DVO_CHIP_TMDS 2
#define INTEL_DVO_CHIP_TVOUT 4
+#define INTEL_DSI_COMMAND_MODE 0
+#define INTEL_DSI_VIDEO_MODE 1
+
struct intel_framebuffer {
struct drm_framebuffer base;
struct drm_i915_gem_object *obj;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 06/14] drm/i915: add structs for MIPI DSI output
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
` (4 preceding siblings ...)
2013-08-13 13:29 ` [PATCH 05/14] drm/i915: add MIPI DSI output type and subtypes Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
2013-08-13 13:29 ` [PATCH 07/14] drm/i915: add MIPI DSI command sending routines Jani Nikula
` (7 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
The sub-encoder model is copied from DVO.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.h | 99 ++++++++++++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_dsi.h
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
new file mode 100644
index 0000000..45f649a
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _INTEL_DSI_H
+#define _INTEL_DSI_H
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include "intel_drv.h"
+
+struct intel_dsi_device {
+ unsigned int panel_id;
+ const char *name;
+ int type;
+ const struct intel_dsi_dev_ops *dev_ops;
+ void *dev_priv;
+};
+
+struct intel_dsi_dev_ops {
+ bool (*init)(struct intel_dsi_device *dsi);
+
+ /* This callback must be able to assume DSI commands can be sent */
+ void (*enable)(struct intel_dsi_device *dsi);
+
+ /* This callback must be able to assume DSI commands can be sent */
+ void (*disable)(struct intel_dsi_device *dsi);
+
+ int (*mode_valid)(struct intel_dsi_device *dsi,
+ struct drm_display_mode *mode);
+
+ bool (*mode_fixup)(struct intel_dsi_device *dsi,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode);
+
+ void (*mode_set)(struct intel_dsi_device *dsi,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode);
+
+ enum drm_connector_status (*detect)(struct intel_dsi_device *dsi);
+
+ bool (*get_hw_state)(struct intel_dsi_device *dev);
+
+ struct drm_display_mode *(*get_modes)(struct intel_dsi_device *dsi);
+
+ void (*destroy) (struct intel_dsi_device *dsi);
+};
+
+struct intel_dsi {
+ struct intel_encoder base;
+
+ struct intel_dsi_device dev;
+
+ struct drm_display_mode *panel_fixed_mode;
+
+ /* if true, use HS mode, otherwise LP */
+ bool hs;
+
+ /* virtual channel */
+ int channel;
+
+ /* number of DSI lanes */
+ unsigned int lane_count;
+
+ /* video mode pixel format for MIPI_DSI_FUNC_PRG register */
+ u32 pixel_format;
+
+ /* video mode format for MIPI_VIDEO_MODE_FORMAT register */
+ u32 video_mode_format;
+
+ /* eot for MIPI_EOT_DISABLE register */
+ u32 eot_disable;
+};
+
+static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
+{
+ return container_of(encoder, struct intel_dsi, base.base);
+}
+
+#endif /* _INTEL_DSI_H */
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 07/14] drm/i915: add MIPI DSI command sending routines
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
` (5 preceding siblings ...)
2013-08-13 13:29 ` [PATCH 06/14] drm/i915: add structs for MIPI DSI output Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
2013-08-13 13:29 ` [PATCH 08/14] drm/i915: add basic MIPI DSI output support Jani Nikula
` (6 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_dsi_cmd.c | 442 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dsi_cmd.h | 109 +++++++++
3 files changed, 552 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.c
create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b8449a8..8bffd29 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -21,6 +21,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
intel_display.o \
intel_crt.o \
intel_lvds.o \
+ intel_dsi_cmd.o \
intel_bios.o \
intel_ddi.o \
intel_dp.o \
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
new file mode 100644
index 0000000..e78dd97
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -0,0 +1,442 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jani Nikula <jani.nikula@intel.com>
+ */
+
+#include <linux/export.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <video/mipi_display.h>
+#include "i915_drv.h"
+#include "intel_drv.h"
+#include "intel_dsi.h"
+#include "intel_dsi_cmd.h"
+
+/*
+ * XXX: MIPI_DATA_ADDRESS, MIPI_DATA_LENGTH, MIPI_COMMAND_LENGTH, and
+ * MIPI_COMMAND_ADDRESS registers.
+ *
+ * Apparently these registers provide a MIPI adapter level way to send (lots of)
+ * commands and data to the receiver, without having to write the commands and
+ * data to MIPI_{HS,LP}_GEN_{CTRL,DATA} registers word by word.
+ *
+ * Presumably for anything other than MIPI_DCS_WRITE_MEMORY_START and
+ * MIPI_DCS_WRITE_MEMORY_CONTINUE (which are used to update the external
+ * framebuffer in command mode displays) these are just an optimization that can
+ * come later.
+ *
+ * For memory writes, these should probably be used for performance.
+ */
+
+static void print_stat(struct intel_dsi *intel_dsi)
+{
+ struct drm_encoder *encoder = &intel_dsi->base.base;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ u32 val;
+
+ val = I915_READ(MIPI_INTR_STAT(pipe));
+
+#define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : ""
+ DRM_DEBUG_KMS("MIPI_INTR_STAT(%d) = %08x"
+ "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
+ "\n", pipe, val,
+ STAT_BIT(val, TEARING_EFFECT),
+ STAT_BIT(val, SPL_PKT_SENT_INTERRUPT),
+ STAT_BIT(val, GEN_READ_DATA_AVAIL),
+ STAT_BIT(val, LP_GENERIC_WR_FIFO_FULL),
+ STAT_BIT(val, HS_GENERIC_WR_FIFO_FULL),
+ STAT_BIT(val, RX_PROT_VIOLATION),
+ STAT_BIT(val, RX_INVALID_TX_LENGTH),
+ STAT_BIT(val, ACK_WITH_NO_ERROR),
+ STAT_BIT(val, TURN_AROUND_ACK_TIMEOUT),
+ STAT_BIT(val, LP_RX_TIMEOUT),
+ STAT_BIT(val, HS_TX_TIMEOUT),
+ STAT_BIT(val, DPI_FIFO_UNDERRUN),
+ STAT_BIT(val, LOW_CONTENTION),
+ STAT_BIT(val, HIGH_CONTENTION),
+ STAT_BIT(val, TXDSI_VC_ID_INVALID),
+ STAT_BIT(val, TXDSI_DATA_TYPE_NOT_RECOGNISED),
+ STAT_BIT(val, TXCHECKSUM_ERROR),
+ STAT_BIT(val, TXECC_MULTIBIT_ERROR),
+ STAT_BIT(val, TXECC_SINGLE_BIT_ERROR),
+ STAT_BIT(val, TXFALSE_CONTROL_ERROR),
+ STAT_BIT(val, RXDSI_VC_ID_INVALID),
+ STAT_BIT(val, RXDSI_DATA_TYPE_NOT_REGOGNISED),
+ STAT_BIT(val, RXCHECKSUM_ERROR),
+ STAT_BIT(val, RXECC_MULTIBIT_ERROR),
+ STAT_BIT(val, RXECC_SINGLE_BIT_ERROR),
+ STAT_BIT(val, RXFALSE_CONTROL_ERROR),
+ STAT_BIT(val, RXHS_RECEIVE_TIMEOUT_ERROR),
+ STAT_BIT(val, RX_LP_TX_SYNC_ERROR),
+ STAT_BIT(val, RXEXCAPE_MODE_ENTRY_ERROR),
+ STAT_BIT(val, RXEOT_SYNC_ERROR),
+ STAT_BIT(val, RXSOT_SYNC_ERROR),
+ STAT_BIT(val, RXSOT_ERROR));
+#undef STAT_BIT
+}
+
+enum dsi_type {
+ DSI_DCS,
+ DSI_GENERIC,
+};
+
+/* enable or disable command mode hs transmissions */
+void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
+{
+ struct drm_encoder *encoder = &intel_dsi->base.base;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ u32 temp;
+ u32 mask = DBI_FIFO_EMPTY;
+
+ /* XXX: or wait for !full...? */
+ if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
+ DRM_ERROR("Timeout waiting for DBI FIFO empty\n");
+
+ temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(pipe));
+ temp &= DBI_HS_LP_MODE_MASK;
+ I915_WRITE(MIPI_HS_LP_DBI_ENABLE(pipe), enable ? DBI_HS_MODE : DBI_LP_MODE);
+
+ intel_dsi->hs = enable;
+}
+
+static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
+ u8 data_type, u16 data)
+{
+ struct drm_encoder *encoder = &intel_dsi->base.base;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ u32 ctrl_reg;
+ u32 ctrl;
+ u32 mask;
+
+ DRM_DEBUG_KMS("channel %d, data_type %d, data %04x\n",
+ channel, data_type, data);
+
+ /* XXX: set MIPI_HS_LS_DBI_ENABLE? wait for dbi fifo empty first */
+
+ /* XXX: short write, do we need to wait for data FIFO? */
+ if (intel_dsi->hs) {
+ ctrl_reg = MIPI_HS_GEN_CTRL(pipe);
+ mask = HS_CTRL_FIFO_FULL;
+ } else {
+ ctrl_reg = MIPI_LP_GEN_CTRL(pipe);
+ mask = LP_CTRL_FIFO_FULL;
+ }
+
+ /* Note: Could also wait for !full instead of empty. */
+ if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) {
+ DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
+ print_stat(intel_dsi);
+ }
+
+ ctrl = data << SHORT_PACKET_PARAM_SHIFT |
+ channel << VIRTUAL_CHANNEL_SHIFT |
+ data_type << DATA_TYPE_SHIFT;
+
+ I915_WRITE(ctrl_reg, ctrl);
+
+ return 0;
+}
+
+static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
+ u8 data_type, const u8 *data, u16 len)
+{
+ struct drm_encoder *encoder = &intel_dsi->base.base;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ u32 data_reg, ctrl_reg, ctrl;
+ u16 i, j, n;
+ u32 mask;
+
+ DRM_DEBUG_KMS("channel %d, data_type %d, len %04x\n",
+ channel, data_type, len);
+
+ /* XXX: set MIPI_HS_LS_DBI_ENABLE? wait for dbi fifo empty first */
+
+ if (intel_dsi->hs) {
+ data_reg = MIPI_HS_GEN_DATA(pipe);
+ ctrl_reg = MIPI_HS_GEN_CTRL(pipe);
+ mask = HS_DATA_FIFO_FULL;
+ } else {
+ data_reg = MIPI_LP_GEN_DATA(pipe);
+ ctrl_reg = MIPI_LP_GEN_CTRL(pipe);
+ mask = LP_DATA_FIFO_FULL;
+ }
+
+ /* Note: Could also wait for !full instead of empty. */
+ if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50))
+ DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
+
+ for (i = 0; i < len; i += n) {
+ u32 val = 0;
+ n = min(len - i, 4);
+
+ for (j = 0; j < n; j++)
+ val |= *data++ << 8 * j;
+
+ I915_WRITE(data_reg, val);
+ /* XXX: check for data fifo full, once that is set, write 4
+ * dwords, then wait for not set, then continue. */
+ }
+
+ if (intel_dsi->hs)
+ mask = HS_CTRL_FIFO_FULL;
+ else
+ mask = LP_CTRL_FIFO_FULL;
+
+ if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50))
+ DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
+
+ ctrl = len << LONG_PACKET_WORD_COUNT_SHIFT;
+ ctrl |= channel << VIRTUAL_CHANNEL_SHIFT;
+ ctrl |= data_type << DATA_TYPE_SHIFT;
+
+ I915_WRITE(ctrl_reg, ctrl);
+
+ return 0;
+}
+
+static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
+ int channel, const u8 *data, int len,
+ enum dsi_type type)
+{
+ int ret;
+
+ if (len == 0) {
+ BUG_ON(type == DSI_GENERIC);
+ ret = dsi_vc_send_short(intel_dsi, channel,
+ MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
+ 0);
+ } else if (len == 1) {
+ ret = dsi_vc_send_short(intel_dsi, channel,
+ type == DSI_GENERIC ?
+ MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
+ MIPI_DSI_DCS_SHORT_WRITE, data[0]);
+ } else if (len == 2) {
+ ret = dsi_vc_send_short(intel_dsi, channel,
+ type == DSI_GENERIC ?
+ MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
+ MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+ (data[1] << 8) | data[0]);
+ } else {
+ ret = dsi_vc_send_long(intel_dsi, channel,
+ type == DSI_GENERIC ?
+ MIPI_DSI_GENERIC_LONG_WRITE :
+ MIPI_DSI_DCS_LONG_WRITE, data, len);
+ }
+
+ return ret;
+}
+
+int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
+ const u8 *data, int len)
+{
+ return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS);
+}
+
+int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
+ const u8 *data, int len)
+{
+ return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC);
+}
+
+static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
+ int channel, u8 dcs_cmd)
+{
+ return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
+ dcs_cmd);
+}
+
+static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
+ int channel, u8 *reqdata,
+ int reqlen)
+{
+ u16 data;
+ u8 data_type;
+
+ switch (reqlen) {
+ case 0:
+ data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
+ data = 0;
+ break;
+ case 1:
+ data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
+ data = reqdata[0];
+ break;
+ case 2:
+ data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
+ data = (reqdata[1] << 8) | reqdata[0];
+ break;
+ default:
+ BUG();
+ }
+
+ return dsi_vc_send_short(intel_dsi, channel, data_type, data);
+}
+
+static int dsi_read_data_return(struct intel_dsi *intel_dsi,
+ u8 *buf, int buflen)
+{
+ struct drm_encoder *encoder = &intel_dsi->base.base;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ int i, j, len = 0;
+ u32 data_valid, val;
+
+ data_valid = I915_READ(MIPI_READ_DATA_VALID(pipe));
+
+ /* XXX: byte order of data in return registers? */
+ for (i = 0; i < 8 && len < buflen; i++) {
+ if (!(data_valid & (1 << i)))
+ break;
+
+ val = I915_READ(MIPI_READ_DATA_RETURN(pipe, i));
+ for (j = 0; j < 4 && len < buflen; j++, len++)
+ buf[len] = val >> 8 * j;
+ }
+
+ /* Clear the data valid bits. */
+ I915_WRITE(MIPI_READ_DATA_VALID(pipe), data_valid);
+
+ return len;
+}
+
+int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
+ u8 *buf, int buflen)
+{
+ struct drm_encoder *encoder = &intel_dsi->base.base;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ u32 mask;
+ int ret;
+
+ /* XXX: should issue multiple read requests and reads if request is
+ * longer than MIPI_MAX_RETURN_PKT_SIZE */
+
+ ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd);
+ if (ret)
+ return ret;
+
+ mask = GEN_READ_DATA_AVAIL;
+ if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
+ DRM_ERROR("Timeout waiting for read data.\n");
+
+ ret = dsi_read_data_return(intel_dsi, buf, buflen);
+ if (ret < 0)
+ return ret;
+
+ if (ret != buflen)
+ return -EIO;
+
+ return 0;
+}
+
+int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
+ u8 *reqdata, int reqlen, u8 *buf, int buflen)
+{
+ struct drm_encoder *encoder = &intel_dsi->base.base;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ u32 mask;
+ int ret;
+
+ /* XXX: should issue multiple read requests and reads if request is
+ * longer than MIPI_MAX_RETURN_PKT_SIZE.
+ */
+
+ ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
+ reqlen);
+ if (ret)
+ return ret;
+
+ mask = GEN_READ_DATA_AVAIL;
+ if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
+ DRM_ERROR("Timeout waiting for read data.\n");
+
+ ret = dsi_read_data_return(intel_dsi, buf, buflen);
+ if (ret < 0)
+ return ret;
+
+ if (ret != buflen)
+ return -EIO;
+
+ return 0;
+}
+
+/*
+ * send a video mode command
+ *
+ * XXX: commands with data in MIPI_DPI_DATA?
+ */
+int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd)
+{
+ struct drm_encoder *encoder = &intel_dsi->base.base;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ u32 mask;
+
+ /* XXX: pipe, hs */
+ if (intel_dsi->hs)
+ cmd &= ~DPI_HS_MODE;
+ else
+ cmd |= DPI_HS_MODE;
+
+ /* DPI virtual channel?! */
+
+ mask = DPI_FIFO_EMPTY;
+ if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
+ DRM_ERROR("Timeout waiting for DPI FIFO empty.\n");
+
+ /* clear bit */
+ I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT);
+
+ /* XXX: old code skips write if control unchanged */
+ if (cmd == I915_READ(MIPI_DPI_CONTROL(pipe)))
+ DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
+
+ I915_WRITE(MIPI_DPI_CONTROL(pipe), cmd);
+
+ mask = SPL_PKT_SENT_INTERRUPT;
+ if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == 0, 50))
+ DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h b/drivers/gpu/drm/i915/intel_dsi_cmd.h
new file mode 100644
index 0000000..54c8a23
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jani Nikula <jani.nikula@intel.com>
+ */
+
+#ifndef _INTEL_DSI_DSI_H
+#define _INTEL_DSI_DSI_H
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <video/mipi_display.h>
+#include "i915_drv.h"
+#include "intel_drv.h"
+#include "intel_dsi.h"
+
+void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable);
+
+int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
+ const u8 *data, int len);
+
+int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
+ const u8 *data, int len);
+
+int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
+ u8 *buf, int buflen);
+
+int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
+ u8 *reqdata, int reqlen, u8 *buf, int buflen);
+
+int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd);
+
+/* XXX: questionable write helpers */
+static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi,
+ int channel, u8 dcs_cmd)
+{
+ return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1);
+}
+
+static inline int dsi_vc_dcs_write_1(struct intel_dsi *intel_dsi,
+ int channel, u8 dcs_cmd, u8 param)
+{
+ u8 buf[2] = { dcs_cmd, param };
+ return dsi_vc_dcs_write(intel_dsi, channel, buf, 2);
+}
+
+static inline int dsi_vc_generic_write_0(struct intel_dsi *intel_dsi,
+ int channel)
+{
+ return dsi_vc_generic_write(intel_dsi, channel, NULL, 0);
+}
+
+static inline int dsi_vc_generic_write_1(struct intel_dsi *intel_dsi,
+ int channel, u8 param)
+{
+ return dsi_vc_generic_write(intel_dsi, channel, ¶m, 1);
+}
+
+static inline int dsi_vc_generic_write_2(struct intel_dsi *intel_dsi,
+ int channel, u8 param1, u8 param2)
+{
+ u8 buf[2] = { param1, param2 };
+ return dsi_vc_generic_write(intel_dsi, channel, buf, 2);
+}
+
+/* XXX: questionable read helpers */
+static inline int dsi_vc_generic_read_0(struct intel_dsi *intel_dsi,
+ int channel, u8 *buf, int buflen)
+{
+ return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen);
+}
+
+static inline int dsi_vc_generic_read_1(struct intel_dsi *intel_dsi,
+ int channel, u8 param, u8 *buf,
+ int buflen)
+{
+ return dsi_vc_generic_read(intel_dsi, channel, ¶m, 1, buf, buflen);
+}
+
+static inline int dsi_vc_generic_read_2(struct intel_dsi *intel_dsi,
+ int channel, u8 param1, u8 param2,
+ u8 *buf, int buflen)
+{
+ u8 req[2] = { param1, param2 };
+
+ return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen);
+}
+
+
+#endif /* _INTEL_DSI_DSI_H */
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 08/14] drm/i915: add basic MIPI DSI output support
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
` (6 preceding siblings ...)
2013-08-13 13:29 ` [PATCH 07/14] drm/i915: add MIPI DSI command sending routines Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
2013-08-13 22:17 ` Daniel Vetter
2013-08-13 13:29 ` [PATCH 09/14] drm/i915: add VLV DSI PLL Calculations Jani Nikula
` (5 subsequent siblings)
13 siblings, 1 reply; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
This does not include any panel specific sub-encoders yet.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_dsi.c | 548 ++++++++++++++++++++++++++++++++++++++
3 files changed, 550 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_dsi.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8bffd29..5864c5b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -21,6 +21,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
intel_display.o \
intel_crt.o \
intel_lvds.o \
+ intel_dsi.o \
intel_dsi_cmd.o \
intel_bios.o \
intel_ddi.o \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a31abc6..cbe3df1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -525,6 +525,7 @@ extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
struct intel_ring_buffer *ring);
extern void intel_mark_idle(struct drm_device *dev);
extern void intel_lvds_init(struct drm_device *dev);
+extern bool intel_dsi_init(struct drm_device *dev);
extern bool intel_is_dual_link_lvds(struct drm_device *dev);
extern void intel_dp_init(struct drm_device *dev, int output_reg,
enum port port);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
new file mode 100644
index 0000000..aa81dd8
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -0,0 +1,548 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jani Nikula <jani.nikula@intel.com>
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_edid.h>
+#include <drm/i915_drm.h>
+#include <linux/slab.h>
+#include "i915_drv.h"
+#include "intel_drv.h"
+#include "intel_dsi.h"
+#include "intel_dsi_cmd.h"
+
+/* the sub-encoders aka panel drivers */
+static const struct intel_dsi_device intel_dsi_devices[] = {
+};
+
+static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
+{
+ return container_of(intel_attached_encoder(connector),
+ struct intel_dsi, base);
+}
+
+static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
+{
+ return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
+}
+
+static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
+{
+ return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
+}
+
+static void intel_dsi_hot_plug(struct intel_encoder *encoder)
+{
+ DRM_DEBUG_KMS("\n");
+}
+
+static bool intel_dsi_compute_config(struct intel_encoder *encoder,
+ struct intel_crtc_config *config)
+{
+ DRM_DEBUG_KMS("\n");
+ return true;
+}
+
+static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
+{
+ DRM_DEBUG_KMS("\n");
+}
+
+static void intel_dsi_pre_enable(struct intel_encoder *encoder)
+{
+ DRM_DEBUG_KMS("\n");
+}
+
+static void intel_dsi_enable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ int pipe = intel_crtc->pipe;
+ u32 temp;
+
+ DRM_DEBUG_KMS("\n");
+
+ temp = I915_READ(MIPI_DEVICE_READY(pipe));
+ temp &= ~ULPS_STATE_MASK;
+ temp &= ~DEVICE_READY; /* XXX: assuming it's already !ready */
+ I915_WRITE(MIPI_DEVICE_READY(pipe), temp | ULPS_STATE_EXIT);
+ msleep(20); /* XXX */
+ I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
+ msleep(20); /* XXX */
+ I915_WRITE(MIPI_DEVICE_READY(pipe), temp | DEVICE_READY);
+
+ if (is_cmd_mode(intel_dsi))
+ I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
+
+ /* Do this here, or let the slave encoder do it in ->dpms? */
+ if (is_vid_mode(intel_dsi)) {
+ dpi_send_cmd(intel_dsi, TURN_ON);
+ msleep(100);
+ }
+
+ /* assert ip_tg_enable signal */
+ temp = I915_READ(MIPI_PORT_CTRL(pipe));
+ I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
+ POSTING_READ(MIPI_PORT_CTRL(pipe));
+
+ intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
+}
+
+static void intel_dsi_disable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ int pipe = intel_crtc->pipe;
+ u32 temp;
+
+ DRM_DEBUG_KMS("\n");
+
+ intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
+
+ if (is_vid_mode(intel_dsi))
+ dpi_send_cmd(intel_dsi, SHUTDOWN);
+
+ if (is_vid_mode(intel_dsi)) {
+ /* de-assert ip_tg_enable signal */
+ temp = I915_READ(MIPI_PORT_CTRL(pipe));
+ I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
+ POSTING_READ(MIPI_PORT_CTRL(pipe));
+ }
+
+ /* XXX: wait for fifos before ulps entry */
+
+ temp = I915_READ(MIPI_DEVICE_READY(pipe));
+ temp &= ~ULPS_STATE_MASK;
+ temp &= ~DEVICE_READY;
+ I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
+ msleep(5);
+ I915_WRITE(MIPI_DEVICE_READY(pipe), temp | ULPS_STATE_ENTER);
+}
+
+static void intel_dsi_post_disable(struct intel_encoder *encoder)
+{
+ DRM_DEBUG_KMS("\n");
+
+ /* XXX: disable dsi pll */
+}
+
+static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
+ enum pipe *pipe)
+{
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+
+ DRM_DEBUG_KMS("\n");
+
+ /* XXX: this is wrong */
+ if (intel_crtc) {
+ *pipe = intel_crtc->pipe;
+ return true;
+ }
+
+ /* XXX: do we also need to call
+ * intel_dsi->dev.dev_ops->get_hw_state(&intel_dsi->dev);
+ */
+
+ return false;
+}
+
+static void intel_dsi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_config *pipe_config)
+{
+ DRM_DEBUG_KMS("\n");
+}
+
+static int intel_dsi_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
+
+ DRM_DEBUG_KMS("\n");
+
+ if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
+ DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
+ return MODE_NO_DBLESCAN;
+ }
+
+ if (intel_dsi->panel_fixed_mode) {
+ if (mode->hdisplay > intel_dsi->panel_fixed_mode->hdisplay)
+ return MODE_PANEL;
+ if (mode->vdisplay > intel_dsi->panel_fixed_mode->vdisplay)
+ return MODE_PANEL;
+ }
+
+ return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
+}
+
+static bool intel_dsi_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+
+ DRM_DEBUG_KMS("\n");
+
+ /* If we have timings from the BIOS for the panel, put them in
+ * to the adjusted mode. The CRTC will be set up for this mode,
+ * with the panel scaling set up to source from the H/VDisplay
+ * of the original mode.
+ */
+ if (intel_dsi->panel_fixed_mode != NULL) {
+#define C(x) adjusted_mode->x = intel_dsi->panel_fixed_mode->x
+ C(hdisplay);
+ C(hsync_start);
+ C(hsync_end);
+ C(htotal);
+ C(vdisplay);
+ C(vsync_start);
+ C(vsync_end);
+ C(vtotal);
+ C(clock);
+#undef C
+ }
+
+ if (intel_dsi->dev.dev_ops->mode_fixup)
+ return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, mode, adjusted_mode);
+
+ return true;
+}
+
+/* return pixels in terms of txbyteclkhs */
+static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
+{
+ return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
+}
+
+static void set_dsi_timings(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode)
+{
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+ int pipe = intel_crtc->pipe;
+ unsigned int bpp = intel_crtc->config.pipe_bpp;
+ unsigned int lane_count = intel_dsi->lane_count;
+
+ u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
+
+ hactive = mode->hdisplay;
+ hfp = mode->hsync_start - mode->hdisplay;
+ hsync = mode->hsync_end - mode->hsync_start;
+ hbp = mode->htotal - mode->hsync_end;
+
+ vfp = mode->vsync_start - mode->vdisplay;
+ vsync = mode->vsync_end - mode->vsync_start;
+ vbp = mode->vtotal - mode->vsync_end;
+
+ /* horizontal values are in terms of high speed byte clock */
+ hactive = txbyteclkhs(hactive, bpp, lane_count);
+ hfp = txbyteclkhs(hfp, bpp, lane_count);
+ hsync = txbyteclkhs(hsync, bpp, lane_count);
+ hbp = txbyteclkhs(hbp, bpp, lane_count);
+
+ I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
+ I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
+
+ /* meaningful for video mode non-burst sync pulse mode only, can be zero
+ * for non-burst sync events and burst modes */
+ I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
+ I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
+
+ /* vertical values are in terms of lines */
+ I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
+ I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
+ I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
+}
+
+static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
+{
+ struct drm_encoder *encoder = &intel_encoder->base;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+ struct drm_display_mode *adjusted_mode =
+ &intel_crtc->config.adjusted_mode;
+ int pipe = intel_crtc->pipe;
+ unsigned int bpp = intel_crtc->config.pipe_bpp;
+ u32 val, tmp;
+
+ DRM_DEBUG_KMS("pipe %d\n", pipe);
+
+ /* escape clock divider, 20MHz, shared for A and C. device ready must be
+ * off when doing this! txclkesc? */
+ tmp = I915_READ(MIPI_CTRL(0));
+ tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+ I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
+
+ /* read request priority is per pipe */
+ tmp = I915_READ(MIPI_CTRL(pipe));
+ tmp &= ~READ_REQUEST_PRIORITY_MASK;
+ I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
+
+ /* XXX: why here, why like this? handling in irq handler?! */
+ I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
+ I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
+
+ I915_WRITE(MIPI_DPHY_PARAM(pipe),
+ 0x3c << EXIT_ZERO_COUNT_SHIFT |
+ 0x1f << TRAIL_COUNT_SHIFT |
+ 0xc5 << CLK_ZERO_COUNT_SHIFT |
+ 0x1f << PREPARE_COUNT_SHIFT);
+
+ I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
+ adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
+ adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
+
+ set_dsi_timings(encoder, adjusted_mode);
+
+ val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
+ if (is_cmd_mode(intel_dsi)) {
+ val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
+ val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
+ } else {
+ val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
+
+ /* XXX: cross-check bpp vs. pixel format? */
+ val |= intel_dsi->pixel_format;
+ }
+ I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
+
+ /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
+ * stop state. */
+
+ if (is_vid_mode(intel_dsi) &&
+ intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
+ I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
+ txbyteclkhs(adjusted_mode->htotal + 1, bpp,
+ intel_dsi->lane_count));
+ } else {
+ I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
+ txbyteclkhs(adjusted_mode->vtotal *
+ adjusted_mode->htotal,
+ bpp, intel_dsi->lane_count));
+ }
+ I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), 0xffff);
+ I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), 0x14);
+
+ I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), 0xffff);
+
+ /* dphy stuff */
+
+ /* in terms of low power clock */
+ I915_WRITE(MIPI_INIT_COUNT(pipe), 0x7d0);
+
+ /* recovery disables */
+ I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
+
+ /* in terms of txbyteclkhs. actual high to low switch +
+ * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
+ *
+ * XXX: write MIPI_STOP_STATE_STALL?
+ */
+ I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), 0x46);
+
+ /* XXX: low power clock equivalence in terms of byte clock. the number
+ * of byte clocks occupied in one low power clock. based on txbyteclkhs
+ * and txclkesc. txclkesc time / txbyteclk time * (105 +
+ * MIPI_STOP_STATE_STALL) / 105.???
+ */
+ I915_WRITE(MIPI_LP_BYTECLK(pipe), 4);
+
+ /* the bw essential for transmitting 16 long packets containing 252
+ * bytes meant for dcs write memory command is programmed in this
+ * register in terms of byte clocks. based on dsi transfer rate and the
+ * number of lanes configured the time taken to transmit 16 long packets
+ * in a dsi stream varies. */
+ I915_WRITE(MIPI_DBI_BW_CTRL(pipe), 0x820);
+
+ I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
+ 0xa << LP_HS_SSW_CNT_SHIFT |
+ 0x14 << HS_LP_PWR_SW_CNT_SHIFT);
+
+ if (is_vid_mode(intel_dsi))
+ I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
+ intel_dsi->video_mode_format);
+}
+
+static enum drm_connector_status
+intel_dsi_detect(struct drm_connector *connector, bool force)
+{
+ struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
+ DRM_DEBUG_KMS("\n");
+ return intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
+}
+
+static int intel_dsi_get_modes(struct drm_connector *connector)
+{
+ struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
+ struct drm_display_mode *mode;
+
+ DRM_DEBUG_KMS("\n");
+
+ if (!intel_dsi->panel_fixed_mode) {
+ DRM_DEBUG_KMS("no fixed mode\n");
+ return 0;
+ }
+
+ mode = drm_mode_duplicate(connector->dev, intel_dsi->panel_fixed_mode);
+ if (!mode) {
+ DRM_DEBUG_KMS("dupe failed\n");
+ return 0;
+ }
+
+ drm_mode_probed_add(connector, mode);
+ return 1;
+}
+
+static void intel_dsi_destroy(struct drm_connector *connector)
+{
+ DRM_DEBUG_KMS("\n");
+ drm_sysfs_connector_remove(connector);
+ drm_connector_cleanup(connector);
+ kfree(connector);
+}
+
+static const struct drm_encoder_helper_funcs intel_dsi_helper_funcs = {
+ .mode_fixup = intel_dsi_mode_fixup,
+};
+
+static const struct drm_encoder_funcs intel_dsi_funcs = {
+ .destroy = intel_encoder_destroy,
+};
+
+static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
+ .get_modes = intel_dsi_get_modes,
+ .mode_valid = intel_dsi_mode_valid,
+ .best_encoder = intel_best_encoder,
+};
+
+static const struct drm_connector_funcs intel_dsi_connector_funcs = {
+ .dpms = intel_connector_dpms,
+ .detect = intel_dsi_detect,
+ .destroy = intel_dsi_destroy,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+};
+
+bool intel_dsi_init(struct drm_device *dev)
+{
+ struct intel_dsi *intel_dsi;
+ struct intel_encoder *intel_encoder;
+ struct drm_encoder *encoder;
+ struct intel_connector *intel_connector;
+ struct drm_connector *connector;
+ struct drm_display_mode *fixed_mode = NULL;
+ const struct intel_dsi_device *dsi;
+ unsigned int i;
+
+ DRM_DEBUG_KMS("\n");
+
+ intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
+ if (!intel_dsi)
+ return false;
+
+ intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
+ if (!intel_connector) {
+ kfree(intel_dsi);
+ return false;
+ }
+
+ intel_encoder = &intel_dsi->base;
+ encoder = &intel_encoder->base;
+
+ connector = &intel_connector->base;
+
+ drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
+
+ /* XXX: very likely not all of these are needed */
+ intel_encoder->hot_plug = intel_dsi_hot_plug;
+ intel_encoder->compute_config = intel_dsi_compute_config;
+ intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
+ intel_encoder->pre_enable = intel_dsi_pre_enable;
+ intel_encoder->enable = intel_dsi_enable;
+ intel_encoder->mode_set = intel_dsi_mode_set;
+ intel_encoder->disable = intel_dsi_disable;
+ intel_encoder->post_disable = intel_dsi_post_disable;
+ intel_encoder->get_hw_state = intel_dsi_get_hw_state;
+ intel_encoder->get_config = intel_dsi_get_config;
+
+ intel_connector->get_hw_state = intel_connector_get_hw_state;
+
+ for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
+ dsi = &intel_dsi_devices[i];
+ intel_dsi->dev = *dsi;
+
+ if (dsi->dev_ops->init(&intel_dsi->dev))
+ break;
+ }
+
+ if (i == ARRAY_SIZE(intel_dsi_devices)) {
+ DRM_DEBUG_KMS("no device found\n");
+ goto err;
+ }
+
+ intel_encoder->type = INTEL_OUTPUT_DSI;
+ intel_encoder->crtc_mask = (1 << 0); /* XXX */
+
+ intel_encoder->cloneable = false;
+ drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+
+ drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
+
+ connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
+ connector->interlace_allowed = false;
+ connector->doublescan_allowed = false;
+
+ drm_encoder_helper_add(encoder, &intel_dsi_helper_funcs);
+
+ intel_connector_attach_encoder(intel_connector, intel_encoder);
+
+ drm_sysfs_connector_add(connector);
+
+ fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
+ if (!fixed_mode) {
+ DRM_DEBUG_KMS("no fixed mode\n");
+ goto err;
+ }
+
+ fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
+
+ intel_dsi->panel_fixed_mode = fixed_mode;
+
+ intel_panel_init(&intel_connector->panel, fixed_mode);
+
+ return true;
+
+err:
+ drm_encoder_cleanup(&intel_encoder->base);
+ kfree(intel_dsi);
+ kfree(intel_connector);
+
+ return false;
+}
--
1.7.9.5
_______________________________________________
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 08/14] drm/i915: add basic MIPI DSI output support
2013-08-13 13:29 ` [PATCH 08/14] drm/i915: add basic MIPI DSI output support Jani Nikula
@ 2013-08-13 22:17 ` Daniel Vetter
0 siblings, 0 replies; 20+ messages in thread
From: Daniel Vetter @ 2013-08-13 22:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, yogesh.mohan.marimuthu
On Tue, Aug 13, 2013 at 04:29:47PM +0300, Jani Nikula wrote:
> This does not include any panel specific sub-encoders yet.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Quick bikesheed on how you wire up the get_modes stuff, mostly because I'm
just discussing this on irc with Rob:
- We now have intel_connector->panel.fixed_mode
- And I think it's better to route all the get_modes stuff entirely
through the connector layer, leaving the dsi encoder entirely out of the
picture. Maybe we should even go as far as registering the drm_connector
from the dsi sink device since that one really knows all the details
(like all the properties of the panel, what mode it supports or whether
maybe this DSI thingy is actually some transcoder with a totally
different output attached ...).
Cheers, Daniel
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_dsi.c | 548 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 550 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/intel_dsi.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 8bffd29..5864c5b 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -21,6 +21,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
> intel_display.o \
> intel_crt.o \
> intel_lvds.o \
> + intel_dsi.o \
> intel_dsi_cmd.o \
> intel_bios.o \
> intel_ddi.o \
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index a31abc6..cbe3df1 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -525,6 +525,7 @@ extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
> struct intel_ring_buffer *ring);
> extern void intel_mark_idle(struct drm_device *dev);
> extern void intel_lvds_init(struct drm_device *dev);
> +extern bool intel_dsi_init(struct drm_device *dev);
> extern bool intel_is_dual_link_lvds(struct drm_device *dev);
> extern void intel_dp_init(struct drm_device *dev, int output_reg,
> enum port port);
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> new file mode 100644
> index 0000000..aa81dd8
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -0,0 +1,548 @@
> +/*
> + * Copyright © 2013 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + *
> + * Author: Jani Nikula <jani.nikula@intel.com>
> + */
> +
> +#include <drm/drmP.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_edid.h>
> +#include <drm/i915_drm.h>
> +#include <linux/slab.h>
> +#include "i915_drv.h"
> +#include "intel_drv.h"
> +#include "intel_dsi.h"
> +#include "intel_dsi_cmd.h"
> +
> +/* the sub-encoders aka panel drivers */
> +static const struct intel_dsi_device intel_dsi_devices[] = {
> +};
> +
> +static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
> +{
> + return container_of(intel_attached_encoder(connector),
> + struct intel_dsi, base);
> +}
> +
> +static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
> +{
> + return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
> +}
> +
> +static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
> +{
> + return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
> +}
> +
> +static void intel_dsi_hot_plug(struct intel_encoder *encoder)
> +{
> + DRM_DEBUG_KMS("\n");
> +}
> +
> +static bool intel_dsi_compute_config(struct intel_encoder *encoder,
> + struct intel_crtc_config *config)
> +{
> + DRM_DEBUG_KMS("\n");
> + return true;
> +}
> +
> +static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
> +{
> + DRM_DEBUG_KMS("\n");
> +}
> +
> +static void intel_dsi_pre_enable(struct intel_encoder *encoder)
> +{
> + DRM_DEBUG_KMS("\n");
> +}
> +
> +static void intel_dsi_enable(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + int pipe = intel_crtc->pipe;
> + u32 temp;
> +
> + DRM_DEBUG_KMS("\n");
> +
> + temp = I915_READ(MIPI_DEVICE_READY(pipe));
> + temp &= ~ULPS_STATE_MASK;
> + temp &= ~DEVICE_READY; /* XXX: assuming it's already !ready */
> + I915_WRITE(MIPI_DEVICE_READY(pipe), temp | ULPS_STATE_EXIT);
> + msleep(20); /* XXX */
> + I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
> + msleep(20); /* XXX */
> + I915_WRITE(MIPI_DEVICE_READY(pipe), temp | DEVICE_READY);
> +
> + if (is_cmd_mode(intel_dsi))
> + I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
> +
> + /* Do this here, or let the slave encoder do it in ->dpms? */
> + if (is_vid_mode(intel_dsi)) {
> + dpi_send_cmd(intel_dsi, TURN_ON);
> + msleep(100);
> + }
> +
> + /* assert ip_tg_enable signal */
> + temp = I915_READ(MIPI_PORT_CTRL(pipe));
> + I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
> + POSTING_READ(MIPI_PORT_CTRL(pipe));
> +
> + intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
> +}
> +
> +static void intel_dsi_disable(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + int pipe = intel_crtc->pipe;
> + u32 temp;
> +
> + DRM_DEBUG_KMS("\n");
> +
> + intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
> +
> + if (is_vid_mode(intel_dsi))
> + dpi_send_cmd(intel_dsi, SHUTDOWN);
> +
> + if (is_vid_mode(intel_dsi)) {
> + /* de-assert ip_tg_enable signal */
> + temp = I915_READ(MIPI_PORT_CTRL(pipe));
> + I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
> + POSTING_READ(MIPI_PORT_CTRL(pipe));
> + }
> +
> + /* XXX: wait for fifos before ulps entry */
> +
> + temp = I915_READ(MIPI_DEVICE_READY(pipe));
> + temp &= ~ULPS_STATE_MASK;
> + temp &= ~DEVICE_READY;
> + I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
> + msleep(5);
> + I915_WRITE(MIPI_DEVICE_READY(pipe), temp | ULPS_STATE_ENTER);
> +}
> +
> +static void intel_dsi_post_disable(struct intel_encoder *encoder)
> +{
> + DRM_DEBUG_KMS("\n");
> +
> + /* XXX: disable dsi pll */
> +}
> +
> +static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> + enum pipe *pipe)
> +{
> + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> +
> + DRM_DEBUG_KMS("\n");
> +
> + /* XXX: this is wrong */
> + if (intel_crtc) {
> + *pipe = intel_crtc->pipe;
> + return true;
> + }
> +
> + /* XXX: do we also need to call
> + * intel_dsi->dev.dev_ops->get_hw_state(&intel_dsi->dev);
> + */
> +
> + return false;
> +}
> +
> +static void intel_dsi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_config *pipe_config)
> +{
> + DRM_DEBUG_KMS("\n");
> +}
> +
> +static int intel_dsi_mode_valid(struct drm_connector *connector,
> + struct drm_display_mode *mode)
> +{
> + struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
> +
> + DRM_DEBUG_KMS("\n");
> +
> + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
> + DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
> + return MODE_NO_DBLESCAN;
> + }
> +
> + if (intel_dsi->panel_fixed_mode) {
> + if (mode->hdisplay > intel_dsi->panel_fixed_mode->hdisplay)
> + return MODE_PANEL;
> + if (mode->vdisplay > intel_dsi->panel_fixed_mode->vdisplay)
> + return MODE_PANEL;
> + }
> +
> + return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
> +}
> +
> +static bool intel_dsi_mode_fixup(struct drm_encoder *encoder,
> + const struct drm_display_mode *mode,
> + struct drm_display_mode *adjusted_mode)
> +{
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> +
> + DRM_DEBUG_KMS("\n");
> +
> + /* If we have timings from the BIOS for the panel, put them in
> + * to the adjusted mode. The CRTC will be set up for this mode,
> + * with the panel scaling set up to source from the H/VDisplay
> + * of the original mode.
> + */
> + if (intel_dsi->panel_fixed_mode != NULL) {
> +#define C(x) adjusted_mode->x = intel_dsi->panel_fixed_mode->x
> + C(hdisplay);
> + C(hsync_start);
> + C(hsync_end);
> + C(htotal);
> + C(vdisplay);
> + C(vsync_start);
> + C(vsync_end);
> + C(vtotal);
> + C(clock);
> +#undef C
> + }
> +
> + if (intel_dsi->dev.dev_ops->mode_fixup)
> + return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, mode, adjusted_mode);
> +
> + return true;
> +}
> +
> +/* return pixels in terms of txbyteclkhs */
> +static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
> +{
> + return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
> +}
> +
> +static void set_dsi_timings(struct drm_encoder *encoder,
> + const struct drm_display_mode *mode)
> +{
> + struct drm_device *dev = encoder->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> + int pipe = intel_crtc->pipe;
> + unsigned int bpp = intel_crtc->config.pipe_bpp;
> + unsigned int lane_count = intel_dsi->lane_count;
> +
> + u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
> +
> + hactive = mode->hdisplay;
> + hfp = mode->hsync_start - mode->hdisplay;
> + hsync = mode->hsync_end - mode->hsync_start;
> + hbp = mode->htotal - mode->hsync_end;
> +
> + vfp = mode->vsync_start - mode->vdisplay;
> + vsync = mode->vsync_end - mode->vsync_start;
> + vbp = mode->vtotal - mode->vsync_end;
> +
> + /* horizontal values are in terms of high speed byte clock */
> + hactive = txbyteclkhs(hactive, bpp, lane_count);
> + hfp = txbyteclkhs(hfp, bpp, lane_count);
> + hsync = txbyteclkhs(hsync, bpp, lane_count);
> + hbp = txbyteclkhs(hbp, bpp, lane_count);
> +
> + I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
> + I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
> +
> + /* meaningful for video mode non-burst sync pulse mode only, can be zero
> + * for non-burst sync events and burst modes */
> + I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
> + I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
> +
> + /* vertical values are in terms of lines */
> + I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
> + I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
> + I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
> +}
> +
> +static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
> +{
> + struct drm_encoder *encoder = &intel_encoder->base;
> + struct drm_device *dev = encoder->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> + struct drm_display_mode *adjusted_mode =
> + &intel_crtc->config.adjusted_mode;
> + int pipe = intel_crtc->pipe;
> + unsigned int bpp = intel_crtc->config.pipe_bpp;
> + u32 val, tmp;
> +
> + DRM_DEBUG_KMS("pipe %d\n", pipe);
> +
> + /* escape clock divider, 20MHz, shared for A and C. device ready must be
> + * off when doing this! txclkesc? */
> + tmp = I915_READ(MIPI_CTRL(0));
> + tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> + I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
> +
> + /* read request priority is per pipe */
> + tmp = I915_READ(MIPI_CTRL(pipe));
> + tmp &= ~READ_REQUEST_PRIORITY_MASK;
> + I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
> +
> + /* XXX: why here, why like this? handling in irq handler?! */
> + I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
> + I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
> +
> + I915_WRITE(MIPI_DPHY_PARAM(pipe),
> + 0x3c << EXIT_ZERO_COUNT_SHIFT |
> + 0x1f << TRAIL_COUNT_SHIFT |
> + 0xc5 << CLK_ZERO_COUNT_SHIFT |
> + 0x1f << PREPARE_COUNT_SHIFT);
> +
> + I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
> + adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
> + adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
> +
> + set_dsi_timings(encoder, adjusted_mode);
> +
> + val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
> + if (is_cmd_mode(intel_dsi)) {
> + val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
> + val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
> + } else {
> + val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
> +
> + /* XXX: cross-check bpp vs. pixel format? */
> + val |= intel_dsi->pixel_format;
> + }
> + I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
> +
> + /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
> + * stop state. */
> +
> + if (is_vid_mode(intel_dsi) &&
> + intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
> + I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
> + txbyteclkhs(adjusted_mode->htotal + 1, bpp,
> + intel_dsi->lane_count));
> + } else {
> + I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
> + txbyteclkhs(adjusted_mode->vtotal *
> + adjusted_mode->htotal,
> + bpp, intel_dsi->lane_count));
> + }
> + I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), 0xffff);
> + I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), 0x14);
> +
> + I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), 0xffff);
> +
> + /* dphy stuff */
> +
> + /* in terms of low power clock */
> + I915_WRITE(MIPI_INIT_COUNT(pipe), 0x7d0);
> +
> + /* recovery disables */
> + I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
> +
> + /* in terms of txbyteclkhs. actual high to low switch +
> + * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
> + *
> + * XXX: write MIPI_STOP_STATE_STALL?
> + */
> + I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), 0x46);
> +
> + /* XXX: low power clock equivalence in terms of byte clock. the number
> + * of byte clocks occupied in one low power clock. based on txbyteclkhs
> + * and txclkesc. txclkesc time / txbyteclk time * (105 +
> + * MIPI_STOP_STATE_STALL) / 105.???
> + */
> + I915_WRITE(MIPI_LP_BYTECLK(pipe), 4);
> +
> + /* the bw essential for transmitting 16 long packets containing 252
> + * bytes meant for dcs write memory command is programmed in this
> + * register in terms of byte clocks. based on dsi transfer rate and the
> + * number of lanes configured the time taken to transmit 16 long packets
> + * in a dsi stream varies. */
> + I915_WRITE(MIPI_DBI_BW_CTRL(pipe), 0x820);
> +
> + I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
> + 0xa << LP_HS_SSW_CNT_SHIFT |
> + 0x14 << HS_LP_PWR_SW_CNT_SHIFT);
> +
> + if (is_vid_mode(intel_dsi))
> + I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
> + intel_dsi->video_mode_format);
> +}
> +
> +static enum drm_connector_status
> +intel_dsi_detect(struct drm_connector *connector, bool force)
> +{
> + struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
> + DRM_DEBUG_KMS("\n");
> + return intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
> +}
> +
> +static int intel_dsi_get_modes(struct drm_connector *connector)
> +{
> + struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
> + struct drm_display_mode *mode;
> +
> + DRM_DEBUG_KMS("\n");
> +
> + if (!intel_dsi->panel_fixed_mode) {
> + DRM_DEBUG_KMS("no fixed mode\n");
> + return 0;
> + }
> +
> + mode = drm_mode_duplicate(connector->dev, intel_dsi->panel_fixed_mode);
> + if (!mode) {
> + DRM_DEBUG_KMS("dupe failed\n");
> + return 0;
> + }
> +
> + drm_mode_probed_add(connector, mode);
> + return 1;
> +}
> +
> +static void intel_dsi_destroy(struct drm_connector *connector)
> +{
> + DRM_DEBUG_KMS("\n");
> + drm_sysfs_connector_remove(connector);
> + drm_connector_cleanup(connector);
> + kfree(connector);
> +}
> +
> +static const struct drm_encoder_helper_funcs intel_dsi_helper_funcs = {
> + .mode_fixup = intel_dsi_mode_fixup,
> +};
> +
> +static const struct drm_encoder_funcs intel_dsi_funcs = {
> + .destroy = intel_encoder_destroy,
> +};
> +
> +static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
> + .get_modes = intel_dsi_get_modes,
> + .mode_valid = intel_dsi_mode_valid,
> + .best_encoder = intel_best_encoder,
> +};
> +
> +static const struct drm_connector_funcs intel_dsi_connector_funcs = {
> + .dpms = intel_connector_dpms,
> + .detect = intel_dsi_detect,
> + .destroy = intel_dsi_destroy,
> + .fill_modes = drm_helper_probe_single_connector_modes,
> +};
> +
> +bool intel_dsi_init(struct drm_device *dev)
> +{
> + struct intel_dsi *intel_dsi;
> + struct intel_encoder *intel_encoder;
> + struct drm_encoder *encoder;
> + struct intel_connector *intel_connector;
> + struct drm_connector *connector;
> + struct drm_display_mode *fixed_mode = NULL;
> + const struct intel_dsi_device *dsi;
> + unsigned int i;
> +
> + DRM_DEBUG_KMS("\n");
> +
> + intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
> + if (!intel_dsi)
> + return false;
> +
> + intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
> + if (!intel_connector) {
> + kfree(intel_dsi);
> + return false;
> + }
> +
> + intel_encoder = &intel_dsi->base;
> + encoder = &intel_encoder->base;
> +
> + connector = &intel_connector->base;
> +
> + drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
> +
> + /* XXX: very likely not all of these are needed */
> + intel_encoder->hot_plug = intel_dsi_hot_plug;
> + intel_encoder->compute_config = intel_dsi_compute_config;
> + intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
> + intel_encoder->pre_enable = intel_dsi_pre_enable;
> + intel_encoder->enable = intel_dsi_enable;
> + intel_encoder->mode_set = intel_dsi_mode_set;
> + intel_encoder->disable = intel_dsi_disable;
> + intel_encoder->post_disable = intel_dsi_post_disable;
> + intel_encoder->get_hw_state = intel_dsi_get_hw_state;
> + intel_encoder->get_config = intel_dsi_get_config;
> +
> + intel_connector->get_hw_state = intel_connector_get_hw_state;
> +
> + for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
> + dsi = &intel_dsi_devices[i];
> + intel_dsi->dev = *dsi;
> +
> + if (dsi->dev_ops->init(&intel_dsi->dev))
> + break;
> + }
> +
> + if (i == ARRAY_SIZE(intel_dsi_devices)) {
> + DRM_DEBUG_KMS("no device found\n");
> + goto err;
> + }
> +
> + intel_encoder->type = INTEL_OUTPUT_DSI;
> + intel_encoder->crtc_mask = (1 << 0); /* XXX */
> +
> + intel_encoder->cloneable = false;
> + drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
> + DRM_MODE_CONNECTOR_DSI);
> +
> + drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
> +
> + connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
> + connector->interlace_allowed = false;
> + connector->doublescan_allowed = false;
> +
> + drm_encoder_helper_add(encoder, &intel_dsi_helper_funcs);
> +
> + intel_connector_attach_encoder(intel_connector, intel_encoder);
> +
> + drm_sysfs_connector_add(connector);
> +
> + fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
> + if (!fixed_mode) {
> + DRM_DEBUG_KMS("no fixed mode\n");
> + goto err;
> + }
> +
> + fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
> +
> + intel_dsi->panel_fixed_mode = fixed_mode;
> +
> + intel_panel_init(&intel_connector->panel, fixed_mode);
> +
> + return true;
> +
> +err:
> + drm_encoder_cleanup(&intel_encoder->base);
> + kfree(intel_dsi);
> + kfree(intel_connector);
> +
> + return false;
> +}
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 09/14] drm/i915: add VLV DSI PLL Calculations
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
` (7 preceding siblings ...)
2013-08-13 13:29 ` [PATCH 08/14] drm/i915: add basic MIPI DSI output support Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
2013-08-13 13:29 ` [PATCH 10/14] drm/i915: don't enable DPLL for DSI Jani Nikula
` (4 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
From: ymohanma <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: ymohanma <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_reg.h | 10 ++
drivers/gpu/drm/i915/intel_display.c | 2 +
drivers/gpu/drm/i915/intel_dsi.c | 5 +
drivers/gpu/drm/i915/intel_dsi.h | 2 +
drivers/gpu/drm/i915/intel_dsi_pll.c | 290 ++++++++++++++++++++++++++++++++++
6 files changed, 310 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_dsi_pll.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5864c5b..65e60d2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -23,6 +23,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
intel_lvds.o \
intel_dsi.o \
intel_dsi_cmd.o \
+ intel_dsi_pll.o \
intel_bios.o \
intel_ddi.o \
intel_dp.o \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 32e32b6..5713540 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -390,6 +390,16 @@
#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
+/* vlv2 north clock has */
+#define CCK_REG_DSI_PLL_FUSE 0x44
+#define CCK_REG_DSI_PLL_CONTROL 0x48
+#define DSI_PLL_VCO_EN (1 << 31)
+#define DSI_PLL_LDO_GATE (1 << 30)
+#define DSI_PLL_P1_POST_DIV_SHIFT 17
+#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
+#define DSI_PLL_LOCK (1 << 0)
+#define CCK_REG_DSI_PLL_DIVIDER 0x4c
+
/*
* DPIO - a special bus for various display related registers to hide behind
*
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cec9189..78c42a1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1683,6 +1683,7 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
* need the check.
*/
if (!HAS_PCH_SPLIT(dev_priv->dev))
+ /* XXX: Fix for DSI PLL */
assert_pll_enabled(dev_priv, pipe);
else {
if (pch_port) {
@@ -6495,6 +6496,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
return;
if (!HAS_PCH_SPLIT(dev_priv->dev))
+ /* XXX: Fix for DSI PLL */
assert_pll_enabled(dev_priv, pipe);
/* use legacy palette for Ironlake */
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index aa81dd8..1dc5a77 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -68,6 +68,8 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
{
DRM_DEBUG_KMS("\n");
+
+ vlv_enable_dsi_pll(encoder);
}
static void intel_dsi_pre_enable(struct intel_encoder *encoder)
@@ -294,6 +296,9 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
DRM_DEBUG_KMS("pipe %d\n", pipe);
+ /* Update the DSI PLL */
+ vlv_enable_dsi_pll(intel_encoder);
+
/* escape clock divider, 20MHz, shared for A and C. device ready must be
* off when doing this! txclkesc? */
tmp = I915_READ(MIPI_CTRL(0));
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 45f649a..0e0a212 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -96,4 +96,6 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
return container_of(encoder, struct intel_dsi, base.base);
}
+extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
+
#endif /* _INTEL_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
new file mode 100644
index 0000000..12ede64
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Shobhit Kumar <shobhit.kumar@intel.com>
+ * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
+ */
+
+#include <linux/kernel.h>
+#include "intel_drv.h"
+#include "i915_drv.h"
+#include "intel_dsi.h"
+
+#define DSI_HSS_PACKET_SIZE 4
+#define DSI_HSE_PACKET_SIZE 4
+#define DSI_HSA_PACKET_EXTRA_SIZE 6
+#define DSI_HBP_PACKET_EXTRA_SIZE 6
+#define DSI_HACTIVE_PACKET_EXTRA_SIZE 6
+#define DSI_HFP_PACKET_EXTRA_SIZE 6
+#define DSI_EOTP_PACKET_SIZE 4
+
+struct dsi_clock_table {
+ u32 freq;
+ u8 m;
+ u8 p;
+};
+
+struct dsi_mnp {
+ u32 dsi_pll_ctrl;
+ u32 dsi_pll_div;
+};
+
+static u32 lfsr_converts[] = {
+ 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
+ 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
+ 106, 53, 282, 397, 354, 227, 113, 56, 284, 142, /* 81 - 90 */
+ 71, 35 /* 91 - 92 */
+};
+
+struct dsi_clock_table dsi_clk_tbl[] = {
+ {300, 72, 6}, {313, 75, 6}, {323, 78, 6}, {333, 80, 6},
+ {343, 82, 6}, {353, 85, 6}, {363, 87, 6}, {373, 90, 6},
+ {383, 92, 6}, {390, 78, 5}, {393, 79, 5}, {400, 80, 5},
+ {401, 80, 5}, {402, 80, 5}, {403, 81, 5}, {404, 81, 5},
+ {405, 81, 5}, {406, 81, 5}, {407, 81, 5}, {408, 82, 5},
+ {409, 82, 5}, {410, 82, 5}, {411, 82, 5}, {412, 82, 5},
+ {413, 83, 5}, {414, 83, 5}, {415, 83, 5}, {416, 83, 5},
+ {417, 83, 5}, {418, 84, 5}, {419, 84, 5}, {420, 84, 5},
+ {430, 86, 5}, {440, 88, 5}, {450, 90, 5}, {460, 92, 5},
+ {470, 75, 4}, {480, 77, 4}, {490, 78, 4}, {500, 80, 4},
+ {510, 82, 4}, {520, 83, 4}, {530, 85, 4}, {540, 86, 4},
+ {550, 88, 4}, {560, 90, 4}, {570, 91, 4}, {580, 70, 3},
+ {590, 71, 3}, {600, 72, 3}, {610, 73, 3}, {620, 74, 3},
+ {630, 76, 3}, {640, 77, 3}, {650, 78, 3}, {660, 79, 3},
+ {670, 80, 3}, {680, 82, 3}, {690, 83, 3}, {700, 84, 3},
+ {710, 85, 3}, {720, 86, 3}, {730, 88, 3}, {740, 89, 3},
+ {750, 90, 3}, {760, 91, 3}, {770, 92, 3}, {780, 62, 2},
+ {790, 63, 2}, {800, 64, 2}, {880, 70, 2}, {900, 72, 2},
+ {1000, 80, 2}, /* dsi clock frequency in Mhz*/
+};
+
+static u32 dsi_rr_formula(struct drm_display_mode *mode,
+ int pixel_format, int video_mode_format,
+ int lane_count, bool eotp)
+{
+ u32 bpp;
+ u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp;
+ u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes;
+ u32 bytes_per_line, bytes_per_frame;
+ u32 num_frames;
+ u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes;
+ u32 dsi_bit_clock_hz;
+ u32 dsi_clk;
+
+ switch (pixel_format) {
+ default:
+ case VID_MODE_FORMAT_RGB888:
+ case VID_MODE_FORMAT_RGB666_LOOSE:
+ bpp = 24;
+ break;
+ case VID_MODE_FORMAT_RGB666:
+ bpp = 18;
+ break;
+ case VID_MODE_FORMAT_RGB565:
+ bpp = 16;
+ break;
+ }
+
+ hactive = mode->hdisplay;
+ vactive = mode->vdisplay;
+ hfp = mode->hsync_start - mode->hdisplay;
+ hsync = mode->hsync_end - mode->hsync_start;
+ hbp = mode->htotal - mode->hsync_end;
+
+ vfp = mode->vsync_start - mode->vdisplay;
+ vsync = mode->vsync_end - mode->vsync_start;
+ vbp = mode->vtotal - mode->vsync_end;
+
+ hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8);
+ hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8);
+ hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8);
+ hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8);
+
+ bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes +
+ DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE +
+ hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE +
+ hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE +
+ hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE;
+
+ /*
+ * XXX: Need to accurately calculate LP to HS transition timeout and add
+ * it to bytes_per_line/bytes_per_frame.
+ */
+
+ if (eotp && video_mode_format == VIDEO_MODE_BURST)
+ bytes_per_line += DSI_EOTP_PACKET_SIZE;
+
+ bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line +
+ vactive * bytes_per_line + vfp * bytes_per_line;
+
+ if (eotp &&
+ (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ||
+ video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS))
+ bytes_per_frame += DSI_EOTP_PACKET_SIZE;
+
+ num_frames = (mode->clock * 1000) / (mode->htotal * mode->vtotal);
+ bytes_per_x_frames = num_frames * bytes_per_frame;
+
+ bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count;
+
+ /* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */
+ dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8;
+ dsi_clk = dsi_bit_clock_hz / (1000 * 1000);
+
+ if (eotp && video_mode_format == VIDEO_MODE_BURST)
+ dsi_clk *= 2;
+
+ return dsi_clk;
+}
+
+static int mnp_from_clk_table(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
+{
+ unsigned int i;
+ u8 m;
+ u8 n;
+ u8 p;
+ u32 m_seed;
+
+ if (dsi_clk < 300 || dsi_clk > 1000)
+ return -ECHRNG;
+
+ for (i = 0; i <= ARRAY_SIZE(dsi_clk_tbl); i++) {
+ if (dsi_clk_tbl[i].freq > dsi_clk)
+ break;
+ }
+
+ m = dsi_clk_tbl[i].m;
+ p = dsi_clk_tbl[i].p;
+ m_seed = lfsr_converts[m - 62];
+ n = 1;
+ dsi_mnp->dsi_pll_ctrl = (1 << (17 + p - 2)) | (1 << 8);
+ dsi_mnp->dsi_pll_div = ((n - 1) << 16) | m_seed;
+
+ return 0;
+}
+
+static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
+{
+ u32 m, n, p;
+ u32 ref_clk;
+ u32 error;
+ u32 tmp_error;
+ u32 target_dsi_clk;
+ u32 calc_dsi_clk;
+ u32 calc_m;
+ u32 calc_p;
+ u32 m_seed;
+
+ if (dsi_clk < 300 || dsi_clk > 1150) {
+ DRM_ERROR("DSI CLK Out of Range\n");
+ return -ECHRNG;
+ }
+
+ ref_clk = 25000;
+ target_dsi_clk = dsi_clk * 1000;
+ error = 0xFFFFFFFF;
+ tmp_error = 0xFFFFFFFF;
+ calc_m = 0;
+ calc_p = 0;
+
+ for (m = 62; m <= 92; m++) {
+ for (p = 2; p <= 6; p++) {
+
+ calc_dsi_clk = (m * ref_clk) / p;
+ if (calc_dsi_clk >= target_dsi_clk) {
+ tmp_error = calc_dsi_clk - target_dsi_clk;
+ if (tmp_error < error) {
+ error = tmp_error;
+ calc_m = m;
+ calc_p = p;
+ }
+ }
+ }
+ }
+
+ m_seed = lfsr_converts[calc_m - 62];
+ n = 1;
+ dsi_mnp->dsi_pll_ctrl = (1 << (17 + calc_p - 2)) | (1 << 8);
+ dsi_mnp->dsi_pll_div = ((n - 1) << 16) | m_seed;
+
+ return 0;
+}
+
+static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+ struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ int ret;
+ struct dsi_mnp dsi_mnp;
+ u32 dsi_clk;
+
+ dsi_clk = dsi_rr_formula(mode, intel_dsi->pixel_format,
+ intel_dsi->video_mode_format,
+ intel_dsi->lane_count, !intel_dsi->eot_disable);
+
+#if 0
+ ret = mnp_from_clk_table(dsi_clk, &dsi_mnp);
+#else
+ ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
+#endif
+
+ if (ret) {
+ DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
+ return;
+ }
+
+ DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
+ dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
+
+ vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
+ vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
+ vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
+}
+
+void vlv_enable_dsi_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+ int pipe = intel_crtc->pipe;
+ u32 tmp;
+
+ DRM_DEBUG_KMS("\n");
+
+ vlv_configure_dsi_pll(encoder);
+
+ /* wait 0.5us after ungating before enabling again */
+ udelay(1 * 1000);
+
+ tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
+ tmp |= DSI_PLL_VCO_EN;
+ vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
+
+ if (wait_for(I915_READ(PIPECONF(pipe)) & PIPECONF_DSI_PLL_LOCKED, 20)) {
+ DRM_ERROR("DSI PLL lock failed\n");
+ return;
+ }
+
+ DRM_DEBUG_KMS("DSI PLL locked\n");
+}
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 10/14] drm/i915: don't enable DPLL for DSI
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
` (8 preceding siblings ...)
2013-08-13 13:29 ` [PATCH 09/14] drm/i915: add VLV DSI PLL Calculations Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
2013-08-13 13:29 ` [PATCH 11/14] drm/i915: Band Gap WA Jani Nikula
` (3 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
DPLL is not needed for DSI
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 48 ++++++++++++++++++++--------------
1 file changed, 29 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 78c42a1..e3ca335 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3660,7 +3660,8 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
if (encoder->pre_pll_enable)
encoder->pre_pll_enable(encoder);
- vlv_enable_pll(intel_crtc);
+ if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
+ vlv_enable_pll(intel_crtc);
for_each_encoder_on_crtc(dev, crtc, encoder)
if (encoder->pre_enable)
@@ -3775,7 +3776,8 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
if (encoder->post_disable)
encoder->post_disable(encoder);
- i9xx_disable_pll(dev_priv, pipe);
+ if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
+ i9xx_disable_pll(dev_priv, pipe);
intel_crtc->active = false;
intel_update_fbc(dev);
@@ -4843,7 +4845,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
intel_clock_t clock, reduced_clock;
u32 dspcntr;
bool ok, has_reduced_clock = false;
- bool is_lvds = false;
+ bool is_lvds = false, is_dsi = false;
struct intel_encoder *encoder;
const intel_limit_t *limit;
int ret;
@@ -4853,6 +4855,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
case INTEL_OUTPUT_LVDS:
is_lvds = true;
break;
+ case INTEL_OUTPUT_DSI:
+ is_dsi = true;
+ break;
}
num_connectors++;
@@ -4860,18 +4865,21 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
refclk = i9xx_get_refclk(crtc, num_connectors);
- /*
- * Returns a set of divisors for the desired target clock with the given
- * refclk, or FALSE. The returned values represent the clock equation:
- * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
- */
- limit = intel_limit(crtc, refclk);
- ok = dev_priv->display.find_dpll(limit, crtc,
- intel_crtc->config.port_clock,
- refclk, NULL, &clock);
- if (!ok && !intel_crtc->config.clock_set) {
- DRM_ERROR("Couldn't find PLL settings for mode!\n");
- return -EINVAL;
+ if (!is_dsi) {
+ /*
+ * Returns a set of divisors for the desired target clock with
+ * the given refclk, or FALSE. The returned values represent
+ * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
+ * 2) / p1 / p2.
+ */
+ limit = intel_limit(crtc, refclk);
+ ok = dev_priv->display.find_dpll(limit, crtc,
+ intel_crtc->config.port_clock,
+ refclk, NULL, &clock);
+ if (!ok && !intel_crtc->config.clock_set) {
+ DRM_ERROR("Couldn't find PLL settings for mode!\n");
+ return -EINVAL;
+ }
}
/* Ensure that the cursor is valid for the new mode before changing... */
@@ -4899,16 +4907,18 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
intel_crtc->config.dpll.p2 = clock.p2;
}
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev)) {
i8xx_update_pll(intel_crtc,
has_reduced_clock ? &reduced_clock : NULL,
num_connectors);
- else if (IS_VALLEYVIEW(dev))
- vlv_update_pll(intel_crtc);
- else
+ } else if (IS_VALLEYVIEW(dev)) {
+ if (!is_dsi)
+ vlv_update_pll(intel_crtc);
+ } else {
i9xx_update_pll(intel_crtc,
has_reduced_clock ? &reduced_clock : NULL,
num_connectors);
+ }
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 11/14] drm/i915: Band Gap WA
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
` (9 preceding siblings ...)
2013-08-13 13:29 ` [PATCH 10/14] drm/i915: don't enable DPLL for DSI Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
2013-08-13 13:29 ` [PATCH 12/14] drm/i915: Parse the MIPI related VBT Block and store relevant info Jani Nikula
` (2 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
From: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: ymohanma <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 48 ++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 1dc5a77..d28be01 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -37,6 +37,51 @@
static const struct intel_dsi_device intel_dsi_devices[] = {
};
+
+static void vlv_cck_modify(struct drm_i915_private *dev_priv, u32 reg, u32 val,
+ u32 mask)
+{
+ u32 tmp = vlv_cck_read(dev_priv, reg);
+ tmp &= ~mask;
+ tmp |= val;
+ vlv_cck_write(dev_priv, reg, tmp);
+}
+
+static void band_gap_wa(struct drm_i915_private *dev_priv)
+{
+ mutex_lock(&dev_priv->dpio_lock);
+
+ /* Enable bandgap fix in GOP driver */
+ vlv_cck_modify(dev_priv, 0x6D, 0x00010000, 0x00030000);
+ msleep(20);
+ vlv_cck_modify(dev_priv, 0x6E, 0x00010000, 0x00030000);
+ msleep(20);
+ vlv_cck_modify(dev_priv, 0x6F, 0x00010000, 0x00030000);
+ msleep(20);
+ vlv_cck_modify(dev_priv, 0x00, 0x00008000, 0x00008000);
+ msleep(20);
+ vlv_cck_modify(dev_priv, 0x00, 0x00000000, 0x00008000);
+ msleep(20);
+
+ /* Turn Display Trunk on */
+ vlv_cck_modify(dev_priv, 0x6B, 0x00020000, 0x00030000);
+ msleep(20);
+
+ vlv_cck_modify(dev_priv, 0x6C, 0x00020000, 0x00030000);
+ msleep(20);
+
+ vlv_cck_modify(dev_priv, 0x6D, 0x00020000, 0x00030000);
+ msleep(20);
+ vlv_cck_modify(dev_priv, 0x6E, 0x00020000, 0x00030000);
+ msleep(20);
+ vlv_cck_modify(dev_priv, 0x6F, 0x00020000, 0x00030000);
+
+ mutex_unlock(&dev_priv->dpio_lock);
+
+ /* Need huge delay, otherwise clock is not stable */
+ msleep(100);
+}
+
static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
{
return container_of(intel_attached_encoder(connector),
@@ -299,6 +344,9 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
/* Update the DSI PLL */
vlv_enable_dsi_pll(intel_encoder);
+ /* XXX: Location of the call */
+ band_gap_wa(dev_priv);
+
/* escape clock divider, 20MHz, shared for A and C. device ready must be
* off when doing this! txclkesc? */
tmp = I915_READ(MIPI_CTRL(0));
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 12/14] drm/i915: Parse the MIPI related VBT Block and store relevant info
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
` (10 preceding siblings ...)
2013-08-13 13:29 ` [PATCH 11/14] drm/i915: Band Gap WA Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
2013-08-13 13:29 ` [PATCH 13/14] drm/i915: initialize DSI output on VLV Jani Nikula
2013-08-13 13:29 ` [PATCH 14/14] drm/i915: add AUO MIPI DSI display sub-encoder Jani Nikula
13 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
From: Shobhit Kumar <shobhit.kumar@intel.com>
Initial parsing of the VBT MIPI block. For now, just store the panel id
if found.
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 5 +++++
drivers/gpu/drm/i915/intel_bios.c | 16 +++++++++++++++
drivers/gpu/drm/i915/intel_bios.h | 41 +++++++++++++++++++++++++++++++++++++
3 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6db95a2..5be251b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1053,6 +1053,11 @@ struct intel_vbt_data {
int edp_bpp;
struct edp_power_seq edp_pps;
+ /* MIPI DSI */
+ struct {
+ u16 panel_id;
+ } dsi;
+
int crt_ddc_pin;
int child_dev_num;
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 53f2bed..6668873 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -569,6 +569,21 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
}
static void
+parse_mipi(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
+{
+ struct bdb_mipi *mipi;
+
+ mipi = find_section(bdb, BDB_MIPI);
+ if (!mipi) {
+ DRM_DEBUG_KMS("No MIPI BDB found");
+ return;
+ }
+
+ /* XXX: add more info */
+ dev_priv->vbt.dsi.panel_id = mipi->panel_id;
+}
+
+static void
parse_device_mapping(struct drm_i915_private *dev_priv,
struct bdb_header *bdb)
{
@@ -745,6 +760,7 @@ intel_parse_bios(struct drm_device *dev)
parse_device_mapping(dev_priv, bdb);
parse_driver_features(dev_priv, bdb);
parse_edp(dev_priv, bdb);
+ parse_mipi(dev_priv, bdb);
if (bios)
pci_unmap_rom(pdev, bios);
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index e088d6f..6e9250e 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -104,6 +104,7 @@ struct vbios_data {
#define BDB_LVDS_LFP_DATA 42
#define BDB_LVDS_BACKLIGHT 43
#define BDB_LVDS_POWER 44
+#define BDB_MIPI 50
#define BDB_SKIP 254 /* VBIOS private block, ignore */
struct bdb_general_features {
@@ -618,4 +619,44 @@ int intel_parse_bios(struct drm_device *dev);
#define PORT_IDPC 8
#define PORT_IDPD 9
+/* MIPI DSI panel info */
+struct bdb_mipi {
+ u16 panel_id;
+ u16 bridge_revision;
+
+ /* General params */
+ u32 dithering:1;
+ u32 bpp_pixel_format:1;
+ u32 rsvd1:1;
+ u32 dphy_valid:1;
+ u32 resvd2:28;
+
+ u16 port_info;
+ u16 rsvd3:2;
+ u16 num_lanes:2;
+ u16 rsvd4:12;
+
+ /* DSI config */
+ u16 virt_ch_num:2;
+ u16 vtm:2;
+ u16 rsvd5:12;
+
+ u32 dsi_clock;
+ u32 bridge_ref_clk;
+ u16 rsvd_pwr;
+
+ /* Dphy Params */
+ u32 prepare_cnt:5;
+ u32 rsvd6:3;
+ u32 clk_zero_cnt:8;
+ u32 trail_cnt:5;
+ u32 rsvd7:3;
+ u32 exit_zero_cnt:6;
+ u32 rsvd8:2;
+
+ u32 hl_switch_cnt;
+ u32 lp_byte_clk;
+ u32 clk_lane_switch_cnt;
+} __attribute__((packed));
+
#endif /* _I830_BIOS_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 13/14] drm/i915: initialize DSI output on VLV
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
` (11 preceding siblings ...)
2013-08-13 13:29 ` [PATCH 12/14] drm/i915: Parse the MIPI related VBT Block and store relevant info Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
2013-08-13 13:29 ` [PATCH 14/14] drm/i915: add AUO MIPI DSI display sub-encoder Jani Nikula
13 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e3ca335..7edb9c0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9357,6 +9357,8 @@ static void intel_setup_outputs(struct drm_device *dev)
if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
}
+
+ intel_dsi_init(dev);
} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
bool found = false;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 14/14] drm/i915: add AUO MIPI DSI display sub-encoder
2013-08-13 13:29 [PATCH 00/14] drm/i915: Baytrail MIPI DSI support Jani Nikula
` (12 preceding siblings ...)
2013-08-13 13:29 ` [PATCH 13/14] drm/i915: initialize DSI output on VLV Jani Nikula
@ 2013-08-13 13:29 ` Jani Nikula
13 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2013-08-13 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, yogesh.mohan.marimuthu
From: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/auo_dsi_display.c | 182 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dsi.c | 5 +
drivers/gpu/drm/i915/intel_dsi.h | 3 +
4 files changed, 191 insertions(+)
create mode 100644 drivers/gpu/drm/i915/auo_dsi_display.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 65e60d2..18bf236 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -42,6 +42,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
intel_opregion.o \
intel_sideband.o \
intel_uncore.o \
+ auo_dsi_display.o \
dvo_ch7xxx.o \
dvo_ch7017.o \
dvo_ivch.o \
diff --git a/drivers/gpu/drm/i915/auo_dsi_display.c b/drivers/gpu/drm/i915/auo_dsi_display.c
new file mode 100644
index 0000000..771a725
--- /dev/null
+++ b/drivers/gpu/drm/i915/auo_dsi_display.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jani Nikula <jani.nikula@intel.com>
+ * Shobhit Kumar <shobhit.kumar@intel.com>
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_edid.h>
+#include <drm/i915_drm.h>
+#include <linux/slab.h>
+#include <video/mipi_display.h>
+#include "i915_drv.h"
+#include "intel_drv.h"
+#include "intel_dsi.h"
+#include "intel_dsi_cmd.h"
+
+#if 0 /* XXX */
+static void auo_vid_get_panel_info(int pipe, struct drm_connector *connector)
+{
+ DRM_DEBUG_KMS("\n");
+ if (!connector)
+ return;
+
+ if (pipe == 0) {
+ connector->display_info.width_mm = 216;
+ connector->display_info.height_mm = 135;
+ }
+
+ return;
+}
+#endif
+
+static bool auo_init(struct intel_dsi_device *dsi)
+{
+ struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
+
+ DRM_DEBUG_KMS("\n");
+
+ intel_dsi->eot_disable = 0;
+ intel_dsi->pixel_format = VID_MODE_FORMAT_RGB888;
+ intel_dsi->video_mode_format = VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE;
+ intel_dsi->lane_count = 4;
+
+ return true;
+}
+
+static void auo_enable(struct intel_dsi_device *dsi)
+{
+ struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
+
+ DRM_DEBUG_KMS("\n");
+
+ dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_EXIT_SLEEP_MODE);
+
+ dsi_vc_dcs_write_1(intel_dsi, 0, MIPI_DCS_SET_TEAR_ON, 0x00);
+
+ dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_ON);
+ dsi_vc_dcs_write_1(intel_dsi, 0, 0x14, 0x55);
+}
+
+static void auo_disable(struct intel_dsi_device *dsi)
+{
+ struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
+
+ DRM_DEBUG_KMS("\n");
+
+ dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_OFF);
+ dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_ENTER_SLEEP_MODE);
+}
+
+static int auo_mode_valid(struct intel_dsi_device *dsi,
+ struct drm_display_mode *mode)
+{
+ return MODE_OK;
+}
+
+static bool auo_mode_fixup(struct intel_dsi_device *dsi,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+static void auo_mode_set(struct intel_dsi_device *dsi,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+}
+
+static enum drm_connector_status auo_detect(struct intel_dsi_device *dsi)
+{
+ return connector_status_connected;
+}
+
+static bool auo_get_hw_state(struct intel_dsi_device *dev)
+{
+ return true;
+}
+
+static struct drm_display_mode *auo_get_modes(struct intel_dsi_device *dsi)
+{
+ struct drm_display_mode *mode = NULL;
+ u32 hblank = 0x78;
+ u32 vblank = 0x0C;
+ u32 hsync_offset = 0x28;
+ u32 hsync_width = 0x28;
+ u32 vsync_offset = 0x4;
+ u32 vsync_width = 0x4;
+
+ /* Allocate */
+ mode = kzalloc(sizeof(*mode), GFP_KERNEL);
+ if (!mode) {
+ DRM_DEBUG_KMS("AUO Panel: No memory\n");
+ return NULL;
+ }
+
+ /* Hardcode 1920x1200*/
+ strcpy(mode->name, "1920x1200");
+ mode->hdisplay = 0x780;
+ mode->vdisplay = 0x4B0;
+ mode->vrefresh = 60;
+ mode->clock = 148350;
+
+ /* Calculate */
+ mode->hsync_start = mode->hdisplay + hsync_offset;
+ mode->hsync_end = mode->hdisplay + hsync_offset
+ + hsync_width;
+ mode->htotal = mode->hdisplay + hblank;
+ mode->vsync_start = mode->vdisplay + vsync_offset;
+ mode->vsync_end = mode->vdisplay + vsync_offset
+ + vsync_width;
+ mode->vtotal = mode->vdisplay + vblank;
+
+ /* Configure */
+ mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC;
+ mode->type |= DRM_MODE_TYPE_PREFERRED;
+ mode->status = MODE_OK;
+
+ return mode;
+}
+
+static void auo_destroy(struct intel_dsi_device *dsi)
+{
+}
+
+/* Callbacks. We might not need them all. */
+struct intel_dsi_dev_ops auo_dsi_display_ops = {
+ .init = auo_init,
+#if 0 /* XXX */
+ .get_info = auo_vid_get_panel_info,
+#endif
+ .enable = auo_enable,
+ .disable = auo_disable,
+ .mode_valid = auo_mode_valid,
+ .mode_fixup = auo_mode_fixup,
+ .mode_set = auo_mode_set,
+ .detect = auo_detect,
+ .get_hw_state = auo_get_hw_state,
+ .get_modes = auo_get_modes,
+ .destroy = auo_destroy,
+};
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index d28be01..a78f4f3 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -35,6 +35,11 @@
/* the sub-encoders aka panel drivers */
static const struct intel_dsi_device intel_dsi_devices[] = {
+ {
+ .type = INTEL_DSI_VIDEO_MODE,
+ .name = "auo-dsi-vid-mode-display",
+ .dev_ops = &auo_dsi_display_ops,
+ },
};
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 0e0a212..05f5ba1 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -98,4 +98,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
+/* the panel drivers */
+extern struct intel_dsi_dev_ops auo_dsi_display_ops;
+
#endif /* _INTEL_DSI_H */
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 20+ messages in thread