* [PATCH 1/1] arm: socfpga: Migrate CONFIG_HPS namespace to HPS
@ 2021-08-10 20:05 Tom Rini
2021-08-10 20:11 ` Marek Vasut
0 siblings, 1 reply; 7+ messages in thread
From: Tom Rini @ 2021-08-10 20:05 UTC (permalink / raw)
To: u-boot; +Cc: Marek Vasut, Simon Goldschmidt, Tien Fong Chee
None of the CONFIG_HPS namespace options are changed via the board
config.h file, nor does it make sense to move them to Kconfig. Rename
these options to the HPS namespace instead.
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Note, this patch is complete as the changes to the regex qts-filter.sh
are such a long line that git send-email fails. This patch was
generated by:
$ git grep -l CONFIG_HPS_ | xargs sed -i -e 's/CONFIG_HPS_/HPS_/g'
and I will re-run that before applying.
arch/arm/mach-socfpga/qts-filter.sh | 4 +-
arch/arm/mach-socfpga/wrap_iocsr_config.c | 8 +-
arch/arm/mach-socfpga/wrap_pll_config.c | 100 ++++++------
arch/arm/mach-socfpga/wrap_sdram_config.c | 148 +++++++++---------
board/altera/arria5-socdk/qts/iocsr_config.h | 8 +-
board/altera/arria5-socdk/qts/pll_config.h | 136 ++++++++--------
board/altera/arria5-socdk/qts/sdram_config.h | 140 ++++++++---------
.../altera/cyclone5-socdk/qts/iocsr_config.h | 8 +-
board/altera/cyclone5-socdk/qts/pll_config.h | 136 ++++++++--------
.../altera/cyclone5-socdk/qts/sdram_config.h | 140 ++++++++---------
board/aries/mcvevk/qts/iocsr_config.h | 8 +-
board/aries/mcvevk/qts/pll_config.h | 136 ++++++++--------
board/aries/mcvevk/qts/sdram_config.h | 140 ++++++++---------
board/devboards/dbm-soc1/qts/iocsr_config.h | 8 +-
board/devboards/dbm-soc1/qts/pll_config.h | 136 ++++++++--------
board/devboards/dbm-soc1/qts/sdram_config.h | 140 ++++++++---------
board/ebv/socrates/qts/iocsr_config.h | 8 +-
board/ebv/socrates/qts/pll_config.h | 136 ++++++++--------
board/ebv/socrates/qts/sdram_config.h | 140 ++++++++---------
board/is1/qts/iocsr_config.h | 8 +-
board/is1/qts/pll_config.h | 136 ++++++++--------
board/is1/qts/sdram_config.h | 140 ++++++++---------
board/keymile/secu1/qts/iocsr_config.h | 8 +-
board/keymile/secu1/qts/pll_config.h | 136 ++++++++--------
board/keymile/secu1/qts/sdram_config.h | 140 ++++++++---------
board/softing/vining_fpga/qts/iocsr_config.h | 8 +-
board/softing/vining_fpga/qts/pll_config.h | 136 ++++++++--------
board/softing/vining_fpga/qts/sdram_config.h | 140 ++++++++---------
board/sr1500/qts/iocsr_config.h | 8 +-
board/sr1500/qts/pll_config.h | 136 ++++++++--------
board/sr1500/qts/sdram_config.h | 140 ++++++++---------
board/terasic/de0-nano-soc/qts/iocsr_config.h | 8 +-
board/terasic/de0-nano-soc/qts/pll_config.h | 136 ++++++++--------
board/terasic/de0-nano-soc/qts/sdram_config.h | 146 ++++++++---------
board/terasic/de1-soc/qts/iocsr_config.h | 8 +-
board/terasic/de1-soc/qts/pll_config.h | 148 +++++++++---------
board/terasic/de1-soc/qts/sdram_config.h | 140 ++++++++---------
board/terasic/de10-nano/qts/iocsr_config.h | 8 +-
board/terasic/de10-nano/qts/pll_config.h | 136 ++++++++--------
board/terasic/de10-nano/qts/sdram_config.h | 140 ++++++++---------
board/terasic/sockit/qts/iocsr_config.h | 8 +-
board/terasic/sockit/qts/pll_config.h | 136 ++++++++--------
board/terasic/sockit/qts/sdram_config.h | 140 ++++++++---------
scripts/config_whitelist.txt | 142 -----------------
44 files changed, 1985 insertions(+), 2127 deletions(-)
diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh
index a49cd1b68a9e..3b66781cdf2e 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -36,7 +36,7 @@ EOF
# Retrieve the scan chain lengths
fix_newlines_in_macros \
${in_bsp_dir}/generated/iocsr_config_${soc}.h |
- grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' | tr -d "()"
+ grep 'HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' | tr -d "()"
echo ""
diff --git a/arch/arm/mach-socfpga/wrap_iocsr_config.c b/arch/arm/mach-socfpga/wrap_iocsr_config.c
index f810fade92a9..93ae1ebac9b0 100644
--- a/arch/arm/mach-socfpga/wrap_iocsr_config.c
+++ b/arch/arm/mach-socfpga/wrap_iocsr_config.c
@@ -17,19 +17,19 @@ int iocsr_get_config_table(const unsigned int chain_id,
switch (chain_id) {
case 0:
*table = iocsr_scan_chain0_table;
- *table_len = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH;
+ *table_len = HPS_IOCSR_SCANCHAIN0_LENGTH;
break;
case 1:
*table = iocsr_scan_chain1_table;
- *table_len = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH;
+ *table_len = HPS_IOCSR_SCANCHAIN1_LENGTH;
break;
case 2:
*table = iocsr_scan_chain2_table;
- *table_len = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH;
+ *table_len = HPS_IOCSR_SCANCHAIN2_LENGTH;
break;
case 3:
*table = iocsr_scan_chain3_table;
- *table_len = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH;
+ *table_len = HPS_IOCSR_SCANCHAIN3_LENGTH;
break;
default:
return -EINVAL;
diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c
index bd631e0fb5fb..54d088c40200 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config.c
@@ -8,116 +8,116 @@
#include <qts/pll_config.h>
#define MAIN_VCO_BASE ( \
- (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
+ (HPS_MAINPLLGRP_VCO_DENOM << \
CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
+ (HPS_MAINPLLGRP_VCO_NUMER << \
CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
)
#define PERI_VCO_BASE ( \
- (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
+ (HPS_PERPLLGRP_VCO_PSRC << \
CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
- (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
+ (HPS_PERPLLGRP_VCO_DENOM << \
CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
+ (HPS_PERPLLGRP_VCO_NUMER << \
CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
)
#define SDR_VCO_BASE ( \
- (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
+ (HPS_SDRPLLGRP_VCO_SSRC << \
CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
- (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
+ (HPS_SDRPLLGRP_VCO_DENOM << \
CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
+ (HPS_SDRPLLGRP_VCO_NUMER << \
CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
)
static const struct cm_config cm_default_cfg = {
/* main group */
MAIN_VCO_BASE,
- (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
+ (HPS_MAINPLLGRP_MPUCLK_CNT <<
CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
+ (HPS_MAINPLLGRP_MAINCLK_CNT <<
CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
+ (HPS_MAINPLLGRP_DBGATCLK_CNT <<
CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
+ (HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
+ (HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
+ (HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
+ (HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
+ (HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
+ (HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
+ (HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
+ (HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
+ (HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
+ (HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
+ (HPS_MAINPLLGRP_L4SRC_L4MP <<
CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
+ (HPS_MAINPLLGRP_L4SRC_L4SP <<
CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
/* peripheral group */
PERI_VCO_BASE,
- (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
+ (HPS_PERPLLGRP_EMAC0CLK_CNT <<
CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
+ (HPS_PERPLLGRP_EMAC1CLK_CNT <<
CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
+ (HPS_PERPLLGRP_PERQSPICLK_CNT <<
CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
+ (HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
+ (HPS_PERPLLGRP_PERBASECLK_CNT <<
CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
+ (HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
+ (HPS_PERPLLGRP_DIV_USBCLK <<
CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
+ (HPS_PERPLLGRP_DIV_SPIMCLK <<
CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
+ (HPS_PERPLLGRP_DIV_CAN0CLK <<
CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
+ (HPS_PERPLLGRP_DIV_CAN1CLK <<
CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
- (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
+ (HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
- (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
+ (HPS_PERPLLGRP_SRC_QSPI <<
CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
+ (HPS_PERPLLGRP_SRC_NAND <<
CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
+ (HPS_PERPLLGRP_SRC_SDMMC <<
CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
/* sdram pll group */
SDR_VCO_BASE,
- (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
+ (HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
+ (HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
+ (HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
+ (HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
+ (HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
+ (HPS_SDRPLLGRP_DDRDQCLK_CNT <<
CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
+ (HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
+ (HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
/* altera group */
- CONFIG_HPS_ALTERAGRP_MPUCLK,
+ HPS_ALTERAGRP_MPUCLK,
};
const struct cm_config * const cm_get_default_config(void)
@@ -128,19 +128,19 @@ const struct cm_config * const cm_get_default_config(void)
const unsigned int cm_get_osc_clk_hz(const int osc)
{
if (osc == 1)
- return CONFIG_HPS_CLK_OSC1_HZ;
+ return HPS_CLK_OSC1_HZ;
else if (osc == 2)
- return CONFIG_HPS_CLK_OSC2_HZ;
+ return HPS_CLK_OSC2_HZ;
else
return 0;
}
const unsigned int cm_get_f2s_per_ref_clk_hz(void)
{
- return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+ return HPS_CLK_F2S_PER_REF_HZ;
}
const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
{
- return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+ return HPS_CLK_F2S_SDR_REF_HZ;
}
diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c
index 4ea32e72c7c9..0190112eac0b 100644
--- a/arch/arm/mach-socfpga/wrap_sdram_config.c
+++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
@@ -12,180 +12,180 @@
static const struct socfpga_sdram_config sdram_config = {
.ctrl_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
+ (HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
+ (HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
+ (HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
+ (HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
+ (HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
+ (HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
+ (HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
+ (HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
+ (HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
.dram_timing1 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
.dram_timing2 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
.dram_timing3 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
.dram_timing4 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
+ (HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
.lowpwr_timing =
- (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
+ (HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
+ (HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
.dram_odt =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
+ (HPS_SDR_CTRLCFG_DRAMODT_READ <<
SDR_CTRLGRP_DRAMODT_READ_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
+ (HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
SDR_CTRLGRP_DRAMODT_WRITE_LSB),
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
+#if (HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
.extratime1 =
- (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
+ (HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
+ (HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
+ (HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
#endif
.dram_addrw =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
+ (HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
+ (HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
+ (HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
- ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
+ ((HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
.dram_if_width =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
+ (HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
.dram_dev_width =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
+ (HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
.dram_intr =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
+ (HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
.lowpwr_eq =
- (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
+ (HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
.static_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
+ (HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
+ (HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
.ctrl_width =
- (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
+ (HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
.cport_width =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
+ (HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
.cport_wmap =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
+ (HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
.cport_rmap =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
+ (HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
.rfifo_cmap =
- (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
+ (HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
.wfifo_cmap =
- (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
+ (HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
.cport_rdwr =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
+ (HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
.port_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
+ (HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
- .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
+ .fpgaport_rst = HPS_SDR_CTRLCFG_FPGAPORTRST,
.fifo_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
+ (HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
+ (HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
.mp_priority =
- (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
+ (HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
.mp_weight0 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
+ (HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
.mp_weight1 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
+ (HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
+ (HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
.mp_weight2 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
+ (HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
.mp_weight3 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
+ (HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
.mp_pacing0 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
+ (HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
.mp_pacing1 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
+ (HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
+ (HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
.mp_pacing2 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
+ (HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
.mp_pacing3 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
+ (HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
.mp_threshold0 =
- (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
+ (HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
.mp_threshold1 =
- (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
+ (HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
.mp_threshold2 =
- (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
+ (HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
- .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
+ .phy_ctrl0 = HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
};
static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
@@ -202,7 +202,7 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
.guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3,
.idle_loop1 = RW_MGR_IDLE_LOOP1,
.idle_loop2 = RW_MGR_IDLE_LOOP2,
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
+#if (HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
.emr = RW_MGR_EMR,
.emr2 = RW_MGR_EMR2,
.emr3 = RW_MGR_EMR3,
@@ -213,7 +213,7 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
.mr_user = RW_MGR_MR_USER,
.mr_dll_reset = RW_MGR_MR_DLL_RESET,
.emr_ocd_enable = RW_MGR_EMR_OCD_ENABLE,
-#elif (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
+#elif (HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
.activate_1 = RW_MGR_ACTIVATE_1,
.idle = RW_MGR_IDLE,
.init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
@@ -287,7 +287,7 @@ static const struct socfpga_sdram_io_config io_config = {
};
static const struct socfpga_sdram_misc_config misc_config = {
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
+#if (HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
.afi_clk_freq = AFI_CLK_FREQ,
#endif
.afi_rate_ratio = AFI_RATE_RATIO,
diff --git a/board/altera/arria5-socdk/qts/iocsr_config.h b/board/altera/arria5-socdk/qts/iocsr_config.h
index 69a92de6361b..3823d1a97b87 100644
--- a/board/altera/arria5-socdk/qts/iocsr_config.h
+++ b/board/altera/arria5-socdk/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define HPS_IOCSR_SCANCHAIN0_LENGTH 1337
+#define HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define HPS_IOCSR_SCANCHAIN2_LENGTH 1528
+#define HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/altera/arria5-socdk/qts/pll_config.h b/board/altera/arria5-socdk/qts/pll_config.h
index 6c8325434440..f9d67b9d1e19 100644
--- a/board/altera/arria5-socdk/qts/pll_config.h
+++ b/board/altera/arria5-socdk/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 41
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define HPS_MAINPLLGRP_VCO_DENOM 0
+#define HPS_MAINPLLGRP_VCO_NUMER 41
+#define HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINQSPICLK_CNT 2
+#define HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0
+#define HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8
+#define HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define HPS_PERPLLGRP_VCO_DENOM 1
+#define HPS_PERPLLGRP_VCO_NUMER 79
+#define HPS_PERPLLGRP_VCO_PSRC 0
+#define HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define HPS_PERPLLGRP_PERQSPICLK_CNT 1
+#define HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define HPS_PERPLLGRP_S2FUSER1CLK_CNT 9
+#define HPS_PERPLLGRP_DIV_USBCLK 0
+#define HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define HPS_PERPLLGRP_SRC_SDMMC 2
+#define HPS_PERPLLGRP_SRC_NAND 2
+#define HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 127
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define HPS_SDRPLLGRP_VCO_DENOM 2
+#define HPS_SDRPLLGRP_VCO_NUMER 127
+#define HPS_SDRPLLGRP_VCO_SSRC 0
+#define HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1050000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 1066000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 350000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 100000000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define HPS_CLK_OSC1_HZ 25000000
+#define HPS_CLK_OSC2_HZ 25000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1050000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_SDRVCO_HZ 1066000000
+#define HPS_CLK_EMAC0_HZ 250000000
+#define HPS_CLK_EMAC1_HZ 250000000
+#define HPS_CLK_USBCLK_HZ 200000000
+#define HPS_CLK_NAND_HZ 50000000
+#define HPS_CLK_SDMMC_HZ 200000000
+#define HPS_CLK_QSPI_HZ 350000000
+#define HPS_CLK_SPIM_HZ 200000000
+#define HPS_CLK_CAN0_HZ 100000000
+#define HPS_CLK_CAN1_HZ 100000000
+#define HPS_CLK_GPIODB_HZ 32000
+#define HPS_CLK_L4_MP_HZ 100000000
+#define HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 0
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 2
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define HPS_ALTERAGRP_MPUCLK 0
+#define HPS_ALTERAGRP_MAINCLK 2
+#define HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/altera/arria5-socdk/qts/sdram_config.h b/board/altera/arria5-socdk/qts/sdram_config.h
index 927a7a4f8e04..341f92546704 100644
--- a/board/altera/arria5-socdk/qts/sdram_config.h
+++ b/board/altera/arria5-socdk/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
+#define HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define HPS_SDR_CTRLCFG_FPGAPORTRST 0
+#define HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/altera/cyclone5-socdk/qts/iocsr_config.h b/board/altera/cyclone5-socdk/qts/iocsr_config.h
index 81c507b842bc..c5cc495a90de 100644
--- a/board/altera/cyclone5-socdk/qts/iocsr_config.h
+++ b/board/altera/cyclone5-socdk/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
index ae5cfab0cf70..820ce9924813 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define HPS_MAINPLLGRP_VCO_DENOM 0
+#define HPS_MAINPLLGRP_VCO_NUMER 73
+#define HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
+#define HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define HPS_PERPLLGRP_VCO_DENOM 0
+#define HPS_PERPLLGRP_VCO_NUMER 39
+#define HPS_PERPLLGRP_VCO_PSRC 0
+#define HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define HPS_PERPLLGRP_DIV_USBCLK 0
+#define HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define HPS_PERPLLGRP_SRC_SDMMC 2
+#define HPS_PERPLLGRP_SRC_NAND 2
+#define HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define HPS_SDRPLLGRP_VCO_DENOM 0
+#define HPS_SDRPLLGRP_VCO_NUMER 31
+#define HPS_SDRPLLGRP_VCO_SSRC 0
+#define HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 370000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define HPS_CLK_OSC1_HZ 25000000
+#define HPS_CLK_OSC2_HZ 25000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1850000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_SDRVCO_HZ 800000000
+#define HPS_CLK_EMAC0_HZ 1953125
+#define HPS_CLK_EMAC1_HZ 250000000
+#define HPS_CLK_USBCLK_HZ 200000000
+#define HPS_CLK_NAND_HZ 50000000
+#define HPS_CLK_SDMMC_HZ 200000000
+#define HPS_CLK_QSPI_HZ 370000000
+#define HPS_CLK_SPIM_HZ 200000000
+#define HPS_CLK_CAN0_HZ 100000000
+#define HPS_CLK_CAN1_HZ 12500000
+#define HPS_CLK_GPIODB_HZ 32000
+#define HPS_CLK_L4_MP_HZ 100000000
+#define HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define HPS_ALTERAGRP_MPUCLK 1
+#define HPS_ALTERAGRP_MAINCLK 4
+#define HPS_ALTERAGRP_DBGATCLK 4
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h b/board/altera/cyclone5-socdk/qts/sdram_config.h
index 8adbfec11f95..1e0b2459238b 100644
--- a/board/altera/cyclone5-socdk/qts/sdram_config.h
+++ b/board/altera/cyclone5-socdk/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
+#define HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define HPS_SDR_CTRLCFG_FPGAPORTRST 0
+#define HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/aries/mcvevk/qts/iocsr_config.h b/board/aries/mcvevk/qts/iocsr_config.h
index e233d02b97db..b2908f1b7e52 100644
--- a/board/aries/mcvevk/qts/iocsr_config.h
+++ b/board/aries/mcvevk/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/aries/mcvevk/qts/pll_config.h b/board/aries/mcvevk/qts/pll_config.h
index 4fa868e458f0..670dca050408 100644
--- a/board/aries/mcvevk/qts/pll_config.h
+++ b/board/aries/mcvevk/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define HPS_MAINPLLGRP_VCO_DENOM 0
+#define HPS_MAINPLLGRP_VCO_NUMER 63
+#define HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define HPS_PERPLLGRP_VCO_DENOM 0
+#define HPS_PERPLLGRP_VCO_NUMER 39
+#define HPS_PERPLLGRP_VCO_PSRC 0
+#define HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define HPS_PERPLLGRP_DIV_USBCLK 0
+#define HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define HPS_PERPLLGRP_SRC_SDMMC 2
+#define HPS_PERPLLGRP_SRC_NAND 2
+#define HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define HPS_SDRPLLGRP_VCO_DENOM 0
+#define HPS_SDRPLLGRP_VCO_NUMER 31
+#define HPS_SDRPLLGRP_VCO_SSRC 0
+#define HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 3125000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 100000000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define HPS_CLK_OSC1_HZ 25000000
+#define HPS_CLK_OSC2_HZ 25000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1600000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_SDRVCO_HZ 800000000
+#define HPS_CLK_EMAC0_HZ 250000000
+#define HPS_CLK_EMAC1_HZ 1953125
+#define HPS_CLK_USBCLK_HZ 200000000
+#define HPS_CLK_NAND_HZ 50000000
+#define HPS_CLK_SDMMC_HZ 200000000
+#define HPS_CLK_QSPI_HZ 3125000
+#define HPS_CLK_SPIM_HZ 200000000
+#define HPS_CLK_CAN0_HZ 100000000
+#define HPS_CLK_CAN1_HZ 100000000
+#define HPS_CLK_GPIODB_HZ 32000
+#define HPS_CLK_L4_MP_HZ 100000000
+#define HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define HPS_ALTERAGRP_MPUCLK 1
+#define HPS_ALTERAGRP_MAINCLK 3
+#define HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/aries/mcvevk/qts/sdram_config.h b/board/aries/mcvevk/qts/sdram_config.h
index fd72926a89e3..966a60bf88c9 100644
--- a/board/aries/mcvevk/qts/sdram_config.h
+++ b/board/aries/mcvevk/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/devboards/dbm-soc1/qts/iocsr_config.h b/board/devboards/dbm-soc1/qts/iocsr_config.h
index 99ed62bb503e..84432ccf5bf3 100644
--- a/board/devboards/dbm-soc1/qts/iocsr_config.h
+++ b/board/devboards/dbm-soc1/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/devboards/dbm-soc1/qts/pll_config.h b/board/devboards/dbm-soc1/qts/pll_config.h
index f6ffa08654ad..fae9dd076ed3 100644
--- a/board/devboards/dbm-soc1/qts/pll_config.h
+++ b/board/devboards/dbm-soc1/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define HPS_MAINPLLGRP_VCO_DENOM 0
+#define HPS_MAINPLLGRP_VCO_NUMER 63
+#define HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define HPS_PERPLLGRP_VCO_DENOM 0
+#define HPS_PERPLLGRP_VCO_NUMER 39
+#define HPS_PERPLLGRP_VCO_PSRC 0
+#define HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define HPS_PERPLLGRP_DIV_USBCLK 0
+#define HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define HPS_PERPLLGRP_SRC_SDMMC 2
+#define HPS_PERPLLGRP_SRC_NAND 2
+#define HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define HPS_SDRPLLGRP_VCO_DENOM 0
+#define HPS_SDRPLLGRP_VCO_NUMER 31
+#define HPS_SDRPLLGRP_VCO_SSRC 0
+#define HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define HPS_CLK_OSC1_HZ 25000000
+#define HPS_CLK_OSC2_HZ 25000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1600000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_SDRVCO_HZ 800000000
+#define HPS_CLK_EMAC0_HZ 1953125
+#define HPS_CLK_EMAC1_HZ 250000000
+#define HPS_CLK_USBCLK_HZ 200000000
+#define HPS_CLK_NAND_HZ 50000000
+#define HPS_CLK_SDMMC_HZ 200000000
+#define HPS_CLK_QSPI_HZ 400000000
+#define HPS_CLK_SPIM_HZ 200000000
+#define HPS_CLK_CAN0_HZ 12500000
+#define HPS_CLK_CAN1_HZ 12500000
+#define HPS_CLK_GPIODB_HZ 32000
+#define HPS_CLK_L4_MP_HZ 100000000
+#define HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define HPS_ALTERAGRP_MPUCLK 1
+#define HPS_ALTERAGRP_MAINCLK 3
+#define HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/devboards/dbm-soc1/qts/sdram_config.h b/board/devboards/dbm-soc1/qts/sdram_config.h
index 2022969bed9b..0a801460c0b0 100644
--- a/board/devboards/dbm-soc1/qts/sdram_config.h
+++ b/board/devboards/dbm-soc1/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/ebv/socrates/qts/iocsr_config.h b/board/ebv/socrates/qts/iocsr_config.h
index 18b9c6ce4dfc..fe14ff2c28f5 100644
--- a/board/ebv/socrates/qts/iocsr_config.h
+++ b/board/ebv/socrates/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/ebv/socrates/qts/pll_config.h b/board/ebv/socrates/qts/pll_config.h
index 71d3674758fc..67c8f6162a85 100644
--- a/board/ebv/socrates/qts/pll_config.h
+++ b/board/ebv/socrates/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define HPS_MAINPLLGRP_VCO_DENOM 0
+#define HPS_MAINPLLGRP_VCO_NUMER 63
+#define HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define HPS_PERPLLGRP_VCO_DENOM 0
+#define HPS_PERPLLGRP_VCO_NUMER 39
+#define HPS_PERPLLGRP_VCO_PSRC 0
+#define HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define HPS_PERPLLGRP_DIV_USBCLK 0
+#define HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define HPS_PERPLLGRP_SRC_SDMMC 2
+#define HPS_PERPLLGRP_SRC_NAND 2
+#define HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define HPS_SDRPLLGRP_VCO_DENOM 2
+#define HPS_SDRPLLGRP_VCO_NUMER 79
+#define HPS_SDRPLLGRP_VCO_SSRC 0
+#define HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define HPS_CLK_OSC1_HZ 25000000
+#define HPS_CLK_OSC2_HZ 25000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1600000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_SDRVCO_HZ 666666666
+#define HPS_CLK_EMAC0_HZ 1953125
+#define HPS_CLK_EMAC1_HZ 250000000
+#define HPS_CLK_USBCLK_HZ 200000000
+#define HPS_CLK_NAND_HZ 50000000
+#define HPS_CLK_SDMMC_HZ 200000000
+#define HPS_CLK_QSPI_HZ 400000000
+#define HPS_CLK_SPIM_HZ 200000000
+#define HPS_CLK_CAN0_HZ 100000000
+#define HPS_CLK_CAN1_HZ 12500000
+#define HPS_CLK_GPIODB_HZ 32000
+#define HPS_CLK_L4_MP_HZ 100000000
+#define HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define HPS_ALTERAGRP_MPUCLK 1
+#define HPS_ALTERAGRP_MAINCLK 3
+#define HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/ebv/socrates/qts/sdram_config.h b/board/ebv/socrates/qts/sdram_config.h
index 2f8465bf77ca..77b514a13c37 100644
--- a/board/ebv/socrates/qts/sdram_config.h
+++ b/board/ebv/socrates/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/is1/qts/iocsr_config.h b/board/is1/qts/iocsr_config.h
index 1d2774aa41a7..c1a85b7e65cf 100644
--- a/board/is1/qts/iocsr_config.h
+++ b/board/is1/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/is1/qts/pll_config.h b/board/is1/qts/pll_config.h
index 218ab35c0424..b6f3f3e002b2 100644
--- a/board/is1/qts/pll_config.h
+++ b/board/is1/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 59
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define HPS_MAINPLLGRP_VCO_DENOM 0
+#define HPS_MAINPLLGRP_VCO_NUMER 59
+#define HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
+#define HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define HPS_PERPLLGRP_VCO_DENOM 0
+#define HPS_PERPLLGRP_VCO_NUMER 39
+#define HPS_PERPLLGRP_VCO_PSRC 0
+#define HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
+#define HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define HPS_PERPLLGRP_S2FUSER1CLK_CNT 39
+#define HPS_PERPLLGRP_DIV_USBCLK 0
+#define HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define HPS_PERPLLGRP_SRC_SDMMC 2
+#define HPS_PERPLLGRP_SRC_NAND 2
+#define HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define HPS_SDRPLLGRP_VCO_DENOM 0
+#define HPS_SDRPLLGRP_VCO_NUMER 31
+#define HPS_SDRPLLGRP_VCO_SSRC 0
+#define HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1500000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 488281
-#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
-#define CONFIG_HPS_CLK_QSPI_HZ 375000000
-#define CONFIG_HPS_CLK_SPIM_HZ 12500000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define HPS_CLK_OSC1_HZ 25000000
+#define HPS_CLK_OSC2_HZ 25000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1500000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_SDRVCO_HZ 800000000
+#define HPS_CLK_EMAC0_HZ 250000000
+#define HPS_CLK_EMAC1_HZ 250000000
+#define HPS_CLK_USBCLK_HZ 200000000
+#define HPS_CLK_NAND_HZ 488281
+#define HPS_CLK_SDMMC_HZ 1953125
+#define HPS_CLK_QSPI_HZ 375000000
+#define HPS_CLK_SPIM_HZ 12500000
+#define HPS_CLK_CAN0_HZ 12500000
+#define HPS_CLK_CAN1_HZ 12500000
+#define HPS_CLK_GPIODB_HZ 32000
+#define HPS_CLK_L4_MP_HZ 100000000
+#define HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define HPS_ALTERAGRP_MPUCLK 1
+#define HPS_ALTERAGRP_MAINCLK 4
+#define HPS_ALTERAGRP_DBGATCLK 4
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h
index 2573171abeb1..877e32adff67 100644
--- a/board/is1/qts/sdram_config.h
+++ b/board/is1/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 64
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 1
+#define HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
+#define HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 16
+#define HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 64
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define HPS_SDR_CTRLCFG_FPGAPORTRST 0x777
+#define HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/keymile/secu1/qts/iocsr_config.h b/board/keymile/secu1/qts/iocsr_config.h
index 7640c56db166..bb87defc4add 100644
--- a/board/keymile/secu1/qts/iocsr_config.h
+++ b/board/keymile/secu1/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define HPS_IOCSR_SCANCHAIN0_LENGTH 1337
+#define HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define HPS_IOCSR_SCANCHAIN2_LENGTH 1528
+#define HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00100000,
diff --git a/board/keymile/secu1/qts/pll_config.h b/board/keymile/secu1/qts/pll_config.h
index f0c31860ca4b..ad56f6c1b903 100644
--- a/board/keymile/secu1/qts/pll_config.h
+++ b/board/keymile/secu1/qts/pll_config.h
@@ -6,78 +6,78 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define HPS_MAINPLLGRP_VCO_DENOM 0
+#define HPS_MAINPLLGRP_VCO_NUMER 39
+#define HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 24
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 1
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define HPS_PERPLLGRP_VCO_DENOM 0
+#define HPS_PERPLLGRP_VCO_NUMER 24
+#define HPS_PERPLLGRP_VCO_PSRC 0
+#define HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7
+#define HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define HPS_PERPLLGRP_DIV_USBCLK 4
+#define HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define HPS_PERPLLGRP_SRC_SDMMC 1
+#define HPS_PERPLLGRP_SRC_NAND 2
+#define HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 14
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define HPS_SDRPLLGRP_VCO_DENOM 0
+#define HPS_SDRPLLGRP_VCO_NUMER 14
+#define HPS_SDRPLLGRP_VCO_SSRC 0
+#define HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
+#define HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 40000000
-#define CONFIG_HPS_CLK_OSC2_HZ 40000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 600000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
-#define CONFIG_HPS_CLK_USBCLK_HZ 12500000
-#define CONFIG_HPS_CLK_NAND_HZ 31250000
-#define CONFIG_HPS_CLK_SDMMC_HZ 3125000
-#define CONFIG_HPS_CLK_QSPI_HZ 3125000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define HPS_CLK_OSC1_HZ 40000000
+#define HPS_CLK_OSC2_HZ 40000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1600000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_SDRVCO_HZ 600000000
+#define HPS_CLK_EMAC0_HZ 250000000
+#define HPS_CLK_EMAC1_HZ 1953125
+#define HPS_CLK_USBCLK_HZ 12500000
+#define HPS_CLK_NAND_HZ 31250000
+#define HPS_CLK_SDMMC_HZ 3125000
+#define HPS_CLK_QSPI_HZ 3125000
+#define HPS_CLK_SPIM_HZ 200000000
+#define HPS_CLK_CAN0_HZ 12500000
+#define HPS_CLK_CAN1_HZ 12500000
+#define HPS_CLK_GPIODB_HZ 32000
+#define HPS_CLK_L4_MP_HZ 100000000
+#define HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define HPS_ALTERAGRP_MPUCLK 1
+#define HPS_ALTERAGRP_MAINCLK 3
+#define HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/keymile/secu1/qts/sdram_config.h b/board/keymile/secu1/qts/sdram_config.h
index b0ff86ef3814..9800f7fb2e8d 100644
--- a/board/keymile/secu1/qts/sdram_config.h
+++ b/board/keymile/secu1/qts/sdram_config.h
@@ -8,76 +8,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
+#define HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3
+#define HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
+#define HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x11
diff --git a/board/softing/vining_fpga/qts/iocsr_config.h b/board/softing/vining_fpga/qts/iocsr_config.h
index 8c78aecdd3de..63f96f1d2bd2 100644
--- a/board/softing/vining_fpga/qts/iocsr_config.h
+++ b/board/softing/vining_fpga/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/softing/vining_fpga/qts/pll_config.h b/board/softing/vining_fpga/qts/pll_config.h
index fa0461833694..b9934dd12cc7 100644
--- a/board/softing/vining_fpga/qts/pll_config.h
+++ b/board/softing/vining_fpga/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define HPS_MAINPLLGRP_VCO_DENOM 0
+#define HPS_MAINPLLGRP_VCO_NUMER 63
+#define HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define HPS_PERPLLGRP_VCO_DENOM 0
+#define HPS_PERPLLGRP_VCO_NUMER 39
+#define HPS_PERPLLGRP_VCO_PSRC 0
+#define HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
+#define HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define HPS_PERPLLGRP_DIV_USBCLK 0
+#define HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define HPS_PERPLLGRP_SRC_SDMMC 2
+#define HPS_PERPLLGRP_SRC_NAND 2
+#define HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define HPS_SDRPLLGRP_VCO_DENOM 0
+#define HPS_SDRPLLGRP_VCO_NUMER 31
+#define HPS_SDRPLLGRP_VCO_SSRC 0
+#define HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
+#define HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 488281
-#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
-#define CONFIG_HPS_CLK_QSPI_HZ 320000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define HPS_CLK_OSC1_HZ 25000000
+#define HPS_CLK_OSC2_HZ 25000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1600000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_SDRVCO_HZ 800000000
+#define HPS_CLK_EMAC0_HZ 250000000
+#define HPS_CLK_EMAC1_HZ 250000000
+#define HPS_CLK_USBCLK_HZ 200000000
+#define HPS_CLK_NAND_HZ 488281
+#define HPS_CLK_SDMMC_HZ 1953125
+#define HPS_CLK_QSPI_HZ 320000000
+#define HPS_CLK_SPIM_HZ 200000000
+#define HPS_CLK_CAN0_HZ 12500000
+#define HPS_CLK_CAN1_HZ 12500000
+#define HPS_CLK_GPIODB_HZ 32000
+#define HPS_CLK_L4_MP_HZ 100000000
+#define HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define HPS_ALTERAGRP_MPUCLK 1
+#define HPS_ALTERAGRP_MAINCLK 3
+#define HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/softing/vining_fpga/qts/sdram_config.h b/board/softing/vining_fpga/qts/sdram_config.h
index ec067eb473d1..37b09a45016d 100644
--- a/board/softing/vining_fpga/qts/sdram_config.h
+++ b/board/softing/vining_fpga/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
+#define HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/sr1500/qts/iocsr_config.h b/board/sr1500/qts/iocsr_config.h
index b3b167fa7fc0..17cdec6fb6ab 100644
--- a/board/sr1500/qts/iocsr_config.h
+++ b/board/sr1500/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00100000,
diff --git a/board/sr1500/qts/pll_config.h b/board/sr1500/qts/pll_config.h
index 02f068f74244..e086434bf0e4 100644
--- a/board/sr1500/qts/pll_config.h
+++ b/board/sr1500/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define HPS_MAINPLLGRP_VCO_DENOM 0
+#define HPS_MAINPLLGRP_VCO_NUMER 63
+#define HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define HPS_PERPLLGRP_VCO_DENOM 0
+#define HPS_PERPLLGRP_VCO_NUMER 39
+#define HPS_PERPLLGRP_VCO_PSRC 0
+#define HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define HPS_PERPLLGRP_DIV_USBCLK 0
+#define HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define HPS_PERPLLGRP_SRC_SDMMC 2
+#define HPS_PERPLLGRP_SRC_NAND 2
+#define HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define HPS_SDRPLLGRP_VCO_DENOM 0
+#define HPS_SDRPLLGRP_VCO_NUMER 31
+#define HPS_SDRPLLGRP_VCO_SSRC 0
+#define HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 12500000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define HPS_CLK_OSC1_HZ 25000000
+#define HPS_CLK_OSC2_HZ 25000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1600000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_SDRVCO_HZ 800000000
+#define HPS_CLK_EMAC0_HZ 1953125
+#define HPS_CLK_EMAC1_HZ 250000000
+#define HPS_CLK_USBCLK_HZ 200000000
+#define HPS_CLK_NAND_HZ 50000000
+#define HPS_CLK_SDMMC_HZ 200000000
+#define HPS_CLK_QSPI_HZ 400000000
+#define HPS_CLK_SPIM_HZ 12500000
+#define HPS_CLK_CAN0_HZ 12500000
+#define HPS_CLK_CAN1_HZ 12500000
+#define HPS_CLK_GPIODB_HZ 32000
+#define HPS_CLK_L4_MP_HZ 100000000
+#define HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define HPS_ALTERAGRP_MPUCLK 1
+#define HPS_ALTERAGRP_MAINCLK 3
+#define HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h
index d25354bb49cd..e67ca284a29e 100644
--- a/board/sr1500/qts/sdram_config.h
+++ b/board/sr1500/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define HPS_SDR_CTRLCFG_FPGAPORTRST 0x330
+#define HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/terasic/de0-nano-soc/qts/iocsr_config.h b/board/terasic/de0-nano-soc/qts/iocsr_config.h
index 6ff5bd57112a..ad2ddcc12407 100644
--- a/board/terasic/de0-nano-soc/qts/iocsr_config.h
+++ b/board/terasic/de0-nano-soc/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/terasic/de0-nano-soc/qts/pll_config.h b/board/terasic/de0-nano-soc/qts/pll_config.h
index 68dc3bc27984..87713852505e 100644
--- a/board/terasic/de0-nano-soc/qts/pll_config.h
+++ b/board/terasic/de0-nano-soc/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef _PRELOADER_PLL_CONFIG_H_
#define _PRELOADER_PLL_CONFIG_H_
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define HPS_MAINPLLGRP_VCO_DENOM 0
+#define HPS_MAINPLLGRP_VCO_NUMER 73
+#define HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18
+#define HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define HPS_PERPLLGRP_VCO_DENOM 0
+#define HPS_PERPLLGRP_VCO_NUMER 39
+#define HPS_PERPLLGRP_VCO_PSRC 0
+#define HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
+#define HPS_PERPLLGRP_DIV_USBCLK 0
+#define HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define HPS_PERPLLGRP_SRC_SDMMC 2
+#define HPS_PERPLLGRP_SRC_NAND 2
+#define HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define HPS_SDRPLLGRP_VCO_DENOM 0
+#define HPS_SDRPLLGRP_VCO_NUMER 31
+#define HPS_SDRPLLGRP_VCO_SSRC 0
+#define HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 3613281
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define HPS_CLK_OSC1_HZ 25000000
+#define HPS_CLK_OSC2_HZ 25000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1850000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_SDRVCO_HZ 800000000
+#define HPS_CLK_EMAC0_HZ 1953125
+#define HPS_CLK_EMAC1_HZ 250000000
+#define HPS_CLK_USBCLK_HZ 200000000
+#define HPS_CLK_NAND_HZ 50000000
+#define HPS_CLK_SDMMC_HZ 200000000
+#define HPS_CLK_QSPI_HZ 3613281
+#define HPS_CLK_SPIM_HZ 200000000
+#define HPS_CLK_CAN0_HZ 12500000
+#define HPS_CLK_CAN1_HZ 12500000
+#define HPS_CLK_GPIODB_HZ 32000
+#define HPS_CLK_L4_MP_HZ 100000000
+#define HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define HPS_ALTERAGRP_MPUCLK 1
+#define HPS_ALTERAGRP_MAINCLK 4
+#define HPS_ALTERAGRP_DBGATCLK 4
#endif /* _PRELOADER_PLL_CONFIG_H_ */
diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h b/board/terasic/de0-nano-soc/qts/sdram_config.h
index 0504dd688f9b..c9ac07789ad0 100644
--- a/board/terasic/de0-nano-soc/qts/sdram_config.h
+++ b/board/terasic/de0-nano-soc/qts/sdram_config.h
@@ -5,80 +5,80 @@
#ifndef __SDRAM_CONFIG_H
#define __SDRAM_CONFIG_H
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0x1
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0x1
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0x3
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x311
+#define HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0x1
+#define HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0x1
+#define HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0x3
+#define HPS_SDR_CTRLCFG_FPGAPORTRST 0x311
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/terasic/de1-soc/qts/iocsr_config.h b/board/terasic/de1-soc/qts/iocsr_config.h
index c65183ed8c08..25a53dc75b0f 100644
--- a/board/terasic/de1-soc/qts/iocsr_config.h
+++ b/board/terasic/de1-soc/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/terasic/de1-soc/qts/pll_config.h b/board/terasic/de1-soc/qts/pll_config.h
index 4544f926935a..8f21e4600269 100644
--- a/board/terasic/de1-soc/qts/pll_config.h
+++ b/board/terasic/de1-soc/qts/pll_config.h
@@ -6,85 +6,85 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define HPS_MAINPLLGRP_VCO_DENOM 0
+#define HPS_MAINPLLGRP_VCO_NUMER 63
+#define HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define HPS_PERPLLGRP_VCO_DENOM 0
+#define HPS_PERPLLGRP_VCO_NUMER 39
+#define HPS_PERPLLGRP_VCO_PSRC 0
+#define HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define HPS_PERPLLGRP_DIV_USBCLK 0
+#define HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define HPS_PERPLLGRP_SRC_SDMMC 2
+#define HPS_PERPLLGRP_SRC_NAND 2
+#define HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define HPS_SDRPLLGRP_VCO_DENOM 0
+#define HPS_SDRPLLGRP_VCO_NUMER 31
+#define HPS_SDRPLLGRP_VCO_SSRC 0
+#define HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define HPS_CLK_OSC1_HZ 25000000
+#define HPS_CLK_OSC2_HZ 25000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1600000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_SDRVCO_HZ 800000000
+#define HPS_CLK_OSC1_HZ 25000000
+#define HPS_CLK_OSC2_HZ 25000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1600000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_EMAC0_HZ 1953125
+#define HPS_CLK_EMAC1_HZ 250000000
+#define HPS_CLK_USBCLK_HZ 200000000
+#define HPS_CLK_NAND_HZ 50000000
+#define HPS_CLK_SDMMC_HZ 200000000
+#define HPS_CLK_QSPI_HZ 400000000
+#define HPS_CLK_SPIM_HZ 200000000
+#define HPS_CLK_CAN0_HZ 12500000
+#define HPS_CLK_CAN1_HZ 12500000
+#define HPS_CLK_GPIODB_HZ 32000
+#define HPS_CLK_L4_MP_HZ 100000000
+#define HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define HPS_ALTERAGRP_MPUCLK 1
+#define HPS_ALTERAGRP_MAINCLK 3
+#define HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/de1-soc/qts/sdram_config.h b/board/terasic/de1-soc/qts/sdram_config.h
index c60426f2ff66..19b3d14e370c 100644
--- a/board/terasic/de1-soc/qts/sdram_config.h
+++ b/board/terasic/de1-soc/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 15
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
+#define HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/terasic/de10-nano/qts/iocsr_config.h b/board/terasic/de10-nano/qts/iocsr_config.h
index bc5b7a07c7d6..7f2c78ad63b2 100644
--- a/board/terasic/de10-nano/qts/iocsr_config.h
+++ b/board/terasic/de10-nano/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/terasic/de10-nano/qts/pll_config.h b/board/terasic/de10-nano/qts/pll_config.h
index 854936b2a33a..b534242bb36c 100644
--- a/board/terasic/de10-nano/qts/pll_config.h
+++ b/board/terasic/de10-nano/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define HPS_MAINPLLGRP_VCO_DENOM 0
+#define HPS_MAINPLLGRP_VCO_NUMER 63
+#define HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define HPS_PERPLLGRP_VCO_DENOM 0
+#define HPS_PERPLLGRP_VCO_NUMER 39
+#define HPS_PERPLLGRP_VCO_PSRC 0
+#define HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
+#define HPS_PERPLLGRP_DIV_USBCLK 0
+#define HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define HPS_PERPLLGRP_SRC_SDMMC 2
+#define HPS_PERPLLGRP_SRC_NAND 2
+#define HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define HPS_SDRPLLGRP_VCO_DENOM 0
+#define HPS_SDRPLLGRP_VCO_NUMER 31
+#define HPS_SDRPLLGRP_VCO_SSRC 0
+#define HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 3125000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define HPS_CLK_OSC1_HZ 25000000
+#define HPS_CLK_OSC2_HZ 25000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1600000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_SDRVCO_HZ 800000000
+#define HPS_CLK_EMAC0_HZ 1953125
+#define HPS_CLK_EMAC1_HZ 250000000
+#define HPS_CLK_USBCLK_HZ 200000000
+#define HPS_CLK_NAND_HZ 50000000
+#define HPS_CLK_SDMMC_HZ 200000000
+#define HPS_CLK_QSPI_HZ 3125000
+#define HPS_CLK_SPIM_HZ 200000000
+#define HPS_CLK_CAN0_HZ 12500000
+#define HPS_CLK_CAN1_HZ 12500000
+#define HPS_CLK_GPIODB_HZ 32000
+#define HPS_CLK_L4_MP_HZ 100000000
+#define HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define HPS_ALTERAGRP_MPUCLK 1
+#define HPS_ALTERAGRP_MAINCLK 3
+#define HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/de10-nano/qts/sdram_config.h b/board/terasic/de10-nano/qts/sdram_config.h
index 26910ef348b7..0b2bda6ea575 100644
--- a/board/terasic/de10-nano/qts/sdram_config.h
+++ b/board/terasic/de10-nano/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
+#define HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
+#define HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
+#define HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/terasic/sockit/qts/iocsr_config.h b/board/terasic/sockit/qts/iocsr_config.h
index b8cb5f08ab69..b57fdbc9b259 100644
--- a/board/terasic/sockit/qts/iocsr_config.h
+++ b/board/terasic/sockit/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/terasic/sockit/qts/pll_config.h b/board/terasic/sockit/qts/pll_config.h
index f6ffa08654ad..fae9dd076ed3 100644
--- a/board/terasic/sockit/qts/pll_config.h
+++ b/board/terasic/sockit/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define HPS_MAINPLLGRP_VCO_DENOM 0
+#define HPS_MAINPLLGRP_VCO_NUMER 63
+#define HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define HPS_PERPLLGRP_VCO_DENOM 0
+#define HPS_PERPLLGRP_VCO_NUMER 39
+#define HPS_PERPLLGRP_VCO_PSRC 0
+#define HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define HPS_PERPLLGRP_DIV_USBCLK 0
+#define HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define HPS_PERPLLGRP_SRC_SDMMC 2
+#define HPS_PERPLLGRP_SRC_NAND 2
+#define HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define HPS_SDRPLLGRP_VCO_DENOM 0
+#define HPS_SDRPLLGRP_VCO_NUMER 31
+#define HPS_SDRPLLGRP_VCO_SSRC 0
+#define HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define HPS_CLK_OSC1_HZ 25000000
+#define HPS_CLK_OSC2_HZ 25000000
+#define HPS_CLK_F2S_SDR_REF_HZ 0
+#define HPS_CLK_F2S_PER_REF_HZ 0
+#define HPS_CLK_MAINVCO_HZ 1600000000
+#define HPS_CLK_PERVCO_HZ 1000000000
+#define HPS_CLK_SDRVCO_HZ 800000000
+#define HPS_CLK_EMAC0_HZ 1953125
+#define HPS_CLK_EMAC1_HZ 250000000
+#define HPS_CLK_USBCLK_HZ 200000000
+#define HPS_CLK_NAND_HZ 50000000
+#define HPS_CLK_SDMMC_HZ 200000000
+#define HPS_CLK_QSPI_HZ 400000000
+#define HPS_CLK_SPIM_HZ 200000000
+#define HPS_CLK_CAN0_HZ 12500000
+#define HPS_CLK_CAN1_HZ 12500000
+#define HPS_CLK_GPIODB_HZ 32000
+#define HPS_CLK_L4_MP_HZ 100000000
+#define HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define HPS_ALTERAGRP_MPUCLK 1
+#define HPS_ALTERAGRP_MAINCLK 3
+#define HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h
index 96cc35703413..e35e2dd76107 100644
--- a/board/terasic/sockit/qts/sdram_config.h
+++ b/board/terasic/sockit/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
+#define HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
+#define HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 2d70bf5da7c5..6791660fcf7f 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -557,148 +557,6 @@ CONFIG_HITACHI_SX14
CONFIG_HOSTNAME
CONFIG_HOST_MAX_DEVICES
CONFIG_HOTPLUG
-CONFIG_HPS_ALTERAGRP_DBGATCLK
-CONFIG_HPS_ALTERAGRP_MAINCLK
-CONFIG_HPS_ALTERAGRP_MPUCLK
-CONFIG_HPS_CLK_CAN0_HZ
-CONFIG_HPS_CLK_CAN1_HZ
-CONFIG_HPS_CLK_EMAC0_HZ
-CONFIG_HPS_CLK_EMAC1_HZ
-CONFIG_HPS_CLK_F2S_PER_REF_HZ
-CONFIG_HPS_CLK_F2S_SDR_REF_HZ
-CONFIG_HPS_CLK_GPIODB_HZ
-CONFIG_HPS_CLK_L4_MP_HZ
-CONFIG_HPS_CLK_L4_SP_HZ
-CONFIG_HPS_CLK_MAINVCO_HZ
-CONFIG_HPS_CLK_NAND_HZ
-CONFIG_HPS_CLK_OSC1_HZ
-CONFIG_HPS_CLK_OSC2_HZ
-CONFIG_HPS_CLK_PERVCO_HZ
-CONFIG_HPS_CLK_QSPI_HZ
-CONFIG_HPS_CLK_SDMMC_HZ
-CONFIG_HPS_CLK_SDRVCO_HZ
-CONFIG_HPS_CLK_SPIM_HZ
-CONFIG_HPS_CLK_USBCLK_HZ
-CONFIG_HPS_DBCTRL_STAYOSC1
-CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH
-CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH
-CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH
-CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
-CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT
-CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT
-CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK
-CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK
-CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP
-CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP
-CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT
-CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK
-CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK
-CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK
-CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK
-CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT
-CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT
-CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT
-CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK
-CONFIG_HPS_MAINPLLGRP_VCO_DENOM
-CONFIG_HPS_MAINPLLGRP_VCO_NUMER
-CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK
-CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK
-CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK
-CONFIG_HPS_PERPLLGRP_DIV_USBCLK
-CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT
-CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT
-CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK
-CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT
-CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT
-CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT
-CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT
-CONFIG_HPS_PERPLLGRP_SRC_NAND
-CONFIG_HPS_PERPLLGRP_SRC_QSPI
-CONFIG_HPS_PERPLLGRP_SRC_SDMMC
-CONFIG_HPS_PERPLLGRP_VCO_DENOM
-CONFIG_HPS_PERPLLGRP_VCO_NUMER
-CONFIG_HPS_PERPLLGRP_VCO_PSRC
-CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT
-CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE
-CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT
-CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE
-CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT
-CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE
-CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT
-CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE
-CONFIG_HPS_SDRPLLGRP_VCO_DENOM
-CONFIG_HPS_SDRPLLGRP_VCO_NUMER
-CONFIG_HPS_SDRPLLGRP_VCO_SSRC
-CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR
-CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP
-CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH
-CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT
-CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH
-CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS
-CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS
-CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS
-CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS
-CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH
-CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH
-CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN
-CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ
-CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
-CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC
-CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
-CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST
-CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED
-CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED
-CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED
-CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK
-CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES
-CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36
-CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY
-CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0
-CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32
-CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46
-CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0
-CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN
-CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP
-CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL
-CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA
-CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP
CONFIG_HSMMC2_8BIT
CONFIG_HUSH_INIT_VAR
CONFIG_HVBOOT
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/1] arm: socfpga: Migrate CONFIG_HPS namespace to HPS
2021-08-10 20:05 [PATCH 1/1] arm: socfpga: Migrate CONFIG_HPS namespace to HPS Tom Rini
@ 2021-08-10 20:11 ` Marek Vasut
2021-08-10 20:28 ` Tom Rini
2021-08-10 20:47 ` Tom Rini
0 siblings, 2 replies; 7+ messages in thread
From: Marek Vasut @ 2021-08-10 20:11 UTC (permalink / raw)
To: Tom Rini, u-boot; +Cc: Simon Goldschmidt, Tien Fong Chee
On 8/10/21 10:05 PM, Tom Rini wrote:
> None of the CONFIG_HPS namespace options are changed via the board
> config.h file, nor does it make sense to move them to Kconfig. Rename
> these options to the HPS namespace instead.
>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> Note, this patch is complete as the changes to the regex qts-filter.sh
> are such a long line that git send-email fails. This patch was
> generated by:
> $ git grep -l CONFIG_HPS_ | xargs sed -i -e 's/CONFIG_HPS_/HPS_/g'
> and I will re-run that before applying.
The problem is, it is the altera tools which generate all those CONFIG_*
symbols which are processed by the qts-filter.sh and placed into those
qts/ board directories, so this patch breaks all that. You'd have to fix
the qts-filter to scrub the CONFIG_ prefixes first.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/1] arm: socfpga: Migrate CONFIG_HPS namespace to HPS
2021-08-10 20:11 ` Marek Vasut
@ 2021-08-10 20:28 ` Tom Rini
2021-08-10 20:47 ` Tom Rini
1 sibling, 0 replies; 7+ messages in thread
From: Tom Rini @ 2021-08-10 20:28 UTC (permalink / raw)
To: Marek Vasut; +Cc: u-boot, Simon Goldschmidt, Tien Fong Chee
[-- Attachment #1: Type: text/plain, Size: 1178 bytes --]
On Tue, Aug 10, 2021 at 10:11:08PM +0200, Marek Vasut wrote:
> On 8/10/21 10:05 PM, Tom Rini wrote:
> > None of the CONFIG_HPS namespace options are changed via the board
> > config.h file, nor does it make sense to move them to Kconfig. Rename
> > these options to the HPS namespace instead.
> >
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> > Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> > Signed-off-by: Tom Rini <trini@konsulko.com>
> > ---
> > Note, this patch is complete as the changes to the regex qts-filter.sh
> > are such a long line that git send-email fails. This patch was
> > generated by:
> > $ git grep -l CONFIG_HPS_ | xargs sed -i -e 's/CONFIG_HPS_/HPS_/g'
> > and I will re-run that before applying.
>
> The problem is, it is the altera tools which generate all those CONFIG_*
> symbols which are processed by the qts-filter.sh and placed into those qts/
> board directories, so this patch breaks all that. You'd have to fix the
> qts-filter to scrub the CONFIG_ prefixes first.
Do you mean the in-tree qts-filter.sh file needs to be changed, or
something else?
--
Tom
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/1] arm: socfpga: Migrate CONFIG_HPS namespace to HPS
2021-08-10 20:11 ` Marek Vasut
2021-08-10 20:28 ` Tom Rini
@ 2021-08-10 20:47 ` Tom Rini
2021-08-10 20:53 ` Marek Vasut
1 sibling, 1 reply; 7+ messages in thread
From: Tom Rini @ 2021-08-10 20:47 UTC (permalink / raw)
To: Marek Vasut; +Cc: u-boot, Simon Goldschmidt, Tien Fong Chee
[-- Attachment #1: Type: text/plain, Size: 1298 bytes --]
On Tue, Aug 10, 2021 at 10:11:08PM +0200, Marek Vasut wrote:
> On 8/10/21 10:05 PM, Tom Rini wrote:
> > None of the CONFIG_HPS namespace options are changed via the board
> > config.h file, nor does it make sense to move them to Kconfig. Rename
> > these options to the HPS namespace instead.
> >
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> > Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> > Signed-off-by: Tom Rini <trini@konsulko.com>
> > ---
> > Note, this patch is complete as the changes to the regex qts-filter.sh
> > are such a long line that git send-email fails. This patch was
> > generated by:
> > $ git grep -l CONFIG_HPS_ | xargs sed -i -e 's/CONFIG_HPS_/HPS_/g'
> > and I will re-run that before applying.
>
> The problem is, it is the altera tools which generate all those CONFIG_*
> symbols which are processed by the qts-filter.sh and placed into those qts/
> board directories, so this patch breaks all that. You'd have to fix the
> qts-filter to scrub the CONFIG_ prefixes first.
Or rather, ugh, are there out of tree tools we need to deal with here?
Perhaps someone with the tools could pick up and v2 something tested if
so as it'll probably be a bit tricky getting it all right.
--
Tom
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/1] arm: socfpga: Migrate CONFIG_HPS namespace to HPS
2021-08-10 20:47 ` Tom Rini
@ 2021-08-10 20:53 ` Marek Vasut
2021-08-10 20:57 ` Tom Rini
0 siblings, 1 reply; 7+ messages in thread
From: Marek Vasut @ 2021-08-10 20:53 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot, Simon Goldschmidt, Tien Fong Chee
On 8/10/21 10:47 PM, Tom Rini wrote:
> On Tue, Aug 10, 2021 at 10:11:08PM +0200, Marek Vasut wrote:
>> On 8/10/21 10:05 PM, Tom Rini wrote:
>>> None of the CONFIG_HPS namespace options are changed via the board
>>> config.h file, nor does it make sense to move them to Kconfig. Rename
>>> these options to the HPS namespace instead.
>>>
>>> Cc: Marek Vasut <marex@denx.de>
>>> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>>> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
>>> Signed-off-by: Tom Rini <trini@konsulko.com>
>>> ---
>>> Note, this patch is complete as the changes to the regex qts-filter.sh
>>> are such a long line that git send-email fails. This patch was
>>> generated by:
>>> $ git grep -l CONFIG_HPS_ | xargs sed -i -e 's/CONFIG_HPS_/HPS_/g'
>>> and I will re-run that before applying.
>>
>> The problem is, it is the altera tools which generate all those CONFIG_*
>> symbols which are processed by the qts-filter.sh and placed into those qts/
>> board directories, so this patch breaks all that. You'd have to fix the
>> qts-filter to scrub the CONFIG_ prefixes first.
>
> Or rather, ugh, are there out of tree tools we need to deal with here?
> Perhaps someone with the tools could pick up and v2 something tested if
> so as it'll probably be a bit tricky getting it all right.
See doc/README.socfpga . The out of tree tools generate board/bitstream
specific input header files which you plug into the qts-filter.sh script
, those files contain the CONFIG_* macros and those files get converted
by the qts-filter.sh script into the output header files in
board/*/qts/*.h . The output header files are what is used by U-Boot then.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/1] arm: socfpga: Migrate CONFIG_HPS namespace to HPS
2021-08-10 20:53 ` Marek Vasut
@ 2021-08-10 20:57 ` Tom Rini
2021-08-12 6:56 ` Chee, Tien Fong
0 siblings, 1 reply; 7+ messages in thread
From: Tom Rini @ 2021-08-10 20:57 UTC (permalink / raw)
To: Marek Vasut; +Cc: u-boot, Simon Goldschmidt, Tien Fong Chee
[-- Attachment #1: Type: text/plain, Size: 2083 bytes --]
On Tue, Aug 10, 2021 at 10:53:02PM +0200, Marek Vasut wrote:
> On 8/10/21 10:47 PM, Tom Rini wrote:
> > On Tue, Aug 10, 2021 at 10:11:08PM +0200, Marek Vasut wrote:
> > > On 8/10/21 10:05 PM, Tom Rini wrote:
> > > > None of the CONFIG_HPS namespace options are changed via the board
> > > > config.h file, nor does it make sense to move them to Kconfig. Rename
> > > > these options to the HPS namespace instead.
> > > >
> > > > Cc: Marek Vasut <marex@denx.de>
> > > > Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> > > > Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > Signed-off-by: Tom Rini <trini@konsulko.com>
> > > > ---
> > > > Note, this patch is complete as the changes to the regex qts-filter.sh
> > > > are such a long line that git send-email fails. This patch was
> > > > generated by:
> > > > $ git grep -l CONFIG_HPS_ | xargs sed -i -e 's/CONFIG_HPS_/HPS_/g'
> > > > and I will re-run that before applying.
> > >
> > > The problem is, it is the altera tools which generate all those CONFIG_*
> > > symbols which are processed by the qts-filter.sh and placed into those qts/
> > > board directories, so this patch breaks all that. You'd have to fix the
> > > qts-filter to scrub the CONFIG_ prefixes first.
> >
> > Or rather, ugh, are there out of tree tools we need to deal with here?
> > Perhaps someone with the tools could pick up and v2 something tested if
> > so as it'll probably be a bit tricky getting it all right.
>
> See doc/README.socfpga . The out of tree tools generate board/bitstream
> specific input header files which you plug into the qts-filter.sh script ,
> those files contain the CONFIG_* macros and those files get converted by the
> qts-filter.sh script into the output header files in board/*/qts/*.h . The
> output header files are what is used by U-Boot then.
So doc/README.socfpga needs to be updated to rST as well, when someone
that can run the tools and test the scripts work as expected and don't
use the CONFIG_HPS namespace. Thanks for explaining a bit more.
--
Tom
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^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 1/1] arm: socfpga: Migrate CONFIG_HPS namespace to HPS
2021-08-10 20:57 ` Tom Rini
@ 2021-08-12 6:56 ` Chee, Tien Fong
0 siblings, 0 replies; 7+ messages in thread
From: Chee, Tien Fong @ 2021-08-12 6:56 UTC (permalink / raw)
To: Tom Rini, Marek Vasut
Cc: u-boot, Simon Goldschmidt, Gan, Yau Wai, Lim, Elly Siew Chin
Hi,
> -----Original Message-----
> From: Tom Rini <trini@konsulko.com>
> Sent: Wednesday, 11 August, 2021 4:57 AM
> To: Marek Vasut <marex@denx.de>
> Cc: u-boot@lists.denx.de; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>
> Subject: Re: [PATCH 1/1] arm: socfpga: Migrate CONFIG_HPS namespace to HPS
>
> On Tue, Aug 10, 2021 at 10:53:02PM +0200, Marek Vasut wrote:
> > On 8/10/21 10:47 PM, Tom Rini wrote:
> > > On Tue, Aug 10, 2021 at 10:11:08PM +0200, Marek Vasut wrote:
> > > > On 8/10/21 10:05 PM, Tom Rini wrote:
> > > > > None of the CONFIG_HPS namespace options are changed via the
> > > > > board config.h file, nor does it make sense to move them to
> > > > > Kconfig. Rename these options to the HPS namespace instead.
> > > > >
> > > > > Cc: Marek Vasut <marex@denx.de>
> > > > > Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> > > > > Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > Signed-off-by: Tom Rini <trini@konsulko.com>
> > > > > ---
> > > > > Note, this patch is complete as the changes to the regex
> > > > > qts-filter.sh are such a long line that git send-email fails.
> > > > > This patch was generated by:
> > > > > $ git grep -l CONFIG_HPS_ | xargs sed -i -e 's/CONFIG_HPS_/HPS_/g'
> > > > > and I will re-run that before applying.
> > > >
> > > > The problem is, it is the altera tools which generate all those
> > > > CONFIG_* symbols which are processed by the qts-filter.sh and
> > > > placed into those qts/ board directories, so this patch breaks all
> > > > that. You'd have to fix the qts-filter to scrub the CONFIG_ prefixes first.
> > >
> > > Or rather, ugh, are there out of tree tools we need to deal with here?
> > > Perhaps someone with the tools could pick up and v2 something tested
> > > if so as it'll probably be a bit tricky getting it all right.
> >
> > See doc/README.socfpga . The out of tree tools generate
> > board/bitstream specific input header files which you plug into the
> > qts-filter.sh script , those files contain the CONFIG_* macros and
> > those files get converted by the qts-filter.sh script into the output
> > header files in board/*/qts/*.h . The output header files are what is used by U-
> Boot then.
>
> So doc/README.socfpga needs to be updated to rST as well, when someone
> that can run the tools and test the scripts work as expected and don't use the
> CONFIG_HPS namespace. Thanks for explaining a bit more.
Thanks for cleaning these up, the scripts are also required to get changed and testing.
I will work with internal team to get these done, include converting doc/README.socfpga into rST as well.
TF
>
> --
> Tom
^ permalink raw reply [flat|nested] 7+ messages in thread
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-- links below jump to the message on this page --
2021-08-10 20:05 [PATCH 1/1] arm: socfpga: Migrate CONFIG_HPS namespace to HPS Tom Rini
2021-08-10 20:11 ` Marek Vasut
2021-08-10 20:28 ` Tom Rini
2021-08-10 20:47 ` Tom Rini
2021-08-10 20:53 ` Marek Vasut
2021-08-10 20:57 ` Tom Rini
2021-08-12 6:56 ` Chee, Tien Fong
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