[U-Boot] [PATCH 01/11] arm64: zynqmp: Remove slcr with mio status pin detection

[U-Boot] [PATCH 01/11] arm64: zynqmp: Remove slcr with mio status pin detection

[Michal Simek]

This code is not used on this platform and it is not called.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/cpu/armv8/zynqmp/Makefile           |  1 -
 arch/arm/cpu/armv8/zynqmp/slcr.c             | 63 ----------------------------
 arch/arm/include/asm/arch-zynqmp/sys_proto.h |  2 -
 3 files changed, 66 deletions(-)
 delete mode 100644 arch/arm/cpu/armv8/zynqmp/slcr.c

diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile
index 013f136707b5..72dee3ded48f 100644
--- a/arch/arm/cpu/armv8/zynqmp/Makefile
+++ b/arch/arm/cpu/armv8/zynqmp/Makefile
@@ -8,5 +8,4 @@
 obj-y	+= clk.o
 obj-y	+= cpu.o
 obj-$(CONFIG_MP)	+= mp.o
-obj-y	+= slcr.o
 obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
diff --git a/arch/arm/cpu/armv8/zynqmp/slcr.c b/arch/arm/cpu/armv8/zynqmp/slcr.c
deleted file mode 100644
index 713e9a62c019..000000000000
--- a/arch/arm/cpu/armv8/zynqmp/slcr.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clk.h>
-
-/*
- * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
- *
- * @peri_name: Name of the peripheral for checking MIO status
- * @get_pins: Pointer to array of get pin for this peripheral
- * @num_pins: Number of pins for this peripheral
- * @mask: Mask value
- * @check_val: Required check value to get the status of  periph
- */
-struct zynq_slcr_mio_get_status {
-	const char *peri_name;
-	const int *get_pins;
-	int num_pins;
-	u32 mask;
-	u32 check_val;
-};
-
-static const struct zynq_slcr_mio_get_status mio_periphs[] = {
-};
-
-/*
- * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
- *
- * @periph: Name of the peripheral
- *
- * Returns count to indicate the number of pins configured for the
- * given @periph.
- */
-int zynq_slcr_get_mio_pin_status(const char *periph)
-{
-	const struct zynq_slcr_mio_get_status *mio_ptr;
-	int val, i, j;
-	int mio = 0;
-
-	for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
-		if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
-			mio_ptr = &mio_periphs[i];
-			for (j = 0; j < mio_ptr->num_pins; j++) {
-				val = readl(&slcr_base->mio_pin
-						[mio_ptr->get_pins[j]]);
-				if ((val & mio_ptr->mask) == mio_ptr->check_val)
-					mio++;
-			}
-			break;
-		}
-	}
-
-	return mio;
-}
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index e52abd71a5a3..db1d5ef306f8 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -29,8 +29,6 @@ enum {
 	TCM_SPLIT,
 };
 
-int zynq_slcr_get_mio_pin_status(const char *periph);
-
 unsigned int zynqmp_get_silicon_version(void);
 
 void psu_init(void);
-- 
1.9.1

[U-Boot] [PATCH 02/11] arm64: zynqmp: mp: Correct the R5 release sequence

[Michal Simek]

From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

This patch corrects the R5 release sequence by adding the
below steps.
1. Flush dcache to ensure that image loaded into memory.
2. Keep R5 reset just to ensure R5 in reset.
3. Disable caches before accessing TCM as with out this
   A53 can do speculative and may result in ECC failures
   if TCM's are not initialized. So, it is always better
   to disable dcaches before accessing TCM and enable back.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reported-by: John Linn <linnj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/cpu/armv8/zynqmp/mp.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c
index 76f889ba7d9e..3ea24b47630c 100644
--- a/arch/arm/cpu/armv8/zynqmp/mp.c
+++ b/arch/arm/cpu/armv8/zynqmp/mp.c
@@ -257,22 +257,36 @@ int cpu_release(int nr, int argc, char * const argv[])
 			boot_addr = ZYNQMP_R5_LOVEC_ADDR;
 		}
 
+		/*
+		 * Since we don't know where the user may have loaded the image
+		 * for an R5 we have to flush all the data cache to ensure
+		 * the R5 sees it.
+		 */
+		flush_dcache_all();
+
 		if (!strncmp(argv[1], "lockstep", 8)) {
 			printf("R5 lockstep mode\n");
+			set_r5_reset(LOCK);
 			set_r5_tcm_mode(LOCK);
 			set_r5_halt_mode(HALT, LOCK);
 			set_r5_start(boot_addr);
 			enable_clock_r5();
 			release_r5_reset(LOCK);
+			dcache_disable();
 			write_tcm_boot_trampoline(boot_addr_uniq);
+			dcache_enable();
 			set_r5_halt_mode(RELEASE, LOCK);
 		} else if (!strncmp(argv[1], "split", 5)) {
 			printf("R5 split mode\n");
+			set_r5_reset(SPLIT);
 			set_r5_tcm_mode(SPLIT);
 			set_r5_halt_mode(HALT, SPLIT);
+			set_r5_start(boot_addr);
 			enable_clock_r5();
 			release_r5_reset(SPLIT);
+			dcache_disable();
 			write_tcm_boot_trampoline(boot_addr_uniq);
+			dcache_enable();
 			set_r5_halt_mode(RELEASE, SPLIT);
 		} else {
 			printf("Unsupported mode\n");
-- 
1.9.1

[U-Boot] [PATCH 03/11] arm64: zynqmp: Provide a Kconfig option to use specified memory for MMU table

[Michal Simek]

From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

This patch provides a Kconfig option to use specified
memory for MMU table using reserve_mmu platform specific
routine. Here we used TCM space for MMU table.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/cpu/armv8/zynqmp/Kconfig           |  7 +++++++
 arch/arm/cpu/armv8/zynqmp/cpu.c             | 12 ++++++++++++
 arch/arm/include/asm/arch-zynqmp/hardware.h |  3 +++
 3 files changed, 22 insertions(+)

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 5ffc9f6c867b..4dc8b1caf79e 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -42,6 +42,13 @@ config SYS_CONFIG_NAME
 	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
 	  will be used for board configuration.
 
+config SYS_MEM_RSVD_FOR_MMU
+	bool "Reserve memory for MMU Table"
+	help
+	  If defined this option is used to setup different space for
+	  MMU table than the one which will be allocated during
+	  relocation.
+
 config BOOT_INIT_FILE
 	string "boot.bin init register filename"
 	depends on SPL
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index 9b83e51885fa..f026cb4511f0 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -77,6 +77,18 @@ u64 get_page_table_size(void)
 	return 0x14000;
 }
 
+#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
+int reserve_mmu(void)
+{
+	initialize_tcm(TCM_LOCK);
+	memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
+	gd->arch.tlb_size = PGTABLE_SIZE;
+	gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
+
+	return 0;
+}
+#endif
+
 static unsigned int zynqmp_get_silicon_version_secure(void)
 {
 	u32 ver;
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index cab29ba03691..5f2c98d633e3 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -21,6 +21,9 @@
 #define ZYNQMP_USB0_XHCI_BASEADDR	0xFE200000
 #define ZYNQMP_USB1_XHCI_BASEADDR	0xFE300000
 
+#define ZYNQMP_TCM_BASE_ADDR	0xFFE00000
+#define ZYNQMP_TCM_SIZE		0x40000
+
 #define ZYNQMP_CRL_APB_BASEADDR	0xFF5E0000
 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT	0x1000000
 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT	0
-- 
1.9.1

[U-Boot] [PATCH 04/11] tools: mkimage: Extend mkimage to also include pmufw

[Michal Simek]

This is generated command line when PMUFW_INIT_FILE is setup.

./tools/mkimage -T zynqmpimage -R ./"" -n
./"board/xilinx/zynqmp/pmufw.bin" -d spl/u-boot-spl.bin spl/boot.bin

pmufw has to be in binary format and mkimage is using dynamic
header size generation without using calloc function based on pmufw
size. Boot.bin header is filled with pmufw size and pmufw is copied to
header data section. When header is generated mkimage append
u-boot-spl.bin.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/cpu/armv8/zynqmp/Kconfig |  7 +++
 scripts/Makefile.spl              |  3 +-
 tools/zynqmpimage.c               | 99 ++++++++++++++++++++++++++++++++++++++-
 3 files changed, 107 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 4dc8b1caf79e..7e4eaf782d17 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -57,6 +57,13 @@ config BOOT_INIT_FILE
 	  Add register writes to boot.bin format (max 256 pairs).
 	  Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
 
+config PMUFW_INIT_FILE
+	string "PMU firmware"
+	depends on SPL
+	default ""
+	help
+	  Include PMUFW to boot.bin.
+
 config ZYNQMP_USB
 	bool "Configure ZynqMP USB"
 
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 49b27ac9267b..2fba9e87108d 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -167,7 +167,8 @@ ifdef CONFIG_ARCH_ZYNQ
 MKIMAGEFLAGS_boot.bin = -T zynqimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE)
 endif
 ifdef CONFIG_ARCH_ZYNQMP
-MKIMAGEFLAGS_boot.bin = -T zynqmpimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE)
+MKIMAGEFLAGS_boot.bin = -T zynqmpimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE) \
+	-n $(srctree)/$(CONFIG_PMUFW_INIT_FILE)
 endif
 
 spl/boot.bin: $(obj)/u-boot-spl.bin FORCE
diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c
index 0c9a3daddd6a..74bd5f5ccc3f 100644
--- a/tools/zynqmpimage.c
+++ b/tools/zynqmpimage.c
@@ -99,6 +99,8 @@ struct zynqmp_header {
 };
 
 static struct zynqmp_header zynqmpimage_header;
+static void *dynamic_header;
+static FILE *fpmu;
 
 static uint32_t zynqmpimage_checksum(struct zynqmp_header *ptr)
 {
@@ -181,6 +183,13 @@ static void zynqmpimage_print_header(const void *ptr)
 	printf("Image Size   : %lu bytes (%lu bytes packed)\n",
 	       (unsigned long)le32_to_cpu(zynqhdr->image_size),
 	       (unsigned long)le32_to_cpu(zynqhdr->image_stored_size));
+
+	if (zynqhdr->pfw_image_length)
+		printf("PMUFW Size   : %lu bytes (%lu bytes packed)\n",
+		       (unsigned long)le32_to_cpu(zynqhdr->pfw_image_length),
+		       (unsigned long)le32_to_cpu(
+				zynqhdr->total_pfw_image_length));
+
 	printf("Image Load   : 0x%08x\n", le32_to_cpu(zynqhdr->image_load));
 	printf("Checksum     : 0x%08x\n", le32_to_cpu(zynqhdr->checksum));
 
@@ -203,6 +212,8 @@ static void zynqmpimage_print_header(const void *ptr)
 		       le32_to_cpu(zynqhdr->register_init[i].address),
 		       le32_to_cpu(zynqhdr->register_init[i].data));
 	}
+
+	free(dynamic_header);
 }
 
 static int zynqmpimage_check_params(struct image_tool_params *params)
@@ -234,6 +245,44 @@ static int zynqmpimage_check_image_types(uint8_t type)
 	return EXIT_FAILURE;
 }
 
+static int fsize(FILE *fp)
+{
+	int size;
+	int origin = ftell(fp);
+
+	fseek(fp, 0L, SEEK_END);
+	size = ftell(fp);
+
+	/* going back */
+	fseek(fp, origin, SEEK_SET);
+
+	return size;
+}
+
+static void zynqmpimage_pmufw(struct zynqmp_header *zynqhdr,
+			      const char *filename)
+{
+	uint32_t size;
+
+	/* Setup PMU fw size */
+	zynqhdr->pfw_image_length = fsize(fpmu);
+	zynqhdr->total_pfw_image_length = zynqhdr->pfw_image_length;
+
+	zynqhdr->image_size -= zynqhdr->pfw_image_length;
+	zynqhdr->image_stored_size -= zynqhdr->total_pfw_image_length;
+
+	/* Read the whole PMUFW to the header */
+	size = fread(&zynqhdr->__reserved4[66], 1,
+		     zynqhdr->pfw_image_length, fpmu);
+	if (size != zynqhdr->pfw_image_length) {
+		fprintf(stderr, "Cannot read PMUFW file: %s\n", filename);
+		fclose(fpmu);
+		exit(1);
+	}
+
+	fclose(fpmu);
+}
+
 static void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr,
 	const char *filename)
 {
@@ -288,6 +337,10 @@ static void zynqmpimage_set_header(void *ptr, struct stat *sbuf, int ifd,
 	if (params->eflag)
 		zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep);
 
+	/* PMUFW */
+	if (fpmu)
+		zynqmpimage_pmufw(zynqhdr, params->imagename);
+
 	/* User can pass in text file with init list */
 	if (strlen(params->imagename2))
 		zynqmpimage_parse_initparams(zynqhdr, params->imagename2);
@@ -295,6 +348,50 @@ static void zynqmpimage_set_header(void *ptr, struct stat *sbuf, int ifd,
 	zynqhdr->checksum = zynqmpimage_checksum(zynqhdr);
 }
 
+static int zynqmpimage_vrec_header(struct image_tool_params *params,
+				   struct image_type_params *tparams)
+{
+	struct stat path_stat;
+	char *filename = params->imagename;
+	int err;
+
+	/* Handle static case without PMUFW */
+	tparams->header_size = sizeof(struct zynqmp_header);
+	tparams->hdr = (void *)&zynqmpimage_header;
+
+	/* PMUFW name is passed via params->imagename */
+	if (strlen(filename) == 0)
+		return EXIT_SUCCESS;
+
+	fpmu = fopen(filename, "r");
+	if (!fpmu) {
+		fprintf(stderr, "Cannot open PMUFW file: %s\n", filename);
+		return EXIT_FAILURE;
+	}
+
+	err = fstat(fileno(fpmu), &path_stat);
+	if (err) {
+		fclose(fpmu);
+		fpmu = NULL;
+		return EXIT_FAILURE;
+	}
+
+	if (!S_ISREG(path_stat.st_mode)) {
+		fclose(fpmu);
+		fpmu = NULL;
+		return EXIT_FAILURE;
+	}
+
+	/* Increase header size by PMUFW file size */
+	tparams->header_size += fsize(fpmu);
+
+	/* Allocate buffer with space for PMUFW */
+	dynamic_header = calloc(1, tparams->header_size);
+	tparams->hdr = dynamic_header;
+
+	return EXIT_SUCCESS;
+}
+
 U_BOOT_IMAGE_TYPE(
 	zynqmpimage,
 	"Xilinx ZynqMP Boot Image support",
@@ -307,5 +404,5 @@ U_BOOT_IMAGE_TYPE(
 	NULL,
 	zynqmpimage_check_image_types,
 	NULL,
-	NULL
+	zynqmpimage_vrec_header
 );
-- 
1.9.1

[U-Boot] [PATCH 05/11] arm64: zynqmp: Enable config DEFINE_TCM_OCM_MMAP if CONFIG_MP defined

[Michal Simek]

From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

This modifies default value of config DEFINE_TCM_OCM_MMAP
to yes if CONFIG_MP is defined MP supports needs OCM and TCM
part of memory map.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/cpu/armv8/zynqmp/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 7e4eaf782d17..4215328a7140 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -72,6 +72,7 @@ config SYS_MALLOC_F_LEN
 
 config DEFINE_TCM_OCM_MMAP
 	bool "Define TCM and OCM memory in MMU Table"
+	default y if MP
 	help
 	  This option if enabled defines the TCM and OCM memory and its
 	  memory attributes in MMU table entry.
-- 
1.9.1

[U-Boot] [PATCH 06/11] arm64: zynqmp: Add SD1 level shifter mode to alternative selection

[Michal Simek]

Extend Kconfig to cover SD1 level shifter mode.

Reported-by: Jason Wu <jason.hy.wu@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/cpu/armv8/zynqmp/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 4215328a7140..1e941c048be0 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -101,6 +101,7 @@ config SPL_ZYNQMP_ALT_BOOTMODE
 	default 0x7 if USB_MODE
 	default 0xa if SW_USBHOST_MODE
 	default 0xb if SW_SATA_MODE
+	default 0xe if SD1_LSHFT_MODE
 
 choice
 	prompt "Boot mode"
@@ -137,6 +138,9 @@ config SW_USBHOST_MODE
 config SW_SATA_MODE
 	bool "SW SATA_MODE"
 
+config SD1_LSHFT_MODE
+	bool "SD1_LSHFT_MODE"
+
 endchoice
 
 endif
-- 
1.9.1

[U-Boot] [PATCH 07/11] arm64: zynqmp: Use u32 type instead of uint32_t

[Michal Simek]

Warning is reported by checkpatch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 board/xilinx/zynqmp/zynqmp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index a036ed6a35d3..5e22cc54ba69 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
 
 static const struct {
-	uint32_t id;
+	u32 id;
 	char *name;
 } zynqmp_devices[] = {
 	{
@@ -136,7 +136,7 @@ int chip_id(unsigned char id)
 	!defined(CONFIG_SPL_BUILD)
 static char *zynqmp_get_silicon_idcode_name(void)
 {
-	uint32_t i, id;
+	u32 i, id;
 
 	id = chip_id(IDCODE);
 	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
-- 
1.9.1

[U-Boot] [PATCH 08/11] arm64: zynqmp: Add support for CG/EG/EV device detection

[Michal Simek]

Version string has unused fields 31:20 which can be used for exporting 9
bits from efuse IPDISABLE regs to recognize eg/cg/ev devices.

These efuse bits are setup for certain devices.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/include/asm/arch-zynqmp/hardware.h  |  2 +
 arch/arm/include/asm/arch-zynqmp/sys_proto.h |  1 +
 board/xilinx/zynqmp/zynqmp.c                 | 68 +++++++++++++++++++++++++++-
 3 files changed, 69 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 5f2c98d633e3..327046bf1b29 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -128,6 +128,8 @@ struct apu_regs {
 #define ZYNQMP_CSU_VERSION_VELOCE	0x2
 #define ZYNQMP_CSU_VERSION_QEMU		0x3
 
+#define ZYNQMP_CSU_VERSION_EMPTY_SHIFT		20
+
 #define ZYNQMP_SILICON_VER_MASK		0xF000
 #define ZYNQMP_SILICON_VER_SHIFT	12
 
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index db1d5ef306f8..f256c7d4a996 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -15,6 +15,7 @@
 enum {
 	IDCODE,
 	VERSION,
+	IDCODE2,
 };
 
 enum {
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 5e22cc54ba69..2b1d8119f567 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -28,6 +28,7 @@ static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
 
 static const struct {
 	u32 id;
+	u32 ver;
 	char *name;
 } zynqmp_devices[] = {
 	{
@@ -35,33 +36,88 @@ static const struct {
 		.name = "3eg",
 	},
 	{
+		.id = 0x10,
+		.ver = 0x2c,
+		.name = "3cg",
+	},
+	{
 		.id = 0x11,
 		.name = "2eg",
 	},
 	{
+		.id = 0x11,
+		.ver = 0x2c,
+		.name = "2cg",
+	},
+	{
 		.id = 0x20,
 		.name = "5ev",
 	},
 	{
+		.id = 0x20,
+		.ver = 0x100,
+		.name = "5eg",
+	},
+	{
+		.id = 0x20,
+		.ver = 0x12c,
+		.name = "5cg",
+	},
+	{
 		.id = 0x21,
 		.name = "4ev",
 	},
 	{
+		.id = 0x21,
+		.ver = 0x100,
+		.name = "4eg",
+	},
+	{
+		.id = 0x21,
+		.ver = 0x12c,
+		.name = "4cg",
+	},
+	{
 		.id = 0x30,
 		.name = "7ev",
 	},
 	{
+		.id = 0x30,
+		.ver = 0x100,
+		.name = "7eg",
+	},
+	{
+		.id = 0x30,
+		.ver = 0x12c,
+		.name = "7cg",
+	},
+	{
 		.id = 0x38,
 		.name = "9eg",
 	},
 	{
+		.id = 0x38,
+		.ver = 0x2c,
+		.name = "9cg",
+	},
+	{
 		.id = 0x39,
 		.name = "6eg",
 	},
 	{
+		.id = 0x39,
+		.ver = 0x2c,
+		.name = "6cg",
+	},
+	{
 		.id = 0x40,
 		.name = "11eg",
 	},
+	{ /* For testing purpose only */
+		.id = 0x50,
+		.ver = 0x2c,
+		.name = "15cg",
+	},
 	{
 		.id = 0x50,
 		.name = "15eg",
@@ -95,6 +151,7 @@ int chip_id(unsigned char id)
 		 * regs[0][31:0]  = status of the operation
 		 * regs[0][63:32] = CSU.IDCODE register
 		 * regs[1][31:0]  = CSU.version register
+		 * regs[1][63:32] = CSU.IDCODE2 register
 		 */
 		switch (id) {
 		case IDCODE:
@@ -109,6 +166,11 @@ int chip_id(unsigned char id)
 			regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 			val = regs.regs[1];
 			break;
+		case IDCODE2:
+			regs.regs[1] = lower_32_bits(regs.regs[1]);
+			regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
+			val = regs.regs[1];
+			break;
 		default:
 			printf("%s, Invalid Req:0x%x\n", __func__, id);
 		}
@@ -136,11 +198,13 @@ int chip_id(unsigned char id)
 	!defined(CONFIG_SPL_BUILD)
 static char *zynqmp_get_silicon_idcode_name(void)
 {
-	u32 i, id;
+	u32 i, id, ver;
 
 	id = chip_id(IDCODE);
+	ver = chip_id(IDCODE2);
+
 	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
-		if (zynqmp_devices[i].id == id)
+		if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
 			return zynqmp_devices[i].name;
 	}
 	return "unknown";
-- 
1.9.1

[U-Boot] [PATCH 09/11] arm64: zynqmp: Add new ID for RFSoC

[Michal Simek]

This ID is available on zc1254.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 board/xilinx/zynqmp/zynqmp.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 2b1d8119f567..f769db7e81b9 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -130,6 +130,30 @@ static const struct {
 		.id = 0x59,
 		.name = "17eg",
 	},
+	{
+		.id = 0x61,
+		.name = "21dr",
+	},
+	{
+		.id = 0x63,
+		.name = "23dr",
+	},
+	{
+		.id = 0x65,
+		.name = "25dr",
+	},
+	{
+		.id = 0x64,
+		.name = "27dr",
+	},
+	{
+		.id = 0x60,
+		.name = "28dr",
+	},
+	{
+		.id = 0x62,
+		.name = "29dr",
+	},
 };
 #endif
 
-- 
1.9.1

[U-Boot] [PATCH 10/11] arm64: zynqmp: Enable debug uart for zc1751 dc5

[Michal Simek]

Showing uart earlier.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index c854ba76709c..0d0a5bcc8697 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm019 dc5"
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
+CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -39,4 +40,8 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_SERIAL=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-- 
1.9.1

[U-Boot] [PATCH 11/11] arm64: zynqmp: Wire QSPI boot mode for SPL

[Michal Simek]

From: Michal Simek <monstr@monstr.eu>

ZynqMP qspi driver is on the way to mainline

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/cpu/armv8/zynqmp/spl.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c
index 468dc1dc4d54..41b0070a5e1a 100644
--- a/arch/arm/cpu/armv8/zynqmp/spl.c
+++ b/arch/arm/cpu/armv8/zynqmp/spl.c
@@ -102,6 +102,11 @@ u32 spl_boot_device(void)
 	case SW_SATA_MODE:
 		return BOOT_DEVICE_SATA;
 #endif
+#ifdef CONFIG_SPL_SPI_SUPPORT
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		return BOOT_DEVICE_SPI;
+#endif
 	default:
 		printf("Invalid Boot Mode:0x%x\n", bootmode);
 		break;
-- 
1.9.1

[U-Boot] [PATCH 04/11] tools: mkimage: Extend mkimage to also include pmufw

[Simon Glass]

Hi Michal,

On 6 November 2017 at 05:02, Michal Simek <michal.simek@xilinx.com> wrote:
> This is generated command line when PMUFW_INIT_FILE is setup.
>
> ./tools/mkimage -T zynqmpimage -R ./"" -n
> ./"board/xilinx/zynqmp/pmufw.bin" -d spl/u-boot-spl.bin spl/boot.bin
>
> pmufw has to be in binary format and mkimage is using dynamic
> header size generation without using calloc function based on pmufw
> size. Boot.bin header is filled with pmufw size and pmufw is copied to
> header data section. When header is generated mkimage append
> u-boot-spl.bin.

Can you reword this a bit? It is a bit confusing to read.

>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
>  arch/arm/cpu/armv8/zynqmp/Kconfig |  7 +++
>  scripts/Makefile.spl              |  3 +-
>  tools/zynqmpimage.c               | 99 ++++++++++++++++++++++++++++++++++++++-
>  3 files changed, 107 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
> index 4dc8b1caf79e..7e4eaf782d17 100644
> --- a/arch/arm/cpu/armv8/zynqmp/Kconfig
> +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
> @@ -57,6 +57,13 @@ config BOOT_INIT_FILE
>           Add register writes to boot.bin format (max 256 pairs).
>           Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
>
> +config PMUFW_INIT_FILE
> +       string "PMU firmware"
> +       depends on SPL
> +       default ""
> +       help
> +         Include PMUFW to boot.bin.

Help should include full details. Abbreviations should be explained.

Also are you saying that this tacks something new onto u-boot.bin?
Where is that happening and how is it found at run time? I'm wondering
is this might be a job for binman?

> +
>  config ZYNQMP_USB
>         bool "Configure ZynqMP USB"
>

Regards,
Simon

[U-Boot] [PATCH 04/11] tools: mkimage: Extend mkimage to also include pmufw

[Michal Simek]

On 20.11.2017 16:38, Simon Glass wrote:
> Hi Michal,
> 
> On 6 November 2017 at 05:02, Michal Simek <michal.simek@xilinx.com> wrote:
>> This is generated command line when PMUFW_INIT_FILE is setup.
>>
>> ./tools/mkimage -T zynqmpimage -R ./"" -n
>> ./"board/xilinx/zynqmp/pmufw.bin" -d spl/u-boot-spl.bin spl/boot.bin
>>
>> pmufw has to be in binary format and mkimage is using dynamic
>> header size generation without using calloc function based on pmufw
>> size. Boot.bin header is filled with pmufw size and pmufw is copied to
>> header data section. When header is generated mkimage append
>> u-boot-spl.bin.
> 
> Can you reword this a bit? It is a bit confusing to read.

Fixed in v2.

> 
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>>  arch/arm/cpu/armv8/zynqmp/Kconfig |  7 +++
>>  scripts/Makefile.spl              |  3 +-
>>  tools/zynqmpimage.c               | 99 ++++++++++++++++++++++++++++++++++++++-
>>  3 files changed, 107 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
>> index 4dc8b1caf79e..7e4eaf782d17 100644
>> --- a/arch/arm/cpu/armv8/zynqmp/Kconfig
>> +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
>> @@ -57,6 +57,13 @@ config BOOT_INIT_FILE
>>           Add register writes to boot.bin format (max 256 pairs).
>>           Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
>>
>> +config PMUFW_INIT_FILE
>> +       string "PMU firmware"
>> +       depends on SPL
>> +       default ""
>> +       help
>> +         Include PMUFW to boot.bin.
> 
> Help should include full details. Abbreviations should be explained.

I have fixed this too.

> 
> Also are you saying that this tacks something new onto u-boot.bin?
> Where is that happening and how is it found at run time? I'm wondering
> is this might be a job for binman?

Nope. It is really just boot header follows by pmufw.bin and
u-boot-spl.bin >> boot.bin

bootrom based on headers know that there is pmufw.bin which is consumed
by PMU unit which is microblaze cpu. And SPL runs on a53s.

I am aware about binman when you send the first version but haven't had
any time to look at it. This mkimage extension is something I used for
pretty long time and I didn't see any issue for this usecase.

boot.bin format can contain multiple sessions for example ATF, full
u-boot, Linux, rootfs, app for arm R5, bitstream, etc. For generating
this boot.bin maybe binman could be right tool but Xilinx has own tools
called bootgen which is capable to generate this image. It also contains
encryption and authentication parts.

Thanks,
Michal


Thanks,
Michal