* [U-Boot] [PATCH v2 0/7] Support for the Faraday ftgmac100 controller
@ 2018-10-01 8:53 Cédric Le Goater
2018-10-01 8:53 ` [U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver Cédric Le Goater
` (6 more replies)
0 siblings, 7 replies; 18+ messages in thread
From: Cédric Le Goater @ 2018-10-01 8:53 UTC (permalink / raw)
To: u-boot
Hello,
This series re-adds a driver for the Faraday ftgmac100 controller and
its Aspeed variant as as one can find on the OpenPOWER platforms.
I have choosen to remove and re-add the driver to ease review of the
changes, which are numerous, but we can proceed differently if you
prefer.
It was tested on the AST2500 evb.
Git tree available here:
https://github.com/legoater/u-boot/commits/aspeed
Thanks,
C.
Changes since v1 :
- improved comments in the code
- changed the type of 'iobase' to 'struct ftgmac100 *' to remove the
casts in other routines.
- replaced the loop in the mdio methods by a call to readl_poll_timeout()
and fixed the returned value.
- added a flush cache on the arrays of TX and RX descriptors in
ftgmac100_start()
- fixed returned value of
- added a timer loop to catch transmit timeouts
- introduced a clk_bulk
- improved Kconfig description
- introduced a udevice_id .data model
- dropped is_aspeed bool
- dropped MDIO interface setting for Aspeed SoC. The default is
correct.
- removed the clcoks which are now handled automatically in the
ftgmac100 driver
- introduced a fix for the D2-PLL clock setting
Cédric Le Goater (7):
net: Remove the Faraday ftgmac100 controller driver
net: Re-add support for the Faraday ftgmac100 controller
aspeed: ast2500: fix missing break in D2PLL clock enablement
net: ftgmac100: Add support for the Aspeed SoC
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level
aspeed: Activate ethernet devices on the ast2500 Eval Board
aspeed: ast2500: fix D2-PLL clock setting in RGMII mode
drivers/net/ftgmac100.h | 158 +--
include/netdev.h | 1 -
drivers/clk/aspeed/clk_ast2500.c | 39 +
drivers/net/ftgmac100.c | 761 ++++++------
arch/arm/dts/ast2500-evb.dts | 23 +
arch/arm/dts/ast2500.dtsi | 1995 ++++++++++++++++++------------
configs/evb-ast2500_defconfig | 8 +
drivers/net/Kconfig | 26 +
8 files changed, 1747 insertions(+), 1264 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver
2018-10-01 8:53 [U-Boot] [PATCH v2 0/7] Support for the Faraday ftgmac100 controller Cédric Le Goater
@ 2018-10-01 8:53 ` Cédric Le Goater
2018-10-02 11:22 ` Simon Glass
2018-10-01 8:53 ` [U-Boot] [PATCH v2 2/7] net: Re-add support for the Faraday ftgmac100 controller Cédric Le Goater
` (5 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Cédric Le Goater @ 2018-10-01 8:53 UTC (permalink / raw)
To: u-boot
There are too many changes in the following patch fixing support for
the Faraday ftgmac100 controller. To ease the review, remove the whole
file which is not compiled anymore today (no Kconfig option for the
driver).
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/net/ftgmac100.h | 242 -----------------
include/netdev.h | 1 -
drivers/net/ftgmac100.c | 582 ----------------------------------------
drivers/net/Makefile | 1 -
4 files changed, 826 deletions(-)
delete mode 100644 drivers/net/ftgmac100.h
delete mode 100644 drivers/net/ftgmac100.c
diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h
deleted file mode 100644
index ffbe1f3e3fa7..000000000000
--- a/drivers/net/ftgmac100.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Faraday FTGMAC100 Ethernet
- *
- * (C) Copyright 2010 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * (C) Copyright 2010 Andes Technology
- * Macpaul Lin <macpaul@andestech.com>
- */
-
-#ifndef __FTGMAC100_H
-#define __FTGMAC100_H
-
-/* The registers offset table of ftgmac100 */
-struct ftgmac100 {
- unsigned int isr; /* 0x00 */
- unsigned int ier; /* 0x04 */
- unsigned int mac_madr; /* 0x08 */
- unsigned int mac_ladr; /* 0x0c */
- unsigned int maht0; /* 0x10 */
- unsigned int maht1; /* 0x14 */
- unsigned int txpd; /* 0x18 */
- unsigned int rxpd; /* 0x1c */
- unsigned int txr_badr; /* 0x20 */
- unsigned int rxr_badr; /* 0x24 */
- unsigned int hptxpd; /* 0x28 */
- unsigned int hptxpd_badr; /* 0x2c */
- unsigned int itc; /* 0x30 */
- unsigned int aptc; /* 0x34 */
- unsigned int dblac; /* 0x38 */
- unsigned int dmafifos; /* 0x3c */
- unsigned int revr; /* 0x40 */
- unsigned int fear; /* 0x44 */
- unsigned int tpafcr; /* 0x48 */
- unsigned int rbsr; /* 0x4c */
- unsigned int maccr; /* 0x50 */
- unsigned int macsr; /* 0x54 */
- unsigned int tm; /* 0x58 */
- unsigned int resv1; /* 0x5c */ /* not defined in spec */
- unsigned int phycr; /* 0x60 */
- unsigned int phydata; /* 0x64 */
- unsigned int fcr; /* 0x68 */
- unsigned int bpr; /* 0x6c */
- unsigned int wolcr; /* 0x70 */
- unsigned int wolsr; /* 0x74 */
- unsigned int wfcrc; /* 0x78 */
- unsigned int resv2; /* 0x7c */ /* not defined in spec */
- unsigned int wfbm1; /* 0x80 */
- unsigned int wfbm2; /* 0x84 */
- unsigned int wfbm3; /* 0x88 */
- unsigned int wfbm4; /* 0x8c */
- unsigned int nptxr_ptr; /* 0x90 */
- unsigned int hptxr_ptr; /* 0x94 */
- unsigned int rxr_ptr; /* 0x98 */
- unsigned int resv3; /* 0x9c */ /* not defined in spec */
- unsigned int tx; /* 0xa0 */
- unsigned int tx_mcol_scol; /* 0xa4 */
- unsigned int tx_ecol_fail; /* 0xa8 */
- unsigned int tx_lcol_und; /* 0xac */
- unsigned int rx; /* 0xb0 */
- unsigned int rx_bc; /* 0xb4 */
- unsigned int rx_mc; /* 0xb8 */
- unsigned int rx_pf_aep; /* 0xbc */
- unsigned int rx_runt; /* 0xc0 */
- unsigned int rx_crcer_ftl; /* 0xc4 */
- unsigned int rx_col_lost; /* 0xc8 */
-};
-
-/*
- * Interrupt status register & interrupt enable register
- */
-#define FTGMAC100_INT_RPKT_BUF (1 << 0)
-#define FTGMAC100_INT_RPKT_FIFO (1 << 1)
-#define FTGMAC100_INT_NO_RXBUF (1 << 2)
-#define FTGMAC100_INT_RPKT_LOST (1 << 3)
-#define FTGMAC100_INT_XPKT_ETH (1 << 4)
-#define FTGMAC100_INT_XPKT_FIFO (1 << 5)
-#define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
-#define FTGMAC100_INT_XPKT_LOST (1 << 7)
-#define FTGMAC100_INT_AHB_ERR (1 << 8)
-#define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
-#define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
-
-/*
- * Interrupt timer control register
- */
-#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
-#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
-#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7)
-#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
-#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
-#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15)
-
-/*
- * Automatic polling timer control register
- */
-#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
-#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
-#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
-#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
-
-/*
- * DMA burst length and arbitration control register
- */
-#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0)
-#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3)
-#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6)
-#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8)
-#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
-#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12)
-#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16)
-#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
-#define FTGMAC100_DBLAC_IFG_INC (1 << 23)
-
-/*
- * DMA FIFO status register
- */
-#define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf)
-#define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf)
-#define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7)
-#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf)
-#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3)
-#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf)
-#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26)
-#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27)
-#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28)
-#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29)
-#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30)
-#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31)
-
-/*
- * Receive buffer size register
- */
-#define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff)
-
-/*
- * MAC control register
- */
-#define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
-#define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
-#define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
-#define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
-#define FTGMAC100_MACCR_RM_VLAN (1 << 4)
-#define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
-#define FTGMAC100_MACCR_LOOP_EN (1 << 6)
-#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
-#define FTGMAC100_MACCR_FULLDUP (1 << 8)
-#define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
-#define FTGMAC100_MACCR_CRC_APD (1 << 10)
-#define FTGMAC100_MACCR_RX_RUNT (1 << 12)
-#define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
-#define FTGMAC100_MACCR_RX_ALL (1 << 14)
-#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
-#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
-#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
-#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
-#define FTGMAC100_MACCR_FAST_MODE (1 << 19)
-#define FTGMAC100_MACCR_SW_RST (1 << 31)
-
-/*
- * PHY control register
- */
-#define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f
-#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f)
-#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16)
-#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21)
-#define FTGMAC100_PHYCR_MIIRD (1 << 26)
-#define FTGMAC100_PHYCR_MIIWR (1 << 27)
-
-/*
- * PHY data register
- */
-#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff)
-#define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff)
-
-/*
- * Transmit descriptor, aligned to 16 bytes
- */
-struct ftgmac100_txdes {
- unsigned int txdes0;
- unsigned int txdes1;
- unsigned int txdes2; /* not used by HW */
- unsigned int txdes3; /* TXBUF_BADR */
-} __attribute__ ((aligned(16)));
-
-#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
-#define FTGMAC100_TXDES0_EDOTR (1 << 15)
-#define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
-#define FTGMAC100_TXDES0_LTS (1 << 28)
-#define FTGMAC100_TXDES0_FTS (1 << 29)
-#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
-
-#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
-#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
-#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
-#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
-#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
-#define FTGMAC100_TXDES1_LLC (1 << 22)
-#define FTGMAC100_TXDES1_TX2FIC (1 << 30)
-#define FTGMAC100_TXDES1_TXIC (1 << 31)
-
-/*
- * Receive descriptor, aligned to 16 bytes
- */
-struct ftgmac100_rxdes {
- unsigned int rxdes0;
- unsigned int rxdes1;
- unsigned int rxdes2; /* not used by HW */
- unsigned int rxdes3; /* RXBUF_BADR */
-} __attribute__ ((aligned(16)));
-
-#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff)
-#define FTGMAC100_RXDES0_EDORR (1 << 15)
-#define FTGMAC100_RXDES0_MULTICAST (1 << 16)
-#define FTGMAC100_RXDES0_BROADCAST (1 << 17)
-#define FTGMAC100_RXDES0_RX_ERR (1 << 18)
-#define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
-#define FTGMAC100_RXDES0_FTL (1 << 20)
-#define FTGMAC100_RXDES0_RUNT (1 << 21)
-#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
-#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
-#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
-#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
-#define FTGMAC100_RXDES0_LRS (1 << 28)
-#define FTGMAC100_RXDES0_FRS (1 << 29)
-#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
-
-#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
-#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
-#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20)
-#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
-#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
-#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
-#define FTGMAC100_RXDES1_LLC (1 << 22)
-#define FTGMAC100_RXDES1_DF (1 << 23)
-#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
-#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
-#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
-#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
-
-#endif /* __FTGMAC100_H */
diff --git a/include/netdev.h b/include/netdev.h
index 55001625fb92..0a1a3a2d8da2 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -43,7 +43,6 @@ int ethoc_initialize(u8 dev_num, int base_addr);
int fec_initialize (bd_t *bis);
int fecmxc_initialize(bd_t *bis);
int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
-int ftgmac100_initialize(bd_t *bits);
int ftmac100_initialize(bd_t *bits);
int ftmac110_initialize(bd_t *bits);
void gt6426x_eth_initialize(bd_t *bis);
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
deleted file mode 100644
index c996f5f4a167..000000000000
--- a/drivers/net/ftgmac100.c
+++ /dev/null
@@ -1,582 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Faraday FTGMAC100 Ethernet
- *
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * (C) Copyright 2010 Andes Technology
- * Macpaul Lin <macpaul@andestech.com>
- */
-
-#include <config.h>
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <asm/dma-mapping.h>
-#include <linux/mii.h>
-
-#include "ftgmac100.h"
-
-#define ETH_ZLEN 60
-#define CFG_XBUF_SIZE 1536
-
-/* RBSR - hw default init value is also 0x640 */
-#define RBSR_DEFAULT_VALUE 0x640
-
-/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
-#define PKTBUFSTX 4 /* must be power of 2 */
-
-struct ftgmac100_data {
- ulong txdes_dma;
- struct ftgmac100_txdes *txdes;
- ulong rxdes_dma;
- struct ftgmac100_rxdes *rxdes;
- int tx_index;
- int rx_index;
- int phy_addr;
-};
-
-/*
- * struct mii_bus functions
- */
-static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr,
- int regnum)
-{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
- int phycr;
- int i;
-
- phycr = readl(&ftgmac100->phycr);
-
- /* preserve MDC cycle threshold */
- phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
-
- phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
- | FTGMAC100_PHYCR_REGAD(regnum)
- | FTGMAC100_PHYCR_MIIRD;
-
- writel(phycr, &ftgmac100->phycr);
-
- for (i = 0; i < 10; i++) {
- phycr = readl(&ftgmac100->phycr);
-
- if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
- int data;
-
- data = readl(&ftgmac100->phydata);
- return FTGMAC100_PHYDATA_MIIRDATA(data);
- }
-
- mdelay(10);
- }
-
- debug("mdio read timed out\n");
- return -1;
-}
-
-static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr,
- int regnum, u16 value)
-{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
- int phycr;
- int data;
- int i;
-
- phycr = readl(&ftgmac100->phycr);
-
- /* preserve MDC cycle threshold */
- phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
-
- phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
- | FTGMAC100_PHYCR_REGAD(regnum)
- | FTGMAC100_PHYCR_MIIWR;
-
- data = FTGMAC100_PHYDATA_MIIWDATA(value);
-
- writel(data, &ftgmac100->phydata);
- writel(phycr, &ftgmac100->phycr);
-
- for (i = 0; i < 10; i++) {
- phycr = readl(&ftgmac100->phycr);
-
- if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) {
- debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \
- "phy_addr: %x\n", phy_addr);
- return 0;
- }
-
- mdelay(1);
- }
-
- debug("mdio write timed out\n");
- return -1;
-}
-
-int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value)
-{
- *value = ftgmac100_mdiobus_read(dev , addr, reg);
-
- if (*value == -1)
- return -1;
-
- return 0;
-}
-
-int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value)
-{
- if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1)
- return -1;
-
- return 0;
-}
-
-static int ftgmac100_phy_reset(struct eth_device *dev)
-{
- struct ftgmac100_data *priv = dev->priv;
- int i;
- u16 status, adv;
-
- adv = ADVERTISE_CSMA | ADVERTISE_ALL;
-
- ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv);
-
- printf("%s: Starting autonegotiation...\n", dev->name);
-
- ftgmac100_phy_write(dev, priv->phy_addr,
- MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
-
- for (i = 0; i < 100000 / 100; i++) {
- ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
-
- if (status & BMSR_ANEGCOMPLETE)
- break;
- mdelay(1);
- }
-
- if (status & BMSR_ANEGCOMPLETE) {
- printf("%s: Autonegotiation complete\n", dev->name);
- } else {
- printf("%s: Autonegotiation timed out (status=0x%04x)\n",
- dev->name, status);
- return 0;
- }
-
- return 1;
-}
-
-static int ftgmac100_phy_init(struct eth_device *dev)
-{
- struct ftgmac100_data *priv = dev->priv;
-
- int phy_addr;
- u16 phy_id, status, adv, lpa, stat_ge;
- int media, speed, duplex;
- int i;
-
- /* Check if the PHY is up to snuff... */
- for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) {
-
- ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id);
-
- /*
- * When it is unable to found PHY,
- * the interface usually return 0xffff or 0x0000
- */
- if (phy_id != 0xffff && phy_id != 0x0) {
- printf("%s: found PHY@0x%02x\n",
- dev->name, phy_addr);
- priv->phy_addr = phy_addr;
- break;
- }
- }
-
- if (phy_id == 0xffff || phy_id == 0x0) {
- printf("%s: no PHY present\n", dev->name);
- return 0;
- }
-
- ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
-
- if (!(status & BMSR_LSTATUS)) {
- /* Try to re-negotiate if we don't have link already. */
- ftgmac100_phy_reset(dev);
-
- for (i = 0; i < 100000 / 100; i++) {
- ftgmac100_phy_read(dev, priv->phy_addr,
- MII_BMSR, &status);
- if (status & BMSR_LSTATUS)
- break;
- udelay(100);
- }
- }
-
- if (!(status & BMSR_LSTATUS)) {
- printf("%s: link down\n", dev->name);
- return 0;
- }
-
-#ifdef CONFIG_FTGMAC100_EGIGA
- /* 1000 Base-T Status Register */
- ftgmac100_phy_read(dev, priv->phy_addr,
- MII_STAT1000, &stat_ge);
-
- speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF)
- ? 1 : 0);
-
- duplex = ((stat_ge & LPA_1000FULL)
- ? 1 : 0);
-
- if (speed) { /* Speed is 1000 */
- printf("%s: link up, 1000bps %s-duplex\n",
- dev->name, duplex ? "full" : "half");
- return 0;
- }
-#endif
-
- ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv);
- ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa);
-
- media = mii_nway_result(lpa & adv);
- speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0);
- duplex = (media & ADVERTISE_FULL) ? 1 : 0;
-
- printf("%s: link up, %sMbps %s-duplex\n",
- dev->name, speed ? "100" : "10", duplex ? "full" : "half");
-
- return 1;
-}
-
-static int ftgmac100_update_link_speed(struct eth_device *dev)
-{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
- struct ftgmac100_data *priv = dev->priv;
-
- unsigned short stat_fe;
- unsigned short stat_ge;
- unsigned int maccr;
-
-#ifdef CONFIG_FTGMAC100_EGIGA
- /* 1000 Base-T Status Register */
- ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge);
-#endif
-
- ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe);
-
- if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */
- return 0;
-
- /* read MAC control register and clear related bits */
- maccr = readl(&ftgmac100->maccr) &
- ~(FTGMAC100_MACCR_GIGA_MODE |
- FTGMAC100_MACCR_FAST_MODE |
- FTGMAC100_MACCR_FULLDUP);
-
-#ifdef CONFIG_FTGMAC100_EGIGA
- if (stat_ge & LPA_1000FULL) {
- /* set gmac for 1000BaseTX and Full Duplex */
- maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP;
- }
-
- if (stat_ge & LPA_1000HALF) {
- /* set gmac for 1000BaseTX and Half Duplex */
- maccr |= FTGMAC100_MACCR_GIGA_MODE;
- }
-#endif
-
- if (stat_fe & BMSR_100FULL) {
- /* set MII for 100BaseTX and Full Duplex */
- maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP;
- }
-
- if (stat_fe & BMSR_10FULL) {
- /* set MII for 10BaseT and Full Duplex */
- maccr |= FTGMAC100_MACCR_FULLDUP;
- }
-
- if (stat_fe & BMSR_100HALF) {
- /* set MII for 100BaseTX and Half Duplex */
- maccr |= FTGMAC100_MACCR_FAST_MODE;
- }
-
- if (stat_fe & BMSR_10HALF) {
- /* set MII for 10BaseT and Half Duplex */
- /* we have already clear these bits, do nothing */
- ;
- }
-
- /* update MII config into maccr */
- writel(maccr, &ftgmac100->maccr);
-
- return 1;
-}
-
-/*
- * Reset MAC
- */
-static void ftgmac100_reset(struct eth_device *dev)
-{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
-
- debug("%s()\n", __func__);
-
- writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr);
-
- while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
- ;
-}
-
-/*
- * Set MAC address
- */
-static void ftgmac100_set_mac(struct eth_device *dev,
- const unsigned char *mac)
-{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
- unsigned int maddr = mac[0] << 8 | mac[1];
- unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
-
- debug("%s(%x %x)\n", __func__, maddr, laddr);
-
- writel(maddr, &ftgmac100->mac_madr);
- writel(laddr, &ftgmac100->mac_ladr);
-}
-
-static void ftgmac100_set_mac_from_env(struct eth_device *dev)
-{
- eth_env_get_enetaddr("ethaddr", dev->enetaddr);
-
- ftgmac100_set_mac(dev, dev->enetaddr);
-}
-
-/*
- * disable transmitter, receiver
- */
-static void ftgmac100_halt(struct eth_device *dev)
-{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
-
- debug("%s()\n", __func__);
-
- writel(0, &ftgmac100->maccr);
-}
-
-static int ftgmac100_init(struct eth_device *dev, bd_t *bd)
-{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
- struct ftgmac100_data *priv = dev->priv;
- struct ftgmac100_txdes *txdes;
- struct ftgmac100_rxdes *rxdes;
- unsigned int maccr;
- void *buf;
- int i;
-
- debug("%s()\n", __func__);
-
- if (!priv->txdes) {
- txdes = dma_alloc_coherent(
- sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
- if (!txdes)
- panic("ftgmac100: out of memory\n");
- memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
- priv->txdes = txdes;
- }
- txdes = priv->txdes;
-
- if (!priv->rxdes) {
- rxdes = dma_alloc_coherent(
- sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
- if (!rxdes)
- panic("ftgmac100: out of memory\n");
- memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
- priv->rxdes = rxdes;
- }
- rxdes = priv->rxdes;
-
- /* set the ethernet address */
- ftgmac100_set_mac_from_env(dev);
-
- /* disable all interrupts */
- writel(0, &ftgmac100->ier);
-
- /* initialize descriptors */
- priv->tx_index = 0;
- priv->rx_index = 0;
-
- txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
- rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
-
- for (i = 0; i < PKTBUFSTX; i++) {
- /* TXBUF_BADR */
- if (!txdes[i].txdes2) {
- buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
- if (!buf)
- panic("ftgmac100: out of memory\n");
- txdes[i].txdes3 = virt_to_phys(buf);
- txdes[i].txdes2 = (uint)buf;
- }
- txdes[i].txdes1 = 0;
- }
-
- for (i = 0; i < PKTBUFSRX; i++) {
- /* RXBUF_BADR */
- if (!rxdes[i].rxdes2) {
- buf = net_rx_packets[i];
- rxdes[i].rxdes3 = virt_to_phys(buf);
- rxdes[i].rxdes2 = (uint)buf;
- }
- rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
- }
-
- /* transmit ring */
- writel(priv->txdes_dma, &ftgmac100->txr_badr);
-
- /* receive ring */
- writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
-
- /* poll receive descriptor automatically */
- writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
-
- /* config receive buffer size register */
- writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr);
-
- /* enable transmitter, receiver */
- maccr = FTGMAC100_MACCR_TXMAC_EN |
- FTGMAC100_MACCR_RXMAC_EN |
- FTGMAC100_MACCR_TXDMA_EN |
- FTGMAC100_MACCR_RXDMA_EN |
- FTGMAC100_MACCR_CRC_APD |
- FTGMAC100_MACCR_FULLDUP |
- FTGMAC100_MACCR_RX_RUNT |
- FTGMAC100_MACCR_RX_BROADPKT;
-
- writel(maccr, &ftgmac100->maccr);
-
- if (!ftgmac100_phy_init(dev)) {
- if (!ftgmac100_update_link_speed(dev))
- return -1;
- }
-
- return 0;
-}
-
-/*
- * Get a data block via Ethernet
- */
-static int ftgmac100_recv(struct eth_device *dev)
-{
- struct ftgmac100_data *priv = dev->priv;
- struct ftgmac100_rxdes *curr_des;
- unsigned short rxlen;
-
- curr_des = &priv->rxdes[priv->rx_index];
-
- if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
- return -1;
-
- if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
- FTGMAC100_RXDES0_CRC_ERR |
- FTGMAC100_RXDES0_FTL |
- FTGMAC100_RXDES0_RUNT |
- FTGMAC100_RXDES0_RX_ODD_NB)) {
- return -1;
- }
-
- rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
-
- debug("%s(): RX buffer %d, %x received\n",
- __func__, priv->rx_index, rxlen);
-
- /* invalidate d-cache */
- dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE);
-
- /* pass the packet up to the protocol layers. */
- net_process_received_packet((void *)curr_des->rxdes2, rxlen);
-
- /* release buffer to DMA */
- curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
-
- priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
-
- return 0;
-}
-
-/*
- * Send a data block via Ethernet
- */
-static int ftgmac100_send(struct eth_device *dev, void *packet, int length)
-{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
- struct ftgmac100_data *priv = dev->priv;
- struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
-
- if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
- debug("%s(): no TX descriptor available\n", __func__);
- return -1;
- }
-
- debug("%s(%x, %x)\n", __func__, (int)packet, length);
-
- length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
-
- memcpy((void *)curr_des->txdes2, (void *)packet, length);
- dma_map_single((void *)curr_des->txdes2, length, DMA_TO_DEVICE);
-
- /* only one descriptor on TXBUF */
- curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
- curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
- FTGMAC100_TXDES0_LTS |
- FTGMAC100_TXDES0_TXBUF_SIZE(length) |
- FTGMAC100_TXDES0_TXDMA_OWN ;
-
- /* start transmit */
- writel(1, &ftgmac100->txpd);
-
- debug("%s(): packet sent\n", __func__);
-
- priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
-
- return 0;
-}
-
-int ftgmac100_initialize(bd_t *bd)
-{
- struct eth_device *dev;
- struct ftgmac100_data *priv;
-
- dev = malloc(sizeof *dev);
- if (!dev) {
- printf("%s(): failed to allocate dev\n", __func__);
- goto out;
- }
-
- /* Transmit and receive descriptors should align to 16 bytes */
- priv = memalign(16, sizeof(struct ftgmac100_data));
- if (!priv) {
- printf("%s(): failed to allocate priv\n", __func__);
- goto free_dev;
- }
-
- memset(dev, 0, sizeof(*dev));
- memset(priv, 0, sizeof(*priv));
-
- strcpy(dev->name, "FTGMAC100");
- dev->iobase = CONFIG_FTGMAC100_BASE;
- dev->init = ftgmac100_init;
- dev->halt = ftgmac100_halt;
- dev->send = ftgmac100_send;
- dev->recv = ftgmac100_recv;
- dev->priv = priv;
-
- eth_register(dev);
-
- ftgmac100_reset(dev);
-
- return 1;
-
-free_dev:
- free(dev);
-out:
- return 0;
-}
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 48a2878071d1..4ca4e15bdd71 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_EP93XX) += ep93xx_eth.o
obj-$(CONFIG_ETHOC) += ethoc.o
obj-$(CONFIG_FEC_MXC) += fec_mxc.o
obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
-obj-$(CONFIG_FTGMAC100) += ftgmac100.o
obj-$(CONFIG_FTMAC110) += ftmac110.o
obj-$(CONFIG_FTMAC100) += ftmac100.o
obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 2/7] net: Re-add support for the Faraday ftgmac100 controller
2018-10-01 8:53 [U-Boot] [PATCH v2 0/7] Support for the Faraday ftgmac100 controller Cédric Le Goater
2018-10-01 8:53 ` [U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver Cédric Le Goater
@ 2018-10-01 8:53 ` Cédric Le Goater
2018-10-01 8:53 ` [U-Boot] [PATCH v2 3/7] aspeed: ast2500: fix missing break in D2PLL clock enablement Cédric Le Goater
` (4 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Cédric Le Goater @ 2018-10-01 8:53 UTC (permalink / raw)
To: u-boot
The driver is based on the previous one and adds the same support for
the Faraday ftgmac100 controller with MAC and MDIO bus support for
RGMII/RMII modes.
Driver model support was added as well as some enhancements and fixes.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes since v1 :
- improved comments in the code
- changed the type of 'iobase' to 'struct ftgmac100 *' to remove the
casts in other routines.
- replaced the loop in the mdio methods by a call to readl_poll_timeout()
and fixed the returned value.
- added a flush cache on the arrays of TX and RX descriptors in
ftgmac100_start()
- fixed returned value of
- added a timer loop to catch transmit timeouts
- introduced a clk_bulk
- improved Kconfig description
drivers/net/ftgmac100.h | 242 ++++++++++++++++++
drivers/net/ftgmac100.c | 548 ++++++++++++++++++++++++++++++++++++++++
drivers/net/Kconfig | 26 ++
drivers/net/Makefile | 1 +
4 files changed, 817 insertions(+)
create mode 100644 drivers/net/ftgmac100.h
create mode 100644 drivers/net/ftgmac100.c
diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h
new file mode 100644
index 000000000000..9a789e4d5bee
--- /dev/null
+++ b/drivers/net/ftgmac100.h
@@ -0,0 +1,242 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Faraday FTGMAC100 Ethernet
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * (C) Copyright 2010 Andes Technology
+ * Macpaul Lin <macpaul@andestech.com>
+ */
+
+#ifndef __FTGMAC100_H
+#define __FTGMAC100_H
+
+/* The registers offset table of ftgmac100 */
+struct ftgmac100 {
+ unsigned int isr; /* 0x00 */
+ unsigned int ier; /* 0x04 */
+ unsigned int mac_madr; /* 0x08 */
+ unsigned int mac_ladr; /* 0x0c */
+ unsigned int maht0; /* 0x10 */
+ unsigned int maht1; /* 0x14 */
+ unsigned int txpd; /* 0x18 */
+ unsigned int rxpd; /* 0x1c */
+ unsigned int txr_badr; /* 0x20 */
+ unsigned int rxr_badr; /* 0x24 */
+ unsigned int hptxpd; /* 0x28 */
+ unsigned int hptxpd_badr; /* 0x2c */
+ unsigned int itc; /* 0x30 */
+ unsigned int aptc; /* 0x34 */
+ unsigned int dblac; /* 0x38 */
+ unsigned int dmafifos; /* 0x3c */
+ unsigned int revr; /* 0x40 */
+ unsigned int fear; /* 0x44 */
+ unsigned int tpafcr; /* 0x48 */
+ unsigned int rbsr; /* 0x4c */
+ unsigned int maccr; /* 0x50 */
+ unsigned int macsr; /* 0x54 */
+ unsigned int tm; /* 0x58 */
+ unsigned int resv1; /* 0x5c */ /* not defined in spec */
+ unsigned int phycr; /* 0x60 */
+ unsigned int phydata; /* 0x64 */
+ unsigned int fcr; /* 0x68 */
+ unsigned int bpr; /* 0x6c */
+ unsigned int wolcr; /* 0x70 */
+ unsigned int wolsr; /* 0x74 */
+ unsigned int wfcrc; /* 0x78 */
+ unsigned int resv2; /* 0x7c */ /* not defined in spec */
+ unsigned int wfbm1; /* 0x80 */
+ unsigned int wfbm2; /* 0x84 */
+ unsigned int wfbm3; /* 0x88 */
+ unsigned int wfbm4; /* 0x8c */
+ unsigned int nptxr_ptr; /* 0x90 */
+ unsigned int hptxr_ptr; /* 0x94 */
+ unsigned int rxr_ptr; /* 0x98 */
+ unsigned int resv3; /* 0x9c */ /* not defined in spec */
+ unsigned int tx; /* 0xa0 */
+ unsigned int tx_mcol_scol; /* 0xa4 */
+ unsigned int tx_ecol_fail; /* 0xa8 */
+ unsigned int tx_lcol_und; /* 0xac */
+ unsigned int rx; /* 0xb0 */
+ unsigned int rx_bc; /* 0xb4 */
+ unsigned int rx_mc; /* 0xb8 */
+ unsigned int rx_pf_aep; /* 0xbc */
+ unsigned int rx_runt; /* 0xc0 */
+ unsigned int rx_crcer_ftl; /* 0xc4 */
+ unsigned int rx_col_lost; /* 0xc8 */
+};
+
+/*
+ * Interrupt status register & interrupt enable register
+ */
+#define FTGMAC100_INT_RPKT_BUF BIT(0)
+#define FTGMAC100_INT_RPKT_FIFO BIT(1)
+#define FTGMAC100_INT_NO_RXBUF BIT(2)
+#define FTGMAC100_INT_RPKT_LOST BIT(3)
+#define FTGMAC100_INT_XPKT_ETH BIT(4)
+#define FTGMAC100_INT_XPKT_FIFO BIT(5)
+#define FTGMAC100_INT_NO_NPTXBUF BIT(6)
+#define FTGMAC100_INT_XPKT_LOST BIT(7)
+#define FTGMAC100_INT_AHB_ERR BIT(8)
+#define FTGMAC100_INT_PHYSTS_CHG BIT(9)
+#define FTGMAC100_INT_NO_HPTXBUF BIT(10)
+
+/*
+ * Interrupt timer control register
+ */
+#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
+#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
+#define FTGMAC100_ITC_RXINT_TIME_SEL BIT(7)
+#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
+#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
+#define FTGMAC100_ITC_TXINT_TIME_SEL BIT(15)
+
+/*
+ * Automatic polling timer control register
+ */
+#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
+#define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4)
+#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
+#define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12)
+
+/*
+ * DMA burst length and arbitration control register
+ */
+#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0)
+#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3)
+#define FTGMAC100_DBLAC_RX_THR_EN BIT(6)
+#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8)
+#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
+#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12)
+#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16)
+#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
+#define FTGMAC100_DBLAC_IFG_INC BIT(23)
+
+/*
+ * DMA FIFO status register
+ */
+#define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf)
+#define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf)
+#define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7)
+#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf)
+#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3)
+#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf)
+#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY BIT(26)
+#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY BIT(27)
+#define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28)
+#define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29)
+#define FTGMAC100_DMAFIFOS_RXDMA_REQ BIT(30)
+#define FTGMAC100_DMAFIFOS_TXDMA_REQ BIT(31)
+
+/*
+ * Receive buffer size register
+ */
+#define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff)
+
+/*
+ * MAC control register
+ */
+#define FTGMAC100_MACCR_TXDMA_EN BIT(0)
+#define FTGMAC100_MACCR_RXDMA_EN BIT(1)
+#define FTGMAC100_MACCR_TXMAC_EN BIT(2)
+#define FTGMAC100_MACCR_RXMAC_EN BIT(3)
+#define FTGMAC100_MACCR_RM_VLAN BIT(4)
+#define FTGMAC100_MACCR_HPTXR_EN BIT(5)
+#define FTGMAC100_MACCR_LOOP_EN BIT(6)
+#define FTGMAC100_MACCR_ENRX_IN_HALFTX BIT(7)
+#define FTGMAC100_MACCR_FULLDUP BIT(8)
+#define FTGMAC100_MACCR_GIGA_MODE BIT(9)
+#define FTGMAC100_MACCR_CRC_APD BIT(10)
+#define FTGMAC100_MACCR_RX_RUNT BIT(12)
+#define FTGMAC100_MACCR_JUMBO_LF BIT(13)
+#define FTGMAC100_MACCR_RX_ALL BIT(14)
+#define FTGMAC100_MACCR_HT_MULTI_EN BIT(15)
+#define FTGMAC100_MACCR_RX_MULTIPKT BIT(16)
+#define FTGMAC100_MACCR_RX_BROADPKT BIT(17)
+#define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18)
+#define FTGMAC100_MACCR_FAST_MODE BIT(19)
+#define FTGMAC100_MACCR_SW_RST BIT(31)
+
+/*
+ * PHY control register
+ */
+#define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f
+#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f)
+#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16)
+#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21)
+#define FTGMAC100_PHYCR_MIIRD BIT(26)
+#define FTGMAC100_PHYCR_MIIWR BIT(27)
+
+/*
+ * PHY data register
+ */
+#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff)
+#define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff)
+
+/*
+ * Transmit descriptor, aligned to 16 bytes
+ */
+struct ftgmac100_txdes {
+ unsigned int txdes0;
+ unsigned int txdes1;
+ unsigned int txdes2; /* not used by HW */
+ unsigned int txdes3; /* TXBUF_BADR */
+} __aligned(16);
+
+#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
+#define FTGMAC100_TXDES0_EDOTR BIT(15)
+#define FTGMAC100_TXDES0_CRC_ERR BIT(19)
+#define FTGMAC100_TXDES0_LTS BIT(28)
+#define FTGMAC100_TXDES0_FTS BIT(29)
+#define FTGMAC100_TXDES0_TXDMA_OWN BIT(31)
+
+#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
+#define FTGMAC100_TXDES1_INS_VLANTAG BIT(16)
+#define FTGMAC100_TXDES1_TCP_CHKSUM BIT(17)
+#define FTGMAC100_TXDES1_UDP_CHKSUM BIT(18)
+#define FTGMAC100_TXDES1_IP_CHKSUM BIT(19)
+#define FTGMAC100_TXDES1_LLC BIT(22)
+#define FTGMAC100_TXDES1_TX2FIC BIT(30)
+#define FTGMAC100_TXDES1_TXIC BIT(31)
+
+/*
+ * Receive descriptor, aligned to 16 bytes
+ */
+struct ftgmac100_rxdes {
+ unsigned int rxdes0;
+ unsigned int rxdes1;
+ unsigned int rxdes2; /* not used by HW */
+ unsigned int rxdes3; /* RXBUF_BADR */
+} __aligned(16);
+
+#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff)
+#define FTGMAC100_RXDES0_EDORR BIT(15)
+#define FTGMAC100_RXDES0_MULTICAST BIT(16)
+#define FTGMAC100_RXDES0_BROADCAST BIT(17)
+#define FTGMAC100_RXDES0_RX_ERR BIT(18)
+#define FTGMAC100_RXDES0_CRC_ERR BIT(19)
+#define FTGMAC100_RXDES0_FTL BIT(20)
+#define FTGMAC100_RXDES0_RUNT BIT(21)
+#define FTGMAC100_RXDES0_RX_ODD_NB BIT(22)
+#define FTGMAC100_RXDES0_FIFO_FULL BIT(23)
+#define FTGMAC100_RXDES0_PAUSE_OPCODE BIT(24)
+#define FTGMAC100_RXDES0_PAUSE_FRAME BIT(25)
+#define FTGMAC100_RXDES0_LRS BIT(28)
+#define FTGMAC100_RXDES0_FRS BIT(29)
+#define FTGMAC100_RXDES0_RXPKT_RDY BIT(31)
+
+#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
+#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
+#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20)
+#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
+#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
+#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
+#define FTGMAC100_RXDES1_LLC BIT(22)
+#define FTGMAC100_RXDES1_DF BIT(23)
+#define FTGMAC100_RXDES1_VLANTAG_AVAIL BIT(24)
+#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR BIT(25)
+#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26)
+#define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27)
+
+#endif /* __FTGMAC100_H */
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
new file mode 100644
index 000000000000..4596385d68cf
--- /dev/null
+++ b/drivers/net/ftgmac100.c
@@ -0,0 +1,548 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Faraday FTGMAC100 Ethernet
+ *
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * (C) Copyright 2010 Andes Technology
+ * Macpaul Lin <macpaul@andestech.com>
+ *
+ * Copyright (C) 2018, IBM Corporation.
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <miiphy.h>
+#include <net.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#include "ftgmac100.h"
+
+/* Min frame ethernet frame size without FCS */
+#define ETH_ZLEN 60
+
+/* Receive Buffer Size Register - HW default is 0x640 */
+#define FTGMAC100_RBSR_DEFAULT 0x640
+
+/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
+#define PKTBUFSTX 4
+
+/* Timeout for transmit */
+#define FTGMAC100_TX_TIMEOUT_MS 1000
+
+/* Timeout for a mdio read/write operation */
+#define FTGMAC100_MDIO_TIMEOUT_USEC 10000
+
+/*
+ * MDC clock cycle threshold
+ *
+ * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
+ */
+#define MDC_CYCTHR 0x34
+
+/**
+ * struct ftgmac100_data - private data for the FTGMAC100 driver
+ *
+ * @iobase: The base address of the hardware registers
+ * @txdes: The array of transmit descriptors
+ * @rxdes: The array of receive descriptors
+ * @tx_index: Transmit descriptor index in @txdes
+ * @rx_index: Receive descriptor index in @rxdes
+ * @phyaddr: The PHY interface address to use
+ * @phydev: The PHY device backing the MAC
+ * @bus: The mdio bus
+ * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
+ * @max_speed: Maximum speed of Ethernet connection supported by MAC
+ * @clks: The bulk of clocks assigned to the device in the DT
+ */
+struct ftgmac100_data {
+ struct ftgmac100 *iobase;
+
+ struct ftgmac100_txdes txdes[PKTBUFSTX];
+ struct ftgmac100_rxdes rxdes[PKTBUFSRX];
+ int tx_index;
+ int rx_index;
+
+ u32 phyaddr;
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+ u32 phy_mode;
+ u32 max_speed;
+
+ struct clk_bulk clks;
+};
+
+static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
+ int reg_addr)
+{
+ struct ftgmac100_data *priv = bus->priv;
+ struct ftgmac100 *ftgmac100 = priv->iobase;
+ int phycr;
+ int data;
+ int ret;
+
+ phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
+ FTGMAC100_PHYCR_PHYAD(phy_addr) |
+ FTGMAC100_PHYCR_REGAD(reg_addr) |
+ FTGMAC100_PHYCR_MIIRD;
+ writel(phycr, &ftgmac100->phycr);
+
+ ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
+ !(phycr & FTGMAC100_PHYCR_MIIRD),
+ FTGMAC100_MDIO_TIMEOUT_USEC);
+ if (ret) {
+ pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
+ priv->phydev->dev->name, phy_addr, reg_addr);
+ return ret;
+ }
+
+ data = readl(&ftgmac100->phydata);
+
+ return FTGMAC100_PHYDATA_MIIRDATA(data);
+}
+
+static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
+ int reg_addr, u16 value)
+{
+ struct ftgmac100_data *priv = bus->priv;
+ struct ftgmac100 *ftgmac100 = priv->iobase;
+ int phycr;
+ int data;
+ int ret;
+
+ phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
+ FTGMAC100_PHYCR_PHYAD(phy_addr) |
+ FTGMAC100_PHYCR_REGAD(reg_addr) |
+ FTGMAC100_PHYCR_MIIWR;
+ data = FTGMAC100_PHYDATA_MIIWDATA(value);
+
+ writel(data, &ftgmac100->phydata);
+ writel(phycr, &ftgmac100->phycr);
+
+ ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
+ !(phycr & FTGMAC100_PHYCR_MIIWR),
+ FTGMAC100_MDIO_TIMEOUT_USEC);
+ if (ret) {
+ pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
+ priv->phydev->dev->name, phy_addr, reg_addr);
+ }
+
+ return ret;
+}
+
+static int ftgmac100_mdio_init(struct ftgmac100_data *priv, int dev_id)
+{
+ struct mii_dev *bus;
+ int ret;
+
+ bus = mdio_alloc();
+ if (!bus)
+ return -ENOMEM;
+
+ bus->read = ftgmac100_mdio_read;
+ bus->write = ftgmac100_mdio_write;
+ bus->priv = priv;
+
+ ret = mdio_register_seq(bus, dev_id);
+ if (ret) {
+ free(bus);
+ return ret;
+ }
+
+ priv->bus = bus;
+
+ return 0;
+}
+
+static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
+{
+ struct ftgmac100 *ftgmac100 = priv->iobase;
+ struct phy_device *phydev = priv->phydev;
+ u32 maccr;
+
+ if (!phydev->link) {
+ dev_err(phydev->dev, "No link\n");
+ return -EREMOTEIO;
+ }
+
+ /* read MAC control register and clear related bits */
+ maccr = readl(&ftgmac100->maccr) &
+ ~(FTGMAC100_MACCR_GIGA_MODE |
+ FTGMAC100_MACCR_FAST_MODE |
+ FTGMAC100_MACCR_FULLDUP);
+
+ if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
+ maccr |= FTGMAC100_MACCR_GIGA_MODE;
+
+ if (phydev->speed == 100)
+ maccr |= FTGMAC100_MACCR_FAST_MODE;
+
+ if (phydev->duplex)
+ maccr |= FTGMAC100_MACCR_FULLDUP;
+
+ /* update MII config into maccr */
+ writel(maccr, &ftgmac100->maccr);
+
+ return 0;
+}
+
+static int ftgmac100_phy_init(struct ftgmac100_data *priv, void *dev)
+{
+ struct phy_device *phydev;
+ int ret;
+
+ phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->phy_mode);
+ if (!phydev)
+ return -ENODEV;
+
+ phydev->supported &= PHY_GBIT_FEATURES;
+ if (priv->max_speed) {
+ ret = phy_set_supported(phydev, priv->max_speed);
+ if (ret)
+ return ret;
+ }
+ phydev->advertising = phydev->supported;
+ priv->phydev = phydev;
+ phy_config(phydev);
+
+ return 0;
+}
+
+static void ftgmac100_reset(struct ftgmac100_data *priv)
+{
+ struct ftgmac100 *ftgmac100 = priv->iobase;
+
+ setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
+
+ while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
+ ;
+}
+
+static int ftgmac100_set_mac(struct ftgmac100_data *priv,
+ const unsigned char *mac)
+{
+ struct ftgmac100 *ftgmac100 = priv->iobase;
+ unsigned int maddr = mac[0] << 8 | mac[1];
+ unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
+
+ writel(maddr, &ftgmac100->mac_madr);
+ writel(laddr, &ftgmac100->mac_ladr);
+
+ return 0;
+}
+
+static void ftgmac100_stop(struct udevice *dev)
+{
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ struct ftgmac100 *ftgmac100 = priv->iobase;
+
+ writel(0, &ftgmac100->maccr);
+
+ phy_shutdown(priv->phydev);
+}
+
+static int ftgmac100_start(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ struct ftgmac100 *ftgmac100 = priv->iobase;
+ struct phy_device *phydev = priv->phydev;
+ unsigned int maccr;
+ ulong start, end;
+ int ret;
+ int i;
+
+ ftgmac100_reset(priv);
+
+ /* set the ethernet address */
+ ftgmac100_set_mac(priv, plat->enetaddr);
+
+ /* disable all interrupts */
+ writel(0, &ftgmac100->ier);
+
+ /* initialize descriptor tables */
+ priv->tx_index = 0;
+ priv->rx_index = 0;
+
+ for (i = 0; i < PKTBUFSTX; i++) {
+ priv->txdes[i].txdes3 = 0;
+ priv->txdes[i].txdes0 = 0;
+ }
+ priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
+
+ start = (ulong)&priv->txdes[0];
+ end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
+ flush_dcache_range(start, end);
+
+ for (i = 0; i < PKTBUFSRX; i++) {
+ priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
+ priv->rxdes[i].rxdes0 = 0;
+ }
+ priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
+
+ start = (ulong)&priv->rxdes[0];
+ end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
+ flush_dcache_range(start, end);
+
+ /* transmit ring */
+ writel((u32)priv->txdes, &ftgmac100->txr_badr);
+
+ /* receive ring */
+ writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
+
+ /* poll receive descriptor automatically */
+ writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
+
+ /* config receive buffer size register */
+ writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
+
+ /* enable transmitter, receiver */
+ maccr = FTGMAC100_MACCR_TXMAC_EN |
+ FTGMAC100_MACCR_RXMAC_EN |
+ FTGMAC100_MACCR_TXDMA_EN |
+ FTGMAC100_MACCR_RXDMA_EN |
+ FTGMAC100_MACCR_CRC_APD |
+ FTGMAC100_MACCR_FULLDUP |
+ FTGMAC100_MACCR_RX_RUNT |
+ FTGMAC100_MACCR_RX_BROADPKT;
+
+ writel(maccr, &ftgmac100->maccr);
+
+ ret = phy_startup(phydev);
+ if (ret) {
+ dev_err(phydev->dev, "Could not start PHY\n");
+ return ret;
+ }
+
+ ret = ftgmac100_phy_adjust_link(priv);
+ if (ret) {
+ dev_err(phydev->dev, "Could not adjust link\n");
+ return ret;
+ }
+
+ printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
+ phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
+
+ return 0;
+}
+
+static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
+ ulong des_start = (ulong)curr_des;
+ ulong des_end = des_start +
+ roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
+
+ /* Release buffer to DMA and flush descriptor */
+ curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
+ flush_dcache_range(des_start, des_end);
+
+ /* Move to next descriptor */
+ priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
+
+ return 0;
+}
+
+static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
+ int length;
+ ulong des_start = (ulong)curr_des;
+ ulong des_end = des_start +
+ roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
+ ulong data_start = curr_des->rxdes3;
+ ulong data_end;
+
+ invalidate_dcache_range(des_start, des_end);
+
+ if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
+ return -EAGAIN;
+
+ if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
+ FTGMAC100_RXDES0_CRC_ERR |
+ FTGMAC100_RXDES0_FTL |
+ FTGMAC100_RXDES0_RUNT |
+ FTGMAC100_RXDES0_RX_ODD_NB)) {
+ return -EAGAIN;
+ }
+
+ length = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
+
+ /* Invalidate received data */
+ data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(data_start, data_end);
+ *packetp = (uchar *)data_start;
+
+ return length;
+}
+
+static int ftgmac100_send(struct udevice *dev, void *packet, int length)
+{
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ struct ftgmac100 *ftgmac100 = priv->iobase;
+ struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
+ ulong des_start = (ulong)curr_des;
+ ulong des_end = des_start +
+ roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
+ ulong data_start;
+ ulong data_end;
+ ulong start;
+
+ invalidate_dcache_range(des_start, des_end);
+
+ if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
+ dev_err(dev, "no TX descriptor available\n");
+ return -EPERM;
+ }
+
+ debug("%s(%x, %x)\n", __func__, (int)packet, length);
+
+ length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
+
+ curr_des->txdes3 = (unsigned int)packet;
+
+ /* Flush data to be sent */
+ data_start = curr_des->txdes3;
+ data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
+ flush_dcache_range(data_start, data_end);
+
+ /* Only one segment on TXBUF */
+ curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
+ curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
+ FTGMAC100_TXDES0_LTS |
+ FTGMAC100_TXDES0_TXBUF_SIZE(length) |
+ FTGMAC100_TXDES0_TXDMA_OWN;
+
+ /* Flush modified buffer descriptor */
+ flush_dcache_range(des_start, des_end);
+
+ /* Start transmit */
+ writel(1, &ftgmac100->txpd);
+
+ /* Wait until packet is transmitted */
+ start = get_timer(0);
+ while (get_timer(start) < FTGMAC100_TX_TIMEOUT_MS) {
+ invalidate_dcache_range(des_start, des_end);
+ if (!(curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN))
+ break;
+ udelay(10);
+ }
+
+ if (get_timer(start) >= FTGMAC100_TX_TIMEOUT_MS) {
+ dev_err(dev, "transmit timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ debug("%s(): packet sent\n", __func__);
+
+ /* Move to next descriptor */
+ priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
+
+ return 0;
+}
+
+static int ftgmac100_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+
+ return ftgmac100_set_mac(priv, pdata->enetaddr);
+}
+
+static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ const char *phy_mode;
+
+ pdata->iobase = devfdt_get_addr(dev);
+ pdata->phy_interface = -1;
+ phy_mode = dev_read_string(dev, "phy-mode");
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
+ return -EINVAL;
+ }
+
+ pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
+
+ return clk_get_bulk(dev, &priv->clks);
+}
+
+static int ftgmac100_probe(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->iobase = (struct ftgmac100 *)pdata->iobase;
+ priv->phy_mode = pdata->phy_interface;
+ priv->max_speed = pdata->max_speed;
+ priv->phyaddr = 0;
+
+ ret = clk_enable_bulk(&priv->clks);
+ if (ret)
+ goto out;
+
+ ret = ftgmac100_mdio_init(priv, dev->seq);
+ if (ret) {
+ dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
+ goto out;
+ }
+
+ ret = ftgmac100_phy_init(priv, dev);
+ if (ret) {
+ dev_err(dev, "Failed to initialize PHY: %d\n", ret);
+ goto out;
+ }
+
+out:
+ if (ret)
+ clk_release_bulk(&priv->clks);
+
+ return ret;
+}
+
+static int ftgmac100_remove(struct udevice *dev)
+{
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+
+ free(priv->phydev);
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+ clk_release_bulk(&priv->clks);
+
+ return 0;
+}
+
+static const struct eth_ops ftgmac100_ops = {
+ .start = ftgmac100_start,
+ .send = ftgmac100_send,
+ .recv = ftgmac100_recv,
+ .stop = ftgmac100_stop,
+ .free_pkt = ftgmac100_free_pkt,
+ .write_hwaddr = ftgmac100_write_hwaddr,
+};
+
+static const struct udevice_id ftgmac100_ids[] = {
+ { .compatible = "faraday,ftgmac100" },
+ { }
+};
+
+U_BOOT_DRIVER(ftgmac100) = {
+ .name = "ftgmac100",
+ .id = UCLASS_ETH,
+ .of_match = ftgmac100_ids,
+ .ofdata_to_platdata = ftgmac100_ofdata_to_platdata,
+ .probe = ftgmac100_probe,
+ .remove = ftgmac100_remove,
+ .ops = &ftgmac100_ops,
+ .priv_auto_alloc_size = sizeof(struct ftgmac100_data),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 5441da47d13e..3efdc5dc2fae 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -186,6 +186,32 @@ config FTMAC100
help
This MAC is present in Andestech SoCs.
+config FTGMAC100
+ bool "Ftgmac100 Ethernet Support"
+ depends on DM_ETH
+ select PHYLIB
+ help
+ This driver supports the Faraday's FTGMAC100 Gigabit SoC
+ Ethernet controller that can be found on Aspeed SoCs (which
+ include NCSI).
+
+ It is fully compliant with IEEE 802.3 specification for
+ 10/100 Mbps Ethernet and IEEE 802.3z specification for 1000
+ Mbps Ethernet and includes Reduced Media Independent
+ Interface (RMII) and Reduced Gigabit Media Independent
+ Interface (RGMII) interfaces. It adopts an AHB bus interface
+ and integrates a link list DMA engine with direct M-Bus
+ accesses for transmitting and receiving packets. It has
+ independent TX/RX fifos, supports half and full duplex (1000
+ Mbps mode only supports full duplex), flow control for full
+ duplex and backpressure for half duplex.
+
+ The FTGMAC100 also implements IP, TCP, UDP checksum offloads
+ and supports IEEE 802.1Q VLAN tag insertion and removal. It
+ offers high-priority transmit queue for QoS and CoS
+ applications.
+
+
config MVGBE
bool "Marvell Orion5x/Kirkwood network interface support"
depends on KIRKWOOD || ORION5X
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 4ca4e15bdd71..48a2878071d1 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_EP93XX) += ep93xx_eth.o
obj-$(CONFIG_ETHOC) += ethoc.o
obj-$(CONFIG_FEC_MXC) += fec_mxc.o
obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
+obj-$(CONFIG_FTGMAC100) += ftgmac100.o
obj-$(CONFIG_FTMAC110) += ftmac110.o
obj-$(CONFIG_FTMAC100) += ftmac100.o
obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 3/7] aspeed: ast2500: fix missing break in D2PLL clock enablement
2018-10-01 8:53 [U-Boot] [PATCH v2 0/7] Support for the Faraday ftgmac100 controller Cédric Le Goater
2018-10-01 8:53 ` [U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver Cédric Le Goater
2018-10-01 8:53 ` [U-Boot] [PATCH v2 2/7] net: Re-add support for the Faraday ftgmac100 controller Cédric Le Goater
@ 2018-10-01 8:53 ` Cédric Le Goater
2018-10-01 8:53 ` [U-Boot] [PATCH v2 4/7] net: ftgmac100: Add support for the Aspeed SoC Cédric Le Goater
` (3 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Cédric Le Goater @ 2018-10-01 8:53 UTC (permalink / raw)
To: u-boot
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
drivers/clk/aspeed/clk_ast2500.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 526470051c5d..2182320f607f 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -411,6 +411,7 @@ static int ast2500_clk_enable(struct clk *clk)
break;
case PLL_D2PLL:
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
+ break;
default:
return -ENOENT;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 4/7] net: ftgmac100: Add support for the Aspeed SoC
2018-10-01 8:53 [U-Boot] [PATCH v2 0/7] Support for the Faraday ftgmac100 controller Cédric Le Goater
` (2 preceding siblings ...)
2018-10-01 8:53 ` [U-Boot] [PATCH v2 3/7] aspeed: ast2500: fix missing break in D2PLL clock enablement Cédric Le Goater
@ 2018-10-01 8:53 ` Cédric Le Goater
2018-10-02 11:22 ` Simon Glass
2018-10-01 8:53 ` [U-Boot] [PATCH v2 5/7] aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level Cédric Le Goater
` (2 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Cédric Le Goater @ 2018-10-01 8:53 UTC (permalink / raw)
To: u-boot
The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have
some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits).
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
Changes since v1:
- introduced a udevice_id .data model
- dropped is_aspeed bool
- dropped MDIO interface setting for Aspeed SoC. The default is
correct.
- removed the clcoks which are now handled automatically in the
ftgmac100 driver
drivers/net/ftgmac100.c | 29 +++++++++++++++++++++++++----
configs/evb-ast2500_defconfig | 8 ++++++++
2 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 4596385d68cf..e48e30c54269 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -42,6 +42,14 @@
*/
#define MDC_CYCTHR 0x34
+/*
+ * ftgmac100 model variants
+ */
+enum ftgmac100_model {
+ FTGMAC100_MODEL_FARADAY,
+ FTGMAC100_MODEL_ASPEED,
+};
+
/**
* struct ftgmac100_data - private data for the FTGMAC100 driver
*
@@ -72,6 +80,10 @@ struct ftgmac100_data {
u32 max_speed;
struct clk_bulk clks;
+
+ /* End of TX/TX ring buffer bits. Depend on model */
+ u32 rxdes0_edorr_mask;
+ u32 txdes0_edotr_mask;
};
static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
@@ -270,7 +282,7 @@ static int ftgmac100_start(struct udevice *dev)
priv->txdes[i].txdes3 = 0;
priv->txdes[i].txdes0 = 0;
}
- priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
+ priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
start = (ulong)&priv->txdes[0];
end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
@@ -280,7 +292,7 @@ static int ftgmac100_start(struct udevice *dev)
priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
priv->rxdes[i].rxdes0 = 0;
}
- priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
+ priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
start = (ulong)&priv->rxdes[0];
end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
@@ -411,7 +423,7 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length)
flush_dcache_range(data_start, data_end);
/* Only one segment on TXBUF */
- curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
+ curr_des->txdes0 &= priv->txdes0_edotr_mask;
curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
FTGMAC100_TXDES0_LTS |
FTGMAC100_TXDES0_TXBUF_SIZE(length) |
@@ -471,6 +483,14 @@ static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
+ if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
+ priv->rxdes0_edorr_mask = BIT(30);
+ priv->txdes0_edotr_mask = BIT(30);
+ } else {
+ priv->rxdes0_edorr_mask = BIT(15);
+ priv->txdes0_edotr_mask = BIT(15);
+ }
+
return clk_get_bulk(dev, &priv->clks);
}
@@ -530,7 +550,8 @@ static const struct eth_ops ftgmac100_ops = {
};
static const struct udevice_id ftgmac100_ids[] = {
- { .compatible = "faraday,ftgmac100" },
+ { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
+ { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
{ }
};
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 88230f4a12db..32581f5ada54 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -25,3 +25,11 @@ CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_WDT=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY=y
+CONFIG_DM_ETH=y
+CONFIG_FTGMAC100=y
+CONFIG_PHY_REALTEK=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 5/7] aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level
2018-10-01 8:53 [U-Boot] [PATCH v2 0/7] Support for the Faraday ftgmac100 controller Cédric Le Goater
` (3 preceding siblings ...)
2018-10-01 8:53 ` [U-Boot] [PATCH v2 4/7] net: ftgmac100: Add support for the Aspeed SoC Cédric Le Goater
@ 2018-10-01 8:53 ` Cédric Le Goater
2018-10-02 11:22 ` Simon Glass
2018-10-01 8:53 ` [U-Boot] [PATCH v2 6/7] aspeed: Activate ethernet devices on the ast2500 Eval Board Cédric Le Goater
2018-10-01 8:53 ` [U-Boot] [PATCH v2 7/7] aspeed: ast2500: fix D2-PLL clock setting in RGMII mode Cédric Le Goater
6 siblings, 1 reply; 18+ messages in thread
From: Cédric Le Goater @ 2018-10-01 8:53 UTC (permalink / raw)
To: u-boot
This is a large update of the AST2500 SoC DTS file bringing it to the
level of commit 927c2fc2db19 :
Author: Joel Stanley <joel@jms.id.au>
Date: Sat Jun 2 01:18:53 2018 -0700
ARM: dts: aspeed: Fix hwrng register address
There are some differences on the compatibility property names. scu,
reset and clock drivers are also different.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/dts/ast2500.dtsi | 1995 ++++++++++++++++++++++---------------
1 file changed, 1198 insertions(+), 797 deletions(-)
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index 7e0ad3a41ac5..283b695d1b0e 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -11,6 +11,29 @@
#size-cells = <1>;
interrupt-parent = <&vic>;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i2c12;
+ i2c13 = &i2c13;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &vuart;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -22,12 +45,80 @@
};
};
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0>;
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ fmc: flash-controller at 1e620000 {
+ reg = < 0x1e620000 0xc4
+ 0x20000000 0x10000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2500-fmc";
+ status = "disabled";
+ interrupts = <19>;
+ flash at 0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash at 1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash at 2 {
+ reg = < 2 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ };
+
+ spi1: flash-controller at 1e630000 {
+ reg = < 0x1e630000 0xc4
+ 0x30000000 0x08000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2500-spi";
+ status = "disabled";
+ flash at 0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash at 1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ };
+
+ spi2: flash-controller at 1e631000 {
+ reg = < 0x1e631000 0xc4
+ 0x38000000 0x08000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2500-spi";
+ status = "disabled";
+ flash at 0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash at 1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ };
+
vic: interrupt-controller at 1e6c0080 {
compatible = "aspeed,ast2400-vic";
interrupt-controller;
@@ -37,18 +128,38 @@
};
mac0: ethernet at 1e660000 {
- compatible = "faraday,ftgmac100";
+ compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
interrupts = <2>;
- no-hw-checksum;
status = "disabled";
};
mac1: ethernet at 1e680000 {
- compatible = "faraday,ftgmac100";
+ compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e680000 0x180>;
interrupts = <3>;
- no-hw-checksum;
+ status = "disabled";
+ };
+
+ ehci0: usb at 1e6a1000 {
+ compatible = "aspeed,ast2500-ehci", "generic-ehci";
+ reg = <0x1e6a1000 0x100>;
+ interrupts = <5>;
+ status = "disabled";
+ };
+
+ ehci1: usb at 1e6a3000 {
+ compatible = "aspeed,ast2500-ehci", "generic-ehci";
+ reg = <0x1e6a3000 0x100>;
+ interrupts = <13>;
+ status = "disabled";
+ };
+
+ uhci: usb at 1e6b0000 {
+ compatible = "aspeed,ast2500-uhci", "generic-uhci";
+ reg = <0x1e6b0000 0x100>;
+ interrupts = <14>;
+ #ports = <2>;
status = "disabled";
};
@@ -58,996 +169,1286 @@
#size-cells = <1>;
ranges;
- clk_clkin: clk_clkin at 1e6e2070 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-clkin-clock";
- reg = <0x1e6e2070 0x04>;
- };
-
syscon: syscon at 1e6e2000 {
compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,g5-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
- pinctrl_acpi_default: acpi_default {
- function = "ACPI";
- groups = "ACPI";
- };
-
- pinctrl_adc0_default: adc0_default {
- function = "ADC0";
- groups = "ADC0";
- };
+ };
+ };
- pinctrl_adc1_default: adc1_default {
- function = "ADC1";
- groups = "ADC1";
- };
+ clk_clkin: clk_clkin at 1e6e2070 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-clkin-clock";
+ reg = <0x1e6e2070 0x04>;
+ };
- pinctrl_adc10_default: adc10_default {
- function = "ADC10";
- groups = "ADC10";
- };
+ clk_hpll: clk_hpll at 1e6e2024 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-hpll-clock";
+ reg = <0x1e6e2024 0x4>;
+ clocks = <&clk_clkin>;
+ };
- pinctrl_adc11_default: adc11_default {
- function = "ADC11";
- groups = "ADC11";
- };
+ clk_ahb: clk_ahb at 1e6e2070 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-ahb-clock";
+ reg = <0x1e6e2070 0x4>;
+ clocks = <&clk_hpll>;
+ };
- pinctrl_adc12_default: adc12_default {
- function = "ADC12";
- groups = "ADC12";
- };
+ clk_apb: clk_apb at 1e6e2008 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-apb-clock";
+ reg = <0x1e6e2008 0x4>;
+ clocks = <&clk_hpll>;
+ };
- pinctrl_adc13_default: adc13_default {
- function = "ADC13";
- groups = "ADC13";
- };
+ clk_uart: clk_uart at 1e6e2008 {
+ #clock-cells = <0>;
+ compatible = "aspeed,uart-clock";
+ reg = <0x1e6e202c 0x4>;
+ };
- pinctrl_adc14_default: adc14_default {
- function = "ADC14";
- groups = "ADC14";
- };
+ rng: hwrng at 1e6e2078 {
+ compatible = "timeriomem_rng";
+ reg = <0x1e6e2078 0x4>;
+ period = <1>;
+ quality = <100>;
+ };
- pinctrl_adc15_default: adc15_default {
- function = "ADC15";
- groups = "ADC15";
- };
+ gfx: display at 1e6e6000 {
+ compatible = "aspeed,ast2500-gfx", "syscon";
+ reg = <0x1e6e6000 0x1000>;
+ reg-io-width = <4>;
+ };
- pinctrl_adc2_default: adc2_default {
- function = "ADC2";
- groups = "ADC2";
- };
+ adc: adc at 1e6e9000 {
+ compatible = "aspeed,ast2500-adc";
+ reg = <0x1e6e9000 0xb0>;
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
- pinctrl_adc3_default: adc3_default {
- function = "ADC3";
- groups = "ADC3";
- };
+ sram at 1e720000 {
+ compatible = "mmio-sram";
+ reg = <0x1e720000 0x9000>; // 36K
+ };
- pinctrl_adc4_default: adc4_default {
- function = "ADC4";
- groups = "ADC4";
- };
+ gpio: gpio at 1e780000 {
+ #gpio-cells = <2>;
+ gpio-controller;
+ compatible = "aspeed,ast2500-gpio";
+ reg = <0x1e780000 0x1000>;
+ interrupts = <20>;
+ gpio-ranges = <&pinctrl 0 0 220>;
+ interrupt-controller;
+ };
- pinctrl_adc5_default: adc5_default {
- function = "ADC5";
- groups = "ADC5";
- };
+ timer: timer at 1e782000 {
+ /* This timer is a Faraday FTTMR010 derivative */
+ compatible = "aspeed,ast2400-timer";
+ reg = <0x1e782000 0x90>;
+ // The moxart_timer driver registers only one
+ // interrupt and assumes it's for timer 1
+ //interrupts = <16 17 18 35 36 37 38 39>;
+ interrupts = <16>;
+ clocks = <&clk_apb>;
+ };
- pinctrl_adc6_default: adc6_default {
- function = "ADC6";
- groups = "ADC6";
- };
+ uart1: serial at 1e783000 {
+ compatible = "ns16550a";
+ reg = <0x1e783000 0x20>;
+ reg-shift = <2>;
+ interrupts = <9>;
+ clocks = <&clk_uart>;
+ no-loopback-test;
+ status = "disabled";
+ };
- pinctrl_adc7_default: adc7_default {
- function = "ADC7";
- groups = "ADC7";
- };
+ uart5: serial at 1e784000 {
+ compatible = "ns16550a";
+ reg = <0x1e784000 0x20>;
+ reg-shift = <2>;
+ interrupts = <10>;
+ clocks = <&clk_uart>;
+ current-speed = <38400>;
+ no-loopback-test;
+ status = "disabled";
+ };
- pinctrl_adc8_default: adc8_default {
- function = "ADC8";
- groups = "ADC8";
- };
+ wdt1: watchdog at 1e785000 {
+ compatible = "aspeed,wdt";
+ reg = <0x1e785000 0x1c>;
+ interrupts = <27>;
+ };
- pinctrl_adc9_default: adc9_default {
- function = "ADC9";
- groups = "ADC9";
- };
+ wdt2: watchdog at 1e785020 {
+ compatible = "aspeed,wdt";
+ reg = <0x1e785020 0x1c>;
+ interrupts = <27>;
+ status = "disabled";
+ };
- pinctrl_bmcint_default: bmcint_default {
- function = "BMCINT";
- groups = "BMCINT";
- };
+ wdt3: watchdog at 1e785040 {
+ compatible = "aspeed,wdt";
+ reg = <0x1e785040 0x1c>;
+ status = "disabled";
+ };
- pinctrl_ddcclk_default: ddcclk_default {
- function = "DDCCLK";
- groups = "DDCCLK";
- };
+ pwm_tacho: pwm-tacho-controller at 1e786000 {
+ compatible = "aspeed,ast2500-pwm-tacho";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1e786000 0x1000>;
+ status = "disabled";
+ };
- pinctrl_ddcdat_default: ddcdat_default {
- function = "DDCDAT";
- groups = "DDCDAT";
- };
+ vuart: serial at 1e787000 {
+ compatible = "aspeed,ast2500-vuart";
+ reg = <0x1e787000 0x40>;
+ reg-shift = <2>;
+ interrupts = <8>;
+ no-loopback-test;
+ status = "disabled";
+ };
- pinctrl_espi_default: espi_default {
- function = "ESPI";
- groups = "ESPI";
- };
+ lpc: lpc at 1e789000 {
+ compatible = "aspeed,ast2500-lpc", "simple-mfd";
+ reg = <0x1e789000 0x1000>;
- pinctrl_fwspics1_default: fwspics1_default {
- function = "FWSPICS1";
- groups = "FWSPICS1";
- };
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
- pinctrl_fwspics2_default: fwspics2_default {
- function = "FWSPICS2";
- groups = "FWSPICS2";
- };
+ lpc_bmc: lpc-bmc at 0 {
+ compatible = "aspeed,ast2500-lpc-bmc";
+ reg = <0x0 0x80>;
+ };
- pinctrl_gpid0_default: gpid0_default {
- function = "GPID0";
- groups = "GPID0";
- };
+ lpc_host: lpc-host at 80 {
+ compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
+ reg = <0x80 0x1e0>;
+ reg-io-width = <4>;
- pinctrl_gpid2_default: gpid2_default {
- function = "GPID2";
- groups = "GPID2";
- };
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80 0x1e0>;
- pinctrl_gpid4_default: gpid4_default {
- function = "GPID4";
- groups = "GPID4";
+ lpc_ctrl: lpc-ctrl at 0 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x0 0x80>;
+ status = "disabled";
};
- pinctrl_gpid6_default: gpid6_default {
- function = "GPID6";
- groups = "GPID6";
+ lpc_snoop: lpc-snoop at 0 {
+ compatible = "aspeed,ast2500-lpc-snoop";
+ reg = <0x0 0x80>;
+ interrupts = <8>;
+ status = "disabled";
};
- pinctrl_gpie0_default: gpie0_default {
- function = "GPIE0";
- groups = "GPIE0";
+ lhc: lhc at 20 {
+ compatible = "aspeed,ast2500-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
};
- pinctrl_gpie2_default: gpie2_default {
- function = "GPIE2";
- groups = "GPIE2";
+ lpc_reset: reset-controller at 18 {
+ compatible = "aspeed,ast2500-lpc-reset";
+ reg = <0x18 0x4>;
+ #reset-cells = <1>;
};
- pinctrl_gpie4_default: gpie4_default {
- function = "GPIE4";
- groups = "GPIE4";
+ ibt: ibt at c0 {
+ compatible = "aspeed,ast2500-ibt-bmc";
+ reg = <0xc0 0x18>;
+ interrupts = <8>;
+ status = "disabled";
};
+ };
+ };
- pinctrl_gpie6_default: gpie6_default {
- function = "GPIE6";
- groups = "GPIE6";
- };
+ uart2: serial at 1e78d000 {
+ compatible = "ns16550a";
+ reg = <0x1e78d000 0x20>;
+ reg-shift = <2>;
+ interrupts = <32>;
+ clocks = <&clk_uart>;
+ no-loopback-test;
+ status = "disabled";
+ };
- pinctrl_i2c10_default: i2c10_default {
- function = "I2C10";
- groups = "I2C10";
- };
+ uart3: serial at 1e78e000 {
+ compatible = "ns16550a";
+ reg = <0x1e78e000 0x20>;
+ reg-shift = <2>;
+ interrupts = <33>;
+ clocks = <&clk_uart>;
+ no-loopback-test;
+ status = "disabled";
+ };
- pinctrl_i2c11_default: i2c11_default {
- function = "I2C11";
- groups = "I2C11";
- };
+ uart4: serial at 1e78f000 {
+ compatible = "ns16550a";
+ reg = <0x1e78f000 0x20>;
+ reg-shift = <2>;
+ interrupts = <34>;
+ clocks = <&clk_uart>;
+ no-loopback-test;
+ status = "disabled";
+ };
- pinctrl_i2c12_default: i2c12_default {
- function = "I2C12";
- groups = "I2C12";
- };
+ i2c: i2c at 1e78a000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1e78a000 0x1000>;
+ };
+ };
+ };
+};
- pinctrl_i2c13_default: i2c13_default {
- function = "I2C13";
- groups = "I2C13";
- };
+&i2c {
+ i2c_ic: interrupt-controller at 0 {
+ #interrupt-cells = <1>;
+ compatible = "aspeed,ast2500-i2c-ic";
+ reg = <0x0 0x40>;
+ interrupts = <12>;
+ interrupt-controller;
+ };
- pinctrl_i2c14_default: i2c14_default {
- function = "I2C14";
- groups = "I2C14";
- };
+ i2c0: i2c-bus at 40 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x40 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <0>;
+ interrupt-parent = <&i2c_ic>;
+ status = "disabled";
+ /* Does not need pinctrl properties */
+ };
- pinctrl_i2c3_default: i2c3_default {
- function = "I2C3";
- groups = "I2C3";
- };
+ i2c1: i2c-bus at 80 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x80 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <1>;
+ interrupt-parent = <&i2c_ic>;
+ status = "disabled";
+ /* Does not need pinctrl properties */
+ };
- pinctrl_i2c4_default: i2c4_default {
- function = "I2C4";
- groups = "I2C4";
- };
+ i2c2: i2c-bus at c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0xc0 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <2>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_default>;
+ status = "disabled";
+ };
- pinctrl_i2c5_default: i2c5_default {
- function = "I2C5";
- groups = "I2C5";
- };
+ i2c3: i2c-bus at 100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x100 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <3>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_default>;
+ status = "disabled";
+ };
- pinctrl_i2c6_default: i2c6_default {
- function = "I2C6";
- groups = "I2C6";
- };
+ i2c4: i2c-bus at 140 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x140 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <4>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c5_default>;
+ status = "disabled";
+ };
- pinctrl_i2c7_default: i2c7_default {
- function = "I2C7";
- groups = "I2C7";
- };
+ i2c5: i2c-bus at 180 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x180 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <5>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c6_default>;
+ status = "disabled";
+ };
- pinctrl_i2c8_default: i2c8_default {
- function = "I2C8";
- groups = "I2C8";
- };
+ i2c6: i2c-bus at 1c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1c0 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <6>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c7_default>;
+ status = "disabled";
+ };
- pinctrl_i2c9_default: i2c9_default {
- function = "I2C9";
- groups = "I2C9";
- };
+ i2c7: i2c-bus at 300 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x300 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <7>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c8_default>;
+ status = "disabled";
+ };
- pinctrl_lad0_default: lad0_default {
- function = "LAD0";
- groups = "LAD0";
- };
+ i2c8: i2c-bus at 340 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x340 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <8>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c9_default>;
+ status = "disabled";
+ };
- pinctrl_lad1_default: lad1_default {
- function = "LAD1";
- groups = "LAD1";
- };
+ i2c9: i2c-bus at 380 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x380 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <9>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c10_default>;
+ status = "disabled";
+ };
- pinctrl_lad2_default: lad2_default {
- function = "LAD2";
- groups = "LAD2";
- };
+ i2c10: i2c-bus at 3c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x3c0 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <10>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c11_default>;
+ status = "disabled";
+ };
- pinctrl_lad3_default: lad3_default {
- function = "LAD3";
- groups = "LAD3";
- };
+ i2c11: i2c-bus at 400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x400 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <11>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c12_default>;
+ status = "disabled";
+ };
- pinctrl_lclk_default: lclk_default {
- function = "LCLK";
- groups = "LCLK";
- };
+ i2c12: i2c-bus at 440 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x440 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <12>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c13_default>;
+ status = "disabled";
+ };
- pinctrl_lframe_default: lframe_default {
- function = "LFRAME";
- groups = "LFRAME";
- };
+ i2c13: i2c-bus at 480 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x480 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <13>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c14_default>;
+ status = "disabled";
+ };
+};
- pinctrl_lpchc_default: lpchc_default {
- function = "LPCHC";
- groups = "LPCHC";
- };
+&pinctrl {
+ pinctrl_acpi_default: acpi_default {
+ function = "ACPI";
+ groups = "ACPI";
+ };
- pinctrl_lpcpd_default: lpcpd_default {
- function = "LPCPD";
- groups = "LPCPD";
- };
+ pinctrl_adc0_default: adc0_default {
+ function = "ADC0";
+ groups = "ADC0";
+ };
- pinctrl_lpcplus_default: lpcplus_default {
- function = "LPCPLUS";
- groups = "LPCPLUS";
- };
+ pinctrl_adc1_default: adc1_default {
+ function = "ADC1";
+ groups = "ADC1";
+ };
- pinctrl_lpcpme_default: lpcpme_default {
- function = "LPCPME";
- groups = "LPCPME";
- };
+ pinctrl_adc10_default: adc10_default {
+ function = "ADC10";
+ groups = "ADC10";
+ };
- pinctrl_lpcrst_default: lpcrst_default {
- function = "LPCRST";
- groups = "LPCRST";
- };
+ pinctrl_adc11_default: adc11_default {
+ function = "ADC11";
+ groups = "ADC11";
+ };
- pinctrl_lpcsmi_default: lpcsmi_default {
- function = "LPCSMI";
- groups = "LPCSMI";
- };
+ pinctrl_adc12_default: adc12_default {
+ function = "ADC12";
+ groups = "ADC12";
+ };
- pinctrl_lsirq_default: lsirq_default {
- function = "LSIRQ";
- groups = "LSIRQ";
- };
+ pinctrl_adc13_default: adc13_default {
+ function = "ADC13";
+ groups = "ADC13";
+ };
- pinctrl_mac1link_default: mac1link_default {
- function = "MAC1LINK";
- groups = "MAC1LINK";
- };
+ pinctrl_adc14_default: adc14_default {
+ function = "ADC14";
+ groups = "ADC14";
+ };
- pinctrl_mac2link_default: mac2link_default {
- function = "MAC2LINK";
- groups = "MAC2LINK";
- };
+ pinctrl_adc15_default: adc15_default {
+ function = "ADC15";
+ groups = "ADC15";
+ };
- pinctrl_mdio1_default: mdio1_default {
- function = "MDIO1";
- groups = "MDIO1";
- };
+ pinctrl_adc2_default: adc2_default {
+ function = "ADC2";
+ groups = "ADC2";
+ };
- pinctrl_mdio2_default: mdio2_default {
- function = "MDIO2";
- groups = "MDIO2";
- };
+ pinctrl_adc3_default: adc3_default {
+ function = "ADC3";
+ groups = "ADC3";
+ };
- pinctrl_ncts1_default: ncts1_default {
- function = "NCTS1";
- groups = "NCTS1";
- };
+ pinctrl_adc4_default: adc4_default {
+ function = "ADC4";
+ groups = "ADC4";
+ };
- pinctrl_ncts2_default: ncts2_default {
- function = "NCTS2";
- groups = "NCTS2";
- };
+ pinctrl_adc5_default: adc5_default {
+ function = "ADC5";
+ groups = "ADC5";
+ };
- pinctrl_ncts3_default: ncts3_default {
- function = "NCTS3";
- groups = "NCTS3";
- };
+ pinctrl_adc6_default: adc6_default {
+ function = "ADC6";
+ groups = "ADC6";
+ };
- pinctrl_ncts4_default: ncts4_default {
- function = "NCTS4";
- groups = "NCTS4";
- };
+ pinctrl_adc7_default: adc7_default {
+ function = "ADC7";
+ groups = "ADC7";
+ };
- pinctrl_ndcd1_default: ndcd1_default {
- function = "NDCD1";
- groups = "NDCD1";
- };
+ pinctrl_adc8_default: adc8_default {
+ function = "ADC8";
+ groups = "ADC8";
+ };
- pinctrl_ndcd2_default: ndcd2_default {
- function = "NDCD2";
- groups = "NDCD2";
- };
+ pinctrl_adc9_default: adc9_default {
+ function = "ADC9";
+ groups = "ADC9";
+ };
- pinctrl_ndcd3_default: ndcd3_default {
- function = "NDCD3";
- groups = "NDCD3";
- };
+ pinctrl_bmcint_default: bmcint_default {
+ function = "BMCINT";
+ groups = "BMCINT";
+ };
- pinctrl_ndcd4_default: ndcd4_default {
- function = "NDCD4";
- groups = "NDCD4";
- };
+ pinctrl_ddcclk_default: ddcclk_default {
+ function = "DDCCLK";
+ groups = "DDCCLK";
+ };
- pinctrl_ndsr1_default: ndsr1_default {
- function = "NDSR1";
- groups = "NDSR1";
- };
+ pinctrl_ddcdat_default: ddcdat_default {
+ function = "DDCDAT";
+ groups = "DDCDAT";
+ };
- pinctrl_ndsr2_default: ndsr2_default {
- function = "NDSR2";
- groups = "NDSR2";
- };
+ pinctrl_espi_default: espi_default {
+ function = "ESPI";
+ groups = "ESPI";
+ };
- pinctrl_ndsr3_default: ndsr3_default {
- function = "NDSR3";
- groups = "NDSR3";
- };
+ pinctrl_fwspics1_default: fwspics1_default {
+ function = "FWSPICS1";
+ groups = "FWSPICS1";
+ };
- pinctrl_ndsr4_default: ndsr4_default {
- function = "NDSR4";
- groups = "NDSR4";
- };
+ pinctrl_fwspics2_default: fwspics2_default {
+ function = "FWSPICS2";
+ groups = "FWSPICS2";
+ };
- pinctrl_ndtr1_default: ndtr1_default {
- function = "NDTR1";
- groups = "NDTR1";
- };
+ pinctrl_gpid0_default: gpid0_default {
+ function = "GPID0";
+ groups = "GPID0";
+ };
- pinctrl_ndtr2_default: ndtr2_default {
- function = "NDTR2";
- groups = "NDTR2";
- };
+ pinctrl_gpid2_default: gpid2_default {
+ function = "GPID2";
+ groups = "GPID2";
+ };
- pinctrl_ndtr3_default: ndtr3_default {
- function = "NDTR3";
- groups = "NDTR3";
- };
+ pinctrl_gpid4_default: gpid4_default {
+ function = "GPID4";
+ groups = "GPID4";
+ };
- pinctrl_ndtr4_default: ndtr4_default {
- function = "NDTR4";
- groups = "NDTR4";
- };
+ pinctrl_gpid6_default: gpid6_default {
+ function = "GPID6";
+ groups = "GPID6";
+ };
- pinctrl_nri1_default: nri1_default {
- function = "NRI1";
- groups = "NRI1";
- };
+ pinctrl_gpie0_default: gpie0_default {
+ function = "GPIE0";
+ groups = "GPIE0";
+ };
- pinctrl_nri2_default: nri2_default {
- function = "NRI2";
- groups = "NRI2";
- };
+ pinctrl_gpie2_default: gpie2_default {
+ function = "GPIE2";
+ groups = "GPIE2";
+ };
- pinctrl_nri3_default: nri3_default {
- function = "NRI3";
- groups = "NRI3";
- };
+ pinctrl_gpie4_default: gpie4_default {
+ function = "GPIE4";
+ groups = "GPIE4";
+ };
- pinctrl_nri4_default: nri4_default {
- function = "NRI4";
- groups = "NRI4";
- };
+ pinctrl_gpie6_default: gpie6_default {
+ function = "GPIE6";
+ groups = "GPIE6";
+ };
- pinctrl_nrts1_default: nrts1_default {
- function = "NRTS1";
- groups = "NRTS1";
- };
+ pinctrl_i2c10_default: i2c10_default {
+ function = "I2C10";
+ groups = "I2C10";
+ };
- pinctrl_nrts2_default: nrts2_default {
- function = "NRTS2";
- groups = "NRTS2";
- };
+ pinctrl_i2c11_default: i2c11_default {
+ function = "I2C11";
+ groups = "I2C11";
+ };
- pinctrl_nrts3_default: nrts3_default {
- function = "NRTS3";
- groups = "NRTS3";
- };
+ pinctrl_i2c12_default: i2c12_default {
+ function = "I2C12";
+ groups = "I2C12";
+ };
- pinctrl_nrts4_default: nrts4_default {
- function = "NRTS4";
- groups = "NRTS4";
- };
+ pinctrl_i2c13_default: i2c13_default {
+ function = "I2C13";
+ groups = "I2C13";
+ };
- pinctrl_oscclk_default: oscclk_default {
- function = "OSCCLK";
- groups = "OSCCLK";
- };
+ pinctrl_i2c14_default: i2c14_default {
+ function = "I2C14";
+ groups = "I2C14";
+ };
- pinctrl_pewake_default: pewake_default {
- function = "PEWAKE";
- groups = "PEWAKE";
- };
+ pinctrl_i2c3_default: i2c3_default {
+ function = "I2C3";
+ groups = "I2C3";
+ };
- pinctrl_pnor_default: pnor_default {
- function = "PNOR";
- groups = "PNOR";
- };
+ pinctrl_i2c4_default: i2c4_default {
+ function = "I2C4";
+ groups = "I2C4";
+ };
- pinctrl_pwm0_default: pwm0_default {
- function = "PWM0";
- groups = "PWM0";
- };
+ pinctrl_i2c5_default: i2c5_default {
+ function = "I2C5";
+ groups = "I2C5";
+ };
- pinctrl_pwm1_default: pwm1_default {
- function = "PWM1";
- groups = "PWM1";
- };
+ pinctrl_i2c6_default: i2c6_default {
+ function = "I2C6";
+ groups = "I2C6";
+ };
- pinctrl_pwm2_default: pwm2_default {
- function = "PWM2";
- groups = "PWM2";
- };
+ pinctrl_i2c7_default: i2c7_default {
+ function = "I2C7";
+ groups = "I2C7";
+ };
- pinctrl_pwm3_default: pwm3_default {
- function = "PWM3";
- groups = "PWM3";
- };
+ pinctrl_i2c8_default: i2c8_default {
+ function = "I2C8";
+ groups = "I2C8";
+ };
- pinctrl_pwm4_default: pwm4_default {
- function = "PWM4";
- groups = "PWM4";
- };
+ pinctrl_i2c9_default: i2c9_default {
+ function = "I2C9";
+ groups = "I2C9";
+ };
- pinctrl_pwm5_default: pwm5_default {
- function = "PWM5";
- groups = "PWM5";
- };
+ pinctrl_lad0_default: lad0_default {
+ function = "LAD0";
+ groups = "LAD0";
+ };
- pinctrl_pwm6_default: pwm6_default {
- function = "PWM6";
- groups = "PWM6";
- };
+ pinctrl_lad1_default: lad1_default {
+ function = "LAD1";
+ groups = "LAD1";
+ };
- pinctrl_pwm7_default: pwm7_default {
- function = "PWM7";
- groups = "PWM7";
- };
+ pinctrl_lad2_default: lad2_default {
+ function = "LAD2";
+ groups = "LAD2";
+ };
- pinctrl_rgmii1_default: rgmii1_default {
- function = "RGMII1";
- groups = "RGMII1";
- };
+ pinctrl_lad3_default: lad3_default {
+ function = "LAD3";
+ groups = "LAD3";
+ };
- pinctrl_rgmii2_default: rgmii2_default {
- function = "RGMII2";
- groups = "RGMII2";
- };
+ pinctrl_lclk_default: lclk_default {
+ function = "LCLK";
+ groups = "LCLK";
+ };
- pinctrl_rmii1_default: rmii1_default {
- function = "RMII1";
- groups = "RMII1";
- };
+ pinctrl_lframe_default: lframe_default {
+ function = "LFRAME";
+ groups = "LFRAME";
+ };
- pinctrl_rmii2_default: rmii2_default {
- function = "RMII2";
- groups = "RMII2";
- };
+ pinctrl_lpchc_default: lpchc_default {
+ function = "LPCHC";
+ groups = "LPCHC";
+ };
- pinctrl_rxd1_default: rxd1_default {
- function = "RXD1";
- groups = "RXD1";
- };
+ pinctrl_lpcpd_default: lpcpd_default {
+ function = "LPCPD";
+ groups = "LPCPD";
+ };
- pinctrl_rxd2_default: rxd2_default {
- function = "RXD2";
- groups = "RXD2";
- };
+ pinctrl_lpcplus_default: lpcplus_default {
+ function = "LPCPLUS";
+ groups = "LPCPLUS";
+ };
- pinctrl_rxd3_default: rxd3_default {
- function = "RXD3";
- groups = "RXD3";
- };
+ pinctrl_lpcpme_default: lpcpme_default {
+ function = "LPCPME";
+ groups = "LPCPME";
+ };
- pinctrl_rxd4_default: rxd4_default {
- function = "RXD4";
- groups = "RXD4";
- };
+ pinctrl_lpcrst_default: lpcrst_default {
+ function = "LPCRST";
+ groups = "LPCRST";
+ };
- pinctrl_salt1_default: salt1_default {
- function = "SALT1";
- groups = "SALT1";
- };
+ pinctrl_lpcsmi_default: lpcsmi_default {
+ function = "LPCSMI";
+ groups = "LPCSMI";
+ };
- pinctrl_salt10_default: salt10_default {
- function = "SALT10";
- groups = "SALT10";
- };
+ pinctrl_lsirq_default: lsirq_default {
+ function = "LSIRQ";
+ groups = "LSIRQ";
+ };
- pinctrl_salt11_default: salt11_default {
- function = "SALT11";
- groups = "SALT11";
- };
+ pinctrl_mac1link_default: mac1link_default {
+ function = "MAC1LINK";
+ groups = "MAC1LINK";
+ };
- pinctrl_salt12_default: salt12_default {
- function = "SALT12";
- groups = "SALT12";
- };
+ pinctrl_mac2link_default: mac2link_default {
+ function = "MAC2LINK";
+ groups = "MAC2LINK";
+ };
- pinctrl_salt13_default: salt13_default {
- function = "SALT13";
- groups = "SALT13";
- };
+ pinctrl_mdio1_default: mdio1_default {
+ function = "MDIO1";
+ groups = "MDIO1";
+ };
- pinctrl_salt14_default: salt14_default {
- function = "SALT14";
- groups = "SALT14";
- };
+ pinctrl_mdio2_default: mdio2_default {
+ function = "MDIO2";
+ groups = "MDIO2";
+ };
- pinctrl_salt2_default: salt2_default {
- function = "SALT2";
- groups = "SALT2";
- };
+ pinctrl_ncts1_default: ncts1_default {
+ function = "NCTS1";
+ groups = "NCTS1";
+ };
- pinctrl_salt3_default: salt3_default {
- function = "SALT3";
- groups = "SALT3";
- };
+ pinctrl_ncts2_default: ncts2_default {
+ function = "NCTS2";
+ groups = "NCTS2";
+ };
- pinctrl_salt4_default: salt4_default {
- function = "SALT4";
- groups = "SALT4";
- };
+ pinctrl_ncts3_default: ncts3_default {
+ function = "NCTS3";
+ groups = "NCTS3";
+ };
- pinctrl_salt5_default: salt5_default {
- function = "SALT5";
- groups = "SALT5";
- };
+ pinctrl_ncts4_default: ncts4_default {
+ function = "NCTS4";
+ groups = "NCTS4";
+ };
- pinctrl_salt6_default: salt6_default {
- function = "SALT6";
- groups = "SALT6";
- };
+ pinctrl_ndcd1_default: ndcd1_default {
+ function = "NDCD1";
+ groups = "NDCD1";
+ };
- pinctrl_salt7_default: salt7_default {
- function = "SALT7";
- groups = "SALT7";
- };
+ pinctrl_ndcd2_default: ndcd2_default {
+ function = "NDCD2";
+ groups = "NDCD2";
+ };
- pinctrl_salt8_default: salt8_default {
- function = "SALT8";
- groups = "SALT8";
- };
+ pinctrl_ndcd3_default: ndcd3_default {
+ function = "NDCD3";
+ groups = "NDCD3";
+ };
- pinctrl_salt9_default: salt9_default {
- function = "SALT9";
- groups = "SALT9";
- };
+ pinctrl_ndcd4_default: ndcd4_default {
+ function = "NDCD4";
+ groups = "NDCD4";
+ };
- pinctrl_scl1_default: scl1_default {
- function = "SCL1";
- groups = "SCL1";
- };
+ pinctrl_ndsr1_default: ndsr1_default {
+ function = "NDSR1";
+ groups = "NDSR1";
+ };
- pinctrl_scl2_default: scl2_default {
- function = "SCL2";
- groups = "SCL2";
- };
+ pinctrl_ndsr2_default: ndsr2_default {
+ function = "NDSR2";
+ groups = "NDSR2";
+ };
- pinctrl_sd1_default: sd1_default {
- function = "SD1";
- groups = "SD1";
- };
+ pinctrl_ndsr3_default: ndsr3_default {
+ function = "NDSR3";
+ groups = "NDSR3";
+ };
- pinctrl_sd2_default: sd2_default {
- function = "SD2";
- groups = "SD2";
- };
+ pinctrl_ndsr4_default: ndsr4_default {
+ function = "NDSR4";
+ groups = "NDSR4";
+ };
- pinctrl_sda1_default: sda1_default {
- function = "SDA1";
- groups = "SDA1";
- };
+ pinctrl_ndtr1_default: ndtr1_default {
+ function = "NDTR1";
+ groups = "NDTR1";
+ };
- pinctrl_sda2_default: sda2_default {
- function = "SDA2";
- groups = "SDA2";
- };
+ pinctrl_ndtr2_default: ndtr2_default {
+ function = "NDTR2";
+ groups = "NDTR2";
+ };
- pinctrl_sgps1_default: sgps1_default {
- function = "SGPS1";
- groups = "SGPS1";
- };
+ pinctrl_ndtr3_default: ndtr3_default {
+ function = "NDTR3";
+ groups = "NDTR3";
+ };
- pinctrl_sgps2_default: sgps2_default {
- function = "SGPS2";
- groups = "SGPS2";
- };
+ pinctrl_ndtr4_default: ndtr4_default {
+ function = "NDTR4";
+ groups = "NDTR4";
+ };
- pinctrl_sioonctrl_default: sioonctrl_default {
- function = "SIOONCTRL";
- groups = "SIOONCTRL";
- };
+ pinctrl_nri1_default: nri1_default {
+ function = "NRI1";
+ groups = "NRI1";
+ };
- pinctrl_siopbi_default: siopbi_default {
- function = "SIOPBI";
- groups = "SIOPBI";
- };
+ pinctrl_nri2_default: nri2_default {
+ function = "NRI2";
+ groups = "NRI2";
+ };
- pinctrl_siopbo_default: siopbo_default {
- function = "SIOPBO";
- groups = "SIOPBO";
- };
+ pinctrl_nri3_default: nri3_default {
+ function = "NRI3";
+ groups = "NRI3";
+ };
- pinctrl_siopwreq_default: siopwreq_default {
- function = "SIOPWREQ";
- groups = "SIOPWREQ";
- };
+ pinctrl_nri4_default: nri4_default {
+ function = "NRI4";
+ groups = "NRI4";
+ };
- pinctrl_siopwrgd_default: siopwrgd_default {
- function = "SIOPWRGD";
- groups = "SIOPWRGD";
- };
+ pinctrl_nrts1_default: nrts1_default {
+ function = "NRTS1";
+ groups = "NRTS1";
+ };
- pinctrl_sios3_default: sios3_default {
- function = "SIOS3";
- groups = "SIOS3";
- };
+ pinctrl_nrts2_default: nrts2_default {
+ function = "NRTS2";
+ groups = "NRTS2";
+ };
- pinctrl_sios5_default: sios5_default {
- function = "SIOS5";
- groups = "SIOS5";
- };
+ pinctrl_nrts3_default: nrts3_default {
+ function = "NRTS3";
+ groups = "NRTS3";
+ };
- pinctrl_siosci_default: siosci_default {
- function = "SIOSCI";
- groups = "SIOSCI";
- };
+ pinctrl_nrts4_default: nrts4_default {
+ function = "NRTS4";
+ groups = "NRTS4";
+ };
- pinctrl_spi1_default: spi1_default {
- function = "SPI1";
- groups = "SPI1";
- };
+ pinctrl_oscclk_default: oscclk_default {
+ function = "OSCCLK";
+ groups = "OSCCLK";
+ };
- pinctrl_spi1cs1_default: spi1cs1_default {
- function = "SPI1CS1";
- groups = "SPI1CS1";
- };
+ pinctrl_pewake_default: pewake_default {
+ function = "PEWAKE";
+ groups = "PEWAKE";
+ };
- pinctrl_spi1debug_default: spi1debug_default {
- function = "SPI1DEBUG";
- groups = "SPI1DEBUG";
- };
+ pinctrl_pnor_default: pnor_default {
+ function = "PNOR";
+ groups = "PNOR";
+ };
- pinctrl_spi1passthru_default: spi1passthru_default {
- function = "SPI1PASSTHRU";
- groups = "SPI1PASSTHRU";
- };
+ pinctrl_pwm0_default: pwm0_default {
+ function = "PWM0";
+ groups = "PWM0";
+ };
- pinctrl_spi2ck_default: spi2ck_default {
- function = "SPI2CK";
- groups = "SPI2CK";
- };
+ pinctrl_pwm1_default: pwm1_default {
+ function = "PWM1";
+ groups = "PWM1";
+ };
- pinctrl_spi2cs0_default: spi2cs0_default {
- function = "SPI2CS0";
- groups = "SPI2CS0";
- };
+ pinctrl_pwm2_default: pwm2_default {
+ function = "PWM2";
+ groups = "PWM2";
+ };
- pinctrl_spi2cs1_default: spi2cs1_default {
- function = "SPI2CS1";
- groups = "SPI2CS1";
- };
+ pinctrl_pwm3_default: pwm3_default {
+ function = "PWM3";
+ groups = "PWM3";
+ };
- pinctrl_spi2miso_default: spi2miso_default {
- function = "SPI2MISO";
- groups = "SPI2MISO";
- };
+ pinctrl_pwm4_default: pwm4_default {
+ function = "PWM4";
+ groups = "PWM4";
+ };
- pinctrl_spi2mosi_default: spi2mosi_default {
- function = "SPI2MOSI";
- groups = "SPI2MOSI";
- };
+ pinctrl_pwm5_default: pwm5_default {
+ function = "PWM5";
+ groups = "PWM5";
+ };
- pinctrl_timer3_default: timer3_default {
- function = "TIMER3";
- groups = "TIMER3";
- };
+ pinctrl_pwm6_default: pwm6_default {
+ function = "PWM6";
+ groups = "PWM6";
+ };
- pinctrl_timer4_default: timer4_default {
- function = "TIMER4";
- groups = "TIMER4";
- };
+ pinctrl_pwm7_default: pwm7_default {
+ function = "PWM7";
+ groups = "PWM7";
+ };
- pinctrl_timer5_default: timer5_default {
- function = "TIMER5";
- groups = "TIMER5";
- };
+ pinctrl_rgmii1_default: rgmii1_default {
+ function = "RGMII1";
+ groups = "RGMII1";
+ };
- pinctrl_timer6_default: timer6_default {
- function = "TIMER6";
- groups = "TIMER6";
- };
+ pinctrl_rgmii2_default: rgmii2_default {
+ function = "RGMII2";
+ groups = "RGMII2";
+ };
- pinctrl_timer7_default: timer7_default {
- function = "TIMER7";
- groups = "TIMER7";
- };
+ pinctrl_rmii1_default: rmii1_default {
+ function = "RMII1";
+ groups = "RMII1";
+ };
- pinctrl_timer8_default: timer8_default {
- function = "TIMER8";
- groups = "TIMER8";
- };
+ pinctrl_rmii2_default: rmii2_default {
+ function = "RMII2";
+ groups = "RMII2";
+ };
- pinctrl_txd1_default: txd1_default {
- function = "TXD1";
- groups = "TXD1";
- };
+ pinctrl_rxd1_default: rxd1_default {
+ function = "RXD1";
+ groups = "RXD1";
+ };
- pinctrl_txd2_default: txd2_default {
- function = "TXD2";
- groups = "TXD2";
- };
+ pinctrl_rxd2_default: rxd2_default {
+ function = "RXD2";
+ groups = "RXD2";
+ };
- pinctrl_txd3_default: txd3_default {
- function = "TXD3";
- groups = "TXD3";
- };
+ pinctrl_rxd3_default: rxd3_default {
+ function = "RXD3";
+ groups = "RXD3";
+ };
- pinctrl_txd4_default: txd4_default {
- function = "TXD4";
- groups = "TXD4";
- };
+ pinctrl_rxd4_default: rxd4_default {
+ function = "RXD4";
+ groups = "RXD4";
+ };
- pinctrl_uart6_default: uart6_default {
- function = "UART6";
- groups = "UART6";
- };
+ pinctrl_salt1_default: salt1_default {
+ function = "SALT1";
+ groups = "SALT1";
+ };
- pinctrl_usbcki_default: usbcki_default {
- function = "USBCKI";
- groups = "USBCKI";
- };
+ pinctrl_salt10_default: salt10_default {
+ function = "SALT10";
+ groups = "SALT10";
+ };
- pinctrl_vgabiosrom_default: vgabiosrom_default {
- function = "VGABIOSROM";
- groups = "VGABIOSROM";
- };
+ pinctrl_salt11_default: salt11_default {
+ function = "SALT11";
+ groups = "SALT11";
+ };
- pinctrl_vgahs_default: vgahs_default {
- function = "VGAHS";
- groups = "VGAHS";
- };
+ pinctrl_salt12_default: salt12_default {
+ function = "SALT12";
+ groups = "SALT12";
+ };
- pinctrl_vgavs_default: vgavs_default {
- function = "VGAVS";
- groups = "VGAVS";
- };
+ pinctrl_salt13_default: salt13_default {
+ function = "SALT13";
+ groups = "SALT13";
+ };
- pinctrl_vpi24_default: vpi24_default {
- function = "VPI24";
- groups = "VPI24";
- };
+ pinctrl_salt14_default: salt14_default {
+ function = "SALT14";
+ groups = "SALT14";
+ };
- pinctrl_vpo_default: vpo_default {
- function = "VPO";
- groups = "VPO";
- };
+ pinctrl_salt2_default: salt2_default {
+ function = "SALT2";
+ groups = "SALT2";
+ };
- pinctrl_wdtrst1_default: wdtrst1_default {
- function = "WDTRST1";
- groups = "WDTRST1";
- };
+ pinctrl_salt3_default: salt3_default {
+ function = "SALT3";
+ groups = "SALT3";
+ };
- pinctrl_wdtrst2_default: wdtrst2_default {
- function = "WDTRST2";
- groups = "WDTRST2";
- };
+ pinctrl_salt4_default: salt4_default {
+ function = "SALT4";
+ groups = "SALT4";
+ };
- };
- };
+ pinctrl_salt5_default: salt5_default {
+ function = "SALT5";
+ groups = "SALT5";
+ };
- clk_hpll: clk_hpll at 1e6e2024 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-hpll-clock";
- reg = <0x1e6e2024 0x4>;
- clocks = <&clk_clkin>;
- };
+ pinctrl_salt6_default: salt6_default {
+ function = "SALT6";
+ groups = "SALT6";
+ };
- clk_ahb: clk_ahb at 1e6e2070 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-ahb-clock";
- reg = <0x1e6e2070 0x4>;
- clocks = <&clk_hpll>;
- };
+ pinctrl_salt7_default: salt7_default {
+ function = "SALT7";
+ groups = "SALT7";
+ };
- clk_apb: clk_apb at 1e6e2008 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-apb-clock";
- reg = <0x1e6e2008 0x4>;
- clocks = <&clk_hpll>;
- };
+ pinctrl_salt8_default: salt8_default {
+ function = "SALT8";
+ groups = "SALT8";
+ };
- clk_uart: clk_uart at 1e6e2008 {
- #clock-cells = <0>;
- compatible = "aspeed,uart-clock";
- reg = <0x1e6e202c 0x4>;
- };
+ pinctrl_salt9_default: salt9_default {
+ function = "SALT9";
+ groups = "SALT9";
+ };
- gfx: display at 1e6e6000 {
- compatible = "aspeed,ast2500-gfx", "syscon";
- reg = <0x1e6e6000 0x1000>;
- reg-io-width = <4>;
- };
+ pinctrl_scl1_default: scl1_default {
+ function = "SCL1";
+ groups = "SCL1";
+ };
- sram at 1e720000 {
- compatible = "mmio-sram";
- reg = <0x1e720000 0x9000>; // 36K
- };
+ pinctrl_scl2_default: scl2_default {
+ function = "SCL2";
+ groups = "SCL2";
+ };
- gpio: gpio at 1e780000 {
- #gpio-cells = <2>;
- gpio-controller;
- compatible = "aspeed,ast2500-gpio";
- reg = <0x1e780000 0x1000>;
- interrupts = <20>;
- gpio-ranges = <&pinctrl 0 0 220>;
- interrupt-controller;
- };
+ pinctrl_sd1_default: sd1_default {
+ function = "SD1";
+ groups = "SD1";
+ };
- timer: timer at 1e782000 {
- compatible = "aspeed,ast2400-timer";
- reg = <0x1e782000 0x90>;
- // The moxart_timer driver registers only one
- // interrupt and assumes it's for timer 1
- //interrupts = <16 17 18 35 36 37 38 39>;
- interrupts = <16>;
- clocks = <&clk_apb>;
- };
+ pinctrl_sd2_default: sd2_default {
+ function = "SD2";
+ groups = "SD2";
+ };
+ pinctrl_sda1_default: sda1_default {
+ function = "SDA1";
+ groups = "SDA1";
+ };
- wdt1: wdt at 1e785000 {
- compatible = "aspeed,wdt";
- reg = <0x1e785000 0x1c>;
- interrupts = <27>;
- };
+ pinctrl_sda2_default: sda2_default {
+ function = "SDA2";
+ groups = "SDA2";
+ };
- wdt2: wdt at 1e785020 {
- compatible = "aspeed,wdt";
- reg = <0x1e785020 0x1c>;
- interrupts = <27>;
- status = "disabled";
- };
+ pinctrl_sgps1_default: sgps1_default {
+ function = "SGPS1";
+ groups = "SGPS1";
+ };
- wdt3: wdt at 1e785040 {
- compatible = "aspeed,wdt";
- reg = <0x1e785074 0x1c>;
- status = "disabled";
- };
+ pinctrl_sgps2_default: sgps2_default {
+ function = "SGPS2";
+ groups = "SGPS2";
+ };
- uart1: serial at 1e783000 {
- compatible = "ns16550a";
- reg = <0x1e783000 0x1000>;
- reg-shift = <2>;
- interrupts = <9>;
- clocks = <&clk_uart>;
- no-loopback-test;
- status = "disabled";
- };
+ pinctrl_sioonctrl_default: sioonctrl_default {
+ function = "SIOONCTRL";
+ groups = "SIOONCTRL";
+ };
- lpc: lpc at 1e789000 {
- compatible = "aspeed,ast2500-lpc", "simple-mfd";
- reg = <0x1e789000 0x1000>;
+ pinctrl_siopbi_default: siopbi_default {
+ function = "SIOPBI";
+ groups = "SIOPBI";
+ };
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1e789000 0x1000>;
+ pinctrl_siopbo_default: siopbo_default {
+ function = "SIOPBO";
+ groups = "SIOPBO";
+ };
- lpc_bmc: lpc-bmc at 0 {
- compatible = "aspeed,ast2500-lpc-bmc";
- reg = <0x0 0x80>;
- };
+ pinctrl_siopwreq_default: siopwreq_default {
+ function = "SIOPWREQ";
+ groups = "SIOPWREQ";
+ };
- lpc_host: lpc-host at 80 {
- compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
+ pinctrl_siopwrgd_default: siopwrgd_default {
+ function = "SIOPWRGD";
+ groups = "SIOPWRGD";
+ };
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x80 0x1e0>;
+ pinctrl_sios3_default: sios3_default {
+ function = "SIOS3";
+ groups = "SIOS3";
+ };
- reg-io-width = <4>;
+ pinctrl_sios5_default: sios5_default {
+ function = "SIOS5";
+ groups = "SIOS5";
+ };
- lhc: lhc at 20 {
- compatible = "aspeed,ast2500-lhc";
- reg = <0x20 0x24 0x48 0x8>;
- };
- };
- };
+ pinctrl_siosci_default: siosci_default {
+ function = "SIOSCI";
+ groups = "SIOSCI";
+ };
- uart2: serial at 1e78d000 {
- compatible = "ns16550a";
- reg = <0x1e78d000 0x1000>;
- reg-shift = <2>;
- interrupts = <32>;
- clocks = <&clk_uart>;
- no-loopback-test;
- status = "disabled";
- };
+ pinctrl_spi1_default: spi1_default {
+ function = "SPI1";
+ groups = "SPI1";
+ };
- uart3: serial at 1e78e000 {
- compatible = "ns16550a";
- reg = <0x1e78e000 0x1000>;
- reg-shift = <2>;
- interrupts = <33>;
- clocks = <&clk_uart>;
- no-loopback-test;
- status = "disabled";
- };
+ pinctrl_spi1cs1_default: spi1cs1_default {
+ function = "SPI1CS1";
+ groups = "SPI1CS1";
+ };
- uart4: serial at 1e78f000 {
- compatible = "ns16550a";
- reg = <0x1e78f000 0x1000>;
- reg-shift = <2>;
- interrupts = <34>;
- clocks = <&clk_uart>;
- no-loopback-test;
- status = "disabled";
- };
+ pinctrl_spi1debug_default: spi1debug_default {
+ function = "SPI1DEBUG";
+ groups = "SPI1DEBUG";
+ };
- uart5: serial at 1e784000 {
- compatible = "ns16550a";
- reg = <0x1e784000 0x1000>;
- reg-shift = <2>;
- interrupts = <10>;
- clocks = <&clk_uart>;
- current-speed = <38400>;
- no-loopback-test;
- status = "disabled";
- };
+ pinctrl_spi1passthru_default: spi1passthru_default {
+ function = "SPI1PASSTHRU";
+ groups = "SPI1PASSTHRU";
+ };
- uart6: serial at 1e787000 {
- compatible = "ns16550a";
- reg = <0x1e787000 0x1000>;
- reg-shift = <2>;
- interrupts = <10>;
- clocks = <&clk_uart>;
- no-loopback-test;
- status = "disabled";
- };
- };
+ pinctrl_spi2ck_default: spi2ck_default {
+ function = "SPI2CK";
+ groups = "SPI2CK";
+ };
+
+ pinctrl_spi2cs0_default: spi2cs0_default {
+ function = "SPI2CS0";
+ groups = "SPI2CS0";
+ };
+
+ pinctrl_spi2cs1_default: spi2cs1_default {
+ function = "SPI2CS1";
+ groups = "SPI2CS1";
+ };
+
+ pinctrl_spi2miso_default: spi2miso_default {
+ function = "SPI2MISO";
+ groups = "SPI2MISO";
+ };
+
+ pinctrl_spi2mosi_default: spi2mosi_default {
+ function = "SPI2MOSI";
+ groups = "SPI2MOSI";
+ };
+
+ pinctrl_timer3_default: timer3_default {
+ function = "TIMER3";
+ groups = "TIMER3";
+ };
+
+ pinctrl_timer4_default: timer4_default {
+ function = "TIMER4";
+ groups = "TIMER4";
+ };
+
+ pinctrl_timer5_default: timer5_default {
+ function = "TIMER5";
+ groups = "TIMER5";
+ };
+
+ pinctrl_timer6_default: timer6_default {
+ function = "TIMER6";
+ groups = "TIMER6";
+ };
+
+ pinctrl_timer7_default: timer7_default {
+ function = "TIMER7";
+ groups = "TIMER7";
+ };
+
+ pinctrl_timer8_default: timer8_default {
+ function = "TIMER8";
+ groups = "TIMER8";
+ };
+
+ pinctrl_txd1_default: txd1_default {
+ function = "TXD1";
+ groups = "TXD1";
+ };
+
+ pinctrl_txd2_default: txd2_default {
+ function = "TXD2";
+ groups = "TXD2";
+ };
+
+ pinctrl_txd3_default: txd3_default {
+ function = "TXD3";
+ groups = "TXD3";
+ };
+
+ pinctrl_txd4_default: txd4_default {
+ function = "TXD4";
+ groups = "TXD4";
+ };
+
+ pinctrl_uart6_default: uart6_default {
+ function = "UART6";
+ groups = "UART6";
+ };
+
+ pinctrl_usbcki_default: usbcki_default {
+ function = "USBCKI";
+ groups = "USBCKI";
+ };
+
+ pinctrl_usb2ah_default: usb2ah_default {
+ function = "USB2AH";
+ groups = "USB2AH";
+ };
+
+ pinctrl_usb11bhid_default: usb11bhid_default {
+ function = "USB11BHID";
+ groups = "USB11BHID";
+ };
+
+ pinctrl_usb2bh_default: usb2bh_default {
+ function = "USB2BH";
+ groups = "USB2BH";
+ };
+
+ pinctrl_vgabiosrom_default: vgabiosrom_default {
+ function = "VGABIOSROM";
+ groups = "VGABIOSROM";
+ };
+
+ pinctrl_vgahs_default: vgahs_default {
+ function = "VGAHS";
+ groups = "VGAHS";
+ };
+
+ pinctrl_vgavs_default: vgavs_default {
+ function = "VGAVS";
+ groups = "VGAVS";
+ };
+
+ pinctrl_vpi24_default: vpi24_default {
+ function = "VPI24";
+ groups = "VPI24";
+ };
+
+ pinctrl_vpo_default: vpo_default {
+ function = "VPO";
+ groups = "VPO";
+ };
+
+ pinctrl_wdtrst1_default: wdtrst1_default {
+ function = "WDTRST1";
+ groups = "WDTRST1";
+ };
+
+ pinctrl_wdtrst2_default: wdtrst2_default {
+ function = "WDTRST2";
+ groups = "WDTRST2";
};
};
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 6/7] aspeed: Activate ethernet devices on the ast2500 Eval Board
2018-10-01 8:53 [U-Boot] [PATCH v2 0/7] Support for the Faraday ftgmac100 controller Cédric Le Goater
` (4 preceding siblings ...)
2018-10-01 8:53 ` [U-Boot] [PATCH v2 5/7] aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level Cédric Le Goater
@ 2018-10-01 8:53 ` Cédric Le Goater
2018-10-01 8:53 ` [U-Boot] [PATCH v2 7/7] aspeed: ast2500: fix D2-PLL clock setting in RGMII mode Cédric Le Goater
6 siblings, 0 replies; 18+ messages in thread
From: Cédric Le Goater @ 2018-10-01 8:53 UTC (permalink / raw)
To: u-boot
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
arch/arm/dts/ast2500-evb.dts | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 723941ac0bee..ebf44fd707f9 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -11,6 +11,11 @@
chosen {
stdout-path = &uart5;
};
+
+ aliases {
+ ethernet0 = &mac0;
+ ethernet1 = &mac1;
+ };
};
&uart5 {
@@ -36,3 +41,21 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&mac0 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mac1link_default &pinctrl_mdio1_default>;
+};
+
+&mac1 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>;
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 7/7] aspeed: ast2500: fix D2-PLL clock setting in RGMII mode
2018-10-01 8:53 [U-Boot] [PATCH v2 0/7] Support for the Faraday ftgmac100 controller Cédric Le Goater
` (5 preceding siblings ...)
2018-10-01 8:53 ` [U-Boot] [PATCH v2 6/7] aspeed: Activate ethernet devices on the ast2500 Eval Board Cédric Le Goater
@ 2018-10-01 8:53 ` Cédric Le Goater
2018-10-02 11:22 ` Simon Glass
6 siblings, 1 reply; 18+ messages in thread
From: Cédric Le Goater @ 2018-10-01 8:53 UTC (permalink / raw)
To: u-boot
The algorithm in the ast2500_calc_clock_config() routine suffers from
integer rounding and the requested rate does not get the appropriate
set of Numerator, Denumerator, Post Divider parameters.
This is the case for the D2-PLL clock used by the MAC controllers in
RGMII mode. The requested rated is 250MHz but a 251MHz is assigned.
The easiest way to fix this problem is to introduce an array of clock
settings defining the N, M, P parameters for well known frequencies
used by the Aspeed SoC.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/clk/aspeed/clk_ast2500.c | 38 ++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 2182320f607f..dbee13a18297 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -165,6 +165,35 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
return rate;
}
+struct ast2500_clock_config {
+ ulong input_rate;
+ ulong rate;
+ struct ast2500_div_config cfg;
+};
+
+static const struct ast2500_clock_config ast2500_clock_config_defaults[] = {
+ { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } },
+};
+
+static bool ast2500_get_clock_config_default(ulong input_rate,
+ ulong requested_rate,
+ struct ast2500_div_config *cfg)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) {
+ const struct ast2500_clock_config *default_cfg =
+ &ast2500_clock_config_defaults[i];
+ if (default_cfg->input_rate == input_rate &&
+ default_cfg->rate == requested_rate) {
+ *cfg = default_cfg->cfg;
+ return true;
+ }
+ }
+
+ return false;
+}
+
/*
* @input_rate - the rate of input clock in Hz
* @requested_rate - desired output rate in Hz
@@ -189,6 +218,12 @@ static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate,
ulong delta = rate_khz;
ulong new_rate_khz = 0;
+ /*
+ * Look for a well known frequency first.
+ */
+ if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg))
+ return requested_rate;
+
for (; it.denum <= max_vals.denum; ++it.denum) {
for (it.post_div = 0; it.post_div <= max_vals.post_div;
++it.post_div) {
@@ -318,6 +353,9 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)
/*
* The values and the meaning of the next three
* parameters are undocumented. Taken from Aspeed SDK.
+ *
+ * TODO(clg@kaod.org): the SIP and SIC values depend on the
+ * Numerator value
*/
const u32 d2_pll_ext_param = 0x2c;
const u32 d2_pll_sip = 0x11;
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 4/7] net: ftgmac100: Add support for the Aspeed SoC
2018-10-01 8:53 ` [U-Boot] [PATCH v2 4/7] net: ftgmac100: Add support for the Aspeed SoC Cédric Le Goater
@ 2018-10-02 11:22 ` Simon Glass
0 siblings, 0 replies; 18+ messages in thread
From: Simon Glass @ 2018-10-02 11:22 UTC (permalink / raw)
To: u-boot
On 1 October 2018 at 01:53, Cédric Le Goater <clg@kaod.org> wrote:
> The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have
> some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits).
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> Changes since v1:
>
> - introduced a udevice_id .data model
> - dropped is_aspeed bool
> - dropped MDIO interface setting for Aspeed SoC. The default is
> correct.
> - removed the clcoks which are now handled automatically in the
> ftgmac100 driver
>
> drivers/net/ftgmac100.c | 29 +++++++++++++++++++++++++----
> configs/evb-ast2500_defconfig | 8 ++++++++
> 2 files changed, 33 insertions(+), 4 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 5/7] aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level
2018-10-01 8:53 ` [U-Boot] [PATCH v2 5/7] aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level Cédric Le Goater
@ 2018-10-02 11:22 ` Simon Glass
0 siblings, 0 replies; 18+ messages in thread
From: Simon Glass @ 2018-10-02 11:22 UTC (permalink / raw)
To: u-boot
On 1 October 2018 at 01:53, Cédric Le Goater <clg@kaod.org> wrote:
> This is a large update of the AST2500 SoC DTS file bringing it to the
> level of commit 927c2fc2db19 :
>
> Author: Joel Stanley <joel@jms.id.au>
> Date: Sat Jun 2 01:18:53 2018 -0700
>
> ARM: dts: aspeed: Fix hwrng register address
>
> There are some differences on the compatibility property names. scu,
> reset and clock drivers are also different.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> arch/arm/dts/ast2500.dtsi | 1995 ++++++++++++++++++++++---------------
> 1 file changed, 1198 insertions(+), 797 deletions(-)
>
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 7/7] aspeed: ast2500: fix D2-PLL clock setting in RGMII mode
2018-10-01 8:53 ` [U-Boot] [PATCH v2 7/7] aspeed: ast2500: fix D2-PLL clock setting in RGMII mode Cédric Le Goater
@ 2018-10-02 11:22 ` Simon Glass
0 siblings, 0 replies; 18+ messages in thread
From: Simon Glass @ 2018-10-02 11:22 UTC (permalink / raw)
To: u-boot
On 1 October 2018 at 01:53, Cédric Le Goater <clg@kaod.org> wrote:
> The algorithm in the ast2500_calc_clock_config() routine suffers from
> integer rounding and the requested rate does not get the appropriate
> set of Numerator, Denumerator, Post Divider parameters.
>
> This is the case for the D2-PLL clock used by the MAC controllers in
> RGMII mode. The requested rated is 250MHz but a 251MHz is assigned.
>
> The easiest way to fix this problem is to introduce an array of clock
> settings defining the N, M, P parameters for well known frequencies
> used by the Aspeed SoC.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> drivers/clk/aspeed/clk_ast2500.c | 38 ++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver
2018-10-01 8:53 ` [U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver Cédric Le Goater
@ 2018-10-02 11:22 ` Simon Glass
2018-10-02 15:48 ` Cédric Le Goater
0 siblings, 1 reply; 18+ messages in thread
From: Simon Glass @ 2018-10-02 11:22 UTC (permalink / raw)
To: u-boot
On 1 October 2018 at 01:53, Cédric Le Goater <clg@kaod.org> wrote:
> There are too many changes in the following patch fixing support for
> the Faraday ftgmac100 controller. To ease the review, remove the whole
> file which is not compiled anymore today (no Kconfig option for the
> driver).
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> drivers/net/ftgmac100.h | 242 -----------------
> include/netdev.h | 1 -
> drivers/net/ftgmac100.c | 582 ----------------------------------------
> drivers/net/Makefile | 1 -
> 4 files changed, 826 deletions(-)
> delete mode 100644 drivers/net/ftgmac100.h
> delete mode 100644 drivers/net/ftgmac100.c
Reviewed-by: Simon Glass <sjg@chromium.org>
Assuming Joe is happy to remove this and start again? While it is
easier to review, it does remove commit history which is bad.
- Simon
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver
2018-10-02 11:22 ` Simon Glass
@ 2018-10-02 15:48 ` Cédric Le Goater
2018-10-09 16:19 ` Simon Glass
0 siblings, 1 reply; 18+ messages in thread
From: Cédric Le Goater @ 2018-10-02 15:48 UTC (permalink / raw)
To: u-boot
On 10/2/18 1:22 PM, Simon Glass wrote:
> On 1 October 2018 at 01:53, Cédric Le Goater <clg@kaod.org> wrote:
>> There are too many changes in the following patch fixing support for
>> the Faraday ftgmac100 controller. To ease the review, remove the whole
>> file which is not compiled anymore today (no Kconfig option for the
>> driver).
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> drivers/net/ftgmac100.h | 242 -----------------
>> include/netdev.h | 1 -
>> drivers/net/ftgmac100.c | 582 ----------------------------------------
>> drivers/net/Makefile | 1 -
>> 4 files changed, 826 deletions(-)
>> delete mode 100644 drivers/net/ftgmac100.h
>> delete mode 100644 drivers/net/ftgmac100.c
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> Assuming Joe is happy to remove this and start again? While it is
> easier to review, it does remove commit history which is bad.
yes.
The changes are so numerous that it is really difficult to understand
what the resulting driver looks like and splitting the changes would
have been nightmarish. So I took the short path as the driver was not
compiled anymore, but this is questionable.
I can also resend without the initial removal patch but wouldn't it
invalidate the review at the same time ?
Thanks,
C.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver
2018-10-02 15:48 ` Cédric Le Goater
@ 2018-10-09 16:19 ` Simon Glass
2018-10-09 20:44 ` Joe Hershberger
0 siblings, 1 reply; 18+ messages in thread
From: Simon Glass @ 2018-10-09 16:19 UTC (permalink / raw)
To: u-boot
Hi Cedric,
On 2 October 2018 at 09:48, Cédric Le Goater <clg@kaod.org> wrote:
> On 10/2/18 1:22 PM, Simon Glass wrote:
>> On 1 October 2018 at 01:53, Cédric Le Goater <clg@kaod.org> wrote:
>>> There are too many changes in the following patch fixing support for
>>> the Faraday ftgmac100 controller. To ease the review, remove the whole
>>> file which is not compiled anymore today (no Kconfig option for the
>>> driver).
>>>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>> ---
>>> drivers/net/ftgmac100.h | 242 -----------------
>>> include/netdev.h | 1 -
>>> drivers/net/ftgmac100.c | 582 ----------------------------------------
>>> drivers/net/Makefile | 1 -
>>> 4 files changed, 826 deletions(-)
>>> delete mode 100644 drivers/net/ftgmac100.h
>>> delete mode 100644 drivers/net/ftgmac100.c
>>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>
>> Assuming Joe is happy to remove this and start again? While it is
>> easier to review, it does remove commit history which is bad.
>
> yes.
>
> The changes are so numerous that it is really difficult to understand
> what the resulting driver looks like and splitting the changes would
> have been nightmarish. So I took the short path as the driver was not
> compiled anymore, but this is questionable.
>
> I can also resend without the initial removal patch but wouldn't it
> invalidate the review at the same time ?
Yes but it is not hard to re-review in this case.
Regards,
Simon
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver
2018-10-09 16:19 ` Simon Glass
@ 2018-10-09 20:44 ` Joe Hershberger
2018-10-09 21:09 ` Cédric Le Goater
0 siblings, 1 reply; 18+ messages in thread
From: Joe Hershberger @ 2018-10-09 20:44 UTC (permalink / raw)
To: u-boot
On Tue, Oct 9, 2018 at 11:20 AM Simon Glass <sjg@chromium.org> wrote:
>
> Hi Cedric,
>
> On 2 October 2018 at 09:48, Cédric Le Goater <clg@kaod.org> wrote:
> > On 10/2/18 1:22 PM, Simon Glass wrote:
> >> On 1 October 2018 at 01:53, Cédric Le Goater <clg@kaod.org> wrote:
> >>> There are too many changes in the following patch fixing support for
> >>> the Faraday ftgmac100 controller. To ease the review, remove the whole
> >>> file which is not compiled anymore today (no Kconfig option for the
> >>> driver).
> >>>
> >>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> >>> ---
> >>> drivers/net/ftgmac100.h | 242 -----------------
> >>> include/netdev.h | 1 -
> >>> drivers/net/ftgmac100.c | 582 ----------------------------------------
> >>> drivers/net/Makefile | 1 -
> >>> 4 files changed, 826 deletions(-)
> >>> delete mode 100644 drivers/net/ftgmac100.h
> >>> delete mode 100644 drivers/net/ftgmac100.c
> >>
> >> Reviewed-by: Simon Glass <sjg@chromium.org>
> >>
> >> Assuming Joe is happy to remove this and start again? While it is
> >> easier to review, it does remove commit history which is bad.
> >
> > yes.
I have to believe there is a decent amount that is the same, no? I
would prefer not to break git blame unless completely necessary.
> > The changes are so numerous that it is really difficult to understand
> > what the resulting driver looks like and splitting the changes would
> > have been nightmarish. So I took the short path as the driver was not
> > compiled anymore, but this is questionable.
How many changes are we talking about here?
> >
> > I can also resend without the initial removal patch but wouldn't it
> > invalidate the review at the same time ?
>
> Yes but it is not hard to re-review in this case.
>
> Regards,
> Simon
Thanks,
-Joe
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver
2018-10-09 20:44 ` Joe Hershberger
@ 2018-10-09 21:09 ` Cédric Le Goater
2018-10-09 21:19 ` Joe Hershberger
0 siblings, 1 reply; 18+ messages in thread
From: Cédric Le Goater @ 2018-10-09 21:09 UTC (permalink / raw)
To: u-boot
Hello Joe,
On 10/9/18 10:44 PM, Joe Hershberger wrote:
> On Tue, Oct 9, 2018 at 11:20 AM Simon Glass <sjg@chromium.org> wrote:
>>
>> Hi Cedric,
>>
>> On 2 October 2018 at 09:48, Cédric Le Goater <clg@kaod.org> wrote:
>>> On 10/2/18 1:22 PM, Simon Glass wrote:
>>>> On 1 October 2018 at 01:53, Cédric Le Goater <clg@kaod.org> wrote:
>>>>> There are too many changes in the following patch fixing support for
>>>>> the Faraday ftgmac100 controller. To ease the review, remove the whole
>>>>> file which is not compiled anymore today (no Kconfig option for the
>>>>> driver).
>>>>>
>>>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>>>> ---
>>>>> drivers/net/ftgmac100.h | 242 -----------------
>>>>> include/netdev.h | 1 -
>>>>> drivers/net/ftgmac100.c | 582 ----------------------------------------
>>>>> drivers/net/Makefile | 1 -
>>>>> 4 files changed, 826 deletions(-)
>>>>> delete mode 100644 drivers/net/ftgmac100.h
>>>>> delete mode 100644 drivers/net/ftgmac100.c
>>>>
>>>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>>>
>>>> Assuming Joe is happy to remove this and start again? While it is
>>>> easier to review, it does remove commit history which is bad.
>>>
>>> yes.
>
> I have to believe there is a decent amount that is the same, no? I
> would prefer not to break git blame unless completely necessary.
OK.
>>> The changes are so numerous that it is really difficult to understand
>>> what the resulting driver looks like and splitting the changes would
>>> have been nightmarish. So I took the short path as the driver was not
>>> compiled anymore, but this is questionable.
>
> How many changes are we talking about here?
below is a merge of patch one and two. If you think it's fine, I will
send a v3 with a couple more cleanups on the Aspeed AST2500 DTS file.
Thanks,
C.
>
>>>
>>> I can also resend without the initial removal patch but wouldn't it
>>> invalidate the review at the same time ?
>>
>> Yes but it is not hard to re-review in this case.
>>
>> Regards,
>> Simon
>
> Thanks,
> -Joe
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver
2018-10-09 21:09 ` Cédric Le Goater
@ 2018-10-09 21:19 ` Joe Hershberger
2018-10-09 21:34 ` Cédric Le Goater
0 siblings, 1 reply; 18+ messages in thread
From: Joe Hershberger @ 2018-10-09 21:19 UTC (permalink / raw)
To: u-boot
On Tue, Oct 9, 2018 at 4:10 PM Cédric Le Goater <clg@kaod.org> wrote:
>
> Hello Joe,
>
> On 10/9/18 10:44 PM, Joe Hershberger wrote:
> > On Tue, Oct 9, 2018 at 11:20 AM Simon Glass <sjg@chromium.org> wrote:
> >>
> >> Hi Cedric,
> >>
> >> On 2 October 2018 at 09:48, Cédric Le Goater <clg@kaod.org> wrote:
> >>> On 10/2/18 1:22 PM, Simon Glass wrote:
> >>>> On 1 October 2018 at 01:53, Cédric Le Goater <clg@kaod.org> wrote:
> >>>>> There are too many changes in the following patch fixing support for
> >>>>> the Faraday ftgmac100 controller. To ease the review, remove the whole
> >>>>> file which is not compiled anymore today (no Kconfig option for the
> >>>>> driver).
> >>>>>
> >>>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> >>>>> ---
> >>>>> drivers/net/ftgmac100.h | 242 -----------------
> >>>>> include/netdev.h | 1 -
> >>>>> drivers/net/ftgmac100.c | 582 ----------------------------------------
> >>>>> drivers/net/Makefile | 1 -
> >>>>> 4 files changed, 826 deletions(-)
> >>>>> delete mode 100644 drivers/net/ftgmac100.h
> >>>>> delete mode 100644 drivers/net/ftgmac100.c
> >>>>
> >>>> Reviewed-by: Simon Glass <sjg@chromium.org>
> >>>>
> >>>> Assuming Joe is happy to remove this and start again? While it is
> >>>> easier to review, it does remove commit history which is bad.
> >>>
> >>> yes.
> >
> > I have to believe there is a decent amount that is the same, no? I
> > would prefer not to break git blame unless completely necessary.
>
> OK.
>
> >>> The changes are so numerous that it is really difficult to understand
> >>> what the resulting driver looks like and splitting the changes would
> >>> have been nightmarish. So I took the short path as the driver was not
> >>> compiled anymore, but this is questionable.
> >
> > How many changes are we talking about here?
>
> below is a merge of patch one and two. If you think it's fine, I will
> send a v3 with a couple more cleanups on the Aspeed AST2500 DTS file.
Can you try to separate the cosmetic changes from the substantive ones?
Thanks,
-Joe
>
> Thanks,
>
> C.
>
> >
> >>>
> >>> I can also resend without the initial removal patch but wouldn't it
> >>> invalidate the review at the same time ?
> >>
> >> Yes but it is not hard to re-review in this case.
> >>
> >> Regards,
> >> Simon
> >
> > Thanks,
> > -Joe
> >
>
>
> From 634d9707525f7a243835f84d5beb9b0e1a673d32 Mon Sep 17 00:00:00 2001
> From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>
> Date: Fri, 7 Sep 2018 19:15:57 +0200
> Subject: [PATCH] net: fix support for the Faraday ftgmac100 controller
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
>
> The driver is based on the previous one and adds the same support for
> the Faraday ftgmac100 controller with MAC and MDIO bus support for
> RGMII/RMII modes. Driver model support was added as well as some
> enhancements and fixes.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> drivers/net/ftgmac100.h | 158 ++++-----
> include/netdev.h | 1 -
> drivers/net/ftgmac100.c | 742 +++++++++++++++++++---------------------
> drivers/net/Kconfig | 26 ++
> 4 files changed, 459 insertions(+), 468 deletions(-)
>
> diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h
> index ffbe1f3e3fa7..9a789e4d5bee 100644
> --- a/drivers/net/ftgmac100.h
> +++ b/drivers/net/ftgmac100.h
> @@ -70,48 +70,48 @@ struct ftgmac100 {
> /*
> * Interrupt status register & interrupt enable register
> */
> -#define FTGMAC100_INT_RPKT_BUF (1 << 0)
> -#define FTGMAC100_INT_RPKT_FIFO (1 << 1)
> -#define FTGMAC100_INT_NO_RXBUF (1 << 2)
> -#define FTGMAC100_INT_RPKT_LOST (1 << 3)
> -#define FTGMAC100_INT_XPKT_ETH (1 << 4)
> -#define FTGMAC100_INT_XPKT_FIFO (1 << 5)
> -#define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
> -#define FTGMAC100_INT_XPKT_LOST (1 << 7)
> -#define FTGMAC100_INT_AHB_ERR (1 << 8)
> -#define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
> -#define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
> +#define FTGMAC100_INT_RPKT_BUF BIT(0)
> +#define FTGMAC100_INT_RPKT_FIFO BIT(1)
> +#define FTGMAC100_INT_NO_RXBUF BIT(2)
> +#define FTGMAC100_INT_RPKT_LOST BIT(3)
> +#define FTGMAC100_INT_XPKT_ETH BIT(4)
> +#define FTGMAC100_INT_XPKT_FIFO BIT(5)
> +#define FTGMAC100_INT_NO_NPTXBUF BIT(6)
> +#define FTGMAC100_INT_XPKT_LOST BIT(7)
> +#define FTGMAC100_INT_AHB_ERR BIT(8)
> +#define FTGMAC100_INT_PHYSTS_CHG BIT(9)
> +#define FTGMAC100_INT_NO_HPTXBUF BIT(10)
>
> /*
> * Interrupt timer control register
> */
> #define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
> #define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
> -#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7)
> +#define FTGMAC100_ITC_RXINT_TIME_SEL BIT(7)
> #define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
> #define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
> -#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15)
> +#define FTGMAC100_ITC_TXINT_TIME_SEL BIT(15)
>
> /*
> * Automatic polling timer control register
> */
> #define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
> -#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
> +#define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4)
> #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
> -#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
> +#define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12)
>
> /*
> * DMA burst length and arbitration control register
> */
> #define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0)
> #define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3)
> -#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6)
> +#define FTGMAC100_DBLAC_RX_THR_EN BIT(6)
> #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8)
> #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
> #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12)
> #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16)
> #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
> -#define FTGMAC100_DBLAC_IFG_INC (1 << 23)
> +#define FTGMAC100_DBLAC_IFG_INC BIT(23)
>
> /*
> * DMA FIFO status register
> @@ -122,12 +122,12 @@ struct ftgmac100 {
> #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf)
> #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3)
> #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf)
> -#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26)
> -#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27)
> -#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28)
> -#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29)
> -#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30)
> -#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31)
> +#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY BIT(26)
> +#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY BIT(27)
> +#define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28)
> +#define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29)
> +#define FTGMAC100_DMAFIFOS_RXDMA_REQ BIT(30)
> +#define FTGMAC100_DMAFIFOS_TXDMA_REQ BIT(31)
>
> /*
> * Receive buffer size register
> @@ -137,26 +137,26 @@ struct ftgmac100 {
> /*
> * MAC control register
> */
> -#define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
> -#define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
> -#define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
> -#define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
> -#define FTGMAC100_MACCR_RM_VLAN (1 << 4)
> -#define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
> -#define FTGMAC100_MACCR_LOOP_EN (1 << 6)
> -#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
> -#define FTGMAC100_MACCR_FULLDUP (1 << 8)
> -#define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
> -#define FTGMAC100_MACCR_CRC_APD (1 << 10)
> -#define FTGMAC100_MACCR_RX_RUNT (1 << 12)
> -#define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
> -#define FTGMAC100_MACCR_RX_ALL (1 << 14)
> -#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
> -#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
> -#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
> -#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
> -#define FTGMAC100_MACCR_FAST_MODE (1 << 19)
> -#define FTGMAC100_MACCR_SW_RST (1 << 31)
> +#define FTGMAC100_MACCR_TXDMA_EN BIT(0)
> +#define FTGMAC100_MACCR_RXDMA_EN BIT(1)
> +#define FTGMAC100_MACCR_TXMAC_EN BIT(2)
> +#define FTGMAC100_MACCR_RXMAC_EN BIT(3)
> +#define FTGMAC100_MACCR_RM_VLAN BIT(4)
> +#define FTGMAC100_MACCR_HPTXR_EN BIT(5)
> +#define FTGMAC100_MACCR_LOOP_EN BIT(6)
> +#define FTGMAC100_MACCR_ENRX_IN_HALFTX BIT(7)
> +#define FTGMAC100_MACCR_FULLDUP BIT(8)
> +#define FTGMAC100_MACCR_GIGA_MODE BIT(9)
> +#define FTGMAC100_MACCR_CRC_APD BIT(10)
> +#define FTGMAC100_MACCR_RX_RUNT BIT(12)
> +#define FTGMAC100_MACCR_JUMBO_LF BIT(13)
> +#define FTGMAC100_MACCR_RX_ALL BIT(14)
> +#define FTGMAC100_MACCR_HT_MULTI_EN BIT(15)
> +#define FTGMAC100_MACCR_RX_MULTIPKT BIT(16)
> +#define FTGMAC100_MACCR_RX_BROADPKT BIT(17)
> +#define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18)
> +#define FTGMAC100_MACCR_FAST_MODE BIT(19)
> +#define FTGMAC100_MACCR_SW_RST BIT(31)
>
> /*
> * PHY control register
> @@ -165,8 +165,8 @@ struct ftgmac100 {
> #define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f)
> #define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16)
> #define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21)
> -#define FTGMAC100_PHYCR_MIIRD (1 << 26)
> -#define FTGMAC100_PHYCR_MIIWR (1 << 27)
> +#define FTGMAC100_PHYCR_MIIRD BIT(26)
> +#define FTGMAC100_PHYCR_MIIWR BIT(27)
>
> /*
> * PHY data register
> @@ -182,23 +182,23 @@ struct ftgmac100_txdes {
> unsigned int txdes1;
> unsigned int txdes2; /* not used by HW */
> unsigned int txdes3; /* TXBUF_BADR */
> -} __attribute__ ((aligned(16)));
> +} __aligned(16);
>
> #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
> -#define FTGMAC100_TXDES0_EDOTR (1 << 15)
> -#define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
> -#define FTGMAC100_TXDES0_LTS (1 << 28)
> -#define FTGMAC100_TXDES0_FTS (1 << 29)
> -#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
> +#define FTGMAC100_TXDES0_EDOTR BIT(15)
> +#define FTGMAC100_TXDES0_CRC_ERR BIT(19)
> +#define FTGMAC100_TXDES0_LTS BIT(28)
> +#define FTGMAC100_TXDES0_FTS BIT(29)
> +#define FTGMAC100_TXDES0_TXDMA_OWN BIT(31)
>
> #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
> -#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
> -#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
> -#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
> -#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
> -#define FTGMAC100_TXDES1_LLC (1 << 22)
> -#define FTGMAC100_TXDES1_TX2FIC (1 << 30)
> -#define FTGMAC100_TXDES1_TXIC (1 << 31)
> +#define FTGMAC100_TXDES1_INS_VLANTAG BIT(16)
> +#define FTGMAC100_TXDES1_TCP_CHKSUM BIT(17)
> +#define FTGMAC100_TXDES1_UDP_CHKSUM BIT(18)
> +#define FTGMAC100_TXDES1_IP_CHKSUM BIT(19)
> +#define FTGMAC100_TXDES1_LLC BIT(22)
> +#define FTGMAC100_TXDES1_TX2FIC BIT(30)
> +#define FTGMAC100_TXDES1_TXIC BIT(31)
>
> /*
> * Receive descriptor, aligned to 16 bytes
> @@ -208,23 +208,23 @@ struct ftgmac100_rxdes {
> unsigned int rxdes1;
> unsigned int rxdes2; /* not used by HW */
> unsigned int rxdes3; /* RXBUF_BADR */
> -} __attribute__ ((aligned(16)));
> +} __aligned(16);
>
> #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff)
> -#define FTGMAC100_RXDES0_EDORR (1 << 15)
> -#define FTGMAC100_RXDES0_MULTICAST (1 << 16)
> -#define FTGMAC100_RXDES0_BROADCAST (1 << 17)
> -#define FTGMAC100_RXDES0_RX_ERR (1 << 18)
> -#define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
> -#define FTGMAC100_RXDES0_FTL (1 << 20)
> -#define FTGMAC100_RXDES0_RUNT (1 << 21)
> -#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
> -#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
> -#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
> -#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
> -#define FTGMAC100_RXDES0_LRS (1 << 28)
> -#define FTGMAC100_RXDES0_FRS (1 << 29)
> -#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
> +#define FTGMAC100_RXDES0_EDORR BIT(15)
> +#define FTGMAC100_RXDES0_MULTICAST BIT(16)
> +#define FTGMAC100_RXDES0_BROADCAST BIT(17)
> +#define FTGMAC100_RXDES0_RX_ERR BIT(18)
> +#define FTGMAC100_RXDES0_CRC_ERR BIT(19)
> +#define FTGMAC100_RXDES0_FTL BIT(20)
> +#define FTGMAC100_RXDES0_RUNT BIT(21)
> +#define FTGMAC100_RXDES0_RX_ODD_NB BIT(22)
> +#define FTGMAC100_RXDES0_FIFO_FULL BIT(23)
> +#define FTGMAC100_RXDES0_PAUSE_OPCODE BIT(24)
> +#define FTGMAC100_RXDES0_PAUSE_FRAME BIT(25)
> +#define FTGMAC100_RXDES0_LRS BIT(28)
> +#define FTGMAC100_RXDES0_FRS BIT(29)
> +#define FTGMAC100_RXDES0_RXPKT_RDY BIT(31)
>
> #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
> #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
> @@ -232,11 +232,11 @@ struct ftgmac100_rxdes {
> #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
> #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
> #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
> -#define FTGMAC100_RXDES1_LLC (1 << 22)
> -#define FTGMAC100_RXDES1_DF (1 << 23)
> -#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
> -#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
> -#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
> -#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
> +#define FTGMAC100_RXDES1_LLC BIT(22)
> +#define FTGMAC100_RXDES1_DF BIT(23)
> +#define FTGMAC100_RXDES1_VLANTAG_AVAIL BIT(24)
> +#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR BIT(25)
> +#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26)
> +#define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27)
>
> #endif /* __FTGMAC100_H */
> diff --git a/include/netdev.h b/include/netdev.h
> index 55001625fb92..0a1a3a2d8da2 100644
> --- a/include/netdev.h
> +++ b/include/netdev.h
> @@ -43,7 +43,6 @@ int ethoc_initialize(u8 dev_num, int base_addr);
> int fec_initialize (bd_t *bis);
> int fecmxc_initialize(bd_t *bis);
> int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
> -int ftgmac100_initialize(bd_t *bits);
> int ftmac100_initialize(bd_t *bits);
> int ftmac110_initialize(bd_t *bits);
> void gt6426x_eth_initialize(bd_t *bis);
> diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
> index c996f5f4a167..4596385d68cf 100644
> --- a/drivers/net/ftgmac100.c
> +++ b/drivers/net/ftgmac100.c
> @@ -7,265 +7,165 @@
> *
> * (C) Copyright 2010 Andes Technology
> * Macpaul Lin <macpaul@andestech.com>
> + *
> + * Copyright (C) 2018, IBM Corporation.
> */
>
> -#include <config.h>
> -#include <common.h>
> -#include <malloc.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <miiphy.h>
> #include <net.h>
> -#include <asm/io.h>
> -#include <asm/dma-mapping.h>
> -#include <linux/mii.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
>
> #include "ftgmac100.h"
>
> -#define ETH_ZLEN 60
> -#define CFG_XBUF_SIZE 1536
> +/* Min frame ethernet frame size without FCS */
> +#define ETH_ZLEN 60
>
> -/* RBSR - hw default init value is also 0x640 */
> -#define RBSR_DEFAULT_VALUE 0x640
> +/* Receive Buffer Size Register - HW default is 0x640 */
> +#define FTGMAC100_RBSR_DEFAULT 0x640
>
> /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
> -#define PKTBUFSTX 4 /* must be power of 2 */
> +#define PKTBUFSTX 4
>
> -struct ftgmac100_data {
> - ulong txdes_dma;
> - struct ftgmac100_txdes *txdes;
> - ulong rxdes_dma;
> - struct ftgmac100_rxdes *rxdes;
> - int tx_index;
> - int rx_index;
> - int phy_addr;
> -};
> +/* Timeout for transmit */
> +#define FTGMAC100_TX_TIMEOUT_MS 1000
> +
> +/* Timeout for a mdio read/write operation */
> +#define FTGMAC100_MDIO_TIMEOUT_USEC 10000
>
> /*
> - * struct mii_bus functions
> + * MDC clock cycle threshold
> + *
> + * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
> */
> -static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr,
> - int regnum)
> -{
> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
> - int phycr;
> - int i;
> -
> - phycr = readl(&ftgmac100->phycr);
> +#define MDC_CYCTHR 0x34
>
> - /* preserve MDC cycle threshold */
> - phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
> +/**
> + * struct ftgmac100_data - private data for the FTGMAC100 driver
> + *
> + * @iobase: The base address of the hardware registers
> + * @txdes: The array of transmit descriptors
> + * @rxdes: The array of receive descriptors
> + * @tx_index: Transmit descriptor index in @txdes
> + * @rx_index: Receive descriptor index in @rxdes
> + * @phyaddr: The PHY interface address to use
> + * @phydev: The PHY device backing the MAC
> + * @bus: The mdio bus
> + * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
> + * @max_speed: Maximum speed of Ethernet connection supported by MAC
> + * @clks: The bulk of clocks assigned to the device in the DT
> + */
> +struct ftgmac100_data {
> + struct ftgmac100 *iobase;
>
> - phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
> - | FTGMAC100_PHYCR_REGAD(regnum)
> - | FTGMAC100_PHYCR_MIIRD;
> + struct ftgmac100_txdes txdes[PKTBUFSTX];
> + struct ftgmac100_rxdes rxdes[PKTBUFSRX];
> + int tx_index;
> + int rx_index;
>
> - writel(phycr, &ftgmac100->phycr);
> + u32 phyaddr;
> + struct phy_device *phydev;
> + struct mii_dev *bus;
> + u32 phy_mode;
> + u32 max_speed;
>
> - for (i = 0; i < 10; i++) {
> - phycr = readl(&ftgmac100->phycr);
> + struct clk_bulk clks;
> +};
>
> - if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
> - int data;
> +static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
> + int reg_addr)
> +{
> + struct ftgmac100_data *priv = bus->priv;
> + struct ftgmac100 *ftgmac100 = priv->iobase;
> + int phycr;
> + int data;
> + int ret;
>
> - data = readl(&ftgmac100->phydata);
> - return FTGMAC100_PHYDATA_MIIRDATA(data);
> - }
> + phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
> + FTGMAC100_PHYCR_PHYAD(phy_addr) |
> + FTGMAC100_PHYCR_REGAD(reg_addr) |
> + FTGMAC100_PHYCR_MIIRD;
> + writel(phycr, &ftgmac100->phycr);
>
> - mdelay(10);
> + ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
> + !(phycr & FTGMAC100_PHYCR_MIIRD),
> + FTGMAC100_MDIO_TIMEOUT_USEC);
> + if (ret) {
> + pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
> + priv->phydev->dev->name, phy_addr, reg_addr);
> + return ret;
> }
>
> - debug("mdio read timed out\n");
> - return -1;
> + data = readl(&ftgmac100->phydata);
> +
> + return FTGMAC100_PHYDATA_MIIRDATA(data);
> }
>
> -static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr,
> - int regnum, u16 value)
> +static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
> + int reg_addr, u16 value)
> {
> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
> + struct ftgmac100_data *priv = bus->priv;
> + struct ftgmac100 *ftgmac100 = priv->iobase;
> int phycr;
> int data;
> - int i;
> -
> - phycr = readl(&ftgmac100->phycr);
> -
> - /* preserve MDC cycle threshold */
> - phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
> -
> - phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
> - | FTGMAC100_PHYCR_REGAD(regnum)
> - | FTGMAC100_PHYCR_MIIWR;
> + int ret;
>
> + phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
> + FTGMAC100_PHYCR_PHYAD(phy_addr) |
> + FTGMAC100_PHYCR_REGAD(reg_addr) |
> + FTGMAC100_PHYCR_MIIWR;
> data = FTGMAC100_PHYDATA_MIIWDATA(value);
>
> writel(data, &ftgmac100->phydata);
> writel(phycr, &ftgmac100->phycr);
>
> - for (i = 0; i < 10; i++) {
> - phycr = readl(&ftgmac100->phycr);
> -
> - if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) {
> - debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \
> - "phy_addr: %x\n", phy_addr);
> - return 0;
> - }
> -
> - mdelay(1);
> + ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
> + !(phycr & FTGMAC100_PHYCR_MIIWR),
> + FTGMAC100_MDIO_TIMEOUT_USEC);
> + if (ret) {
> + pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
> + priv->phydev->dev->name, phy_addr, reg_addr);
> }
>
> - debug("mdio write timed out\n");
> - return -1;
> + return ret;
> }
>
> -int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value)
> +static int ftgmac100_mdio_init(struct ftgmac100_data *priv, int dev_id)
> {
> - *value = ftgmac100_mdiobus_read(dev , addr, reg);
> -
> - if (*value == -1)
> - return -1;
> -
> - return 0;
> -}
> -
> -int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value)
> -{
> - if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1)
> - return -1;
> -
> - return 0;
> -}
> -
> -static int ftgmac100_phy_reset(struct eth_device *dev)
> -{
> - struct ftgmac100_data *priv = dev->priv;
> - int i;
> - u16 status, adv;
> -
> - adv = ADVERTISE_CSMA | ADVERTISE_ALL;
> -
> - ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv);
> + struct mii_dev *bus;
> + int ret;
>
> - printf("%s: Starting autonegotiation...\n", dev->name);
> + bus = mdio_alloc();
> + if (!bus)
> + return -ENOMEM;
>
> - ftgmac100_phy_write(dev, priv->phy_addr,
> - MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
> + bus->read = ftgmac100_mdio_read;
> + bus->write = ftgmac100_mdio_write;
> + bus->priv = priv;
>
> - for (i = 0; i < 100000 / 100; i++) {
> - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
> -
> - if (status & BMSR_ANEGCOMPLETE)
> - break;
> - mdelay(1);
> + ret = mdio_register_seq(bus, dev_id);
> + if (ret) {
> + free(bus);
> + return ret;
> }
>
> - if (status & BMSR_ANEGCOMPLETE) {
> - printf("%s: Autonegotiation complete\n", dev->name);
> - } else {
> - printf("%s: Autonegotiation timed out (status=0x%04x)\n",
> - dev->name, status);
> - return 0;
> - }
> + priv->bus = bus;
>
> - return 1;
> + return 0;
> }
>
> -static int ftgmac100_phy_init(struct eth_device *dev)
> +static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
> {
> - struct ftgmac100_data *priv = dev->priv;
> -
> - int phy_addr;
> - u16 phy_id, status, adv, lpa, stat_ge;
> - int media, speed, duplex;
> - int i;
> -
> - /* Check if the PHY is up to snuff... */
> - for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) {
> -
> - ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id);
> -
> - /*
> - * When it is unable to found PHY,
> - * the interface usually return 0xffff or 0x0000
> - */
> - if (phy_id != 0xffff && phy_id != 0x0) {
> - printf("%s: found PHY at 0x%02x\n",
> - dev->name, phy_addr);
> - priv->phy_addr = phy_addr;
> - break;
> - }
> - }
> -
> - if (phy_id == 0xffff || phy_id == 0x0) {
> - printf("%s: no PHY present\n", dev->name);
> - return 0;
> - }
> -
> - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
> -
> - if (!(status & BMSR_LSTATUS)) {
> - /* Try to re-negotiate if we don't have link already. */
> - ftgmac100_phy_reset(dev);
> -
> - for (i = 0; i < 100000 / 100; i++) {
> - ftgmac100_phy_read(dev, priv->phy_addr,
> - MII_BMSR, &status);
> - if (status & BMSR_LSTATUS)
> - break;
> - udelay(100);
> - }
> - }
> -
> - if (!(status & BMSR_LSTATUS)) {
> - printf("%s: link down\n", dev->name);
> - return 0;
> - }
> -
> -#ifdef CONFIG_FTGMAC100_EGIGA
> - /* 1000 Base-T Status Register */
> - ftgmac100_phy_read(dev, priv->phy_addr,
> - MII_STAT1000, &stat_ge);
> -
> - speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF)
> - ? 1 : 0);
> + struct ftgmac100 *ftgmac100 = priv->iobase;
> + struct phy_device *phydev = priv->phydev;
> + u32 maccr;
>
> - duplex = ((stat_ge & LPA_1000FULL)
> - ? 1 : 0);
> -
> - if (speed) { /* Speed is 1000 */
> - printf("%s: link up, 1000bps %s-duplex\n",
> - dev->name, duplex ? "full" : "half");
> - return 0;
> + if (!phydev->link) {
> + dev_err(phydev->dev, "No link\n");
> + return -EREMOTEIO;
> }
> -#endif
> -
> - ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv);
> - ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa);
> -
> - media = mii_nway_result(lpa & adv);
> - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0);
> - duplex = (media & ADVERTISE_FULL) ? 1 : 0;
> -
> - printf("%s: link up, %sMbps %s-duplex\n",
> - dev->name, speed ? "100" : "10", duplex ? "full" : "half");
> -
> - return 1;
> -}
> -
> -static int ftgmac100_update_link_speed(struct eth_device *dev)
> -{
> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
> - struct ftgmac100_data *priv = dev->priv;
> -
> - unsigned short stat_fe;
> - unsigned short stat_ge;
> - unsigned int maccr;
> -
> -#ifdef CONFIG_FTGMAC100_EGIGA
> - /* 1000 Base-T Status Register */
> - ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge);
> -#endif
> -
> - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe);
> -
> - if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */
> - return 0;
>
> /* read MAC control register and clear related bits */
> maccr = readl(&ftgmac100->maccr) &
> @@ -273,173 +173,130 @@ static int ftgmac100_update_link_speed(struct eth_device *dev)
> FTGMAC100_MACCR_FAST_MODE |
> FTGMAC100_MACCR_FULLDUP);
>
> -#ifdef CONFIG_FTGMAC100_EGIGA
> - if (stat_ge & LPA_1000FULL) {
> - /* set gmac for 1000BaseTX and Full Duplex */
> - maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP;
> - }
> -
> - if (stat_ge & LPA_1000HALF) {
> - /* set gmac for 1000BaseTX and Half Duplex */
> + if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
> maccr |= FTGMAC100_MACCR_GIGA_MODE;
> - }
> -#endif
> -
> - if (stat_fe & BMSR_100FULL) {
> - /* set MII for 100BaseTX and Full Duplex */
> - maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP;
> - }
> -
> - if (stat_fe & BMSR_10FULL) {
> - /* set MII for 10BaseT and Full Duplex */
> - maccr |= FTGMAC100_MACCR_FULLDUP;
> - }
>
> - if (stat_fe & BMSR_100HALF) {
> - /* set MII for 100BaseTX and Half Duplex */
> + if (phydev->speed == 100)
> maccr |= FTGMAC100_MACCR_FAST_MODE;
> - }
>
> - if (stat_fe & BMSR_10HALF) {
> - /* set MII for 10BaseT and Half Duplex */
> - /* we have already clear these bits, do nothing */
> - ;
> - }
> + if (phydev->duplex)
> + maccr |= FTGMAC100_MACCR_FULLDUP;
>
> /* update MII config into maccr */
> writel(maccr, &ftgmac100->maccr);
>
> - return 1;
> + return 0;
> }
>
> -/*
> - * Reset MAC
> - */
> -static void ftgmac100_reset(struct eth_device *dev)
> +static int ftgmac100_phy_init(struct ftgmac100_data *priv, void *dev)
> {
> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
> + struct phy_device *phydev;
> + int ret;
> +
> + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->phy_mode);
> + if (!phydev)
> + return -ENODEV;
> +
> + phydev->supported &= PHY_GBIT_FEATURES;
> + if (priv->max_speed) {
> + ret = phy_set_supported(phydev, priv->max_speed);
> + if (ret)
> + return ret;
> + }
> + phydev->advertising = phydev->supported;
> + priv->phydev = phydev;
> + phy_config(phydev);
> +
> + return 0;
> +}
>
> - debug("%s()\n", __func__);
> +static void ftgmac100_reset(struct ftgmac100_data *priv)
> +{
> + struct ftgmac100 *ftgmac100 = priv->iobase;
>
> - writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr);
> + setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
>
> while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
> ;
> }
>
> -/*
> - * Set MAC address
> - */
> -static void ftgmac100_set_mac(struct eth_device *dev,
> - const unsigned char *mac)
> +static int ftgmac100_set_mac(struct ftgmac100_data *priv,
> + const unsigned char *mac)
> {
> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
> + struct ftgmac100 *ftgmac100 = priv->iobase;
> unsigned int maddr = mac[0] << 8 | mac[1];
> unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
>
> - debug("%s(%x %x)\n", __func__, maddr, laddr);
> -
> writel(maddr, &ftgmac100->mac_madr);
> writel(laddr, &ftgmac100->mac_ladr);
> -}
>
> -static void ftgmac100_set_mac_from_env(struct eth_device *dev)
> -{
> - eth_env_get_enetaddr("ethaddr", dev->enetaddr);
> -
> - ftgmac100_set_mac(dev, dev->enetaddr);
> + return 0;
> }
>
> -/*
> - * disable transmitter, receiver
> - */
> -static void ftgmac100_halt(struct eth_device *dev)
> +static void ftgmac100_stop(struct udevice *dev)
> {
> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
> -
> - debug("%s()\n", __func__);
> + struct ftgmac100_data *priv = dev_get_priv(dev);
> + struct ftgmac100 *ftgmac100 = priv->iobase;
>
> writel(0, &ftgmac100->maccr);
> +
> + phy_shutdown(priv->phydev);
> }
>
> -static int ftgmac100_init(struct eth_device *dev, bd_t *bd)
> +static int ftgmac100_start(struct udevice *dev)
> {
> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
> - struct ftgmac100_data *priv = dev->priv;
> - struct ftgmac100_txdes *txdes;
> - struct ftgmac100_rxdes *rxdes;
> + struct eth_pdata *plat = dev_get_platdata(dev);
> + struct ftgmac100_data *priv = dev_get_priv(dev);
> + struct ftgmac100 *ftgmac100 = priv->iobase;
> + struct phy_device *phydev = priv->phydev;
> unsigned int maccr;
> - void *buf;
> + ulong start, end;
> + int ret;
> int i;
>
> - debug("%s()\n", __func__);
> -
> - if (!priv->txdes) {
> - txdes = dma_alloc_coherent(
> - sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
> - if (!txdes)
> - panic("ftgmac100: out of memory\n");
> - memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
> - priv->txdes = txdes;
> - }
> - txdes = priv->txdes;
> -
> - if (!priv->rxdes) {
> - rxdes = dma_alloc_coherent(
> - sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
> - if (!rxdes)
> - panic("ftgmac100: out of memory\n");
> - memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
> - priv->rxdes = rxdes;
> - }
> - rxdes = priv->rxdes;
> + ftgmac100_reset(priv);
>
> /* set the ethernet address */
> - ftgmac100_set_mac_from_env(dev);
> + ftgmac100_set_mac(priv, plat->enetaddr);
>
> /* disable all interrupts */
> writel(0, &ftgmac100->ier);
>
> - /* initialize descriptors */
> + /* initialize descriptor tables */
> priv->tx_index = 0;
> priv->rx_index = 0;
>
> - txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
> - rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
> -
> for (i = 0; i < PKTBUFSTX; i++) {
> - /* TXBUF_BADR */
> - if (!txdes[i].txdes2) {
> - buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
> - if (!buf)
> - panic("ftgmac100: out of memory\n");
> - txdes[i].txdes3 = virt_to_phys(buf);
> - txdes[i].txdes2 = (uint)buf;
> - }
> - txdes[i].txdes1 = 0;
> + priv->txdes[i].txdes3 = 0;
> + priv->txdes[i].txdes0 = 0;
> }
> + priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
> +
> + start = (ulong)&priv->txdes[0];
> + end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
> + flush_dcache_range(start, end);
>
> for (i = 0; i < PKTBUFSRX; i++) {
> - /* RXBUF_BADR */
> - if (!rxdes[i].rxdes2) {
> - buf = net_rx_packets[i];
> - rxdes[i].rxdes3 = virt_to_phys(buf);
> - rxdes[i].rxdes2 = (uint)buf;
> - }
> - rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
> + priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
> + priv->rxdes[i].rxdes0 = 0;
> }
> + priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
> +
> + start = (ulong)&priv->rxdes[0];
> + end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
> + flush_dcache_range(start, end);
>
> /* transmit ring */
> - writel(priv->txdes_dma, &ftgmac100->txr_badr);
> + writel((u32)priv->txdes, &ftgmac100->txr_badr);
>
> /* receive ring */
> - writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
> + writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
>
> /* poll receive descriptor automatically */
> writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
>
> /* config receive buffer size register */
> - writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr);
> + writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
>
> /* enable transmitter, receiver */
> maccr = FTGMAC100_MACCR_TXMAC_EN |
> @@ -453,130 +310,239 @@ static int ftgmac100_init(struct eth_device *dev, bd_t *bd)
>
> writel(maccr, &ftgmac100->maccr);
>
> - if (!ftgmac100_phy_init(dev)) {
> - if (!ftgmac100_update_link_speed(dev))
> - return -1;
> + ret = phy_startup(phydev);
> + if (ret) {
> + dev_err(phydev->dev, "Could not start PHY\n");
> + return ret;
> + }
> +
> + ret = ftgmac100_phy_adjust_link(priv);
> + if (ret) {
> + dev_err(phydev->dev, "Could not adjust link\n");
> + return ret;
> }
>
> + printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
> + phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
> +
> return 0;
> }
>
> -/*
> - * Get a data block via Ethernet
> - */
> -static int ftgmac100_recv(struct eth_device *dev)
> +static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
> +{
> + struct ftgmac100_data *priv = dev_get_priv(dev);
> + struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
> + ulong des_start = (ulong)curr_des;
> + ulong des_end = des_start +
> + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
> +
> + /* Release buffer to DMA and flush descriptor */
> + curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
> + flush_dcache_range(des_start, des_end);
> +
> + /* Move to next descriptor */
> + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
> +
> + return 0;
> +}
> +
> +static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
> {
> - struct ftgmac100_data *priv = dev->priv;
> - struct ftgmac100_rxdes *curr_des;
> - unsigned short rxlen;
> + struct ftgmac100_data *priv = dev_get_priv(dev);
> + struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
> + int length;
> + ulong des_start = (ulong)curr_des;
> + ulong des_end = des_start +
> + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
> + ulong data_start = curr_des->rxdes3;
> + ulong data_end;
>
> - curr_des = &priv->rxdes[priv->rx_index];
> + invalidate_dcache_range(des_start, des_end);
>
> if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
> - return -1;
> + return -EAGAIN;
>
> if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
> FTGMAC100_RXDES0_CRC_ERR |
> FTGMAC100_RXDES0_FTL |
> FTGMAC100_RXDES0_RUNT |
> FTGMAC100_RXDES0_RX_ODD_NB)) {
> - return -1;
> + return -EAGAIN;
> }
>
> - rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
> + length = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
>
> - debug("%s(): RX buffer %d, %x received\n",
> - __func__, priv->rx_index, rxlen);
> + /* Invalidate received data */
> + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
> + invalidate_dcache_range(data_start, data_end);
> + *packetp = (uchar *)data_start;
>
> - /* invalidate d-cache */
> - dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE);
> -
> - /* pass the packet up to the protocol layers. */
> - net_process_received_packet((void *)curr_des->rxdes2, rxlen);
> -
> - /* release buffer to DMA */
> - curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
> -
> - priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
> -
> - return 0;
> + return length;
> }
>
> -/*
> - * Send a data block via Ethernet
> - */
> -static int ftgmac100_send(struct eth_device *dev, void *packet, int length)
> +static int ftgmac100_send(struct udevice *dev, void *packet, int length)
> {
> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
> - struct ftgmac100_data *priv = dev->priv;
> + struct ftgmac100_data *priv = dev_get_priv(dev);
> + struct ftgmac100 *ftgmac100 = priv->iobase;
> struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
> + ulong des_start = (ulong)curr_des;
> + ulong des_end = des_start +
> + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
> + ulong data_start;
> + ulong data_end;
> + ulong start;
> +
> + invalidate_dcache_range(des_start, des_end);
>
> if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
> - debug("%s(): no TX descriptor available\n", __func__);
> - return -1;
> + dev_err(dev, "no TX descriptor available\n");
> + return -EPERM;
> }
>
> debug("%s(%x, %x)\n", __func__, (int)packet, length);
>
> length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
>
> - memcpy((void *)curr_des->txdes2, (void *)packet, length);
> - dma_map_single((void *)curr_des->txdes2, length, DMA_TO_DEVICE);
> + curr_des->txdes3 = (unsigned int)packet;
> +
> + /* Flush data to be sent */
> + data_start = curr_des->txdes3;
> + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
> + flush_dcache_range(data_start, data_end);
>
> - /* only one descriptor on TXBUF */
> + /* Only one segment on TXBUF */
> curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
> curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
> - FTGMAC100_TXDES0_LTS |
> - FTGMAC100_TXDES0_TXBUF_SIZE(length) |
> - FTGMAC100_TXDES0_TXDMA_OWN ;
> + FTGMAC100_TXDES0_LTS |
> + FTGMAC100_TXDES0_TXBUF_SIZE(length) |
> + FTGMAC100_TXDES0_TXDMA_OWN;
>
> - /* start transmit */
> + /* Flush modified buffer descriptor */
> + flush_dcache_range(des_start, des_end);
> +
> + /* Start transmit */
> writel(1, &ftgmac100->txpd);
>
> + /* Wait until packet is transmitted */
> + start = get_timer(0);
> + while (get_timer(start) < FTGMAC100_TX_TIMEOUT_MS) {
> + invalidate_dcache_range(des_start, des_end);
> + if (!(curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN))
> + break;
> + udelay(10);
> + }
> +
> + if (get_timer(start) >= FTGMAC100_TX_TIMEOUT_MS) {
> + dev_err(dev, "transmit timeout\n");
> + return -ETIMEDOUT;
> + }
> +
> debug("%s(): packet sent\n", __func__);
>
> + /* Move to next descriptor */
> priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
>
> return 0;
> }
>
> -int ftgmac100_initialize(bd_t *bd)
> +static int ftgmac100_write_hwaddr(struct udevice *dev)
> {
> - struct eth_device *dev;
> - struct ftgmac100_data *priv;
> + struct eth_pdata *pdata = dev_get_platdata(dev);
> + struct ftgmac100_data *priv = dev_get_priv(dev);
>
> - dev = malloc(sizeof *dev);
> - if (!dev) {
> - printf("%s(): failed to allocate dev\n", __func__);
> - goto out;
> - }
> + return ftgmac100_set_mac(priv, pdata->enetaddr);
> +}
>
> - /* Transmit and receive descriptors should align to 16 bytes */
> - priv = memalign(16, sizeof(struct ftgmac100_data));
> - if (!priv) {
> - printf("%s(): failed to allocate priv\n", __func__);
> - goto free_dev;
> +static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_platdata(dev);
> + struct ftgmac100_data *priv = dev_get_priv(dev);
> + const char *phy_mode;
> +
> + pdata->iobase = devfdt_get_addr(dev);
> + pdata->phy_interface = -1;
> + phy_mode = dev_read_string(dev, "phy-mode");
> + if (phy_mode)
> + pdata->phy_interface = phy_get_interface_by_name(phy_mode);
> + if (pdata->phy_interface == -1) {
> + dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
> + return -EINVAL;
> }
>
> - memset(dev, 0, sizeof(*dev));
> - memset(priv, 0, sizeof(*priv));
> + pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
>
> - strcpy(dev->name, "FTGMAC100");
> - dev->iobase = CONFIG_FTGMAC100_BASE;
> - dev->init = ftgmac100_init;
> - dev->halt = ftgmac100_halt;
> - dev->send = ftgmac100_send;
> - dev->recv = ftgmac100_recv;
> - dev->priv = priv;
> + return clk_get_bulk(dev, &priv->clks);
> +}
> +
> +static int ftgmac100_probe(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_platdata(dev);
> + struct ftgmac100_data *priv = dev_get_priv(dev);
> + int ret;
>
> - eth_register(dev);
> + priv->iobase = (struct ftgmac100 *)pdata->iobase;
> + priv->phy_mode = pdata->phy_interface;
> + priv->max_speed = pdata->max_speed;
> + priv->phyaddr = 0;
>
> - ftgmac100_reset(dev);
> + ret = clk_enable_bulk(&priv->clks);
> + if (ret)
> + goto out;
>
> - return 1;
> + ret = ftgmac100_mdio_init(priv, dev->seq);
> + if (ret) {
> + dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
> + goto out;
> + }
> +
> + ret = ftgmac100_phy_init(priv, dev);
> + if (ret) {
> + dev_err(dev, "Failed to initialize PHY: %d\n", ret);
> + goto out;
> + }
>
> -free_dev:
> - free(dev);
> out:
> + if (ret)
> + clk_release_bulk(&priv->clks);
> +
> + return ret;
> +}
> +
> +static int ftgmac100_remove(struct udevice *dev)
> +{
> + struct ftgmac100_data *priv = dev_get_priv(dev);
> +
> + free(priv->phydev);
> + mdio_unregister(priv->bus);
> + mdio_free(priv->bus);
> + clk_release_bulk(&priv->clks);
> +
> return 0;
> }
> +
> +static const struct eth_ops ftgmac100_ops = {
> + .start = ftgmac100_start,
> + .send = ftgmac100_send,
> + .recv = ftgmac100_recv,
> + .stop = ftgmac100_stop,
> + .free_pkt = ftgmac100_free_pkt,
> + .write_hwaddr = ftgmac100_write_hwaddr,
> +};
> +
> +static const struct udevice_id ftgmac100_ids[] = {
> + { .compatible = "faraday,ftgmac100" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(ftgmac100) = {
> + .name = "ftgmac100",
> + .id = UCLASS_ETH,
> + .of_match = ftgmac100_ids,
> + .ofdata_to_platdata = ftgmac100_ofdata_to_platdata,
> + .probe = ftgmac100_probe,
> + .remove = ftgmac100_remove,
> + .ops = &ftgmac100_ops,
> + .priv_auto_alloc_size = sizeof(struct ftgmac100_data),
> + .platdata_auto_alloc_size = sizeof(struct eth_pdata),
> + .flags = DM_FLAG_ALLOC_PRIV_DMA,
> +};
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 5441da47d13e..3efdc5dc2fae 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -186,6 +186,32 @@ config FTMAC100
> help
> This MAC is present in Andestech SoCs.
>
> +config FTGMAC100
> + bool "Ftgmac100 Ethernet Support"
> + depends on DM_ETH
> + select PHYLIB
> + help
> + This driver supports the Faraday's FTGMAC100 Gigabit SoC
> + Ethernet controller that can be found on Aspeed SoCs (which
> + include NCSI).
> +
> + It is fully compliant with IEEE 802.3 specification for
> + 10/100 Mbps Ethernet and IEEE 802.3z specification for 1000
> + Mbps Ethernet and includes Reduced Media Independent
> + Interface (RMII) and Reduced Gigabit Media Independent
> + Interface (RGMII) interfaces. It adopts an AHB bus interface
> + and integrates a link list DMA engine with direct M-Bus
> + accesses for transmitting and receiving packets. It has
> + independent TX/RX fifos, supports half and full duplex (1000
> + Mbps mode only supports full duplex), flow control for full
> + duplex and backpressure for half duplex.
> +
> + The FTGMAC100 also implements IP, TCP, UDP checksum offloads
> + and supports IEEE 802.1Q VLAN tag insertion and removal. It
> + offers high-priority transmit queue for QoS and CoS
> + applications.
> +
> +
> config MVGBE
> bool "Marvell Orion5x/Kirkwood network interface support"
> depends on KIRKWOOD || ORION5X
> --
> 2.17.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver
2018-10-09 21:19 ` Joe Hershberger
@ 2018-10-09 21:34 ` Cédric Le Goater
0 siblings, 0 replies; 18+ messages in thread
From: Cédric Le Goater @ 2018-10-09 21:34 UTC (permalink / raw)
To: u-boot
On 10/9/18 11:19 PM, Joe Hershberger wrote:
> On Tue, Oct 9, 2018 at 4:10 PM Cédric Le Goater <clg@kaod.org> wrote:
>>
>> Hello Joe,
>>
>> On 10/9/18 10:44 PM, Joe Hershberger wrote:
>>> On Tue, Oct 9, 2018 at 11:20 AM Simon Glass <sjg@chromium.org> wrote:
>>>>
>>>> Hi Cedric,
>>>>
>>>> On 2 October 2018 at 09:48, Cédric Le Goater <clg@kaod.org> wrote:
>>>>> On 10/2/18 1:22 PM, Simon Glass wrote:
>>>>>> On 1 October 2018 at 01:53, Cédric Le Goater <clg@kaod.org> wrote:
>>>>>>> There are too many changes in the following patch fixing support for
>>>>>>> the Faraday ftgmac100 controller. To ease the review, remove the whole
>>>>>>> file which is not compiled anymore today (no Kconfig option for the
>>>>>>> driver).
>>>>>>>
>>>>>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>>>>>> ---
>>>>>>> drivers/net/ftgmac100.h | 242 -----------------
>>>>>>> include/netdev.h | 1 -
>>>>>>> drivers/net/ftgmac100.c | 582 ----------------------------------------
>>>>>>> drivers/net/Makefile | 1 -
>>>>>>> 4 files changed, 826 deletions(-)
>>>>>>> delete mode 100644 drivers/net/ftgmac100.h
>>>>>>> delete mode 100644 drivers/net/ftgmac100.c
>>>>>>
>>>>>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>>>>>
>>>>>> Assuming Joe is happy to remove this and start again? While it is
>>>>>> easier to review, it does remove commit history which is bad.
>>>>>
>>>>> yes.
>>>
>>> I have to believe there is a decent amount that is the same, no? I
>>> would prefer not to break git blame unless completely necessary.
>>
>> OK.
>>
>>>>> The changes are so numerous that it is really difficult to understand
>>>>> what the resulting driver looks like and splitting the changes would
>>>>> have been nightmarish. So I took the short path as the driver was not
>>>>> compiled anymore, but this is questionable.
>>>
>>> How many changes are we talking about here?
>>
>> below is a merge of patch one and two. If you think it's fine, I will
>> send a v3 with a couple more cleanups on the Aspeed AST2500 DTS file.
>
> Can you try to separate the cosmetic changes from the substantive ones?
I will in v3.
Thanks,
C.
> Thanks,
> -Joe
>
>>
>> Thanks,
>>
>> C.
>>
>>>
>>>>>
>>>>> I can also resend without the initial removal patch but wouldn't it
>>>>> invalidate the review at the same time ?
>>>>
>>>> Yes but it is not hard to re-review in this case.
>>>>
>>>> Regards,
>>>> Simon
>>>
>>> Thanks,
>>> -Joe
>>>
>>
>>
>> From 634d9707525f7a243835f84d5beb9b0e1a673d32 Mon Sep 17 00:00:00 2001
>> From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>
>> Date: Fri, 7 Sep 2018 19:15:57 +0200
>> Subject: [PATCH] net: fix support for the Faraday ftgmac100 controller
>> MIME-Version: 1.0
>> Content-Type: text/plain; charset=UTF-8
>> Content-Transfer-Encoding: 8bit
>>
>> The driver is based on the previous one and adds the same support for
>> the Faraday ftgmac100 controller with MAC and MDIO bus support for
>> RGMII/RMII modes. Driver model support was added as well as some
>> enhancements and fixes.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> drivers/net/ftgmac100.h | 158 ++++-----
>> include/netdev.h | 1 -
>> drivers/net/ftgmac100.c | 742 +++++++++++++++++++---------------------
>> drivers/net/Kconfig | 26 ++
>> 4 files changed, 459 insertions(+), 468 deletions(-)
>>
>> diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h
>> index ffbe1f3e3fa7..9a789e4d5bee 100644
>> --- a/drivers/net/ftgmac100.h
>> +++ b/drivers/net/ftgmac100.h
>> @@ -70,48 +70,48 @@ struct ftgmac100 {
>> /*
>> * Interrupt status register & interrupt enable register
>> */
>> -#define FTGMAC100_INT_RPKT_BUF (1 << 0)
>> -#define FTGMAC100_INT_RPKT_FIFO (1 << 1)
>> -#define FTGMAC100_INT_NO_RXBUF (1 << 2)
>> -#define FTGMAC100_INT_RPKT_LOST (1 << 3)
>> -#define FTGMAC100_INT_XPKT_ETH (1 << 4)
>> -#define FTGMAC100_INT_XPKT_FIFO (1 << 5)
>> -#define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
>> -#define FTGMAC100_INT_XPKT_LOST (1 << 7)
>> -#define FTGMAC100_INT_AHB_ERR (1 << 8)
>> -#define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
>> -#define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
>> +#define FTGMAC100_INT_RPKT_BUF BIT(0)
>> +#define FTGMAC100_INT_RPKT_FIFO BIT(1)
>> +#define FTGMAC100_INT_NO_RXBUF BIT(2)
>> +#define FTGMAC100_INT_RPKT_LOST BIT(3)
>> +#define FTGMAC100_INT_XPKT_ETH BIT(4)
>> +#define FTGMAC100_INT_XPKT_FIFO BIT(5)
>> +#define FTGMAC100_INT_NO_NPTXBUF BIT(6)
>> +#define FTGMAC100_INT_XPKT_LOST BIT(7)
>> +#define FTGMAC100_INT_AHB_ERR BIT(8)
>> +#define FTGMAC100_INT_PHYSTS_CHG BIT(9)
>> +#define FTGMAC100_INT_NO_HPTXBUF BIT(10)
>>
>> /*
>> * Interrupt timer control register
>> */
>> #define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
>> #define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
>> -#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7)
>> +#define FTGMAC100_ITC_RXINT_TIME_SEL BIT(7)
>> #define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
>> #define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
>> -#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15)
>> +#define FTGMAC100_ITC_TXINT_TIME_SEL BIT(15)
>>
>> /*
>> * Automatic polling timer control register
>> */
>> #define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
>> -#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
>> +#define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4)
>> #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
>> -#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
>> +#define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12)
>>
>> /*
>> * DMA burst length and arbitration control register
>> */
>> #define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0)
>> #define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3)
>> -#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6)
>> +#define FTGMAC100_DBLAC_RX_THR_EN BIT(6)
>> #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8)
>> #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
>> #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12)
>> #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16)
>> #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
>> -#define FTGMAC100_DBLAC_IFG_INC (1 << 23)
>> +#define FTGMAC100_DBLAC_IFG_INC BIT(23)
>>
>> /*
>> * DMA FIFO status register
>> @@ -122,12 +122,12 @@ struct ftgmac100 {
>> #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf)
>> #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3)
>> #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf)
>> -#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26)
>> -#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27)
>> -#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28)
>> -#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29)
>> -#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30)
>> -#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31)
>> +#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY BIT(26)
>> +#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY BIT(27)
>> +#define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28)
>> +#define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29)
>> +#define FTGMAC100_DMAFIFOS_RXDMA_REQ BIT(30)
>> +#define FTGMAC100_DMAFIFOS_TXDMA_REQ BIT(31)
>>
>> /*
>> * Receive buffer size register
>> @@ -137,26 +137,26 @@ struct ftgmac100 {
>> /*
>> * MAC control register
>> */
>> -#define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
>> -#define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
>> -#define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
>> -#define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
>> -#define FTGMAC100_MACCR_RM_VLAN (1 << 4)
>> -#define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
>> -#define FTGMAC100_MACCR_LOOP_EN (1 << 6)
>> -#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
>> -#define FTGMAC100_MACCR_FULLDUP (1 << 8)
>> -#define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
>> -#define FTGMAC100_MACCR_CRC_APD (1 << 10)
>> -#define FTGMAC100_MACCR_RX_RUNT (1 << 12)
>> -#define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
>> -#define FTGMAC100_MACCR_RX_ALL (1 << 14)
>> -#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
>> -#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
>> -#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
>> -#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
>> -#define FTGMAC100_MACCR_FAST_MODE (1 << 19)
>> -#define FTGMAC100_MACCR_SW_RST (1 << 31)
>> +#define FTGMAC100_MACCR_TXDMA_EN BIT(0)
>> +#define FTGMAC100_MACCR_RXDMA_EN BIT(1)
>> +#define FTGMAC100_MACCR_TXMAC_EN BIT(2)
>> +#define FTGMAC100_MACCR_RXMAC_EN BIT(3)
>> +#define FTGMAC100_MACCR_RM_VLAN BIT(4)
>> +#define FTGMAC100_MACCR_HPTXR_EN BIT(5)
>> +#define FTGMAC100_MACCR_LOOP_EN BIT(6)
>> +#define FTGMAC100_MACCR_ENRX_IN_HALFTX BIT(7)
>> +#define FTGMAC100_MACCR_FULLDUP BIT(8)
>> +#define FTGMAC100_MACCR_GIGA_MODE BIT(9)
>> +#define FTGMAC100_MACCR_CRC_APD BIT(10)
>> +#define FTGMAC100_MACCR_RX_RUNT BIT(12)
>> +#define FTGMAC100_MACCR_JUMBO_LF BIT(13)
>> +#define FTGMAC100_MACCR_RX_ALL BIT(14)
>> +#define FTGMAC100_MACCR_HT_MULTI_EN BIT(15)
>> +#define FTGMAC100_MACCR_RX_MULTIPKT BIT(16)
>> +#define FTGMAC100_MACCR_RX_BROADPKT BIT(17)
>> +#define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18)
>> +#define FTGMAC100_MACCR_FAST_MODE BIT(19)
>> +#define FTGMAC100_MACCR_SW_RST BIT(31)
>>
>> /*
>> * PHY control register
>> @@ -165,8 +165,8 @@ struct ftgmac100 {
>> #define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f)
>> #define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16)
>> #define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21)
>> -#define FTGMAC100_PHYCR_MIIRD (1 << 26)
>> -#define FTGMAC100_PHYCR_MIIWR (1 << 27)
>> +#define FTGMAC100_PHYCR_MIIRD BIT(26)
>> +#define FTGMAC100_PHYCR_MIIWR BIT(27)
>>
>> /*
>> * PHY data register
>> @@ -182,23 +182,23 @@ struct ftgmac100_txdes {
>> unsigned int txdes1;
>> unsigned int txdes2; /* not used by HW */
>> unsigned int txdes3; /* TXBUF_BADR */
>> -} __attribute__ ((aligned(16)));
>> +} __aligned(16);
>>
>> #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
>> -#define FTGMAC100_TXDES0_EDOTR (1 << 15)
>> -#define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
>> -#define FTGMAC100_TXDES0_LTS (1 << 28)
>> -#define FTGMAC100_TXDES0_FTS (1 << 29)
>> -#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
>> +#define FTGMAC100_TXDES0_EDOTR BIT(15)
>> +#define FTGMAC100_TXDES0_CRC_ERR BIT(19)
>> +#define FTGMAC100_TXDES0_LTS BIT(28)
>> +#define FTGMAC100_TXDES0_FTS BIT(29)
>> +#define FTGMAC100_TXDES0_TXDMA_OWN BIT(31)
>>
>> #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
>> -#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
>> -#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
>> -#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
>> -#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
>> -#define FTGMAC100_TXDES1_LLC (1 << 22)
>> -#define FTGMAC100_TXDES1_TX2FIC (1 << 30)
>> -#define FTGMAC100_TXDES1_TXIC (1 << 31)
>> +#define FTGMAC100_TXDES1_INS_VLANTAG BIT(16)
>> +#define FTGMAC100_TXDES1_TCP_CHKSUM BIT(17)
>> +#define FTGMAC100_TXDES1_UDP_CHKSUM BIT(18)
>> +#define FTGMAC100_TXDES1_IP_CHKSUM BIT(19)
>> +#define FTGMAC100_TXDES1_LLC BIT(22)
>> +#define FTGMAC100_TXDES1_TX2FIC BIT(30)
>> +#define FTGMAC100_TXDES1_TXIC BIT(31)
>>
>> /*
>> * Receive descriptor, aligned to 16 bytes
>> @@ -208,23 +208,23 @@ struct ftgmac100_rxdes {
>> unsigned int rxdes1;
>> unsigned int rxdes2; /* not used by HW */
>> unsigned int rxdes3; /* RXBUF_BADR */
>> -} __attribute__ ((aligned(16)));
>> +} __aligned(16);
>>
>> #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff)
>> -#define FTGMAC100_RXDES0_EDORR (1 << 15)
>> -#define FTGMAC100_RXDES0_MULTICAST (1 << 16)
>> -#define FTGMAC100_RXDES0_BROADCAST (1 << 17)
>> -#define FTGMAC100_RXDES0_RX_ERR (1 << 18)
>> -#define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
>> -#define FTGMAC100_RXDES0_FTL (1 << 20)
>> -#define FTGMAC100_RXDES0_RUNT (1 << 21)
>> -#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
>> -#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
>> -#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
>> -#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
>> -#define FTGMAC100_RXDES0_LRS (1 << 28)
>> -#define FTGMAC100_RXDES0_FRS (1 << 29)
>> -#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
>> +#define FTGMAC100_RXDES0_EDORR BIT(15)
>> +#define FTGMAC100_RXDES0_MULTICAST BIT(16)
>> +#define FTGMAC100_RXDES0_BROADCAST BIT(17)
>> +#define FTGMAC100_RXDES0_RX_ERR BIT(18)
>> +#define FTGMAC100_RXDES0_CRC_ERR BIT(19)
>> +#define FTGMAC100_RXDES0_FTL BIT(20)
>> +#define FTGMAC100_RXDES0_RUNT BIT(21)
>> +#define FTGMAC100_RXDES0_RX_ODD_NB BIT(22)
>> +#define FTGMAC100_RXDES0_FIFO_FULL BIT(23)
>> +#define FTGMAC100_RXDES0_PAUSE_OPCODE BIT(24)
>> +#define FTGMAC100_RXDES0_PAUSE_FRAME BIT(25)
>> +#define FTGMAC100_RXDES0_LRS BIT(28)
>> +#define FTGMAC100_RXDES0_FRS BIT(29)
>> +#define FTGMAC100_RXDES0_RXPKT_RDY BIT(31)
>>
>> #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
>> #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
>> @@ -232,11 +232,11 @@ struct ftgmac100_rxdes {
>> #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
>> #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
>> #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
>> -#define FTGMAC100_RXDES1_LLC (1 << 22)
>> -#define FTGMAC100_RXDES1_DF (1 << 23)
>> -#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
>> -#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
>> -#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
>> -#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
>> +#define FTGMAC100_RXDES1_LLC BIT(22)
>> +#define FTGMAC100_RXDES1_DF BIT(23)
>> +#define FTGMAC100_RXDES1_VLANTAG_AVAIL BIT(24)
>> +#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR BIT(25)
>> +#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26)
>> +#define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27)
>>
>> #endif /* __FTGMAC100_H */
>> diff --git a/include/netdev.h b/include/netdev.h
>> index 55001625fb92..0a1a3a2d8da2 100644
>> --- a/include/netdev.h
>> +++ b/include/netdev.h
>> @@ -43,7 +43,6 @@ int ethoc_initialize(u8 dev_num, int base_addr);
>> int fec_initialize (bd_t *bis);
>> int fecmxc_initialize(bd_t *bis);
>> int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
>> -int ftgmac100_initialize(bd_t *bits);
>> int ftmac100_initialize(bd_t *bits);
>> int ftmac110_initialize(bd_t *bits);
>> void gt6426x_eth_initialize(bd_t *bis);
>> diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
>> index c996f5f4a167..4596385d68cf 100644
>> --- a/drivers/net/ftgmac100.c
>> +++ b/drivers/net/ftgmac100.c
>> @@ -7,265 +7,165 @@
>> *
>> * (C) Copyright 2010 Andes Technology
>> * Macpaul Lin <macpaul@andestech.com>
>> + *
>> + * Copyright (C) 2018, IBM Corporation.
>> */
>>
>> -#include <config.h>
>> -#include <common.h>
>> -#include <malloc.h>
>> +#include <clk.h>
>> +#include <dm.h>
>> +#include <miiphy.h>
>> #include <net.h>
>> -#include <asm/io.h>
>> -#include <asm/dma-mapping.h>
>> -#include <linux/mii.h>
>> +#include <linux/io.h>
>> +#include <linux/iopoll.h>
>>
>> #include "ftgmac100.h"
>>
>> -#define ETH_ZLEN 60
>> -#define CFG_XBUF_SIZE 1536
>> +/* Min frame ethernet frame size without FCS */
>> +#define ETH_ZLEN 60
>>
>> -/* RBSR - hw default init value is also 0x640 */
>> -#define RBSR_DEFAULT_VALUE 0x640
>> +/* Receive Buffer Size Register - HW default is 0x640 */
>> +#define FTGMAC100_RBSR_DEFAULT 0x640
>>
>> /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
>> -#define PKTBUFSTX 4 /* must be power of 2 */
>> +#define PKTBUFSTX 4
>>
>> -struct ftgmac100_data {
>> - ulong txdes_dma;
>> - struct ftgmac100_txdes *txdes;
>> - ulong rxdes_dma;
>> - struct ftgmac100_rxdes *rxdes;
>> - int tx_index;
>> - int rx_index;
>> - int phy_addr;
>> -};
>> +/* Timeout for transmit */
>> +#define FTGMAC100_TX_TIMEOUT_MS 1000
>> +
>> +/* Timeout for a mdio read/write operation */
>> +#define FTGMAC100_MDIO_TIMEOUT_USEC 10000
>>
>> /*
>> - * struct mii_bus functions
>> + * MDC clock cycle threshold
>> + *
>> + * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
>> */
>> -static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr,
>> - int regnum)
>> -{
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> - int phycr;
>> - int i;
>> -
>> - phycr = readl(&ftgmac100->phycr);
>> +#define MDC_CYCTHR 0x34
>>
>> - /* preserve MDC cycle threshold */
>> - phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
>> +/**
>> + * struct ftgmac100_data - private data for the FTGMAC100 driver
>> + *
>> + * @iobase: The base address of the hardware registers
>> + * @txdes: The array of transmit descriptors
>> + * @rxdes: The array of receive descriptors
>> + * @tx_index: Transmit descriptor index in @txdes
>> + * @rx_index: Receive descriptor index in @rxdes
>> + * @phyaddr: The PHY interface address to use
>> + * @phydev: The PHY device backing the MAC
>> + * @bus: The mdio bus
>> + * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
>> + * @max_speed: Maximum speed of Ethernet connection supported by MAC
>> + * @clks: The bulk of clocks assigned to the device in the DT
>> + */
>> +struct ftgmac100_data {
>> + struct ftgmac100 *iobase;
>>
>> - phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
>> - | FTGMAC100_PHYCR_REGAD(regnum)
>> - | FTGMAC100_PHYCR_MIIRD;
>> + struct ftgmac100_txdes txdes[PKTBUFSTX];
>> + struct ftgmac100_rxdes rxdes[PKTBUFSRX];
>> + int tx_index;
>> + int rx_index;
>>
>> - writel(phycr, &ftgmac100->phycr);
>> + u32 phyaddr;
>> + struct phy_device *phydev;
>> + struct mii_dev *bus;
>> + u32 phy_mode;
>> + u32 max_speed;
>>
>> - for (i = 0; i < 10; i++) {
>> - phycr = readl(&ftgmac100->phycr);
>> + struct clk_bulk clks;
>> +};
>>
>> - if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
>> - int data;
>> +static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
>> + int reg_addr)
>> +{
>> + struct ftgmac100_data *priv = bus->priv;
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>> + int phycr;
>> + int data;
>> + int ret;
>>
>> - data = readl(&ftgmac100->phydata);
>> - return FTGMAC100_PHYDATA_MIIRDATA(data);
>> - }
>> + phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
>> + FTGMAC100_PHYCR_PHYAD(phy_addr) |
>> + FTGMAC100_PHYCR_REGAD(reg_addr) |
>> + FTGMAC100_PHYCR_MIIRD;
>> + writel(phycr, &ftgmac100->phycr);
>>
>> - mdelay(10);
>> + ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
>> + !(phycr & FTGMAC100_PHYCR_MIIRD),
>> + FTGMAC100_MDIO_TIMEOUT_USEC);
>> + if (ret) {
>> + pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
>> + priv->phydev->dev->name, phy_addr, reg_addr);
>> + return ret;
>> }
>>
>> - debug("mdio read timed out\n");
>> - return -1;
>> + data = readl(&ftgmac100->phydata);
>> +
>> + return FTGMAC100_PHYDATA_MIIRDATA(data);
>> }
>>
>> -static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr,
>> - int regnum, u16 value)
>> +static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
>> + int reg_addr, u16 value)
>> {
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> + struct ftgmac100_data *priv = bus->priv;
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>> int phycr;
>> int data;
>> - int i;
>> -
>> - phycr = readl(&ftgmac100->phycr);
>> -
>> - /* preserve MDC cycle threshold */
>> - phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
>> -
>> - phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
>> - | FTGMAC100_PHYCR_REGAD(regnum)
>> - | FTGMAC100_PHYCR_MIIWR;
>> + int ret;
>>
>> + phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
>> + FTGMAC100_PHYCR_PHYAD(phy_addr) |
>> + FTGMAC100_PHYCR_REGAD(reg_addr) |
>> + FTGMAC100_PHYCR_MIIWR;
>> data = FTGMAC100_PHYDATA_MIIWDATA(value);
>>
>> writel(data, &ftgmac100->phydata);
>> writel(phycr, &ftgmac100->phycr);
>>
>> - for (i = 0; i < 10; i++) {
>> - phycr = readl(&ftgmac100->phycr);
>> -
>> - if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) {
>> - debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \
>> - "phy_addr: %x\n", phy_addr);
>> - return 0;
>> - }
>> -
>> - mdelay(1);
>> + ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
>> + !(phycr & FTGMAC100_PHYCR_MIIWR),
>> + FTGMAC100_MDIO_TIMEOUT_USEC);
>> + if (ret) {
>> + pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
>> + priv->phydev->dev->name, phy_addr, reg_addr);
>> }
>>
>> - debug("mdio write timed out\n");
>> - return -1;
>> + return ret;
>> }
>>
>> -int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value)
>> +static int ftgmac100_mdio_init(struct ftgmac100_data *priv, int dev_id)
>> {
>> - *value = ftgmac100_mdiobus_read(dev , addr, reg);
>> -
>> - if (*value == -1)
>> - return -1;
>> -
>> - return 0;
>> -}
>> -
>> -int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value)
>> -{
>> - if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1)
>> - return -1;
>> -
>> - return 0;
>> -}
>> -
>> -static int ftgmac100_phy_reset(struct eth_device *dev)
>> -{
>> - struct ftgmac100_data *priv = dev->priv;
>> - int i;
>> - u16 status, adv;
>> -
>> - adv = ADVERTISE_CSMA | ADVERTISE_ALL;
>> -
>> - ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv);
>> + struct mii_dev *bus;
>> + int ret;
>>
>> - printf("%s: Starting autonegotiation...\n", dev->name);
>> + bus = mdio_alloc();
>> + if (!bus)
>> + return -ENOMEM;
>>
>> - ftgmac100_phy_write(dev, priv->phy_addr,
>> - MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
>> + bus->read = ftgmac100_mdio_read;
>> + bus->write = ftgmac100_mdio_write;
>> + bus->priv = priv;
>>
>> - for (i = 0; i < 100000 / 100; i++) {
>> - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
>> -
>> - if (status & BMSR_ANEGCOMPLETE)
>> - break;
>> - mdelay(1);
>> + ret = mdio_register_seq(bus, dev_id);
>> + if (ret) {
>> + free(bus);
>> + return ret;
>> }
>>
>> - if (status & BMSR_ANEGCOMPLETE) {
>> - printf("%s: Autonegotiation complete\n", dev->name);
>> - } else {
>> - printf("%s: Autonegotiation timed out (status=0x%04x)\n",
>> - dev->name, status);
>> - return 0;
>> - }
>> + priv->bus = bus;
>>
>> - return 1;
>> + return 0;
>> }
>>
>> -static int ftgmac100_phy_init(struct eth_device *dev)
>> +static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
>> {
>> - struct ftgmac100_data *priv = dev->priv;
>> -
>> - int phy_addr;
>> - u16 phy_id, status, adv, lpa, stat_ge;
>> - int media, speed, duplex;
>> - int i;
>> -
>> - /* Check if the PHY is up to snuff... */
>> - for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) {
>> -
>> - ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id);
>> -
>> - /*
>> - * When it is unable to found PHY,
>> - * the interface usually return 0xffff or 0x0000
>> - */
>> - if (phy_id != 0xffff && phy_id != 0x0) {
>> - printf("%s: found PHY at 0x%02x\n",
>> - dev->name, phy_addr);
>> - priv->phy_addr = phy_addr;
>> - break;
>> - }
>> - }
>> -
>> - if (phy_id == 0xffff || phy_id == 0x0) {
>> - printf("%s: no PHY present\n", dev->name);
>> - return 0;
>> - }
>> -
>> - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
>> -
>> - if (!(status & BMSR_LSTATUS)) {
>> - /* Try to re-negotiate if we don't have link already. */
>> - ftgmac100_phy_reset(dev);
>> -
>> - for (i = 0; i < 100000 / 100; i++) {
>> - ftgmac100_phy_read(dev, priv->phy_addr,
>> - MII_BMSR, &status);
>> - if (status & BMSR_LSTATUS)
>> - break;
>> - udelay(100);
>> - }
>> - }
>> -
>> - if (!(status & BMSR_LSTATUS)) {
>> - printf("%s: link down\n", dev->name);
>> - return 0;
>> - }
>> -
>> -#ifdef CONFIG_FTGMAC100_EGIGA
>> - /* 1000 Base-T Status Register */
>> - ftgmac100_phy_read(dev, priv->phy_addr,
>> - MII_STAT1000, &stat_ge);
>> -
>> - speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF)
>> - ? 1 : 0);
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>> + struct phy_device *phydev = priv->phydev;
>> + u32 maccr;
>>
>> - duplex = ((stat_ge & LPA_1000FULL)
>> - ? 1 : 0);
>> -
>> - if (speed) { /* Speed is 1000 */
>> - printf("%s: link up, 1000bps %s-duplex\n",
>> - dev->name, duplex ? "full" : "half");
>> - return 0;
>> + if (!phydev->link) {
>> + dev_err(phydev->dev, "No link\n");
>> + return -EREMOTEIO;
>> }
>> -#endif
>> -
>> - ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv);
>> - ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa);
>> -
>> - media = mii_nway_result(lpa & adv);
>> - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0);
>> - duplex = (media & ADVERTISE_FULL) ? 1 : 0;
>> -
>> - printf("%s: link up, %sMbps %s-duplex\n",
>> - dev->name, speed ? "100" : "10", duplex ? "full" : "half");
>> -
>> - return 1;
>> -}
>> -
>> -static int ftgmac100_update_link_speed(struct eth_device *dev)
>> -{
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> - struct ftgmac100_data *priv = dev->priv;
>> -
>> - unsigned short stat_fe;
>> - unsigned short stat_ge;
>> - unsigned int maccr;
>> -
>> -#ifdef CONFIG_FTGMAC100_EGIGA
>> - /* 1000 Base-T Status Register */
>> - ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge);
>> -#endif
>> -
>> - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe);
>> -
>> - if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */
>> - return 0;
>>
>> /* read MAC control register and clear related bits */
>> maccr = readl(&ftgmac100->maccr) &
>> @@ -273,173 +173,130 @@ static int ftgmac100_update_link_speed(struct eth_device *dev)
>> FTGMAC100_MACCR_FAST_MODE |
>> FTGMAC100_MACCR_FULLDUP);
>>
>> -#ifdef CONFIG_FTGMAC100_EGIGA
>> - if (stat_ge & LPA_1000FULL) {
>> - /* set gmac for 1000BaseTX and Full Duplex */
>> - maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP;
>> - }
>> -
>> - if (stat_ge & LPA_1000HALF) {
>> - /* set gmac for 1000BaseTX and Half Duplex */
>> + if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
>> maccr |= FTGMAC100_MACCR_GIGA_MODE;
>> - }
>> -#endif
>> -
>> - if (stat_fe & BMSR_100FULL) {
>> - /* set MII for 100BaseTX and Full Duplex */
>> - maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP;
>> - }
>> -
>> - if (stat_fe & BMSR_10FULL) {
>> - /* set MII for 10BaseT and Full Duplex */
>> - maccr |= FTGMAC100_MACCR_FULLDUP;
>> - }
>>
>> - if (stat_fe & BMSR_100HALF) {
>> - /* set MII for 100BaseTX and Half Duplex */
>> + if (phydev->speed == 100)
>> maccr |= FTGMAC100_MACCR_FAST_MODE;
>> - }
>>
>> - if (stat_fe & BMSR_10HALF) {
>> - /* set MII for 10BaseT and Half Duplex */
>> - /* we have already clear these bits, do nothing */
>> - ;
>> - }
>> + if (phydev->duplex)
>> + maccr |= FTGMAC100_MACCR_FULLDUP;
>>
>> /* update MII config into maccr */
>> writel(maccr, &ftgmac100->maccr);
>>
>> - return 1;
>> + return 0;
>> }
>>
>> -/*
>> - * Reset MAC
>> - */
>> -static void ftgmac100_reset(struct eth_device *dev)
>> +static int ftgmac100_phy_init(struct ftgmac100_data *priv, void *dev)
>> {
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> + struct phy_device *phydev;
>> + int ret;
>> +
>> + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->phy_mode);
>> + if (!phydev)
>> + return -ENODEV;
>> +
>> + phydev->supported &= PHY_GBIT_FEATURES;
>> + if (priv->max_speed) {
>> + ret = phy_set_supported(phydev, priv->max_speed);
>> + if (ret)
>> + return ret;
>> + }
>> + phydev->advertising = phydev->supported;
>> + priv->phydev = phydev;
>> + phy_config(phydev);
>> +
>> + return 0;
>> +}
>>
>> - debug("%s()\n", __func__);
>> +static void ftgmac100_reset(struct ftgmac100_data *priv)
>> +{
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>>
>> - writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr);
>> + setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
>>
>> while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
>> ;
>> }
>>
>> -/*
>> - * Set MAC address
>> - */
>> -static void ftgmac100_set_mac(struct eth_device *dev,
>> - const unsigned char *mac)
>> +static int ftgmac100_set_mac(struct ftgmac100_data *priv,
>> + const unsigned char *mac)
>> {
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>> unsigned int maddr = mac[0] << 8 | mac[1];
>> unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
>>
>> - debug("%s(%x %x)\n", __func__, maddr, laddr);
>> -
>> writel(maddr, &ftgmac100->mac_madr);
>> writel(laddr, &ftgmac100->mac_ladr);
>> -}
>>
>> -static void ftgmac100_set_mac_from_env(struct eth_device *dev)
>> -{
>> - eth_env_get_enetaddr("ethaddr", dev->enetaddr);
>> -
>> - ftgmac100_set_mac(dev, dev->enetaddr);
>> + return 0;
>> }
>>
>> -/*
>> - * disable transmitter, receiver
>> - */
>> -static void ftgmac100_halt(struct eth_device *dev)
>> +static void ftgmac100_stop(struct udevice *dev)
>> {
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> -
>> - debug("%s()\n", __func__);
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>>
>> writel(0, &ftgmac100->maccr);
>> +
>> + phy_shutdown(priv->phydev);
>> }
>>
>> -static int ftgmac100_init(struct eth_device *dev, bd_t *bd)
>> +static int ftgmac100_start(struct udevice *dev)
>> {
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> - struct ftgmac100_data *priv = dev->priv;
>> - struct ftgmac100_txdes *txdes;
>> - struct ftgmac100_rxdes *rxdes;
>> + struct eth_pdata *plat = dev_get_platdata(dev);
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>> + struct phy_device *phydev = priv->phydev;
>> unsigned int maccr;
>> - void *buf;
>> + ulong start, end;
>> + int ret;
>> int i;
>>
>> - debug("%s()\n", __func__);
>> -
>> - if (!priv->txdes) {
>> - txdes = dma_alloc_coherent(
>> - sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
>> - if (!txdes)
>> - panic("ftgmac100: out of memory\n");
>> - memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
>> - priv->txdes = txdes;
>> - }
>> - txdes = priv->txdes;
>> -
>> - if (!priv->rxdes) {
>> - rxdes = dma_alloc_coherent(
>> - sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
>> - if (!rxdes)
>> - panic("ftgmac100: out of memory\n");
>> - memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
>> - priv->rxdes = rxdes;
>> - }
>> - rxdes = priv->rxdes;
>> + ftgmac100_reset(priv);
>>
>> /* set the ethernet address */
>> - ftgmac100_set_mac_from_env(dev);
>> + ftgmac100_set_mac(priv, plat->enetaddr);
>>
>> /* disable all interrupts */
>> writel(0, &ftgmac100->ier);
>>
>> - /* initialize descriptors */
>> + /* initialize descriptor tables */
>> priv->tx_index = 0;
>> priv->rx_index = 0;
>>
>> - txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
>> - rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
>> -
>> for (i = 0; i < PKTBUFSTX; i++) {
>> - /* TXBUF_BADR */
>> - if (!txdes[i].txdes2) {
>> - buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
>> - if (!buf)
>> - panic("ftgmac100: out of memory\n");
>> - txdes[i].txdes3 = virt_to_phys(buf);
>> - txdes[i].txdes2 = (uint)buf;
>> - }
>> - txdes[i].txdes1 = 0;
>> + priv->txdes[i].txdes3 = 0;
>> + priv->txdes[i].txdes0 = 0;
>> }
>> + priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
>> +
>> + start = (ulong)&priv->txdes[0];
>> + end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
>> + flush_dcache_range(start, end);
>>
>> for (i = 0; i < PKTBUFSRX; i++) {
>> - /* RXBUF_BADR */
>> - if (!rxdes[i].rxdes2) {
>> - buf = net_rx_packets[i];
>> - rxdes[i].rxdes3 = virt_to_phys(buf);
>> - rxdes[i].rxdes2 = (uint)buf;
>> - }
>> - rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
>> + priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
>> + priv->rxdes[i].rxdes0 = 0;
>> }
>> + priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
>> +
>> + start = (ulong)&priv->rxdes[0];
>> + end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
>> + flush_dcache_range(start, end);
>>
>> /* transmit ring */
>> - writel(priv->txdes_dma, &ftgmac100->txr_badr);
>> + writel((u32)priv->txdes, &ftgmac100->txr_badr);
>>
>> /* receive ring */
>> - writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
>> + writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
>>
>> /* poll receive descriptor automatically */
>> writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
>>
>> /* config receive buffer size register */
>> - writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr);
>> + writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
>>
>> /* enable transmitter, receiver */
>> maccr = FTGMAC100_MACCR_TXMAC_EN |
>> @@ -453,130 +310,239 @@ static int ftgmac100_init(struct eth_device *dev, bd_t *bd)
>>
>> writel(maccr, &ftgmac100->maccr);
>>
>> - if (!ftgmac100_phy_init(dev)) {
>> - if (!ftgmac100_update_link_speed(dev))
>> - return -1;
>> + ret = phy_startup(phydev);
>> + if (ret) {
>> + dev_err(phydev->dev, "Could not start PHY\n");
>> + return ret;
>> + }
>> +
>> + ret = ftgmac100_phy_adjust_link(priv);
>> + if (ret) {
>> + dev_err(phydev->dev, "Could not adjust link\n");
>> + return ret;
>> }
>>
>> + printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
>> + phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
>> +
>> return 0;
>> }
>>
>> -/*
>> - * Get a data block via Ethernet
>> - */
>> -static int ftgmac100_recv(struct eth_device *dev)
>> +static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
>> +{
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
>> + ulong des_start = (ulong)curr_des;
>> + ulong des_end = des_start +
>> + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
>> +
>> + /* Release buffer to DMA and flush descriptor */
>> + curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
>> + flush_dcache_range(des_start, des_end);
>> +
>> + /* Move to next descriptor */
>> + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
>> +
>> + return 0;
>> +}
>> +
>> +static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
>> {
>> - struct ftgmac100_data *priv = dev->priv;
>> - struct ftgmac100_rxdes *curr_des;
>> - unsigned short rxlen;
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
>> + int length;
>> + ulong des_start = (ulong)curr_des;
>> + ulong des_end = des_start +
>> + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
>> + ulong data_start = curr_des->rxdes3;
>> + ulong data_end;
>>
>> - curr_des = &priv->rxdes[priv->rx_index];
>> + invalidate_dcache_range(des_start, des_end);
>>
>> if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
>> - return -1;
>> + return -EAGAIN;
>>
>> if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
>> FTGMAC100_RXDES0_CRC_ERR |
>> FTGMAC100_RXDES0_FTL |
>> FTGMAC100_RXDES0_RUNT |
>> FTGMAC100_RXDES0_RX_ODD_NB)) {
>> - return -1;
>> + return -EAGAIN;
>> }
>>
>> - rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
>> + length = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
>>
>> - debug("%s(): RX buffer %d, %x received\n",
>> - __func__, priv->rx_index, rxlen);
>> + /* Invalidate received data */
>> + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
>> + invalidate_dcache_range(data_start, data_end);
>> + *packetp = (uchar *)data_start;
>>
>> - /* invalidate d-cache */
>> - dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE);
>> -
>> - /* pass the packet up to the protocol layers. */
>> - net_process_received_packet((void *)curr_des->rxdes2, rxlen);
>> -
>> - /* release buffer to DMA */
>> - curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
>> -
>> - priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
>> -
>> - return 0;
>> + return length;
>> }
>>
>> -/*
>> - * Send a data block via Ethernet
>> - */
>> -static int ftgmac100_send(struct eth_device *dev, void *packet, int length)
>> +static int ftgmac100_send(struct udevice *dev, void *packet, int length)
>> {
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> - struct ftgmac100_data *priv = dev->priv;
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>> struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
>> + ulong des_start = (ulong)curr_des;
>> + ulong des_end = des_start +
>> + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
>> + ulong data_start;
>> + ulong data_end;
>> + ulong start;
>> +
>> + invalidate_dcache_range(des_start, des_end);
>>
>> if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
>> - debug("%s(): no TX descriptor available\n", __func__);
>> - return -1;
>> + dev_err(dev, "no TX descriptor available\n");
>> + return -EPERM;
>> }
>>
>> debug("%s(%x, %x)\n", __func__, (int)packet, length);
>>
>> length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
>>
>> - memcpy((void *)curr_des->txdes2, (void *)packet, length);
>> - dma_map_single((void *)curr_des->txdes2, length, DMA_TO_DEVICE);
>> + curr_des->txdes3 = (unsigned int)packet;
>> +
>> + /* Flush data to be sent */
>> + data_start = curr_des->txdes3;
>> + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
>> + flush_dcache_range(data_start, data_end);
>>
>> - /* only one descriptor on TXBUF */
>> + /* Only one segment on TXBUF */
>> curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
>> curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
>> - FTGMAC100_TXDES0_LTS |
>> - FTGMAC100_TXDES0_TXBUF_SIZE(length) |
>> - FTGMAC100_TXDES0_TXDMA_OWN ;
>> + FTGMAC100_TXDES0_LTS |
>> + FTGMAC100_TXDES0_TXBUF_SIZE(length) |
>> + FTGMAC100_TXDES0_TXDMA_OWN;
>>
>> - /* start transmit */
>> + /* Flush modified buffer descriptor */
>> + flush_dcache_range(des_start, des_end);
>> +
>> + /* Start transmit */
>> writel(1, &ftgmac100->txpd);
>>
>> + /* Wait until packet is transmitted */
>> + start = get_timer(0);
>> + while (get_timer(start) < FTGMAC100_TX_TIMEOUT_MS) {
>> + invalidate_dcache_range(des_start, des_end);
>> + if (!(curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN))
>> + break;
>> + udelay(10);
>> + }
>> +
>> + if (get_timer(start) >= FTGMAC100_TX_TIMEOUT_MS) {
>> + dev_err(dev, "transmit timeout\n");
>> + return -ETIMEDOUT;
>> + }
>> +
>> debug("%s(): packet sent\n", __func__);
>>
>> + /* Move to next descriptor */
>> priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
>>
>> return 0;
>> }
>>
>> -int ftgmac100_initialize(bd_t *bd)
>> +static int ftgmac100_write_hwaddr(struct udevice *dev)
>> {
>> - struct eth_device *dev;
>> - struct ftgmac100_data *priv;
>> + struct eth_pdata *pdata = dev_get_platdata(dev);
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>>
>> - dev = malloc(sizeof *dev);
>> - if (!dev) {
>> - printf("%s(): failed to allocate dev\n", __func__);
>> - goto out;
>> - }
>> + return ftgmac100_set_mac(priv, pdata->enetaddr);
>> +}
>>
>> - /* Transmit and receive descriptors should align to 16 bytes */
>> - priv = memalign(16, sizeof(struct ftgmac100_data));
>> - if (!priv) {
>> - printf("%s(): failed to allocate priv\n", __func__);
>> - goto free_dev;
>> +static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
>> +{
>> + struct eth_pdata *pdata = dev_get_platdata(dev);
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + const char *phy_mode;
>> +
>> + pdata->iobase = devfdt_get_addr(dev);
>> + pdata->phy_interface = -1;
>> + phy_mode = dev_read_string(dev, "phy-mode");
>> + if (phy_mode)
>> + pdata->phy_interface = phy_get_interface_by_name(phy_mode);
>> + if (pdata->phy_interface == -1) {
>> + dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
>> + return -EINVAL;
>> }
>>
>> - memset(dev, 0, sizeof(*dev));
>> - memset(priv, 0, sizeof(*priv));
>> + pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
>>
>> - strcpy(dev->name, "FTGMAC100");
>> - dev->iobase = CONFIG_FTGMAC100_BASE;
>> - dev->init = ftgmac100_init;
>> - dev->halt = ftgmac100_halt;
>> - dev->send = ftgmac100_send;
>> - dev->recv = ftgmac100_recv;
>> - dev->priv = priv;
>> + return clk_get_bulk(dev, &priv->clks);
>> +}
>> +
>> +static int ftgmac100_probe(struct udevice *dev)
>> +{
>> + struct eth_pdata *pdata = dev_get_platdata(dev);
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + int ret;
>>
>> - eth_register(dev);
>> + priv->iobase = (struct ftgmac100 *)pdata->iobase;
>> + priv->phy_mode = pdata->phy_interface;
>> + priv->max_speed = pdata->max_speed;
>> + priv->phyaddr = 0;
>>
>> - ftgmac100_reset(dev);
>> + ret = clk_enable_bulk(&priv->clks);
>> + if (ret)
>> + goto out;
>>
>> - return 1;
>> + ret = ftgmac100_mdio_init(priv, dev->seq);
>> + if (ret) {
>> + dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
>> + goto out;
>> + }
>> +
>> + ret = ftgmac100_phy_init(priv, dev);
>> + if (ret) {
>> + dev_err(dev, "Failed to initialize PHY: %d\n", ret);
>> + goto out;
>> + }
>>
>> -free_dev:
>> - free(dev);
>> out:
>> + if (ret)
>> + clk_release_bulk(&priv->clks);
>> +
>> + return ret;
>> +}
>> +
>> +static int ftgmac100_remove(struct udevice *dev)
>> +{
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> +
>> + free(priv->phydev);
>> + mdio_unregister(priv->bus);
>> + mdio_free(priv->bus);
>> + clk_release_bulk(&priv->clks);
>> +
>> return 0;
>> }
>> +
>> +static const struct eth_ops ftgmac100_ops = {
>> + .start = ftgmac100_start,
>> + .send = ftgmac100_send,
>> + .recv = ftgmac100_recv,
>> + .stop = ftgmac100_stop,
>> + .free_pkt = ftgmac100_free_pkt,
>> + .write_hwaddr = ftgmac100_write_hwaddr,
>> +};
>> +
>> +static const struct udevice_id ftgmac100_ids[] = {
>> + { .compatible = "faraday,ftgmac100" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(ftgmac100) = {
>> + .name = "ftgmac100",
>> + .id = UCLASS_ETH,
>> + .of_match = ftgmac100_ids,
>> + .ofdata_to_platdata = ftgmac100_ofdata_to_platdata,
>> + .probe = ftgmac100_probe,
>> + .remove = ftgmac100_remove,
>> + .ops = &ftgmac100_ops,
>> + .priv_auto_alloc_size = sizeof(struct ftgmac100_data),
>> + .platdata_auto_alloc_size = sizeof(struct eth_pdata),
>> + .flags = DM_FLAG_ALLOC_PRIV_DMA,
>> +};
>> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
>> index 5441da47d13e..3efdc5dc2fae 100644
>> --- a/drivers/net/Kconfig
>> +++ b/drivers/net/Kconfig
>> @@ -186,6 +186,32 @@ config FTMAC100
>> help
>> This MAC is present in Andestech SoCs.
>>
>> +config FTGMAC100
>> + bool "Ftgmac100 Ethernet Support"
>> + depends on DM_ETH
>> + select PHYLIB
>> + help
>> + This driver supports the Faraday's FTGMAC100 Gigabit SoC
>> + Ethernet controller that can be found on Aspeed SoCs (which
>> + include NCSI).
>> +
>> + It is fully compliant with IEEE 802.3 specification for
>> + 10/100 Mbps Ethernet and IEEE 802.3z specification for 1000
>> + Mbps Ethernet and includes Reduced Media Independent
>> + Interface (RMII) and Reduced Gigabit Media Independent
>> + Interface (RGMII) interfaces. It adopts an AHB bus interface
>> + and integrates a link list DMA engine with direct M-Bus
>> + accesses for transmitting and receiving packets. It has
>> + independent TX/RX fifos, supports half and full duplex (1000
>> + Mbps mode only supports full duplex), flow control for full
>> + duplex and backpressure for half duplex.
>> +
>> + The FTGMAC100 also implements IP, TCP, UDP checksum offloads
>> + and supports IEEE 802.1Q VLAN tag insertion and removal. It
>> + offers high-priority transmit queue for QoS and CoS
>> + applications.
>> +
>> +
>> config MVGBE
>> bool "Marvell Orion5x/Kirkwood network interface support"
>> depends on KIRKWOOD || ORION5X
>> --
>> 2.17.1
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2018-10-09 21:34 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-01 8:53 [U-Boot] [PATCH v2 0/7] Support for the Faraday ftgmac100 controller Cédric Le Goater
2018-10-01 8:53 ` [U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver Cédric Le Goater
2018-10-02 11:22 ` Simon Glass
2018-10-02 15:48 ` Cédric Le Goater
2018-10-09 16:19 ` Simon Glass
2018-10-09 20:44 ` Joe Hershberger
2018-10-09 21:09 ` Cédric Le Goater
2018-10-09 21:19 ` Joe Hershberger
2018-10-09 21:34 ` Cédric Le Goater
2018-10-01 8:53 ` [U-Boot] [PATCH v2 2/7] net: Re-add support for the Faraday ftgmac100 controller Cédric Le Goater
2018-10-01 8:53 ` [U-Boot] [PATCH v2 3/7] aspeed: ast2500: fix missing break in D2PLL clock enablement Cédric Le Goater
2018-10-01 8:53 ` [U-Boot] [PATCH v2 4/7] net: ftgmac100: Add support for the Aspeed SoC Cédric Le Goater
2018-10-02 11:22 ` Simon Glass
2018-10-01 8:53 ` [U-Boot] [PATCH v2 5/7] aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level Cédric Le Goater
2018-10-02 11:22 ` Simon Glass
2018-10-01 8:53 ` [U-Boot] [PATCH v2 6/7] aspeed: Activate ethernet devices on the ast2500 Eval Board Cédric Le Goater
2018-10-01 8:53 ` [U-Boot] [PATCH v2 7/7] aspeed: ast2500: fix D2-PLL clock setting in RGMII mode Cédric Le Goater
2018-10-02 11:22 ` Simon Glass
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