From: Christophe Leroy <christophe.leroy@c-s.fr> To: Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>, Michael Ellerman <mpe@ellerman.id.au>, joakim.tjernlund@infinera.com Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH 00/10] Optimise TLB miss handlers on 603/e300 Date: Fri, 25 Jan 2019 12:34:00 +0000 (UTC) [thread overview] Message-ID: <cover.1548419273.git.christophe.leroy@c-s.fr> (raw) The purpose of this serie is to optimise the handling of TLB misses on the 603/e300. Today the TLB miss handlers are implemented by more or less copying the actions performed by the hash page handlers used on processors having HASH pagetable. This serie brings some simplification. Christophe Leroy (10): powerpc: simplify BDI switch powerpc/603: Store PGDIR physical address in a SPRG powerpc/603: use physical address directly in TLB miss handlers. powerpc/hash32: use physical address directly in hash handlers. powerpc/603: Don't handle kernel page TLB misses when not need powerpc/603: Don't handle _PAGE_RW and _PAGE_DIRTY on ITLB misses powerpc/603: let's handle PAGE_DIRTY directly powerpc/603: Don't worry about _PAGE_USER in TLB miss handlers powerpc/603: don't handle PAGE_ACCESSED in TLB miss handlers. powerpc/book3s32: Reorder _PAGE_XXX flags to simplify TLB handling arch/powerpc/include/asm/book3s/32/hash.h | 8 +-- arch/powerpc/include/asm/mmu.h | 2 + arch/powerpc/include/asm/reg.h | 1 + arch/powerpc/kernel/cpu_setup_6xx.S | 4 ++ arch/powerpc/kernel/head_32.S | 97 ++++++++++++++----------------- arch/powerpc/kernel/head_40x.S | 5 +- arch/powerpc/kernel/head_8xx.S | 1 + arch/powerpc/mm/8xx_mmu.c | 7 +-- arch/powerpc/mm/hash_low_32.S | 68 +++++++++------------- arch/powerpc/mm/ppc_mmu_32.c | 6 +- 10 files changed, 93 insertions(+), 106 deletions(-) -- 2.13.3
WARNING: multiple messages have this Message-ID (diff)
From: Christophe Leroy <christophe.leroy@c-s.fr> To: Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>, Michael Ellerman <mpe@ellerman.id.au>, joakim.tjernlund@infinera.com Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH 00/10] Optimise TLB miss handlers on 603/e300 Date: Fri, 25 Jan 2019 12:34:00 +0000 (UTC) [thread overview] Message-ID: <cover.1548419273.git.christophe.leroy@c-s.fr> (raw) The purpose of this serie is to optimise the handling of TLB misses on the 603/e300. Today the TLB miss handlers are implemented by more or less copying the actions performed by the hash page handlers used on processors having HASH pagetable. This serie brings some simplification. Christophe Leroy (10): powerpc: simplify BDI switch powerpc/603: Store PGDIR physical address in a SPRG powerpc/603: use physical address directly in TLB miss handlers. powerpc/hash32: use physical address directly in hash handlers. powerpc/603: Don't handle kernel page TLB misses when not need powerpc/603: Don't handle _PAGE_RW and _PAGE_DIRTY on ITLB misses powerpc/603: let's handle PAGE_DIRTY directly powerpc/603: Don't worry about _PAGE_USER in TLB miss handlers powerpc/603: don't handle PAGE_ACCESSED in TLB miss handlers. powerpc/book3s32: Reorder _PAGE_XXX flags to simplify TLB handling arch/powerpc/include/asm/book3s/32/hash.h | 8 +-- arch/powerpc/include/asm/mmu.h | 2 + arch/powerpc/include/asm/reg.h | 1 + arch/powerpc/kernel/cpu_setup_6xx.S | 4 ++ arch/powerpc/kernel/head_32.S | 97 ++++++++++++++----------------- arch/powerpc/kernel/head_40x.S | 5 +- arch/powerpc/kernel/head_8xx.S | 1 + arch/powerpc/mm/8xx_mmu.c | 7 +-- arch/powerpc/mm/hash_low_32.S | 68 +++++++++------------- arch/powerpc/mm/ppc_mmu_32.c | 6 +- 10 files changed, 93 insertions(+), 106 deletions(-) -- 2.13.3
next reply other threads:[~2019-01-25 12:34 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-25 12:34 Christophe Leroy [this message] 2019-01-25 12:34 ` [PATCH 00/10] Optimise TLB miss handlers on 603/e300 Christophe Leroy 2019-01-25 12:34 ` [PATCH 01/10] powerpc: simplify BDI switch Christophe Leroy 2019-01-25 12:34 ` Christophe Leroy 2019-01-25 12:34 ` [PATCH 02/10] powerpc/603: Store PGDIR physical address in a SPRG Christophe Leroy 2019-01-25 12:34 ` Christophe Leroy 2019-02-20 17:39 ` Christophe Leroy 2019-01-25 12:34 ` [PATCH 03/10] powerpc/603: use physical address directly in TLB miss handlers Christophe Leroy 2019-01-25 12:34 ` Christophe Leroy 2019-01-25 12:34 ` [PATCH 04/10] powerpc/hash32: use physical address directly in hash handlers Christophe Leroy 2019-01-25 12:34 ` Christophe Leroy 2019-01-25 12:34 ` [PATCH 05/10] powerpc/603: Don't handle kernel page TLB misses when not need Christophe Leroy 2019-01-25 12:34 ` Christophe Leroy 2019-01-25 12:34 ` [PATCH 06/10] powerpc/603: Don't handle _PAGE_RW and _PAGE_DIRTY on ITLB misses Christophe Leroy 2019-01-25 12:34 ` Christophe Leroy 2019-01-25 12:34 ` [PATCH 07/10] powerpc/603: let's handle PAGE_DIRTY directly Christophe Leroy 2019-01-25 12:34 ` Christophe Leroy 2019-01-25 12:34 ` [PATCH 08/10] powerpc/603: Don't worry about _PAGE_USER in TLB miss handlers Christophe Leroy 2019-01-25 12:34 ` Christophe Leroy 2019-01-25 12:34 ` [PATCH 09/10] powerpc/603: don't handle PAGE_ACCESSED " Christophe Leroy 2019-01-25 12:34 ` Christophe Leroy 2019-01-25 12:34 ` [PATCH 10/10] powerpc/book3s32: Reorder _PAGE_XXX flags to simplify TLB handling Christophe Leroy 2019-01-25 12:34 ` Christophe Leroy 2019-02-22 9:47 ` [10/10] " Michael Ellerman
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