From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linuxarm@huawei.com, mauro.chehab@huawei.com,
"Mauro Carvalho Chehab" <mchehab+huawei@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Binghui Wang" <wangbinghui@hisilicon.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Xiaowei Song" <songxiaowei@hisilicon.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org
Subject: [PATCH v5 0/8] Add support for Hikey 970 PCIe
Date: Tue, 13 Jul 2021 08:28:33 +0200 [thread overview]
Message-ID: <cover.1626157454.git.mchehab+huawei@kernel.org> (raw)
As requested by Rob Herring, this series split the PHY part into a separate driver.
Then, it adds support for Kirin 970 on a single patch.
With this change, the PHY-specific device tree bindings for Kirin 960 moved
to its own PHY properties.
Tested on Hikey970:
$ lspci
00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3670 (rev 01)
01:00.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:01.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:04.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:05.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:07.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:09.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 07)
$ ethtool enp6s0
Settings for enp6s0:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Half 1000baseT/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Half 1000baseT/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
Link partner advertised pause frame use: Symmetric Receive-only
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
Speed: 100Mb/s
Duplex: Full
Auto-negotiation: on
master-slave cfg: preferred slave
master-slave status: slave
Port: Twisted Pair
PHYAD: 0
Transceiver: external
MDI-X: Unknown
netlink error: Operation not permitted
Link detected: yes
Partially tested on Hikey 960[1]:
$ lspci
00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3660 (rev 01)
[1] The Hikey 960 doesn't come with any internal PCIe device.
Its hardware supports just an external device via a M.2 slot that
doesn't support SATA. I ordered a NVMe device to test, but the vendor
is currently out of supply. It should take 3-4 weeks to arrive here. I'll
run an extra test on it once it arrives.
---
v5:
- added "static" to hi3670_pcie_get_eyeparam() declaration on patch 6/8
v4:
- dropped the DTS patch, as it depends on a PMIC-related patch series;
- minor changes at the patch description;
- HiKey and HiSilicon are now using the preferred CamelCase format.
Mauro Carvalho Chehab (8):
dt-bindings: phy: Add bindings for HiKey 960 PCIe PHY
dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY
dt-bindings: PCI: kirin: Fix compatible string
dt-bindings: PCI: kirin: Drop PHY properties
phy: HiSilicon: Add driver for Kirin 960 PCIe PHY
phy: HiSilicon: add driver for Kirin 970 PCIe PHY
PCI: kirin: Drop the PHY logic from the driver
PCI: kirin: Use regmap for APB registers
.../devicetree/bindings/pci/kirin-pcie.txt | 21 +-
.../phy/hisilicon,phy-hi3660-pcie.yaml | 82 ++
.../phy/hisilicon,phy-hi3670-pcie.yaml | 101 ++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 29 +-
drivers/pci/controller/dwc/pcie-kirin.c | 298 ++----
drivers/phy/hisilicon/Kconfig | 20 +
drivers/phy/hisilicon/Makefile | 2 +
drivers/phy/hisilicon/phy-hi3660-pcie.c | 325 +++++++
drivers/phy/hisilicon/phy-hi3670-pcie.c | 892 ++++++++++++++++++
9 files changed, 1500 insertions(+), 270 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
create mode 100644 drivers/phy/hisilicon/phy-hi3660-pcie.c
create mode 100644 drivers/phy/hisilicon/phy-hi3670-pcie.c
--
2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linuxarm@huawei.com, mauro.chehab@huawei.com,
"Mauro Carvalho Chehab" <mchehab+huawei@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Binghui Wang" <wangbinghui@hisilicon.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Xiaowei Song" <songxiaowei@hisilicon.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org
Subject: [PATCH v5 0/8] Add support for Hikey 970 PCIe
Date: Tue, 13 Jul 2021 08:28:33 +0200 [thread overview]
Message-ID: <cover.1626157454.git.mchehab+huawei@kernel.org> (raw)
As requested by Rob Herring, this series split the PHY part into a separate driver.
Then, it adds support for Kirin 970 on a single patch.
With this change, the PHY-specific device tree bindings for Kirin 960 moved
to its own PHY properties.
Tested on Hikey970:
$ lspci
00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3670 (rev 01)
01:00.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:01.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:04.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:05.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:07.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:09.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 07)
$ ethtool enp6s0
Settings for enp6s0:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Half 1000baseT/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Half 1000baseT/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
Link partner advertised pause frame use: Symmetric Receive-only
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
Speed: 100Mb/s
Duplex: Full
Auto-negotiation: on
master-slave cfg: preferred slave
master-slave status: slave
Port: Twisted Pair
PHYAD: 0
Transceiver: external
MDI-X: Unknown
netlink error: Operation not permitted
Link detected: yes
Partially tested on Hikey 960[1]:
$ lspci
00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3660 (rev 01)
[1] The Hikey 960 doesn't come with any internal PCIe device.
Its hardware supports just an external device via a M.2 slot that
doesn't support SATA. I ordered a NVMe device to test, but the vendor
is currently out of supply. It should take 3-4 weeks to arrive here. I'll
run an extra test on it once it arrives.
---
v5:
- added "static" to hi3670_pcie_get_eyeparam() declaration on patch 6/8
v4:
- dropped the DTS patch, as it depends on a PMIC-related patch series;
- minor changes at the patch description;
- HiKey and HiSilicon are now using the preferred CamelCase format.
Mauro Carvalho Chehab (8):
dt-bindings: phy: Add bindings for HiKey 960 PCIe PHY
dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY
dt-bindings: PCI: kirin: Fix compatible string
dt-bindings: PCI: kirin: Drop PHY properties
phy: HiSilicon: Add driver for Kirin 960 PCIe PHY
phy: HiSilicon: add driver for Kirin 970 PCIe PHY
PCI: kirin: Drop the PHY logic from the driver
PCI: kirin: Use regmap for APB registers
.../devicetree/bindings/pci/kirin-pcie.txt | 21 +-
.../phy/hisilicon,phy-hi3660-pcie.yaml | 82 ++
.../phy/hisilicon,phy-hi3670-pcie.yaml | 101 ++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 29 +-
drivers/pci/controller/dwc/pcie-kirin.c | 298 ++----
drivers/phy/hisilicon/Kconfig | 20 +
drivers/phy/hisilicon/Makefile | 2 +
drivers/phy/hisilicon/phy-hi3660-pcie.c | 325 +++++++
drivers/phy/hisilicon/phy-hi3670-pcie.c | 892 ++++++++++++++++++
9 files changed, 1500 insertions(+), 270 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
create mode 100644 drivers/phy/hisilicon/phy-hi3660-pcie.c
create mode 100644 drivers/phy/hisilicon/phy-hi3670-pcie.c
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linuxarm@huawei.com, mauro.chehab@huawei.com,
"Mauro Carvalho Chehab" <mchehab+huawei@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Binghui Wang" <wangbinghui@hisilicon.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Xiaowei Song" <songxiaowei@hisilicon.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org
Subject: [PATCH v5 0/8] Add support for Hikey 970 PCIe
Date: Tue, 13 Jul 2021 08:28:33 +0200 [thread overview]
Message-ID: <cover.1626157454.git.mchehab+huawei@kernel.org> (raw)
As requested by Rob Herring, this series split the PHY part into a separate driver.
Then, it adds support for Kirin 970 on a single patch.
With this change, the PHY-specific device tree bindings for Kirin 960 moved
to its own PHY properties.
Tested on Hikey970:
$ lspci
00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3670 (rev 01)
01:00.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:01.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:04.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:05.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:07.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:09.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 07)
$ ethtool enp6s0
Settings for enp6s0:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Half 1000baseT/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Half 1000baseT/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
Link partner advertised pause frame use: Symmetric Receive-only
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
Speed: 100Mb/s
Duplex: Full
Auto-negotiation: on
master-slave cfg: preferred slave
master-slave status: slave
Port: Twisted Pair
PHYAD: 0
Transceiver: external
MDI-X: Unknown
netlink error: Operation not permitted
Link detected: yes
Partially tested on Hikey 960[1]:
$ lspci
00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3660 (rev 01)
[1] The Hikey 960 doesn't come with any internal PCIe device.
Its hardware supports just an external device via a M.2 slot that
doesn't support SATA. I ordered a NVMe device to test, but the vendor
is currently out of supply. It should take 3-4 weeks to arrive here. I'll
run an extra test on it once it arrives.
---
v5:
- added "static" to hi3670_pcie_get_eyeparam() declaration on patch 6/8
v4:
- dropped the DTS patch, as it depends on a PMIC-related patch series;
- minor changes at the patch description;
- HiKey and HiSilicon are now using the preferred CamelCase format.
Mauro Carvalho Chehab (8):
dt-bindings: phy: Add bindings for HiKey 960 PCIe PHY
dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY
dt-bindings: PCI: kirin: Fix compatible string
dt-bindings: PCI: kirin: Drop PHY properties
phy: HiSilicon: Add driver for Kirin 960 PCIe PHY
phy: HiSilicon: add driver for Kirin 970 PCIe PHY
PCI: kirin: Drop the PHY logic from the driver
PCI: kirin: Use regmap for APB registers
.../devicetree/bindings/pci/kirin-pcie.txt | 21 +-
.../phy/hisilicon,phy-hi3660-pcie.yaml | 82 ++
.../phy/hisilicon,phy-hi3670-pcie.yaml | 101 ++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 29 +-
drivers/pci/controller/dwc/pcie-kirin.c | 298 ++----
drivers/phy/hisilicon/Kconfig | 20 +
drivers/phy/hisilicon/Makefile | 2 +
drivers/phy/hisilicon/phy-hi3660-pcie.c | 325 +++++++
drivers/phy/hisilicon/phy-hi3670-pcie.c | 892 ++++++++++++++++++
9 files changed, 1500 insertions(+), 270 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
create mode 100644 drivers/phy/hisilicon/phy-hi3660-pcie.c
create mode 100644 drivers/phy/hisilicon/phy-hi3670-pcie.c
--
2.31.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next reply other threads:[~2021-07-13 6:28 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-13 6:28 Mauro Carvalho Chehab [this message]
2021-07-13 6:28 ` [PATCH v5 0/8] Add support for Hikey 970 PCIe Mauro Carvalho Chehab
2021-07-13 6:28 ` Mauro Carvalho Chehab
2021-07-13 6:28 ` [PATCH v5 1/8] dt-bindings: phy: Add bindings for HiKey 960 PCIe PHY Mauro Carvalho Chehab
2021-07-13 6:28 ` Mauro Carvalho Chehab
2021-07-14 2:22 ` Rob Herring
2021-07-14 2:22 ` Rob Herring
2021-07-13 6:28 ` [PATCH v5 2/8] dt-bindings: phy: Add bindings for HiKey 970 " Mauro Carvalho Chehab
2021-07-13 6:28 ` Mauro Carvalho Chehab
2021-07-14 2:26 ` Rob Herring
2021-07-14 2:26 ` Rob Herring
2021-07-14 7:14 ` Mauro Carvalho Chehab
2021-07-14 7:14 ` Mauro Carvalho Chehab
2021-07-14 14:17 ` Rob Herring
2021-07-14 14:17 ` Rob Herring
2021-07-14 14:31 ` Mauro Carvalho Chehab
2021-07-14 14:31 ` Mauro Carvalho Chehab
2021-07-14 17:42 ` Manivannan Sadhasivam
2021-07-14 17:42 ` Manivannan Sadhasivam
2021-07-15 6:37 ` Mauro Carvalho Chehab
2021-07-15 6:37 ` Mauro Carvalho Chehab
2021-07-19 15:26 ` Mauro Carvalho Chehab
2021-07-19 15:26 ` Mauro Carvalho Chehab
2021-07-27 8:11 ` Mauro Carvalho Chehab
2021-07-27 8:11 ` Mauro Carvalho Chehab
2021-07-13 6:28 ` [PATCH v5 3/8] dt-bindings: PCI: kirin: Fix compatible string Mauro Carvalho Chehab
2021-07-14 2:27 ` Rob Herring
2021-07-13 6:28 ` [PATCH v5 4/8] dt-bindings: PCI: kirin: Drop PHY properties Mauro Carvalho Chehab
2021-07-14 2:28 ` Rob Herring
2021-07-14 11:22 ` Mauro Carvalho Chehab
2021-07-16 11:22 ` Mauro Carvalho Chehab
2021-07-13 6:28 ` [PATCH v5 5/8] phy: HiSilicon: Add driver for Kirin 960 PCIe PHY Mauro Carvalho Chehab
2021-07-13 6:28 ` Mauro Carvalho Chehab
2021-07-13 6:28 ` [PATCH v5 6/8] phy: HiSilicon: add driver for Kirin 970 " Mauro Carvalho Chehab
2021-07-13 6:28 ` Mauro Carvalho Chehab
2021-07-13 6:28 ` [PATCH v5 7/8] PCI: kirin: Drop the PHY logic from the driver Mauro Carvalho Chehab
2021-07-13 6:28 ` Mauro Carvalho Chehab
2021-07-13 6:28 ` [PATCH v5 8/8] PCI: kirin: Use regmap for APB registers Mauro Carvalho Chehab
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cover.1626157454.git.mchehab+huawei@kernel.org \
--to=mchehab+huawei@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=helgaas@kernel.org \
--cc=kw@linux.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=linuxarm@huawei.com \
--cc=mani@kernel.org \
--cc=mauro.chehab@huawei.com \
--cc=robh+dt@kernel.org \
--cc=robh@kernel.org \
--cc=songxiaowei@hisilicon.com \
--cc=wangbinghui@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.