[PATCH v3 0/4] DRM: Bridge: DW_HDMI: Add new features and bug fix

[PATCH v3 0/4] DRM: Bridge: DW_HDMI: Add new features and bug fix

[Sandor.yu]

From: Sandor Yu <Sandor.yu@nxp.com>

This is new features and bug fix patch set for DW_HDMI DRM bridge driver
that has verified by NXP i.MX8MPlus.
Two new feature added:
1. Add GPA interface for DW_HDMI Audio.
3. New API for reset PHY Gen1.
Two bugs fixed:
1. Enable overflow workaround for all IP versions later than v1.30a.
2. Clear GCP_Auto bit for 24-bit color depth to pass CTS.

v1->v2:
1. Save CEC interrupt registers in struct dw_hdmi_cec
2. Restore CEC logical address register by cec->addresses.
3. Default enable overflow workaround for all versions later than v1.30a.
4. Add clear_gcp_auto flag to clear gcp_auto bit for all 24-bit color.
5. Remove i.MX8MPlus specific reference.

v2->v3:
1. Drop the patch of Add CEC Suspend/Resume to restore registers.
Because it is not a general feature for other SOCs, their CEC engine are
enabled in suspend for CEC wakeup.
2. More detail comments for patch GCP only for Deep Color.
3. Address coments for patch GPA driver and move enable_audio/disable_audio
from dw_hdmi_phy_ops to dw_hdmi_plat_data.

Sandor Yu (4):
  drm: bridge: dw_hdmi: default enable workaround to clear the overflow
  drm: bridge: dw_hdmi: Enable GCP only for Deep Color
  drm: bridge: dw_hdmi: add reset function for PHY GEN1
  drm: bridge: dw_hdmi: Audio: Add General Parallel Audio (GPA) driver

 drivers/gpu/drm/bridge/synopsys/Kconfig       |  10 +
 drivers/gpu/drm/bridge/synopsys/Makefile      |   1 +
 .../drm/bridge/synopsys/dw-hdmi-gp-audio.c    | 199 ++++++++++++++++++
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c     | 186 ++++++++++++++--
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h     |  16 +-
 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c        |   2 +-
 include/drm/bridge/dw_hdmi.h                  |  11 +-
 7 files changed, 400 insertions(+), 25 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c

-- 
2.25.1

[PATCH v3 0/4] DRM: Bridge: DW_HDMI: Add new features and bug fix

[Sandor.yu]

From: Sandor Yu <Sandor.yu@nxp.com>

This is new features and bug fix patch set for DW_HDMI DRM bridge driver
that has verified by NXP i.MX8MPlus.
Two new feature added:
1. Add GPA interface for DW_HDMI Audio.
3. New API for reset PHY Gen1.
Two bugs fixed:
1. Enable overflow workaround for all IP versions later than v1.30a.
2. Clear GCP_Auto bit for 24-bit color depth to pass CTS.

v1->v2:
1. Save CEC interrupt registers in struct dw_hdmi_cec
2. Restore CEC logical address register by cec->addresses.
3. Default enable overflow workaround for all versions later than v1.30a.
4. Add clear_gcp_auto flag to clear gcp_auto bit for all 24-bit color.
5. Remove i.MX8MPlus specific reference.

v2->v3:
1. Drop the patch of Add CEC Suspend/Resume to restore registers.
Because it is not a general feature for other SOCs, their CEC engine are
enabled in suspend for CEC wakeup.
2. More detail comments for patch GCP only for Deep Color.
3. Address coments for patch GPA driver and move enable_audio/disable_audio
from dw_hdmi_phy_ops to dw_hdmi_plat_data.

Sandor Yu (4):
  drm: bridge: dw_hdmi: default enable workaround to clear the overflow
  drm: bridge: dw_hdmi: Enable GCP only for Deep Color
  drm: bridge: dw_hdmi: add reset function for PHY GEN1
  drm: bridge: dw_hdmi: Audio: Add General Parallel Audio (GPA) driver

 drivers/gpu/drm/bridge/synopsys/Kconfig       |  10 +
 drivers/gpu/drm/bridge/synopsys/Makefile      |   1 +
 .../drm/bridge/synopsys/dw-hdmi-gp-audio.c    | 199 ++++++++++++++++++
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c     | 186 ++++++++++++++--
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h     |  16 +-
 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c        |   2 +-
 include/drm/bridge/dw_hdmi.h                  |  11 +-
 7 files changed, 400 insertions(+), 25 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c

-- 
2.25.1

[PATCH v3 1/4] drm: bridge: dw_hdmi: default enable workaround to clear the overflow

[Sandor.yu]

From: Sandor Yu <Sandor.yu@nxp.com>

i.MX8MPlus (v2.13a) has verified need the workaround to clear the
overflow with one iteration.
Only i.MX6Q(v1.30a) need the workaround with 4 iterations,
the others versions later than v1.3a have been identified as needing
the workaround with a single iteration.

Default enable the workaround with one iteration for all versions
later than v1.30a.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 23 +++++++----------------
 1 file changed, 7 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 4befc104d220..02d8f7e08814 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2086,30 +2086,21 @@ static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
 	 * then write one of the FC registers several times.
 	 *
 	 * The number of iterations matters and depends on the HDMI TX revision
-	 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
-	 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
-	 * as needing the workaround, with 4 iterations for v1.30a and 1
-	 * iteration for others.
-	 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
-	 * the workaround with a single iteration.
-	 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
-	 * been identified as needing the workaround with a single iteration.
+	 * (and possibly on the platform).
+	 * 4 iterations for i.MX6Q(v1.30a) and 1 iteration for others.
+	 * i.MX6DL (v1.31a), Allwinner SoCs (v1.32a), Rockchip RK3288 SoC (v2.00a),
+	 * Amlogic Meson GX SoCs (v2.01a), RK3328/RK3399 SoCs (v2.11a)
+	 * and i.MX8MPlus (v2.13a) have been identified as needing the workaround
+	 * with a single iteration.
 	 */
 
 	switch (hdmi->version) {
 	case 0x130a:
 		count = 4;
 		break;
-	case 0x131a:
-	case 0x132a:
-	case 0x200a:
-	case 0x201a:
-	case 0x211a:
-	case 0x212a:
+	default:
 		count = 1;
 		break;
-	default:
-		return;
 	}
 
 	/* TMDS software reset */
-- 
2.25.1

[PATCH v3 1/4] drm: bridge: dw_hdmi: default enable workaround to clear the overflow

[Sandor.yu]

From: Sandor Yu <Sandor.yu@nxp.com>

i.MX8MPlus (v2.13a) has verified need the workaround to clear the
overflow with one iteration.
Only i.MX6Q(v1.30a) need the workaround with 4 iterations,
the others versions later than v1.3a have been identified as needing
the workaround with a single iteration.

Default enable the workaround with one iteration for all versions
later than v1.30a.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 23 +++++++----------------
 1 file changed, 7 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 4befc104d220..02d8f7e08814 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2086,30 +2086,21 @@ static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
 	 * then write one of the FC registers several times.
 	 *
 	 * The number of iterations matters and depends on the HDMI TX revision
-	 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
-	 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
-	 * as needing the workaround, with 4 iterations for v1.30a and 1
-	 * iteration for others.
-	 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
-	 * the workaround with a single iteration.
-	 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
-	 * been identified as needing the workaround with a single iteration.
+	 * (and possibly on the platform).
+	 * 4 iterations for i.MX6Q(v1.30a) and 1 iteration for others.
+	 * i.MX6DL (v1.31a), Allwinner SoCs (v1.32a), Rockchip RK3288 SoC (v2.00a),
+	 * Amlogic Meson GX SoCs (v2.01a), RK3328/RK3399 SoCs (v2.11a)
+	 * and i.MX8MPlus (v2.13a) have been identified as needing the workaround
+	 * with a single iteration.
 	 */
 
 	switch (hdmi->version) {
 	case 0x130a:
 		count = 4;
 		break;
-	case 0x131a:
-	case 0x132a:
-	case 0x200a:
-	case 0x201a:
-	case 0x211a:
-	case 0x212a:
+	default:
 		count = 1;
 		break;
-	default:
-		return;
 	}
 
 	/* TMDS software reset */
-- 
2.25.1

[PATCH v3 2/4] drm: bridge: dw_hdmi: Enable GCP only for Deep Color

[Sandor.yu]

From: Sandor Yu <Sandor.yu@nxp.com>

HDMI1.4b specification section 6.5.3:
Source shall only send GCPs with non-zero CD to sinks
that indicate support for Deep Color.

DW HDMI GCP default enabled, but only transmit CD
and do not handle AVMUTE, PP norDefault_Phase (yet).
Disable Auto GCP when 24-bit color for sinks that not support Deep Color.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 +++++++++++++++++
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h |  3 +++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 02d8f7e08814..312500921754 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1108,6 +1108,8 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 	unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 	struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 	u8 val, vp_conf;
+	u8 clear_gcp_auto = 0;
+
 
 	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 	    hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
@@ -1117,6 +1119,7 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 		case 8:
 			color_depth = 4;
 			output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
+			clear_gcp_auto = 1;
 			break;
 		case 10:
 			color_depth = 5;
@@ -1136,6 +1139,7 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 		case 0:
 		case 8:
 			remap_size = HDMI_VP_REMAP_YCC422_16bit;
+			clear_gcp_auto = 1;
 			break;
 		case 10:
 			remap_size = HDMI_VP_REMAP_YCC422_20bit;
@@ -1160,6 +1164,19 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 	hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 
+	/* HDMI1.4b specification section 6.5.3:
+	 * Source shall only send GCPs with non-zero CD to sinks
+	 * that indicate support for Deep Color.
+	 * GCP only transmit CD and do not handle AVMUTE, PP norDefault_Phase (yet).
+	 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color.
+	 */
+	val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3);
+	if (clear_gcp_auto == 1)
+		val &= ~HDMI_FC_DATAUTO3_GCP_AUTO;
+	else
+		val |= HDMI_FC_DATAUTO3_GCP_AUTO;
+	hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3);
+
 	hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 		  HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
index 1999db05bc3b..18df3e119553 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
@@ -850,6 +850,9 @@ enum {
 	HDMI_FC_DATAUTO0_VSD_MASK = 0x08,
 	HDMI_FC_DATAUTO0_VSD_OFFSET = 3,
 
+/* FC_DATAUTO3 field values */
+	HDMI_FC_DATAUTO3_GCP_AUTO = 0x04,
+
 /* PHY_CONF0 field values */
 	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
 	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
-- 
2.25.1

[PATCH v3 2/4] drm: bridge: dw_hdmi: Enable GCP only for Deep Color

[Sandor.yu]

From: Sandor Yu <Sandor.yu@nxp.com>

HDMI1.4b specification section 6.5.3:
Source shall only send GCPs with non-zero CD to sinks
that indicate support for Deep Color.

DW HDMI GCP default enabled, but only transmit CD
and do not handle AVMUTE, PP norDefault_Phase (yet).
Disable Auto GCP when 24-bit color for sinks that not support Deep Color.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 +++++++++++++++++
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h |  3 +++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 02d8f7e08814..312500921754 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1108,6 +1108,8 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 	unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 	struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 	u8 val, vp_conf;
+	u8 clear_gcp_auto = 0;
+
 
 	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 	    hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
@@ -1117,6 +1119,7 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 		case 8:
 			color_depth = 4;
 			output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
+			clear_gcp_auto = 1;
 			break;
 		case 10:
 			color_depth = 5;
@@ -1136,6 +1139,7 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 		case 0:
 		case 8:
 			remap_size = HDMI_VP_REMAP_YCC422_16bit;
+			clear_gcp_auto = 1;
 			break;
 		case 10:
 			remap_size = HDMI_VP_REMAP_YCC422_20bit;
@@ -1160,6 +1164,19 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 	hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 
+	/* HDMI1.4b specification section 6.5.3:
+	 * Source shall only send GCPs with non-zero CD to sinks
+	 * that indicate support for Deep Color.
+	 * GCP only transmit CD and do not handle AVMUTE, PP norDefault_Phase (yet).
+	 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color.
+	 */
+	val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3);
+	if (clear_gcp_auto == 1)
+		val &= ~HDMI_FC_DATAUTO3_GCP_AUTO;
+	else
+		val |= HDMI_FC_DATAUTO3_GCP_AUTO;
+	hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3);
+
 	hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 		  HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
index 1999db05bc3b..18df3e119553 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
@@ -850,6 +850,9 @@ enum {
 	HDMI_FC_DATAUTO0_VSD_MASK = 0x08,
 	HDMI_FC_DATAUTO0_VSD_OFFSET = 3,
 
+/* FC_DATAUTO3 field values */
+	HDMI_FC_DATAUTO3_GCP_AUTO = 0x04,
+
 /* PHY_CONF0 field values */
 	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
 	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
-- 
2.25.1

Re: [PATCH v3 2/4] drm: bridge: dw_hdmi: Enable GCP only for Deep Color

[Neil Armstrong]

On 15/04/2022 04:42, Sandor.yu@nxp.com wrote:
> From: Sandor Yu <Sandor.yu@nxp.com>
> 
> HDMI1.4b specification section 6.5.3:
> Source shall only send GCPs with non-zero CD to sinks
> that indicate support for Deep Color.
> 
> DW HDMI GCP default enabled, but only transmit CD
> and do not handle AVMUTE, PP norDefault_Phase (yet).
> Disable Auto GCP when 24-bit color for sinks that not support Deep Color.
> 
> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> ---
>   drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 +++++++++++++++++
>   drivers/gpu/drm/bridge/synopsys/dw-hdmi.h |  3 +++
>   2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index 02d8f7e08814..312500921754 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -1108,6 +1108,8 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
>   	unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
>   	struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
>   	u8 val, vp_conf;
> +	u8 clear_gcp_auto = 0;
> +
>   
>   	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
>   	    hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
> @@ -1117,6 +1119,7 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
>   		case 8:
>   			color_depth = 4;
>   			output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
> +			clear_gcp_auto = 1;
>   			break;
>   		case 10:
>   			color_depth = 5;
> @@ -1136,6 +1139,7 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
>   		case 0:
>   		case 8:
>   			remap_size = HDMI_VP_REMAP_YCC422_16bit;
> +			clear_gcp_auto = 1;
>   			break;
>   		case 10:
>   			remap_size = HDMI_VP_REMAP_YCC422_20bit;
> @@ -1160,6 +1164,19 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
>   		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
>   	hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
>   
> +	/* HDMI1.4b specification section 6.5.3:
> +	 * Source shall only send GCPs with non-zero CD to sinks
> +	 * that indicate support for Deep Color.
> +	 * GCP only transmit CD and do not handle AVMUTE, PP norDefault_Phase (yet).
> +	 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color.
> +	 */
> +	val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3);
> +	if (clear_gcp_auto == 1)
> +		val &= ~HDMI_FC_DATAUTO3_GCP_AUTO;
> +	else
> +		val |= HDMI_FC_DATAUTO3_GCP_AUTO;
> +	hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3);
> +
>   	hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
>   		  HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
>   
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
> index 1999db05bc3b..18df3e119553 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
> @@ -850,6 +850,9 @@ enum {
>   	HDMI_FC_DATAUTO0_VSD_MASK = 0x08,
>   	HDMI_FC_DATAUTO0_VSD_OFFSET = 3,
>   
> +/* FC_DATAUTO3 field values */
> +	HDMI_FC_DATAUTO3_GCP_AUTO = 0x04,
> +
>   /* PHY_CONF0 field values */
>   	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
>   	HDMI_PHY_CONF0_PDZ_OFFSET = 7,

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH v3 2/4] drm: bridge: dw_hdmi: Enable GCP only for Deep Color

[Neil Armstrong]

On 15/04/2022 04:42, Sandor.yu@nxp.com wrote:
> From: Sandor Yu <Sandor.yu@nxp.com>
> 
> HDMI1.4b specification section 6.5.3:
> Source shall only send GCPs with non-zero CD to sinks
> that indicate support for Deep Color.
> 
> DW HDMI GCP default enabled, but only transmit CD
> and do not handle AVMUTE, PP norDefault_Phase (yet).
> Disable Auto GCP when 24-bit color for sinks that not support Deep Color.
> 
> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> ---
>   drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 +++++++++++++++++
>   drivers/gpu/drm/bridge/synopsys/dw-hdmi.h |  3 +++
>   2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index 02d8f7e08814..312500921754 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -1108,6 +1108,8 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
>   	unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
>   	struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
>   	u8 val, vp_conf;
> +	u8 clear_gcp_auto = 0;
> +
>   
>   	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
>   	    hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
> @@ -1117,6 +1119,7 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
>   		case 8:
>   			color_depth = 4;
>   			output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
> +			clear_gcp_auto = 1;
>   			break;
>   		case 10:
>   			color_depth = 5;
> @@ -1136,6 +1139,7 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
>   		case 0:
>   		case 8:
>   			remap_size = HDMI_VP_REMAP_YCC422_16bit;
> +			clear_gcp_auto = 1;
>   			break;
>   		case 10:
>   			remap_size = HDMI_VP_REMAP_YCC422_20bit;
> @@ -1160,6 +1164,19 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
>   		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
>   	hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
>   
> +	/* HDMI1.4b specification section 6.5.3:
> +	 * Source shall only send GCPs with non-zero CD to sinks
> +	 * that indicate support for Deep Color.
> +	 * GCP only transmit CD and do not handle AVMUTE, PP norDefault_Phase (yet).
> +	 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color.
> +	 */
> +	val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3);
> +	if (clear_gcp_auto == 1)
> +		val &= ~HDMI_FC_DATAUTO3_GCP_AUTO;
> +	else
> +		val |= HDMI_FC_DATAUTO3_GCP_AUTO;
> +	hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3);
> +
>   	hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
>   		  HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
>   
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
> index 1999db05bc3b..18df3e119553 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
> @@ -850,6 +850,9 @@ enum {
>   	HDMI_FC_DATAUTO0_VSD_MASK = 0x08,
>   	HDMI_FC_DATAUTO0_VSD_OFFSET = 3,
>   
> +/* FC_DATAUTO3 field values */
> +	HDMI_FC_DATAUTO3_GCP_AUTO = 0x04,
> +
>   /* PHY_CONF0 field values */
>   	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
>   	HDMI_PHY_CONF0_PDZ_OFFSET = 7,

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

[PATCH v3 3/4] drm: bridge: dw_hdmi: add reset function for PHY GEN1

[Sandor.yu]

From: Sandor Yu <Sandor.yu@nxp.com>

PHY reset register(MC_PHYRSTZ) active high reset control for PHY GEN2,
and active low reset control for PHY GEN1.

Rename function dw_hdmi_phy_reset to dw_hdmi_phy_gen2_reset.
Add dw_hdmi_phy_gen1_reset function for PHY GEN1.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 +++++++++++---
 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c    |  2 +-
 include/drm/bridge/dw_hdmi.h              |  4 +++-
 3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 312500921754..ac98605a6811 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1374,13 +1374,21 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
 			 HDMI_PHY_CONF0_SELDIPIF_MASK);
 }
 
-void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
+void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi)
+{
+	/* PHY reset. The reset signal is active low on Gen1 PHYs. */
+	hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
+	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
+}
+EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset);
+
+void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi)
 {
 	/* PHY reset. The reset signal is active high on Gen2 PHYs. */
 	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
 	hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
 }
-EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
+EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset);
 
 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
 {
@@ -1534,7 +1542,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi,
 	if (phy->has_svsret)
 		dw_hdmi_phy_enable_svsret(hdmi, 1);
 
-	dw_hdmi_phy_reset(hdmi);
+	dw_hdmi_phy_gen2_reset(hdmi);
 
 	hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index 5e2b0175df36..2860e6bff8b7 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -135,7 +135,7 @@ static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi,
 	dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 	dw_hdmi_phy_gen2_pddq(hdmi, 1);
 
-	dw_hdmi_phy_reset(hdmi);
+	dw_hdmi_phy_gen2_reset(hdmi);
 
 	dw_hdmi_phy_gen2_pddq(hdmi, 0);
 
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 2a1f85f9a8a3..70082f80a8c8 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -187,9 +187,11 @@ void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address);
 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 			   unsigned char addr);
 
+void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi);
+
 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable);
 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable);
-void dw_hdmi_phy_reset(struct dw_hdmi *hdmi);
+void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi);
 
 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
 					       void *data);
-- 
2.25.1

[PATCH v3 3/4] drm: bridge: dw_hdmi: add reset function for PHY GEN1

[Sandor.yu]

From: Sandor Yu <Sandor.yu@nxp.com>

PHY reset register(MC_PHYRSTZ) active high reset control for PHY GEN2,
and active low reset control for PHY GEN1.

Rename function dw_hdmi_phy_reset to dw_hdmi_phy_gen2_reset.
Add dw_hdmi_phy_gen1_reset function for PHY GEN1.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 +++++++++++---
 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c    |  2 +-
 include/drm/bridge/dw_hdmi.h              |  4 +++-
 3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 312500921754..ac98605a6811 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1374,13 +1374,21 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
 			 HDMI_PHY_CONF0_SELDIPIF_MASK);
 }
 
-void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
+void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi)
+{
+	/* PHY reset. The reset signal is active low on Gen1 PHYs. */
+	hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
+	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
+}
+EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset);
+
+void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi)
 {
 	/* PHY reset. The reset signal is active high on Gen2 PHYs. */
 	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
 	hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
 }
-EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
+EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset);
 
 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
 {
@@ -1534,7 +1542,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi,
 	if (phy->has_svsret)
 		dw_hdmi_phy_enable_svsret(hdmi, 1);
 
-	dw_hdmi_phy_reset(hdmi);
+	dw_hdmi_phy_gen2_reset(hdmi);
 
 	hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index 5e2b0175df36..2860e6bff8b7 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -135,7 +135,7 @@ static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi,
 	dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 	dw_hdmi_phy_gen2_pddq(hdmi, 1);
 
-	dw_hdmi_phy_reset(hdmi);
+	dw_hdmi_phy_gen2_reset(hdmi);
 
 	dw_hdmi_phy_gen2_pddq(hdmi, 0);
 
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 2a1f85f9a8a3..70082f80a8c8 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -187,9 +187,11 @@ void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address);
 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 			   unsigned char addr);
 
+void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi);
+
 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable);
 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable);
-void dw_hdmi_phy_reset(struct dw_hdmi *hdmi);
+void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi);
 
 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
 					       void *data);
-- 
2.25.1

[PATCH v3 4/4] drm: bridge: dw_hdmi: Audio: Add General Parallel Audio (GPA) driver

[Sandor.yu]

From: Sandor Yu <Sandor.yu@nxp.com>

General Parallel Audio (GPA) interface is one of the supported
audio interface for synopsys HDMI module, which has verified for
i.MX8MPlus platform.
This is initial version for GPA.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
---
 drivers/gpu/drm/bridge/synopsys/Kconfig       |  10 +
 drivers/gpu/drm/bridge/synopsys/Makefile      |   1 +
 .../drm/bridge/synopsys/dw-hdmi-gp-audio.c    | 199 ++++++++++++++++++
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c     | 132 +++++++++++-
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h     |  13 +-
 include/drm/bridge/dw_hdmi.h                  |   7 +
 6 files changed, 358 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c

diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig
index 21a1be3ced0f..a4a31b669b65 100644
--- a/drivers/gpu/drm/bridge/synopsys/Kconfig
+++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
@@ -25,6 +25,16 @@ config DRM_DW_HDMI_I2S_AUDIO
 	  Support the I2S Audio interface which is part of the Synopsys
 	  Designware HDMI block.
 
+config DRM_DW_HDMI_GP_AUDIO
+	tristate "Synopsys Designware GP Audio interface"
+	depends on DRM_DW_HDMI && SND
+	select SND_PCM
+	select SND_PCM_ELD
+	select SND_PCM_IEC958
+	help
+	  Support the GP Audio interface which is part of the Synopsys
+	  Designware HDMI block.
+
 config DRM_DW_HDMI_CEC
 	tristate "Synopsis Designware CEC interface"
 	depends on DRM_DW_HDMI
diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile
index 91d746ad5de1..ce715562e9e5 100644
--- a/drivers/gpu/drm/bridge/synopsys/Makefile
+++ b/drivers/gpu/drm/bridge/synopsys/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
+obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o
 obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
 obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o
 
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c
new file mode 100644
index 000000000000..8ca401b0dc2b
--- /dev/null
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * dw-hdmi-gp-audio.c
+ *
+ * Copyright 2020-2022 NXP
+ */
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <drm/bridge/dw_hdmi.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_connector.h>
+
+#include <sound/hdmi-codec.h>
+#include <sound/asoundef.h>
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <sound/pcm.h>
+#include <sound/pcm_drm_eld.h>
+#include <sound/pcm_iec958.h>
+#include <sound/dmaengine_pcm.h>
+
+#include "dw-hdmi-audio.h"
+
+#define DRIVER_NAME "dw-hdmi-gp-audio"
+#define DRV_NAME    "hdmi-gp-audio"
+
+struct snd_dw_hdmi {
+	struct dw_hdmi_audio_data data;
+	struct platform_device  *audio_pdev;
+	unsigned int pos;
+};
+
+struct dw_hdmi_channel_conf {
+	u8 conf1;
+	u8 ca;
+};
+
+/*
+ * The default mapping of ALSA channels to HDMI channels and speaker
+ * allocation bits.  Note that we can't do channel remapping here -
+ * channels must be in the same order.
+ *
+ * Mappings for alsa-lib pcm/surround*.conf files:
+ *
+ *		Front	Sur4.0	Sur4.1	Sur5.0	Sur5.1	Sur7.1
+ * Channels	2	4	6	6	6	8
+ *
+ * Our mapping from ALSA channel to CEA686D speaker name and HDMI channel:
+ *
+ *				Number of ALSA channels
+ * ALSA Channel	2	3	4	5	6	7	8
+ * 0		FL:0	=	=	=	=	=	=
+ * 1		FR:1	=	=	=	=	=	=
+ * 2			FC:3	RL:4	LFE:2	=	=	=
+ * 3				RR:5	RL:4	FC:3	=	=
+ * 4					RR:5	RL:4	=	=
+ * 5						RR:5	=	=
+ * 6							RC:6	=
+ * 7							RLC/FRC	RLC/FRC
+ */
+static struct dw_hdmi_channel_conf default_hdmi_channel_config[7] = {
+	{ 0x03, 0x00 },	/* FL,FR */
+	{ 0x0b, 0x02 },	/* FL,FR,FC */
+	{ 0x33, 0x08 },	/* FL,FR,RL,RR */
+	{ 0x37, 0x09 },	/* FL,FR,LFE,RL,RR */
+	{ 0x3f, 0x0b },	/* FL,FR,LFE,FC,RL,RR */
+	{ 0x7f, 0x0f },	/* FL,FR,LFE,FC,RL,RR,RC */
+	{ 0xff, 0x13 },	/* FL,FR,LFE,FC,RL,RR,[FR]RC,[FR]LC */
+};
+
+static int audio_hw_params(struct device *dev,  void *data,
+			   struct hdmi_codec_daifmt *daifmt,
+			   struct hdmi_codec_params *params)
+{
+	struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
+	int ret = 0;
+	u8 ca;
+
+	dw_hdmi_set_sample_rate(dw->data.hdmi, params->sample_rate);
+
+	ca = default_hdmi_channel_config[params->channels - 2].ca;
+
+	dw_hdmi_set_channel_count(dw->data.hdmi, params->channels);
+	dw_hdmi_set_channel_allocation(dw->data.hdmi, ca);
+
+	dw_hdmi_set_sample_non_pcm(dw->data.hdmi,
+				   params->iec.status[0] & IEC958_AES0_NONAUDIO);
+	dw_hdmi_set_sample_width(dw->data.hdmi, params->sample_width);
+
+	return ret;
+}
+
+static void audio_shutdown(struct device *dev, void *data)
+{
+}
+
+static int audio_mute_stream(struct device *dev, void *data,
+			      bool enable, int direction)
+{
+	struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
+	int ret = 0;
+
+	if (!enable)
+		dw_hdmi_audio_enable(dw->data.hdmi);
+	else
+		dw_hdmi_audio_disable(dw->data.hdmi);
+
+	return ret;
+}
+
+static int audio_get_eld(struct device *dev, void *data,
+			 u8 *buf, size_t len)
+{
+	struct dw_hdmi_audio_data *audio = data;
+	u8 *eld;
+
+	eld = audio->get_eld(audio->hdmi);
+	if (eld)
+		memcpy(buf, eld, min_t(size_t, MAX_ELD_BYTES, len));
+	else
+		/* Pass en empty ELD if connector not available */
+		memset(buf, 0, len);
+
+	return 0;
+}
+
+static int audio_hook_plugged_cb(struct device *dev, void *data,
+				 hdmi_codec_plugged_cb fn,
+				 struct device *codec_dev)
+{
+	struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
+
+	return dw_hdmi_set_plugged_cb(dw->data.hdmi, fn, codec_dev);
+}
+
+static const struct hdmi_codec_ops audio_codec_ops = {
+	.hw_params = audio_hw_params,
+	.audio_shutdown = audio_shutdown,
+	.mute_stream = audio_mute_stream,
+	.get_eld = audio_get_eld,
+	.hook_plugged_cb = audio_hook_plugged_cb,
+};
+
+static int snd_dw_hdmi_probe(struct platform_device *pdev)
+{
+	struct dw_hdmi_audio_data *data = pdev->dev.platform_data;
+	struct snd_dw_hdmi *dw;
+
+	const struct hdmi_codec_pdata codec_data = {
+		.i2s = 1,
+		.spdif = 0,
+		.ops = &audio_codec_ops,
+		.max_i2s_channels = 8,
+		.data = data,
+	};
+
+	dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL);
+	if (!dw)
+		return -ENOMEM;
+
+	dw->data = *data;
+
+	platform_set_drvdata(pdev, dw);
+
+	dw->audio_pdev = platform_device_register_data(&pdev->dev,
+						       HDMI_CODEC_DRV_NAME, 1,
+						       &codec_data,
+						       sizeof(codec_data));
+
+	return PTR_ERR_OR_ZERO(dw->audio_pdev);
+}
+
+static int snd_dw_hdmi_remove(struct platform_device *pdev)
+{
+	struct snd_dw_hdmi *dw = platform_get_drvdata(pdev);
+
+	platform_device_unregister(dw->audio_pdev);
+
+	return 0;
+}
+
+static struct platform_driver snd_dw_hdmi_driver = {
+	.probe	= snd_dw_hdmi_probe,
+	.remove	= snd_dw_hdmi_remove,
+	.driver	= {
+		.name = DRIVER_NAME,
+	},
+};
+
+module_platform_driver(snd_dw_hdmi_driver);
+
+MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>");
+MODULE_DESCRIPTION("Synopsys Designware HDMI GPA ALSA interface");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index ac98605a6811..f51e199a7493 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -191,7 +191,10 @@ struct dw_hdmi {
 
 	spinlock_t audio_lock;
 	struct mutex audio_mutex;
+	unsigned int sample_non_pcm;
+	unsigned int sample_width;
 	unsigned int sample_rate;
+	unsigned int channels;
 	unsigned int audio_cts;
 	unsigned int audio_n;
 	bool audio_enable;
@@ -589,6 +592,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 			n = 4096;
 		else if (pixel_clk == 74176000 || pixel_clk == 148352000)
 			n = 11648;
+		else if (pixel_clk == 297000000)
+			n = 3072;
 		else
 			n = 4096;
 		n *= mult;
@@ -601,6 +606,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 			n = 17836;
 		else if (pixel_clk == 148352000)
 			n = 8918;
+		else if (pixel_clk == 297000000)
+			n = 4704;
 		else
 			n = 6272;
 		n *= mult;
@@ -615,6 +622,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 			n = 11648;
 		else if (pixel_clk == 148352000)
 			n = 5824;
+		else if (pixel_clk == 297000000)
+			n = 5120;
 		else
 			n = 6144;
 		n *= mult;
@@ -659,8 +668,8 @@ static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 
 	config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
 
-	/* Only compute CTS when using internal AHB audio */
-	if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
+	/* Compute CTS when using internal AHB audio or General Parallel audio*/
+	if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) {
 		/*
 		 * Compute the CTS value from the N value.  Note that CTS and N
 		 * can be up to 20 bits in total, so we need 64-bit math.  Also
@@ -702,6 +711,22 @@ static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 	mutex_unlock(&hdmi->audio_mutex);
 }
 
+void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width)
+{
+	mutex_lock(&hdmi->audio_mutex);
+	hdmi->sample_width = width;
+	mutex_unlock(&hdmi->audio_mutex);
+}
+EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_width);
+
+void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm)
+{
+	mutex_lock(&hdmi->audio_mutex);
+	hdmi->sample_non_pcm = non_pcm;
+	mutex_unlock(&hdmi->audio_mutex);
+}
+EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_non_pcm);
+
 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 {
 	mutex_lock(&hdmi->audio_mutex);
@@ -717,6 +742,7 @@ void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
 	u8 layout;
 
 	mutex_lock(&hdmi->audio_mutex);
+	hdmi->channels = cnt;
 
 	/*
 	 * For >2 channel PCM audio, we need to select layout 1
@@ -765,6 +791,89 @@ static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)
 	return hdmi->curr_conn->eld;
 }
 
+static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi)
+{
+	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
+	int sample_freq = 0x2, org_sample_freq = 0xD;
+	int ch_mask = BIT(hdmi->channels) - 1;
+
+	switch (hdmi->sample_rate) {
+	case 32000:
+		sample_freq = 0x03;
+		org_sample_freq = 0x0C;
+		break;
+	case 44100:
+		sample_freq = 0x00;
+		org_sample_freq = 0x0F;
+		break;
+	case 48000:
+		sample_freq = 0x02;
+		org_sample_freq = 0x0D;
+		break;
+	case 88200:
+		sample_freq = 0x08;
+		org_sample_freq = 0x07;
+		break;
+	case 96000:
+		sample_freq = 0x0A;
+		org_sample_freq = 0x05;
+		break;
+	case 176400:
+		sample_freq = 0x0C;
+		org_sample_freq = 0x03;
+		break;
+	case 192000:
+		sample_freq = 0x0E;
+		org_sample_freq = 0x01;
+		break;
+	default:
+		break;
+	}
+
+	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
+	hdmi_enable_audio_clk(hdmi, true);
+
+	hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNLS0);
+	hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2);
+	hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS3);
+	hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS4);
+	hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS5);
+	hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS6);
+	hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7);
+	hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8);
+
+	hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1);
+	hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2);
+	hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0);
+
+	hdmi_modb(hdmi,  0x3, 0x3, HDMI_FC_DATAUTO3);
+
+	/* hbr */
+	if (hdmi->sample_rate == 192000 && hdmi->channels == 8 &&
+			hdmi->sample_width == 32 && hdmi->sample_non_pcm)
+		hdmi_modb(hdmi, 0x01, 0x01, HDMI_GP_CONF2);
+
+	if (pdata->enable_audio)
+		pdata->enable_audio(hdmi,
+					    hdmi->channels,
+					    hdmi->sample_width,
+					    hdmi->sample_rate,
+					    hdmi->sample_non_pcm);
+}
+
+static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi)
+{
+	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
+
+	hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
+
+	hdmi_modb(hdmi,  0, 0x3, HDMI_FC_DATAUTO3);
+	if (pdata->disable_audio)
+		pdata->disable_audio(hdmi);
+
+	hdmi_enable_audio_clk(hdmi, false);
+}
+
 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
 {
 	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
@@ -3258,6 +3367,7 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
 	hdmi->plat_data = plat_data;
 	hdmi->dev = dev;
 	hdmi->sample_rate = 48000;
+	hdmi->channels = 2;
 	hdmi->disabled = true;
 	hdmi->rxsense = true;
 	hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
@@ -3481,6 +3591,24 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
 		pdevinfo.size_data = sizeof(audio);
 		pdevinfo.dma_mask = DMA_BIT_MASK(32);
 		hdmi->audio = platform_device_register_full(&pdevinfo);
+	} else if (iores && config3 & HDMI_CONFIG3_GPAUD) {
+		struct dw_hdmi_audio_data audio;
+
+		audio.phys = iores->start;
+		audio.base = hdmi->regs;
+		audio.irq = irq;
+		audio.hdmi = hdmi;
+		audio.get_eld = hdmi_audio_get_eld;
+
+		hdmi->enable_audio = dw_hdmi_gp_audio_enable;
+		hdmi->disable_audio = dw_hdmi_gp_audio_disable;
+
+		pdevinfo.name = "dw-hdmi-gp-audio";
+		pdevinfo.id = PLATFORM_DEVID_NONE;
+		pdevinfo.data = &audio;
+		pdevinfo.size_data = sizeof(audio);
+		pdevinfo.dma_mask = DMA_BIT_MASK(32);
+		hdmi->audio = platform_device_register_full(&pdevinfo);
 	}
 
 	if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) {
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
index 18df3e119553..af43a0414b78 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
@@ -158,8 +158,17 @@
 #define HDMI_FC_SPDDEVICEINF                    0x1062
 #define HDMI_FC_AUDSCONF                        0x1063
 #define HDMI_FC_AUDSSTAT                        0x1064
-#define HDMI_FC_AUDSCHNLS7                      0x106e
-#define HDMI_FC_AUDSCHNLS8                      0x106f
+#define HDMI_FC_AUDSV                           0x1065
+#define HDMI_FC_AUDSU                           0x1066
+#define HDMI_FC_AUDSCHNLS0                       0x1067
+#define HDMI_FC_AUDSCHNLS1                       0x1068
+#define HDMI_FC_AUDSCHNLS2                       0x1069
+#define HDMI_FC_AUDSCHNLS3                       0x106A
+#define HDMI_FC_AUDSCHNLS4                       0x106B
+#define HDMI_FC_AUDSCHNLS5                       0x106C
+#define HDMI_FC_AUDSCHNLS6                       0x106D
+#define HDMI_FC_AUDSCHNLS7                       0x106E
+#define HDMI_FC_AUDSCHNLS8                       0x106F
 #define HDMI_FC_DATACH0FILL                     0x1070
 #define HDMI_FC_DATACH1FILL                     0x1071
 #define HDMI_FC_DATACH2FILL                     0x1072
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 70082f80a8c8..f668e75fbabe 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -143,6 +143,11 @@ struct dw_hdmi_plat_data {
 					   const struct drm_display_info *info,
 					   const struct drm_display_mode *mode);
 
+	/* Platform-specific audio enable/disable (optional) */
+	void (*enable_audio)(struct dw_hdmi *hdmi, int channel,
+			     int width, int rate, int non_pcm);
+	void (*disable_audio)(struct dw_hdmi *hdmi);
+
 	/* Vendor PHY support */
 	const struct dw_hdmi_phy_ops *phy_ops;
 	const char *phy_name;
@@ -173,6 +178,8 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
 
 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
 			   struct device *codec_dev);
+void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm);
+void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width);
 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt);
 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status);
-- 
2.25.1

[PATCH v3 4/4] drm: bridge: dw_hdmi: Audio: Add General Parallel Audio (GPA) driver

[Sandor.yu]

From: Sandor Yu <Sandor.yu@nxp.com>

General Parallel Audio (GPA) interface is one of the supported
audio interface for synopsys HDMI module, which has verified for
i.MX8MPlus platform.
This is initial version for GPA.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
---
 drivers/gpu/drm/bridge/synopsys/Kconfig       |  10 +
 drivers/gpu/drm/bridge/synopsys/Makefile      |   1 +
 .../drm/bridge/synopsys/dw-hdmi-gp-audio.c    | 199 ++++++++++++++++++
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c     | 132 +++++++++++-
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h     |  13 +-
 include/drm/bridge/dw_hdmi.h                  |   7 +
 6 files changed, 358 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c

diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig
index 21a1be3ced0f..a4a31b669b65 100644
--- a/drivers/gpu/drm/bridge/synopsys/Kconfig
+++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
@@ -25,6 +25,16 @@ config DRM_DW_HDMI_I2S_AUDIO
 	  Support the I2S Audio interface which is part of the Synopsys
 	  Designware HDMI block.
 
+config DRM_DW_HDMI_GP_AUDIO
+	tristate "Synopsys Designware GP Audio interface"
+	depends on DRM_DW_HDMI && SND
+	select SND_PCM
+	select SND_PCM_ELD
+	select SND_PCM_IEC958
+	help
+	  Support the GP Audio interface which is part of the Synopsys
+	  Designware HDMI block.
+
 config DRM_DW_HDMI_CEC
 	tristate "Synopsis Designware CEC interface"
 	depends on DRM_DW_HDMI
diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile
index 91d746ad5de1..ce715562e9e5 100644
--- a/drivers/gpu/drm/bridge/synopsys/Makefile
+++ b/drivers/gpu/drm/bridge/synopsys/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
+obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o
 obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
 obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o
 
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c
new file mode 100644
index 000000000000..8ca401b0dc2b
--- /dev/null
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * dw-hdmi-gp-audio.c
+ *
+ * Copyright 2020-2022 NXP
+ */
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <drm/bridge/dw_hdmi.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_connector.h>
+
+#include <sound/hdmi-codec.h>
+#include <sound/asoundef.h>
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <sound/pcm.h>
+#include <sound/pcm_drm_eld.h>
+#include <sound/pcm_iec958.h>
+#include <sound/dmaengine_pcm.h>
+
+#include "dw-hdmi-audio.h"
+
+#define DRIVER_NAME "dw-hdmi-gp-audio"
+#define DRV_NAME    "hdmi-gp-audio"
+
+struct snd_dw_hdmi {
+	struct dw_hdmi_audio_data data;
+	struct platform_device  *audio_pdev;
+	unsigned int pos;
+};
+
+struct dw_hdmi_channel_conf {
+	u8 conf1;
+	u8 ca;
+};
+
+/*
+ * The default mapping of ALSA channels to HDMI channels and speaker
+ * allocation bits.  Note that we can't do channel remapping here -
+ * channels must be in the same order.
+ *
+ * Mappings for alsa-lib pcm/surround*.conf files:
+ *
+ *		Front	Sur4.0	Sur4.1	Sur5.0	Sur5.1	Sur7.1
+ * Channels	2	4	6	6	6	8
+ *
+ * Our mapping from ALSA channel to CEA686D speaker name and HDMI channel:
+ *
+ *				Number of ALSA channels
+ * ALSA Channel	2	3	4	5	6	7	8
+ * 0		FL:0	=	=	=	=	=	=
+ * 1		FR:1	=	=	=	=	=	=
+ * 2			FC:3	RL:4	LFE:2	=	=	=
+ * 3				RR:5	RL:4	FC:3	=	=
+ * 4					RR:5	RL:4	=	=
+ * 5						RR:5	=	=
+ * 6							RC:6	=
+ * 7							RLC/FRC	RLC/FRC
+ */
+static struct dw_hdmi_channel_conf default_hdmi_channel_config[7] = {
+	{ 0x03, 0x00 },	/* FL,FR */
+	{ 0x0b, 0x02 },	/* FL,FR,FC */
+	{ 0x33, 0x08 },	/* FL,FR,RL,RR */
+	{ 0x37, 0x09 },	/* FL,FR,LFE,RL,RR */
+	{ 0x3f, 0x0b },	/* FL,FR,LFE,FC,RL,RR */
+	{ 0x7f, 0x0f },	/* FL,FR,LFE,FC,RL,RR,RC */
+	{ 0xff, 0x13 },	/* FL,FR,LFE,FC,RL,RR,[FR]RC,[FR]LC */
+};
+
+static int audio_hw_params(struct device *dev,  void *data,
+			   struct hdmi_codec_daifmt *daifmt,
+			   struct hdmi_codec_params *params)
+{
+	struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
+	int ret = 0;
+	u8 ca;
+
+	dw_hdmi_set_sample_rate(dw->data.hdmi, params->sample_rate);
+
+	ca = default_hdmi_channel_config[params->channels - 2].ca;
+
+	dw_hdmi_set_channel_count(dw->data.hdmi, params->channels);
+	dw_hdmi_set_channel_allocation(dw->data.hdmi, ca);
+
+	dw_hdmi_set_sample_non_pcm(dw->data.hdmi,
+				   params->iec.status[0] & IEC958_AES0_NONAUDIO);
+	dw_hdmi_set_sample_width(dw->data.hdmi, params->sample_width);
+
+	return ret;
+}
+
+static void audio_shutdown(struct device *dev, void *data)
+{
+}
+
+static int audio_mute_stream(struct device *dev, void *data,
+			      bool enable, int direction)
+{
+	struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
+	int ret = 0;
+
+	if (!enable)
+		dw_hdmi_audio_enable(dw->data.hdmi);
+	else
+		dw_hdmi_audio_disable(dw->data.hdmi);
+
+	return ret;
+}
+
+static int audio_get_eld(struct device *dev, void *data,
+			 u8 *buf, size_t len)
+{
+	struct dw_hdmi_audio_data *audio = data;
+	u8 *eld;
+
+	eld = audio->get_eld(audio->hdmi);
+	if (eld)
+		memcpy(buf, eld, min_t(size_t, MAX_ELD_BYTES, len));
+	else
+		/* Pass en empty ELD if connector not available */
+		memset(buf, 0, len);
+
+	return 0;
+}
+
+static int audio_hook_plugged_cb(struct device *dev, void *data,
+				 hdmi_codec_plugged_cb fn,
+				 struct device *codec_dev)
+{
+	struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
+
+	return dw_hdmi_set_plugged_cb(dw->data.hdmi, fn, codec_dev);
+}
+
+static const struct hdmi_codec_ops audio_codec_ops = {
+	.hw_params = audio_hw_params,
+	.audio_shutdown = audio_shutdown,
+	.mute_stream = audio_mute_stream,
+	.get_eld = audio_get_eld,
+	.hook_plugged_cb = audio_hook_plugged_cb,
+};
+
+static int snd_dw_hdmi_probe(struct platform_device *pdev)
+{
+	struct dw_hdmi_audio_data *data = pdev->dev.platform_data;
+	struct snd_dw_hdmi *dw;
+
+	const struct hdmi_codec_pdata codec_data = {
+		.i2s = 1,
+		.spdif = 0,
+		.ops = &audio_codec_ops,
+		.max_i2s_channels = 8,
+		.data = data,
+	};
+
+	dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL);
+	if (!dw)
+		return -ENOMEM;
+
+	dw->data = *data;
+
+	platform_set_drvdata(pdev, dw);
+
+	dw->audio_pdev = platform_device_register_data(&pdev->dev,
+						       HDMI_CODEC_DRV_NAME, 1,
+						       &codec_data,
+						       sizeof(codec_data));
+
+	return PTR_ERR_OR_ZERO(dw->audio_pdev);
+}
+
+static int snd_dw_hdmi_remove(struct platform_device *pdev)
+{
+	struct snd_dw_hdmi *dw = platform_get_drvdata(pdev);
+
+	platform_device_unregister(dw->audio_pdev);
+
+	return 0;
+}
+
+static struct platform_driver snd_dw_hdmi_driver = {
+	.probe	= snd_dw_hdmi_probe,
+	.remove	= snd_dw_hdmi_remove,
+	.driver	= {
+		.name = DRIVER_NAME,
+	},
+};
+
+module_platform_driver(snd_dw_hdmi_driver);
+
+MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>");
+MODULE_DESCRIPTION("Synopsys Designware HDMI GPA ALSA interface");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index ac98605a6811..f51e199a7493 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -191,7 +191,10 @@ struct dw_hdmi {
 
 	spinlock_t audio_lock;
 	struct mutex audio_mutex;
+	unsigned int sample_non_pcm;
+	unsigned int sample_width;
 	unsigned int sample_rate;
+	unsigned int channels;
 	unsigned int audio_cts;
 	unsigned int audio_n;
 	bool audio_enable;
@@ -589,6 +592,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 			n = 4096;
 		else if (pixel_clk == 74176000 || pixel_clk == 148352000)
 			n = 11648;
+		else if (pixel_clk == 297000000)
+			n = 3072;
 		else
 			n = 4096;
 		n *= mult;
@@ -601,6 +606,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 			n = 17836;
 		else if (pixel_clk == 148352000)
 			n = 8918;
+		else if (pixel_clk == 297000000)
+			n = 4704;
 		else
 			n = 6272;
 		n *= mult;
@@ -615,6 +622,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 			n = 11648;
 		else if (pixel_clk == 148352000)
 			n = 5824;
+		else if (pixel_clk == 297000000)
+			n = 5120;
 		else
 			n = 6144;
 		n *= mult;
@@ -659,8 +668,8 @@ static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 
 	config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
 
-	/* Only compute CTS when using internal AHB audio */
-	if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
+	/* Compute CTS when using internal AHB audio or General Parallel audio*/
+	if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) {
 		/*
 		 * Compute the CTS value from the N value.  Note that CTS and N
 		 * can be up to 20 bits in total, so we need 64-bit math.  Also
@@ -702,6 +711,22 @@ static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 	mutex_unlock(&hdmi->audio_mutex);
 }
 
+void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width)
+{
+	mutex_lock(&hdmi->audio_mutex);
+	hdmi->sample_width = width;
+	mutex_unlock(&hdmi->audio_mutex);
+}
+EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_width);
+
+void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm)
+{
+	mutex_lock(&hdmi->audio_mutex);
+	hdmi->sample_non_pcm = non_pcm;
+	mutex_unlock(&hdmi->audio_mutex);
+}
+EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_non_pcm);
+
 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 {
 	mutex_lock(&hdmi->audio_mutex);
@@ -717,6 +742,7 @@ void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
 	u8 layout;
 
 	mutex_lock(&hdmi->audio_mutex);
+	hdmi->channels = cnt;
 
 	/*
 	 * For >2 channel PCM audio, we need to select layout 1
@@ -765,6 +791,89 @@ static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)
 	return hdmi->curr_conn->eld;
 }
 
+static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi)
+{
+	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
+	int sample_freq = 0x2, org_sample_freq = 0xD;
+	int ch_mask = BIT(hdmi->channels) - 1;
+
+	switch (hdmi->sample_rate) {
+	case 32000:
+		sample_freq = 0x03;
+		org_sample_freq = 0x0C;
+		break;
+	case 44100:
+		sample_freq = 0x00;
+		org_sample_freq = 0x0F;
+		break;
+	case 48000:
+		sample_freq = 0x02;
+		org_sample_freq = 0x0D;
+		break;
+	case 88200:
+		sample_freq = 0x08;
+		org_sample_freq = 0x07;
+		break;
+	case 96000:
+		sample_freq = 0x0A;
+		org_sample_freq = 0x05;
+		break;
+	case 176400:
+		sample_freq = 0x0C;
+		org_sample_freq = 0x03;
+		break;
+	case 192000:
+		sample_freq = 0x0E;
+		org_sample_freq = 0x01;
+		break;
+	default:
+		break;
+	}
+
+	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
+	hdmi_enable_audio_clk(hdmi, true);
+
+	hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNLS0);
+	hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2);
+	hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS3);
+	hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS4);
+	hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS5);
+	hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS6);
+	hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7);
+	hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8);
+
+	hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1);
+	hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2);
+	hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0);
+
+	hdmi_modb(hdmi,  0x3, 0x3, HDMI_FC_DATAUTO3);
+
+	/* hbr */
+	if (hdmi->sample_rate == 192000 && hdmi->channels == 8 &&
+			hdmi->sample_width == 32 && hdmi->sample_non_pcm)
+		hdmi_modb(hdmi, 0x01, 0x01, HDMI_GP_CONF2);
+
+	if (pdata->enable_audio)
+		pdata->enable_audio(hdmi,
+					    hdmi->channels,
+					    hdmi->sample_width,
+					    hdmi->sample_rate,
+					    hdmi->sample_non_pcm);
+}
+
+static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi)
+{
+	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
+
+	hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
+
+	hdmi_modb(hdmi,  0, 0x3, HDMI_FC_DATAUTO3);
+	if (pdata->disable_audio)
+		pdata->disable_audio(hdmi);
+
+	hdmi_enable_audio_clk(hdmi, false);
+}
+
 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
 {
 	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
@@ -3258,6 +3367,7 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
 	hdmi->plat_data = plat_data;
 	hdmi->dev = dev;
 	hdmi->sample_rate = 48000;
+	hdmi->channels = 2;
 	hdmi->disabled = true;
 	hdmi->rxsense = true;
 	hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
@@ -3481,6 +3591,24 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
 		pdevinfo.size_data = sizeof(audio);
 		pdevinfo.dma_mask = DMA_BIT_MASK(32);
 		hdmi->audio = platform_device_register_full(&pdevinfo);
+	} else if (iores && config3 & HDMI_CONFIG3_GPAUD) {
+		struct dw_hdmi_audio_data audio;
+
+		audio.phys = iores->start;
+		audio.base = hdmi->regs;
+		audio.irq = irq;
+		audio.hdmi = hdmi;
+		audio.get_eld = hdmi_audio_get_eld;
+
+		hdmi->enable_audio = dw_hdmi_gp_audio_enable;
+		hdmi->disable_audio = dw_hdmi_gp_audio_disable;
+
+		pdevinfo.name = "dw-hdmi-gp-audio";
+		pdevinfo.id = PLATFORM_DEVID_NONE;
+		pdevinfo.data = &audio;
+		pdevinfo.size_data = sizeof(audio);
+		pdevinfo.dma_mask = DMA_BIT_MASK(32);
+		hdmi->audio = platform_device_register_full(&pdevinfo);
 	}
 
 	if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) {
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
index 18df3e119553..af43a0414b78 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
@@ -158,8 +158,17 @@
 #define HDMI_FC_SPDDEVICEINF                    0x1062
 #define HDMI_FC_AUDSCONF                        0x1063
 #define HDMI_FC_AUDSSTAT                        0x1064
-#define HDMI_FC_AUDSCHNLS7                      0x106e
-#define HDMI_FC_AUDSCHNLS8                      0x106f
+#define HDMI_FC_AUDSV                           0x1065
+#define HDMI_FC_AUDSU                           0x1066
+#define HDMI_FC_AUDSCHNLS0                       0x1067
+#define HDMI_FC_AUDSCHNLS1                       0x1068
+#define HDMI_FC_AUDSCHNLS2                       0x1069
+#define HDMI_FC_AUDSCHNLS3                       0x106A
+#define HDMI_FC_AUDSCHNLS4                       0x106B
+#define HDMI_FC_AUDSCHNLS5                       0x106C
+#define HDMI_FC_AUDSCHNLS6                       0x106D
+#define HDMI_FC_AUDSCHNLS7                       0x106E
+#define HDMI_FC_AUDSCHNLS8                       0x106F
 #define HDMI_FC_DATACH0FILL                     0x1070
 #define HDMI_FC_DATACH1FILL                     0x1071
 #define HDMI_FC_DATACH2FILL                     0x1072
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 70082f80a8c8..f668e75fbabe 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -143,6 +143,11 @@ struct dw_hdmi_plat_data {
 					   const struct drm_display_info *info,
 					   const struct drm_display_mode *mode);
 
+	/* Platform-specific audio enable/disable (optional) */
+	void (*enable_audio)(struct dw_hdmi *hdmi, int channel,
+			     int width, int rate, int non_pcm);
+	void (*disable_audio)(struct dw_hdmi *hdmi);
+
 	/* Vendor PHY support */
 	const struct dw_hdmi_phy_ops *phy_ops;
 	const char *phy_name;
@@ -173,6 +178,8 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
 
 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
 			   struct device *codec_dev);
+void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm);
+void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width);
 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt);
 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status);
-- 
2.25.1

Re: [PATCH v3 4/4] drm: bridge: dw_hdmi: Audio: Add General Parallel Audio (GPA) driver

[Neil Armstrong]

On 15/04/2022 04:42, Sandor.yu@nxp.com wrote:
> From: Sandor Yu <Sandor.yu@nxp.com>
> 
> General Parallel Audio (GPA) interface is one of the supported
> audio interface for synopsys HDMI module, which has verified for
> i.MX8MPlus platform.
> This is initial version for GPA.
> 
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> ---
>   drivers/gpu/drm/bridge/synopsys/Kconfig       |  10 +
>   drivers/gpu/drm/bridge/synopsys/Makefile      |   1 +
>   .../drm/bridge/synopsys/dw-hdmi-gp-audio.c    | 199 ++++++++++++++++++
>   drivers/gpu/drm/bridge/synopsys/dw-hdmi.c     | 132 +++++++++++-
>   drivers/gpu/drm/bridge/synopsys/dw-hdmi.h     |  13 +-
>   include/drm/bridge/dw_hdmi.h                  |   7 +
>   6 files changed, 358 insertions(+), 4 deletions(-)
>   create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig
> index 21a1be3ced0f..a4a31b669b65 100644
> --- a/drivers/gpu/drm/bridge/synopsys/Kconfig
> +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
> @@ -25,6 +25,16 @@ config DRM_DW_HDMI_I2S_AUDIO
>   	  Support the I2S Audio interface which is part of the Synopsys
>   	  Designware HDMI block.
>   
> +config DRM_DW_HDMI_GP_AUDIO
> +	tristate "Synopsys Designware GP Audio interface"
> +	depends on DRM_DW_HDMI && SND
> +	select SND_PCM
> +	select SND_PCM_ELD
> +	select SND_PCM_IEC958
> +	help
> +	  Support the GP Audio interface which is part of the Synopsys
> +	  Designware HDMI block.
> +
>   config DRM_DW_HDMI_CEC
>   	tristate "Synopsis Designware CEC interface"
>   	depends on DRM_DW_HDMI
> diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile
> index 91d746ad5de1..ce715562e9e5 100644
> --- a/drivers/gpu/drm/bridge/synopsys/Makefile
> +++ b/drivers/gpu/drm/bridge/synopsys/Makefile
> @@ -1,6 +1,7 @@
>   # SPDX-License-Identifier: GPL-2.0-only
>   obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
>   obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
> +obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o
>   obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
>   obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o
>   
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c
> new file mode 100644
> index 000000000000..8ca401b0dc2b
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c
> @@ -0,0 +1,199 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * dw-hdmi-gp-audio.c
> + *
> + * Copyright 2020-2022 NXP
> + */
> +#include <linux/io.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/dmaengine.h>
> +#include <linux/dma-mapping.h>
> +#include <drm/bridge/dw_hdmi.h>
> +#include <drm/drm_edid.h>
> +#include <drm/drm_connector.h>
> +
> +#include <sound/hdmi-codec.h>
> +#include <sound/asoundef.h>
> +#include <sound/core.h>
> +#include <sound/initval.h>
> +#include <sound/pcm.h>
> +#include <sound/pcm_drm_eld.h>
> +#include <sound/pcm_iec958.h>
> +#include <sound/dmaengine_pcm.h>
> +
> +#include "dw-hdmi-audio.h"
> +
> +#define DRIVER_NAME "dw-hdmi-gp-audio"
> +#define DRV_NAME    "hdmi-gp-audio"
> +
> +struct snd_dw_hdmi {
> +	struct dw_hdmi_audio_data data;
> +	struct platform_device  *audio_pdev;
> +	unsigned int pos;
> +};
> +
> +struct dw_hdmi_channel_conf {
> +	u8 conf1;
> +	u8 ca;
> +};
> +
> +/*
> + * The default mapping of ALSA channels to HDMI channels and speaker
> + * allocation bits.  Note that we can't do channel remapping here -
> + * channels must be in the same order.
> + *
> + * Mappings for alsa-lib pcm/surround*.conf files:
> + *
> + *		Front	Sur4.0	Sur4.1	Sur5.0	Sur5.1	Sur7.1
> + * Channels	2	4	6	6	6	8
> + *
> + * Our mapping from ALSA channel to CEA686D speaker name and HDMI channel:
> + *
> + *				Number of ALSA channels
> + * ALSA Channel	2	3	4	5	6	7	8
> + * 0		FL:0	=	=	=	=	=	=
> + * 1		FR:1	=	=	=	=	=	=
> + * 2			FC:3	RL:4	LFE:2	=	=	=
> + * 3				RR:5	RL:4	FC:3	=	=
> + * 4					RR:5	RL:4	=	=
> + * 5						RR:5	=	=
> + * 6							RC:6	=
> + * 7							RLC/FRC	RLC/FRC
> + */
> +static struct dw_hdmi_channel_conf default_hdmi_channel_config[7] = {
> +	{ 0x03, 0x00 },	/* FL,FR */
> +	{ 0x0b, 0x02 },	/* FL,FR,FC */
> +	{ 0x33, 0x08 },	/* FL,FR,RL,RR */
> +	{ 0x37, 0x09 },	/* FL,FR,LFE,RL,RR */
> +	{ 0x3f, 0x0b },	/* FL,FR,LFE,FC,RL,RR */
> +	{ 0x7f, 0x0f },	/* FL,FR,LFE,FC,RL,RR,RC */
> +	{ 0xff, 0x13 },	/* FL,FR,LFE,FC,RL,RR,[FR]RC,[FR]LC */
> +};
> +
> +static int audio_hw_params(struct device *dev,  void *data,
> +			   struct hdmi_codec_daifmt *daifmt,
> +			   struct hdmi_codec_params *params)
> +{
> +	struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
> +	int ret = 0;
> +	u8 ca;
> +
> +	dw_hdmi_set_sample_rate(dw->data.hdmi, params->sample_rate);
> +
> +	ca = default_hdmi_channel_config[params->channels - 2].ca;
> +
> +	dw_hdmi_set_channel_count(dw->data.hdmi, params->channels);
> +	dw_hdmi_set_channel_allocation(dw->data.hdmi, ca);
> +
> +	dw_hdmi_set_sample_non_pcm(dw->data.hdmi,
> +				   params->iec.status[0] & IEC958_AES0_NONAUDIO);
> +	dw_hdmi_set_sample_width(dw->data.hdmi, params->sample_width);
> +
> +	return ret;
> +}
> +
> +static void audio_shutdown(struct device *dev, void *data)
> +{
> +}
> +
> +static int audio_mute_stream(struct device *dev, void *data,
> +			      bool enable, int direction)
> +{
> +	struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
> +	int ret = 0;
> +
> +	if (!enable)
> +		dw_hdmi_audio_enable(dw->data.hdmi);
> +	else
> +		dw_hdmi_audio_disable(dw->data.hdmi);
> +
> +	return ret;
> +}
> +
> +static int audio_get_eld(struct device *dev, void *data,
> +			 u8 *buf, size_t len)
> +{
> +	struct dw_hdmi_audio_data *audio = data;
> +	u8 *eld;
> +
> +	eld = audio->get_eld(audio->hdmi);
> +	if (eld)
> +		memcpy(buf, eld, min_t(size_t, MAX_ELD_BYTES, len));
> +	else
> +		/* Pass en empty ELD if connector not available */
> +		memset(buf, 0, len);
> +
> +	return 0;
> +}
> +
> +static int audio_hook_plugged_cb(struct device *dev, void *data,
> +				 hdmi_codec_plugged_cb fn,
> +				 struct device *codec_dev)
> +{
> +	struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
> +
> +	return dw_hdmi_set_plugged_cb(dw->data.hdmi, fn, codec_dev);
> +}
> +
> +static const struct hdmi_codec_ops audio_codec_ops = {
> +	.hw_params = audio_hw_params,
> +	.audio_shutdown = audio_shutdown,
> +	.mute_stream = audio_mute_stream,
> +	.get_eld = audio_get_eld,
> +	.hook_plugged_cb = audio_hook_plugged_cb,
> +};
> +
> +static int snd_dw_hdmi_probe(struct platform_device *pdev)
> +{
> +	struct dw_hdmi_audio_data *data = pdev->dev.platform_data;
> +	struct snd_dw_hdmi *dw;
> +
> +	const struct hdmi_codec_pdata codec_data = {
> +		.i2s = 1,
> +		.spdif = 0,
> +		.ops = &audio_codec_ops,
> +		.max_i2s_channels = 8,
> +		.data = data,
> +	};
> +
> +	dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL);
> +	if (!dw)
> +		return -ENOMEM;
> +
> +	dw->data = *data;
> +
> +	platform_set_drvdata(pdev, dw);
> +
> +	dw->audio_pdev = platform_device_register_data(&pdev->dev,
> +						       HDMI_CODEC_DRV_NAME, 1,
> +						       &codec_data,
> +						       sizeof(codec_data));
> +
> +	return PTR_ERR_OR_ZERO(dw->audio_pdev);
> +}
> +
> +static int snd_dw_hdmi_remove(struct platform_device *pdev)
> +{
> +	struct snd_dw_hdmi *dw = platform_get_drvdata(pdev);
> +
> +	platform_device_unregister(dw->audio_pdev);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver snd_dw_hdmi_driver = {
> +	.probe	= snd_dw_hdmi_probe,
> +	.remove	= snd_dw_hdmi_remove,
> +	.driver	= {
> +		.name = DRIVER_NAME,
> +	},
> +};
> +
> +module_platform_driver(snd_dw_hdmi_driver);
> +
> +MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>");
> +MODULE_DESCRIPTION("Synopsys Designware HDMI GPA ALSA interface");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:" DRIVER_NAME);
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index ac98605a6811..f51e199a7493 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -191,7 +191,10 @@ struct dw_hdmi {
>   
>   	spinlock_t audio_lock;
>   	struct mutex audio_mutex;
> +	unsigned int sample_non_pcm;
> +	unsigned int sample_width;
>   	unsigned int sample_rate;
> +	unsigned int channels;
>   	unsigned int audio_cts;
>   	unsigned int audio_n;
>   	bool audio_enable;
> @@ -589,6 +592,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
>   			n = 4096;
>   		else if (pixel_clk == 74176000 || pixel_clk == 148352000)
>   			n = 11648;
> +		else if (pixel_clk == 297000000)
> +			n = 3072;
>   		else
>   			n = 4096;
>   		n *= mult;
> @@ -601,6 +606,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
>   			n = 17836;
>   		else if (pixel_clk == 148352000)
>   			n = 8918;
> +		else if (pixel_clk == 297000000)
> +			n = 4704;
>   		else
>   			n = 6272;
>   		n *= mult;
> @@ -615,6 +622,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
>   			n = 11648;
>   		else if (pixel_clk == 148352000)
>   			n = 5824;
> +		else if (pixel_clk == 297000000)
> +			n = 5120;
>   		else
>   			n = 6144;
>   		n *= mult;
> @@ -659,8 +668,8 @@ static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
>   
>   	config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
>   
> -	/* Only compute CTS when using internal AHB audio */
> -	if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
> +	/* Compute CTS when using internal AHB audio or General Parallel audio*/
> +	if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) {
>   		/*
>   		 * Compute the CTS value from the N value.  Note that CTS and N
>   		 * can be up to 20 bits in total, so we need 64-bit math.  Also
> @@ -702,6 +711,22 @@ static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
>   	mutex_unlock(&hdmi->audio_mutex);
>   }
>   
> +void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width)
> +{
> +	mutex_lock(&hdmi->audio_mutex);
> +	hdmi->sample_width = width;
> +	mutex_unlock(&hdmi->audio_mutex);
> +}
> +EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_width);
> +
> +void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm)
> +{
> +	mutex_lock(&hdmi->audio_mutex);
> +	hdmi->sample_non_pcm = non_pcm;
> +	mutex_unlock(&hdmi->audio_mutex);
> +}
> +EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_non_pcm);
> +
>   void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
>   {
>   	mutex_lock(&hdmi->audio_mutex);
> @@ -717,6 +742,7 @@ void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
>   	u8 layout;
>   
>   	mutex_lock(&hdmi->audio_mutex);
> +	hdmi->channels = cnt;
>   
>   	/*
>   	 * For >2 channel PCM audio, we need to select layout 1
> @@ -765,6 +791,89 @@ static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)
>   	return hdmi->curr_conn->eld;
>   }
>   
> +static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi)
> +{
> +	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
> +	int sample_freq = 0x2, org_sample_freq = 0xD;
> +	int ch_mask = BIT(hdmi->channels) - 1;
> +
> +	switch (hdmi->sample_rate) {
> +	case 32000:
> +		sample_freq = 0x03;
> +		org_sample_freq = 0x0C;
> +		break;
> +	case 44100:
> +		sample_freq = 0x00;
> +		org_sample_freq = 0x0F;
> +		break;
> +	case 48000:
> +		sample_freq = 0x02;
> +		org_sample_freq = 0x0D;
> +		break;
> +	case 88200:
> +		sample_freq = 0x08;
> +		org_sample_freq = 0x07;
> +		break;
> +	case 96000:
> +		sample_freq = 0x0A;
> +		org_sample_freq = 0x05;
> +		break;
> +	case 176400:
> +		sample_freq = 0x0C;
> +		org_sample_freq = 0x03;
> +		break;
> +	case 192000:
> +		sample_freq = 0x0E;
> +		org_sample_freq = 0x01;
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
> +	hdmi_enable_audio_clk(hdmi, true);
> +
> +	hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNLS0);
> +	hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2);
> +	hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS3);
> +	hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS4);
> +	hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS5);
> +	hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS6);
> +	hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7);
> +	hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8);
> +
> +	hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1);
> +	hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2);
> +	hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0);
> +
> +	hdmi_modb(hdmi,  0x3, 0x3, HDMI_FC_DATAUTO3);
> +
> +	/* hbr */
> +	if (hdmi->sample_rate == 192000 && hdmi->channels == 8 &&
> +			hdmi->sample_width == 32 && hdmi->sample_non_pcm)
> +		hdmi_modb(hdmi, 0x01, 0x01, HDMI_GP_CONF2);
> +
> +	if (pdata->enable_audio)
> +		pdata->enable_audio(hdmi,
> +					    hdmi->channels,
> +					    hdmi->sample_width,
> +					    hdmi->sample_rate,
> +					    hdmi->sample_non_pcm);
> +}
> +
> +static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi)
> +{
> +	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
> +
> +	hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
> +
> +	hdmi_modb(hdmi,  0, 0x3, HDMI_FC_DATAUTO3);
> +	if (pdata->disable_audio)
> +		pdata->disable_audio(hdmi);
> +
> +	hdmi_enable_audio_clk(hdmi, false);
> +}
> +
>   static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
>   {
>   	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
> @@ -3258,6 +3367,7 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
>   	hdmi->plat_data = plat_data;
>   	hdmi->dev = dev;
>   	hdmi->sample_rate = 48000;
> +	hdmi->channels = 2;
>   	hdmi->disabled = true;
>   	hdmi->rxsense = true;
>   	hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
> @@ -3481,6 +3591,24 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
>   		pdevinfo.size_data = sizeof(audio);
>   		pdevinfo.dma_mask = DMA_BIT_MASK(32);
>   		hdmi->audio = platform_device_register_full(&pdevinfo);
> +	} else if (iores && config3 & HDMI_CONFIG3_GPAUD) {
> +		struct dw_hdmi_audio_data audio;
> +
> +		audio.phys = iores->start;
> +		audio.base = hdmi->regs;
> +		audio.irq = irq;
> +		audio.hdmi = hdmi;
> +		audio.get_eld = hdmi_audio_get_eld;
> +
> +		hdmi->enable_audio = dw_hdmi_gp_audio_enable;
> +		hdmi->disable_audio = dw_hdmi_gp_audio_disable;
> +
> +		pdevinfo.name = "dw-hdmi-gp-audio";
> +		pdevinfo.id = PLATFORM_DEVID_NONE;
> +		pdevinfo.data = &audio;
> +		pdevinfo.size_data = sizeof(audio);
> +		pdevinfo.dma_mask = DMA_BIT_MASK(32);
> +		hdmi->audio = platform_device_register_full(&pdevinfo);
>   	}
>   
>   	if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) {
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
> index 18df3e119553..af43a0414b78 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
> @@ -158,8 +158,17 @@
>   #define HDMI_FC_SPDDEVICEINF                    0x1062
>   #define HDMI_FC_AUDSCONF                        0x1063
>   #define HDMI_FC_AUDSSTAT                        0x1064
> -#define HDMI_FC_AUDSCHNLS7                      0x106e
> -#define HDMI_FC_AUDSCHNLS8                      0x106f
> +#define HDMI_FC_AUDSV                           0x1065
> +#define HDMI_FC_AUDSU                           0x1066
> +#define HDMI_FC_AUDSCHNLS0                       0x1067
> +#define HDMI_FC_AUDSCHNLS1                       0x1068
> +#define HDMI_FC_AUDSCHNLS2                       0x1069
> +#define HDMI_FC_AUDSCHNLS3                       0x106A
> +#define HDMI_FC_AUDSCHNLS4                       0x106B
> +#define HDMI_FC_AUDSCHNLS5                       0x106C
> +#define HDMI_FC_AUDSCHNLS6                       0x106D
> +#define HDMI_FC_AUDSCHNLS7                       0x106E
> +#define HDMI_FC_AUDSCHNLS8                       0x106F
>   #define HDMI_FC_DATACH0FILL                     0x1070
>   #define HDMI_FC_DATACH1FILL                     0x1071
>   #define HDMI_FC_DATACH2FILL                     0x1072
> diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
> index 70082f80a8c8..f668e75fbabe 100644
> --- a/include/drm/bridge/dw_hdmi.h
> +++ b/include/drm/bridge/dw_hdmi.h
> @@ -143,6 +143,11 @@ struct dw_hdmi_plat_data {
>   					   const struct drm_display_info *info,
>   					   const struct drm_display_mode *mode);
>   
> +	/* Platform-specific audio enable/disable (optional) */
> +	void (*enable_audio)(struct dw_hdmi *hdmi, int channel,
> +			     int width, int rate, int non_pcm);
> +	void (*disable_audio)(struct dw_hdmi *hdmi);
> +
>   	/* Vendor PHY support */
>   	const struct dw_hdmi_phy_ops *phy_ops;
>   	const char *phy_name;
> @@ -173,6 +178,8 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
>   
>   int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
>   			   struct device *codec_dev);
> +void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm);
> +void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width);
>   void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
>   void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt);
>   void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status);

Looks fine for me

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

another review before merging would be great !

Thanks,
Neil

Re: [PATCH v3 4/4] drm: bridge: dw_hdmi: Audio: Add General Parallel Audio (GPA) driver

[Neil Armstrong]

On 15/04/2022 04:42, Sandor.yu@nxp.com wrote:
> From: Sandor Yu <Sandor.yu@nxp.com>
> 
> General Parallel Audio (GPA) interface is one of the supported
> audio interface for synopsys HDMI module, which has verified for
> i.MX8MPlus platform.
> This is initial version for GPA.
> 
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> ---
>   drivers/gpu/drm/bridge/synopsys/Kconfig       |  10 +
>   drivers/gpu/drm/bridge/synopsys/Makefile      |   1 +
>   .../drm/bridge/synopsys/dw-hdmi-gp-audio.c    | 199 ++++++++++++++++++
>   drivers/gpu/drm/bridge/synopsys/dw-hdmi.c     | 132 +++++++++++-
>   drivers/gpu/drm/bridge/synopsys/dw-hdmi.h     |  13 +-
>   include/drm/bridge/dw_hdmi.h                  |   7 +
>   6 files changed, 358 insertions(+), 4 deletions(-)
>   create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig
> index 21a1be3ced0f..a4a31b669b65 100644
> --- a/drivers/gpu/drm/bridge/synopsys/Kconfig
> +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
> @@ -25,6 +25,16 @@ config DRM_DW_HDMI_I2S_AUDIO
>   	  Support the I2S Audio interface which is part of the Synopsys
>   	  Designware HDMI block.
>   
> +config DRM_DW_HDMI_GP_AUDIO
> +	tristate "Synopsys Designware GP Audio interface"
> +	depends on DRM_DW_HDMI && SND
> +	select SND_PCM
> +	select SND_PCM_ELD
> +	select SND_PCM_IEC958
> +	help
> +	  Support the GP Audio interface which is part of the Synopsys
> +	  Designware HDMI block.
> +
>   config DRM_DW_HDMI_CEC
>   	tristate "Synopsis Designware CEC interface"
>   	depends on DRM_DW_HDMI
> diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile
> index 91d746ad5de1..ce715562e9e5 100644
> --- a/drivers/gpu/drm/bridge/synopsys/Makefile
> +++ b/drivers/gpu/drm/bridge/synopsys/Makefile
> @@ -1,6 +1,7 @@
>   # SPDX-License-Identifier: GPL-2.0-only
>   obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
>   obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
> +obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o
>   obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
>   obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o
>   
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c
> new file mode 100644
> index 000000000000..8ca401b0dc2b
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c
> @@ -0,0 +1,199 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * dw-hdmi-gp-audio.c
> + *
> + * Copyright 2020-2022 NXP
> + */
> +#include <linux/io.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/dmaengine.h>
> +#include <linux/dma-mapping.h>
> +#include <drm/bridge/dw_hdmi.h>
> +#include <drm/drm_edid.h>
> +#include <drm/drm_connector.h>
> +
> +#include <sound/hdmi-codec.h>
> +#include <sound/asoundef.h>
> +#include <sound/core.h>
> +#include <sound/initval.h>
> +#include <sound/pcm.h>
> +#include <sound/pcm_drm_eld.h>
> +#include <sound/pcm_iec958.h>
> +#include <sound/dmaengine_pcm.h>
> +
> +#include "dw-hdmi-audio.h"
> +
> +#define DRIVER_NAME "dw-hdmi-gp-audio"
> +#define DRV_NAME    "hdmi-gp-audio"
> +
> +struct snd_dw_hdmi {
> +	struct dw_hdmi_audio_data data;
> +	struct platform_device  *audio_pdev;
> +	unsigned int pos;
> +};
> +
> +struct dw_hdmi_channel_conf {
> +	u8 conf1;
> +	u8 ca;
> +};
> +
> +/*
> + * The default mapping of ALSA channels to HDMI channels and speaker
> + * allocation bits.  Note that we can't do channel remapping here -
> + * channels must be in the same order.
> + *
> + * Mappings for alsa-lib pcm/surround*.conf files:
> + *
> + *		Front	Sur4.0	Sur4.1	Sur5.0	Sur5.1	Sur7.1
> + * Channels	2	4	6	6	6	8
> + *
> + * Our mapping from ALSA channel to CEA686D speaker name and HDMI channel:
> + *
> + *				Number of ALSA channels
> + * ALSA Channel	2	3	4	5	6	7	8
> + * 0		FL:0	=	=	=	=	=	=
> + * 1		FR:1	=	=	=	=	=	=
> + * 2			FC:3	RL:4	LFE:2	=	=	=
> + * 3				RR:5	RL:4	FC:3	=	=
> + * 4					RR:5	RL:4	=	=
> + * 5						RR:5	=	=
> + * 6							RC:6	=
> + * 7							RLC/FRC	RLC/FRC
> + */
> +static struct dw_hdmi_channel_conf default_hdmi_channel_config[7] = {
> +	{ 0x03, 0x00 },	/* FL,FR */
> +	{ 0x0b, 0x02 },	/* FL,FR,FC */
> +	{ 0x33, 0x08 },	/* FL,FR,RL,RR */
> +	{ 0x37, 0x09 },	/* FL,FR,LFE,RL,RR */
> +	{ 0x3f, 0x0b },	/* FL,FR,LFE,FC,RL,RR */
> +	{ 0x7f, 0x0f },	/* FL,FR,LFE,FC,RL,RR,RC */
> +	{ 0xff, 0x13 },	/* FL,FR,LFE,FC,RL,RR,[FR]RC,[FR]LC */
> +};
> +
> +static int audio_hw_params(struct device *dev,  void *data,
> +			   struct hdmi_codec_daifmt *daifmt,
> +			   struct hdmi_codec_params *params)
> +{
> +	struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
> +	int ret = 0;
> +	u8 ca;
> +
> +	dw_hdmi_set_sample_rate(dw->data.hdmi, params->sample_rate);
> +
> +	ca = default_hdmi_channel_config[params->channels - 2].ca;
> +
> +	dw_hdmi_set_channel_count(dw->data.hdmi, params->channels);
> +	dw_hdmi_set_channel_allocation(dw->data.hdmi, ca);
> +
> +	dw_hdmi_set_sample_non_pcm(dw->data.hdmi,
> +				   params->iec.status[0] & IEC958_AES0_NONAUDIO);
> +	dw_hdmi_set_sample_width(dw->data.hdmi, params->sample_width);
> +
> +	return ret;
> +}
> +
> +static void audio_shutdown(struct device *dev, void *data)
> +{
> +}
> +
> +static int audio_mute_stream(struct device *dev, void *data,
> +			      bool enable, int direction)
> +{
> +	struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
> +	int ret = 0;
> +
> +	if (!enable)
> +		dw_hdmi_audio_enable(dw->data.hdmi);
> +	else
> +		dw_hdmi_audio_disable(dw->data.hdmi);
> +
> +	return ret;
> +}
> +
> +static int audio_get_eld(struct device *dev, void *data,
> +			 u8 *buf, size_t len)
> +{
> +	struct dw_hdmi_audio_data *audio = data;
> +	u8 *eld;
> +
> +	eld = audio->get_eld(audio->hdmi);
> +	if (eld)
> +		memcpy(buf, eld, min_t(size_t, MAX_ELD_BYTES, len));
> +	else
> +		/* Pass en empty ELD if connector not available */
> +		memset(buf, 0, len);
> +
> +	return 0;
> +}
> +
> +static int audio_hook_plugged_cb(struct device *dev, void *data,
> +				 hdmi_codec_plugged_cb fn,
> +				 struct device *codec_dev)
> +{
> +	struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
> +
> +	return dw_hdmi_set_plugged_cb(dw->data.hdmi, fn, codec_dev);
> +}
> +
> +static const struct hdmi_codec_ops audio_codec_ops = {
> +	.hw_params = audio_hw_params,
> +	.audio_shutdown = audio_shutdown,
> +	.mute_stream = audio_mute_stream,
> +	.get_eld = audio_get_eld,
> +	.hook_plugged_cb = audio_hook_plugged_cb,
> +};
> +
> +static int snd_dw_hdmi_probe(struct platform_device *pdev)
> +{
> +	struct dw_hdmi_audio_data *data = pdev->dev.platform_data;
> +	struct snd_dw_hdmi *dw;
> +
> +	const struct hdmi_codec_pdata codec_data = {
> +		.i2s = 1,
> +		.spdif = 0,
> +		.ops = &audio_codec_ops,
> +		.max_i2s_channels = 8,
> +		.data = data,
> +	};
> +
> +	dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL);
> +	if (!dw)
> +		return -ENOMEM;
> +
> +	dw->data = *data;
> +
> +	platform_set_drvdata(pdev, dw);
> +
> +	dw->audio_pdev = platform_device_register_data(&pdev->dev,
> +						       HDMI_CODEC_DRV_NAME, 1,
> +						       &codec_data,
> +						       sizeof(codec_data));
> +
> +	return PTR_ERR_OR_ZERO(dw->audio_pdev);
> +}
> +
> +static int snd_dw_hdmi_remove(struct platform_device *pdev)
> +{
> +	struct snd_dw_hdmi *dw = platform_get_drvdata(pdev);
> +
> +	platform_device_unregister(dw->audio_pdev);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver snd_dw_hdmi_driver = {
> +	.probe	= snd_dw_hdmi_probe,
> +	.remove	= snd_dw_hdmi_remove,
> +	.driver	= {
> +		.name = DRIVER_NAME,
> +	},
> +};
> +
> +module_platform_driver(snd_dw_hdmi_driver);
> +
> +MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>");
> +MODULE_DESCRIPTION("Synopsys Designware HDMI GPA ALSA interface");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:" DRIVER_NAME);
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index ac98605a6811..f51e199a7493 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -191,7 +191,10 @@ struct dw_hdmi {
>   
>   	spinlock_t audio_lock;
>   	struct mutex audio_mutex;
> +	unsigned int sample_non_pcm;
> +	unsigned int sample_width;
>   	unsigned int sample_rate;
> +	unsigned int channels;
>   	unsigned int audio_cts;
>   	unsigned int audio_n;
>   	bool audio_enable;
> @@ -589,6 +592,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
>   			n = 4096;
>   		else if (pixel_clk == 74176000 || pixel_clk == 148352000)
>   			n = 11648;
> +		else if (pixel_clk == 297000000)
> +			n = 3072;
>   		else
>   			n = 4096;
>   		n *= mult;
> @@ -601,6 +606,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
>   			n = 17836;
>   		else if (pixel_clk == 148352000)
>   			n = 8918;
> +		else if (pixel_clk == 297000000)
> +			n = 4704;
>   		else
>   			n = 6272;
>   		n *= mult;
> @@ -615,6 +622,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
>   			n = 11648;
>   		else if (pixel_clk == 148352000)
>   			n = 5824;
> +		else if (pixel_clk == 297000000)
> +			n = 5120;
>   		else
>   			n = 6144;
>   		n *= mult;
> @@ -659,8 +668,8 @@ static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
>   
>   	config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
>   
> -	/* Only compute CTS when using internal AHB audio */
> -	if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
> +	/* Compute CTS when using internal AHB audio or General Parallel audio*/
> +	if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) {
>   		/*
>   		 * Compute the CTS value from the N value.  Note that CTS and N
>   		 * can be up to 20 bits in total, so we need 64-bit math.  Also
> @@ -702,6 +711,22 @@ static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
>   	mutex_unlock(&hdmi->audio_mutex);
>   }
>   
> +void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width)
> +{
> +	mutex_lock(&hdmi->audio_mutex);
> +	hdmi->sample_width = width;
> +	mutex_unlock(&hdmi->audio_mutex);
> +}
> +EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_width);
> +
> +void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm)
> +{
> +	mutex_lock(&hdmi->audio_mutex);
> +	hdmi->sample_non_pcm = non_pcm;
> +	mutex_unlock(&hdmi->audio_mutex);
> +}
> +EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_non_pcm);
> +
>   void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
>   {
>   	mutex_lock(&hdmi->audio_mutex);
> @@ -717,6 +742,7 @@ void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
>   	u8 layout;
>   
>   	mutex_lock(&hdmi->audio_mutex);
> +	hdmi->channels = cnt;
>   
>   	/*
>   	 * For >2 channel PCM audio, we need to select layout 1
> @@ -765,6 +791,89 @@ static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)
>   	return hdmi->curr_conn->eld;
>   }
>   
> +static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi)
> +{
> +	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
> +	int sample_freq = 0x2, org_sample_freq = 0xD;
> +	int ch_mask = BIT(hdmi->channels) - 1;
> +
> +	switch (hdmi->sample_rate) {
> +	case 32000:
> +		sample_freq = 0x03;
> +		org_sample_freq = 0x0C;
> +		break;
> +	case 44100:
> +		sample_freq = 0x00;
> +		org_sample_freq = 0x0F;
> +		break;
> +	case 48000:
> +		sample_freq = 0x02;
> +		org_sample_freq = 0x0D;
> +		break;
> +	case 88200:
> +		sample_freq = 0x08;
> +		org_sample_freq = 0x07;
> +		break;
> +	case 96000:
> +		sample_freq = 0x0A;
> +		org_sample_freq = 0x05;
> +		break;
> +	case 176400:
> +		sample_freq = 0x0C;
> +		org_sample_freq = 0x03;
> +		break;
> +	case 192000:
> +		sample_freq = 0x0E;
> +		org_sample_freq = 0x01;
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
> +	hdmi_enable_audio_clk(hdmi, true);
> +
> +	hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNLS0);
> +	hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2);
> +	hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS3);
> +	hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS4);
> +	hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS5);
> +	hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS6);
> +	hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7);
> +	hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8);
> +
> +	hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1);
> +	hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2);
> +	hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0);
> +
> +	hdmi_modb(hdmi,  0x3, 0x3, HDMI_FC_DATAUTO3);
> +
> +	/* hbr */
> +	if (hdmi->sample_rate == 192000 && hdmi->channels == 8 &&
> +			hdmi->sample_width == 32 && hdmi->sample_non_pcm)
> +		hdmi_modb(hdmi, 0x01, 0x01, HDMI_GP_CONF2);
> +
> +	if (pdata->enable_audio)
> +		pdata->enable_audio(hdmi,
> +					    hdmi->channels,
> +					    hdmi->sample_width,
> +					    hdmi->sample_rate,
> +					    hdmi->sample_non_pcm);
> +}
> +
> +static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi)
> +{
> +	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
> +
> +	hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
> +
> +	hdmi_modb(hdmi,  0, 0x3, HDMI_FC_DATAUTO3);
> +	if (pdata->disable_audio)
> +		pdata->disable_audio(hdmi);
> +
> +	hdmi_enable_audio_clk(hdmi, false);
> +}
> +
>   static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
>   {
>   	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
> @@ -3258,6 +3367,7 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
>   	hdmi->plat_data = plat_data;
>   	hdmi->dev = dev;
>   	hdmi->sample_rate = 48000;
> +	hdmi->channels = 2;
>   	hdmi->disabled = true;
>   	hdmi->rxsense = true;
>   	hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
> @@ -3481,6 +3591,24 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
>   		pdevinfo.size_data = sizeof(audio);
>   		pdevinfo.dma_mask = DMA_BIT_MASK(32);
>   		hdmi->audio = platform_device_register_full(&pdevinfo);
> +	} else if (iores && config3 & HDMI_CONFIG3_GPAUD) {
> +		struct dw_hdmi_audio_data audio;
> +
> +		audio.phys = iores->start;
> +		audio.base = hdmi->regs;
> +		audio.irq = irq;
> +		audio.hdmi = hdmi;
> +		audio.get_eld = hdmi_audio_get_eld;
> +
> +		hdmi->enable_audio = dw_hdmi_gp_audio_enable;
> +		hdmi->disable_audio = dw_hdmi_gp_audio_disable;
> +
> +		pdevinfo.name = "dw-hdmi-gp-audio";
> +		pdevinfo.id = PLATFORM_DEVID_NONE;
> +		pdevinfo.data = &audio;
> +		pdevinfo.size_data = sizeof(audio);
> +		pdevinfo.dma_mask = DMA_BIT_MASK(32);
> +		hdmi->audio = platform_device_register_full(&pdevinfo);
>   	}
>   
>   	if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) {
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
> index 18df3e119553..af43a0414b78 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
> @@ -158,8 +158,17 @@
>   #define HDMI_FC_SPDDEVICEINF                    0x1062
>   #define HDMI_FC_AUDSCONF                        0x1063
>   #define HDMI_FC_AUDSSTAT                        0x1064
> -#define HDMI_FC_AUDSCHNLS7                      0x106e
> -#define HDMI_FC_AUDSCHNLS8                      0x106f
> +#define HDMI_FC_AUDSV                           0x1065
> +#define HDMI_FC_AUDSU                           0x1066
> +#define HDMI_FC_AUDSCHNLS0                       0x1067
> +#define HDMI_FC_AUDSCHNLS1                       0x1068
> +#define HDMI_FC_AUDSCHNLS2                       0x1069
> +#define HDMI_FC_AUDSCHNLS3                       0x106A
> +#define HDMI_FC_AUDSCHNLS4                       0x106B
> +#define HDMI_FC_AUDSCHNLS5                       0x106C
> +#define HDMI_FC_AUDSCHNLS6                       0x106D
> +#define HDMI_FC_AUDSCHNLS7                       0x106E
> +#define HDMI_FC_AUDSCHNLS8                       0x106F
>   #define HDMI_FC_DATACH0FILL                     0x1070
>   #define HDMI_FC_DATACH1FILL                     0x1071
>   #define HDMI_FC_DATACH2FILL                     0x1072
> diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
> index 70082f80a8c8..f668e75fbabe 100644
> --- a/include/drm/bridge/dw_hdmi.h
> +++ b/include/drm/bridge/dw_hdmi.h
> @@ -143,6 +143,11 @@ struct dw_hdmi_plat_data {
>   					   const struct drm_display_info *info,
>   					   const struct drm_display_mode *mode);
>   
> +	/* Platform-specific audio enable/disable (optional) */
> +	void (*enable_audio)(struct dw_hdmi *hdmi, int channel,
> +			     int width, int rate, int non_pcm);
> +	void (*disable_audio)(struct dw_hdmi *hdmi);
> +
>   	/* Vendor PHY support */
>   	const struct dw_hdmi_phy_ops *phy_ops;
>   	const char *phy_name;
> @@ -173,6 +178,8 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
>   
>   int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
>   			   struct device *codec_dev);
> +void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm);
> +void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width);
>   void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
>   void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt);
>   void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status);

Looks fine for me

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

another review before merging would be great !

Thanks,
Neil

Re: [PATCH v3 0/4] DRM: Bridge: DW_HDMI: Add new features and bug fix

[Robert Foss]

On Fri, 15 Apr 2022 at 04:43, <Sandor.yu@nxp.com> wrote:
>
> From: Sandor Yu <Sandor.yu@nxp.com>
>
> This is new features and bug fix patch set for DW_HDMI DRM bridge driver
> that has verified by NXP i.MX8MPlus.
> Two new feature added:
> 1. Add GPA interface for DW_HDMI Audio.
> 3. New API for reset PHY Gen1.
> Two bugs fixed:
> 1. Enable overflow workaround for all IP versions later than v1.30a.
> 2. Clear GCP_Auto bit for 24-bit color depth to pass CTS.
>
> v1->v2:
> 1. Save CEC interrupt registers in struct dw_hdmi_cec
> 2. Restore CEC logical address register by cec->addresses.
> 3. Default enable overflow workaround for all versions later than v1.30a.
> 4. Add clear_gcp_auto flag to clear gcp_auto bit for all 24-bit color.
> 5. Remove i.MX8MPlus specific reference.
>
> v2->v3:
> 1. Drop the patch of Add CEC Suspend/Resume to restore registers.
> Because it is not a general feature for other SOCs, their CEC engine are
> enabled in suspend for CEC wakeup.
> 2. More detail comments for patch GCP only for Deep Color.
> 3. Address coments for patch GPA driver and move enable_audio/disable_audio
> from dw_hdmi_phy_ops to dw_hdmi_plat_data.
>
> Sandor Yu (4):
>   drm: bridge: dw_hdmi: default enable workaround to clear the overflow
>   drm: bridge: dw_hdmi: Enable GCP only for Deep Color
>   drm: bridge: dw_hdmi: add reset function for PHY GEN1
>   drm: bridge: dw_hdmi: Audio: Add General Parallel Audio (GPA) driver
>
>  drivers/gpu/drm/bridge/synopsys/Kconfig       |  10 +
>  drivers/gpu/drm/bridge/synopsys/Makefile      |   1 +
>  .../drm/bridge/synopsys/dw-hdmi-gp-audio.c    | 199 ++++++++++++++++++
>  drivers/gpu/drm/bridge/synopsys/dw-hdmi.c     | 186 ++++++++++++++--
>  drivers/gpu/drm/bridge/synopsys/dw-hdmi.h     |  16 +-
>  drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c        |   2 +-
>  include/drm/bridge/dw_hdmi.h                  |  11 +-
>  7 files changed, 400 insertions(+), 25 deletions(-)
>  create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c

Fixed two checkpatch --strict formatting warnings.

Applied to drm-misc-next.

Re: [PATCH v3 0/4] DRM: Bridge: DW_HDMI: Add new features and bug fix

[Robert Foss]

On Fri, 15 Apr 2022 at 04:43, <Sandor.yu@nxp.com> wrote:
>
> From: Sandor Yu <Sandor.yu@nxp.com>
>
> This is new features and bug fix patch set for DW_HDMI DRM bridge driver
> that has verified by NXP i.MX8MPlus.
> Two new feature added:
> 1. Add GPA interface for DW_HDMI Audio.
> 3. New API for reset PHY Gen1.
> Two bugs fixed:
> 1. Enable overflow workaround for all IP versions later than v1.30a.
> 2. Clear GCP_Auto bit for 24-bit color depth to pass CTS.
>
> v1->v2:
> 1. Save CEC interrupt registers in struct dw_hdmi_cec
> 2. Restore CEC logical address register by cec->addresses.
> 3. Default enable overflow workaround for all versions later than v1.30a.
> 4. Add clear_gcp_auto flag to clear gcp_auto bit for all 24-bit color.
> 5. Remove i.MX8MPlus specific reference.
>
> v2->v3:
> 1. Drop the patch of Add CEC Suspend/Resume to restore registers.
> Because it is not a general feature for other SOCs, their CEC engine are
> enabled in suspend for CEC wakeup.
> 2. More detail comments for patch GCP only for Deep Color.
> 3. Address coments for patch GPA driver and move enable_audio/disable_audio
> from dw_hdmi_phy_ops to dw_hdmi_plat_data.
>
> Sandor Yu (4):
>   drm: bridge: dw_hdmi: default enable workaround to clear the overflow
>   drm: bridge: dw_hdmi: Enable GCP only for Deep Color
>   drm: bridge: dw_hdmi: add reset function for PHY GEN1
>   drm: bridge: dw_hdmi: Audio: Add General Parallel Audio (GPA) driver
>
>  drivers/gpu/drm/bridge/synopsys/Kconfig       |  10 +
>  drivers/gpu/drm/bridge/synopsys/Makefile      |   1 +
>  .../drm/bridge/synopsys/dw-hdmi-gp-audio.c    | 199 ++++++++++++++++++
>  drivers/gpu/drm/bridge/synopsys/dw-hdmi.c     | 186 ++++++++++++++--
>  drivers/gpu/drm/bridge/synopsys/dw-hdmi.h     |  16 +-
>  drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c        |   2 +-
>  include/drm/bridge/dw_hdmi.h                  |  11 +-
>  7 files changed, 400 insertions(+), 25 deletions(-)
>  create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-hdmi-gp-audio.c

Fixed two checkpatch --strict formatting warnings.

Applied to drm-misc-next.