[PATCH 0/2] Floating-point OE/UE exception bug

[PATCH 0/2] Floating-point OE/UE exception bug

[Lucas Mateus Castro(alqotel)]

From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>

Changes in v2:
    - Completely reworked the solution:
        * Created re_bias in FloatFmt, it is 3/4 of the total exponent
          range of a FP type
        * Added rebias bools that dictates if the result should have
          its exponent add/subtract the re_bias value if an
          overflow/underflow occurs.
        * ppc_store_fpscr sets/unsets rebias if OE/UE is set/unset

The PowerISA defines that if an overflow exception happen with FPSCR.OE
set, the exponent of the intermediate result is subtracted 1536 in
double precision operations and is added 1536 in an underflow exception,
currently this behavior is not QEMU's behavior, this patch series fixes
that.

Currently there's no test in this patch series as there's no way to
disable MSR.FE0 and MSR.FE1 in linux user, so any overflow/underflow
exception with OE/UE set causes a trapping exception.

Lucas Mateus Castro (alqotel) (2):
  fpu: Add rebias bool, value and operation
  target/ppc: Bugfix FP when OE/UE are set

 fpu/softfloat-parts.c.inc     | 21 +++++++++++++++++++--
 fpu/softfloat.c               |  2 ++
 include/fpu/softfloat-types.h |  4 ++++
 target/ppc/cpu.c              |  2 ++
 target/ppc/fpu_helper.c       |  2 --
 5 files changed, 27 insertions(+), 4 deletions(-)

-- 
2.31.1

[PATCH 1/2] fpu: Add rebias bool, value and operation

[Lucas Mateus Castro(alqotel)]

From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>

Added the possibility of recalculating a result if it overflows or
underflows, if the result overflow and the rebias bool is true then the
intermediate result should have 3/4 of the total range subtracted from
the exponent. The same for underflow but it should be added to the
exponent of the intermediate number instead.

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
---
 fpu/softfloat-parts.c.inc     | 21 +++++++++++++++++++--
 fpu/softfloat.c               |  2 ++
 include/fpu/softfloat-types.h |  4 ++++
 3 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index bbeadaa189..a9f268fcab 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -214,18 +214,35 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,
                 p->frac_lo &= ~round_mask;
             }
         } else if (unlikely(exp >= exp_max)) {
-            flags |= float_flag_overflow | float_flag_inexact;
-            if (overflow_norm) {
+            flags |= float_flag_overflow;
+            if (s->rebias_overflow) {
+                exp -= fmt->exp_re_bias;
+            } else if (overflow_norm) {
+                flags |= float_flag_inexact;
                 exp = exp_max - 1;
                 frac_allones(p);
                 p->frac_lo &= ~round_mask;
             } else {
+                flags |= float_flag_inexact;
                 p->cls = float_class_inf;
                 exp = exp_max;
                 frac_clear(p);
             }
         }
         frac_shr(p, frac_shift);
+    } else if (unlikely(s->rebias_underflow)) {
+        flags |= float_flag_underflow;
+        exp += fmt->exp_re_bias;
+        if (p->frac_lo & round_mask) {
+            flags |= float_flag_inexact;
+            if (frac_addi(p, p, inc)) {
+                frac_shr(p, 1);
+                p->frac_hi |= DECOMPOSED_IMPLICIT_BIT;
+                exp++;
+            }
+            p->frac_lo &= ~round_mask;
+        }
+        frac_shr(p, frac_shift);
     } else if (s->flush_to_zero) {
         flags |= float_flag_output_denormal;
         p->cls = float_class_zero;
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 4a871ef2a1..c7454c3eb1 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -521,6 +521,7 @@ typedef struct {
 typedef struct {
     int exp_size;
     int exp_bias;
+    int exp_re_bias;
     int exp_max;
     int frac_size;
     int frac_shift;
@@ -532,6 +533,7 @@ typedef struct {
 #define FLOAT_PARAMS_(E)                                \
     .exp_size       = E,                                \
     .exp_bias       = ((1 << E) - 1) >> 1,              \
+    .exp_re_bias    = (1 << (E - 1)) + (1 << (E - 2)),  \
     .exp_max        = (1 << E) - 1
 
 #define FLOAT_PARAMS(E, F)                              \
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 7a6ea881d8..9735543ac4 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -195,6 +195,10 @@ typedef struct float_status {
     bool snan_bit_is_one;
     bool use_first_nan;
     bool no_signaling_nans;
+    /* should overflowed results subtract re_bias to its exponent? */
+    bool rebias_overflow;
+    /* should underflowed results add re_bias to its exponent? */
+    bool rebias_underflow;
 } float_status;
 
 #endif /* SOFTFLOAT_TYPES_H */
-- 
2.31.1

[PATCH 2/2] target/ppc: Bugfix FP when OE/UE are set

[Lucas Mateus Castro(alqotel)]

From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>

When an overflow exception occurs and OE is set the intermediate result
should be adjusted (by subtracting from the exponent) to avoid rounding
to inf. The same applies to an underflow exceptionion and UE (but adding
to the exponent). To do this set the fp_status.rebias_overflow when OE
is set and fp_status.rebias_underflow when UE is set as the FPU will
recalculate in case of a overflow/underflow if the according rebias* is
set.

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
---
 target/ppc/cpu.c        | 2 ++
 target/ppc/fpu_helper.c | 2 --
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index 401b6f9e63..0ebac04bc4 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -120,6 +120,8 @@ void ppc_store_fpscr(CPUPPCState *env, target_ulong val)
         val |= FP_FEX;
     }
     env->fpscr = val;
+    env->fp_status.rebias_overflow  = (FP_OE & env->fpscr) ? true : false;
+    env->fp_status.rebias_underflow = (FP_UE & env->fpscr) ? true : false;
     if (tcg_enabled()) {
         fpscr_set_rounding_mode(env);
     }
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 134804628b..c17575de5d 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -344,7 +344,6 @@ static inline int float_overflow_excp(CPUPPCState *env)
 
     bool overflow_enabled = !!(env->fpscr & FP_OE);
     if (overflow_enabled) {
-        /* XXX: should adjust the result */
         /* Update the floating-point enabled exception summary */
         env->fpscr |= FP_FEX;
         /* We must update the target FPR before raising the exception */
@@ -363,7 +362,6 @@ static inline void float_underflow_excp(CPUPPCState *env)
     /* Update the floating-point exception summary */
     env->fpscr |= FP_FX;
     if (env->fpscr & FP_UE) {
-        /* XXX: should adjust the result */
         /* Update the floating-point enabled exception summary */
         env->fpscr |= FP_FEX;
         /* We must update the target FPR before raising the exception */
-- 
2.31.1

Re: [PATCH 0/2] Floating-point OE/UE exception bug

[Alex Bennée]

"Lucas Mateus Castro(alqotel)" <lucas.araujo@eldorado.org.br> writes:

> From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>
>
> Changes in v2:
>     - Completely reworked the solution:
>         * Created re_bias in FloatFmt, it is 3/4 of the total exponent
>           range of a FP type

I thought this might have an effect on the efficiency of the FloatFmt
extraction/packing but I couldn't see any real difference in fpbench. I
doubt the compiler can dead code it away if not used by a front-end.

Anyway have a:

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

for the series.

>         * Added rebias bools that dictates if the result should have
>           its exponent add/subtract the re_bias value if an
>           overflow/underflow occurs.
>         * ppc_store_fpscr sets/unsets rebias if OE/UE is set/unset
>
> The PowerISA defines that if an overflow exception happen with FPSCR.OE
> set, the exponent of the intermediate result is subtracted 1536 in
> double precision operations and is added 1536 in an underflow exception,
> currently this behavior is not QEMU's behavior, this patch series fixes
> that.
>
> Currently there's no test in this patch series as there's no way to
> disable MSR.FE0 and MSR.FE1 in linux user, so any overflow/underflow
> exception with OE/UE set causes a trapping exception.

Could you do it with a system mode test? Probably overkill for this
though. I suspect tweaking testfloat would be tricky.

>
> Lucas Mateus Castro (alqotel) (2):
>   fpu: Add rebias bool, value and operation
>   target/ppc: Bugfix FP when OE/UE are set
>
>  fpu/softfloat-parts.c.inc     | 21 +++++++++++++++++++--
>  fpu/softfloat.c               |  2 ++
>  include/fpu/softfloat-types.h |  4 ++++
>  target/ppc/cpu.c              |  2 ++
>  target/ppc/fpu_helper.c       |  2 --
>  5 files changed, 27 insertions(+), 4 deletions(-)


-- 
Alex Bennée

Re: [PATCH 0/2] Floating-point OE/UE exception bug

[Lucas Mateus Martins Araujo e Castro]

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On 05/08/2022 13:20, Alex Bennée wrote:
> "Lucas Mateus Castro(alqotel)"<lucas.araujo@eldorado.org.br>  writes:
>
>> From: "Lucas Mateus Castro (alqotel)"<lucas.araujo@eldorado.org.br>
>>
>> Changes in v2:
>>      - Completely reworked the solution:
>>          * Created re_bias in FloatFmt, it is 3/4 of the total exponent
>>            range of a FP type
> I thought this might have an effect on the efficiency of the FloatFmt
> extraction/packing but I couldn't see any real difference in fpbench. I
> doubt the compiler can dead code it away if not used by a front-end.
>
> Anyway have a:
>
> Reviewed-by: Alex Bennée<alex.bennee@linaro.org>
>
> for the series.
>
>>          * Added rebias bools that dictates if the result should have
>>            its exponent add/subtract the re_bias value if an
>>            overflow/underflow occurs.
>>          * ppc_store_fpscr sets/unsets rebias if OE/UE is set/unset
>>
>> The PowerISA defines that if an overflow exception happen with FPSCR.OE
>> set, the exponent of the intermediate result is subtracted 1536 in
>> double precision operations and is added 1536 in an underflow exception,
>> currently this behavior is not QEMU's behavior, this patch series fixes
>> that.
>>
>> Currently there's no test in this patch series as there's no way to
>> disable MSR.FE0 and MSR.FE1 in linux user, so any overflow/underflow
>> exception with OE/UE set causes a trapping exception.
> Could you do it with a system mode test? Probably overkill for this
> though. I suspect tweaking testfloat would be tricky.

Matheus currently has a patch to enable prctl, it still needs to change 
some places that have hardcoded values for linux-user 
(https://github.com/PPC64/qemu/tree/alqotel-ferst-prctl-patch has 
Matheus' patch and a patch to remove the ifdef from fp_exceptions_enabled).

With that change it should be possible to create a normal test for this 
(I sent a basic one along with v1, 
Message-Id=<20220803124324.23593-1-lucas.araujo@eldorado.org.br>) built 
on top of that branch.

Thanks,

>> Lucas Mateus Castro (alqotel) (2):
>>    fpu: Add rebias bool, value and operation
>>    target/ppc: Bugfix FP when OE/UE are set
>>
>>   fpu/softfloat-parts.c.inc     | 21 +++++++++++++++++++--
>>   fpu/softfloat.c               |  2 ++
>>   include/fpu/softfloat-types.h |  4 ++++
>>   target/ppc/cpu.c              |  2 ++
>>   target/ppc/fpu_helper.c       |  2 --
>>   5 files changed, 27 insertions(+), 4 deletions(-)
>
> --
> Alex Bennée
-- 
Lucas Mateus M. Araujo e Castro
Instituto de Pesquisas ELDORADO 
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>

[-- Attachment #2: Type: text/html, Size: 4361 bytes --]

Re: [PATCH 0/2] Floating-point OE/UE exception bug

[Lucas Mateus Martins Araujo e Castro]

[-- Attachment #1: Type: text/plain, Size: 1937 bytes --]

It's missing from the title but this is a v2.

v1 id:
Message-Id: <20220803122217.20847-1-lucas.araujo@eldorado.org.br>

On 05/08/2022 11:15, Lucas Mateus Castro(alqotel) wrote:
> From: "Lucas Mateus Castro (alqotel)"<lucas.araujo@eldorado.org.br>
>
> Changes in v2:
>      - Completely reworked the solution:
>          * Created re_bias in FloatFmt, it is 3/4 of the total exponent
>            range of a FP type
>          * Added rebias bools that dictates if the result should have
>            its exponent add/subtract the re_bias value if an
>            overflow/underflow occurs.
>          * ppc_store_fpscr sets/unsets rebias if OE/UE is set/unset
>
> The PowerISA defines that if an overflow exception happen with FPSCR.OE
> set, the exponent of the intermediate result is subtracted 1536 in
> double precision operations and is added 1536 in an underflow exception,
> currently this behavior is not QEMU's behavior, this patch series fixes
> that.
>
> Currently there's no test in this patch series as there's no way to
> disable MSR.FE0 and MSR.FE1 in linux user, so any overflow/underflow
> exception with OE/UE set causes a trapping exception.
>
> Lucas Mateus Castro (alqotel) (2):
>    fpu: Add rebias bool, value and operation
>    target/ppc: Bugfix FP when OE/UE are set
>
>   fpu/softfloat-parts.c.inc     | 21 +++++++++++++++++++--
>   fpu/softfloat.c               |  2 ++
>   include/fpu/softfloat-types.h |  4 ++++
>   target/ppc/cpu.c              |  2 ++
>   target/ppc/fpu_helper.c       |  2 --
>   5 files changed, 27 insertions(+), 4 deletions(-)
>
-- 
Lucas Mateus M. Araujo e Castro
Instituto de Pesquisas ELDORADO 
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>

[-- Attachment #2: Type: text/html, Size: 2598 bytes --]

Re: [PATCH 0/2] Floating-point OE/UE exception bug

[Richard Henderson]

On 8/5/22 07:15, Lucas Mateus Castro(alqotel) wrote:
> Currently there's no test in this patch series as there's no way to
> disable MSR.FE0 and MSR.FE1 in linux user, so any overflow/underflow
> exception with OE/UE set causes a trapping exception.

You could check the value in the fp register in the signal handler.  The exception is 
supposed to occur after the register writeback.


r~

Re: [PATCH 1/2] fpu: Add rebias bool, value and operation

[Richard Henderson]

On 8/5/22 07:15, Lucas Mateus Castro(alqotel) wrote:
> From: "Lucas Mateus Castro (alqotel)"<lucas.araujo@eldorado.org.br>
> 
> Added the possibility of recalculating a result if it overflows or
> underflows, if the result overflow and the rebias bool is true then the
> intermediate result should have 3/4 of the total range subtracted from
> the exponent. The same for underflow but it should be added to the
> exponent of the intermediate number instead.
> 
> Signed-off-by: Lucas Mateus Castro (alqotel)<lucas.araujo@eldorado.org.br>
> ---
>   fpu/softfloat-parts.c.inc     | 21 +++++++++++++++++++--
>   fpu/softfloat.c               |  2 ++
>   include/fpu/softfloat-types.h |  4 ++++
>   3 files changed, 25 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH 2/2] target/ppc: Bugfix FP when OE/UE are set

[Richard Henderson]

On 8/5/22 07:15, Lucas Mateus Castro(alqotel) wrote:
> From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>
> 
> When an overflow exception occurs and OE is set the intermediate result
> should be adjusted (by subtracting from the exponent) to avoid rounding
> to inf. The same applies to an underflow exceptionion and UE (but adding
> to the exponent). To do this set the fp_status.rebias_overflow when OE
> is set and fp_status.rebias_underflow when UE is set as the FPU will
> recalculate in case of a overflow/underflow if the according rebias* is
> set.
> 
> Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
> ---
>   target/ppc/cpu.c        | 2 ++
>   target/ppc/fpu_helper.c | 2 --
>   2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
> index 401b6f9e63..0ebac04bc4 100644
> --- a/target/ppc/cpu.c
> +++ b/target/ppc/cpu.c
> @@ -120,6 +120,8 @@ void ppc_store_fpscr(CPUPPCState *env, target_ulong val)
>           val |= FP_FEX;
>       }
>       env->fpscr = val;
> +    env->fp_status.rebias_overflow  = (FP_OE & env->fpscr) ? true : false;
> +    env->fp_status.rebias_underflow = (FP_UE & env->fpscr) ? true : false;

No point in the ?: operator.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

>       if (tcg_enabled()) {
>           fpscr_set_rounding_mode(env);
>       }
> diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
> index 134804628b..c17575de5d 100644
> --- a/target/ppc/fpu_helper.c
> +++ b/target/ppc/fpu_helper.c
> @@ -344,7 +344,6 @@ static inline int float_overflow_excp(CPUPPCState *env)
>   
>       bool overflow_enabled = !!(env->fpscr & FP_OE);
>       if (overflow_enabled) {
> -        /* XXX: should adjust the result */
>           /* Update the floating-point enabled exception summary */
>           env->fpscr |= FP_FEX;
>           /* We must update the target FPR before raising the exception */
> @@ -363,7 +362,6 @@ static inline void float_underflow_excp(CPUPPCState *env)
>       /* Update the floating-point exception summary */
>       env->fpscr |= FP_FX;
>       if (env->fpscr & FP_UE) {
> -        /* XXX: should adjust the result */
>           /* Update the floating-point enabled exception summary */
>           env->fpscr |= FP_FEX;
>           /* We must update the target FPR before raising the exception */

Re: [PATCH 2/2] target/ppc: Bugfix FP when OE/UE are set

[Daniel Henrique Barboza]

On 8/5/22 14:17, Richard Henderson wrote:
> On 8/5/22 07:15, Lucas Mateus Castro(alqotel) wrote:
>> From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>
>>
>> When an overflow exception occurs and OE is set the intermediate result
>> should be adjusted (by subtracting from the exponent) to avoid rounding
>> to inf. The same applies to an underflow exceptionion and UE (but adding
>> to the exponent). To do this set the fp_status.rebias_overflow when OE
>> is set and fp_status.rebias_underflow when UE is set as the FPU will
>> recalculate in case of a overflow/underflow if the according rebias* is
>> set.
>>
>> Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
>> ---
>>   target/ppc/cpu.c        | 2 ++
>>   target/ppc/fpu_helper.c | 2 --
>>   2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
>> index 401b6f9e63..0ebac04bc4 100644
>> --- a/target/ppc/cpu.c
>> +++ b/target/ppc/cpu.c
>> @@ -120,6 +120,8 @@ void ppc_store_fpscr(CPUPPCState *env, target_ulong val)
>>           val |= FP_FEX;
>>       }
>>       env->fpscr = val;
>> +    env->fp_status.rebias_overflow  = (FP_OE & env->fpscr) ? true : false;
>> +    env->fp_status.rebias_underflow = (FP_UE & env->fpscr) ? true : false;
> 
> No point in the ?: operator.
> 
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> 

Amended in the tree. No need to re-send.


diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index 0ebac04bc4..947a4bfe1f 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -120,8 +120,8 @@ void ppc_store_fpscr(CPUPPCState *env, target_ulong val)
          val |= FP_FEX;
      }
      env->fpscr = val;
-    env->fp_status.rebias_overflow  = (FP_OE & env->fpscr) ? true : false;
-    env->fp_status.rebias_underflow = (FP_UE & env->fpscr) ? true : false;
+    env->fp_status.rebias_overflow  = FP_OE & env->fpscr;
+    env->fp_status.rebias_underflow = FP_UE & env->fpscr;
      if (tcg_enabled()) {
          fpscr_set_rounding_mode(env);
      }


Thanks,


Daniel

> 
> r~
> 
>>       if (tcg_enabled()) {
>>           fpscr_set_rounding_mode(env);
>>       }
>> diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
>> index 134804628b..c17575de5d 100644
>> --- a/target/ppc/fpu_helper.c
>> +++ b/target/ppc/fpu_helper.c
>> @@ -344,7 +344,6 @@ static inline int float_overflow_excp(CPUPPCState *env)
>>       bool overflow_enabled = !!(env->fpscr & FP_OE);
>>       if (overflow_enabled) {
>> -        /* XXX: should adjust the result */
>>           /* Update the floating-point enabled exception summary */
>>           env->fpscr |= FP_FEX;
>>           /* We must update the target FPR before raising the exception */
>> @@ -363,7 +362,6 @@ static inline void float_underflow_excp(CPUPPCState *env)
>>       /* Update the floating-point exception summary */
>>       env->fpscr |= FP_FX;
>>       if (env->fpscr & FP_UE) {
>> -        /* XXX: should adjust the result */
>>           /* Update the floating-point enabled exception summary */
>>           env->fpscr |= FP_FEX;
>>           /* We must update the target FPR before raising the exception */
> 

Re: [PATCH 0/2] Floating-point OE/UE exception bug

[Daniel Henrique Barboza]

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,


Daniel

On 8/5/22 11:15, Lucas Mateus Castro(alqotel) wrote:
> From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>
> 
> Changes in v2:
>      - Completely reworked the solution:
>          * Created re_bias in FloatFmt, it is 3/4 of the total exponent
>            range of a FP type
>          * Added rebias bools that dictates if the result should have
>            its exponent add/subtract the re_bias value if an
>            overflow/underflow occurs.
>          * ppc_store_fpscr sets/unsets rebias if OE/UE is set/unset
> 
> The PowerISA defines that if an overflow exception happen with FPSCR.OE
> set, the exponent of the intermediate result is subtracted 1536 in
> double precision operations and is added 1536 in an underflow exception,
> currently this behavior is not QEMU's behavior, this patch series fixes
> that.
> 
> Currently there's no test in this patch series as there's no way to
> disable MSR.FE0 and MSR.FE1 in linux user, so any overflow/underflow
> exception with OE/UE set causes a trapping exception.
> 
> Lucas Mateus Castro (alqotel) (2):
>    fpu: Add rebias bool, value and operation
>    target/ppc: Bugfix FP when OE/UE are set
> 
>   fpu/softfloat-parts.c.inc     | 21 +++++++++++++++++++--
>   fpu/softfloat.c               |  2 ++
>   include/fpu/softfloat-types.h |  4 ++++
>   target/ppc/cpu.c              |  2 ++
>   target/ppc/fpu_helper.c       |  2 --
>   5 files changed, 27 insertions(+), 4 deletions(-)
>