Parent clock for MFIS module

Parent clock for MFIS module

[Julien Massot]

Hi,
I did a linux driver which makes use of the MFIS module, and so my first 
step would be to send a patch to add the MFIS module clock, which will 
basically do that:

--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -137,6 +137,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] 
__initdata = {
  	DEF_MOD("msiof2",		 209,	R8A7795_CLK_MSO),
  	DEF_MOD("msiof1",		 210,	R8A7795_CLK_MSO),
  	DEF_MOD("msiof0",		 211,	R8A7795_CLK_MSO),
+	DEF_MOD("mfis",		         213,	R8A7795_CLK_MSO),
  	DEF_MOD("sys-dmac2",		 217,	R8A7795_CLK_S3D1),

But the third parameter of DEF_MOD is definitely wrong and despite 
having read the hardware manual I can't figure out where this 
information is. Does someone have any hint on where to find the parent 
clock for the mfis mod clock ?

Thanks,
Julien

Re: Parent clock for MFIS module

[Geert Uytterhoeven]

Hi Julien,

On Thu, Dec 10, 2020 at 2:17 PM Julien Massot <julien.massot@iot.bzh> wrote:
> I did a linux driver which makes use of the MFIS module, and so my first
> step would be to send a patch to add the MFIS module clock, which will
> basically do that:
>
> --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> @@ -137,6 +137,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[]
> __initdata = {
>         DEF_MOD("msiof2",                209,   R8A7795_CLK_MSO),
>         DEF_MOD("msiof1",                210,   R8A7795_CLK_MSO),
>         DEF_MOD("msiof0",                211,   R8A7795_CLK_MSO),
> +       DEF_MOD("mfis",                  213,   R8A7795_CLK_MSO),
>         DEF_MOD("sys-dmac2",             217,   R8A7795_CLK_S3D1),
>
> But the third parameter of DEF_MOD is definitely wrong and despite
> having read the hardware manual I can't figure out where this
> information is. Does someone have any hint on where to find the parent
> clock for the mfis mod clock ?

Unfortunately this information isn't always properly documented in the
Hardware User's Manual.  Based on the MFIS Block Diagram, I would
say it must be one of the APB bus clocks.

The BSP uses R8A77970_CLK_S2D2 for R-Car V3M, which sounds
reasonable. Reading the PCIe chapter, it could also be S3D1 or S3D3.
However, in this case, the driver wouldn't care about the clock rate,
so the actual parent clock used doesn't matter much.
Hence S2D2 sounds acceptable to me.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: Parent clock for MFIS module

[Julien Massot]

Hi Geert,

> Unfortunately this information isn't always properly documented in the
> Hardware User's Manual.  Based on the MFIS Block Diagram, I would
> say it must be one of the APB bus clocks.
> 
> The BSP uses R8A77970_CLK_S2D2 for R-Car V3M, which sounds
> reasonable. Reading the PCIe chapter, it could also be S3D1 or S3D3.
> However, in this case, the driver wouldn't care about the clock rate,
> so the actual parent clock used doesn't matter much.
> Hence S2D2 sounds acceptable to me.

Many thanks, let's put S2D2 then, patches are in flight !

Regards,

-- 
Julien Massot [IoT.bzh]