From: "Łukasz Majewski" <lukma@denx.de> To: Nicolin Chen <nicoleotsuka@gmail.com> Cc: Timur Tabi <timur@tabi.org>, Xiubo Li <Xiubo.Lee@gmail.com>, Fabio Estevam <fabio.estevam@nxp.com>, Liam Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>, Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>, alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] sound: soc: fsl: Do not set DAI sysclk when it is equal to system freq Date: Tue, 5 Sep 2017 10:19:05 +0200 [thread overview] Message-ID: <deb40031-9db0-d667-7314-352cf548c295@denx.de> (raw) In-Reply-To: <20170905075247.GA6112@Asurada> On 09/05/2017 09:52 AM, Nicolin Chen wrote: > On Tue, Sep 05, 2017 at 09:37:43AM +0200, Łukasz Majewski wrote: > >>>> The last call is changing the bit clock (BCLK) frequency to SSI's IP >>>> block clock (ipg = 66 MHz) [1]. >>> >>> I think a bigger question here is why the routine sets BCLK to 66MHz. >> >> Yes, exactly. >> >> In my case the bclk is set to ipg clock, which is the SSI IP block clock >> (ipg). > > Can you elaborate why you set ipg clock as bclk? I don't remember SSI could > derive bitclock from ipg clock. Just to be clear: What clock shall be set with: struct snd_soc_dai_ops { int (*set_sysclk)(struct snd_soc_dai *dai, int clk_id, unsigned int freq, int dir); } callback? The SSI IP block or BCLK ? > >>>> This is wrong, since IMX SSI block requires the I2S BCLK to be less >>>> than 1/5 of [1]. >>>> >>>> As a result the driver initialization passes without any errors, but the >>>> speaker-test test case breaks. >>>> >>>> This commit checks if the fsl_ssi_set_dai_sysclk() frequency passed is >>>> not equal to [1]. >>> >>> I don't feel it's quite comprehensive...what if it's being set to 67MHz. >> >> I think that this clock is not changing for the SoC. It should be 66 MHz >> fixed. > > What I mean is that we cannot just look at this SoC. Today is 66MHz for this > SoC. Tomorrow could be 133MHz for another one. We should put a check that none > of these shall pass -- the 1/5 limit. > Ok. Good point. -- Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
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From: "Łukasz Majewski" <lukma@denx.de> To: Nicolin Chen <nicoleotsuka@gmail.com> Cc: alsa-devel@alsa-project.org, Timur Tabi <timur@tabi.org>, Xiubo Li <Xiubo.Lee@gmail.com>, linux-kernel@vger.kernel.org, Takashi Iwai <tiwai@suse.com>, Liam Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>, Fabio Estevam <fabio.estevam@nxp.com>, linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] sound: soc: fsl: Do not set DAI sysclk when it is equal to system freq Date: Tue, 5 Sep 2017 10:19:05 +0200 [thread overview] Message-ID: <deb40031-9db0-d667-7314-352cf548c295@denx.de> (raw) In-Reply-To: <20170905075247.GA6112@Asurada> On 09/05/2017 09:52 AM, Nicolin Chen wrote: > On Tue, Sep 05, 2017 at 09:37:43AM +0200, Łukasz Majewski wrote: > >>>> The last call is changing the bit clock (BCLK) frequency to SSI's IP >>>> block clock (ipg = 66 MHz) [1]. >>> >>> I think a bigger question here is why the routine sets BCLK to 66MHz. >> >> Yes, exactly. >> >> In my case the bclk is set to ipg clock, which is the SSI IP block clock >> (ipg). > > Can you elaborate why you set ipg clock as bclk? I don't remember SSI could > derive bitclock from ipg clock. Just to be clear: What clock shall be set with: struct snd_soc_dai_ops { int (*set_sysclk)(struct snd_soc_dai *dai, int clk_id, unsigned int freq, int dir); } callback? The SSI IP block or BCLK ? > >>>> This is wrong, since IMX SSI block requires the I2S BCLK to be less >>>> than 1/5 of [1]. >>>> >>>> As a result the driver initialization passes without any errors, but the >>>> speaker-test test case breaks. >>>> >>>> This commit checks if the fsl_ssi_set_dai_sysclk() frequency passed is >>>> not equal to [1]. >>> >>> I don't feel it's quite comprehensive...what if it's being set to 67MHz. >> >> I think that this clock is not changing for the SoC. It should be 66 MHz >> fixed. > > What I mean is that we cannot just look at this SoC. Today is 66MHz for this > SoC. Tomorrow could be 133MHz for another one. We should put a check that none > of these shall pass -- the 1/5 limit. > Ok. Good point. -- Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
next prev parent reply other threads:[~2017-09-05 8:19 UTC|newest] Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-09-03 11:05 [PATCH] sound: soc: fsl: Do not set DAI sysclk when it is equal to system freq Lukasz Majewski 2017-09-03 12:44 ` Fabio Estevam 2017-09-03 12:44 ` Fabio Estevam 2017-09-03 14:40 ` Łukasz Majewski 2017-09-03 15:29 ` Fabio Estevam 2017-09-03 15:29 ` Fabio Estevam 2017-09-03 15:29 ` Fabio Estevam 2017-09-05 5:20 ` Nicolin Chen 2017-09-05 8:35 ` Łukasz Majewski 2017-09-05 18:11 ` Nicolin Chen 2017-09-05 21:13 ` Łukasz Majewski 2017-09-05 21:13 ` Łukasz Majewski 2017-09-05 22:52 ` Nicolin Chen 2017-09-05 22:52 ` Nicolin Chen 2017-09-06 9:22 ` Łukasz Majewski 2017-09-06 9:22 ` Łukasz Majewski 2017-09-06 17:33 ` Nicolin Chen 2017-09-06 17:33 ` Nicolin Chen 2017-09-06 18:35 ` Łukasz Majewski 2017-09-06 19:47 ` Nicolin Chen 2017-09-06 19:47 ` Nicolin Chen 2017-09-06 21:18 ` Łukasz Majewski 2017-09-06 21:18 ` Łukasz Majewski 2017-09-07 23:10 ` Łukasz Majewski 2017-09-07 23:10 ` Łukasz Majewski 2017-09-08 0:39 ` Nicolin Chen 2017-09-08 0:39 ` Nicolin Chen 2017-09-05 23:20 ` Fabio Estevam 2017-09-05 23:20 ` Fabio Estevam 2017-09-05 23:20 ` Fabio Estevam 2017-09-06 8:44 ` Łukasz Majewski 2017-09-05 20:14 ` Fabio Estevam 2017-09-05 20:14 ` Fabio Estevam 2017-09-05 21:14 ` Łukasz Majewski 2017-09-05 5:06 ` Nicolin Chen 2017-09-05 7:37 ` Łukasz Majewski 2017-09-05 7:52 ` Nicolin Chen 2017-09-05 8:19 ` Łukasz Majewski [this message] 2017-09-05 8:19 ` Łukasz Majewski 2017-09-05 15:15 ` Mark Brown 2017-09-05 15:15 ` Mark Brown 2017-09-05 17:45 ` Nicolin Chen 2017-09-07 13:44 ` Mark Brown 2017-09-07 13:44 ` Mark Brown 2017-09-07 23:03 ` Nicolin Chen
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