* [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes
@ 2020-12-08 20:36 Philippe Mathieu-Daudé
2020-12-08 20:36 ` [PATCH 01/13] !fixup "target/mips/translate: Add declarations for generic code" Philippe Mathieu-Daudé
` (13 more replies)
0 siblings, 14 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Complete the MSA conversion with the LSA/DLSA opcodes,
which are shared with the Release 6.
Keep going converting the removed opcodes.
We now have 2 decoders on 32-bit, and 4 on 64-bit.
Extensions are decoded first, then ISA.
I might introduce a macro to have a generic decode()
function to hide the 32/64 check, to keep the main
decode_opc() loop easy to review.
Series available here:
https://gitlab.com/philmd/qemu/-/tree/mips_decodetree_lsa_r6
Regards,
Phil.
Philippe Mathieu-Daudé (13):
!fixup "target/mips/translate: Add declarations for generic code"
target/mips: Extract LSA/DLSA translation generators
target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
target/mips: Introduce decodetree helpers for Release6 LSA/DLSA
opcodes
target/mips: Remove now unreachable LSA/DLSA opcodes code
target/mips: Convert Rel6 Special2 opcode to decodetree
target/mips: Convert Rel6 COP1X opcode to decodetree
target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
target/mips: Convert Rel6 LL/SC opcodes to decodetree
target/mips/translate.h | 21 +++++-
target/mips/isa-mips32r6.decode | 36 ++++++++++
target/mips/isa-mips64r6.decode | 26 +++++++
target/mips/mod-msa32.decode | 4 ++
target/mips/mod-msa64.decode | 17 +++++
target/mips/isa-mips_rel6_translate.c | 40 +++++++++++
target/mips/mod-msa_translate.c | 15 ++++
target/mips/translate.c | 98 +++++++--------------------
target/mips/translate_addr_const.c | 54 +++++++++++++++
target/mips/meson.build | 9 +++
10 files changed, 245 insertions(+), 75 deletions(-)
create mode 100644 target/mips/isa-mips32r6.decode
create mode 100644 target/mips/isa-mips64r6.decode
create mode 100644 target/mips/mod-msa64.decode
create mode 100644 target/mips/isa-mips_rel6_translate.c
create mode 100644 target/mips/translate_addr_const.c
--
2.26.2
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 01/13] !fixup "target/mips/translate: Add declarations for generic code"
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
@ 2020-12-08 20:36 ` Philippe Mathieu-Daudé
2020-12-09 0:09 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 02/13] target/mips: Extract LSA/DLSA translation generators Philippe Mathieu-Daudé
` (12 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Missed in previous "Convert MSA to decodetree" series.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 8 +++++++-
target/mips/translate.c | 4 ++--
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index cba28f49753..da88387418c 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -55,11 +55,15 @@ typedef struct DisasContext {
void generate_exception_end(DisasContext *ctx, int excp);
void gen_reserved_instruction(DisasContext *ctx);
void check_insn(DisasContext *ctx, uint64_t flags);
-void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
+#ifdef TARGET_MIPS64
+void check_mips_64(DisasContext *ctx);
+#endif
+void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
void gen_load_gpr(TCGv t, int reg);
void gen_store_gpr(TCGv t, int reg);
+extern TCGv cpu_gpr[32], cpu_PC;
extern TCGv bcond;
#define LOG_DISAS(...) \
@@ -82,6 +86,8 @@ extern TCGv bcond;
/* MSA */
void msa_translate_init(void);
+
+/* decodetree generated */
bool decode_msa32(DisasContext *ctx, uint32_t insn);
#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 41c0b59a473..3c7307233c9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2187,7 +2187,7 @@ enum {
};
/* global register indices */
-static TCGv cpu_gpr[32], cpu_PC;
+TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
static TCGv cpu_dspctrl, btarget;
TCGv bcond;
@@ -2728,7 +2728,7 @@ static inline void check_ps(DisasContext *ctx)
* This code generates a "reserved instruction" exception if 64-bit
* instructions are not enabled.
*/
-static inline void check_mips_64(DisasContext *ctx)
+void check_mips_64(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
generate_exception_end(ctx, EXCP_RI);
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 02/13] target/mips: Extract LSA/DLSA translation generators
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
2020-12-08 20:36 ` [PATCH 01/13] !fixup "target/mips/translate: Add declarations for generic code" Philippe Mathieu-Daudé
@ 2020-12-08 20:36 ` Philippe Mathieu-Daudé
2020-12-09 0:16 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 03/13] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Philippe Mathieu-Daudé
` (11 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Extract gen_lsa() from translate.c and explode it as
gen_LSA() and gen_DLSA().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 8 +++++
target/mips/translate.c | 35 +++----------------
target/mips/translate_addr_const.c | 54 ++++++++++++++++++++++++++++++
target/mips/meson.build | 1 +
4 files changed, 67 insertions(+), 31 deletions(-)
create mode 100644 target/mips/translate_addr_const.c
diff --git a/target/mips/translate.h b/target/mips/translate.h
index da88387418c..4eb218e2c9f 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -63,6 +63,14 @@ void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
void gen_load_gpr(TCGv t, int reg);
void gen_store_gpr(TCGv t, int reg);
+/*
+ * Address Computation and Large Constant Instructions
+ */
+bool gen_LSA(DisasContext *ctx, int rd, int rt, int rs, int sa);
+#if defined(TARGET_MIPS64)
+bool gen_DLSA(DisasContext *ctx, int rd, int rt, int rs, int sa);
+#endif
+
extern TCGv cpu_gpr[32], cpu_PC;
extern TCGv bcond;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3c7307233c9..752a06afa21 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6624,31 +6624,6 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
tcg_temp_free(t0);
}
-static void gen_lsa(DisasContext *ctx, int opc, int rd, int rs, int rt,
- int imm2)
-{
- TCGv t0;
- TCGv t1;
- if (rd == 0) {
- /* Treat as NOP. */
- return;
- }
- t0 = tcg_temp_new();
- t1 = tcg_temp_new();
- gen_load_gpr(t0, rs);
- gen_load_gpr(t1, rt);
- tcg_gen_shli_tl(t0, t0, imm2 + 1);
- tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
- if (opc == OPC_LSA) {
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- }
-
- tcg_temp_free(t1);
- tcg_temp_free(t0);
-
- return;
-}
-
static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
int rt, int bits)
{
@@ -16504,8 +16479,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
return;
case LSA:
check_insn(ctx, ISA_MIPS32R6);
- gen_lsa(ctx, OPC_LSA, rd, rs, rt,
- extract32(ctx->opcode, 9, 2));
+ gen_LSA(ctx, rd, rs, rt, extract32(ctx->opcode, 9, 2));
break;
case ALIGN:
check_insn(ctx, ISA_MIPS32R6);
@@ -21468,8 +21442,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
* amount, meaning that the supported shift values are in
* the range 0 to 3 (instead of 1 to 4 in MIPSR6).
*/
- gen_lsa(ctx, OPC_LSA, rd, rs, rt,
- extract32(ctx->opcode, 9, 2) - 1);
+ gen_LSA(ctx, rd, rs, rt, extract32(ctx->opcode, 9, 2) - 1);
break;
case NM_EXTW:
gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
@@ -24355,7 +24328,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) {
case OPC_LSA:
- gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
+ gen_LSA(ctx, rd, rs, rt, extract32(ctx->opcode, 6, 2));
break;
case OPC_MULT:
case OPC_MULTU:
@@ -24409,7 +24382,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
case OPC_DLSA:
check_mips_64(ctx);
- gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
+ gen_DLSA(ctx, rd, rs, rt, extract32(ctx->opcode, 6, 2));
break;
case R6_OPC_DCLO:
case R6_OPC_DCLZ:
diff --git a/target/mips/translate_addr_const.c b/target/mips/translate_addr_const.c
new file mode 100644
index 00000000000..e6da5c66544
--- /dev/null
+++ b/target/mips/translate_addr_const.c
@@ -0,0 +1,54 @@
+/*
+ * Address Computation and Large Constant Instructions
+ */
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "translate.h"
+
+bool gen_LSA(DisasContext *ctx, int rd, int rt, int rs, int sa)
+{
+ TCGv t0;
+ TCGv t1;
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ tcg_gen_shli_tl(t0, t0, sa + 1);
+ tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+
+ tcg_temp_free(t1);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+#if defined(TARGET_MIPS64)
+bool gen_DLSA(DisasContext *ctx, int rd, int rt, int rs, int sa)
+{
+ TCGv t0;
+ TCGv t1;
+
+ check_mips_64(ctx);
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ tcg_gen_shli_tl(t0, t0, sa + 1);
+ tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
+ tcg_temp_free(t1);
+ tcg_temp_free(t0);
+
+ return true;
+}
+#endif /* TARGET_MIPS64 */
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 7d0414bbe23..9e42c341a90 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -15,6 +15,7 @@
'mod-msa_helper.c',
'translate.c',
+ 'translate_addr_const.c',
'mod-msa_translate.c',
))
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 03/13] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
2020-12-08 20:36 ` [PATCH 01/13] !fixup "target/mips/translate: Add declarations for generic code" Philippe Mathieu-Daudé
2020-12-08 20:36 ` [PATCH 02/13] target/mips: Extract LSA/DLSA translation generators Philippe Mathieu-Daudé
@ 2020-12-08 20:36 ` Philippe Mathieu-Daudé
2020-12-09 0:22 ` Richard Henderson
2020-12-09 14:14 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 04/13] target/mips: Introduce decodetree helpers for Release6 " Philippe Mathieu-Daudé
` (10 subsequent siblings)
13 siblings, 2 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Add the LSA opcode to the MSA32 decodetree config, add DLSA
to a new config for the MSA64 ASE, and call decode_msa64()
in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 3 +++
target/mips/mod-msa32.decode | 4 ++++
target/mips/mod-msa64.decode | 17 +++++++++++++++++
target/mips/mod-msa_translate.c | 15 +++++++++++++++
target/mips/translate.c | 5 +++++
target/mips/meson.build | 5 +++++
6 files changed, 49 insertions(+)
create mode 100644 target/mips/mod-msa64.decode
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 4eb218e2c9f..00601232b97 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -97,5 +97,8 @@ void msa_translate_init(void);
/* decodetree generated */
bool decode_msa32(DisasContext *ctx, uint32_t insn);
+#if defined(TARGET_MIPS64)
+bool decode_msa64(DisasContext *ctx, uint32_t insn);
+#endif
#endif
diff --git a/target/mips/mod-msa32.decode b/target/mips/mod-msa32.decode
index d69675132b8..0b2f0863251 100644
--- a/target/mips/mod-msa32.decode
+++ b/target/mips/mod-msa32.decode
@@ -10,11 +10,15 @@
# (Document Number: MD00866-2B-MSA32-AFP-01.12)
#
+&lsa rd rt rs sa
&msa_bz df wt s16
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
+LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
+
BZ_V 010001 01011 ..... ................ @bz
BNZ_V 010001 01111 ..... ................ @bz
diff --git a/target/mips/mod-msa64.decode b/target/mips/mod-msa64.decode
new file mode 100644
index 00000000000..8dcbbcd8538
--- /dev/null
+++ b/target/mips/mod-msa64.decode
@@ -0,0 +1,17 @@
+# MIPS SIMD Architecture Module instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume IV-j
+# The MIPS64 SIMD Architecture Module, Revision 1.12
+# (Document Number: MD00868-1D-MSA64-AFP-01.12)
+#
+
+&lsa rd rt rs sa !extern
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
+
+DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translate.c
index 7e7fc0644ff..7af0c2fd657 100644
--- a/target/mips/mod-msa_translate.c
+++ b/target/mips/mod-msa_translate.c
@@ -20,6 +20,9 @@
/* Include the auto-generated decoder. */
#include "decode-mod-msa32.c.inc"
+#if defined(TARGET_MIPS64)
+#include "decode-mod-msa64.c.inc"
+#endif /* TARGET_MIPS64 */
#define OPC_MSA (0x1E << 26)
@@ -2268,3 +2271,15 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
return true;
}
+
+static bool trans_LSA(DisasContext *ctx, arg_LSA *a)
+{
+ return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
+#if defined(TARGET_MIPS64)
+static bool trans_DLSA(DisasContext *ctx, arg_LSA *a)
+{
+ return gen_DLSA(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+#endif /* TARGET_MIPS64 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 752a06afa21..b3c45d6211a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28311,6 +28311,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* Transition to the auto-generated decoder. */
/* ISA Extensions */
+#if defined(TARGET_MIPS64)
+ if (ase_msa_available(env) && decode_msa64(ctx, ctx->opcode)) {
+ return;
+ }
+#endif /* TARGET_MIPS64 */
if (ase_msa_available(env) && decode_msa32(ctx, ctx->opcode)) {
return;
}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 9e42c341a90..124b5f7d49d 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,6 +1,9 @@
gen = [
decodetree.process('mod-msa32.decode', extra_args: [ '--decode=decode_msa32' ]),
]
+gen64 = [
+ decodetree.process('mod-msa64.decode', extra_args: [ '--decode=decode_msa64' ]),
+]
mips_ss = ss.source_set()
mips_ss.add(gen)
@@ -18,6 +21,8 @@
'translate_addr_const.c',
'mod-msa_translate.c',
))
+mips_ss.add(when: 'TARGET_MIPS64', if_true: gen64)
+
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
mips_softmmu_ss = ss.source_set()
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 04/13] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2020-12-08 20:36 ` [PATCH 03/13] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Philippe Mathieu-Daudé
@ 2020-12-08 20:36 ` Philippe Mathieu-Daudé
2020-12-09 14:21 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 05/13] target/mips: Remove now unreachable LSA/DLSA opcodes code Philippe Mathieu-Daudé
` (9 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
LSA and LDSA opcodes are also available with MIPS release 6.
Introduce the decodetree config files and call the decode()
helpers in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 2 ++
target/mips/isa-mips32r6.decode | 17 ++++++++++++++
target/mips/isa-mips64r6.decode | 17 ++++++++++++++
target/mips/isa-mips_rel6_translate.c | 33 +++++++++++++++++++++++++++
target/mips/translate.c | 10 ++++++++
target/mips/meson.build | 3 +++
6 files changed, 82 insertions(+)
create mode 100644 target/mips/isa-mips32r6.decode
create mode 100644 target/mips/isa-mips64r6.decode
create mode 100644 target/mips/isa-mips_rel6_translate.c
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 00601232b97..dcd8de602c1 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -96,8 +96,10 @@ extern TCGv bcond;
void msa_translate_init(void);
/* decodetree generated */
+bool decode_mips32r6(DisasContext *ctx, uint32_t insn);
bool decode_msa32(DisasContext *ctx, uint32_t insn);
#if defined(TARGET_MIPS64)
+bool decode_mips64r6(DisasContext *ctx, uint32_t insn);
bool decode_msa64(DisasContext *ctx, uint32_t insn);
#endif
diff --git a/target/mips/isa-mips32r6.decode b/target/mips/isa-mips32r6.decode
new file mode 100644
index 00000000000..027585ee042
--- /dev/null
+++ b/target/mips/isa-mips32r6.decode
@@ -0,0 +1,17 @@
+# MIPS32 Release 6 instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume II-A
+# The MIPS32 Instruction Set Reference Manual, Revision 6.06
+# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06)
+#
+
+&lsa rd rt rs sa
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
+
+LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
diff --git a/target/mips/isa-mips64r6.decode b/target/mips/isa-mips64r6.decode
new file mode 100644
index 00000000000..e812224341e
--- /dev/null
+++ b/target/mips/isa-mips64r6.decode
@@ -0,0 +1,17 @@
+# MIPS64 Release 6 instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume II-A
+# The MIPS64 Instruction Set Reference Manual, Revision 6.06
+# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06)
+#
+
+&lsa rd rt rs sa !extern
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
+
+DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
diff --git a/target/mips/isa-mips_rel6_translate.c b/target/mips/isa-mips_rel6_translate.c
new file mode 100644
index 00000000000..c77f3ed57e0
--- /dev/null
+++ b/target/mips/isa-mips_rel6_translate.c
@@ -0,0 +1,33 @@
+/*
+ * MIPS emulation for QEMU - # Release 6 translation routines
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "exec/helper-gen.h"
+#include "translate.h"
+
+/* Include the auto-generated decoder. */
+#include "decode-isa-mips32r6.c.inc"
+#if defined(TARGET_MIPS64)
+#include "decode-isa-mips64r6.c.inc"
+#endif /* TARGET_MIPS64 */
+
+static bool trans_LSA(DisasContext *ctx, arg_LSA *a)
+{
+ return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
+#if defined(TARGET_MIPS64)
+static bool trans_DLSA(DisasContext *ctx, arg_LSA *a)
+{
+ return gen_DLSA(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+#endif /* TARGET_MIPS64 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b3c45d6211a..9b333f97822 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28320,6 +28320,16 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
return;
}
+ /* ISA */
+#if defined(TARGET_MIPS64)
+ if ((ctx->insn_flags & ISA_MIPS64R6) && decode_mips64r6(ctx, ctx->opcode)) {
+ return;
+ }
+#endif /* TARGET_MIPS64 */
+ if ((ctx->insn_flags & ISA_MIPS32R6) && decode_mips32r6(ctx, ctx->opcode)) {
+ return;
+ }
+
op = MASK_OP_MAJOR(ctx->opcode);
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 124b5f7d49d..a459d0917ee 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,7 +1,9 @@
gen = [
+ decodetree.process('isa-mips32r6.decode', extra_args: [ '--decode=decode_mips32r6' ]),
decodetree.process('mod-msa32.decode', extra_args: [ '--decode=decode_msa32' ]),
]
gen64 = [
+ decodetree.process('isa-mips64r6.decode', extra_args: [ '--decode=decode_mips64r6' ]),
decodetree.process('mod-msa64.decode', extra_args: [ '--decode=decode_msa64' ]),
]
@@ -13,6 +15,7 @@
'fpu_helper.c',
'gdbstub.c',
'helper.c',
+ 'isa-mips_rel6_translate.c',
'lmmi_helper.c',
'op_helper.c',
'mod-msa_helper.c',
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 05/13] target/mips: Remove now unreachable LSA/DLSA opcodes code
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2020-12-08 20:36 ` [PATCH 04/13] target/mips: Introduce decodetree helpers for Release6 " Philippe Mathieu-Daudé
@ 2020-12-08 20:36 ` Philippe Mathieu-Daudé
2020-12-09 14:22 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 06/13] target/mips: Convert Rel6 Special2 opcode to decodetree Philippe Mathieu-Daudé
` (8 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Since we switched to decodetree-generated processing,
we can remove this now unreachable code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 29 +++++------------------------
1 file changed, 5 insertions(+), 24 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9b333f97822..8f0a0a3830c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -286,9 +286,6 @@ enum {
R6_OPC_DCLZ = 0x12 | OPC_SPECIAL,
R6_OPC_DCLO = 0x13 | OPC_SPECIAL,
R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
-
- OPC_LSA = 0x05 | OPC_SPECIAL,
- OPC_DLSA = 0x15 | OPC_SPECIAL,
};
/* Multiplication variants of the vr54xx. */
@@ -24327,9 +24324,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) {
- case OPC_LSA:
- gen_LSA(ctx, rd, rs, rt, extract32(ctx->opcode, 6, 2));
- break;
case OPC_MULT:
case OPC_MULTU:
case OPC_DIV:
@@ -24380,10 +24374,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DLSA:
- check_mips_64(ctx);
- gen_DLSA(ctx, rd, rs, rt, extract32(ctx->opcode, 6, 2));
- break;
case R6_OPC_DCLO:
case R6_OPC_DCLZ:
if (rt == 0 && sa == 1) {
@@ -24645,18 +24635,14 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
check_insn(ctx, ISA_MIPS2);
gen_trap(ctx, op1, rs, rt, -1);
break;
- case OPC_LSA: /* OPC_PMON */
- if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) {
- decode_opc_special_r6(env, ctx);
- } else {
- /* Pmon entry point, also R4010 selsl */
+ case OPC_PMON:
+ /* Pmon entry point, also R4010 selsl */
#ifdef MIPS_STRICT_STANDARD
- MIPS_INVAL("PMON / selsl");
- generate_exception_end(ctx, EXCP_RI);
+ MIPS_INVAL("PMON / selsl");
+ generate_exception_end(ctx, EXCP_RI);
#else
- gen_helper_0e0i(pmon, sa);
+ gen_helper_0e0i(pmon, sa);
#endif
- }
break;
case OPC_SYSCALL:
generate_exception_end(ctx, EXCP_SYSCALL);
@@ -24747,11 +24733,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
- case OPC_DLSA:
- if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) {
- decode_opc_special_r6(env, ctx);
- }
- break;
#endif
default:
if (ctx->insn_flags & ISA_MIPS32R6) {
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 06/13] target/mips: Convert Rel6 Special2 opcode to decodetree
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2020-12-08 20:36 ` [PATCH 05/13] target/mips: Remove now unreachable LSA/DLSA opcodes code Philippe Mathieu-Daudé
@ 2020-12-08 20:36 ` Philippe Mathieu-Daudé
2020-12-09 14:23 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 07/13] target/mips: Convert Rel6 COP1X " Philippe Mathieu-Daudé
` (7 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Special2 opcode have been removed from the Release 6.
Add a single decodetree entry for all the opcode class,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/isa-mips32r6.decode | 2 ++
target/mips/isa-mips_rel6_translate.c | 7 +++++++
target/mips/translate.c | 2 --
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/mips/isa-mips32r6.decode b/target/mips/isa-mips32r6.decode
index 027585ee042..259bac612ab 100644
--- a/target/mips/isa-mips32r6.decode
+++ b/target/mips/isa-mips32r6.decode
@@ -15,3 +15,5 @@
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
+
+REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
diff --git a/target/mips/isa-mips_rel6_translate.c b/target/mips/isa-mips_rel6_translate.c
index c77f3ed57e0..9ac906b1f33 100644
--- a/target/mips/isa-mips_rel6_translate.c
+++ b/target/mips/isa-mips_rel6_translate.c
@@ -20,6 +20,13 @@
#include "decode-isa-mips64r6.c.inc"
#endif /* TARGET_MIPS64 */
+bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
+{
+ gen_reserved_instruction(ctx);
+
+ return true;
+}
+
static bool trans_LSA(DisasContext *ctx, arg_LSA *a)
{
return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8f0a0a3830c..788b5112a80 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -27145,8 +27145,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
int rs, rt, rd;
uint32_t op1;
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
-
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 07/13] target/mips: Convert Rel6 COP1X opcode to decodetree
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2020-12-08 20:36 ` [PATCH 06/13] target/mips: Convert Rel6 Special2 opcode to decodetree Philippe Mathieu-Daudé
@ 2020-12-08 20:36 ` Philippe Mathieu-Daudé
2020-12-09 14:23 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 08/13] target/mips: Convert Rel6 CACHE/PREF opcodes " Philippe Mathieu-Daudé
` (6 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
COP1x opcode has been removed from the Release 6.
Add a single decodetree entry for it, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/isa-mips32r6.decode | 2 ++
target/mips/translate.c | 1 -
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/isa-mips32r6.decode b/target/mips/isa-mips32r6.decode
index 259bac612ab..7b12a1bff25 100644
--- a/target/mips/isa-mips32r6.decode
+++ b/target/mips/isa-mips32r6.decode
@@ -16,4 +16,6 @@
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
+REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3)
+
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 788b5112a80..81ca1d45063 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28874,7 +28874,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_CP3:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
op1 = MASK_CP3(ctx->opcode);
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 08/13] target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2020-12-08 20:36 ` [PATCH 07/13] target/mips: Convert Rel6 COP1X " Philippe Mathieu-Daudé
@ 2020-12-08 20:36 ` Philippe Mathieu-Daudé
2020-12-09 14:24 ` Richard Henderson
2020-12-08 20:37 ` [PATCH 09/13] target/mips: Convert Rel6 LWL/LWR/SWL/SWR " Philippe Mathieu-Daudé
` (5 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
CACHE/PREF opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/isa-mips32r6.decode | 3 +++
target/mips/translate.c | 2 --
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/isa-mips32r6.decode b/target/mips/isa-mips32r6.decode
index 7b12a1bff25..e3b3934539a 100644
--- a/target/mips/isa-mips32r6.decode
+++ b/target/mips/isa-mips32r6.decode
@@ -19,3 +19,6 @@ LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3)
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
+
+REMOVED 101111 ----- ----- ---------------- # CACHE
+REMOVED 110011 ----- ----- ---------------- # PREF
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 81ca1d45063..ba1b2360c50 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28667,7 +28667,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
break;
case OPC_CACHE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS3 | ISA_MIPS32);
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
@@ -28676,7 +28675,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* Treat as NOP. */
break;
case OPC_PREF:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
if (ctx->insn_flags & INSN_R5900) {
/* Treat as NOP. */
} else {
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 09/13] target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2020-12-08 20:36 ` [PATCH 08/13] target/mips: Convert Rel6 CACHE/PREF opcodes " Philippe Mathieu-Daudé
@ 2020-12-08 20:37 ` Philippe Mathieu-Daudé
2020-12-09 14:24 ` Richard Henderson
2020-12-08 20:37 ` [PATCH 10/13] target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE " Philippe Mathieu-Daudé
` (4 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:37 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
LWL/LWR/SWL/SWR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/isa-mips32r6.decode | 5 +++++
target/mips/translate.c | 5 +----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/mips/isa-mips32r6.decode b/target/mips/isa-mips32r6.decode
index e3b3934539a..89a0085fafd 100644
--- a/target/mips/isa-mips32r6.decode
+++ b/target/mips/isa-mips32r6.decode
@@ -20,5 +20,10 @@ REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3)
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
+REMOVED 100010 ----- ----- ---------------- # LWL
+REMOVED 100110 ----- ----- ---------------- # LWR
+REMOVED 101010 ----- ----- ---------------- # SWL
+REMOVED 101110 ----- ----- ---------------- # SWR
+
REMOVED 101111 ----- ----- ---------------- # CACHE
REMOVED 110011 ----- ----- ---------------- # PREF
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ba1b2360c50..3d627d049bd 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28636,11 +28636,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* Fallthrough */
case OPC_LWL:
case OPC_LWR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
- /* Fallthrough */
case OPC_LB:
case OPC_LH:
case OPC_LW:
@@ -28651,8 +28650,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SWL:
case OPC_SWR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
- /* fall through */
case OPC_SB:
case OPC_SH:
case OPC_SW:
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 10/13] target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2020-12-08 20:37 ` [PATCH 09/13] target/mips: Convert Rel6 LWL/LWR/SWL/SWR " Philippe Mathieu-Daudé
@ 2020-12-08 20:37 ` Philippe Mathieu-Daudé
2020-12-09 14:35 ` Richard Henderson
2020-12-08 20:37 ` [PATCH 11/13] target/mips: Convert Rel6 LDL/LDR/SDL/SDR " Philippe Mathieu-Daudé
` (3 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:37 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from
the Release 6. Add a single decodetree entry for the opcodes,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/isa-mips32r6.decode | 5 +++++
target/mips/translate.c | 4 ----
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/isa-mips32r6.decode b/target/mips/isa-mips32r6.decode
index 89a0085fafd..3ec50704cf2 100644
--- a/target/mips/isa-mips32r6.decode
+++ b/target/mips/isa-mips32r6.decode
@@ -20,6 +20,11 @@ REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3)
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
+REMOVED 011111 ----- ----- ---------- 011001 # LWLE
+REMOVED 011111 ----- ----- ---------- 011010 # LWRE
+REMOVED 011111 ----- ----- ---------- 100001 # SWLE
+REMOVED 011111 ----- ----- ---------- 100010 # SWRE
+
REMOVED 100010 ----- ----- ---------------- # LWL
REMOVED 100110 ----- ----- ---------------- # LWR
REMOVED 101010 ----- ----- ---------------- # SWL
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3d627d049bd..962522b0e02 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28130,8 +28130,6 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
switch (op1) {
case OPC_LWLE:
case OPC_LWRE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
- /* fall through */
case OPC_LBUE:
case OPC_LHUE:
case OPC_LBE:
@@ -28143,8 +28141,6 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
return;
case OPC_SWLE:
case OPC_SWRE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
- /* fall through */
case OPC_SBE:
case OPC_SHE:
case OPC_SWE:
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 11/13] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2020-12-08 20:37 ` [PATCH 10/13] target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE " Philippe Mathieu-Daudé
@ 2020-12-08 20:37 ` Philippe Mathieu-Daudé
2020-12-09 14:39 ` Richard Henderson
2020-12-08 20:37 ` [PATCH 12/13] target/mips: Convert Rel6 LLD/SCD " Philippe Mathieu-Daudé
` (2 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:37 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
LDL/LDR/SDL/SDR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/isa-mips64r6.decode | 6 ++++++
target/mips/translate.c | 5 +----
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/target/mips/isa-mips64r6.decode b/target/mips/isa-mips64r6.decode
index e812224341e..8c3fc5dae9c 100644
--- a/target/mips/isa-mips64r6.decode
+++ b/target/mips/isa-mips64r6.decode
@@ -10,8 +10,14 @@
# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06)
#
+&REMOVED !extern
&lsa rd rt rs sa !extern
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
+
+REMOVED 011010 ----- ----- ---------------- # LDL
+REMOVED 011011 ----- ----- ---------------- # LDR
+REMOVED 101100 ----- ----- ---------------- # SDL
+REMOVED 101101 ----- ----- ---------------- # SDR
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 962522b0e02..aeba8efeb17 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28918,11 +28918,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
case OPC_LDL:
case OPC_LDR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
- /* fall through */
case OPC_LWU:
case OPC_LD:
check_insn(ctx, ISA_MIPS3);
@@ -28931,8 +28930,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SDL:
case OPC_SDR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
- /* fall through */
case OPC_SD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 12/13] target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2020-12-08 20:37 ` [PATCH 11/13] target/mips: Convert Rel6 LDL/LDR/SDL/SDR " Philippe Mathieu-Daudé
@ 2020-12-08 20:37 ` Philippe Mathieu-Daudé
2020-12-09 14:40 ` Richard Henderson
2020-12-08 20:37 ` [PATCH 13/13] target/mips: Convert Rel6 LL/SC " Philippe Mathieu-Daudé
2021-01-07 18:48 ` [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
13 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:37 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
LLD/SCD opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/isa-mips64r6.decode | 3 +++
target/mips/translate.c | 2 --
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/isa-mips64r6.decode b/target/mips/isa-mips64r6.decode
index 8c3fc5dae9c..609b8958d25 100644
--- a/target/mips/isa-mips64r6.decode
+++ b/target/mips/isa-mips64r6.decode
@@ -21,3 +21,6 @@ REMOVED 011010 ----- ----- ---------------- # LDL
REMOVED 011011 ----- ----- ---------------- # LDR
REMOVED 101100 ----- ----- ---------------- # SDL
REMOVED 101101 ----- ----- ---------------- # SDR
+
+REMOVED 110100 ----- ----- ---------------- # LLD
+REMOVED 111100 ----- ----- ---------------- # SCD
diff --git a/target/mips/translate.c b/target/mips/translate.c
index aeba8efeb17..009301c9ceb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28918,7 +28918,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
case OPC_LDL:
case OPC_LDR:
@@ -28936,7 +28935,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st(ctx, op, rt, rs, imm);
break;
case OPC_SCD:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_insn(ctx, ISA_MIPS3);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 13/13] target/mips: Convert Rel6 LL/SC opcodes to decodetree
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2020-12-08 20:37 ` [PATCH 12/13] target/mips: Convert Rel6 LLD/SCD " Philippe Mathieu-Daudé
@ 2020-12-08 20:37 ` Philippe Mathieu-Daudé
2020-12-09 14:40 ` Richard Henderson
2021-01-07 18:48 ` [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
13 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 20:37 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
LL/SC opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/isa-mips32r6.decode | 2 ++
target/mips/translate.c | 2 --
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/isa-mips32r6.decode b/target/mips/isa-mips32r6.decode
index 3ec50704cf2..489c20aa4e9 100644
--- a/target/mips/isa-mips32r6.decode
+++ b/target/mips/isa-mips32r6.decode
@@ -31,4 +31,6 @@ REMOVED 101010 ----- ----- ---------------- # SWL
REMOVED 101110 ----- ----- ---------------- # SWR
REMOVED 101111 ----- ----- ---------------- # CACHE
+REMOVED 110000 ----- ----- ---------------- # LL
REMOVED 110011 ----- ----- ---------------- # PREF
+REMOVED 111000 ----- ----- ---------------- # SC
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 009301c9ceb..90a6dfcd2b3 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28632,7 +28632,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* Fallthrough */
case OPC_LWL:
case OPC_LWR:
@@ -28653,7 +28652,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SC:
check_insn(ctx, ISA_MIPS2);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH 01/13] !fixup "target/mips/translate: Add declarations for generic code"
2020-12-08 20:36 ` [PATCH 01/13] !fixup "target/mips/translate: Add declarations for generic code" Philippe Mathieu-Daudé
@ 2020-12-09 0:09 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 0:09 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
> Missed in previous "Convert MSA to decodetree" series.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.h | 8 +++++++-
> target/mips/translate.c | 4 ++--
> 2 files changed, 9 insertions(+), 3 deletions(-)
Ack.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 02/13] target/mips: Extract LSA/DLSA translation generators
2020-12-08 20:36 ` [PATCH 02/13] target/mips: Extract LSA/DLSA translation generators Philippe Mathieu-Daudé
@ 2020-12-09 0:16 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 0:16 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
> +++ b/target/mips/translate_addr_const.c
> @@ -0,0 +1,54 @@
> +/*
> + * Address Computation and Large Constant Instructions
> + */
Missing license. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 03/13] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
2020-12-08 20:36 ` [PATCH 03/13] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Philippe Mathieu-Daudé
@ 2020-12-09 0:22 ` Richard Henderson
2020-12-09 14:14 ` Richard Henderson
1 sibling, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 0:22 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
> /* ISA Extensions */
> +#if defined(TARGET_MIPS64)
> + if (ase_msa_available(env) && decode_msa64(ctx, ctx->opcode)) {
> + return;
> + }
> +#endif /* TARGET_MIPS64 */
> if (ase_msa_available(env) && decode_msa32(ctx, ctx->opcode)) {
> return;
> }
Can we reduce the number of ifdefs involved? Perhaps to zero?
if (ase_msa) {
if (TARGET_LONG_BITS == 64 && decode_msa64()) {
return;
}
if (decode_msa32()) {
return;
}
}
I realize this means extra decodetree invocations for mips32, but... does that
really matter?
I suppose some of the tcg expansions could not work for TCGv = TCGv_i32, which
wouldn't help the cause...
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 03/13] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
2020-12-08 20:36 ` [PATCH 03/13] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Philippe Mathieu-Daudé
2020-12-09 0:22 ` Richard Henderson
@ 2020-12-09 14:14 ` Richard Henderson
1 sibling, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 14:14 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
> Add the LSA opcode to the MSA32 decodetree config, add DLSA
> to a new config for the MSA64 ASE, and call decode_msa64()
> in the main decode_opc() loop.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.h | 3 +++
> target/mips/mod-msa32.decode | 4 ++++
> target/mips/mod-msa64.decode | 17 +++++++++++++++++
> target/mips/mod-msa_translate.c | 15 +++++++++++++++
> target/mips/translate.c | 5 +++++
> target/mips/meson.build | 5 +++++
> 6 files changed, 49 insertions(+)
> create mode 100644 target/mips/mod-msa64.decode
Assuming nothing better can be done about the ifdefs,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 04/13] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes
2020-12-08 20:36 ` [PATCH 04/13] target/mips: Introduce decodetree helpers for Release6 " Philippe Mathieu-Daudé
@ 2020-12-09 14:21 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 14:21 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
> +++ b/target/mips/isa-mips_rel6_translate.c
> @@ -0,0 +1,33 @@
> +/*
> + * MIPS emulation for QEMU - # Release 6 translation routines
> + *
> + * Copyright (c) 2004-2005 Jocelyn Mayer
> + * Copyright (c) 2006 Marius Groeger (FPU operations)
> + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
> + * Copyright (c) 2020 Philippe Mathieu-Daudé
> + *
> + * This code is licensed under the GNU GPLv2 and later.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "tcg/tcg-op.h"
> +#include "exec/helper-gen.h"
> +#include "translate.h"
> +
> +/* Include the auto-generated decoder. */
> +#include "decode-isa-mips32r6.c.inc"
> +#if defined(TARGET_MIPS64)
> +#include "decode-isa-mips64r6.c.inc"
> +#endif /* TARGET_MIPS64 */
> +
> +static bool trans_LSA(DisasContext *ctx, arg_LSA *a)
> +{
> + return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa);
> +}
> +
> +#if defined(TARGET_MIPS64)
> +static bool trans_DLSA(DisasContext *ctx, arg_LSA *a)
> +{
> + return gen_DLSA(ctx, a->rd, a->rt, a->rs, a->sa);
> +}
You should be able to share these trans_* functions, and then with or after the
next patch, fold the gen_* functions into their single caller, the trans_*
functions.
Note that decodetree --translate=trans will drop the static, without otherwise
adjusting the function naming.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 05/13] target/mips: Remove now unreachable LSA/DLSA opcodes code
2020-12-08 20:36 ` [PATCH 05/13] target/mips: Remove now unreachable LSA/DLSA opcodes code Philippe Mathieu-Daudé
@ 2020-12-09 14:22 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 14:22 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
> Since we switched to decodetree-generated processing,
> we can remove this now unreachable code.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.c | 29 +++++------------------------
> 1 file changed, 5 insertions(+), 24 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 06/13] target/mips: Convert Rel6 Special2 opcode to decodetree
2020-12-08 20:36 ` [PATCH 06/13] target/mips: Convert Rel6 Special2 opcode to decodetree Philippe Mathieu-Daudé
@ 2020-12-09 14:23 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 14:23 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
> Special2 opcode have been removed from the Release 6.
> Add a single decodetree entry for all the opcode class,
> triggering Reserved Instruction if ever used.
>
> Remove unreachable check_insn_opc_removed() call.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/isa-mips32r6.decode | 2 ++
> target/mips/isa-mips_rel6_translate.c | 7 +++++++
> target/mips/translate.c | 2 --
> 3 files changed, 9 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 07/13] target/mips: Convert Rel6 COP1X opcode to decodetree
2020-12-08 20:36 ` [PATCH 07/13] target/mips: Convert Rel6 COP1X " Philippe Mathieu-Daudé
@ 2020-12-09 14:23 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 14:23 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
> COP1x opcode has been removed from the Release 6.
> Add a single decodetree entry for it, triggering
> Reserved Instruction if ever used.
>
> Remove unreachable check_insn_opc_removed() call.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/isa-mips32r6.decode | 2 ++
> target/mips/translate.c | 1 -
> 2 files changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 08/13] target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
2020-12-08 20:36 ` [PATCH 08/13] target/mips: Convert Rel6 CACHE/PREF opcodes " Philippe Mathieu-Daudé
@ 2020-12-09 14:24 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 14:24 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
> CACHE/PREF opcodes have been removed from the Release 6.
> Add a single decodetree entry for the opcodes, triggering
> Reserved Instruction if ever used.
>
> Remove unreachable check_insn_opc_removed() calls.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/isa-mips32r6.decode | 3 +++
> target/mips/translate.c | 2 --
> 2 files changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 09/13] target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
2020-12-08 20:37 ` [PATCH 09/13] target/mips: Convert Rel6 LWL/LWR/SWL/SWR " Philippe Mathieu-Daudé
@ 2020-12-09 14:24 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 14:24 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:37 PM, Philippe Mathieu-Daudé wrote:
> LWL/LWR/SWL/SWR opcodes have been removed from the Release 6.
> Add a single decodetree entry for the opcodes, triggering
> Reserved Instruction if ever used.
>
> Remove unreachable check_insn_opc_removed() calls.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/isa-mips32r6.decode | 5 +++++
> target/mips/translate.c | 5 +----
> 2 files changed, 6 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 10/13] target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
2020-12-08 20:37 ` [PATCH 10/13] target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE " Philippe Mathieu-Daudé
@ 2020-12-09 14:35 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 14:35 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:37 PM, Philippe Mathieu-Daudé wrote:
> LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from
> the Release 6. Add a single decodetree entry for the opcodes,
> triggering Reserved Instruction if ever used.
>
> Remove unreachable check_insn_opc_removed() calls.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/isa-mips32r6.decode | 5 +++++
> target/mips/translate.c | 4 ----
> 2 files changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 11/13] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
2020-12-08 20:37 ` [PATCH 11/13] target/mips: Convert Rel6 LDL/LDR/SDL/SDR " Philippe Mathieu-Daudé
@ 2020-12-09 14:39 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 14:39 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:37 PM, Philippe Mathieu-Daudé wrote:
> LDL/LDR/SDL/SDR opcodes have been removed from the Release 6.
> Add a single decodetree entry for the opcodes, triggering
> Reserved Instruction if ever used.
>
> Remove unreachable check_insn_opc_removed() calls.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/isa-mips64r6.decode | 6 ++++++
> target/mips/translate.c | 5 +----
> 2 files changed, 7 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 12/13] target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
2020-12-08 20:37 ` [PATCH 12/13] target/mips: Convert Rel6 LLD/SCD " Philippe Mathieu-Daudé
@ 2020-12-09 14:40 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 14:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:37 PM, Philippe Mathieu-Daudé wrote:
> LLD/SCD opcodes have been removed from the Release 6.
> Add a single decodetree entry for the opcodes, triggering
> Reserved Instruction if ever used.
>
> Remove unreachable check_insn_opc_removed() calls.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/isa-mips64r6.decode | 3 +++
> target/mips/translate.c | 2 --
> 2 files changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 13/13] target/mips: Convert Rel6 LL/SC opcodes to decodetree
2020-12-08 20:37 ` [PATCH 13/13] target/mips: Convert Rel6 LL/SC " Philippe Mathieu-Daudé
@ 2020-12-09 14:40 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 14:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/8/20 2:37 PM, Philippe Mathieu-Daudé wrote:
> LL/SC opcodes have been removed from the Release 6.
> Add a single decodetree entry for the opcodes, triggering
> Reserved Instruction if ever used.
>
> Remove unreachable check_insn_opc_removed() calls.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/isa-mips32r6.decode | 2 ++
> target/mips/translate.c | 2 --
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2020-12-08 20:37 ` [PATCH 13/13] target/mips: Convert Rel6 LL/SC " Philippe Mathieu-Daudé
@ 2021-01-07 18:48 ` Philippe Mathieu-Daudé
13 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-07 18:48 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Richard Henderson, Aurelien Jarno
On 12/8/20 9:36 PM, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (13):
...
> target/mips: Remove now unreachable LSA/DLSA opcodes code
> target/mips: Convert Rel6 Special2 opcode to decodetree
> target/mips: Convert Rel6 COP1X opcode to decodetree
> target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
> target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
> target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
> target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
> target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
> target/mips: Convert Rel6 LL/SC opcodes to decodetree
Thanks, patches 5 to 13 applied to mips-next.
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2021-01-07 18:49 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-08 20:36 [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
2020-12-08 20:36 ` [PATCH 01/13] !fixup "target/mips/translate: Add declarations for generic code" Philippe Mathieu-Daudé
2020-12-09 0:09 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 02/13] target/mips: Extract LSA/DLSA translation generators Philippe Mathieu-Daudé
2020-12-09 0:16 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 03/13] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Philippe Mathieu-Daudé
2020-12-09 0:22 ` Richard Henderson
2020-12-09 14:14 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 04/13] target/mips: Introduce decodetree helpers for Release6 " Philippe Mathieu-Daudé
2020-12-09 14:21 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 05/13] target/mips: Remove now unreachable LSA/DLSA opcodes code Philippe Mathieu-Daudé
2020-12-09 14:22 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 06/13] target/mips: Convert Rel6 Special2 opcode to decodetree Philippe Mathieu-Daudé
2020-12-09 14:23 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 07/13] target/mips: Convert Rel6 COP1X " Philippe Mathieu-Daudé
2020-12-09 14:23 ` Richard Henderson
2020-12-08 20:36 ` [PATCH 08/13] target/mips: Convert Rel6 CACHE/PREF opcodes " Philippe Mathieu-Daudé
2020-12-09 14:24 ` Richard Henderson
2020-12-08 20:37 ` [PATCH 09/13] target/mips: Convert Rel6 LWL/LWR/SWL/SWR " Philippe Mathieu-Daudé
2020-12-09 14:24 ` Richard Henderson
2020-12-08 20:37 ` [PATCH 10/13] target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE " Philippe Mathieu-Daudé
2020-12-09 14:35 ` Richard Henderson
2020-12-08 20:37 ` [PATCH 11/13] target/mips: Convert Rel6 LDL/LDR/SDL/SDR " Philippe Mathieu-Daudé
2020-12-09 14:39 ` Richard Henderson
2020-12-08 20:37 ` [PATCH 12/13] target/mips: Convert Rel6 LLD/SCD " Philippe Mathieu-Daudé
2020-12-09 14:40 ` Richard Henderson
2020-12-08 20:37 ` [PATCH 13/13] target/mips: Convert Rel6 LL/SC " Philippe Mathieu-Daudé
2020-12-09 14:40 ` Richard Henderson
2021-01-07 18:48 ` [PATCH 00/13] target/mips: Convert LSA/DLSA and part of the Rel6 removed opcodes Philippe Mathieu-Daudé
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