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From: <Tudor.Ambarus@microchip.com>
To: <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>,
	<p.yadav@ti.com>, <michael@walle.cc>,
	<linux-mtd@lists.infradead.org>, <broonie@kernel.org>,
	<linux-spi@vger.kernel.org>, <robh+dt@kernel.org>,
	<devicetree@vger.kernel.org>
Cc: <thomas.petazzoni@bootlin.com>, <monstr@monstr.eu>, <robh@kernel.org>
Subject: Re: [PATCH v3 1/3] dt-bindings: mtd: spi-nor: Allow two CS per device
Date: Tue, 7 Dec 2021 07:16:11 +0000	[thread overview]
Message-ID: <e5d05d00-8823-f9a2-156e-ac0c268d705c@microchip.com> (raw)
In-Reply-To: <20211206095921.33302-2-miquel.raynal@bootlin.com>

Hi, Miquel,

On 12/6/21 11:59 AM, Miquel Raynal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> The Xilinx QSPI controller has two advanced modes which allow the
> controller to behave differently and consider two flashes as one single
> storage.
> 
> One of these two modes is quite complex to support from a binding point
> of view and is the dual parallel memories. In this mode, each byte of
> data is stored in both devices: the even bits in one, the odd bits in
> the other. The split is automatically handled by the QSPI controller and
> is transparent for the user.
> 
> The other mode is simpler to support, it is called dual stacked
> memories. The controller shares the same SPI bus but each of the devices
> contain half of the data. Once in this mode, the controller does not
> follow CS requests but instead internally wires the two CS levels with
> the value of the most significant address bit.

The stacked mode that you describe seems particular to a specific
vendor. There are multi die NOR flashes which do not require any
controller intervention, the logic is held at the flash level:
https://media-www.micron.com/-/media/client/global/documents/products/technical-note/nor-flash/tn2505_n25q_mt25q_stacked_devices.pdf?rev=7a23cc95238e46f7b22e2a9f6bc736b7

Can you point us to which kind of memories you're willing to add
support for? Some datasheets will be best.

Cheers,
ta

> 
> Supporting these two modes will involve core changes which include the
> possibility of providing two CS for a single SPI device
> 
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>  Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> index 39421f7233e4..4abfb4cfc157 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> @@ -47,7 +47,8 @@ properties:
>        identified by the JEDEC READ ID opcode (0x9F).
> 
>    reg:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 2
> 
>    spi-max-frequency: true
>    spi-rx-bus-width: true
> --
> 2.27.0
> 

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: <Tudor.Ambarus@microchip.com>
To: <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>,
	<p.yadav@ti.com>, <michael@walle.cc>,
	<linux-mtd@lists.infradead.org>, <broonie@kernel.org>,
	<linux-spi@vger.kernel.org>, <robh+dt@kernel.org>,
	<devicetree@vger.kernel.org>
Cc: <thomas.petazzoni@bootlin.com>, <monstr@monstr.eu>, <robh@kernel.org>
Subject: Re: [PATCH v3 1/3] dt-bindings: mtd: spi-nor: Allow two CS per device
Date: Tue, 7 Dec 2021 07:16:11 +0000	[thread overview]
Message-ID: <e5d05d00-8823-f9a2-156e-ac0c268d705c@microchip.com> (raw)
In-Reply-To: <20211206095921.33302-2-miquel.raynal@bootlin.com>

Hi, Miquel,

On 12/6/21 11:59 AM, Miquel Raynal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> The Xilinx QSPI controller has two advanced modes which allow the
> controller to behave differently and consider two flashes as one single
> storage.
> 
> One of these two modes is quite complex to support from a binding point
> of view and is the dual parallel memories. In this mode, each byte of
> data is stored in both devices: the even bits in one, the odd bits in
> the other. The split is automatically handled by the QSPI controller and
> is transparent for the user.
> 
> The other mode is simpler to support, it is called dual stacked
> memories. The controller shares the same SPI bus but each of the devices
> contain half of the data. Once in this mode, the controller does not
> follow CS requests but instead internally wires the two CS levels with
> the value of the most significant address bit.

The stacked mode that you describe seems particular to a specific
vendor. There are multi die NOR flashes which do not require any
controller intervention, the logic is held at the flash level:
https://media-www.micron.com/-/media/client/global/documents/products/technical-note/nor-flash/tn2505_n25q_mt25q_stacked_devices.pdf?rev=7a23cc95238e46f7b22e2a9f6bc736b7

Can you point us to which kind of memories you're willing to add
support for? Some datasheets will be best.

Cheers,
ta

> 
> Supporting these two modes will involve core changes which include the
> possibility of providing two CS for a single SPI device
> 
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>  Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> index 39421f7233e4..4abfb4cfc157 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> @@ -47,7 +47,8 @@ properties:
>        identified by the JEDEC READ ID opcode (0x9F).
> 
>    reg:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 2
> 
>    spi-max-frequency: true
>    spi-rx-bus-width: true
> --
> 2.27.0
> 


  reply	other threads:[~2021-12-07  7:17 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-06  9:59 [PATCH v3 0/3] Stacked/parallel memories bindings Miquel Raynal
2021-12-06  9:59 ` Miquel Raynal
2021-12-06  9:59 ` [PATCH v3 1/3] dt-bindings: mtd: spi-nor: Allow two CS per device Miquel Raynal
2021-12-06  9:59   ` Miquel Raynal
2021-12-07  7:16   ` Tudor.Ambarus [this message]
2021-12-07  7:16     ` Tudor.Ambarus
2021-12-07  8:44     ` Miquel Raynal
2021-12-07  8:44       ` Miquel Raynal
2021-12-06  9:59 ` [PATCH v3 2/3] spi: dt-bindings: Describe stacked/parallel memories modes Miquel Raynal
2021-12-06  9:59   ` Miquel Raynal
2021-12-06 21:22   ` Rob Herring
2021-12-06 21:22     ` Rob Herring
2021-12-10 20:07     ` Miquel Raynal
2021-12-10 20:07       ` Miquel Raynal
2021-12-07  7:14   ` Pratyush Yadav
2021-12-07  7:14     ` Pratyush Yadav
2021-12-07  7:35     ` Tudor.Ambarus
2021-12-07  7:35       ` Tudor.Ambarus
2021-12-07  7:43       ` Tudor.Ambarus
2021-12-07  7:43         ` Tudor.Ambarus
2021-12-07  7:47         ` Tudor.Ambarus
2021-12-07  7:47           ` Tudor.Ambarus
2021-12-07  7:57       ` Pratyush Yadav
2021-12-07  7:57         ` Pratyush Yadav
2021-12-07  8:37         ` Miquel Raynal
2021-12-07  8:37           ` Miquel Raynal
2021-12-06  9:59 ` [PATCH v3 3/3] spi: dt-bindings: Add an example with two stacked flashes Miquel Raynal
2021-12-06  9:59   ` Miquel Raynal
2021-12-06 21:31   ` Rob Herring
2021-12-06 21:31     ` Rob Herring
2021-12-06 21:31 ` [PATCH v3 0/3] Stacked/parallel memories bindings Rob Herring
2021-12-06 21:31   ` Rob Herring
2021-12-07 14:31   ` Mark Brown
2021-12-07 14:31     ` Mark Brown

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