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From: <Tudor.Ambarus@microchip.com>
To: <p.yadav@ti.com>, <miquel.raynal@bootlin.com>
Cc: <richard@nod.at>, <vigneshr@ti.com>, <michael@walle.cc>,
	<linux-mtd@lists.infradead.org>, <broonie@kernel.org>,
	<linux-spi@vger.kernel.org>, <robh+dt@kernel.org>,
	<devicetree@vger.kernel.org>, <thomas.petazzoni@bootlin.com>,
	<monstr@monstr.eu>
Subject: Re: [PATCH v3 2/3] spi: dt-bindings: Describe stacked/parallel memories modes
Date: Tue, 7 Dec 2021 07:47:51 +0000	[thread overview]
Message-ID: <e99a977b-87dd-9e9a-62ea-ef544dfc80e4@microchip.com> (raw)
In-Reply-To: <11cb8408-1c5b-de83-dec0-5ec67305e772@microchip.com>

On 12/7/21 9:43 AM, Tudor Ambarus wrote:
> On 12/7/21 9:35 AM, Tudor Ambarus wrote:
>> On 12/7/21 9:14 AM, Pratyush Yadav wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 06/12/21 10:59AM, Miquel Raynal wrote:
>>>> Describe two new memories modes:
>>>> - A stacked mode when the bus is common but the address space extended
>>>>   with an additinals wires.
>>>> - A parallel mode with parallel busses accessing parallel flashes where
>>>>   the data is spread.
>>>>
>>>> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
>>>> ---
>>>>  .../bindings/spi/spi-peripheral-props.yaml    | 21 +++++++++++++++++++
>>>>  1 file changed, 21 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
>>>> index 5dd209206e88..13aa6a2374c9 100644
>>>> --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
>>>> +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
>>>> @@ -82,6 +82,27 @@ properties:
>>>>      description:
>>>>        Delay, in microseconds, after a write transfer.
>>>>
>>>> +  stacked-memories:
>>>> +    type: boolean
>>>
>>> I don't think a boolean is enough to completely describe the memory.
>>> Sure, you say the memories are stacked, but where do you specify when to
>>> switch the CS? They could be two 512 MiB memories, two 1 GiB memories,
>>> or one 512 MiB and one 256 MiB.
>>
>> If the multi-die flash contains identical dies then the die boundary can be
>> determined with flash_size / number_of_cs. Are there any multi die flashes
> 
> but the problem is there, yes, there is still the case where there are stacked
> devices with a single cs. We'll need to describe the size of the die in some
> way.
> 

Even better, winbond stacks a NOR and a NAND:
https://www.winbond.com/hq/product/code-storage-flash-memory/spistack-flash/?__locale=en

WARNING: multiple messages have this Message-ID (diff)
From: <Tudor.Ambarus@microchip.com>
To: <p.yadav@ti.com>, <miquel.raynal@bootlin.com>
Cc: <richard@nod.at>, <vigneshr@ti.com>, <michael@walle.cc>,
	<linux-mtd@lists.infradead.org>, <broonie@kernel.org>,
	<linux-spi@vger.kernel.org>, <robh+dt@kernel.org>,
	<devicetree@vger.kernel.org>, <thomas.petazzoni@bootlin.com>,
	<monstr@monstr.eu>
Subject: Re: [PATCH v3 2/3] spi: dt-bindings: Describe stacked/parallel memories modes
Date: Tue, 7 Dec 2021 07:47:51 +0000	[thread overview]
Message-ID: <e99a977b-87dd-9e9a-62ea-ef544dfc80e4@microchip.com> (raw)
In-Reply-To: <11cb8408-1c5b-de83-dec0-5ec67305e772@microchip.com>

On 12/7/21 9:43 AM, Tudor Ambarus wrote:
> On 12/7/21 9:35 AM, Tudor Ambarus wrote:
>> On 12/7/21 9:14 AM, Pratyush Yadav wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 06/12/21 10:59AM, Miquel Raynal wrote:
>>>> Describe two new memories modes:
>>>> - A stacked mode when the bus is common but the address space extended
>>>>   with an additinals wires.
>>>> - A parallel mode with parallel busses accessing parallel flashes where
>>>>   the data is spread.
>>>>
>>>> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
>>>> ---
>>>>  .../bindings/spi/spi-peripheral-props.yaml    | 21 +++++++++++++++++++
>>>>  1 file changed, 21 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
>>>> index 5dd209206e88..13aa6a2374c9 100644
>>>> --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
>>>> +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
>>>> @@ -82,6 +82,27 @@ properties:
>>>>      description:
>>>>        Delay, in microseconds, after a write transfer.
>>>>
>>>> +  stacked-memories:
>>>> +    type: boolean
>>>
>>> I don't think a boolean is enough to completely describe the memory.
>>> Sure, you say the memories are stacked, but where do you specify when to
>>> switch the CS? They could be two 512 MiB memories, two 1 GiB memories,
>>> or one 512 MiB and one 256 MiB.
>>
>> If the multi-die flash contains identical dies then the die boundary can be
>> determined with flash_size / number_of_cs. Are there any multi die flashes
> 
> but the problem is there, yes, there is still the case where there are stacked
> devices with a single cs. We'll need to describe the size of the die in some
> way.
> 

Even better, winbond stacks a NOR and a NAND:
https://www.winbond.com/hq/product/code-storage-flash-memory/spistack-flash/?__locale=en
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http://lists.infradead.org/mailman/listinfo/linux-mtd/

  reply	other threads:[~2021-12-07  7:48 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-06  9:59 [PATCH v3 0/3] Stacked/parallel memories bindings Miquel Raynal
2021-12-06  9:59 ` Miquel Raynal
2021-12-06  9:59 ` [PATCH v3 1/3] dt-bindings: mtd: spi-nor: Allow two CS per device Miquel Raynal
2021-12-06  9:59   ` Miquel Raynal
2021-12-07  7:16   ` Tudor.Ambarus
2021-12-07  7:16     ` Tudor.Ambarus
2021-12-07  8:44     ` Miquel Raynal
2021-12-07  8:44       ` Miquel Raynal
2021-12-06  9:59 ` [PATCH v3 2/3] spi: dt-bindings: Describe stacked/parallel memories modes Miquel Raynal
2021-12-06  9:59   ` Miquel Raynal
2021-12-06 21:22   ` Rob Herring
2021-12-06 21:22     ` Rob Herring
2021-12-10 20:07     ` Miquel Raynal
2021-12-10 20:07       ` Miquel Raynal
2021-12-07  7:14   ` Pratyush Yadav
2021-12-07  7:14     ` Pratyush Yadav
2021-12-07  7:35     ` Tudor.Ambarus
2021-12-07  7:35       ` Tudor.Ambarus
2021-12-07  7:43       ` Tudor.Ambarus
2021-12-07  7:43         ` Tudor.Ambarus
2021-12-07  7:47         ` Tudor.Ambarus [this message]
2021-12-07  7:47           ` Tudor.Ambarus
2021-12-07  7:57       ` Pratyush Yadav
2021-12-07  7:57         ` Pratyush Yadav
2021-12-07  8:37         ` Miquel Raynal
2021-12-07  8:37           ` Miquel Raynal
2021-12-06  9:59 ` [PATCH v3 3/3] spi: dt-bindings: Add an example with two stacked flashes Miquel Raynal
2021-12-06  9:59   ` Miquel Raynal
2021-12-06 21:31   ` Rob Herring
2021-12-06 21:31     ` Rob Herring
2021-12-06 21:31 ` [PATCH v3 0/3] Stacked/parallel memories bindings Rob Herring
2021-12-06 21:31   ` Rob Herring
2021-12-07 14:31   ` Mark Brown
2021-12-07 14:31     ` Mark Brown

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