From: "Christian König" <ckoenig.leichtzumerken@gmail.com> To: Thomas Zimmermann <tzimmermann@suse.de>, Oak Zeng <Oak.Zeng@amd.com>, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: jinhuieric.huang@amd.com, Alexander.Deucher@amd.com, Felix.Kuehling@amd.com, harish.kasiviswanathan@amd.com, christian.koenig@amd.com Subject: Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem caching setting Date: Wed, 3 Mar 2021 11:37:22 +0100 [thread overview] Message-ID: <e5e46c63-7dcf-44b0-6df9-4c88b9904fa1@gmail.com> (raw) In-Reply-To: <cff35ce0-3ad1-cc4a-f6ec-d423a913d0bc@suse.de> [-- Attachment #1.1: Type: text/plain, Size: 3263 bytes --] Hi Thomas, Am 03.03.21 um 09:49 schrieb Thomas Zimmermann: > Hi > > Am 01.03.21 um 23:43 schrieb Oak Zeng: >> If tbo.mem.bus.caching is cached, buffer is intended to be mapped >> as cached from CPU. Map it with ioremap_cache. > > Just a question for my understanding: This is on-device memory? > Accessing device memory is usually slow. If that memory can be mapped > with CPU caching enabled, access will roughly be as fast as for system > memory? There is still a penalty associated with accessing it from the CPU, but it is much faster (both lower latency as well as throughput) as traditional device memory accessed over PCIe. Regards, Christian. > > Best regards > Thomas > >> >> This wasn't necessary before as device memory was never mapped >> as cached from CPU side. It becomes necessary for aldebaran as >> device memory is mapped cached from CPU. >> >> Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> >> Reviewed-by: Christian Konig <Christian.Koenig@amd.com> >> --- >> drivers/gpu/drm/ttm/ttm_bo_util.c | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c >> b/drivers/gpu/drm/ttm/ttm_bo_util.c >> index 031e581..8c65a13 100644 >> --- a/drivers/gpu/drm/ttm/ttm_bo_util.c >> +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c >> @@ -91,6 +91,8 @@ static int ttm_resource_ioremap(struct ttm_device >> *bdev, >> if (mem->bus.caching == ttm_write_combined) >> addr = ioremap_wc(mem->bus.offset, bus_size); >> + else if (mem->bus.caching == ttm_cached) >> + addr = ioremap_cache(mem->bus.offset, bus_size); >> else >> addr = ioremap(mem->bus.offset, bus_size); >> if (!addr) { >> @@ -372,6 +374,9 @@ static int ttm_bo_ioremap(struct >> ttm_buffer_object *bo, >> if (mem->bus.caching == ttm_write_combined) >> map->virtual = ioremap_wc(bo->mem.bus.offset + offset, >> size); >> + else if (mem->bus.caching == ttm_cached) >> + map->virtual = ioremap_cache(bo->mem.bus.offset + offset, >> + size); >> else >> map->virtual = ioremap(bo->mem.bus.offset + offset, >> size); >> @@ -490,6 +495,9 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, >> struct dma_buf_map *map) >> else if (mem->bus.caching == ttm_write_combined) >> vaddr_iomem = ioremap_wc(mem->bus.offset, >> bo->base.size); >> + else if (mem->bus.caching == ttm_cached) >> + vaddr_iomem = ioremap_cache(mem->bus.offset, >> + bo->base.size); >> else >> vaddr_iomem = ioremap(mem->bus.offset, bo->base.size); >> > > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx [-- Attachment #1.2: Type: text/html, Size: 5298 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: "Christian König" <ckoenig.leichtzumerken@gmail.com> To: Thomas Zimmermann <tzimmermann@suse.de>, Oak Zeng <Oak.Zeng@amd.com>, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: jinhuieric.huang@amd.com, Alexander.Deucher@amd.com, Felix.Kuehling@amd.com, harish.kasiviswanathan@amd.com, christian.koenig@amd.com Subject: Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem caching setting Date: Wed, 3 Mar 2021 11:37:22 +0100 [thread overview] Message-ID: <e5e46c63-7dcf-44b0-6df9-4c88b9904fa1@gmail.com> (raw) In-Reply-To: <cff35ce0-3ad1-cc4a-f6ec-d423a913d0bc@suse.de> [-- Attachment #1.1: Type: text/plain, Size: 3263 bytes --] Hi Thomas, Am 03.03.21 um 09:49 schrieb Thomas Zimmermann: > Hi > > Am 01.03.21 um 23:43 schrieb Oak Zeng: >> If tbo.mem.bus.caching is cached, buffer is intended to be mapped >> as cached from CPU. Map it with ioremap_cache. > > Just a question for my understanding: This is on-device memory? > Accessing device memory is usually slow. If that memory can be mapped > with CPU caching enabled, access will roughly be as fast as for system > memory? There is still a penalty associated with accessing it from the CPU, but it is much faster (both lower latency as well as throughput) as traditional device memory accessed over PCIe. Regards, Christian. > > Best regards > Thomas > >> >> This wasn't necessary before as device memory was never mapped >> as cached from CPU side. It becomes necessary for aldebaran as >> device memory is mapped cached from CPU. >> >> Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> >> Reviewed-by: Christian Konig <Christian.Koenig@amd.com> >> --- >> drivers/gpu/drm/ttm/ttm_bo_util.c | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c >> b/drivers/gpu/drm/ttm/ttm_bo_util.c >> index 031e581..8c65a13 100644 >> --- a/drivers/gpu/drm/ttm/ttm_bo_util.c >> +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c >> @@ -91,6 +91,8 @@ static int ttm_resource_ioremap(struct ttm_device >> *bdev, >> if (mem->bus.caching == ttm_write_combined) >> addr = ioremap_wc(mem->bus.offset, bus_size); >> + else if (mem->bus.caching == ttm_cached) >> + addr = ioremap_cache(mem->bus.offset, bus_size); >> else >> addr = ioremap(mem->bus.offset, bus_size); >> if (!addr) { >> @@ -372,6 +374,9 @@ static int ttm_bo_ioremap(struct >> ttm_buffer_object *bo, >> if (mem->bus.caching == ttm_write_combined) >> map->virtual = ioremap_wc(bo->mem.bus.offset + offset, >> size); >> + else if (mem->bus.caching == ttm_cached) >> + map->virtual = ioremap_cache(bo->mem.bus.offset + offset, >> + size); >> else >> map->virtual = ioremap(bo->mem.bus.offset + offset, >> size); >> @@ -490,6 +495,9 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, >> struct dma_buf_map *map) >> else if (mem->bus.caching == ttm_write_combined) >> vaddr_iomem = ioremap_wc(mem->bus.offset, >> bo->base.size); >> + else if (mem->bus.caching == ttm_cached) >> + vaddr_iomem = ioremap_cache(mem->bus.offset, >> + bo->base.size); >> else >> vaddr_iomem = ioremap(mem->bus.offset, bo->base.size); >> > > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx [-- Attachment #1.2: Type: text/html, Size: 5298 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next prev parent reply other threads:[~2021-03-03 10:37 UTC|newest] Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-01 22:43 [PATCH] drm/ttm: ioremap buffer according to TTM mem caching setting Oak Zeng 2021-03-01 22:43 ` Oak Zeng 2021-03-02 2:16 ` kernel test robot 2021-03-02 2:16 ` kernel test robot 2021-03-02 2:16 ` kernel test robot 2021-03-02 4:12 ` kernel test robot 2021-03-02 4:12 ` kernel test robot 2021-03-02 4:12 ` kernel test robot 2021-03-02 11:31 ` Christian König 2021-03-02 11:31 ` Christian König 2021-03-02 22:45 ` Zeng, Oak 2021-03-02 22:45 ` Zeng, Oak 2021-03-02 22:53 ` Dave Airlie 2021-03-02 22:53 ` Dave Airlie 2021-03-02 22:53 ` Dave Airlie 2021-03-03 10:45 ` Christian König 2021-03-03 10:45 ` Christian König 2021-03-03 20:59 ` Zeng, Oak 2021-03-03 20:59 ` Zeng, Oak 2021-03-04 7:46 ` Christian König 2021-03-04 7:46 ` Christian König 2021-03-11 13:06 ` Daniel Vetter 2021-03-11 13:06 ` Daniel Vetter 2021-03-11 13:06 ` Daniel Vetter 2021-03-03 20:59 ` Zeng, Oak 2021-03-02 22:45 ` Zeng, Oak 2021-03-03 8:49 ` Thomas Zimmermann 2021-03-03 8:49 ` Thomas Zimmermann 2021-03-03 10:37 ` Christian König [this message] 2021-03-03 10:37 ` Christian König 2021-03-03 21:12 Oak Zeng 2021-03-03 21:12 ` Oak Zeng 2021-03-04 7:48 ` Christian König 2021-03-04 7:48 ` Christian König 2021-03-04 16:04 Oak Zeng 2021-03-04 16:04 ` Oak Zeng 2021-03-04 17:01 ` Bhardwaj, Rajneesh 2021-03-04 17:01 ` Bhardwaj, Rajneesh 2021-03-04 17:31 ` Christian König 2021-03-04 17:31 ` Christian König 2021-03-04 17:40 ` Bhardwaj, Rajneesh 2021-03-04 17:40 ` Bhardwaj, Rajneesh 2021-03-04 18:05 ` Christian König 2021-03-04 18:05 ` Christian König 2021-03-04 19:00 ` kernel test robot 2021-03-04 19:00 ` kernel test robot 2021-03-04 19:04 ` kernel test robot 2021-03-04 19:04 ` kernel test robot 2021-03-04 19:16 Oak Zeng
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