[U-Boot] [PATCH 0/4] AE350 support SMP boot from flash

[U-Boot] [PATCH 0/4] AE350 support SMP boot from flash

[Andes]

From: Rick Chen <rick@andestech.com>

In current RISC-V SMP flow, AE350 will encounter the the write
failure problem since hart_lottery and available_harts_lock was
not in ram address but in flash address when booing from flash.

This patch can help to fix the failure problem when AE350 was
booting from flash by disable this two features.

Rick Chen (4):
  riscv: hart_lottery and available harts feature can be seletable
  riscv: configs: Support AE350 SMP boot from flash flow
  riscv: prior_stage_fdt_address only be used when OF_PRIOR_STAGE is
    enable
  riscv: configs: AE350 will use OF_PRIOR_STAGE when boot from ram

 arch/riscv/Kconfig                   | 21 ++++++++++++++++++++
 arch/riscv/cpu/cpu.c                 |  4 ++++
 arch/riscv/cpu/start.S               | 11 ++++++++++-
 arch/riscv/include/asm/global_data.h |  2 ++
 arch/riscv/lib/asm-offsets.c         |  2 ++
 arch/riscv/lib/smp.c                 |  2 ++
 configs/ae350_rv32_defconfig         |  2 +-
 configs/ae350_rv32_xip_defconfig     | 37 +++++++++++++++++++++++++++++++++++
 configs/ae350_rv64_defconfig         |  2 +-
 configs/ae350_rv64_xip_defconfig     | 38 ++++++++++++++++++++++++++++++++++++
 10 files changed, 118 insertions(+), 3 deletions(-)
 create mode 100644 configs/ae350_rv32_xip_defconfig
 create mode 100644 configs/ae350_rv64_xip_defconfig

-- 
2.7.4

[U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable

[Andes]

From: Rick Chen <rick@andestech.com>

In smp flow this two features only can be enabled when U-Boot
boot from ram. It shall be disabled when U-Boot boot from flash.

Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select
this two features. Their default value will say YES for booting
from ram.

AE350 will encounter the the write failure problem since
hart_lottery and available_harts_lock was not in ram address
but in flash address when booing from flash.

This patch can help to fix the failure problem when AE350 was
booting from flash by disable this two features.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
 arch/riscv/Kconfig                   | 21 +++++++++++++++++++++
 arch/riscv/cpu/cpu.c                 |  4 ++++
 arch/riscv/cpu/start.S               |  9 ++++++++-
 arch/riscv/include/asm/global_data.h |  2 ++
 arch/riscv/lib/asm-offsets.c         |  2 ++
 arch/riscv/lib/smp.c                 |  2 ++
 6 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ae8ff7b..4354396 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -162,6 +162,27 @@ config SBI_IPI
 	default y if RISCV_SMODE
 	depends on SMP
 
+config HART_LOTTERY
+	bool "Hart lottery support"
+	default y
+	depends on SMP
+	help
+	  This will upport hart lottery, all harts have changce to become
+	  main hart. But if you say N here, hart 0 will be the main hart.
+	  It only can be enabled when U-Boot boot from ram, but shall be
+	  disabled when boot from flash.
+
+config AVAILABLE_HARTS
+	bool "available harts support"
+	default y
+	depends on SMP
+	depends on HART_LOTTERY
+	help
+	  This will help to record active harts and compare with dts' cpus.
+	  So it will not send ipi to in-active harts.
+	  It only can be enabled when U-Boot boot from ram, but shall be
+	  disabled when boot from flash.
+
 config STACK_SIZE_SHIFT
 	int
 	default 13
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c32de8a..0add783 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -16,13 +16,17 @@
  * before the bss section is available.
  */
 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#ifdef CONFIG_HART_LOTTERY
 u32 hart_lottery __attribute__((section(".data"))) = 0;
+#endif
 
+#ifdef CONFIG_AVAILABLE_HARTS
 /*
  * The main hart running U-Boot has acquired available_harts_lock until it has
  * finished initialization of global data.
  */
 u32 available_harts_lock = 1;
+#endif
 
 static inline bool supports_extension(char ext)
 {
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a4433fb..d030d4a 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -98,6 +98,7 @@ call_board_init_f_0:
 	mv	sp, a0
 #endif
 
+#ifdef CONFIG_HART_LOTTERY
 	/*
 	 * Pick hart to initialize global data and run U-Boot. The other harts
 	 * wait for initialization to complete.
@@ -106,6 +107,9 @@ call_board_init_f_0:
 	li	s2, 1
 	amoswap.w s2, t1, 0(t0)
 	bnez	s2, wait_for_gd_init
+#else
+	bnez	tp, secondary_hart_loop
+#endif
 
 	la	t0, prior_stage_fdt_address
 	SREG	s1, 0(t0)
@@ -115,6 +119,7 @@ call_board_init_f_0:
 	/* save the boot hart id to global_data */
 	SREG	tp, GD_BOOT_HART(gp)
 
+#ifdef CONFIG_AVAILABLE_HARTS
 	la	t0, available_harts_lock
 	fence	rw, w
 	amoswap.w zero, zero, 0(t0)
@@ -135,13 +140,15 @@ wait_for_gd_init:
 
 	fence	rw, w
 	amoswap.w zero, zero, 0(t0)
+#endif
 
+#ifdef CONFIG_HART_LOTTERY
 	/*
 	 * Continue on hart lottery winner, others branch to
 	 * secondary_hart_loop.
 	 */
 	bnez	s2, secondary_hart_loop
-
+#endif
 	/* Enable cache */
 	jal	icache_enable
 	jal	dcache_enable
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index dffcd45..e2e8b65 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -27,7 +27,9 @@ struct arch_global_data {
 #ifdef CONFIG_SMP
 	struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
+#ifdef CONFIG_AVAILABLE_HARTS
 	ulong available_harts;
+#endif
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index f998402..3ebda97 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -14,7 +14,9 @@
 int main(void)
 {
 	DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+#ifdef CONFIG_AVAILABLE_HARTS
 	DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
+#endif
 
 	return 0;
 }
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index caa292c..4de7ea2 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi)
 			continue;
 		}
 
+#ifdef CONFIG_AVAILABLE_HARTS
 		/* skip if hart is not available */
 		if (!(gd->arch.available_harts & (1 << reg)))
 			continue;
+#endif
 
 		gd->arch.ipi[reg].addr = ipi->addr;
 		gd->arch.ipi[reg].arg0 = ipi->arg0;
-- 
2.7.4

[U-Boot] [PATCH 2/4] riscv: configs: Support AE350 SMP boot from flash flow

[Andes]

From: Rick Chen <rick@andestech.com>

Add two defconfig to support AE350 SMP boot from flash
by disable CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
 configs/ae350_rv32_xip_defconfig | 37 +++++++++++++++++++++++++++++++++++++
 configs/ae350_rv64_xip_defconfig | 38 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 75 insertions(+)
 create mode 100644 configs/ae350_rv32_xip_defconfig
 create mode 100644 configs/ae350_rv64_xip_defconfig

diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
new file mode 100644
index 0000000..1639367
--- /dev/null
+++ b/configs/ae350_rv32_xip_defconfig
@@ -0,0 +1,37 @@
+CONFIG_RISCV=y
+CONFIG_HART_LOTTERY=n
+CONFIG_AVAILABLE_HARTS=n
+CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_BOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
new file mode 100644
index 0000000..d6a502c
--- /dev/null
+++ b/configs/ae350_rv64_xip_defconfig
@@ -0,0 +1,38 @@
+CONFIG_RISCV=y
+CONFIG_HART_LOTTERY=n
+CONFIG_AVAILABLE_HARTS=n
+CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_BOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
-- 
2.7.4

[U-Boot] [PATCH 3/4] riscv: prior_stage_fdt_address only be used when OF_PRIOR_STAGE is enable

[Andes]

From: Rick Chen <rick@andestech.com>

This patch will fix prior_stage_fdt_address write failure problem, when
AE350 was booting from flash.

When AE350 was booting from falsh, prior_stage_fdt_address will be in
flash address, we shall avoid it to be written.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
 arch/riscv/cpu/start.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index d030d4a..0e672e0 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,7 +111,9 @@ call_board_init_f_0:
 	bnez	tp, secondary_hart_loop
 #endif
 
+#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
 	la	t0, prior_stage_fdt_address
+#endif
 	SREG	s1, 0(t0)
 
 	jal	board_init_f_init_reserve
-- 
2.7.4

[U-Boot] [PATCH 4/4] riscv: configs: AE350 will use OF_PRIOR_STAGE when boot from ram

[Andes]

From: Rick Chen <rick@andestech.com>

When AE350 was booting from ram, use OF_PRIOR_STAGE instead
of OF_PRIOR_STAGE.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
 configs/ae350_rv32_defconfig | 2 +-
 configs/ae350_rv64_defconfig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index e13c7de..54b65f1 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index a41f918..0ff4de8 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
-- 
2.7.4

[U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable

[Bin Meng]

Hi Rick,

On Tue, Apr 23, 2019 at 1:47 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>

typo in the commit title: seletable -> selectable

> In smp flow this two features only can be enabled when U-Boot

this->these

> boot from ram. It shall be disabled when U-Boot boot from flash.

boot->boots

>
> Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select
> this two features. Their default value will say YES for booting

this->these

> from ram.
>
> AE350 will encounter the the write failure problem since
> hart_lottery and available_harts_lock was not in ram address

was->is

> but in flash address when booing from flash.

booing->booting

>
> This patch can help to fix the failure problem when AE350 was

was->is

> booting from flash by disable this two features.

disable->disabling

>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
>  arch/riscv/Kconfig                   | 21 +++++++++++++++++++++
>  arch/riscv/cpu/cpu.c                 |  4 ++++
>  arch/riscv/cpu/start.S               |  9 ++++++++-
>  arch/riscv/include/asm/global_data.h |  2 ++
>  arch/riscv/lib/asm-offsets.c         |  2 ++
>  arch/riscv/lib/smp.c                 |  2 ++
>  6 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index ae8ff7b..4354396 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -162,6 +162,27 @@ config SBI_IPI
>         default y if RISCV_SMODE
>         depends on SMP
>
> +config HART_LOTTERY
> +       bool "Hart lottery support"

nits: I would use "hart"

> +       default y
> +       depends on SMP
> +       help
> +         This will upport hart lottery, all harts have changce to become

upport->support, changce->chance

> +         main hart. But if you say N here, hart 0 will be the main hart.
> +         It only can be enabled when U-Boot boot from ram, but shall be

boot->boots

> +         disabled when boot from flash.

boot->booting

> +
> +config AVAILABLE_HARTS
> +       bool "available harts support"
> +       default y
> +       depends on SMP
> +       depends on HART_LOTTERY
> +       help
> +         This will help to record active harts and compare with dts' cpus.
> +         So it will not send ipi to in-active harts.

in-active->inactive

> +         It only can be enabled when U-Boot boot from ram, but shall be

boot->boots

> +         disabled when boot from flash.

boot->booting

> +
>  config STACK_SIZE_SHIFT
>         int
>         default 13
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index c32de8a..0add783 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -16,13 +16,17 @@
>   * before the bss section is available.
>   */
>  phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
> +#ifdef CONFIG_HART_LOTTERY
>  u32 hart_lottery __attribute__((section(".data"))) = 0;
> +#endif
>
> +#ifdef CONFIG_AVAILABLE_HARTS
>  /*
>   * The main hart running U-Boot has acquired available_harts_lock until it has
>   * finished initialization of global data.
>   */
>  u32 available_harts_lock = 1;
> +#endif
>
>  static inline bool supports_extension(char ext)
>  {
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index a4433fb..d030d4a 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -98,6 +98,7 @@ call_board_init_f_0:
>         mv      sp, a0
>  #endif
>
> +#ifdef CONFIG_HART_LOTTERY
>         /*
>          * Pick hart to initialize global data and run U-Boot. The other harts
>          * wait for initialization to complete.
> @@ -106,6 +107,9 @@ call_board_init_f_0:
>         li      s2, 1
>         amoswap.w s2, t1, 0(t0)
>         bnez    s2, wait_for_gd_init
> +#else
> +       bnez    tp, secondary_hart_loop
> +#endif
>
>         la      t0, prior_stage_fdt_address
>         SREG    s1, 0(t0)
> @@ -115,6 +119,7 @@ call_board_init_f_0:
>         /* save the boot hart id to global_data */
>         SREG    tp, GD_BOOT_HART(gp)
>
> +#ifdef CONFIG_AVAILABLE_HARTS
>         la      t0, available_harts_lock
>         fence   rw, w
>         amoswap.w zero, zero, 0(t0)
> @@ -135,13 +140,15 @@ wait_for_gd_init:
>
>         fence   rw, w
>         amoswap.w zero, zero, 0(t0)
> +#endif
>
> +#ifdef CONFIG_HART_LOTTERY
>         /*
>          * Continue on hart lottery winner, others branch to
>          * secondary_hart_loop.
>          */
>         bnez    s2, secondary_hart_loop
> -

This blank line should not be deleted.

> +#endif
>         /* Enable cache */
>         jal     icache_enable
>         jal     dcache_enable
> diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> index dffcd45..e2e8b65 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -27,7 +27,9 @@ struct arch_global_data {
>  #ifdef CONFIG_SMP
>         struct ipi_data ipi[CONFIG_NR_CPUS];
>  #endif
> +#ifdef CONFIG_AVAILABLE_HARTS
>         ulong available_harts;
> +#endif
>  };
>
>  #include <asm-generic/global_data.h>
> diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
> index f998402..3ebda97 100644
> --- a/arch/riscv/lib/asm-offsets.c
> +++ b/arch/riscv/lib/asm-offsets.c
> @@ -14,7 +14,9 @@
>  int main(void)
>  {
>         DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
> +#ifdef CONFIG_AVAILABLE_HARTS
>         DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
> +#endif
>
>         return 0;
>  }
> diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
> index caa292c..4de7ea2 100644
> --- a/arch/riscv/lib/smp.c
> +++ b/arch/riscv/lib/smp.c
> @@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi)
>                         continue;
>                 }
>
> +#ifdef CONFIG_AVAILABLE_HARTS
>                 /* skip if hart is not available */
>                 if (!(gd->arch.available_harts & (1 << reg)))
>                         continue;
> +#endif
>
>                 gd->arch.ipi[reg].addr = ipi->addr;
>                 gd->arch.ipi[reg].arg0 = ipi->arg0;
> --

Regards,
Bin

[U-Boot] [PATCH 2/4] riscv: configs: Support AE350 SMP boot from flash flow

[Bin Meng]

Hi Rick,

On Tue, Apr 23, 2019 at 1:47 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>

nits in the commit title: boot->booting

>
> Add two defconfig to support AE350 SMP boot from flash

boot->bootings

> by disable CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS.

disable->disabling

>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
>  configs/ae350_rv32_xip_defconfig | 37 +++++++++++++++++++++++++++++++++++++
>  configs/ae350_rv64_xip_defconfig | 38 ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 75 insertions(+)
>  create mode 100644 configs/ae350_rv32_xip_defconfig
>  create mode 100644 configs/ae350_rv64_xip_defconfig
>
> diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
> new file mode 100644
> index 0000000..1639367
> --- /dev/null
> +++ b/configs/ae350_rv32_xip_defconfig
> @@ -0,0 +1,37 @@
> +CONFIG_RISCV=y
> +CONFIG_HART_LOTTERY=n
> +CONFIG_AVAILABLE_HARTS=n

I think this should be:

# CONFIG_HART_LOTTERY is not set
# CONFIG_AVAILABLE_HARTS is not set

> +CONFIG_SYS_TEXT_BASE=0x80000000
> +CONFIG_TARGET_AX25_AE350=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_NR_DRAM_BANKS=2
> +CONFIG_FIT=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_SYS_PROMPT="RISC-V # "
> +CONFIG_CMD_IMLS=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SF_TEST=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_BOOTP_PREFER_SERVERIP=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_OF_BOARD=y
> +CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_MMC=y
> +CONFIG_FTSDC010=y
> +CONFIG_FTSDC010_SDIO=y
> +CONFIG_MTD_NOR_FLASH=y
> +CONFIG_FLASH_CFI_DRIVER=y
> +CONFIG_CFI_FLASH=y
> +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> +CONFIG_SYS_FLASH_CFI=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_FTMAC100=y
> +CONFIG_BAUDRATE=38400
> +CONFIG_SYS_NS16550=y
> +CONFIG_SPI=y
> +CONFIG_ATCSPI200_SPI=y
> diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
> new file mode 100644
> index 0000000..d6a502c
> --- /dev/null
> +++ b/configs/ae350_rv64_xip_defconfig
> @@ -0,0 +1,38 @@
> +CONFIG_RISCV=y
> +CONFIG_HART_LOTTERY=n
> +CONFIG_AVAILABLE_HARTS=n

ditto

> +CONFIG_SYS_TEXT_BASE=0x80000000
> +CONFIG_TARGET_AX25_AE350=y
> +CONFIG_ARCH_RV64I=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_NR_DRAM_BANKS=2
> +CONFIG_FIT=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_SYS_PROMPT="RISC-V # "
> +CONFIG_CMD_IMLS=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SF_TEST=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_BOOTP_PREFER_SERVERIP=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_OF_BOARD=y
> +CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_MMC=y
> +CONFIG_FTSDC010=y
> +CONFIG_FTSDC010_SDIO=y
> +CONFIG_MTD_NOR_FLASH=y
> +CONFIG_FLASH_CFI_DRIVER=y
> +CONFIG_CFI_FLASH=y
> +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> +CONFIG_SYS_FLASH_CFI=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_FTMAC100=y
> +CONFIG_BAUDRATE=38400
> +CONFIG_SYS_NS16550=y
> +CONFIG_SPI=y
> +CONFIG_ATCSPI200_SPI=y

Regards,
Bin

[U-Boot] [PATCH 3/4] riscv: prior_stage_fdt_address only be used when OF_PRIOR_STAGE is enable

[Bin Meng]

Hi Rick,

On Tue, Apr 23, 2019 at 1:47 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>

commit title should read: prior_stage_fdt_address should only be used
when OF_PRIOR_STAGE is enabled

> This patch will fix prior_stage_fdt_address write failure problem, when
> AE350 was booting from flash.
>
> When AE350 was booting from falsh, prior_stage_fdt_address will be in
> flash address, we shall avoid it to be written.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
>  arch/riscv/cpu/start.S | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index d030d4a..0e672e0 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -111,7 +111,9 @@ call_board_init_f_0:
>         bnez    tp, secondary_hart_loop
>  #endif
>
> +#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
>         la      t0, prior_stage_fdt_address
> +#endif

I think you should also surround the declaration of
prior_stage_fdt_address in arch/riscv/cpu/cpu.c with OF_PRIOR_STAGE

>         SREG    s1, 0(t0)
>
>         jal     board_init_f_init_reserve
> --

Regards,
Bin

[U-Boot] [PATCH 4/4] riscv: configs: AE350 will use OF_PRIOR_STAGE when boot from ram

[Bin Meng]

Hi Rick,

On Tue, Apr 23, 2019 at 1:47 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>

nits in the commit title: boot->booting

> When AE350 was booting from ram, use OF_PRIOR_STAGE instead
> of OF_PRIOR_STAGE.

This should be CONFIG_OF_BOARD

>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
>  configs/ae350_rv32_defconfig | 2 +-
>  configs/ae350_rv64_defconfig | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
> index e13c7de..54b65f1 100644
> --- a/configs/ae350_rv32_defconfig
> +++ b/configs/ae350_rv32_defconfig
> @@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y
>  # CONFIG_CMD_SETEXPR is not set
>  CONFIG_BOOTP_PREFER_SERVERIP=y
>  CONFIG_CMD_CACHE=y
> -CONFIG_OF_BOARD=y
> +CONFIG_OF_PRIOR_STAGE=y
>  CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
>  CONFIG_ENV_IS_IN_SPI_FLASH=y
>  CONFIG_NET_RANDOM_ETHADDR=y
> diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
> index a41f918..0ff4de8 100644
> --- a/configs/ae350_rv64_defconfig
> +++ b/configs/ae350_rv64_defconfig
> @@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y
>  # CONFIG_CMD_SETEXPR is not set
>  CONFIG_BOOTP_PREFER_SERVERIP=y
>  CONFIG_CMD_CACHE=y
> -CONFIG_OF_BOARD=y
> +CONFIG_OF_PRIOR_STAGE=y
>  CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
>  CONFIG_ENV_IS_IN_SPI_FLASH=y
>  CONFIG_NET_RANDOM_ETHADDR=y

Regards,
Bin

[U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable

[Bin Meng]

On Tue, Apr 23, 2019 at 8:14 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Rick,
>
> On Tue, Apr 23, 2019 at 1:47 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
>
> typo in the commit title: seletable -> selectable
>
> > In smp flow this two features only can be enabled when U-Boot
>
> this->these
>
> > boot from ram. It shall be disabled when U-Boot boot from flash.
>
> boot->boots
>
> >
> > Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select

BTW: is it possible to use a single option for such feature, like
CONFIG_XIP? Basically these two options are used for the same reason.

> > this two features. Their default value will say YES for booting
>
> this->these
>
> > from ram.

Regards,
Bin

[U-Boot] [PATCH 0/4] AE350 support SMP boot from flash

[Auer, Lukas]

Hi Rick,

On Tue, 2019-04-23 at 13:42 +0800, Andes wrote:
> From: Rick Chen <rick@andestech.com>
> 
> In current RISC-V SMP flow, AE350 will encounter the the write
> failure problem since hart_lottery and available_harts_lock was
> not in ram address but in flash address when booing from flash.
> 
> This patch can help to fix the failure problem when AE350 was
> booting from flash by disable this two features.
> 

Can you describe the issue you are seeing a bit more. The write
failures are both to variables in the .data section, which should be
writable. Perhaps the write failures can be avoided by moving the .data
section or just the variable to RAM?

Thanks,
Lukas

[U-Boot] [PATCH 0/4] AE350 support SMP boot from flash

[Rick Chen]

Hi Lukas

Auer, Lukas <lukas.auer@aisec.fraunhofer.de> 於 2019年4月24日 週三 上午3:58寫道：
>
> Hi Rick,
>
> On Tue, 2019-04-23 at 13:42 +0800, Andes wrote:
> > From: Rick Chen <rick@andestech.com>
> >
> > In current RISC-V SMP flow, AE350 will encounter the the write
> > failure problem since hart_lottery and available_harts_lock was
> > not in ram address but in flash address when booing from flash.
> >
> > This patch can help to fix the failure problem when AE350 was
> > booting from flash by disable this two features.
> >
>
> Can you describe the issue you are seeing a bit more. The write
> failures are both to variables in the .data section, which should be
> writable. Perhaps the write failures can be avoided by moving the .data
> section or just the variable to RAM?
>

When I compile AE350's CONFIG_SYS_TEXT_BASE=0x80000000 which is spi flash base.
And burn u-boot.bin into AE350 spi flash. Power off / on, U-Boot will
run in XIP mode.
At this time prior_stage_fdt_address will be in flash address(0x8004e9e8)
So it is not writable.

80000042:       16021563                bnez    tp,800001ac
<secondary_hart_loop>
80000046:       0004f297                auipc   t0,0x4f
8000004a:       9a22a283                lw      t0,-1630(t0) #
8004e9e8 <prior_stage_fdt_address+0x3f74>
8000004e:       0092a023                sw      s1,0(t0)

Rick

> Thanks,
> Lukas

[U-Boot] [PATCH 2/4] riscv: configs: Support AE350 SMP boot from flash flow

[Rick Chen]

Hi Bin

Bin Meng <bmeng.cn@gmail.com> 於 2019年4月23日 週二 下午8:14寫道：
>
> Hi Rick,
>
> On Tue, Apr 23, 2019 at 1:47 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
>
> nits in the commit title: boot->booting

OK

>
> >
> > Add two defconfig to support AE350 SMP boot from flash
>
> boot->bootings

OK

>
> > by disable CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS.
>
> disable->disabling

OK

>
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> >  configs/ae350_rv32_xip_defconfig | 37 +++++++++++++++++++++++++++++++++++++
> >  configs/ae350_rv64_xip_defconfig | 38 ++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 75 insertions(+)
> >  create mode 100644 configs/ae350_rv32_xip_defconfig
> >  create mode 100644 configs/ae350_rv64_xip_defconfig
> >
> > diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
> > new file mode 100644
> > index 0000000..1639367
> > --- /dev/null
> > +++ b/configs/ae350_rv32_xip_defconfig
> > @@ -0,0 +1,37 @@
> > +CONFIG_RISCV=y
> > +CONFIG_HART_LOTTERY=n
> > +CONFIG_AVAILABLE_HARTS=n
>
> I think this should be:
>
> # CONFIG_HART_LOTTERY is not set
> # CONFIG_AVAILABLE_HARTS is not set

OK

>
> > +CONFIG_SYS_TEXT_BASE=0x80000000
> > +CONFIG_TARGET_AX25_AE350=y
> > +CONFIG_DISTRO_DEFAULTS=y
> > +CONFIG_NR_DRAM_BANKS=2
> > +CONFIG_FIT=y
> > +CONFIG_BOOTDELAY=3
> > +CONFIG_BOARD_EARLY_INIT_F=y
> > +CONFIG_SYS_PROMPT="RISC-V # "
> > +CONFIG_CMD_IMLS=y
> > +CONFIG_CMD_MMC=y
> > +CONFIG_CMD_SF=y
> > +CONFIG_CMD_SF_TEST=y
> > +# CONFIG_CMD_SETEXPR is not set
> > +CONFIG_BOOTP_PREFER_SERVERIP=y
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_OF_BOARD=y
> > +CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
> > +CONFIG_ENV_IS_IN_SPI_FLASH=y
> > +CONFIG_NET_RANDOM_ETHADDR=y
> > +CONFIG_MMC=y
> > +CONFIG_FTSDC010=y
> > +CONFIG_FTSDC010_SDIO=y
> > +CONFIG_MTD_NOR_FLASH=y
> > +CONFIG_FLASH_CFI_DRIVER=y
> > +CONFIG_CFI_FLASH=y
> > +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> > +CONFIG_SYS_FLASH_CFI=y
> > +CONFIG_SPI_FLASH=y
> > +CONFIG_SPI_FLASH_MACRONIX=y
> > +CONFIG_FTMAC100=y
> > +CONFIG_BAUDRATE=38400
> > +CONFIG_SYS_NS16550=y
> > +CONFIG_SPI=y
> > +CONFIG_ATCSPI200_SPI=y
> > diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
> > new file mode 100644
> > index 0000000..d6a502c
> > --- /dev/null
> > +++ b/configs/ae350_rv64_xip_defconfig
> > @@ -0,0 +1,38 @@
> > +CONFIG_RISCV=y
> > +CONFIG_HART_LOTTERY=n
> > +CONFIG_AVAILABLE_HARTS=n
>
> ditto

OK

>
> > +CONFIG_SYS_TEXT_BASE=0x80000000
> > +CONFIG_TARGET_AX25_AE350=y
> > +CONFIG_ARCH_RV64I=y
> > +CONFIG_DISTRO_DEFAULTS=y
> > +CONFIG_NR_DRAM_BANKS=2
> > +CONFIG_FIT=y
> > +CONFIG_BOOTDELAY=3
> > +CONFIG_BOARD_EARLY_INIT_F=y
> > +CONFIG_SYS_PROMPT="RISC-V # "
> > +CONFIG_CMD_IMLS=y
> > +CONFIG_CMD_MMC=y
> > +CONFIG_CMD_SF=y
> > +CONFIG_CMD_SF_TEST=y
> > +# CONFIG_CMD_SETEXPR is not set
> > +CONFIG_BOOTP_PREFER_SERVERIP=y
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_OF_BOARD=y
> > +CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
> > +CONFIG_ENV_IS_IN_SPI_FLASH=y
> > +CONFIG_NET_RANDOM_ETHADDR=y
> > +CONFIG_MMC=y
> > +CONFIG_FTSDC010=y
> > +CONFIG_FTSDC010_SDIO=y
> > +CONFIG_MTD_NOR_FLASH=y
> > +CONFIG_FLASH_CFI_DRIVER=y
> > +CONFIG_CFI_FLASH=y
> > +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> > +CONFIG_SYS_FLASH_CFI=y
> > +CONFIG_SPI_FLASH=y
> > +CONFIG_SPI_FLASH_MACRONIX=y
> > +CONFIG_FTMAC100=y
> > +CONFIG_BAUDRATE=38400
> > +CONFIG_SYS_NS16550=y
> > +CONFIG_SPI=y
> > +CONFIG_ATCSPI200_SPI=y
>

Thanks for your review.
Rick

> Regards,
> Bin

[U-Boot] [PATCH 3/4] riscv: prior_stage_fdt_address only be used when OF_PRIOR_STAGE is enable

[Rick Chen]

Hi Bin

Bin Meng <bmeng.cn@gmail.com> 於 2019年4月23日 週二 下午8:14寫道：
>
> Hi Rick,
>
> On Tue, Apr 23, 2019 at 1:47 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
>
> commit title should read: prior_stage_fdt_address should only be used
> when OF_PRIOR_STAGE is enabled

OK

>
> > This patch will fix prior_stage_fdt_address write failure problem, when
> > AE350 was booting from flash.
> >
> > When AE350 was booting from falsh, prior_stage_fdt_address will be in
> > flash address, we shall avoid it to be written.
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> >  arch/riscv/cpu/start.S | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> > index d030d4a..0e672e0 100644
> > --- a/arch/riscv/cpu/start.S
> > +++ b/arch/riscv/cpu/start.S
> > @@ -111,7 +111,9 @@ call_board_init_f_0:
> >         bnez    tp, secondary_hart_loop
> >  #endif
> >
> > +#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
> >         la      t0, prior_stage_fdt_address
> > +#endif
>
> I think you should also surround the declaration of
> prior_stage_fdt_address in arch/riscv/cpu/cpu.c with OF_PRIOR_STAGE

OK
I will surround it.

Thanks for review
Rick

>
> >         SREG    s1, 0(t0)
> >
> >         jal     board_init_f_init_reserve
> > --
>
> Regards,
> Bin

[U-Boot] [PATCH 4/4] riscv: configs: AE350 will use OF_PRIOR_STAGE when boot from ram

[Rick Chen]

Hi Bin

Bin Meng <bmeng.cn@gmail.com> 於 2019年4月23日 週二 下午8:14寫道：
>
> Hi Rick,
>
> On Tue, Apr 23, 2019 at 1:47 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
>
> nits in the commit title: boot->booting

OK

>
> > When AE350 was booting from ram, use OF_PRIOR_STAGE instead
> > of OF_PRIOR_STAGE.
>
> This should be CONFIG_OF_BOARD

OK

Thanks
Rick

>
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> >  configs/ae350_rv32_defconfig | 2 +-
> >  configs/ae350_rv64_defconfig | 2 +-
> >  2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
> > index e13c7de..54b65f1 100644
> > --- a/configs/ae350_rv32_defconfig
> > +++ b/configs/ae350_rv32_defconfig
> > @@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y
> >  # CONFIG_CMD_SETEXPR is not set
> >  CONFIG_BOOTP_PREFER_SERVERIP=y
> >  CONFIG_CMD_CACHE=y
> > -CONFIG_OF_BOARD=y
> > +CONFIG_OF_PRIOR_STAGE=y
> >  CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
> >  CONFIG_ENV_IS_IN_SPI_FLASH=y
> >  CONFIG_NET_RANDOM_ETHADDR=y
> > diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
> > index a41f918..0ff4de8 100644
> > --- a/configs/ae350_rv64_defconfig
> > +++ b/configs/ae350_rv64_defconfig
> > @@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y
> >  # CONFIG_CMD_SETEXPR is not set
> >  CONFIG_BOOTP_PREFER_SERVERIP=y
> >  CONFIG_CMD_CACHE=y
> > -CONFIG_OF_BOARD=y
> > +CONFIG_OF_PRIOR_STAGE=y
> >  CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
> >  CONFIG_ENV_IS_IN_SPI_FLASH=y
> >  CONFIG_NET_RANDOM_ETHADDR=y
>
> Regards,
> Bin

[U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable

[Rick Chen]

Hi Bin

Bin Meng <bmeng.cn@gmail.com> 於 2019年4月23日 週二 下午8:19寫道：
>
> On Tue, Apr 23, 2019 at 8:14 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Rick,
> >
> > On Tue, Apr 23, 2019 at 1:47 PM Andes <uboot@andestech.com> wrote:
> > >
> > > From: Rick Chen <rick@andestech.com>
> > >
> >
> > typo in the commit title: seletable -> selectable

OK

> >
> > > In smp flow this two features only can be enabled when U-Boot
> >
> > this->these

OK

> >
> > > boot from ram. It shall be disabled when U-Boot boot from flash.
> >
> > boot->boots

OK

> >
> > >
> > > Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select
>
> BTW: is it possible to use a single option for such feature, like
> CONFIG_XIP? Basically these two options are used for the same reason.

Yes. This is my initial idea. But I worry the connection seem a little weak.
But if you say so, I will do it as you say.

Thanks
Rick

>
> > > this two features. Their default value will say YES for booting
> >
> > this->these
> >
> > > from ram.
>
> Regards,
> Bin

[U-Boot] [PATCH 0/4] AE350 support SMP boot from flash

[Auer, Lukas]

Hi Rick,

On Wed, 2019-04-24 at 09:35 +0800, Rick Chen wrote:
> Hi Lukas
> 
> Auer, Lukas <lukas.auer@aisec.fraunhofer.de> 於 2019年4月24日 週三 上午3:58寫道：
> > Hi Rick,
> > 
> > On Tue, 2019-04-23 at 13:42 +0800, Andes wrote:
> > > From: Rick Chen <rick@andestech.com>
> > > 
> > > In current RISC-V SMP flow, AE350 will encounter the the write
> > > failure problem since hart_lottery and available_harts_lock was
> > > not in ram address but in flash address when booing from flash.
> > > 
> > > This patch can help to fix the failure problem when AE350 was
> > > booting from flash by disable this two features.
> > > 
> > 
> > Can you describe the issue you are seeing a bit more. The write
> > failures are both to variables in the .data section, which should be
> > writable. Perhaps the write failures can be avoided by moving the .data
> > section or just the variable to RAM?
> > 
> 
> When I compile AE350's CONFIG_SYS_TEXT_BASE=0x80000000 which is spi flash base.
> And burn u-boot.bin into AE350 spi flash. Power off / on, U-Boot will
> run in XIP mode.
> At this time prior_stage_fdt_address will be in flash address(0x8004e9e8)
> So it is not writable.
> 
> 80000042:       16021563                bnez    tp,800001ac
> <secondary_hart_loop>
> 80000046:       0004f297                auipc   t0,0x4f
> 8000004a:       9a22a283                lw      t0,-1630(t0) #
> 8004e9e8 <prior_stage_fdt_address+0x3f74>
> 8000004e:       0092a023                sw      s1,0(t0)
> 

Ok, that makes sense.
Another option would be to move the variable to RAM or some other
location, which is write-accessible when U-Boot starts. Would this
work?
I think it would be good to support the hart lottery and the available
harts mask in all configurations.

Thanks,
Lukas

[U-Boot] [PATCH 0/4] AE350 support SMP boot from flash

[Rick Chen]

Hi Lukas

Auer, Lukas <lukas.auer@aisec.fraunhofer.de> 於 2019年4月25日 週四 上午5:18寫道：
>
> Hi Rick,
>
> On Wed, 2019-04-24 at 09:35 +0800, Rick Chen wrote:
> > Hi Lukas
> >
> > Auer, Lukas <lukas.auer@aisec.fraunhofer.de> 於 2019年4月24日 週三 上午3:58寫道：
> > > Hi Rick,
> > >
> > > On Tue, 2019-04-23 at 13:42 +0800, Andes wrote:
> > > > From: Rick Chen <rick@andestech.com>
> > > >
> > > > In current RISC-V SMP flow, AE350 will encounter the the write
> > > > failure problem since hart_lottery and available_harts_lock was
> > > > not in ram address but in flash address when booing from flash.
> > > >
> > > > This patch can help to fix the failure problem when AE350 was
> > > > booting from flash by disable this two features.
> > > >
> > >
> > > Can you describe the issue you are seeing a bit more. The write
> > > failures are both to variables in the .data section, which should be
> > > writable. Perhaps the write failures can be avoided by moving the .data
> > > section or just the variable to RAM?
> > >
> >
> > When I compile AE350's CONFIG_SYS_TEXT_BASE=0x80000000 which is spi flash base.
> > And burn u-boot.bin into AE350 spi flash. Power off / on, U-Boot will
> > run in XIP mode.
> > At this time prior_stage_fdt_address will be in flash address(0x8004e9e8)
> > So it is not writable.
> >
> > 80000042:       16021563                bnez    tp,800001ac
> > <secondary_hart_loop>
> > 80000046:       0004f297                auipc   t0,0x4f
> > 8000004a:       9a22a283                lw      t0,-1630(t0) #
> > 8004e9e8 <prior_stage_fdt_address+0x3f74>
> > 8000004e:       0092a023                sw      s1,0(t0)
> >
>
> Ok, that makes sense.
> Another option would be to move the variable to RAM or some other
> location, which is write-accessible when U-Boot starts. Would this
> work?
> I think it would be good to support the hart lottery and the available
> harts mask in all configurations.
>

Actually I have tried to move them to gd, but it fail.
Because it need some requirements :
hart_lottery need equal to 0 and available_harts_lock equal to 1 at
compile time.
It is hard to achieve this at run time.
That is why I add a CONFIG_XXX to remove this two features simply.

Thanks
Rick

> Thanks,
> Lukas

[U-Boot] [PATCH 0/4] AE350 support SMP boot from flash

[Auer, Lukas]

Hi Rick,

On Thu, 2019-04-25 at 08:55 +0800, Rick Chen wrote:
> Hi Lukas
> 
> Auer, Lukas <lukas.auer@aisec.fraunhofer.de> 於 2019年4月25日 週四 上午5:18寫道：
> > Hi Rick,
> > 
> > On Wed, 2019-04-24 at 09:35 +0800, Rick Chen wrote:
> > > Hi Lukas
> > > 
> > > Auer, Lukas <lukas.auer@aisec.fraunhofer.de> 於 2019年4月24日 週三 上午3:58寫道：
> > > > Hi Rick,
> > > > 
> > > > On Tue, 2019-04-23 at 13:42 +0800, Andes wrote:
> > > > > From: Rick Chen <rick@andestech.com>
> > > > > 
> > > > > In current RISC-V SMP flow, AE350 will encounter the the write
> > > > > failure problem since hart_lottery and available_harts_lock was
> > > > > not in ram address but in flash address when booing from flash.
> > > > > 
> > > > > This patch can help to fix the failure problem when AE350 was
> > > > > booting from flash by disable this two features.
> > > > > 
> > > > 
> > > > Can you describe the issue you are seeing a bit more. The write
> > > > failures are both to variables in the .data section, which should be
> > > > writable. Perhaps the write failures can be avoided by moving the .data
> > > > section or just the variable to RAM?
> > > > 
> > > 
> > > When I compile AE350's CONFIG_SYS_TEXT_BASE=0x80000000 which is spi flash base.
> > > And burn u-boot.bin into AE350 spi flash. Power off / on, U-Boot will
> > > run in XIP mode.
> > > At this time prior_stage_fdt_address will be in flash address(0x8004e9e8)
> > > So it is not writable.
> > > 
> > > 80000042:       16021563                bnez    tp,800001ac
> > > <secondary_hart_loop>
> > > 80000046:       0004f297                auipc   t0,0x4f
> > > 8000004a:       9a22a283                lw      t0,-1630(t0) #
> > > 8004e9e8 <prior_stage_fdt_address+0x3f74>
> > > 8000004e:       0092a023                sw      s1,0(t0)
> > > 
> > 
> > Ok, that makes sense.
> > Another option would be to move the variable to RAM or some other
> > location, which is write-accessible when U-Boot starts. Would this
> > work?
> > I think it would be good to support the hart lottery and the available
> > harts mask in all configurations.
> > 
> 
> Actually I have tried to move them to gd, but it fail.
> Because it need some requirements :
> hart_lottery need equal to 0 and available_harts_lock equal to 1 at
> compile time.
> It is hard to achieve this at run time.
> That is why I add a CONFIG_XXX to remove this two features simply.
> 

Ah, you are right. I did not consider that.

Thanks,
Lukas