From: "Shankar, Uma" <uma.shankar@intel.com> To: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>, "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org> Cc: "airlied@linux.ie" <airlied@linux.ie>, "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>, "Sharma, Swati2" <swati2.sharma@intel.com>, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> Subject: RE: [PATCH v4 14/16] drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding Date: Sun, 13 Dec 2020 07:16:33 +0000 [thread overview] Message-ID: <ee4394858c4a4dbd8365caa159297f23@intel.com> (raw) In-Reply-To: <20201208075145.17389-15-ankit.k.nautiyal@intel.com> > -----Original Message----- > From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> > Sent: Tuesday, December 8, 2020 1:22 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>; > airlied@linux.ie; jani.nikula@linux.intel.com; ville.syrjala@linux.intel.com; > Kulkarni, Vandita <vandita.kulkarni@intel.com>; Sharma, Swati2 > <swati2.sharma@intel.com> > Subject: [PATCH v4 14/16] drm/i915/display: Configure PCON for DSC1.1 to > DSC1.2 encoding > > When a source supporting DSC1.1 is connected to DSC1.2 HDMI2.1 sink via DP > HDMI2.1 PCON, the PCON can be configured to decode the > DSC1.1 compressed stream and encode to DSC1.2. It then sends the > DSC1.2 compressed stream to the HDMI2.1 sink. > > This patch configures the PCON for DSC1.1 to DSC1.2 encoding, based on the > PCON's DSC encoder capablities and HDMI2.1 sink's DSC decoder capabilities. > > v2: Addressed review comments from Uma Shankar: > -fixed the error in packing pps parameter values -added check for pcon in the > pcon related function -appended display in commit message Looks good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 117 ++++++++++++++++++++++- > drivers/gpu/drm/i915/display/intel_dp.h | 2 + > 3 files changed, 118 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 3ff8b18f1997..721a47bbc009 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3653,6 +3653,7 @@ static void tgl_ddi_pre_enable_dp(struct > intel_atomic_state *state, > intel_dp_sink_set_fec_ready(intel_dp, crtc_state); > > intel_dp_check_frl_training(intel_dp, crtc_state); > + intel_dp_pcon_dsc_configure(intel_dp, crtc_state); > > /* > * 7.i Follow DisplayPort specification training sequence (see notes for > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 4dd272a34ee8..30c76ba63232 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4039,9 +4039,21 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp > *intel_dp) { > struct intel_connector *intel_connector = intel_dp->attached_connector; > struct drm_connector *connector = &intel_connector->base; > + int max_frl_rate; > + int max_lanes, rate_per_lane; > + int max_dsc_lanes, dsc_rate_per_lane; > > - return (connector->display_info.hdmi.max_frl_rate_per_lane * > - connector->display_info.hdmi.max_lanes); > + max_lanes = connector->display_info.hdmi.max_lanes; > + rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane; > + max_frl_rate = max_lanes * rate_per_lane; > + > + if (connector->display_info.hdmi.dsc_cap.v_1p2) { > + max_dsc_lanes = connector- > >display_info.hdmi.dsc_cap.max_lanes; > + dsc_rate_per_lane = connector- > >display_info.hdmi.dsc_cap.max_frl_rate_per_lane; > + max_frl_rate = min(max_frl_rate, max_dsc_lanes * > dsc_rate_per_lane); > + } > + > + return max_frl_rate; > } > > static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) @@ - > 4171,6 +4183,105 @@ void intel_dp_check_frl_training(struct intel_dp *intel_dp, > } > } > > +static int > +intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state > +*crtc_state) { > + > + int vactive = crtc_state->hw.adjusted_mode.vdisplay; > + > + return intel_hdmi_dsc_get_slice_height(vactive); > +} > + > +static int > +intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp, > + const struct intel_crtc_state *crtc_state) { > + struct intel_connector *intel_connector = intel_dp->attached_connector; > + struct drm_connector *connector = &intel_connector->base; > + int hdmi_throughput = connector- > >display_info.hdmi.dsc_cap.clk_per_slice; > + int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices; > + int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp- > >pcon_dsc_dpcd); > + int pcon_max_slice_width = > +drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); > + > + > + return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices, > + pcon_max_slice_width, > + hdmi_max_slices, hdmi_throughput); } > + > +static int > +intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp, > + const struct intel_crtc_state *crtc_state, > + int num_slices, int slice_width) > +{ > + struct intel_connector *intel_connector = intel_dp->attached_connector; > + struct drm_connector *connector = &intel_connector->base; > + int output_format = crtc_state->output_format; > + bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp; > + int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp- > >pcon_dsc_dpcd); > + int hdmi_max_chunk_bytes = > + connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * > 1024; > + > + return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, > + num_slices, output_format, hdmi_all_bpp, > + hdmi_max_chunk_bytes); > +} > + > +void > +intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, > + const struct intel_crtc_state *crtc_state) { > + u8 pps_param[6]; > + int slice_height; > + int slice_width; > + int num_slices; > + int bits_per_pixel; > + int ret; > + struct intel_connector *intel_connector = intel_dp->attached_connector; > + struct drm_i915_private *i915 = dp_to_i915(intel_dp); > + struct drm_connector *connector; > + bool hdmi_is_dsc_1_2; > + > + if (!intel_dp_is_hdmi_2_1_sink(intel_dp)) > + return; > + > + if (!intel_connector) > + return; > + connector = &intel_connector->base; > + hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2; > + > + if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || > + !hdmi_is_dsc_1_2) > + return; > + > + slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state); > + if (!slice_height) > + return; > + > + num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state); > + if (!num_slices) > + return; > + > + slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, > + num_slices); > + > + bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state, > + num_slices, slice_width); > + if (!bits_per_pixel) > + return; > + > + pps_param[0] = slice_height & 0xFF; > + pps_param[1] = slice_height >> 8; > + pps_param[2] = slice_width & 0xFF; > + pps_param[3] = slice_width >> 8; > + pps_param[4] = bits_per_pixel & 0xFF; > + pps_param[5] = (bits_per_pixel >> 8) & 0x3; > + > + ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); > + if (ret < 0) > + drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n"); } > + > static void > g4x_set_link_train(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state, @@ -4302,6 +4413,7 > @@ static void intel_enable_dp(struct intel_atomic_state *state, > intel_dp_set_power(intel_dp, DP_SET_POWER_D0); > intel_dp_configure_protocol_converter(intel_dp); > intel_dp_check_frl_training(intel_dp, pipe_config); > + intel_dp_pcon_dsc_configure(intel_dp, pipe_config); > intel_dp_start_link_train(intel_dp, pipe_config); > intel_dp_stop_link_train(intel_dp, pipe_config); > > @@ -6261,6 +6373,7 @@ int intel_dp_retrain_link(struct intel_encoder > *encoder, > continue; > > intel_dp_check_frl_training(intel_dp, crtc_state); > + intel_dp_pcon_dsc_configure(intel_dp, crtc_state); > intel_dp_start_link_train(intel_dp, crtc_state); > intel_dp_stop_link_train(intel_dp, crtc_state); > break; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h > b/drivers/gpu/drm/i915/display/intel_dp.h > index b4a14646caea..9bba920b8197 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -146,5 +146,7 @@ void intel_dp_sync_state(struct intel_encoder *encoder, > > void intel_dp_check_frl_training(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state); > +void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, > + const struct intel_crtc_state *crtc_state); > > #endif /* __INTEL_DP_H__ */ > -- > 2.17.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: "Shankar, Uma" <uma.shankar@intel.com> To: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>, "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org> Cc: "airlied@linux.ie" <airlied@linux.ie>, "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org> Subject: Re: [Intel-gfx] [PATCH v4 14/16] drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding Date: Sun, 13 Dec 2020 07:16:33 +0000 [thread overview] Message-ID: <ee4394858c4a4dbd8365caa159297f23@intel.com> (raw) In-Reply-To: <20201208075145.17389-15-ankit.k.nautiyal@intel.com> > -----Original Message----- > From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> > Sent: Tuesday, December 8, 2020 1:22 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>; > airlied@linux.ie; jani.nikula@linux.intel.com; ville.syrjala@linux.intel.com; > Kulkarni, Vandita <vandita.kulkarni@intel.com>; Sharma, Swati2 > <swati2.sharma@intel.com> > Subject: [PATCH v4 14/16] drm/i915/display: Configure PCON for DSC1.1 to > DSC1.2 encoding > > When a source supporting DSC1.1 is connected to DSC1.2 HDMI2.1 sink via DP > HDMI2.1 PCON, the PCON can be configured to decode the > DSC1.1 compressed stream and encode to DSC1.2. It then sends the > DSC1.2 compressed stream to the HDMI2.1 sink. > > This patch configures the PCON for DSC1.1 to DSC1.2 encoding, based on the > PCON's DSC encoder capablities and HDMI2.1 sink's DSC decoder capabilities. > > v2: Addressed review comments from Uma Shankar: > -fixed the error in packing pps parameter values -added check for pcon in the > pcon related function -appended display in commit message Looks good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 117 ++++++++++++++++++++++- > drivers/gpu/drm/i915/display/intel_dp.h | 2 + > 3 files changed, 118 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 3ff8b18f1997..721a47bbc009 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3653,6 +3653,7 @@ static void tgl_ddi_pre_enable_dp(struct > intel_atomic_state *state, > intel_dp_sink_set_fec_ready(intel_dp, crtc_state); > > intel_dp_check_frl_training(intel_dp, crtc_state); > + intel_dp_pcon_dsc_configure(intel_dp, crtc_state); > > /* > * 7.i Follow DisplayPort specification training sequence (see notes for > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 4dd272a34ee8..30c76ba63232 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4039,9 +4039,21 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp > *intel_dp) { > struct intel_connector *intel_connector = intel_dp->attached_connector; > struct drm_connector *connector = &intel_connector->base; > + int max_frl_rate; > + int max_lanes, rate_per_lane; > + int max_dsc_lanes, dsc_rate_per_lane; > > - return (connector->display_info.hdmi.max_frl_rate_per_lane * > - connector->display_info.hdmi.max_lanes); > + max_lanes = connector->display_info.hdmi.max_lanes; > + rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane; > + max_frl_rate = max_lanes * rate_per_lane; > + > + if (connector->display_info.hdmi.dsc_cap.v_1p2) { > + max_dsc_lanes = connector- > >display_info.hdmi.dsc_cap.max_lanes; > + dsc_rate_per_lane = connector- > >display_info.hdmi.dsc_cap.max_frl_rate_per_lane; > + max_frl_rate = min(max_frl_rate, max_dsc_lanes * > dsc_rate_per_lane); > + } > + > + return max_frl_rate; > } > > static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) @@ - > 4171,6 +4183,105 @@ void intel_dp_check_frl_training(struct intel_dp *intel_dp, > } > } > > +static int > +intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state > +*crtc_state) { > + > + int vactive = crtc_state->hw.adjusted_mode.vdisplay; > + > + return intel_hdmi_dsc_get_slice_height(vactive); > +} > + > +static int > +intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp, > + const struct intel_crtc_state *crtc_state) { > + struct intel_connector *intel_connector = intel_dp->attached_connector; > + struct drm_connector *connector = &intel_connector->base; > + int hdmi_throughput = connector- > >display_info.hdmi.dsc_cap.clk_per_slice; > + int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices; > + int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp- > >pcon_dsc_dpcd); > + int pcon_max_slice_width = > +drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); > + > + > + return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices, > + pcon_max_slice_width, > + hdmi_max_slices, hdmi_throughput); } > + > +static int > +intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp, > + const struct intel_crtc_state *crtc_state, > + int num_slices, int slice_width) > +{ > + struct intel_connector *intel_connector = intel_dp->attached_connector; > + struct drm_connector *connector = &intel_connector->base; > + int output_format = crtc_state->output_format; > + bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp; > + int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp- > >pcon_dsc_dpcd); > + int hdmi_max_chunk_bytes = > + connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * > 1024; > + > + return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, > + num_slices, output_format, hdmi_all_bpp, > + hdmi_max_chunk_bytes); > +} > + > +void > +intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, > + const struct intel_crtc_state *crtc_state) { > + u8 pps_param[6]; > + int slice_height; > + int slice_width; > + int num_slices; > + int bits_per_pixel; > + int ret; > + struct intel_connector *intel_connector = intel_dp->attached_connector; > + struct drm_i915_private *i915 = dp_to_i915(intel_dp); > + struct drm_connector *connector; > + bool hdmi_is_dsc_1_2; > + > + if (!intel_dp_is_hdmi_2_1_sink(intel_dp)) > + return; > + > + if (!intel_connector) > + return; > + connector = &intel_connector->base; > + hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2; > + > + if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || > + !hdmi_is_dsc_1_2) > + return; > + > + slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state); > + if (!slice_height) > + return; > + > + num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state); > + if (!num_slices) > + return; > + > + slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, > + num_slices); > + > + bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state, > + num_slices, slice_width); > + if (!bits_per_pixel) > + return; > + > + pps_param[0] = slice_height & 0xFF; > + pps_param[1] = slice_height >> 8; > + pps_param[2] = slice_width & 0xFF; > + pps_param[3] = slice_width >> 8; > + pps_param[4] = bits_per_pixel & 0xFF; > + pps_param[5] = (bits_per_pixel >> 8) & 0x3; > + > + ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); > + if (ret < 0) > + drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n"); } > + > static void > g4x_set_link_train(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state, @@ -4302,6 +4413,7 > @@ static void intel_enable_dp(struct intel_atomic_state *state, > intel_dp_set_power(intel_dp, DP_SET_POWER_D0); > intel_dp_configure_protocol_converter(intel_dp); > intel_dp_check_frl_training(intel_dp, pipe_config); > + intel_dp_pcon_dsc_configure(intel_dp, pipe_config); > intel_dp_start_link_train(intel_dp, pipe_config); > intel_dp_stop_link_train(intel_dp, pipe_config); > > @@ -6261,6 +6373,7 @@ int intel_dp_retrain_link(struct intel_encoder > *encoder, > continue; > > intel_dp_check_frl_training(intel_dp, crtc_state); > + intel_dp_pcon_dsc_configure(intel_dp, crtc_state); > intel_dp_start_link_train(intel_dp, crtc_state); > intel_dp_stop_link_train(intel_dp, crtc_state); > break; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h > b/drivers/gpu/drm/i915/display/intel_dp.h > index b4a14646caea..9bba920b8197 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -146,5 +146,7 @@ void intel_dp_sync_state(struct intel_encoder *encoder, > > void intel_dp_check_frl_training(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state); > +void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, > + const struct intel_crtc_state *crtc_state); > > #endif /* __INTEL_DP_H__ */ > -- > 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-12-13 7:16 UTC|newest] Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-08 7:51 [PATCH v4 00/16] Add support for DP-HDMI2.1 PCON Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-08 7:51 ` [PATCH v4 01/16] drm/edid: Add additional HFVSDB fields for HDMI2.1 Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-08 7:51 ` [PATCH v4 02/16] drm/edid: Parse MAX_FRL field from HFVSDB block Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-08 7:51 ` [PATCH v4 03/16] drm/edid: Parse DSC1.2 cap fields " Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-08 7:51 ` [PATCH v4 04/16] drm/dp_helper: Add Helpers for FRL Link Training support for DP-HDMI2.1 PCON Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-08 7:51 ` [PATCH v4 05/16] drm/dp_helper: Add support for link failure detection Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-08 7:51 ` [PATCH v4 06/16] drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-08 7:51 ` [PATCH v4 07/16] drm/dp_helper: Add helpers to configure PCONs RGB-YCbCr Conversion Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-09 17:50 ` Dan Carpenter 2020-12-09 17:50 ` Dan Carpenter 2020-12-09 17:50 ` Dan Carpenter 2020-12-09 17:50 ` [Intel-gfx] " Dan Carpenter 2020-12-10 12:20 ` Nautiyal, Ankit K 2020-12-10 12:20 ` Nautiyal, Ankit K 2020-12-10 12:20 ` [Intel-gfx] " Nautiyal, Ankit K 2020-12-13 7:10 ` Shankar, Uma 2020-12-13 7:10 ` [Intel-gfx] " Shankar, Uma 2020-12-14 13:17 ` Nautiyal, Ankit K 2020-12-14 13:17 ` [Intel-gfx] " Nautiyal, Ankit K 2020-12-08 7:51 ` [PATCH v4 08/16] drm/i915: Capture max frl rate for PCON in dfp cap structure Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-08 7:51 ` [PATCH v4 09/16] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-08 7:51 ` [PATCH v4 10/16] drm/i915: Check for FRL training before DP Link training Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-08 7:51 ` [PATCH v4 11/16] drm/i915: Add support for enabling link status and recovery Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-08 7:51 ` [PATCH v4 12/16] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-08 7:51 ` [PATCH v4 13/16] drm/i915: Add helper functions for calculating DSC parameters for HDMI2.1 Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-13 7:13 ` Shankar, Uma 2020-12-13 7:13 ` [Intel-gfx] " Shankar, Uma 2020-12-08 7:51 ` [PATCH v4 14/16] drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-13 7:16 ` Shankar, Uma [this message] 2020-12-13 7:16 ` Shankar, Uma 2020-12-08 7:51 ` [PATCH v4 15/16] drm/i915: Let PCON convert from RGB to YUV if it can Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-13 7:23 ` Shankar, Uma 2020-12-13 7:23 ` [Intel-gfx] " Shankar, Uma 2020-12-14 13:27 ` Nautiyal, Ankit K 2020-12-14 13:27 ` [Intel-gfx] " Nautiyal, Ankit K 2020-12-08 7:51 ` [PATCH v4 16/16] drm/i915: Enable PCON configuration for Color Conversion for TGL Ankit Nautiyal 2020-12-08 7:51 ` [Intel-gfx] " Ankit Nautiyal 2020-12-13 7:29 ` Shankar, Uma 2020-12-13 7:29 ` [Intel-gfx] " Shankar, Uma 2020-12-14 13:51 ` Nautiyal, Ankit K 2020-12-14 13:51 ` [Intel-gfx] " Nautiyal, Ankit K 2020-12-08 8:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON (rev6) Patchwork 2020-12-08 8:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2020-12-08 8:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-12-08 9:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2020-12-08 10:33 ` [PATCH v4 00/16] Add support for DP-HDMI2.1 PCON Jani Nikula 2020-12-08 10:33 ` [Intel-gfx] " Jani Nikula
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