* [PATCH v2 0/7] add support for SAM9X60 pin controller
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, Claudiu.Beznea, linux-kernel, linux-arm-kernel, devicetree
From: Claudiu Beznea <claudiu.beznea@microchip.com>
This series adds drive strenght and slew rate support for SAMX60's pin
controller. For drive strenght we could have 2 values: low, high.
For slew rate we could have 2 values: enable, disabled.
Besides this I took the chance and adapt the documentation for at91 pinctrl
driver.
Changes in v2:
- s/microchip,sam9x60-pictrl/microchip,sam9x60-pinctrl in patches 3/7, 5/7
Claudiu Beznea (7):
pinctrl: at91: add option to use drive strength bits
pinctrl: at91: add drive strength support for SAM9X60
pinctrl: at91: add compatibles for SAM9X60 pin controller
dt-bindings: add documentation for banks
dt-bindings: add bindings for SAM9X60
pinctrl: at91: add slewrate support for SAM9X60
dt-bindings: add documentation for slew rate
.../bindings/pinctrl/atmel,at91-pinctrl.txt | 27 ++++-
drivers/pinctrl/pinctrl-at91.c | 134 +++++++++++++++++++--
drivers/pinctrl/pinctrl-at91.h | 3 +
include/dt-bindings/pinctrl/at91.h | 4 +
4 files changed, 155 insertions(+), 13 deletions(-)
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 0/7] add support for SAM9X60 pin controller
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
This series adds drive strenght and slew rate support for SAMX60's pin
controller. For drive strenght we could have 2 values: low, high.
For slew rate we could have 2 values: enable, disabled.
Besides this I took the chance and adapt the documentation for at91 pinctrl
driver.
Changes in v2:
- s/microchip,sam9x60-pictrl/microchip,sam9x60-pinctrl in patches 3/7, 5/7
Claudiu Beznea (7):
pinctrl: at91: add option to use drive strength bits
pinctrl: at91: add drive strength support for SAM9X60
pinctrl: at91: add compatibles for SAM9X60 pin controller
dt-bindings: add documentation for banks
dt-bindings: add bindings for SAM9X60
pinctrl: at91: add slewrate support for SAM9X60
dt-bindings: add documentation for slew rate
.../bindings/pinctrl/atmel,at91-pinctrl.txt | 27 ++++-
drivers/pinctrl/pinctrl-at91.c | 134 +++++++++++++++++++--
drivers/pinctrl/pinctrl-at91.h | 3 +
include/dt-bindings/pinctrl/at91.h | 4 +
4 files changed, 155 insertions(+), 13 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
2019-01-31 16:18 ` Claudiu.Beznea
(?)
@ 2019-01-31 16:18 ` Claudiu.Beznea
-1 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
SAM9X60 uses high and low drive strengths. To implement this, in
at91_pinctrl_mux_ops::set_drivestrength and
at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
drive strengths (1 for low, 2 for high), thus change the code to
allow the usage of drive strength bit numbers.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 3d49bbbcdbc7..31f06dafca2e 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -72,10 +72,15 @@ static int gpio_banks;
* DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
* strength when there is no dt config for it.
*/
-#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
+enum drive_strength_bit {
+ DRIVE_STRENGTH_BIT_DEF,
+ DRIVE_STRENGTH_BIT_LOW,
+ DRIVE_STRENGTH_BIT_MED,
+ DRIVE_STRENGTH_BIT_HI,
+};
+
+#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
+ DRIVE_STRENGTH_SHIFT)
/**
* struct at91_pmx_func - describes AT91 pinmux functions
@@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
/* SAMA5 strength is 1:1 with our defines,
* except 0 is equivalent to low per datasheet */
if (!tmp)
- tmp = DRIVE_STRENGTH_LOW;
+ tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
return tmp;
}
@@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
/* strength is inverse in SAM9x5s hardware with the pinctrl defines
* hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
- tmp = DRIVE_STRENGTH_HI - tmp;
+ tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
return tmp;
}
@@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
/* strength is inverse on SAM9x5s with our defines
* 0 = hi, 1 = med, 2 = low, 3 = rsvd */
- setting = DRIVE_STRENGTH_HI - setting;
+ setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
setting);
@@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
} \
} while (0)
-#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
+#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
if ((config & mask) == flag) { \
if (num_conf) \
seq_puts(s, "|"); \
- seq_puts(s, #flag); \
+ seq_puts(s, #name); \
num_conf++; \
} \
} while (0)
@@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
DBG_SHOW_FLAG(PULL_DOWN);
DBG_SHOW_FLAG(DIS_SCHMIT);
DBG_SHOW_FLAG(DEGLITCH);
- DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
- DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
- DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
+ DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
+ DRIVE_STRENGTH_LOW);
+ DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
+ DRIVE_STRENGTH_MED);
+ DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
+ DRIVE_STRENGTH_HI);
DBG_SHOW_FLAG(DEBOUNCE);
if (config & DEBOUNCE) {
val = config >> DEBOUNCE_VAL_SHIFT;
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, Claudiu.Beznea, linux-kernel, linux-arm-kernel, devicetree
From: Claudiu Beznea <claudiu.beznea@microchip.com>
SAM9X60 uses high and low drive strengths. To implement this, in
at91_pinctrl_mux_ops::set_drivestrength and
at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
drive strengths (1 for low, 2 for high), thus change the code to
allow the usage of drive strength bit numbers.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 3d49bbbcdbc7..31f06dafca2e 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -72,10 +72,15 @@ static int gpio_banks;
* DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
* strength when there is no dt config for it.
*/
-#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
+enum drive_strength_bit {
+ DRIVE_STRENGTH_BIT_DEF,
+ DRIVE_STRENGTH_BIT_LOW,
+ DRIVE_STRENGTH_BIT_MED,
+ DRIVE_STRENGTH_BIT_HI,
+};
+
+#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
+ DRIVE_STRENGTH_SHIFT)
/**
* struct at91_pmx_func - describes AT91 pinmux functions
@@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
/* SAMA5 strength is 1:1 with our defines,
* except 0 is equivalent to low per datasheet */
if (!tmp)
- tmp = DRIVE_STRENGTH_LOW;
+ tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
return tmp;
}
@@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
/* strength is inverse in SAM9x5s hardware with the pinctrl defines
* hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
- tmp = DRIVE_STRENGTH_HI - tmp;
+ tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
return tmp;
}
@@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
/* strength is inverse on SAM9x5s with our defines
* 0 = hi, 1 = med, 2 = low, 3 = rsvd */
- setting = DRIVE_STRENGTH_HI - setting;
+ setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
setting);
@@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
} \
} while (0)
-#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
+#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
if ((config & mask) == flag) { \
if (num_conf) \
seq_puts(s, "|"); \
- seq_puts(s, #flag); \
+ seq_puts(s, #name); \
num_conf++; \
} \
} while (0)
@@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
DBG_SHOW_FLAG(PULL_DOWN);
DBG_SHOW_FLAG(DIS_SCHMIT);
DBG_SHOW_FLAG(DEGLITCH);
- DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
- DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
- DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
+ DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
+ DRIVE_STRENGTH_LOW);
+ DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
+ DRIVE_STRENGTH_MED);
+ DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
+ DRIVE_STRENGTH_HI);
DBG_SHOW_FLAG(DEBOUNCE);
if (config & DEBOUNCE) {
val = config >> DEBOUNCE_VAL_SHIFT;
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
SAM9X60 uses high and low drive strengths. To implement this, in
at91_pinctrl_mux_ops::set_drivestrength and
at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
drive strengths (1 for low, 2 for high), thus change the code to
allow the usage of drive strength bit numbers.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 3d49bbbcdbc7..31f06dafca2e 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -72,10 +72,15 @@ static int gpio_banks;
* DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
* strength when there is no dt config for it.
*/
-#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
+enum drive_strength_bit {
+ DRIVE_STRENGTH_BIT_DEF,
+ DRIVE_STRENGTH_BIT_LOW,
+ DRIVE_STRENGTH_BIT_MED,
+ DRIVE_STRENGTH_BIT_HI,
+};
+
+#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
+ DRIVE_STRENGTH_SHIFT)
/**
* struct at91_pmx_func - describes AT91 pinmux functions
@@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
/* SAMA5 strength is 1:1 with our defines,
* except 0 is equivalent to low per datasheet */
if (!tmp)
- tmp = DRIVE_STRENGTH_LOW;
+ tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
return tmp;
}
@@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
/* strength is inverse in SAM9x5s hardware with the pinctrl defines
* hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
- tmp = DRIVE_STRENGTH_HI - tmp;
+ tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
return tmp;
}
@@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
/* strength is inverse on SAM9x5s with our defines
* 0 = hi, 1 = med, 2 = low, 3 = rsvd */
- setting = DRIVE_STRENGTH_HI - setting;
+ setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
setting);
@@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
} \
} while (0)
-#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
+#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
if ((config & mask) == flag) { \
if (num_conf) \
seq_puts(s, "|"); \
- seq_puts(s, #flag); \
+ seq_puts(s, #name); \
num_conf++; \
} \
} while (0)
@@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
DBG_SHOW_FLAG(PULL_DOWN);
DBG_SHOW_FLAG(DIS_SCHMIT);
DBG_SHOW_FLAG(DEGLITCH);
- DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
- DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
- DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
+ DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
+ DRIVE_STRENGTH_LOW);
+ DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
+ DRIVE_STRENGTH_MED);
+ DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
+ DRIVE_STRENGTH_HI);
DBG_SHOW_FLAG(DEBOUNCE);
if (config & DEBOUNCE) {
val = config >> DEBOUNCE_VAL_SHIFT;
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
2019-01-31 16:18 ` Claudiu.Beznea
(?)
@ 2019-02-06 8:13 ` Ludovic Desroches
-1 siblings, 0 replies; 39+ messages in thread
From: Ludovic Desroches @ 2019-02-06 8:13 UTC (permalink / raw)
To: Claudiu Beznea - M18063
Cc: linus.walleij, robh+dt, mark.rutland, Nicolas Ferre - M43238,
alexandre.belloni, linux-gpio, devicetree, linux-arm-kernel,
linux-kernel
On Thu, Jan 31, 2019 at 05:18:04PM +0100, Claudiu Beznea - M18063 wrote:
> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>
> SAM9X60 uses high and low drive strengths. To implement this, in
> at91_pinctrl_mux_ops::set_drivestrength and
> at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
> drive strengths (1 for low, 2 for high), thus change the code to
> allow the usage of drive strength bit numbers.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
> 1 file changed, 20 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> index 3d49bbbcdbc7..31f06dafca2e 100644
> --- a/drivers/pinctrl/pinctrl-at91.c
> +++ b/drivers/pinctrl/pinctrl-at91.c
> @@ -72,10 +72,15 @@ static int gpio_banks;
> * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
> * strength when there is no dt config for it.
> */
> -#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
> -#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
> -#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
> -#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
> +enum drive_strength_bit {
> + DRIVE_STRENGTH_BIT_DEF,
> + DRIVE_STRENGTH_BIT_LOW,
> + DRIVE_STRENGTH_BIT_MED,
> + DRIVE_STRENGTH_BIT_HI,
> +};
> +
> +#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
> + DRIVE_STRENGTH_SHIFT)
>
> /**
> * struct at91_pmx_func - describes AT91 pinmux functions
> @@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
> /* SAMA5 strength is 1:1 with our defines,
> * except 0 is equivalent to low per datasheet */
> if (!tmp)
> - tmp = DRIVE_STRENGTH_LOW;
> + tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
>
> return tmp;
> }
> @@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
>
> /* strength is inverse in SAM9x5s hardware with the pinctrl defines
> * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
> - tmp = DRIVE_STRENGTH_HI - tmp;
> + tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
>
> return tmp;
> }
> @@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
>
> /* strength is inverse on SAM9x5s with our defines
> * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
> - setting = DRIVE_STRENGTH_HI - setting;
> + setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
>
> set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
> setting);
> @@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
> } \
> } while (0)
>
> -#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
> +#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
checkpatch error: space required
> if ((config & mask) == flag) { \
> if (num_conf) \
> seq_puts(s, "|"); \
> - seq_puts(s, #flag); \
> + seq_puts(s, #name); \
> num_conf++; \
> } \
> } while (0)
> @@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
> DBG_SHOW_FLAG(PULL_DOWN);
> DBG_SHOW_FLAG(DIS_SCHMIT);
> DBG_SHOW_FLAG(DEGLITCH);
> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
> + DRIVE_STRENGTH_LOW);
> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
> + DRIVE_STRENGTH_MED);
> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
> + DRIVE_STRENGTH_HI);
> DBG_SHOW_FLAG(DEBOUNCE);
> if (config & DEBOUNCE) {
> val = config >> DEBOUNCE_VAL_SHIFT;
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
@ 2019-02-06 8:13 ` Ludovic Desroches
0 siblings, 0 replies; 39+ messages in thread
From: Ludovic Desroches @ 2019-02-06 8:13 UTC (permalink / raw)
To: Claudiu Beznea - M18063
Cc: mark.rutland, devicetree, alexandre.belloni, linus.walleij,
linux-kernel, linux-gpio, robh+dt, linux-arm-kernel
On Thu, Jan 31, 2019 at 05:18:04PM +0100, Claudiu Beznea - M18063 wrote:
> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>
> SAM9X60 uses high and low drive strengths. To implement this, in
> at91_pinctrl_mux_ops::set_drivestrength and
> at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
> drive strengths (1 for low, 2 for high), thus change the code to
> allow the usage of drive strength bit numbers.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
> 1 file changed, 20 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> index 3d49bbbcdbc7..31f06dafca2e 100644
> --- a/drivers/pinctrl/pinctrl-at91.c
> +++ b/drivers/pinctrl/pinctrl-at91.c
> @@ -72,10 +72,15 @@ static int gpio_banks;
> * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
> * strength when there is no dt config for it.
> */
> -#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
> -#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
> -#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
> -#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
> +enum drive_strength_bit {
> + DRIVE_STRENGTH_BIT_DEF,
> + DRIVE_STRENGTH_BIT_LOW,
> + DRIVE_STRENGTH_BIT_MED,
> + DRIVE_STRENGTH_BIT_HI,
> +};
> +
> +#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
> + DRIVE_STRENGTH_SHIFT)
>
> /**
> * struct at91_pmx_func - describes AT91 pinmux functions
> @@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
> /* SAMA5 strength is 1:1 with our defines,
> * except 0 is equivalent to low per datasheet */
> if (!tmp)
> - tmp = DRIVE_STRENGTH_LOW;
> + tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
>
> return tmp;
> }
> @@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
>
> /* strength is inverse in SAM9x5s hardware with the pinctrl defines
> * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
> - tmp = DRIVE_STRENGTH_HI - tmp;
> + tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
>
> return tmp;
> }
> @@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
>
> /* strength is inverse on SAM9x5s with our defines
> * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
> - setting = DRIVE_STRENGTH_HI - setting;
> + setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
>
> set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
> setting);
> @@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
> } \
> } while (0)
>
> -#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
> +#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
checkpatch error: space required
> if ((config & mask) == flag) { \
> if (num_conf) \
> seq_puts(s, "|"); \
> - seq_puts(s, #flag); \
> + seq_puts(s, #name); \
> num_conf++; \
> } \
> } while (0)
> @@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
> DBG_SHOW_FLAG(PULL_DOWN);
> DBG_SHOW_FLAG(DIS_SCHMIT);
> DBG_SHOW_FLAG(DEGLITCH);
> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
> + DRIVE_STRENGTH_LOW);
> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
> + DRIVE_STRENGTH_MED);
> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
> + DRIVE_STRENGTH_HI);
> DBG_SHOW_FLAG(DEBOUNCE);
> if (config & DEBOUNCE) {
> val = config >> DEBOUNCE_VAL_SHIFT;
> --
> 2.7.4
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
@ 2019-02-06 8:13 ` Ludovic Desroches
0 siblings, 0 replies; 39+ messages in thread
From: Ludovic Desroches @ 2019-02-06 8:13 UTC (permalink / raw)
To: Claudiu Beznea - M18063
Cc: linus.walleij, robh+dt, mark.rutland, Nicolas Ferre - M43238,
alexandre.belloni, linux-gpio, devicetree, linux-arm-kernel,
linux-kernel
On Thu, Jan 31, 2019 at 05:18:04PM +0100, Claudiu Beznea - M18063 wrote:
> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>
> SAM9X60 uses high and low drive strengths. To implement this, in
> at91_pinctrl_mux_ops::set_drivestrength and
> at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
> drive strengths (1 for low, 2 for high), thus change the code to
> allow the usage of drive strength bit numbers.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
> 1 file changed, 20 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> index 3d49bbbcdbc7..31f06dafca2e 100644
> --- a/drivers/pinctrl/pinctrl-at91.c
> +++ b/drivers/pinctrl/pinctrl-at91.c
> @@ -72,10 +72,15 @@ static int gpio_banks;
> * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
> * strength when there is no dt config for it.
> */
> -#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
> -#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
> -#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
> -#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
> +enum drive_strength_bit {
> + DRIVE_STRENGTH_BIT_DEF,
> + DRIVE_STRENGTH_BIT_LOW,
> + DRIVE_STRENGTH_BIT_MED,
> + DRIVE_STRENGTH_BIT_HI,
> +};
> +
> +#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
> + DRIVE_STRENGTH_SHIFT)
>
> /**
> * struct at91_pmx_func - describes AT91 pinmux functions
> @@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
> /* SAMA5 strength is 1:1 with our defines,
> * except 0 is equivalent to low per datasheet */
> if (!tmp)
> - tmp = DRIVE_STRENGTH_LOW;
> + tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
>
> return tmp;
> }
> @@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
>
> /* strength is inverse in SAM9x5s hardware with the pinctrl defines
> * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
> - tmp = DRIVE_STRENGTH_HI - tmp;
> + tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
>
> return tmp;
> }
> @@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
>
> /* strength is inverse on SAM9x5s with our defines
> * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
> - setting = DRIVE_STRENGTH_HI - setting;
> + setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
>
> set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
> setting);
> @@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
> } \
> } while (0)
>
> -#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
> +#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
checkpatch error: space required
> if ((config & mask) == flag) { \
> if (num_conf) \
> seq_puts(s, "|"); \
> - seq_puts(s, #flag); \
> + seq_puts(s, #name); \
> num_conf++; \
> } \
> } while (0)
> @@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
> DBG_SHOW_FLAG(PULL_DOWN);
> DBG_SHOW_FLAG(DIS_SCHMIT);
> DBG_SHOW_FLAG(DEGLITCH);
> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
> + DRIVE_STRENGTH_LOW);
> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
> + DRIVE_STRENGTH_MED);
> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
> + DRIVE_STRENGTH_HI);
> DBG_SHOW_FLAG(DEBOUNCE);
> if (config & DEBOUNCE) {
> val = config >> DEBOUNCE_VAL_SHIFT;
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
2019-02-06 8:13 ` Ludovic Desroches
(?)
@ 2019-02-06 9:46 ` Claudiu.Beznea
-1 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-02-06 9:46 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, linux-gpio, devicetree, linux-arm-kernel,
linux-kernel
On 06.02.2019 10:13, Ludovic Desroches wrote:
> On Thu, Jan 31, 2019 at 05:18:04PM +0100, Claudiu Beznea - M18063 wrote:
>> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>>
>> SAM9X60 uses high and low drive strengths. To implement this, in
>> at91_pinctrl_mux_ops::set_drivestrength and
>> at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
>> drive strengths (1 for low, 2 for high), thus change the code to
>> allow the usage of drive strength bit numbers.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>> drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
>> 1 file changed, 20 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
>> index 3d49bbbcdbc7..31f06dafca2e 100644
>> --- a/drivers/pinctrl/pinctrl-at91.c
>> +++ b/drivers/pinctrl/pinctrl-at91.c
>> @@ -72,10 +72,15 @@ static int gpio_banks;
>> * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
>> * strength when there is no dt config for it.
>> */
>> -#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
>> -#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
>> -#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
>> -#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
>> +enum drive_strength_bit {
>> + DRIVE_STRENGTH_BIT_DEF,
>> + DRIVE_STRENGTH_BIT_LOW,
>> + DRIVE_STRENGTH_BIT_MED,
>> + DRIVE_STRENGTH_BIT_HI,
>> +};
>> +
>> +#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
>> + DRIVE_STRENGTH_SHIFT)
>>
>> /**
>> * struct at91_pmx_func - describes AT91 pinmux functions
>> @@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
>> /* SAMA5 strength is 1:1 with our defines,
>> * except 0 is equivalent to low per datasheet */
>> if (!tmp)
>> - tmp = DRIVE_STRENGTH_LOW;
>> + tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
>>
>> return tmp;
>> }
>> @@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
>>
>> /* strength is inverse in SAM9x5s hardware with the pinctrl defines
>> * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
>> - tmp = DRIVE_STRENGTH_HI - tmp;
>> + tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
>>
>> return tmp;
>> }
>> @@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
>>
>> /* strength is inverse on SAM9x5s with our defines
>> * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
>> - setting = DRIVE_STRENGTH_HI - setting;
>> + setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
>>
>> set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
>> setting);
>> @@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
>> } \
>> } while (0)
>>
>> -#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
>> +#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
>
> checkpatch error: space required
I'm aware of that but I added it in the way it was previously (were the
checkpatch error was still present). Please let me know if you want me to
send a new version fixing this.
Thank you,
Claudiu Beznea
>
>> if ((config & mask) == flag) { \
>> if (num_conf) \
>> seq_puts(s, "|"); \
>> - seq_puts(s, #flag); \
>> + seq_puts(s, #name); \
>> num_conf++; \
>> } \
>> } while (0)
>> @@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
>> DBG_SHOW_FLAG(PULL_DOWN);
>> DBG_SHOW_FLAG(DIS_SCHMIT);
>> DBG_SHOW_FLAG(DEGLITCH);
>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
>> + DRIVE_STRENGTH_LOW);
>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
>> + DRIVE_STRENGTH_MED);
>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
>> + DRIVE_STRENGTH_HI);
>> DBG_SHOW_FLAG(DEBOUNCE);
>> if (config & DEBOUNCE) {
>> val = config >> DEBOUNCE_VAL_SHIFT;
>> --
>> 2.7.4
>>
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
@ 2019-02-06 9:46 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-02-06 9:46 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, linux-gpio, devicetree, linux-arm-kernel,
linux-kernel
On 06.02.2019 10:13, Ludovic Desroches wrote:
> On Thu, Jan 31, 2019 at 05:18:04PM +0100, Claudiu Beznea - M18063 wrote:
>> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>>
>> SAM9X60 uses high and low drive strengths. To implement this, in
>> at91_pinctrl_mux_ops::set_drivestrength and
>> at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
>> drive strengths (1 for low, 2 for high), thus change the code to
>> allow the usage of drive strength bit numbers.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>> drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
>> 1 file changed, 20 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
>> index 3d49bbbcdbc7..31f06dafca2e 100644
>> --- a/drivers/pinctrl/pinctrl-at91.c
>> +++ b/drivers/pinctrl/pinctrl-at91.c
>> @@ -72,10 +72,15 @@ static int gpio_banks;
>> * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
>> * strength when there is no dt config for it.
>> */
>> -#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
>> -#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
>> -#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
>> -#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
>> +enum drive_strength_bit {
>> + DRIVE_STRENGTH_BIT_DEF,
>> + DRIVE_STRENGTH_BIT_LOW,
>> + DRIVE_STRENGTH_BIT_MED,
>> + DRIVE_STRENGTH_BIT_HI,
>> +};
>> +
>> +#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
>> + DRIVE_STRENGTH_SHIFT)
>>
>> /**
>> * struct at91_pmx_func - describes AT91 pinmux functions
>> @@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
>> /* SAMA5 strength is 1:1 with our defines,
>> * except 0 is equivalent to low per datasheet */
>> if (!tmp)
>> - tmp = DRIVE_STRENGTH_LOW;
>> + tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
>>
>> return tmp;
>> }
>> @@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
>>
>> /* strength is inverse in SAM9x5s hardware with the pinctrl defines
>> * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
>> - tmp = DRIVE_STRENGTH_HI - tmp;
>> + tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
>>
>> return tmp;
>> }
>> @@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
>>
>> /* strength is inverse on SAM9x5s with our defines
>> * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
>> - setting = DRIVE_STRENGTH_HI - setting;
>> + setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
>>
>> set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
>> setting);
>> @@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
>> } \
>> } while (0)
>>
>> -#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
>> +#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
>
> checkpatch error: space required
I'm aware of that but I added it in the way it was previously (were the
checkpatch error was still present). Please let me know if you want me to
send a new version fixing this.
Thank you,
Claudiu Beznea
>
>> if ((config & mask) == flag) { \
>> if (num_conf) \
>> seq_puts(s, "|"); \
>> - seq_puts(s, #flag); \
>> + seq_puts(s, #name); \
>> num_conf++; \
>> } \
>> } while (0)
>> @@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
>> DBG_SHOW_FLAG(PULL_DOWN);
>> DBG_SHOW_FLAG(DIS_SCHMIT);
>> DBG_SHOW_FLAG(DEGLITCH);
>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
>> + DRIVE_STRENGTH_LOW);
>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
>> + DRIVE_STRENGTH_MED);
>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
>> + DRIVE_STRENGTH_HI);
>> DBG_SHOW_FLAG(DEBOUNCE);
>> if (config & DEBOUNCE) {
>> val = config >> DEBOUNCE_VAL_SHIFT;
>> --
>> 2.7.4
>>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
@ 2019-02-06 9:46 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-02-06 9:46 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, linux-gpio, devicetree, linux-arm-kernel,
linux-kernel
On 06.02.2019 10:13, Ludovic Desroches wrote:
> On Thu, Jan 31, 2019 at 05:18:04PM +0100, Claudiu Beznea - M18063 wrote:
>> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>>
>> SAM9X60 uses high and low drive strengths. To implement this, in
>> at91_pinctrl_mux_ops::set_drivestrength and
>> at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
>> drive strengths (1 for low, 2 for high), thus change the code to
>> allow the usage of drive strength bit numbers.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>> drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
>> 1 file changed, 20 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
>> index 3d49bbbcdbc7..31f06dafca2e 100644
>> --- a/drivers/pinctrl/pinctrl-at91.c
>> +++ b/drivers/pinctrl/pinctrl-at91.c
>> @@ -72,10 +72,15 @@ static int gpio_banks;
>> * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
>> * strength when there is no dt config for it.
>> */
>> -#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
>> -#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
>> -#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
>> -#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
>> +enum drive_strength_bit {
>> + DRIVE_STRENGTH_BIT_DEF,
>> + DRIVE_STRENGTH_BIT_LOW,
>> + DRIVE_STRENGTH_BIT_MED,
>> + DRIVE_STRENGTH_BIT_HI,
>> +};
>> +
>> +#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
>> + DRIVE_STRENGTH_SHIFT)
>>
>> /**
>> * struct at91_pmx_func - describes AT91 pinmux functions
>> @@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
>> /* SAMA5 strength is 1:1 with our defines,
>> * except 0 is equivalent to low per datasheet */
>> if (!tmp)
>> - tmp = DRIVE_STRENGTH_LOW;
>> + tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
>>
>> return tmp;
>> }
>> @@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
>>
>> /* strength is inverse in SAM9x5s hardware with the pinctrl defines
>> * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
>> - tmp = DRIVE_STRENGTH_HI - tmp;
>> + tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
>>
>> return tmp;
>> }
>> @@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
>>
>> /* strength is inverse on SAM9x5s with our defines
>> * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
>> - setting = DRIVE_STRENGTH_HI - setting;
>> + setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
>>
>> set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
>> setting);
>> @@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
>> } \
>> } while (0)
>>
>> -#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
>> +#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
>
> checkpatch error: space required
I'm aware of that but I added it in the way it was previously (were the
checkpatch error was still present). Please let me know if you want me to
send a new version fixing this.
Thank you,
Claudiu Beznea
>
>> if ((config & mask) == flag) { \
>> if (num_conf) \
>> seq_puts(s, "|"); \
>> - seq_puts(s, #flag); \
>> + seq_puts(s, #name); \
>> num_conf++; \
>> } \
>> } while (0)
>> @@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
>> DBG_SHOW_FLAG(PULL_DOWN);
>> DBG_SHOW_FLAG(DIS_SCHMIT);
>> DBG_SHOW_FLAG(DEGLITCH);
>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
>> + DRIVE_STRENGTH_LOW);
>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
>> + DRIVE_STRENGTH_MED);
>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
>> + DRIVE_STRENGTH_HI);
>> DBG_SHOW_FLAG(DEBOUNCE);
>> if (config & DEBOUNCE) {
>> val = config >> DEBOUNCE_VAL_SHIFT;
>> --
>> 2.7.4
>>
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
2019-02-06 9:46 ` Claudiu.Beznea
(?)
@ 2019-02-06 10:24 ` Ludovic Desroches
-1 siblings, 0 replies; 39+ messages in thread
From: Ludovic Desroches @ 2019-02-06 10:24 UTC (permalink / raw)
To: Claudiu.Beznea
Cc: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, linux-gpio, devicetree, linux-arm-kernel,
linux-kernel
On Wed, Feb 06, 2019 at 09:46:28AM +0000, Claudiu.Beznea@microchip.com wrote:
>
>
> On 06.02.2019 10:13, Ludovic Desroches wrote:
> > On Thu, Jan 31, 2019 at 05:18:04PM +0100, Claudiu Beznea - M18063 wrote:
> >> From: Claudiu Beznea <claudiu.beznea@microchip.com>
> >>
> >> SAM9X60 uses high and low drive strengths. To implement this, in
> >> at91_pinctrl_mux_ops::set_drivestrength and
> >> at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
> >> drive strengths (1 for low, 2 for high), thus change the code to
> >> allow the usage of drive strength bit numbers.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> >> ---
> >> drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
> >> 1 file changed, 20 insertions(+), 12 deletions(-)
> >>
> >> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> >> index 3d49bbbcdbc7..31f06dafca2e 100644
> >> --- a/drivers/pinctrl/pinctrl-at91.c
> >> +++ b/drivers/pinctrl/pinctrl-at91.c
> >> @@ -72,10 +72,15 @@ static int gpio_banks;
> >> * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
> >> * strength when there is no dt config for it.
> >> */
> >> -#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
> >> -#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
> >> -#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
> >> -#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
> >> +enum drive_strength_bit {
> >> + DRIVE_STRENGTH_BIT_DEF,
> >> + DRIVE_STRENGTH_BIT_LOW,
> >> + DRIVE_STRENGTH_BIT_MED,
> >> + DRIVE_STRENGTH_BIT_HI,
> >> +};
> >> +
> >> +#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
> >> + DRIVE_STRENGTH_SHIFT)
> >>
> >> /**
> >> * struct at91_pmx_func - describes AT91 pinmux functions
> >> @@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
> >> /* SAMA5 strength is 1:1 with our defines,
> >> * except 0 is equivalent to low per datasheet */
> >> if (!tmp)
> >> - tmp = DRIVE_STRENGTH_LOW;
> >> + tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
> >>
> >> return tmp;
> >> }
> >> @@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
> >>
> >> /* strength is inverse in SAM9x5s hardware with the pinctrl defines
> >> * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
> >> - tmp = DRIVE_STRENGTH_HI - tmp;
> >> + tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
> >>
> >> return tmp;
> >> }
> >> @@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
> >>
> >> /* strength is inverse on SAM9x5s with our defines
> >> * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
> >> - setting = DRIVE_STRENGTH_HI - setting;
> >> + setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
> >>
> >> set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
> >> setting);
> >> @@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
> >> } \
> >> } while (0)
> >>
> >> -#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
> >> +#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
> >
> > checkpatch error: space required
>
> I'm aware of that but I added it in the way it was previously (were the
> checkpatch error was still present). Please let me know if you want me to
> send a new version fixing this.
I think it's the opportunity to fix it. If you can resend a new version
including my ack.
Regards
Ludovic
>
> Thank you,
> Claudiu Beznea
>
> >
> >> if ((config & mask) == flag) { \
> >> if (num_conf) \
> >> seq_puts(s, "|"); \
> >> - seq_puts(s, #flag); \
> >> + seq_puts(s, #name); \
> >> num_conf++; \
> >> } \
> >> } while (0)
> >> @@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
> >> DBG_SHOW_FLAG(PULL_DOWN);
> >> DBG_SHOW_FLAG(DIS_SCHMIT);
> >> DBG_SHOW_FLAG(DEGLITCH);
> >> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
> >> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
> >> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
> >> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
> >> + DRIVE_STRENGTH_LOW);
> >> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
> >> + DRIVE_STRENGTH_MED);
> >> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
> >> + DRIVE_STRENGTH_HI);
> >> DBG_SHOW_FLAG(DEBOUNCE);
> >> if (config & DEBOUNCE) {
> >> val = config >> DEBOUNCE_VAL_SHIFT;
> >> --
> >> 2.7.4
> >>
> >
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
@ 2019-02-06 10:24 ` Ludovic Desroches
0 siblings, 0 replies; 39+ messages in thread
From: Ludovic Desroches @ 2019-02-06 10:24 UTC (permalink / raw)
To: Claudiu.Beznea
Cc: mark.rutland, devicetree, alexandre.belloni, linus.walleij,
linux-kernel, linux-gpio, robh+dt, linux-arm-kernel
On Wed, Feb 06, 2019 at 09:46:28AM +0000, Claudiu.Beznea@microchip.com wrote:
>
>
> On 06.02.2019 10:13, Ludovic Desroches wrote:
> > On Thu, Jan 31, 2019 at 05:18:04PM +0100, Claudiu Beznea - M18063 wrote:
> >> From: Claudiu Beznea <claudiu.beznea@microchip.com>
> >>
> >> SAM9X60 uses high and low drive strengths. To implement this, in
> >> at91_pinctrl_mux_ops::set_drivestrength and
> >> at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
> >> drive strengths (1 for low, 2 for high), thus change the code to
> >> allow the usage of drive strength bit numbers.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> >> ---
> >> drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
> >> 1 file changed, 20 insertions(+), 12 deletions(-)
> >>
> >> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> >> index 3d49bbbcdbc7..31f06dafca2e 100644
> >> --- a/drivers/pinctrl/pinctrl-at91.c
> >> +++ b/drivers/pinctrl/pinctrl-at91.c
> >> @@ -72,10 +72,15 @@ static int gpio_banks;
> >> * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
> >> * strength when there is no dt config for it.
> >> */
> >> -#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
> >> -#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
> >> -#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
> >> -#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
> >> +enum drive_strength_bit {
> >> + DRIVE_STRENGTH_BIT_DEF,
> >> + DRIVE_STRENGTH_BIT_LOW,
> >> + DRIVE_STRENGTH_BIT_MED,
> >> + DRIVE_STRENGTH_BIT_HI,
> >> +};
> >> +
> >> +#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
> >> + DRIVE_STRENGTH_SHIFT)
> >>
> >> /**
> >> * struct at91_pmx_func - describes AT91 pinmux functions
> >> @@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
> >> /* SAMA5 strength is 1:1 with our defines,
> >> * except 0 is equivalent to low per datasheet */
> >> if (!tmp)
> >> - tmp = DRIVE_STRENGTH_LOW;
> >> + tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
> >>
> >> return tmp;
> >> }
> >> @@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
> >>
> >> /* strength is inverse in SAM9x5s hardware with the pinctrl defines
> >> * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
> >> - tmp = DRIVE_STRENGTH_HI - tmp;
> >> + tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
> >>
> >> return tmp;
> >> }
> >> @@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
> >>
> >> /* strength is inverse on SAM9x5s with our defines
> >> * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
> >> - setting = DRIVE_STRENGTH_HI - setting;
> >> + setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
> >>
> >> set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
> >> setting);
> >> @@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
> >> } \
> >> } while (0)
> >>
> >> -#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
> >> +#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
> >
> > checkpatch error: space required
>
> I'm aware of that but I added it in the way it was previously (were the
> checkpatch error was still present). Please let me know if you want me to
> send a new version fixing this.
I think it's the opportunity to fix it. If you can resend a new version
including my ack.
Regards
Ludovic
>
> Thank you,
> Claudiu Beznea
>
> >
> >> if ((config & mask) == flag) { \
> >> if (num_conf) \
> >> seq_puts(s, "|"); \
> >> - seq_puts(s, #flag); \
> >> + seq_puts(s, #name); \
> >> num_conf++; \
> >> } \
> >> } while (0)
> >> @@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
> >> DBG_SHOW_FLAG(PULL_DOWN);
> >> DBG_SHOW_FLAG(DIS_SCHMIT);
> >> DBG_SHOW_FLAG(DEGLITCH);
> >> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
> >> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
> >> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
> >> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
> >> + DRIVE_STRENGTH_LOW);
> >> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
> >> + DRIVE_STRENGTH_MED);
> >> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
> >> + DRIVE_STRENGTH_HI);
> >> DBG_SHOW_FLAG(DEBOUNCE);
> >> if (config & DEBOUNCE) {
> >> val = config >> DEBOUNCE_VAL_SHIFT;
> >> --
> >> 2.7.4
> >>
> >
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
@ 2019-02-06 10:24 ` Ludovic Desroches
0 siblings, 0 replies; 39+ messages in thread
From: Ludovic Desroches @ 2019-02-06 10:24 UTC (permalink / raw)
To: Claudiu.Beznea
Cc: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, linux-gpio, devicetree, linux-arm-kernel,
linux-kernel
On Wed, Feb 06, 2019 at 09:46:28AM +0000, Claudiu.Beznea@microchip.com wrote:
>
>
> On 06.02.2019 10:13, Ludovic Desroches wrote:
> > On Thu, Jan 31, 2019 at 05:18:04PM +0100, Claudiu Beznea - M18063 wrote:
> >> From: Claudiu Beznea <claudiu.beznea@microchip.com>
> >>
> >> SAM9X60 uses high and low drive strengths. To implement this, in
> >> at91_pinctrl_mux_ops::set_drivestrength and
> >> at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
> >> drive strengths (1 for low, 2 for high), thus change the code to
> >> allow the usage of drive strength bit numbers.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> >> ---
> >> drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
> >> 1 file changed, 20 insertions(+), 12 deletions(-)
> >>
> >> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> >> index 3d49bbbcdbc7..31f06dafca2e 100644
> >> --- a/drivers/pinctrl/pinctrl-at91.c
> >> +++ b/drivers/pinctrl/pinctrl-at91.c
> >> @@ -72,10 +72,15 @@ static int gpio_banks;
> >> * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
> >> * strength when there is no dt config for it.
> >> */
> >> -#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
> >> -#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
> >> -#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
> >> -#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
> >> +enum drive_strength_bit {
> >> + DRIVE_STRENGTH_BIT_DEF,
> >> + DRIVE_STRENGTH_BIT_LOW,
> >> + DRIVE_STRENGTH_BIT_MED,
> >> + DRIVE_STRENGTH_BIT_HI,
> >> +};
> >> +
> >> +#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
> >> + DRIVE_STRENGTH_SHIFT)
> >>
> >> /**
> >> * struct at91_pmx_func - describes AT91 pinmux functions
> >> @@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
> >> /* SAMA5 strength is 1:1 with our defines,
> >> * except 0 is equivalent to low per datasheet */
> >> if (!tmp)
> >> - tmp = DRIVE_STRENGTH_LOW;
> >> + tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
> >>
> >> return tmp;
> >> }
> >> @@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
> >>
> >> /* strength is inverse in SAM9x5s hardware with the pinctrl defines
> >> * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
> >> - tmp = DRIVE_STRENGTH_HI - tmp;
> >> + tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
> >>
> >> return tmp;
> >> }
> >> @@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
> >>
> >> /* strength is inverse on SAM9x5s with our defines
> >> * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
> >> - setting = DRIVE_STRENGTH_HI - setting;
> >> + setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
> >>
> >> set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
> >> setting);
> >> @@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
> >> } \
> >> } while (0)
> >>
> >> -#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
> >> +#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
> >
> > checkpatch error: space required
>
> I'm aware of that but I added it in the way it was previously (were the
> checkpatch error was still present). Please let me know if you want me to
> send a new version fixing this.
I think it's the opportunity to fix it. If you can resend a new version
including my ack.
Regards
Ludovic
>
> Thank you,
> Claudiu Beznea
>
> >
> >> if ((config & mask) == flag) { \
> >> if (num_conf) \
> >> seq_puts(s, "|"); \
> >> - seq_puts(s, #flag); \
> >> + seq_puts(s, #name); \
> >> num_conf++; \
> >> } \
> >> } while (0)
> >> @@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
> >> DBG_SHOW_FLAG(PULL_DOWN);
> >> DBG_SHOW_FLAG(DIS_SCHMIT);
> >> DBG_SHOW_FLAG(DEGLITCH);
> >> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
> >> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
> >> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
> >> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
> >> + DRIVE_STRENGTH_LOW);
> >> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
> >> + DRIVE_STRENGTH_MED);
> >> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
> >> + DRIVE_STRENGTH_HI);
> >> DBG_SHOW_FLAG(DEBOUNCE);
> >> if (config & DEBOUNCE) {
> >> val = config >> DEBOUNCE_VAL_SHIFT;
> >> --
> >> 2.7.4
> >>
> >
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
2019-02-06 10:24 ` Ludovic Desroches
(?)
@ 2019-02-06 13:46 ` Claudiu.Beznea
-1 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-02-06 13:46 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, linux-gpio, devicetree, linux-arm-kernel,
linux-kernel
On 06.02.2019 12:24, Ludovic Desroches wrote:
> On Wed, Feb 06, 2019 at 09:46:28AM +0000, Claudiu.Beznea@microchip.com wrote:
>>
>>
>> On 06.02.2019 10:13, Ludovic Desroches wrote:
>>> On Thu, Jan 31, 2019 at 05:18:04PM +0100, Claudiu Beznea - M18063 wrote:
>>>> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>>>>
>>>> SAM9X60 uses high and low drive strengths. To implement this, in
>>>> at91_pinctrl_mux_ops::set_drivestrength and
>>>> at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
>>>> drive strengths (1 for low, 2 for high), thus change the code to
>>>> allow the usage of drive strength bit numbers.
>>>>
>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>>>> ---
>>>> drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
>>>> 1 file changed, 20 insertions(+), 12 deletions(-)
>>>>
>>>> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
>>>> index 3d49bbbcdbc7..31f06dafca2e 100644
>>>> --- a/drivers/pinctrl/pinctrl-at91.c
>>>> +++ b/drivers/pinctrl/pinctrl-at91.c
>>>> @@ -72,10 +72,15 @@ static int gpio_banks;
>>>> * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
>>>> * strength when there is no dt config for it.
>>>> */
>>>> -#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
>>>> -#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
>>>> -#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
>>>> -#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
>>>> +enum drive_strength_bit {
>>>> + DRIVE_STRENGTH_BIT_DEF,
>>>> + DRIVE_STRENGTH_BIT_LOW,
>>>> + DRIVE_STRENGTH_BIT_MED,
>>>> + DRIVE_STRENGTH_BIT_HI,
>>>> +};
>>>> +
>>>> +#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
>>>> + DRIVE_STRENGTH_SHIFT)
>>>>
>>>> /**
>>>> * struct at91_pmx_func - describes AT91 pinmux functions
>>>> @@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
>>>> /* SAMA5 strength is 1:1 with our defines,
>>>> * except 0 is equivalent to low per datasheet */
>>>> if (!tmp)
>>>> - tmp = DRIVE_STRENGTH_LOW;
>>>> + tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
>>>>
>>>> return tmp;
>>>> }
>>>> @@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
>>>>
>>>> /* strength is inverse in SAM9x5s hardware with the pinctrl defines
>>>> * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
>>>> - tmp = DRIVE_STRENGTH_HI - tmp;
>>>> + tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
>>>>
>>>> return tmp;
>>>> }
>>>> @@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
>>>>
>>>> /* strength is inverse on SAM9x5s with our defines
>>>> * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
>>>> - setting = DRIVE_STRENGTH_HI - setting;
>>>> + setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
>>>>
>>>> set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
>>>> setting);
>>>> @@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
>>>> } \
>>>> } while (0)
>>>>
>>>> -#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
>>>> +#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
>>>
>>> checkpatch error: space required
>>
>> I'm aware of that but I added it in the way it was previously (were the
>> checkpatch error was still present). Please let me know if you want me to
>> send a new version fixing this.
>
> I think it's the opportunity to fix it. If you can resend a new version
> including my ack.
Sure!
Thanks,
Claudiu
>
> Regards
>
> Ludovic
>
>>
>> Thank you,
>> Claudiu Beznea
>>
>>>
>>>> if ((config & mask) == flag) { \
>>>> if (num_conf) \
>>>> seq_puts(s, "|"); \
>>>> - seq_puts(s, #flag); \
>>>> + seq_puts(s, #name); \
>>>> num_conf++; \
>>>> } \
>>>> } while (0)
>>>> @@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
>>>> DBG_SHOW_FLAG(PULL_DOWN);
>>>> DBG_SHOW_FLAG(DIS_SCHMIT);
>>>> DBG_SHOW_FLAG(DEGLITCH);
>>>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
>>>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
>>>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
>>>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
>>>> + DRIVE_STRENGTH_LOW);
>>>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
>>>> + DRIVE_STRENGTH_MED);
>>>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
>>>> + DRIVE_STRENGTH_HI);
>>>> DBG_SHOW_FLAG(DEBOUNCE);
>>>> if (config & DEBOUNCE) {
>>>> val = config >> DEBOUNCE_VAL_SHIFT;
>>>> --
>>>> 2.7.4
>>>>
>>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
@ 2019-02-06 13:46 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-02-06 13:46 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, linux-gpio, devicetree, linux-arm-kernel,
linux-kernel
On 06.02.2019 12:24, Ludovic Desroches wrote:
> On Wed, Feb 06, 2019 at 09:46:28AM +0000, Claudiu.Beznea@microchip.com wrote:
>>
>>
>> On 06.02.2019 10:13, Ludovic Desroches wrote:
>>> On Thu, Jan 31, 2019 at 05:18:04PM +0100, Claudiu Beznea - M18063 wrote:
>>>> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>>>>
>>>> SAM9X60 uses high and low drive strengths. To implement this, in
>>>> at91_pinctrl_mux_ops::set_drivestrength and
>>>> at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
>>>> drive strengths (1 for low, 2 for high), thus change the code to
>>>> allow the usage of drive strength bit numbers.
>>>>
>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>>>> ---
>>>> drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
>>>> 1 file changed, 20 insertions(+), 12 deletions(-)
>>>>
>>>> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
>>>> index 3d49bbbcdbc7..31f06dafca2e 100644
>>>> --- a/drivers/pinctrl/pinctrl-at91.c
>>>> +++ b/drivers/pinctrl/pinctrl-at91.c
>>>> @@ -72,10 +72,15 @@ static int gpio_banks;
>>>> * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
>>>> * strength when there is no dt config for it.
>>>> */
>>>> -#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
>>>> -#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
>>>> -#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
>>>> -#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
>>>> +enum drive_strength_bit {
>>>> + DRIVE_STRENGTH_BIT_DEF,
>>>> + DRIVE_STRENGTH_BIT_LOW,
>>>> + DRIVE_STRENGTH_BIT_MED,
>>>> + DRIVE_STRENGTH_BIT_HI,
>>>> +};
>>>> +
>>>> +#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
>>>> + DRIVE_STRENGTH_SHIFT)
>>>>
>>>> /**
>>>> * struct at91_pmx_func - describes AT91 pinmux functions
>>>> @@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
>>>> /* SAMA5 strength is 1:1 with our defines,
>>>> * except 0 is equivalent to low per datasheet */
>>>> if (!tmp)
>>>> - tmp = DRIVE_STRENGTH_LOW;
>>>> + tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
>>>>
>>>> return tmp;
>>>> }
>>>> @@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
>>>>
>>>> /* strength is inverse in SAM9x5s hardware with the pinctrl defines
>>>> * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
>>>> - tmp = DRIVE_STRENGTH_HI - tmp;
>>>> + tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
>>>>
>>>> return tmp;
>>>> }
>>>> @@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
>>>>
>>>> /* strength is inverse on SAM9x5s with our defines
>>>> * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
>>>> - setting = DRIVE_STRENGTH_HI - setting;
>>>> + setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
>>>>
>>>> set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
>>>> setting);
>>>> @@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
>>>> } \
>>>> } while (0)
>>>>
>>>> -#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
>>>> +#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
>>>
>>> checkpatch error: space required
>>
>> I'm aware of that but I added it in the way it was previously (were the
>> checkpatch error was still present). Please let me know if you want me to
>> send a new version fixing this.
>
> I think it's the opportunity to fix it. If you can resend a new version
> including my ack.
Sure!
Thanks,
Claudiu
>
> Regards
>
> Ludovic
>
>>
>> Thank you,
>> Claudiu Beznea
>>
>>>
>>>> if ((config & mask) == flag) { \
>>>> if (num_conf) \
>>>> seq_puts(s, "|"); \
>>>> - seq_puts(s, #flag); \
>>>> + seq_puts(s, #name); \
>>>> num_conf++; \
>>>> } \
>>>> } while (0)
>>>> @@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
>>>> DBG_SHOW_FLAG(PULL_DOWN);
>>>> DBG_SHOW_FLAG(DIS_SCHMIT);
>>>> DBG_SHOW_FLAG(DEGLITCH);
>>>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
>>>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
>>>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
>>>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
>>>> + DRIVE_STRENGTH_LOW);
>>>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
>>>> + DRIVE_STRENGTH_MED);
>>>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
>>>> + DRIVE_STRENGTH_HI);
>>>> DBG_SHOW_FLAG(DEBOUNCE);
>>>> if (config & DEBOUNCE) {
>>>> val = config >> DEBOUNCE_VAL_SHIFT;
>>>> --
>>>> 2.7.4
>>>>
>>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v2 1/7] pinctrl: at91: add option to use drive strength bits
@ 2019-02-06 13:46 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-02-06 13:46 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, linux-gpio, devicetree, linux-arm-kernel,
linux-kernel
On 06.02.2019 12:24, Ludovic Desroches wrote:
> On Wed, Feb 06, 2019 at 09:46:28AM +0000, Claudiu.Beznea@microchip.com wrote:
>>
>>
>> On 06.02.2019 10:13, Ludovic Desroches wrote:
>>> On Thu, Jan 31, 2019 at 05:18:04PM +0100, Claudiu Beznea - M18063 wrote:
>>>> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>>>>
>>>> SAM9X60 uses high and low drive strengths. To implement this, in
>>>> at91_pinctrl_mux_ops::set_drivestrength and
>>>> at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
>>>> drive strengths (1 for low, 2 for high), thus change the code to
>>>> allow the usage of drive strength bit numbers.
>>>>
>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>>>> ---
>>>> drivers/pinctrl/pinctrl-at91.c | 32 ++++++++++++++++++++------------
>>>> 1 file changed, 20 insertions(+), 12 deletions(-)
>>>>
>>>> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
>>>> index 3d49bbbcdbc7..31f06dafca2e 100644
>>>> --- a/drivers/pinctrl/pinctrl-at91.c
>>>> +++ b/drivers/pinctrl/pinctrl-at91.c
>>>> @@ -72,10 +72,15 @@ static int gpio_banks;
>>>> * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
>>>> * strength when there is no dt config for it.
>>>> */
>>>> -#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
>>>> -#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
>>>> -#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
>>>> -#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
>>>> +enum drive_strength_bit {
>>>> + DRIVE_STRENGTH_BIT_DEF,
>>>> + DRIVE_STRENGTH_BIT_LOW,
>>>> + DRIVE_STRENGTH_BIT_MED,
>>>> + DRIVE_STRENGTH_BIT_HI,
>>>> +};
>>>> +
>>>> +#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
>>>> + DRIVE_STRENGTH_SHIFT)
>>>>
>>>> /**
>>>> * struct at91_pmx_func - describes AT91 pinmux functions
>>>> @@ -551,7 +556,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
>>>> /* SAMA5 strength is 1:1 with our defines,
>>>> * except 0 is equivalent to low per datasheet */
>>>> if (!tmp)
>>>> - tmp = DRIVE_STRENGTH_LOW;
>>>> + tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
>>>>
>>>> return tmp;
>>>> }
>>>> @@ -564,7 +569,7 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
>>>>
>>>> /* strength is inverse in SAM9x5s hardware with the pinctrl defines
>>>> * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
>>>> - tmp = DRIVE_STRENGTH_HI - tmp;
>>>> + tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
>>>>
>>>> return tmp;
>>>> }
>>>> @@ -600,7 +605,7 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
>>>>
>>>> /* strength is inverse on SAM9x5s with our defines
>>>> * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
>>>> - setting = DRIVE_STRENGTH_HI - setting;
>>>> + setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
>>>>
>>>> set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
>>>> setting);
>>>> @@ -959,11 +964,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
>>>> } \
>>>> } while (0)
>>>>
>>>> -#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
>>>> +#define DBG_SHOW_FLAG_MASKED(mask,flag,name) do { \
>>>
>>> checkpatch error: space required
>>
>> I'm aware of that but I added it in the way it was previously (were the
>> checkpatch error was still present). Please let me know if you want me to
>> send a new version fixing this.
>
> I think it's the opportunity to fix it. If you can resend a new version
> including my ack.
Sure!
Thanks,
Claudiu
>
> Regards
>
> Ludovic
>
>>
>> Thank you,
>> Claudiu Beznea
>>
>>>
>>>> if ((config & mask) == flag) { \
>>>> if (num_conf) \
>>>> seq_puts(s, "|"); \
>>>> - seq_puts(s, #flag); \
>>>> + seq_puts(s, #name); \
>>>> num_conf++; \
>>>> } \
>>>> } while (0)
>>>> @@ -981,9 +986,12 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
>>>> DBG_SHOW_FLAG(PULL_DOWN);
>>>> DBG_SHOW_FLAG(DIS_SCHMIT);
>>>> DBG_SHOW_FLAG(DEGLITCH);
>>>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
>>>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
>>>> - DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
>>>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
>>>> + DRIVE_STRENGTH_LOW);
>>>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
>>>> + DRIVE_STRENGTH_MED);
>>>> + DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
>>>> + DRIVE_STRENGTH_HI);
>>>> DBG_SHOW_FLAG(DEBOUNCE);
>>>> if (config & DEBOUNCE) {
>>>> val = config >> DEBOUNCE_VAL_SHIFT;
>>>> --
>>>> 2.7.4
>>>>
>>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2 2/7] pinctrl: at91: add drive strength support for SAM9X60
2019-01-31 16:18 ` Claudiu.Beznea
(?)
@ 2019-01-31 16:18 ` Claudiu.Beznea
-1 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add drive strength support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 52 ++++++++++++++++++++++++++++++++++++++++++
drivers/pinctrl/pinctrl-at91.h | 2 ++
2 files changed, 54 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 31f06dafca2e..46443b97d811 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -574,6 +574,17 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
return tmp;
}
+static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
+ unsigned pin)
+{
+ unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
+
+ if (tmp & BIT(pin))
+ return DRIVE_STRENGTH_BIT_HI;
+
+ return DRIVE_STRENGTH_BIT_LOW;
+}
+
static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
{
unsigned tmp = readl_relaxed(reg);
@@ -611,6 +622,27 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
setting);
}
+static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
+ u32 setting)
+{
+ unsigned int tmp;
+
+ if (setting <= DRIVE_STRENGTH_BIT_DEF ||
+ setting == DRIVE_STRENGTH_BIT_MED ||
+ setting > DRIVE_STRENGTH_BIT_HI)
+ return;
+
+ tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
+
+ /* Strength is 0: low, 1: hi */
+ if (setting == DRIVE_STRENGTH_BIT_LOW)
+ tmp &= ~BIT(pin);
+ else
+ tmp |= BIT(pin);
+
+ writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
+}
+
static struct at91_pinctrl_mux_ops at91rm9200_ops = {
.get_periph = at91_mux_get_periph,
.mux_A_periph = at91_mux_set_A_periph,
@@ -639,6 +671,26 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
.irq_type = alt_gpio_irq_type,
};
+static const struct at91_pinctrl_mux_ops sam9x60_ops = {
+ .get_periph = at91_mux_pio3_get_periph,
+ .mux_A_periph = at91_mux_pio3_set_A_periph,
+ .mux_B_periph = at91_mux_pio3_set_B_periph,
+ .mux_C_periph = at91_mux_pio3_set_C_periph,
+ .mux_D_periph = at91_mux_pio3_set_D_periph,
+ .get_deglitch = at91_mux_pio3_get_deglitch,
+ .set_deglitch = at91_mux_pio3_set_deglitch,
+ .get_debounce = at91_mux_pio3_get_debounce,
+ .set_debounce = at91_mux_pio3_set_debounce,
+ .get_pulldown = at91_mux_pio3_get_pulldown,
+ .set_pulldown = at91_mux_pio3_set_pulldown,
+ .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
+ .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
+ .get_drivestrength = at91_mux_sam9x60_get_drivestrength,
+ .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
+ .irq_type = alt_gpio_irq_type,
+
+};
+
static struct at91_pinctrl_mux_ops sama5d3_ops = {
.get_periph = at91_mux_pio3_get_periph,
.mux_A_periph = at91_mux_pio3_set_A_periph,
diff --git a/drivers/pinctrl/pinctrl-at91.h b/drivers/pinctrl/pinctrl-at91.h
index 79b957f1dfa2..19fc27e66bfd 100644
--- a/drivers/pinctrl/pinctrl-at91.h
+++ b/drivers/pinctrl/pinctrl-at91.h
@@ -69,4 +69,6 @@
#define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
#define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
+#define SAM9X60_PIO_DRIVER1 0x118 /* PIO Driver 1 register offset */
+
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v2 2/7] pinctrl: at91: add drive strength support for SAM9X60
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, Claudiu.Beznea, linux-kernel, linux-arm-kernel, devicetree
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add drive strength support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 52 ++++++++++++++++++++++++++++++++++++++++++
drivers/pinctrl/pinctrl-at91.h | 2 ++
2 files changed, 54 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 31f06dafca2e..46443b97d811 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -574,6 +574,17 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
return tmp;
}
+static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
+ unsigned pin)
+{
+ unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
+
+ if (tmp & BIT(pin))
+ return DRIVE_STRENGTH_BIT_HI;
+
+ return DRIVE_STRENGTH_BIT_LOW;
+}
+
static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
{
unsigned tmp = readl_relaxed(reg);
@@ -611,6 +622,27 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
setting);
}
+static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
+ u32 setting)
+{
+ unsigned int tmp;
+
+ if (setting <= DRIVE_STRENGTH_BIT_DEF ||
+ setting == DRIVE_STRENGTH_BIT_MED ||
+ setting > DRIVE_STRENGTH_BIT_HI)
+ return;
+
+ tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
+
+ /* Strength is 0: low, 1: hi */
+ if (setting == DRIVE_STRENGTH_BIT_LOW)
+ tmp &= ~BIT(pin);
+ else
+ tmp |= BIT(pin);
+
+ writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
+}
+
static struct at91_pinctrl_mux_ops at91rm9200_ops = {
.get_periph = at91_mux_get_periph,
.mux_A_periph = at91_mux_set_A_periph,
@@ -639,6 +671,26 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
.irq_type = alt_gpio_irq_type,
};
+static const struct at91_pinctrl_mux_ops sam9x60_ops = {
+ .get_periph = at91_mux_pio3_get_periph,
+ .mux_A_periph = at91_mux_pio3_set_A_periph,
+ .mux_B_periph = at91_mux_pio3_set_B_periph,
+ .mux_C_periph = at91_mux_pio3_set_C_periph,
+ .mux_D_periph = at91_mux_pio3_set_D_periph,
+ .get_deglitch = at91_mux_pio3_get_deglitch,
+ .set_deglitch = at91_mux_pio3_set_deglitch,
+ .get_debounce = at91_mux_pio3_get_debounce,
+ .set_debounce = at91_mux_pio3_set_debounce,
+ .get_pulldown = at91_mux_pio3_get_pulldown,
+ .set_pulldown = at91_mux_pio3_set_pulldown,
+ .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
+ .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
+ .get_drivestrength = at91_mux_sam9x60_get_drivestrength,
+ .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
+ .irq_type = alt_gpio_irq_type,
+
+};
+
static struct at91_pinctrl_mux_ops sama5d3_ops = {
.get_periph = at91_mux_pio3_get_periph,
.mux_A_periph = at91_mux_pio3_set_A_periph,
diff --git a/drivers/pinctrl/pinctrl-at91.h b/drivers/pinctrl/pinctrl-at91.h
index 79b957f1dfa2..19fc27e66bfd 100644
--- a/drivers/pinctrl/pinctrl-at91.h
+++ b/drivers/pinctrl/pinctrl-at91.h
@@ -69,4 +69,6 @@
#define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
#define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
+#define SAM9X60_PIO_DRIVER1 0x118 /* PIO Driver 1 register offset */
+
#endif
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v2 2/7] pinctrl: at91: add drive strength support for SAM9X60
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add drive strength support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 52 ++++++++++++++++++++++++++++++++++++++++++
drivers/pinctrl/pinctrl-at91.h | 2 ++
2 files changed, 54 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 31f06dafca2e..46443b97d811 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -574,6 +574,17 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
return tmp;
}
+static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
+ unsigned pin)
+{
+ unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
+
+ if (tmp & BIT(pin))
+ return DRIVE_STRENGTH_BIT_HI;
+
+ return DRIVE_STRENGTH_BIT_LOW;
+}
+
static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
{
unsigned tmp = readl_relaxed(reg);
@@ -611,6 +622,27 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
setting);
}
+static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
+ u32 setting)
+{
+ unsigned int tmp;
+
+ if (setting <= DRIVE_STRENGTH_BIT_DEF ||
+ setting == DRIVE_STRENGTH_BIT_MED ||
+ setting > DRIVE_STRENGTH_BIT_HI)
+ return;
+
+ tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
+
+ /* Strength is 0: low, 1: hi */
+ if (setting == DRIVE_STRENGTH_BIT_LOW)
+ tmp &= ~BIT(pin);
+ else
+ tmp |= BIT(pin);
+
+ writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
+}
+
static struct at91_pinctrl_mux_ops at91rm9200_ops = {
.get_periph = at91_mux_get_periph,
.mux_A_periph = at91_mux_set_A_periph,
@@ -639,6 +671,26 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
.irq_type = alt_gpio_irq_type,
};
+static const struct at91_pinctrl_mux_ops sam9x60_ops = {
+ .get_periph = at91_mux_pio3_get_periph,
+ .mux_A_periph = at91_mux_pio3_set_A_periph,
+ .mux_B_periph = at91_mux_pio3_set_B_periph,
+ .mux_C_periph = at91_mux_pio3_set_C_periph,
+ .mux_D_periph = at91_mux_pio3_set_D_periph,
+ .get_deglitch = at91_mux_pio3_get_deglitch,
+ .set_deglitch = at91_mux_pio3_set_deglitch,
+ .get_debounce = at91_mux_pio3_get_debounce,
+ .set_debounce = at91_mux_pio3_set_debounce,
+ .get_pulldown = at91_mux_pio3_get_pulldown,
+ .set_pulldown = at91_mux_pio3_set_pulldown,
+ .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
+ .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
+ .get_drivestrength = at91_mux_sam9x60_get_drivestrength,
+ .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
+ .irq_type = alt_gpio_irq_type,
+
+};
+
static struct at91_pinctrl_mux_ops sama5d3_ops = {
.get_periph = at91_mux_pio3_get_periph,
.mux_A_periph = at91_mux_pio3_set_A_periph,
diff --git a/drivers/pinctrl/pinctrl-at91.h b/drivers/pinctrl/pinctrl-at91.h
index 79b957f1dfa2..19fc27e66bfd 100644
--- a/drivers/pinctrl/pinctrl-at91.h
+++ b/drivers/pinctrl/pinctrl-at91.h
@@ -69,4 +69,6 @@
#define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
#define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
+#define SAM9X60_PIO_DRIVER1 0x118 /* PIO Driver 1 register offset */
+
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v2 3/7] pinctrl: at91: add compatibles for SAM9X60 pin controller
2019-01-31 16:18 ` Claudiu.Beznea
(?)
@ 2019-01-31 16:18 ` Claudiu.Beznea
-1 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add compatibles for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 46443b97d811..5456a2692b8c 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -1215,6 +1215,7 @@ static const struct of_device_id at91_pinctrl_of_match[] = {
{ .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
{ .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
{ .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
+ { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
{ /* sentinel */ }
};
@@ -1757,6 +1758,7 @@ static const struct gpio_chip at91_gpio_template = {
static const struct of_device_id at91_gpio_of_match[] = {
{ .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
{ .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
+ { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
{ /* sentinel */ }
};
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v2 3/7] pinctrl: at91: add compatibles for SAM9X60 pin controller
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, Claudiu.Beznea, linux-kernel, linux-arm-kernel, devicetree
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add compatibles for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 46443b97d811..5456a2692b8c 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -1215,6 +1215,7 @@ static const struct of_device_id at91_pinctrl_of_match[] = {
{ .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
{ .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
{ .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
+ { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
{ /* sentinel */ }
};
@@ -1757,6 +1758,7 @@ static const struct gpio_chip at91_gpio_template = {
static const struct of_device_id at91_gpio_of_match[] = {
{ .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
{ .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
+ { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
{ /* sentinel */ }
};
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v2 3/7] pinctrl: at91: add compatibles for SAM9X60 pin controller
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add compatibles for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 46443b97d811..5456a2692b8c 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -1215,6 +1215,7 @@ static const struct of_device_id at91_pinctrl_of_match[] = {
{ .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
{ .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
{ .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
+ { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
{ /* sentinel */ }
};
@@ -1757,6 +1758,7 @@ static const struct gpio_chip at91_gpio_template = {
static const struct of_device_id at91_gpio_of_match[] = {
{ .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
{ .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
+ { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
{ /* sentinel */ }
};
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v2 4/7] dt-bindings: add documentation for banks
2019-01-31 16:18 ` Claudiu.Beznea
(?)
@ 2019-01-31 16:18 ` Claudiu.Beznea
-1 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add documentation for at91 pin controller banks.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
.../bindings/pinctrl/atmel,at91-pinctrl.txt | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index 3e23fece99da..40e33dfc36fd 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -116,6 +116,18 @@ Some requirements for using atmel,at91rm9200-pinctrl binding:
configurations by referring to the phandle of that pin configuration node.
4. The gpio controller must be describe in the pinctrl simple-bus.
+For each bank the required properties are:
+- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio"
+- reg: physical base address and length of the controller's registers
+- interrupts: interrupt outputs from the controller
+- interrupt-controller: marks the device node as an interrupt controller
+- #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt
+ for more details.
+- gpio-controller
+- #gpio-cells: should be 2; the first cell is the GPIO number and the second
+ cell specifies GPIO flags as defined in <dt-bindings/gpio/gpio.h>.
+- clocks: bank clock
+
Examples:
pinctrl@fffff400 {
@@ -125,6 +137,17 @@ pinctrl@fffff400 {
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
reg = <0xfffff400 0x600>;
+ pioA: gpio@fffff400 {
+ compatible = "atmel,at91sam9x5-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+ };
+
atmel,mux-mask = <
/* A B */
0xffffffff 0xffc00c3b /* pioA */
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v2 4/7] dt-bindings: add documentation for banks
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, Claudiu.Beznea, linux-kernel, linux-arm-kernel, devicetree
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add documentation for at91 pin controller banks.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
.../bindings/pinctrl/atmel,at91-pinctrl.txt | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index 3e23fece99da..40e33dfc36fd 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -116,6 +116,18 @@ Some requirements for using atmel,at91rm9200-pinctrl binding:
configurations by referring to the phandle of that pin configuration node.
4. The gpio controller must be describe in the pinctrl simple-bus.
+For each bank the required properties are:
+- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio"
+- reg: physical base address and length of the controller's registers
+- interrupts: interrupt outputs from the controller
+- interrupt-controller: marks the device node as an interrupt controller
+- #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt
+ for more details.
+- gpio-controller
+- #gpio-cells: should be 2; the first cell is the GPIO number and the second
+ cell specifies GPIO flags as defined in <dt-bindings/gpio/gpio.h>.
+- clocks: bank clock
+
Examples:
pinctrl@fffff400 {
@@ -125,6 +137,17 @@ pinctrl@fffff400 {
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
reg = <0xfffff400 0x600>;
+ pioA: gpio@fffff400 {
+ compatible = "atmel,at91sam9x5-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+ };
+
atmel,mux-mask = <
/* A B */
0xffffffff 0xffc00c3b /* pioA */
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v2 4/7] dt-bindings: add documentation for banks
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add documentation for at91 pin controller banks.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
.../bindings/pinctrl/atmel,at91-pinctrl.txt | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index 3e23fece99da..40e33dfc36fd 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -116,6 +116,18 @@ Some requirements for using atmel,at91rm9200-pinctrl binding:
configurations by referring to the phandle of that pin configuration node.
4. The gpio controller must be describe in the pinctrl simple-bus.
+For each bank the required properties are:
+- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio"
+- reg: physical base address and length of the controller's registers
+- interrupts: interrupt outputs from the controller
+- interrupt-controller: marks the device node as an interrupt controller
+- #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt
+ for more details.
+- gpio-controller
+- #gpio-cells: should be 2; the first cell is the GPIO number and the second
+ cell specifies GPIO flags as defined in <dt-bindings/gpio/gpio.h>.
+- clocks: bank clock
+
Examples:
pinctrl@fffff400 {
@@ -125,6 +137,17 @@ pinctrl@fffff400 {
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
reg = <0xfffff400 0x600>;
+ pioA: gpio@fffff400 {
+ compatible = "atmel,at91sam9x5-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+ };
+
atmel,mux-mask = <
/* A B */
0xffffffff 0xffc00c3b /* pioA */
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v2 5/7] dt-bindings: add bindings for SAM9X60
2019-01-31 16:18 ` Claudiu.Beznea
(?)
@ 2019-01-31 16:18 ` Claudiu.Beznea
-1 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add device tree binding for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index 40e33dfc36fd..c2d51ed86d47 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -19,7 +19,7 @@ such as pull-up, multi drive, etc.
Required properties for iomux controller:
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
- or "atmel,sama5d3-pinctrl"
+ or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
@@ -117,7 +117,8 @@ Some requirements for using atmel,at91rm9200-pinctrl binding:
4. The gpio controller must be describe in the pinctrl simple-bus.
For each bank the required properties are:
-- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio"
+- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or
+ "microchip,sam9x60-gpio"
- reg: physical base address and length of the controller's registers
- interrupts: interrupt outputs from the controller
- interrupt-controller: marks the device node as an interrupt controller
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v2 5/7] dt-bindings: add bindings for SAM9X60
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, Claudiu.Beznea, linux-kernel, linux-arm-kernel, devicetree
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add device tree binding for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index 40e33dfc36fd..c2d51ed86d47 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -19,7 +19,7 @@ such as pull-up, multi drive, etc.
Required properties for iomux controller:
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
- or "atmel,sama5d3-pinctrl"
+ or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
@@ -117,7 +117,8 @@ Some requirements for using atmel,at91rm9200-pinctrl binding:
4. The gpio controller must be describe in the pinctrl simple-bus.
For each bank the required properties are:
-- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio"
+- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or
+ "microchip,sam9x60-gpio"
- reg: physical base address and length of the controller's registers
- interrupts: interrupt outputs from the controller
- interrupt-controller: marks the device node as an interrupt controller
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v2 5/7] dt-bindings: add bindings for SAM9X60
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add device tree binding for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index 40e33dfc36fd..c2d51ed86d47 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -19,7 +19,7 @@ such as pull-up, multi drive, etc.
Required properties for iomux controller:
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
- or "atmel,sama5d3-pinctrl"
+ or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
@@ -117,7 +117,8 @@ Some requirements for using atmel,at91rm9200-pinctrl binding:
4. The gpio controller must be describe in the pinctrl simple-bus.
For each bank the required properties are:
-- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio"
+- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or
+ "microchip,sam9x60-gpio"
- reg: physical base address and length of the controller's registers
- interrupts: interrupt outputs from the controller
- interrupt-controller: marks the device node as an interrupt controller
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v2 6/7] pinctrl: at91: add slewrate support for SAM9X60
2019-01-31 16:18 ` Claudiu.Beznea
(?)
@ 2019-01-31 16:18 ` Claudiu.Beznea
-1 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add slew rate support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 48 ++++++++++++++++++++++++++++++++++++++
drivers/pinctrl/pinctrl-at91.h | 1 +
include/dt-bindings/pinctrl/at91.h | 4 ++++
3 files changed, 53 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 5456a2692b8c..2c6d3b61951f 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -59,6 +59,9 @@ static int gpio_banks;
#define OUTPUT (1 << 7)
#define OUTPUT_VAL_SHIFT 8
#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
+#define SLEWRATE_SHIFT 9
+#define SLEWRATE_MASK 0x1
+#define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
#define DEBOUNCE (1 << 16)
#define DEBOUNCE_VAL_SHIFT 17
#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
@@ -82,6 +85,13 @@ enum drive_strength_bit {
#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
DRIVE_STRENGTH_SHIFT)
+enum slewrate_bit {
+ SLEWRATE_BIT_DIS,
+ SLEWRATE_BIT_ENA,
+};
+
+#define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
+
/**
* struct at91_pmx_func - describes AT91 pinmux functions
* @name: the name of this specific function
@@ -171,6 +181,8 @@ struct at91_pinctrl_mux_ops {
unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
void (*set_drivestrength)(void __iomem *pio, unsigned pin,
u32 strength);
+ unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
+ void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
/* irq */
int (*irq_type)(struct irq_data *d, unsigned type);
};
@@ -585,6 +597,16 @@ static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
return DRIVE_STRENGTH_BIT_LOW;
}
+static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
+{
+ unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
+
+ if ((tmp & BIT(pin)))
+ return SLEWRATE_BIT_ENA;
+
+ return SLEWRATE_BIT_DIS;
+}
+
static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
{
unsigned tmp = readl_relaxed(reg);
@@ -643,6 +665,24 @@ static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
}
+static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
+ u32 setting)
+{
+ unsigned int tmp;
+
+ if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
+ return;
+
+ tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
+
+ if (setting == SLEWRATE_BIT_DIS)
+ tmp &= ~BIT(pin);
+ else
+ tmp |= BIT(pin);
+
+ writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
+}
+
static struct at91_pinctrl_mux_ops at91rm9200_ops = {
.get_periph = at91_mux_get_periph,
.mux_A_periph = at91_mux_set_A_periph,
@@ -687,6 +727,8 @@ static const struct at91_pinctrl_mux_ops sam9x60_ops = {
.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
.get_drivestrength = at91_mux_sam9x60_get_drivestrength,
.set_drivestrength = at91_mux_sam9x60_set_drivestrength,
+ .get_slewrate = at91_mux_sam9x60_get_slewrate,
+ .set_slewrate = at91_mux_sam9x60_set_slewrate,
.irq_type = alt_gpio_irq_type,
};
@@ -950,6 +992,8 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
if (info->ops->get_drivestrength)
*config |= (info->ops->get_drivestrength(pio, pin)
<< DRIVE_STRENGTH_SHIFT);
+ if (info->ops->get_slewrate)
+ *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
if (at91_mux_get_output(pio, pin, &out))
*config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
@@ -1001,6 +1045,9 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
info->ops->set_drivestrength(pio, pin,
(config & DRIVE_STRENGTH)
>> DRIVE_STRENGTH_SHIFT);
+ if (info->ops->set_slewrate)
+ info->ops->set_slewrate(pio, pin,
+ (config & SLEWRATE) >> SLEWRATE_SHIFT);
} /* for each config */
@@ -1044,6 +1091,7 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
DRIVE_STRENGTH_MED);
DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
DRIVE_STRENGTH_HI);
+ DBG_SHOW_FLAG(SLEWRATE);
DBG_SHOW_FLAG(DEBOUNCE);
if (config & DEBOUNCE) {
val = config >> DEBOUNCE_VAL_SHIFT;
diff --git a/drivers/pinctrl/pinctrl-at91.h b/drivers/pinctrl/pinctrl-at91.h
index 19fc27e66bfd..223620f14b05 100644
--- a/drivers/pinctrl/pinctrl-at91.h
+++ b/drivers/pinctrl/pinctrl-at91.h
@@ -69,6 +69,7 @@
#define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
#define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
+#define SAM9X60_PIO_SLEWR 0x110 /* PIO Slew Rate Control Register */
#define SAM9X60_PIO_DRIVER1 0x118 /* PIO Driver 1 register offset */
#endif
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
index eb81867eac77..8dc10e00c627 100644
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -17,6 +17,7 @@
#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
#define AT91_PINCTRL_OUTPUT (1 << 7)
#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
+#define AT91_PINCTRL_SLEWRATE (1 << 9)
#define AT91_PINCTRL_DEBOUNCE (1 << 16)
#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
@@ -27,6 +28,9 @@
#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
+#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9)
+#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9)
+
#define AT91_PIOA 0
#define AT91_PIOB 1
#define AT91_PIOC 2
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v2 6/7] pinctrl: at91: add slewrate support for SAM9X60
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, Claudiu.Beznea, linux-kernel, linux-arm-kernel, devicetree
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add slew rate support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 48 ++++++++++++++++++++++++++++++++++++++
drivers/pinctrl/pinctrl-at91.h | 1 +
include/dt-bindings/pinctrl/at91.h | 4 ++++
3 files changed, 53 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 5456a2692b8c..2c6d3b61951f 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -59,6 +59,9 @@ static int gpio_banks;
#define OUTPUT (1 << 7)
#define OUTPUT_VAL_SHIFT 8
#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
+#define SLEWRATE_SHIFT 9
+#define SLEWRATE_MASK 0x1
+#define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
#define DEBOUNCE (1 << 16)
#define DEBOUNCE_VAL_SHIFT 17
#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
@@ -82,6 +85,13 @@ enum drive_strength_bit {
#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
DRIVE_STRENGTH_SHIFT)
+enum slewrate_bit {
+ SLEWRATE_BIT_DIS,
+ SLEWRATE_BIT_ENA,
+};
+
+#define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
+
/**
* struct at91_pmx_func - describes AT91 pinmux functions
* @name: the name of this specific function
@@ -171,6 +181,8 @@ struct at91_pinctrl_mux_ops {
unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
void (*set_drivestrength)(void __iomem *pio, unsigned pin,
u32 strength);
+ unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
+ void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
/* irq */
int (*irq_type)(struct irq_data *d, unsigned type);
};
@@ -585,6 +597,16 @@ static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
return DRIVE_STRENGTH_BIT_LOW;
}
+static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
+{
+ unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
+
+ if ((tmp & BIT(pin)))
+ return SLEWRATE_BIT_ENA;
+
+ return SLEWRATE_BIT_DIS;
+}
+
static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
{
unsigned tmp = readl_relaxed(reg);
@@ -643,6 +665,24 @@ static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
}
+static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
+ u32 setting)
+{
+ unsigned int tmp;
+
+ if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
+ return;
+
+ tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
+
+ if (setting == SLEWRATE_BIT_DIS)
+ tmp &= ~BIT(pin);
+ else
+ tmp |= BIT(pin);
+
+ writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
+}
+
static struct at91_pinctrl_mux_ops at91rm9200_ops = {
.get_periph = at91_mux_get_periph,
.mux_A_periph = at91_mux_set_A_periph,
@@ -687,6 +727,8 @@ static const struct at91_pinctrl_mux_ops sam9x60_ops = {
.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
.get_drivestrength = at91_mux_sam9x60_get_drivestrength,
.set_drivestrength = at91_mux_sam9x60_set_drivestrength,
+ .get_slewrate = at91_mux_sam9x60_get_slewrate,
+ .set_slewrate = at91_mux_sam9x60_set_slewrate,
.irq_type = alt_gpio_irq_type,
};
@@ -950,6 +992,8 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
if (info->ops->get_drivestrength)
*config |= (info->ops->get_drivestrength(pio, pin)
<< DRIVE_STRENGTH_SHIFT);
+ if (info->ops->get_slewrate)
+ *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
if (at91_mux_get_output(pio, pin, &out))
*config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
@@ -1001,6 +1045,9 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
info->ops->set_drivestrength(pio, pin,
(config & DRIVE_STRENGTH)
>> DRIVE_STRENGTH_SHIFT);
+ if (info->ops->set_slewrate)
+ info->ops->set_slewrate(pio, pin,
+ (config & SLEWRATE) >> SLEWRATE_SHIFT);
} /* for each config */
@@ -1044,6 +1091,7 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
DRIVE_STRENGTH_MED);
DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
DRIVE_STRENGTH_HI);
+ DBG_SHOW_FLAG(SLEWRATE);
DBG_SHOW_FLAG(DEBOUNCE);
if (config & DEBOUNCE) {
val = config >> DEBOUNCE_VAL_SHIFT;
diff --git a/drivers/pinctrl/pinctrl-at91.h b/drivers/pinctrl/pinctrl-at91.h
index 19fc27e66bfd..223620f14b05 100644
--- a/drivers/pinctrl/pinctrl-at91.h
+++ b/drivers/pinctrl/pinctrl-at91.h
@@ -69,6 +69,7 @@
#define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
#define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
+#define SAM9X60_PIO_SLEWR 0x110 /* PIO Slew Rate Control Register */
#define SAM9X60_PIO_DRIVER1 0x118 /* PIO Driver 1 register offset */
#endif
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
index eb81867eac77..8dc10e00c627 100644
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -17,6 +17,7 @@
#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
#define AT91_PINCTRL_OUTPUT (1 << 7)
#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
+#define AT91_PINCTRL_SLEWRATE (1 << 9)
#define AT91_PINCTRL_DEBOUNCE (1 << 16)
#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
@@ -27,6 +28,9 @@
#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
+#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9)
+#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9)
+
#define AT91_PIOA 0
#define AT91_PIOB 1
#define AT91_PIOC 2
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v2 6/7] pinctrl: at91: add slewrate support for SAM9X60
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add slew rate support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/pinctrl/pinctrl-at91.c | 48 ++++++++++++++++++++++++++++++++++++++
drivers/pinctrl/pinctrl-at91.h | 1 +
include/dt-bindings/pinctrl/at91.h | 4 ++++
3 files changed, 53 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 5456a2692b8c..2c6d3b61951f 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -59,6 +59,9 @@ static int gpio_banks;
#define OUTPUT (1 << 7)
#define OUTPUT_VAL_SHIFT 8
#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
+#define SLEWRATE_SHIFT 9
+#define SLEWRATE_MASK 0x1
+#define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
#define DEBOUNCE (1 << 16)
#define DEBOUNCE_VAL_SHIFT 17
#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
@@ -82,6 +85,13 @@ enum drive_strength_bit {
#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
DRIVE_STRENGTH_SHIFT)
+enum slewrate_bit {
+ SLEWRATE_BIT_DIS,
+ SLEWRATE_BIT_ENA,
+};
+
+#define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
+
/**
* struct at91_pmx_func - describes AT91 pinmux functions
* @name: the name of this specific function
@@ -171,6 +181,8 @@ struct at91_pinctrl_mux_ops {
unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
void (*set_drivestrength)(void __iomem *pio, unsigned pin,
u32 strength);
+ unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
+ void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
/* irq */
int (*irq_type)(struct irq_data *d, unsigned type);
};
@@ -585,6 +597,16 @@ static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
return DRIVE_STRENGTH_BIT_LOW;
}
+static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
+{
+ unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
+
+ if ((tmp & BIT(pin)))
+ return SLEWRATE_BIT_ENA;
+
+ return SLEWRATE_BIT_DIS;
+}
+
static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
{
unsigned tmp = readl_relaxed(reg);
@@ -643,6 +665,24 @@ static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
}
+static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
+ u32 setting)
+{
+ unsigned int tmp;
+
+ if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
+ return;
+
+ tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
+
+ if (setting == SLEWRATE_BIT_DIS)
+ tmp &= ~BIT(pin);
+ else
+ tmp |= BIT(pin);
+
+ writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
+}
+
static struct at91_pinctrl_mux_ops at91rm9200_ops = {
.get_periph = at91_mux_get_periph,
.mux_A_periph = at91_mux_set_A_periph,
@@ -687,6 +727,8 @@ static const struct at91_pinctrl_mux_ops sam9x60_ops = {
.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
.get_drivestrength = at91_mux_sam9x60_get_drivestrength,
.set_drivestrength = at91_mux_sam9x60_set_drivestrength,
+ .get_slewrate = at91_mux_sam9x60_get_slewrate,
+ .set_slewrate = at91_mux_sam9x60_set_slewrate,
.irq_type = alt_gpio_irq_type,
};
@@ -950,6 +992,8 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
if (info->ops->get_drivestrength)
*config |= (info->ops->get_drivestrength(pio, pin)
<< DRIVE_STRENGTH_SHIFT);
+ if (info->ops->get_slewrate)
+ *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
if (at91_mux_get_output(pio, pin, &out))
*config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
@@ -1001,6 +1045,9 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
info->ops->set_drivestrength(pio, pin,
(config & DRIVE_STRENGTH)
>> DRIVE_STRENGTH_SHIFT);
+ if (info->ops->set_slewrate)
+ info->ops->set_slewrate(pio, pin,
+ (config & SLEWRATE) >> SLEWRATE_SHIFT);
} /* for each config */
@@ -1044,6 +1091,7 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
DRIVE_STRENGTH_MED);
DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
DRIVE_STRENGTH_HI);
+ DBG_SHOW_FLAG(SLEWRATE);
DBG_SHOW_FLAG(DEBOUNCE);
if (config & DEBOUNCE) {
val = config >> DEBOUNCE_VAL_SHIFT;
diff --git a/drivers/pinctrl/pinctrl-at91.h b/drivers/pinctrl/pinctrl-at91.h
index 19fc27e66bfd..223620f14b05 100644
--- a/drivers/pinctrl/pinctrl-at91.h
+++ b/drivers/pinctrl/pinctrl-at91.h
@@ -69,6 +69,7 @@
#define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
#define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
+#define SAM9X60_PIO_SLEWR 0x110 /* PIO Slew Rate Control Register */
#define SAM9X60_PIO_DRIVER1 0x118 /* PIO Driver 1 register offset */
#endif
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
index eb81867eac77..8dc10e00c627 100644
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -17,6 +17,7 @@
#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
#define AT91_PINCTRL_OUTPUT (1 << 7)
#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
+#define AT91_PINCTRL_SLEWRATE (1 << 9)
#define AT91_PINCTRL_DEBOUNCE (1 << 16)
#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
@@ -27,6 +28,9 @@
#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
+#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9)
+#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9)
+
#define AT91_PIOA 0
#define AT91_PIOB 1
#define AT91_PIOC 2
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v2 7/7] dt-bindings: add documentation for slew rate
2019-01-31 16:18 ` Claudiu.Beznea
(?)
@ 2019-01-31 16:18 ` Claudiu.Beznea
-1 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add documentation for slew rate.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index c2d51ed86d47..19c255346a49 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -100,6 +100,7 @@ DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
11 - High
OUTPUT (1 << 7): indicate this pin need to be configured as an output.
OUTPUT_VAL (1 << 8): output val (1 = high, 0 = low)
+SLEWRATE (1 << 9): slew rate of the pin: 0 = disable, 1 = enable
DEBOUNCE (1 << 16): indicate this pin needs debounce.
DEBOUNCE_VAL (0x3fff << 17): debounce value.
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v2 7/7] dt-bindings: add documentation for slew rate
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, Claudiu.Beznea, linux-kernel, linux-arm-kernel, devicetree
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add documentation for slew rate.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index c2d51ed86d47..19c255346a49 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -100,6 +100,7 @@ DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
11 - High
OUTPUT (1 << 7): indicate this pin need to be configured as an output.
OUTPUT_VAL (1 << 8): output val (1 = high, 0 = low)
+SLEWRATE (1 << 9): slew rate of the pin: 0 = disable, 1 = enable
DEBOUNCE (1 << 16): indicate this pin needs debounce.
DEBOUNCE_VAL (0x3fff << 17): debounce value.
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v2 7/7] dt-bindings: add documentation for slew rate
@ 2019-01-31 16:18 ` Claudiu.Beznea
0 siblings, 0 replies; 39+ messages in thread
From: Claudiu.Beznea @ 2019-01-31 16:18 UTC (permalink / raw)
To: linus.walleij, robh+dt, mark.rutland, Nicolas.Ferre,
alexandre.belloni, Ludovic.Desroches
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Claudiu.Beznea
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Add documentation for slew rate.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index c2d51ed86d47..19c255346a49 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -100,6 +100,7 @@ DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
11 - High
OUTPUT (1 << 7): indicate this pin need to be configured as an output.
OUTPUT_VAL (1 << 8): output val (1 = high, 0 = low)
+SLEWRATE (1 << 9): slew rate of the pin: 0 = disable, 1 = enable
DEBOUNCE (1 << 16): indicate this pin needs debounce.
DEBOUNCE_VAL (0x3fff << 17): debounce value.
--
2.7.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH v2 0/7] add support for SAM9X60 pin controller
2019-01-31 16:18 ` Claudiu.Beznea
(?)
@ 2019-02-06 8:56 ` Ludovic Desroches
-1 siblings, 0 replies; 39+ messages in thread
From: Ludovic Desroches @ 2019-02-06 8:56 UTC (permalink / raw)
To: Claudiu Beznea - M18063
Cc: linus.walleij, robh+dt, mark.rutland, Nicolas Ferre - M43238,
alexandre.belloni, linux-gpio, devicetree, linux-arm-kernel,
linux-kernel
On Thu, Jan 31, 2019 at 05:18:00PM +0100, Claudiu Beznea - M18063 wrote:
> From: Claudiu Beznea <claudiu.beznea@microchip.com>
Minor comment for patch 1.
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> for the
whole series.
>
> This series adds drive strenght and slew rate support for SAMX60's pin
> controller. For drive strenght we could have 2 values: low, high.
> For slew rate we could have 2 values: enable, disabled.
>
> Besides this I took the chance and adapt the documentation for at91 pinctrl
> driver.
>
> Changes in v2:
> - s/microchip,sam9x60-pictrl/microchip,sam9x60-pinctrl in patches 3/7, 5/7
>
> Claudiu Beznea (7):
> pinctrl: at91: add option to use drive strength bits
> pinctrl: at91: add drive strength support for SAM9X60
> pinctrl: at91: add compatibles for SAM9X60 pin controller
> dt-bindings: add documentation for banks
> dt-bindings: add bindings for SAM9X60
> pinctrl: at91: add slewrate support for SAM9X60
> dt-bindings: add documentation for slew rate
>
> .../bindings/pinctrl/atmel,at91-pinctrl.txt | 27 ++++-
> drivers/pinctrl/pinctrl-at91.c | 134 +++++++++++++++++++--
> drivers/pinctrl/pinctrl-at91.h | 3 +
> include/dt-bindings/pinctrl/at91.h | 4 +
> 4 files changed, 155 insertions(+), 13 deletions(-)
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v2 0/7] add support for SAM9X60 pin controller
@ 2019-02-06 8:56 ` Ludovic Desroches
0 siblings, 0 replies; 39+ messages in thread
From: Ludovic Desroches @ 2019-02-06 8:56 UTC (permalink / raw)
To: Claudiu Beznea - M18063
Cc: mark.rutland, devicetree, alexandre.belloni, linus.walleij,
linux-kernel, linux-gpio, robh+dt, linux-arm-kernel
On Thu, Jan 31, 2019 at 05:18:00PM +0100, Claudiu Beznea - M18063 wrote:
> From: Claudiu Beznea <claudiu.beznea@microchip.com>
Minor comment for patch 1.
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> for the
whole series.
>
> This series adds drive strenght and slew rate support for SAMX60's pin
> controller. For drive strenght we could have 2 values: low, high.
> For slew rate we could have 2 values: enable, disabled.
>
> Besides this I took the chance and adapt the documentation for at91 pinctrl
> driver.
>
> Changes in v2:
> - s/microchip,sam9x60-pictrl/microchip,sam9x60-pinctrl in patches 3/7, 5/7
>
> Claudiu Beznea (7):
> pinctrl: at91: add option to use drive strength bits
> pinctrl: at91: add drive strength support for SAM9X60
> pinctrl: at91: add compatibles for SAM9X60 pin controller
> dt-bindings: add documentation for banks
> dt-bindings: add bindings for SAM9X60
> pinctrl: at91: add slewrate support for SAM9X60
> dt-bindings: add documentation for slew rate
>
> .../bindings/pinctrl/atmel,at91-pinctrl.txt | 27 ++++-
> drivers/pinctrl/pinctrl-at91.c | 134 +++++++++++++++++++--
> drivers/pinctrl/pinctrl-at91.h | 3 +
> include/dt-bindings/pinctrl/at91.h | 4 +
> 4 files changed, 155 insertions(+), 13 deletions(-)
>
> --
> 2.7.4
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v2 0/7] add support for SAM9X60 pin controller
@ 2019-02-06 8:56 ` Ludovic Desroches
0 siblings, 0 replies; 39+ messages in thread
From: Ludovic Desroches @ 2019-02-06 8:56 UTC (permalink / raw)
To: Claudiu Beznea - M18063
Cc: linus.walleij, robh+dt, mark.rutland, Nicolas Ferre - M43238,
alexandre.belloni, linux-gpio, devicetree, linux-arm-kernel,
linux-kernel
On Thu, Jan 31, 2019 at 05:18:00PM +0100, Claudiu Beznea - M18063 wrote:
> From: Claudiu Beznea <claudiu.beznea@microchip.com>
Minor comment for patch 1.
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> for the
whole series.
>
> This series adds drive strenght and slew rate support for SAMX60's pin
> controller. For drive strenght we could have 2 values: low, high.
> For slew rate we could have 2 values: enable, disabled.
>
> Besides this I took the chance and adapt the documentation for at91 pinctrl
> driver.
>
> Changes in v2:
> - s/microchip,sam9x60-pictrl/microchip,sam9x60-pinctrl in patches 3/7, 5/7
>
> Claudiu Beznea (7):
> pinctrl: at91: add option to use drive strength bits
> pinctrl: at91: add drive strength support for SAM9X60
> pinctrl: at91: add compatibles for SAM9X60 pin controller
> dt-bindings: add documentation for banks
> dt-bindings: add bindings for SAM9X60
> pinctrl: at91: add slewrate support for SAM9X60
> dt-bindings: add documentation for slew rate
>
> .../bindings/pinctrl/atmel,at91-pinctrl.txt | 27 ++++-
> drivers/pinctrl/pinctrl-at91.c | 134 +++++++++++++++++++--
> drivers/pinctrl/pinctrl-at91.h | 3 +
> include/dt-bindings/pinctrl/at91.h | 4 +
> 4 files changed, 155 insertions(+), 13 deletions(-)
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 39+ messages in thread