[PATCH 0/6] ARM64: dts: meson-axg: UART DT updates

[PATCH 0/6] ARM64: dts: meson-axg: UART DT updates

[Yixun Lan]

HI Kevin
 These are the UART DT updates for the Meson-AXG platform.

The patch 1, 2 are two general fixes.
Other patches are about adding clock & pinctrl info, then using them.
Last patch enable UART_A which connect to BT module in the S400 board.

Note: 
This series depend on previous UART_AO clock switch patch[1]
also, these patch request clocks, so they need the
tag:meson-clk-for-v4.16-2 from clk-meson's tree in order to compile.

[1] 
http://lkml.kernel.org/r/20171215141741.175985-1-yixun.lan@amlogic.com

Yixun Lan (6):
  ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART
  ARM64: dts: meson-axg: uart: fix address space range
  ARM64: dts: meson-axg: uart: Add the clock info description
  ARM64: dts: meson-axg: uart: Add the pinctrl info description
  arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A
  ARM64: dts: meson-axg: enable the UART_A controller

 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |   9 +++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi     | 108 ++++++++++++++++++++++++-
 2 files changed, 113 insertions(+), 4 deletions(-)

-- 
2.15.1

[PATCH 0/6] ARM64: dts: meson-axg: UART DT updates

[Yixun Lan]

HI Kevin
 These are the UART DT updates for the Meson-AXG platform.

The patch 1, 2 are two general fixes.
Other patches are about adding clock & pinctrl info, then using them.
Last patch enable UART_A which connect to BT module in the S400 board.

Note: 
This series depend on previous UART_AO clock switch patch[1]
also, these patch request clocks, so they need the
tag:meson-clk-for-v4.16-2 from clk-meson's tree in order to compile.

[1] 
http://lkml.kernel.org/r/20171215141741.175985-1-yixun.lan@amlogic.com

Yixun Lan (6):
  ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART
  ARM64: dts: meson-axg: uart: fix address space range
  ARM64: dts: meson-axg: uart: Add the clock info description
  ARM64: dts: meson-axg: uart: Add the pinctrl info description
  arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A
  ARM64: dts: meson-axg: enable the UART_A controller

 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |   9 +++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi     | 108 ++++++++++++++++++++++++-
 2 files changed, 113 insertions(+), 4 deletions(-)

-- 
2.15.1

[PATCH 0/6] ARM64: dts: meson-axg: UART DT updates

[Yixun Lan]

HI Kevin
 These are the UART DT updates for the Meson-AXG platform.

The patch 1, 2 are two general fixes.
Other patches are about adding clock & pinctrl info, then using them.
Last patch enable UART_A which connect to BT module in the S400 board.

Note: 
This series depend on previous UART_AO clock switch patch[1]
also, these patch request clocks, so they need the
tag:meson-clk-for-v4.16-2 from clk-meson's tree in order to compile.

[1] 
http://lkml.kernel.org/r/20171215141741.175985-1-yixun.lan at amlogic.com

Yixun Lan (6):
  ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART
  ARM64: dts: meson-axg: uart: fix address space range
  ARM64: dts: meson-axg: uart: Add the clock info description
  ARM64: dts: meson-axg: uart: Add the pinctrl info description
  arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A
  ARM64: dts: meson-axg: enable the UART_A controller

 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |   9 +++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi     | 108 ++++++++++++++++++++++++-
 2 files changed, 113 insertions(+), 4 deletions(-)

-- 
2.15.1

[PATCH 0/6] ARM64: dts: meson-axg: UART DT updates

[Yixun Lan]

HI Kevin
 These are the UART DT updates for the Meson-AXG platform.

The patch 1, 2 are two general fixes.
Other patches are about adding clock & pinctrl info, then using them.
Last patch enable UART_A which connect to BT module in the S400 board.

Note: 
This series depend on previous UART_AO clock switch patch[1]
also, these patch request clocks, so they need the
tag:meson-clk-for-v4.16-2 from clk-meson's tree in order to compile.

[1] 
http://lkml.kernel.org/r/20171215141741.175985-1-yixun.lan at amlogic.com

Yixun Lan (6):
  ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART
  ARM64: dts: meson-axg: uart: fix address space range
  ARM64: dts: meson-axg: uart: Add the clock info description
  ARM64: dts: meson-axg: uart: Add the pinctrl info description
  arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A
  ARM64: dts: meson-axg: enable the UART_A controller

 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |   9 +++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi     | 108 ++++++++++++++++++++++++-
 2 files changed, 113 insertions(+), 4 deletions(-)

-- 
2.15.1

[PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

For the UART controller in EE domain, they require 'pclk' to work.
Current logic of the code will force to go for legacy clock probe
if it found current compatible string match to 'amlogic,meson-ao-uart'.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index e2b8a9c8bf0b..1c6002b3fe34 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -142,14 +142,14 @@
 			};
 
 			uart_A: serial@24000 {
-				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
+				compatible = "amlogic,meson-gx-uart";
 				reg = <0x0 0x24000 0x0 0x14>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			uart_B: serial@23000 {
-				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
+				compatible = "amlogic,meson-gx-uart";
 				reg = <0x0 0x23000 0x0 0x14>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
-- 
2.15.1

[PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

For the UART controller in EE domain, they require 'pclk' to work.
Current logic of the code will force to go for legacy clock probe
if it found current compatible string match to 'amlogic,meson-ao-uart'.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index e2b8a9c8bf0b..1c6002b3fe34 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -142,14 +142,14 @@
 			};
 
 			uart_A: serial@24000 {
-				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
+				compatible = "amlogic,meson-gx-uart";
 				reg = <0x0 0x24000 0x0 0x14>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			uart_B: serial@23000 {
-				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
+				compatible = "amlogic,meson-gx-uart";
 				reg = <0x0 0x23000 0x0 0x14>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
-- 
2.15.1

[PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

For the UART controller in EE domain, they require 'pclk' to work.
Current logic of the code will force to go for legacy clock probe
if it found current compatible string match to 'amlogic,meson-ao-uart'.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index e2b8a9c8bf0b..1c6002b3fe34 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -142,14 +142,14 @@
 			};
 
 			uart_A: serial at 24000 {
-				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
+				compatible = "amlogic,meson-gx-uart";
 				reg = <0x0 0x24000 0x0 0x14>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			uart_B: serial at 23000 {
-				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
+				compatible = "amlogic,meson-gx-uart";
 				reg = <0x0 0x23000 0x0 0x14>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
-- 
2.15.1

[PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

For the UART controller in EE domain, they require 'pclk' to work.
Current logic of the code will force to go for legacy clock probe
if it found current compatible string match to 'amlogic,meson-ao-uart'.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index e2b8a9c8bf0b..1c6002b3fe34 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -142,14 +142,14 @@
 			};
 
 			uart_A: serial at 24000 {
-				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
+				compatible = "amlogic,meson-gx-uart";
 				reg = <0x0 0x24000 0x0 0x14>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			uart_B: serial at 23000 {
-				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
+				compatible = "amlogic,meson-gx-uart";
 				reg = <0x0 0x23000 0x0 0x14>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
-- 
2.15.1

[PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Yixun Lan]

The address space range is actually 0x18, fixed here.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 1c6002b3fe34..9636a7c5f6ed 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -143,14 +143,14 @@
 
 			uart_A: serial@24000 {
 				compatible = "amlogic,meson-gx-uart";
-				reg = <0x0 0x24000 0x0 0x14>;
+				reg = <0x0 0x24000 0x0 0x18>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			uart_B: serial@23000 {
 				compatible = "amlogic,meson-gx-uart";
-				reg = <0x0 0x23000 0x0 0x14>;
+				reg = <0x0 0x23000 0x0 0x18>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
-- 
2.15.1

[PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Yixun Lan]

The address space range is actually 0x18, fixed here.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 1c6002b3fe34..9636a7c5f6ed 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -143,14 +143,14 @@
 
 			uart_A: serial@24000 {
 				compatible = "amlogic,meson-gx-uart";
-				reg = <0x0 0x24000 0x0 0x14>;
+				reg = <0x0 0x24000 0x0 0x18>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			uart_B: serial@23000 {
 				compatible = "amlogic,meson-gx-uart";
-				reg = <0x0 0x23000 0x0 0x14>;
+				reg = <0x0 0x23000 0x0 0x18>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
-- 
2.15.1

[PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Yixun Lan]

The address space range is actually 0x18, fixed here.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 1c6002b3fe34..9636a7c5f6ed 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -143,14 +143,14 @@
 
 			uart_A: serial at 24000 {
 				compatible = "amlogic,meson-gx-uart";
-				reg = <0x0 0x24000 0x0 0x14>;
+				reg = <0x0 0x24000 0x0 0x18>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			uart_B: serial at 23000 {
 				compatible = "amlogic,meson-gx-uart";
-				reg = <0x0 0x23000 0x0 0x14>;
+				reg = <0x0 0x23000 0x0 0x18>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
-- 
2.15.1

[PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Yixun Lan]

The address space range is actually 0x18, fixed here.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 1c6002b3fe34..9636a7c5f6ed 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -143,14 +143,14 @@
 
 			uart_A: serial at 24000 {
 				compatible = "amlogic,meson-gx-uart";
-				reg = <0x0 0x24000 0x0 0x14>;
+				reg = <0x0 0x24000 0x0 0x18>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
 
 			uart_B: serial at 23000 {
 				compatible = "amlogic,meson-gx-uart";
-				reg = <0x0 0x23000 0x0 0x14>;
+				reg = <0x0 0x23000 0x0 0x18>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
 			};
-- 
2.15.1

[PATCH 3/6] ARM64: dts: meson-axg: uart: Add the clock info description

[Yixun Lan]

Add the clock info description for the EE UART controller.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 9636a7c5f6ed..f6bf01cfff4b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -146,6 +146,8 @@
 				reg = <0x0 0x24000 0x0 0x18>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
+				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
 			};
 
 			uart_B: serial@23000 {
@@ -153,6 +155,8 @@
 				reg = <0x0 0x23000 0x0 0x18>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
+				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
 			};
 		};
 
-- 
2.15.1

[PATCH 3/6] ARM64: dts: meson-axg: uart: Add the clock info description

[Yixun Lan]

Add the clock info description for the EE UART controller.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 9636a7c5f6ed..f6bf01cfff4b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -146,6 +146,8 @@
 				reg = <0x0 0x24000 0x0 0x18>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
+				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
 			};
 
 			uart_B: serial@23000 {
@@ -153,6 +155,8 @@
 				reg = <0x0 0x23000 0x0 0x18>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
+				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
 			};
 		};
 
-- 
2.15.1

[PATCH 3/6] ARM64: dts: meson-axg: uart: Add the clock info description

[Yixun Lan]

Add the clock info description for the EE UART controller.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 9636a7c5f6ed..f6bf01cfff4b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -146,6 +146,8 @@
 				reg = <0x0 0x24000 0x0 0x18>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
+				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
 			};
 
 			uart_B: serial at 23000 {
@@ -153,6 +155,8 @@
 				reg = <0x0 0x23000 0x0 0x18>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
+				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
 			};
 		};
 
-- 
2.15.1

[PATCH 3/6] ARM64: dts: meson-axg: uart: Add the clock info description

[Yixun Lan]

Add the clock info description for the EE UART controller.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 9636a7c5f6ed..f6bf01cfff4b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -146,6 +146,8 @@
 				reg = <0x0 0x24000 0x0 0x18>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
+				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
 			};
 
 			uart_B: serial at 23000 {
@@ -153,6 +155,8 @@
 				reg = <0x0 0x23000 0x0 0x18>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
+				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
 			};
 		};
 
-- 
2.15.1

[PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

Describe the pinctrl info for the UART controller which found
in the Meson-AXG SoCs.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index f6bf01cfff4b..78bb206e2897 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -303,6 +303,70 @@
 						function = "pwm_d";
 					};
 				};
+
+				uart_a_pins: uart_a {
+					mux {
+						groups = "uart_tx_a",
+							"uart_rx_a";
+						function = "uart_a";
+					};
+				};
+
+				uart_a_cts_rts_pins: uart_a_cts_rts {
+					mux {
+						groups = "uart_ctx_a",
+							"uart_rts_a";
+						function = "uart_a";
+					};
+				};
+
+				uart_b_x_pins: uart_b_x {
+					mux {
+						groups = "uart_tx_b_x",
+							"uart_rx_b_x";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+					mux {
+						groups = "uart_cts_b_x",
+							"uart_rts_b_x";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_z_pins: uart_b_z {
+					mux {
+						groups = "uart_tx_b_z",
+							"uart_rx_b_z";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+					mux {
+						groups = "uart_cts_b_z",
+							"uart_rts_b_z";
+						function = "uart_b";
+					};
+				};
+
+				uart_ao_b_z_pins: uart_ao_b_z {
+					mux {
+						groups = "uart_ao_tx_b_z",
+							"uart_ao_rx_b_z";
+						function = "uart_ao_b_groupz";
+					};
+				};
+
+				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+					mux {
+						groups = "uart_ao_cts_b_z",
+							"uart_ao_rts_b_z";
+						function = "uart_ao_b_groupz";
+					};
+				};
 			};
 		};
 
@@ -346,6 +410,38 @@
 					#gpio-cells = <2>;
 					gpio-ranges = <&pinctrl_aobus 0 0 15>;
 				};
+
+				uart_ao_a_pins: uart_ao_a {
+					mux {
+						groups = "uart_ao_tx_a",
+							"uart_ao_rx_a";
+						function = "uart_ao_a";
+					};
+				};
+
+				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
+					mux {
+						groups = "uart_ao_cts_a",
+							"uart_ao_rts_a";
+						function = "uart_ao_a";
+					};
+				};
+
+				uart_ao_b_pins: uart_ao_b {
+					mux {
+						groups = "uart_ao_tx_b",
+							"uart_ao_rx_b";
+						function = "uart_ao_b";
+					};
+				};
+
+				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
+					mux {
+						groups = "uart_ao_cts_b",
+							"uart_ao_rts_b";
+						function = "uart_ao_b";
+					};
+				};
 			};
 
 			pwm_AO_ab: pwm@7000 {
-- 
2.15.1

[PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

Describe the pinctrl info for the UART controller which found
in the Meson-AXG SoCs.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index f6bf01cfff4b..78bb206e2897 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -303,6 +303,70 @@
 						function = "pwm_d";
 					};
 				};
+
+				uart_a_pins: uart_a {
+					mux {
+						groups = "uart_tx_a",
+							"uart_rx_a";
+						function = "uart_a";
+					};
+				};
+
+				uart_a_cts_rts_pins: uart_a_cts_rts {
+					mux {
+						groups = "uart_ctx_a",
+							"uart_rts_a";
+						function = "uart_a";
+					};
+				};
+
+				uart_b_x_pins: uart_b_x {
+					mux {
+						groups = "uart_tx_b_x",
+							"uart_rx_b_x";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+					mux {
+						groups = "uart_cts_b_x",
+							"uart_rts_b_x";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_z_pins: uart_b_z {
+					mux {
+						groups = "uart_tx_b_z",
+							"uart_rx_b_z";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+					mux {
+						groups = "uart_cts_b_z",
+							"uart_rts_b_z";
+						function = "uart_b";
+					};
+				};
+
+				uart_ao_b_z_pins: uart_ao_b_z {
+					mux {
+						groups = "uart_ao_tx_b_z",
+							"uart_ao_rx_b_z";
+						function = "uart_ao_b_groupz";
+					};
+				};
+
+				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+					mux {
+						groups = "uart_ao_cts_b_z",
+							"uart_ao_rts_b_z";
+						function = "uart_ao_b_groupz";
+					};
+				};
 			};
 		};
 
@@ -346,6 +410,38 @@
 					#gpio-cells = <2>;
 					gpio-ranges = <&pinctrl_aobus 0 0 15>;
 				};
+
+				uart_ao_a_pins: uart_ao_a {
+					mux {
+						groups = "uart_ao_tx_a",
+							"uart_ao_rx_a";
+						function = "uart_ao_a";
+					};
+				};
+
+				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
+					mux {
+						groups = "uart_ao_cts_a",
+							"uart_ao_rts_a";
+						function = "uart_ao_a";
+					};
+				};
+
+				uart_ao_b_pins: uart_ao_b {
+					mux {
+						groups = "uart_ao_tx_b",
+							"uart_ao_rx_b";
+						function = "uart_ao_b";
+					};
+				};
+
+				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
+					mux {
+						groups = "uart_ao_cts_b",
+							"uart_ao_rts_b";
+						function = "uart_ao_b";
+					};
+				};
 			};
 
 			pwm_AO_ab: pwm@7000 {
-- 
2.15.1

[PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

Describe the pinctrl info for the UART controller which found
in the Meson-AXG SoCs.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index f6bf01cfff4b..78bb206e2897 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -303,6 +303,70 @@
 						function = "pwm_d";
 					};
 				};
+
+				uart_a_pins: uart_a {
+					mux {
+						groups = "uart_tx_a",
+							"uart_rx_a";
+						function = "uart_a";
+					};
+				};
+
+				uart_a_cts_rts_pins: uart_a_cts_rts {
+					mux {
+						groups = "uart_ctx_a",
+							"uart_rts_a";
+						function = "uart_a";
+					};
+				};
+
+				uart_b_x_pins: uart_b_x {
+					mux {
+						groups = "uart_tx_b_x",
+							"uart_rx_b_x";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+					mux {
+						groups = "uart_cts_b_x",
+							"uart_rts_b_x";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_z_pins: uart_b_z {
+					mux {
+						groups = "uart_tx_b_z",
+							"uart_rx_b_z";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+					mux {
+						groups = "uart_cts_b_z",
+							"uart_rts_b_z";
+						function = "uart_b";
+					};
+				};
+
+				uart_ao_b_z_pins: uart_ao_b_z {
+					mux {
+						groups = "uart_ao_tx_b_z",
+							"uart_ao_rx_b_z";
+						function = "uart_ao_b_groupz";
+					};
+				};
+
+				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+					mux {
+						groups = "uart_ao_cts_b_z",
+							"uart_ao_rts_b_z";
+						function = "uart_ao_b_groupz";
+					};
+				};
 			};
 		};
 
@@ -346,6 +410,38 @@
 					#gpio-cells = <2>;
 					gpio-ranges = <&pinctrl_aobus 0 0 15>;
 				};
+
+				uart_ao_a_pins: uart_ao_a {
+					mux {
+						groups = "uart_ao_tx_a",
+							"uart_ao_rx_a";
+						function = "uart_ao_a";
+					};
+				};
+
+				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
+					mux {
+						groups = "uart_ao_cts_a",
+							"uart_ao_rts_a";
+						function = "uart_ao_a";
+					};
+				};
+
+				uart_ao_b_pins: uart_ao_b {
+					mux {
+						groups = "uart_ao_tx_b",
+							"uart_ao_rx_b";
+						function = "uart_ao_b";
+					};
+				};
+
+				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
+					mux {
+						groups = "uart_ao_cts_b",
+							"uart_ao_rts_b";
+						function = "uart_ao_b";
+					};
+				};
 			};
 
 			pwm_AO_ab: pwm at 7000 {
-- 
2.15.1

[PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

Describe the pinctrl info for the UART controller which found
in the Meson-AXG SoCs.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index f6bf01cfff4b..78bb206e2897 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -303,6 +303,70 @@
 						function = "pwm_d";
 					};
 				};
+
+				uart_a_pins: uart_a {
+					mux {
+						groups = "uart_tx_a",
+							"uart_rx_a";
+						function = "uart_a";
+					};
+				};
+
+				uart_a_cts_rts_pins: uart_a_cts_rts {
+					mux {
+						groups = "uart_ctx_a",
+							"uart_rts_a";
+						function = "uart_a";
+					};
+				};
+
+				uart_b_x_pins: uart_b_x {
+					mux {
+						groups = "uart_tx_b_x",
+							"uart_rx_b_x";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+					mux {
+						groups = "uart_cts_b_x",
+							"uart_rts_b_x";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_z_pins: uart_b_z {
+					mux {
+						groups = "uart_tx_b_z",
+							"uart_rx_b_z";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+					mux {
+						groups = "uart_cts_b_z",
+							"uart_rts_b_z";
+						function = "uart_b";
+					};
+				};
+
+				uart_ao_b_z_pins: uart_ao_b_z {
+					mux {
+						groups = "uart_ao_tx_b_z",
+							"uart_ao_rx_b_z";
+						function = "uart_ao_b_groupz";
+					};
+				};
+
+				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+					mux {
+						groups = "uart_ao_cts_b_z",
+							"uart_ao_rts_b_z";
+						function = "uart_ao_b_groupz";
+					};
+				};
 			};
 		};
 
@@ -346,6 +410,38 @@
 					#gpio-cells = <2>;
 					gpio-ranges = <&pinctrl_aobus 0 0 15>;
 				};
+
+				uart_ao_a_pins: uart_ao_a {
+					mux {
+						groups = "uart_ao_tx_a",
+							"uart_ao_rx_a";
+						function = "uart_ao_a";
+					};
+				};
+
+				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
+					mux {
+						groups = "uart_ao_cts_a",
+							"uart_ao_rts_a";
+						function = "uart_ao_a";
+					};
+				};
+
+				uart_ao_b_pins: uart_ao_b {
+					mux {
+						groups = "uart_ao_tx_b",
+							"uart_ao_rx_b";
+						function = "uart_ao_b";
+					};
+				};
+
+				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
+					mux {
+						groups = "uart_ao_cts_b",
+							"uart_ao_rts_b";
+						function = "uart_ao_b";
+					};
+				};
 			};
 
 			pwm_AO_ab: pwm at 7000 {
-- 
2.15.1

[PATCH 5/6] arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Yixun Lan]

Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we my rely on bootloader for the initialization.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..2b79be356996 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -19,4 +19,6 @@
 
 &uart_AO {
 	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
 };
-- 
2.15.1

[PATCH 5/6] arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Yixun Lan]

Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we my rely on bootloader for the initialization.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..2b79be356996 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -19,4 +19,6 @@
 
 &uart_AO {
 	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
 };
-- 
2.15.1

[PATCH 5/6] arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Yixun Lan]

Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we my rely on bootloader for the initialization.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..2b79be356996 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -19,4 +19,6 @@
 
 &uart_AO {
 	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
 };
-- 
2.15.1

[PATCH 5/6] arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Yixun Lan]

Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we my rely on bootloader for the initialization.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..2b79be356996 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -19,4 +19,6 @@
 
 &uart_AO {
 	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
 };
-- 
2.15.1

[PATCH 6/6] ARM64: dts: meson-axg: enable the UART_A controller

[Yixun Lan]

The UART_A is connect to a BT module in the S400 board.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 2b79be356996..7e03b8da4856 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -14,9 +14,16 @@
 
 	aliases {
 		serial0 = &uart_AO;
+		serial1 = &uart_A;
 	};
 };
 
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>;
+	pinctrl-names = "default";
+};
+
 &uart_AO {
 	status = "okay";
 	pinctrl-0 = <&uart_ao_a_pins>;
-- 
2.15.1

[PATCH 6/6] ARM64: dts: meson-axg: enable the UART_A controller

[Yixun Lan]

The UART_A is connect to a BT module in the S400 board.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 2b79be356996..7e03b8da4856 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -14,9 +14,16 @@
 
 	aliases {
 		serial0 = &uart_AO;
+		serial1 = &uart_A;
 	};
 };
 
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>;
+	pinctrl-names = "default";
+};
+
 &uart_AO {
 	status = "okay";
 	pinctrl-0 = <&uart_ao_a_pins>;
-- 
2.15.1

[PATCH 6/6] ARM64: dts: meson-axg: enable the UART_A controller

[Yixun Lan]

The UART_A is connect to a BT module in the S400 board.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 2b79be356996..7e03b8da4856 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -14,9 +14,16 @@
 
 	aliases {
 		serial0 = &uart_AO;
+		serial1 = &uart_A;
 	};
 };
 
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>;
+	pinctrl-names = "default";
+};
+
 &uart_AO {
 	status = "okay";
 	pinctrl-0 = <&uart_ao_a_pins>;
-- 
2.15.1

[PATCH 6/6] ARM64: dts: meson-axg: enable the UART_A controller

[Yixun Lan]

The UART_A is connect to a BT module in the S400 board.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 2b79be356996..7e03b8da4856 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -14,9 +14,16 @@
 
 	aliases {
 		serial0 = &uart_AO;
+		serial1 = &uart_A;
 	};
 };
 
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>;
+	pinctrl-names = "default";
+};
+
 &uart_AO {
 	status = "okay";
 	pinctrl-0 = <&uart_ao_a_pins>;
-- 
2.15.1

Re: [PATCH 6/6] ARM64: dts: meson-axg: enable the UART_A controller

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> The UART_A is connect to a BT module in the S400 board.

The UART_A is connected to a BT module on the S400 board.
                     --                --

Apart from this:
Acked-by: Jerome Brunet <jbrunet@baylibre.com>


> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> index 2b79be356996..7e03b8da4856 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> @@ -14,9 +14,16 @@
>  
>  	aliases {
>  		serial0 = &uart_AO;
> +		serial1 = &uart_A;
>  	};
>  };
>  
> +&uart_A {
> +	status = "okay";
> +	pinctrl-0 = <&uart_a_pins>;
> +	pinctrl-names = "default";
> +};
> +
>  &uart_AO {
>  	status = "okay";
>  	pinctrl-0 = <&uart_ao_a_pins>;

Re: [PATCH 6/6] ARM64: dts: meson-axg: enable the UART_A controller

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> The UART_A is connect to a BT module in the S400 board.

The UART_A is connected to a BT module on the S400 board.
                     --                --

Apart from this:
Acked-by: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>


> 
> Signed-off-by: Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> index 2b79be356996..7e03b8da4856 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> @@ -14,9 +14,16 @@
>  
>  	aliases {
>  		serial0 = &uart_AO;
> +		serial1 = &uart_A;
>  	};
>  };
>  
> +&uart_A {
> +	status = "okay";
> +	pinctrl-0 = <&uart_a_pins>;
> +	pinctrl-names = "default";
> +};
> +
>  &uart_AO {
>  	status = "okay";
>  	pinctrl-0 = <&uart_ao_a_pins>;

--
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[PATCH 6/6] ARM64: dts: meson-axg: enable the UART_A controller

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> The UART_A is connect to a BT module in the S400 board.

The UART_A is connected to a BT module on the S400 board.
                     --                --

Apart from this:
Acked-by: Jerome Brunet <jbrunet@baylibre.com>


> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> index 2b79be356996..7e03b8da4856 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> @@ -14,9 +14,16 @@
>  
>  	aliases {
>  		serial0 = &uart_AO;
> +		serial1 = &uart_A;
>  	};
>  };
>  
> +&uart_A {
> +	status = "okay";
> +	pinctrl-0 = <&uart_a_pins>;
> +	pinctrl-names = "default";
> +};
> +
>  &uart_AO {
>  	status = "okay";
>  	pinctrl-0 = <&uart_ao_a_pins>;

[PATCH 6/6] ARM64: dts: meson-axg: enable the UART_A controller

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> The UART_A is connect to a BT module in the S400 board.

The UART_A is connected to a BT module on the S400 board.
                     --                --

Apart from this:
Acked-by: Jerome Brunet <jbrunet@baylibre.com>


> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> index 2b79be356996..7e03b8da4856 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> @@ -14,9 +14,16 @@
>  
>  	aliases {
>  		serial0 = &uart_AO;
> +		serial1 = &uart_A;
>  	};
>  };
>  
> +&uart_A {
> +	status = "okay";
> +	pinctrl-0 = <&uart_a_pins>;
> +	pinctrl-names = "default";
> +};
> +
>  &uart_AO {
>  	status = "okay";
>  	pinctrl-0 = <&uart_ao_a_pins>;

Re: [PATCH 5/6] arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> Explictly request the pinctrl info for the UART_AO_A controller,
> otherwise we my rely on bootloader for the initialization.
  "we may" ? --^

> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>

Please be consistent in the title
s/arm64/ARM64

Otherwise looks good once patch #4 is fixed

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

> ---
>  arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> index 70eca1f8736a..2b79be356996 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> @@ -19,4 +19,6 @@
>  
>  &uart_AO {
>  	status = "okay";
> +	pinctrl-0 = <&uart_ao_a_pins>;
> +	pinctrl-names = "default";
>  };

Re: [PATCH 5/6] arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> Explictly request the pinctrl info for the UART_AO_A controller,
> otherwise we my rely on bootloader for the initialization.
  "we may" ? --^

> 
> Signed-off-by: Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>

Please be consistent in the title
s/arm64/ARM64

Otherwise looks good once patch #4 is fixed

Acked-by: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>

> ---
>  arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> index 70eca1f8736a..2b79be356996 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> @@ -19,4 +19,6 @@
>  
>  &uart_AO {
>  	status = "okay";
> +	pinctrl-0 = <&uart_ao_a_pins>;
> +	pinctrl-names = "default";
>  };

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH 5/6] arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> Explictly request the pinctrl info for the UART_AO_A controller,
> otherwise we my rely on bootloader for the initialization.
  "we may" ? --^

> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>

Please be consistent in the title
s/arm64/ARM64

Otherwise looks good once patch #4 is fixed

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

> ---
>  arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> index 70eca1f8736a..2b79be356996 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> @@ -19,4 +19,6 @@
>  
>  &uart_AO {
>  	status = "okay";
> +	pinctrl-0 = <&uart_ao_a_pins>;
> +	pinctrl-names = "default";
>  };

[PATCH 5/6] arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> Explictly request the pinctrl info for the UART_AO_A controller,
> otherwise we my rely on bootloader for the initialization.
  "we may" ? --^

> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>

Please be consistent in the title
s/arm64/ARM64

Otherwise looks good once patch #4 is fixed

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

> ---
>  arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> index 70eca1f8736a..2b79be356996 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> @@ -19,4 +19,6 @@
>  
>  &uart_AO {
>  	status = "okay";
> +	pinctrl-0 = <&uart_ao_a_pins>;
> +	pinctrl-names = "default";
>  };

Re: [PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> Describe the pinctrl info for the UART controller which 

is

> found
> in the Meson-AXG SoCs.

Yixun,

Could you please review this patch again. Some "strings" used here will
obviously not work. I've picked up a few but I'm pretty sure there are other ...

Thanks

> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++++++++++++++++++++++++++++++
>  1 file changed, 96 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index f6bf01cfff4b..78bb206e2897 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -303,6 +303,70 @@
>  						function = "pwm_d";
>  					};
>  				};
> +
> +				uart_a_pins: uart_a {
> +					mux {
> +						groups = "uart_tx_a",
> +							"uart_rx_a";
> +						function = "uart_a";
> +					};
> +				};
> +
> +				uart_a_cts_rts_pins: uart_a_cts_rts {
> +					mux {
> +						groups = "uart_ctx_a",

uart_ctx_a does not exist in pinctrl

> +							"uart_rts_a";
> +						function = "uart_a";
> +					};
> +				};
> +
> +				uart_b_x_pins: uart_b_x {
> +					mux {
> +						groups = "uart_tx_b_x",
> +							"uart_rx_b_x";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
> +					mux {
> +						groups = "uart_cts_b_x",
> +							"uart_rts_b_x";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_b_z_pins: uart_b_z {
> +					mux {
> +						groups = "uart_tx_b_z",
> +							"uart_rx_b_z";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
> +					mux {
> +						groups = "uart_cts_b_z",
> +							"uart_rts_b_z";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_ao_b_z_pins: uart_ao_b_z {
> +					mux {
> +						groups = "uart_ao_tx_b_z",
> +							"uart_ao_rx_b_z";
> +						function = "uart_ao_b_groupz";

"uart_ao_b_groupz" function does not exist in pinctrl

> +					};
> +				};
> +
> +				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
> +					mux {
> +						groups = "uart_ao_cts_b_z",
> +							"uart_ao_rts_b_z";
> +						function = "uart_ao_b_groupz";
> +					};
> +				};
>  			};
>  		};
>  
> @@ -346,6 +410,38 @@
>  					#gpio-cells = <2>;
>  					gpio-ranges = <&pinctrl_aobus 0 0 15>;
>  				};
> +
> +				uart_ao_a_pins: uart_ao_a {
> +					mux {
> +						groups = "uart_ao_tx_a",
> +							"uart_ao_rx_a";
> +						function = "uart_ao_a";
> +					};
> +				};
> +
> +				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
> +					mux {
> +						groups = "uart_ao_cts_a",
> +							"uart_ao_rts_a";
> +						function = "uart_ao_a";
> +					};
> +				};
> +
> +				uart_ao_b_pins: uart_ao_b {
> +					mux {
> +						groups = "uart_ao_tx_b",
> +							"uart_ao_rx_b";
> +						function = "uart_ao_b";
> +					};
> +				};
> +
> +				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
> +					mux {
> +						groups = "uart_ao_cts_b",
> +							"uart_ao_rts_b";
> +						function = "uart_ao_b";
> +					};
> +				};
>  			};
>  
>  			pwm_AO_ab: pwm@7000 {

Re: [PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> Describe the pinctrl info for the UART controller which 

is

> found
> in the Meson-AXG SoCs.

Yixun,

Could you please review this patch again. Some "strings" used here will
obviously not work. I've picked up a few but I'm pretty sure there are other ...

Thanks

> 
> Signed-off-by: Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++++++++++++++++++++++++++++++
>  1 file changed, 96 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index f6bf01cfff4b..78bb206e2897 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -303,6 +303,70 @@
>  						function = "pwm_d";
>  					};
>  				};
> +
> +				uart_a_pins: uart_a {
> +					mux {
> +						groups = "uart_tx_a",
> +							"uart_rx_a";
> +						function = "uart_a";
> +					};
> +				};
> +
> +				uart_a_cts_rts_pins: uart_a_cts_rts {
> +					mux {
> +						groups = "uart_ctx_a",

uart_ctx_a does not exist in pinctrl

> +							"uart_rts_a";
> +						function = "uart_a";
> +					};
> +				};
> +
> +				uart_b_x_pins: uart_b_x {
> +					mux {
> +						groups = "uart_tx_b_x",
> +							"uart_rx_b_x";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
> +					mux {
> +						groups = "uart_cts_b_x",
> +							"uart_rts_b_x";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_b_z_pins: uart_b_z {
> +					mux {
> +						groups = "uart_tx_b_z",
> +							"uart_rx_b_z";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
> +					mux {
> +						groups = "uart_cts_b_z",
> +							"uart_rts_b_z";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_ao_b_z_pins: uart_ao_b_z {
> +					mux {
> +						groups = "uart_ao_tx_b_z",
> +							"uart_ao_rx_b_z";
> +						function = "uart_ao_b_groupz";

"uart_ao_b_groupz" function does not exist in pinctrl

> +					};
> +				};
> +
> +				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
> +					mux {
> +						groups = "uart_ao_cts_b_z",
> +							"uart_ao_rts_b_z";
> +						function = "uart_ao_b_groupz";
> +					};
> +				};
>  			};
>  		};
>  
> @@ -346,6 +410,38 @@
>  					#gpio-cells = <2>;
>  					gpio-ranges = <&pinctrl_aobus 0 0 15>;
>  				};
> +
> +				uart_ao_a_pins: uart_ao_a {
> +					mux {
> +						groups = "uart_ao_tx_a",
> +							"uart_ao_rx_a";
> +						function = "uart_ao_a";
> +					};
> +				};
> +
> +				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
> +					mux {
> +						groups = "uart_ao_cts_a",
> +							"uart_ao_rts_a";
> +						function = "uart_ao_a";
> +					};
> +				};
> +
> +				uart_ao_b_pins: uart_ao_b {
> +					mux {
> +						groups = "uart_ao_tx_b",
> +							"uart_ao_rx_b";
> +						function = "uart_ao_b";
> +					};
> +				};
> +
> +				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
> +					mux {
> +						groups = "uart_ao_cts_b",
> +							"uart_ao_rts_b";
> +						function = "uart_ao_b";
> +					};
> +				};
>  			};
>  
>  			pwm_AO_ab: pwm@7000 {

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[PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> Describe the pinctrl info for the UART controller which 

is

> found
> in the Meson-AXG SoCs.

Yixun,

Could you please review this patch again. Some "strings" used here will
obviously not work. I've picked up a few but I'm pretty sure there are other ...

Thanks

> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++++++++++++++++++++++++++++++
>  1 file changed, 96 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index f6bf01cfff4b..78bb206e2897 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -303,6 +303,70 @@
>  						function = "pwm_d";
>  					};
>  				};
> +
> +				uart_a_pins: uart_a {
> +					mux {
> +						groups = "uart_tx_a",
> +							"uart_rx_a";
> +						function = "uart_a";
> +					};
> +				};
> +
> +				uart_a_cts_rts_pins: uart_a_cts_rts {
> +					mux {
> +						groups = "uart_ctx_a",

uart_ctx_a does not exist in pinctrl

> +							"uart_rts_a";
> +						function = "uart_a";
> +					};
> +				};
> +
> +				uart_b_x_pins: uart_b_x {
> +					mux {
> +						groups = "uart_tx_b_x",
> +							"uart_rx_b_x";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
> +					mux {
> +						groups = "uart_cts_b_x",
> +							"uart_rts_b_x";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_b_z_pins: uart_b_z {
> +					mux {
> +						groups = "uart_tx_b_z",
> +							"uart_rx_b_z";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
> +					mux {
> +						groups = "uart_cts_b_z",
> +							"uart_rts_b_z";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_ao_b_z_pins: uart_ao_b_z {
> +					mux {
> +						groups = "uart_ao_tx_b_z",
> +							"uart_ao_rx_b_z";
> +						function = "uart_ao_b_groupz";

"uart_ao_b_groupz" function does not exist in pinctrl

> +					};
> +				};
> +
> +				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
> +					mux {
> +						groups = "uart_ao_cts_b_z",
> +							"uart_ao_rts_b_z";
> +						function = "uart_ao_b_groupz";
> +					};
> +				};
>  			};
>  		};
>  
> @@ -346,6 +410,38 @@
>  					#gpio-cells = <2>;
>  					gpio-ranges = <&pinctrl_aobus 0 0 15>;
>  				};
> +
> +				uart_ao_a_pins: uart_ao_a {
> +					mux {
> +						groups = "uart_ao_tx_a",
> +							"uart_ao_rx_a";
> +						function = "uart_ao_a";
> +					};
> +				};
> +
> +				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
> +					mux {
> +						groups = "uart_ao_cts_a",
> +							"uart_ao_rts_a";
> +						function = "uart_ao_a";
> +					};
> +				};
> +
> +				uart_ao_b_pins: uart_ao_b {
> +					mux {
> +						groups = "uart_ao_tx_b",
> +							"uart_ao_rx_b";
> +						function = "uart_ao_b";
> +					};
> +				};
> +
> +				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
> +					mux {
> +						groups = "uart_ao_cts_b",
> +							"uart_ao_rts_b";
> +						function = "uart_ao_b";
> +					};
> +				};
>  			};
>  
>  			pwm_AO_ab: pwm at 7000 {

[PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> Describe the pinctrl info for the UART controller which 

is

> found
> in the Meson-AXG SoCs.

Yixun,

Could you please review this patch again. Some "strings" used here will
obviously not work. I've picked up a few but I'm pretty sure there are other ...

Thanks

> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++++++++++++++++++++++++++++++
>  1 file changed, 96 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index f6bf01cfff4b..78bb206e2897 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -303,6 +303,70 @@
>  						function = "pwm_d";
>  					};
>  				};
> +
> +				uart_a_pins: uart_a {
> +					mux {
> +						groups = "uart_tx_a",
> +							"uart_rx_a";
> +						function = "uart_a";
> +					};
> +				};
> +
> +				uart_a_cts_rts_pins: uart_a_cts_rts {
> +					mux {
> +						groups = "uart_ctx_a",

uart_ctx_a does not exist in pinctrl

> +							"uart_rts_a";
> +						function = "uart_a";
> +					};
> +				};
> +
> +				uart_b_x_pins: uart_b_x {
> +					mux {
> +						groups = "uart_tx_b_x",
> +							"uart_rx_b_x";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
> +					mux {
> +						groups = "uart_cts_b_x",
> +							"uart_rts_b_x";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_b_z_pins: uart_b_z {
> +					mux {
> +						groups = "uart_tx_b_z",
> +							"uart_rx_b_z";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
> +					mux {
> +						groups = "uart_cts_b_z",
> +							"uart_rts_b_z";
> +						function = "uart_b";
> +					};
> +				};
> +
> +				uart_ao_b_z_pins: uart_ao_b_z {
> +					mux {
> +						groups = "uart_ao_tx_b_z",
> +							"uart_ao_rx_b_z";
> +						function = "uart_ao_b_groupz";

"uart_ao_b_groupz" function does not exist in pinctrl

> +					};
> +				};
> +
> +				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
> +					mux {
> +						groups = "uart_ao_cts_b_z",
> +							"uart_ao_rts_b_z";
> +						function = "uart_ao_b_groupz";
> +					};
> +				};
>  			};
>  		};
>  
> @@ -346,6 +410,38 @@
>  					#gpio-cells = <2>;
>  					gpio-ranges = <&pinctrl_aobus 0 0 15>;
>  				};
> +
> +				uart_ao_a_pins: uart_ao_a {
> +					mux {
> +						groups = "uart_ao_tx_a",
> +							"uart_ao_rx_a";
> +						function = "uart_ao_a";
> +					};
> +				};
> +
> +				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
> +					mux {
> +						groups = "uart_ao_cts_a",
> +							"uart_ao_rts_a";
> +						function = "uart_ao_a";
> +					};
> +				};
> +
> +				uart_ao_b_pins: uart_ao_b {
> +					mux {
> +						groups = "uart_ao_tx_b",
> +							"uart_ao_rx_b";
> +						function = "uart_ao_b";
> +					};
> +				};
> +
> +				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
> +					mux {
> +						groups = "uart_ao_cts_b",
> +							"uart_ao_rts_b";
> +						function = "uart_ao_b";
> +					};
> +				};
>  			};
>  
>  			pwm_AO_ab: pwm at 7000 {

Re: [PATCH 3/6] ARM64: dts: meson-axg: uart: Add the clock info description

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> Add the clock info description for the EE UART controller.
> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index 9636a7c5f6ed..f6bf01cfff4b 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -146,6 +146,8 @@
>  				reg = <0x0 0x24000 0x0 0x18>;
>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
> +				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
> +				clock-names = "xtal", "pclk", "baud";

This should squashed with change #1, where you remove amlogic,meson-uartcompatible. 

Otherwise uart is going to be broken between these patches.

>  			};
>  
>  			uart_B: serial@23000 {
> @@ -153,6 +155,8 @@
>  				reg = <0x0 0x23000 0x0 0x18>;
>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
> +				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
> +				clock-names = "xtal", "pclk", "baud";
>  			};
>  		};
>  

[PATCH 3/6] ARM64: dts: meson-axg: uart: Add the clock info description

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> Add the clock info description for the EE UART controller.
> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index 9636a7c5f6ed..f6bf01cfff4b 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -146,6 +146,8 @@
>  				reg = <0x0 0x24000 0x0 0x18>;
>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
> +				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
> +				clock-names = "xtal", "pclk", "baud";

This should squashed with change #1, where you remove amlogic,meson-uartcompatible. 

Otherwise uart is going to be broken between these patches.

>  			};
>  
>  			uart_B: serial at 23000 {
> @@ -153,6 +155,8 @@
>  				reg = <0x0 0x23000 0x0 0x18>;
>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
> +				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
> +				clock-names = "xtal", "pclk", "baud";
>  			};
>  		};
>  

[PATCH 3/6] ARM64: dts: meson-axg: uart: Add the clock info description

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> Add the clock info description for the EE UART controller.
> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index 9636a7c5f6ed..f6bf01cfff4b 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -146,6 +146,8 @@
>  				reg = <0x0 0x24000 0x0 0x18>;
>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
> +				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
> +				clock-names = "xtal", "pclk", "baud";

This should squashed with change #1, where you remove amlogic,meson-uartcompatible. 

Otherwise uart is going to be broken between these patches.

>  			};
>  
>  			uart_B: serial at 23000 {
> @@ -153,6 +155,8 @@
>  				reg = <0x0 0x23000 0x0 0x18>;
>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
> +				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
> +				clock-names = "xtal", "pclk", "baud";
>  			};
>  		};
>  

Re: [PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> The address space range is actually 0x18, fixed here.

Isn't it the same for other meson SoC ? If they are compatible, it should.
Could you please re-submit this change addressing all the required platforms ?

> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index 1c6002b3fe34..9636a7c5f6ed 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -143,14 +143,14 @@
>  
>  			uart_A: serial@24000 {
>  				compatible = "amlogic,meson-gx-uart";
> -				reg = <0x0 0x24000 0x0 0x14>;
> +				reg = <0x0 0x24000 0x0 0x18>;
>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
>  			};
>  
>  			uart_B: serial@23000 {
>  				compatible = "amlogic,meson-gx-uart";
> -				reg = <0x0 0x23000 0x0 0x14>;
> +				reg = <0x0 0x23000 0x0 0x18>;
>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
>  			};

[PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> The address space range is actually 0x18, fixed here.

Isn't it the same for other meson SoC ? If they are compatible, it should.
Could you please re-submit this change addressing all the required platforms ?

> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index 1c6002b3fe34..9636a7c5f6ed 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -143,14 +143,14 @@
>  
>  			uart_A: serial at 24000 {
>  				compatible = "amlogic,meson-gx-uart";
> -				reg = <0x0 0x24000 0x0 0x14>;
> +				reg = <0x0 0x24000 0x0 0x18>;
>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
>  			};
>  
>  			uart_B: serial at 23000 {
>  				compatible = "amlogic,meson-gx-uart";
> -				reg = <0x0 0x23000 0x0 0x14>;
> +				reg = <0x0 0x23000 0x0 0x18>;
>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
>  			};

[PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> The address space range is actually 0x18, fixed here.

Isn't it the same for other meson SoC ? If they are compatible, it should.
Could you please re-submit this change addressing all the required platforms ?

> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index 1c6002b3fe34..9636a7c5f6ed 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -143,14 +143,14 @@
>  
>  			uart_A: serial at 24000 {
>  				compatible = "amlogic,meson-gx-uart";
> -				reg = <0x0 0x24000 0x0 0x14>;
> +				reg = <0x0 0x24000 0x0 0x18>;
>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
>  			};
>  
>  			uart_B: serial at 23000 {
>  				compatible = "amlogic,meson-gx-uart";
> -				reg = <0x0 0x23000 0x0 0x14>;
> +				reg = <0x0 0x23000 0x0 0x18>;
>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
>  			};

Re: [PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> For the UART controller in EE domain, they require 'pclk' to work.

they ? "the driver" maybe ?

> Current logic of the code will force to go for legacy clock probe
> if it found current compatible string match to 'amlogic,meson-ao-uart'.

did you mean "amlogic,meson-uart" instead ?

Apart from that

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index e2b8a9c8bf0b..1c6002b3fe34 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -142,14 +142,14 @@
>  			};
>  
>  			uart_A: serial@24000 {
> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
> +				compatible = "amlogic,meson-gx-uart";
>  				reg = <0x0 0x24000 0x0 0x14>;
>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
>  			};
>  
>  			uart_B: serial@23000 {
> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
> +				compatible = "amlogic,meson-gx-uart";
>  				reg = <0x0 0x23000 0x0 0x14>;
>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";

Re: [PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> For the UART controller in EE domain, they require 'pclk' to work.

they ? "the driver" maybe ?

> Current logic of the code will force to go for legacy clock probe
> if it found current compatible string match to 'amlogic,meson-ao-uart'.

did you mean "amlogic,meson-uart" instead ?

Apart from that

Acked-by: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>

> 
> Signed-off-by: Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index e2b8a9c8bf0b..1c6002b3fe34 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -142,14 +142,14 @@
>  			};
>  
>  			uart_A: serial@24000 {
> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
> +				compatible = "amlogic,meson-gx-uart";
>  				reg = <0x0 0x24000 0x0 0x14>;
>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
>  			};
>  
>  			uart_B: serial@23000 {
> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
> +				compatible = "amlogic,meson-gx-uart";
>  				reg = <0x0 0x23000 0x0 0x14>;
>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";

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[PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> For the UART controller in EE domain, they require 'pclk' to work.

they ? "the driver" maybe ?

> Current logic of the code will force to go for legacy clock probe
> if it found current compatible string match to 'amlogic,meson-ao-uart'.

did you mean "amlogic,meson-uart" instead ?

Apart from that

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index e2b8a9c8bf0b..1c6002b3fe34 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -142,14 +142,14 @@
>  			};
>  
>  			uart_A: serial at 24000 {
> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
> +				compatible = "amlogic,meson-gx-uart";
>  				reg = <0x0 0x24000 0x0 0x14>;
>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
>  			};
>  
>  			uart_B: serial at 23000 {
> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
> +				compatible = "amlogic,meson-gx-uart";
>  				reg = <0x0 0x23000 0x0 0x14>;
>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";

[PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Jerome Brunet]

On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
> For the UART controller in EE domain, they require 'pclk' to work.

they ? "the driver" maybe ?

> Current logic of the code will force to go for legacy clock probe
> if it found current compatible string match to 'amlogic,meson-ao-uart'.

did you mean "amlogic,meson-uart" instead ?

Apart from that

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index e2b8a9c8bf0b..1c6002b3fe34 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -142,14 +142,14 @@
>  			};
>  
>  			uart_A: serial at 24000 {
> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
> +				compatible = "amlogic,meson-gx-uart";
>  				reg = <0x0 0x24000 0x0 0x14>;
>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";
>  			};
>  
>  			uart_B: serial at 23000 {
> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
> +				compatible = "amlogic,meson-gx-uart";
>  				reg = <0x0 0x23000 0x0 0x14>;
>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>  				status = "disabled";

Re: [PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> For the UART controller in EE domain, they require 'pclk' to work.
> 
> they ? "the driver" maybe ?
> 
>> Current logic of the code will force to go for legacy clock probe
>> if it found current compatible string match to 'amlogic,meson-ao-uart'.
> 
> did you mean "amlogic,meson-uart" instead ?
> 
good catch! it's "amlogic,meson-uart"


> Apart from that
> 
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
> 
>>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index e2b8a9c8bf0b..1c6002b3fe34 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -142,14 +142,14 @@
>>  			};
>>  
>>  			uart_A: serial@24000 {
>> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
>> +				compatible = "amlogic,meson-gx-uart";
>>  				reg = <0x0 0x24000 0x0 0x14>;
>>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
>>  			};
>>  
>>  			uart_B: serial@23000 {
>> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
>> +				compatible = "amlogic,meson-gx-uart";
>>  				reg = <0x0 0x23000 0x0 0x14>;
>>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
> 
> .
> 

Re: [PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> For the UART controller in EE domain, they require 'pclk' to work.
> 
> they ? "the driver" maybe ?
> 
>> Current logic of the code will force to go for legacy clock probe
>> if it found current compatible string match to 'amlogic,meson-ao-uart'.
> 
> did you mean "amlogic,meson-uart" instead ?
> 
good catch! it's "amlogic,meson-uart"


> Apart from that
> 
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
> 
>>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index e2b8a9c8bf0b..1c6002b3fe34 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -142,14 +142,14 @@
>>  			};
>>  
>>  			uart_A: serial@24000 {
>> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
>> +				compatible = "amlogic,meson-gx-uart";
>>  				reg = <0x0 0x24000 0x0 0x14>;
>>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
>>  			};
>>  
>>  			uart_B: serial@23000 {
>> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
>> +				compatible = "amlogic,meson-gx-uart";
>>  				reg = <0x0 0x23000 0x0 0x14>;
>>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
> 
> .
> 

[PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> For the UART controller in EE domain, they require 'pclk' to work.
> 
> they ? "the driver" maybe ?
> 
>> Current logic of the code will force to go for legacy clock probe
>> if it found current compatible string match to 'amlogic,meson-ao-uart'.
> 
> did you mean "amlogic,meson-uart" instead ?
> 
good catch! it's "amlogic,meson-uart"


> Apart from that
> 
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
> 
>>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index e2b8a9c8bf0b..1c6002b3fe34 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -142,14 +142,14 @@
>>  			};
>>  
>>  			uart_A: serial at 24000 {
>> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
>> +				compatible = "amlogic,meson-gx-uart";
>>  				reg = <0x0 0x24000 0x0 0x14>;
>>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
>>  			};
>>  
>>  			uart_B: serial at 23000 {
>> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
>> +				compatible = "amlogic,meson-gx-uart";
>>  				reg = <0x0 0x23000 0x0 0x14>;
>>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
> 
> .
> 

[PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> For the UART controller in EE domain, they require 'pclk' to work.
> 
> they ? "the driver" maybe ?
> 
>> Current logic of the code will force to go for legacy clock probe
>> if it found current compatible string match to 'amlogic,meson-ao-uart'.
> 
> did you mean "amlogic,meson-uart" instead ?
> 
good catch! it's "amlogic,meson-uart"


> Apart from that
> 
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
> 
>>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index e2b8a9c8bf0b..1c6002b3fe34 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -142,14 +142,14 @@
>>  			};
>>  
>>  			uart_A: serial at 24000 {
>> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
>> +				compatible = "amlogic,meson-gx-uart";
>>  				reg = <0x0 0x24000 0x0 0x14>;
>>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
>>  			};
>>  
>>  			uart_B: serial at 23000 {
>> -				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
>> +				compatible = "amlogic,meson-gx-uart";
>>  				reg = <0x0 0x23000 0x0 0x14>;
>>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
> 
> .
> 

Re: [PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Yixun Lan]

On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> The address space range is actually 0x18, fixed here.
> 
> Isn't it the same for other meson SoC ? If they are compatible, it should.
> Could you please re-submit this change addressing all the required platforms ?
> 

sure

sorry, I was in hurry to send the patch set without do a full tree check..

you right, the fix should also apply to other SoCs, I will fold them
into this patch together, thanks for raising the idea.



>>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index 1c6002b3fe34..9636a7c5f6ed 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -143,14 +143,14 @@
>>  
>>  			uart_A: serial@24000 {
>>  				compatible = "amlogic,meson-gx-uart";
>> -				reg = <0x0 0x24000 0x0 0x14>;
>> +				reg = <0x0 0x24000 0x0 0x18>;
>>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
>>  			};
>>  
>>  			uart_B: serial@23000 {
>>  				compatible = "amlogic,meson-gx-uart";
>> -				reg = <0x0 0x23000 0x0 0x14>;
>> +				reg = <0x0 0x23000 0x0 0x18>;
>>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
>>  			};
> 
> .
> 

Re: [PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Yixun Lan]

On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> The address space range is actually 0x18, fixed here.
> 
> Isn't it the same for other meson SoC ? If they are compatible, it should.
> Could you please re-submit this change addressing all the required platforms ?
> 

sure

sorry, I was in hurry to send the patch set without do a full tree check..

you right, the fix should also apply to other SoCs, I will fold them
into this patch together, thanks for raising the idea.



>>
>> Signed-off-by: Yixun Lan <yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index 1c6002b3fe34..9636a7c5f6ed 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -143,14 +143,14 @@
>>  
>>  			uart_A: serial@24000 {
>>  				compatible = "amlogic,meson-gx-uart";
>> -				reg = <0x0 0x24000 0x0 0x14>;
>> +				reg = <0x0 0x24000 0x0 0x18>;
>>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
>>  			};
>>  
>>  			uart_B: serial@23000 {
>>  				compatible = "amlogic,meson-gx-uart";
>> -				reg = <0x0 0x23000 0x0 0x14>;
>> +				reg = <0x0 0x23000 0x0 0x18>;
>>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
>>  			};
> 
> .
> 

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[PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Yixun Lan]

On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> The address space range is actually 0x18, fixed here.
> 
> Isn't it the same for other meson SoC ? If they are compatible, it should.
> Could you please re-submit this change addressing all the required platforms ?
> 

sure

sorry, I was in hurry to send the patch set without do a full tree check..

you right, the fix should also apply to other SoCs, I will fold them
into this patch together, thanks for raising the idea.



>>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index 1c6002b3fe34..9636a7c5f6ed 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -143,14 +143,14 @@
>>  
>>  			uart_A: serial at 24000 {
>>  				compatible = "amlogic,meson-gx-uart";
>> -				reg = <0x0 0x24000 0x0 0x14>;
>> +				reg = <0x0 0x24000 0x0 0x18>;
>>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
>>  			};
>>  
>>  			uart_B: serial at 23000 {
>>  				compatible = "amlogic,meson-gx-uart";
>> -				reg = <0x0 0x23000 0x0 0x14>;
>> +				reg = <0x0 0x23000 0x0 0x18>;
>>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
>>  			};
> 
> .
> 

[PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Yixun Lan]

On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> The address space range is actually 0x18, fixed here.
> 
> Isn't it the same for other meson SoC ? If they are compatible, it should.
> Could you please re-submit this change addressing all the required platforms ?
> 

sure

sorry, I was in hurry to send the patch set without do a full tree check..

you right, the fix should also apply to other SoCs, I will fold them
into this patch together, thanks for raising the idea.



>>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index 1c6002b3fe34..9636a7c5f6ed 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -143,14 +143,14 @@
>>  
>>  			uart_A: serial at 24000 {
>>  				compatible = "amlogic,meson-gx-uart";
>> -				reg = <0x0 0x24000 0x0 0x14>;
>> +				reg = <0x0 0x24000 0x0 0x18>;
>>  				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
>>  			};
>>  
>>  			uart_B: serial at 23000 {
>>  				compatible = "amlogic,meson-gx-uart";
>> -				reg = <0x0 0x23000 0x0 0x14>;
>> +				reg = <0x0 0x23000 0x0 0x18>;
>>  				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
>>  				status = "disabled";
>>  			};
> 
> .
> 

Re: [PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

On 01/05/2018 06:28 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> Describe the pinctrl info for the UART controller which 
.

>> +				uart_a_cts_rts_pins: uart_a_cts_rts {
>> +					mux {
>> +						groups = "uart_ctx_a",
> 
> uart_ctx_a does not exist in pinctrl
> 
sorry, it's a typo, it's uart_cts_a

em. end of the Friday is really bad time for me to compose the patches..


>> +							"uart_rts_a";
>> +						function = "uart_a";
>> +					};
>> +				};
>> +
>> +				uart_b_x_pins: uart_b_x {
>> +					mux {
>> +						groups = "uart_tx_b_x",
>> +							"uart_rx_b_x";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
>> +					mux {
>> +						groups = "uart_cts_b_x",
>> +							"uart_rts_b_x";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_b_z_pins: uart_b_z {
>> +					mux {
>> +						groups = "uart_tx_b_z",
>> +							"uart_rx_b_z";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
>> +					mux {
>> +						groups = "uart_cts_b_z",
>> +							"uart_rts_b_z";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_ao_b_z_pins: uart_ao_b_z {
>> +					mux {
>> +						groups = "uart_ao_tx_b_z",
>> +							"uart_ao_rx_b_z";
>> +						function = "uart_ao_b_groupz";
> 
> "uart_ao_b_groupz" function does not exist in pinctrl
typo, uart_ao_b_gpioz

> 
.

Re: [PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

On 01/05/2018 06:28 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> Describe the pinctrl info for the UART controller which 
.

>> +				uart_a_cts_rts_pins: uart_a_cts_rts {
>> +					mux {
>> +						groups = "uart_ctx_a",
> 
> uart_ctx_a does not exist in pinctrl
> 
sorry, it's a typo, it's uart_cts_a

em. end of the Friday is really bad time for me to compose the patches..


>> +							"uart_rts_a";
>> +						function = "uart_a";
>> +					};
>> +				};
>> +
>> +				uart_b_x_pins: uart_b_x {
>> +					mux {
>> +						groups = "uart_tx_b_x",
>> +							"uart_rx_b_x";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
>> +					mux {
>> +						groups = "uart_cts_b_x",
>> +							"uart_rts_b_x";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_b_z_pins: uart_b_z {
>> +					mux {
>> +						groups = "uart_tx_b_z",
>> +							"uart_rx_b_z";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
>> +					mux {
>> +						groups = "uart_cts_b_z",
>> +							"uart_rts_b_z";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_ao_b_z_pins: uart_ao_b_z {
>> +					mux {
>> +						groups = "uart_ao_tx_b_z",
>> +							"uart_ao_rx_b_z";
>> +						function = "uart_ao_b_groupz";
> 
> "uart_ao_b_groupz" function does not exist in pinctrl
typo, uart_ao_b_gpioz

> 
.

[PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

On 01/05/2018 06:28 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> Describe the pinctrl info for the UART controller which 
.

>> +				uart_a_cts_rts_pins: uart_a_cts_rts {
>> +					mux {
>> +						groups = "uart_ctx_a",
> 
> uart_ctx_a does not exist in pinctrl
> 
sorry, it's a typo, it's uart_cts_a

em. end of the Friday is really bad time for me to compose the patches..


>> +							"uart_rts_a";
>> +						function = "uart_a";
>> +					};
>> +				};
>> +
>> +				uart_b_x_pins: uart_b_x {
>> +					mux {
>> +						groups = "uart_tx_b_x",
>> +							"uart_rx_b_x";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
>> +					mux {
>> +						groups = "uart_cts_b_x",
>> +							"uart_rts_b_x";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_b_z_pins: uart_b_z {
>> +					mux {
>> +						groups = "uart_tx_b_z",
>> +							"uart_rx_b_z";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
>> +					mux {
>> +						groups = "uart_cts_b_z",
>> +							"uart_rts_b_z";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_ao_b_z_pins: uart_ao_b_z {
>> +					mux {
>> +						groups = "uart_ao_tx_b_z",
>> +							"uart_ao_rx_b_z";
>> +						function = "uart_ao_b_groupz";
> 
> "uart_ao_b_groupz" function does not exist in pinctrl
typo, uart_ao_b_gpioz

> 
.

[PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

On 01/05/2018 06:28 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> Describe the pinctrl info for the UART controller which 
.

>> +				uart_a_cts_rts_pins: uart_a_cts_rts {
>> +					mux {
>> +						groups = "uart_ctx_a",
> 
> uart_ctx_a does not exist in pinctrl
> 
sorry, it's a typo, it's uart_cts_a

em. end of the Friday is really bad time for me to compose the patches..


>> +							"uart_rts_a";
>> +						function = "uart_a";
>> +					};
>> +				};
>> +
>> +				uart_b_x_pins: uart_b_x {
>> +					mux {
>> +						groups = "uart_tx_b_x",
>> +							"uart_rx_b_x";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
>> +					mux {
>> +						groups = "uart_cts_b_x",
>> +							"uart_rts_b_x";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_b_z_pins: uart_b_z {
>> +					mux {
>> +						groups = "uart_tx_b_z",
>> +							"uart_rx_b_z";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
>> +					mux {
>> +						groups = "uart_cts_b_z",
>> +							"uart_rts_b_z";
>> +						function = "uart_b";
>> +					};
>> +				};
>> +
>> +				uart_ao_b_z_pins: uart_ao_b_z {
>> +					mux {
>> +						groups = "uart_ao_tx_b_z",
>> +							"uart_ao_rx_b_z";
>> +						function = "uart_ao_b_groupz";
> 
> "uart_ao_b_groupz" function does not exist in pinctrl
typo, uart_ao_b_gpioz

> 
.