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* [PATCH 0/4] Add PMEM support for RISC-V
@ 2022-08-29 12:52 ` Anup Patel
  0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-08-29 12:52 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel

The Linux NVDIMM PEM drivers require arch support to map and access the
persistent memory device. This series adds RISC-V PMEM support using
recently added Svpbmt and Zicbom support.

These patches can also be found in riscv_pmem_v1 branch at:
https://github.com/avpatel/linux.git

Anup Patel (4):
  RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt
  RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c
  RISC-V: Implement arch specific PMEM APIs
  RISC-V: Enable PMEM drivers

 arch/riscv/Kconfig                  |  1 +
 arch/riscv/configs/defconfig        |  1 +
 arch/riscv/include/asm/cacheflush.h |  2 ++
 arch/riscv/include/asm/io.h         | 10 ++++++++
 arch/riscv/include/asm/pgtable.h    |  2 ++
 arch/riscv/mm/Makefile              |  1 +
 arch/riscv/mm/cacheflush.c          | 37 +++++++++++++++++++++++++++++
 arch/riscv/mm/dma-noncoherent.c     | 36 ----------------------------
 arch/riscv/mm/pmem.c                | 21 ++++++++++++++++
 9 files changed, 75 insertions(+), 36 deletions(-)
 create mode 100644 arch/riscv/mm/pmem.c

-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [PATCH 0/4] Add PMEM support for RISC-V
@ 2022-08-29 12:52 ` Anup Patel
  0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-08-29 12:52 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel

The Linux NVDIMM PEM drivers require arch support to map and access the
persistent memory device. This series adds RISC-V PMEM support using
recently added Svpbmt and Zicbom support.

These patches can also be found in riscv_pmem_v1 branch at:
https://github.com/avpatel/linux.git

Anup Patel (4):
  RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt
  RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c
  RISC-V: Implement arch specific PMEM APIs
  RISC-V: Enable PMEM drivers

 arch/riscv/Kconfig                  |  1 +
 arch/riscv/configs/defconfig        |  1 +
 arch/riscv/include/asm/cacheflush.h |  2 ++
 arch/riscv/include/asm/io.h         | 10 ++++++++
 arch/riscv/include/asm/pgtable.h    |  2 ++
 arch/riscv/mm/Makefile              |  1 +
 arch/riscv/mm/cacheflush.c          | 37 +++++++++++++++++++++++++++++
 arch/riscv/mm/dma-noncoherent.c     | 36 ----------------------------
 arch/riscv/mm/pmem.c                | 21 ++++++++++++++++
 9 files changed, 75 insertions(+), 36 deletions(-)
 create mode 100644 arch/riscv/mm/pmem.c

-- 
2.34.1


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [PATCH 1/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt
  2022-08-29 12:52 ` Anup Patel
@ 2022-08-29 12:52   ` Anup Patel
  -1 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-08-29 12:52 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel, Mayuresh Chitale

Currently, all flavors of ioremap_xyz() function maps to the generic
ioremap() which means any ioremap_xyz() call will always map the
target memory as IO using _PAGE_IOREMAP page attributes. This breaks
ioremap_cache() and ioremap_wc() on systems with Svpbmt because memory
remapped using ioremap_cache() and ioremap_wc() will use _PAGE_IOREMAP
page attributes.

To address above (just like other architectures), we implement RISC-V
specific ioremap_cache() and ioremap_wc() which maps memory using page
attributes as defined by the Svpbmt specification.

Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/io.h      | 10 ++++++++++
 arch/riscv/include/asm/pgtable.h |  2 ++
 2 files changed, 12 insertions(+)

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 69605a474270..07ac63999575 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -133,6 +133,16 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
 #define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
 #endif
 
+#ifdef CONFIG_MMU
+#define ioremap_wc(addr, size)		\
+	ioremap_prot((addr), (size), _PAGE_IOREMAP_WC)
+#endif
+
 #include <asm-generic/io.h>
 
+#ifdef CONFIG_MMU
+#define ioremap_cache(addr, size)	\
+	ioremap_prot((addr), (size), _PAGE_KERNEL)
+#endif
+
 #endif /* _ASM_RISCV_IO_H */
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 7ec936910a96..346b7c1a3eeb 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -182,6 +182,8 @@ extern struct pt_alloc_ops pt_ops __initdata;
 #define PAGE_TABLE		__pgprot(_PAGE_TABLE)
 
 #define _PAGE_IOREMAP	((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO)
+#define _PAGE_IOREMAP_WC	((_PAGE_KERNEL & ~_PAGE_MTMASK) | \
+				 _PAGE_NOCACHE)
 #define PAGE_KERNEL_IO		__pgprot(_PAGE_IOREMAP)
 
 extern pgd_t swapper_pg_dir[];
-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [PATCH 1/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt
@ 2022-08-29 12:52   ` Anup Patel
  0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-08-29 12:52 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel, Mayuresh Chitale

Currently, all flavors of ioremap_xyz() function maps to the generic
ioremap() which means any ioremap_xyz() call will always map the
target memory as IO using _PAGE_IOREMAP page attributes. This breaks
ioremap_cache() and ioremap_wc() on systems with Svpbmt because memory
remapped using ioremap_cache() and ioremap_wc() will use _PAGE_IOREMAP
page attributes.

To address above (just like other architectures), we implement RISC-V
specific ioremap_cache() and ioremap_wc() which maps memory using page
attributes as defined by the Svpbmt specification.

Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/io.h      | 10 ++++++++++
 arch/riscv/include/asm/pgtable.h |  2 ++
 2 files changed, 12 insertions(+)

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 69605a474270..07ac63999575 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -133,6 +133,16 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
 #define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
 #endif
 
+#ifdef CONFIG_MMU
+#define ioremap_wc(addr, size)		\
+	ioremap_prot((addr), (size), _PAGE_IOREMAP_WC)
+#endif
+
 #include <asm-generic/io.h>
 
+#ifdef CONFIG_MMU
+#define ioremap_cache(addr, size)	\
+	ioremap_prot((addr), (size), _PAGE_KERNEL)
+#endif
+
 #endif /* _ASM_RISCV_IO_H */
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 7ec936910a96..346b7c1a3eeb 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -182,6 +182,8 @@ extern struct pt_alloc_ops pt_ops __initdata;
 #define PAGE_TABLE		__pgprot(_PAGE_TABLE)
 
 #define _PAGE_IOREMAP	((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO)
+#define _PAGE_IOREMAP_WC	((_PAGE_KERNEL & ~_PAGE_MTMASK) | \
+				 _PAGE_NOCACHE)
 #define PAGE_KERNEL_IO		__pgprot(_PAGE_IOREMAP)
 
 extern pgd_t swapper_pg_dir[];
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [PATCH 2/4] RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c
  2022-08-29 12:52 ` Anup Patel
@ 2022-08-29 12:52   ` Anup Patel
  -1 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-08-29 12:52 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel, Mayuresh Chitale

The riscv_cbom_block_size parsing from DT belongs to cacheflush.c which
is home for all cache maintenance related stuff so let us move the
riscv_init_cbom_blocksize() and riscv_cbom_block_size to cacheflush.c.

Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/cacheflush.h |  2 ++
 arch/riscv/mm/cacheflush.c          | 37 +++++++++++++++++++++++++++++
 arch/riscv/mm/dma-noncoherent.c     | 36 ----------------------------
 3 files changed, 39 insertions(+), 36 deletions(-)

diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
index a60acaecfeda..de55d6b8deeb 100644
--- a/arch/riscv/include/asm/cacheflush.h
+++ b/arch/riscv/include/asm/cacheflush.h
@@ -42,6 +42,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local);
 
 #endif /* CONFIG_SMP */
 
+extern unsigned int riscv_cbom_block_size;
+
 #ifdef CONFIG_RISCV_ISA_ZICBOM
 void riscv_init_cbom_blocksize(void);
 #else
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 6cb7d96ad9c7..26be957dcbf2 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -86,3 +86,40 @@ void flush_icache_pte(pte_t pte)
 		flush_icache_all();
 }
 #endif /* CONFIG_MMU */
+
+unsigned int riscv_cbom_block_size = L1_CACHE_BYTES;
+
+#ifdef CONFIG_RISCV_ISA_ZICBOM
+void riscv_init_cbom_blocksize(void)
+{
+	struct device_node *node;
+	int ret;
+	u32 val;
+
+	for_each_of_cpu_node(node) {
+		unsigned long hartid;
+		int cbom_hartid;
+
+		ret = riscv_of_processor_hartid(node, &hartid);
+		if (ret)
+			continue;
+
+		if (hartid < 0)
+			continue;
+
+		/* set block-size for cbom extension if available */
+		ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
+		if (ret)
+			continue;
+
+		if (!riscv_cbom_block_size) {
+			riscv_cbom_block_size = val;
+			cbom_hartid = hartid;
+		} else {
+			if (riscv_cbom_block_size != val)
+				pr_warn("cbom-block-size mismatched between harts %d and %lu\n",
+					cbom_hartid, hartid);
+		}
+	}
+}
+#endif
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index cd2225304c82..b09e4b431307 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -12,7 +12,6 @@
 #include <linux/of_device.h>
 #include <asm/cacheflush.h>
 
-static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES;
 static bool noncoherent_supported;
 
 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
@@ -75,41 +74,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
 	dev->dma_coherent = coherent;
 }
 
-#ifdef CONFIG_RISCV_ISA_ZICBOM
-void riscv_init_cbom_blocksize(void)
-{
-	struct device_node *node;
-	int ret;
-	u32 val;
-
-	for_each_of_cpu_node(node) {
-		unsigned long hartid;
-		int cbom_hartid;
-
-		ret = riscv_of_processor_hartid(node, &hartid);
-		if (ret)
-			continue;
-
-		if (hartid < 0)
-			continue;
-
-		/* set block-size for cbom extension if available */
-		ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
-		if (ret)
-			continue;
-
-		if (!riscv_cbom_block_size) {
-			riscv_cbom_block_size = val;
-			cbom_hartid = hartid;
-		} else {
-			if (riscv_cbom_block_size != val)
-				pr_warn("cbom-block-size mismatched between harts %d and %lu\n",
-					cbom_hartid, hartid);
-		}
-	}
-}
-#endif
-
 void riscv_noncoherent_supported(void)
 {
 	noncoherent_supported = true;
-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [PATCH 2/4] RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c
@ 2022-08-29 12:52   ` Anup Patel
  0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-08-29 12:52 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel, Mayuresh Chitale

The riscv_cbom_block_size parsing from DT belongs to cacheflush.c which
is home for all cache maintenance related stuff so let us move the
riscv_init_cbom_blocksize() and riscv_cbom_block_size to cacheflush.c.

Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/cacheflush.h |  2 ++
 arch/riscv/mm/cacheflush.c          | 37 +++++++++++++++++++++++++++++
 arch/riscv/mm/dma-noncoherent.c     | 36 ----------------------------
 3 files changed, 39 insertions(+), 36 deletions(-)

diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
index a60acaecfeda..de55d6b8deeb 100644
--- a/arch/riscv/include/asm/cacheflush.h
+++ b/arch/riscv/include/asm/cacheflush.h
@@ -42,6 +42,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local);
 
 #endif /* CONFIG_SMP */
 
+extern unsigned int riscv_cbom_block_size;
+
 #ifdef CONFIG_RISCV_ISA_ZICBOM
 void riscv_init_cbom_blocksize(void);
 #else
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 6cb7d96ad9c7..26be957dcbf2 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -86,3 +86,40 @@ void flush_icache_pte(pte_t pte)
 		flush_icache_all();
 }
 #endif /* CONFIG_MMU */
+
+unsigned int riscv_cbom_block_size = L1_CACHE_BYTES;
+
+#ifdef CONFIG_RISCV_ISA_ZICBOM
+void riscv_init_cbom_blocksize(void)
+{
+	struct device_node *node;
+	int ret;
+	u32 val;
+
+	for_each_of_cpu_node(node) {
+		unsigned long hartid;
+		int cbom_hartid;
+
+		ret = riscv_of_processor_hartid(node, &hartid);
+		if (ret)
+			continue;
+
+		if (hartid < 0)
+			continue;
+
+		/* set block-size for cbom extension if available */
+		ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
+		if (ret)
+			continue;
+
+		if (!riscv_cbom_block_size) {
+			riscv_cbom_block_size = val;
+			cbom_hartid = hartid;
+		} else {
+			if (riscv_cbom_block_size != val)
+				pr_warn("cbom-block-size mismatched between harts %d and %lu\n",
+					cbom_hartid, hartid);
+		}
+	}
+}
+#endif
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index cd2225304c82..b09e4b431307 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -12,7 +12,6 @@
 #include <linux/of_device.h>
 #include <asm/cacheflush.h>
 
-static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES;
 static bool noncoherent_supported;
 
 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
@@ -75,41 +74,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
 	dev->dma_coherent = coherent;
 }
 
-#ifdef CONFIG_RISCV_ISA_ZICBOM
-void riscv_init_cbom_blocksize(void)
-{
-	struct device_node *node;
-	int ret;
-	u32 val;
-
-	for_each_of_cpu_node(node) {
-		unsigned long hartid;
-		int cbom_hartid;
-
-		ret = riscv_of_processor_hartid(node, &hartid);
-		if (ret)
-			continue;
-
-		if (hartid < 0)
-			continue;
-
-		/* set block-size for cbom extension if available */
-		ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
-		if (ret)
-			continue;
-
-		if (!riscv_cbom_block_size) {
-			riscv_cbom_block_size = val;
-			cbom_hartid = hartid;
-		} else {
-			if (riscv_cbom_block_size != val)
-				pr_warn("cbom-block-size mismatched between harts %d and %lu\n",
-					cbom_hartid, hartid);
-		}
-	}
-}
-#endif
-
 void riscv_noncoherent_supported(void)
 {
 	noncoherent_supported = true;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [PATCH 3/4] RISC-V: Implement arch specific PMEM APIs
  2022-08-29 12:52 ` Anup Patel
@ 2022-08-29 12:52   ` Anup Patel
  -1 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-08-29 12:52 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel, Mayuresh Chitale

The NVDIMM PMEM driver expects arch specific APIs for cache maintenance
and if arch does not provide these APIs then NVDIMM PMEM driver will
always use MEMREMAP_WT to map persistent memory which in-turn maps as
UC memory type defined by the RISC-V Svpbmt specification.

Now that the Svpbmt and Zicbom support is available in RISC-V kernel,
we implement PMEM APIs using ALT_CMO_OP() macros so that the NVDIMM
PMEM driver can use MEMREMAP_WB to map persistent memory.

Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/Kconfig     |  1 +
 arch/riscv/mm/Makefile |  1 +
 arch/riscv/mm/pmem.c   | 21 +++++++++++++++++++++
 3 files changed, 23 insertions(+)
 create mode 100644 arch/riscv/mm/pmem.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 0ebd8da388d8..37d6370d29c3 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -25,6 +25,7 @@ config RISCV
 	select ARCH_HAS_GIGANTIC_PAGE
 	select ARCH_HAS_KCOV
 	select ARCH_HAS_MMIOWB
+	select ARCH_HAS_PMEM_API
 	select ARCH_HAS_PTE_SPECIAL
 	select ARCH_HAS_SET_DIRECT_MAP if MMU
 	select ARCH_HAS_SET_MEMORY if MMU
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index d76aabf4b94d..3b368e547f83 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -31,3 +31,4 @@ endif
 
 obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
 obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o
+obj-$(CONFIG_ARCH_HAS_PMEM_API) += pmem.o
diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c
new file mode 100644
index 000000000000..089df92ae876
--- /dev/null
+++ b/arch/riscv/mm/pmem.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Ventana Micro Systems Inc.
+ */
+
+#include <linux/export.h>
+#include <linux/libnvdimm.h>
+
+#include <asm/cacheflush.h>
+
+void arch_wb_cache_pmem(void *addr, size_t size)
+{
+	ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size);
+}
+EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);
+
+void arch_invalidate_pmem(void *addr, size_t size)
+{
+	ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size);
+}
+EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [PATCH 3/4] RISC-V: Implement arch specific PMEM APIs
@ 2022-08-29 12:52   ` Anup Patel
  0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-08-29 12:52 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel, Mayuresh Chitale

The NVDIMM PMEM driver expects arch specific APIs for cache maintenance
and if arch does not provide these APIs then NVDIMM PMEM driver will
always use MEMREMAP_WT to map persistent memory which in-turn maps as
UC memory type defined by the RISC-V Svpbmt specification.

Now that the Svpbmt and Zicbom support is available in RISC-V kernel,
we implement PMEM APIs using ALT_CMO_OP() macros so that the NVDIMM
PMEM driver can use MEMREMAP_WB to map persistent memory.

Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/Kconfig     |  1 +
 arch/riscv/mm/Makefile |  1 +
 arch/riscv/mm/pmem.c   | 21 +++++++++++++++++++++
 3 files changed, 23 insertions(+)
 create mode 100644 arch/riscv/mm/pmem.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 0ebd8da388d8..37d6370d29c3 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -25,6 +25,7 @@ config RISCV
 	select ARCH_HAS_GIGANTIC_PAGE
 	select ARCH_HAS_KCOV
 	select ARCH_HAS_MMIOWB
+	select ARCH_HAS_PMEM_API
 	select ARCH_HAS_PTE_SPECIAL
 	select ARCH_HAS_SET_DIRECT_MAP if MMU
 	select ARCH_HAS_SET_MEMORY if MMU
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index d76aabf4b94d..3b368e547f83 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -31,3 +31,4 @@ endif
 
 obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
 obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o
+obj-$(CONFIG_ARCH_HAS_PMEM_API) += pmem.o
diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c
new file mode 100644
index 000000000000..089df92ae876
--- /dev/null
+++ b/arch/riscv/mm/pmem.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Ventana Micro Systems Inc.
+ */
+
+#include <linux/export.h>
+#include <linux/libnvdimm.h>
+
+#include <asm/cacheflush.h>
+
+void arch_wb_cache_pmem(void *addr, size_t size)
+{
+	ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size);
+}
+EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);
+
+void arch_invalidate_pmem(void *addr, size_t size)
+{
+	ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size);
+}
+EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [PATCH 4/4] RISC-V: Enable PMEM drivers
  2022-08-29 12:52 ` Anup Patel
@ 2022-08-29 12:52   ` Anup Patel
  -1 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-08-29 12:52 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel, Mayuresh Chitale

We now have PMEM arch support available in RISC-V kernel so let us
enable relevant drivers in defconfig.

Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index aed332a9d4ea..010b673ebd11 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -159,6 +159,7 @@ CONFIG_VIRTIO_MMIO=y
 CONFIG_RPMSG_CHAR=y
 CONFIG_RPMSG_CTRL=y
 CONFIG_RPMSG_VIRTIO=y
+CONFIG_LIBNVDIMM=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [PATCH 4/4] RISC-V: Enable PMEM drivers
@ 2022-08-29 12:52   ` Anup Patel
  0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-08-29 12:52 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel, Mayuresh Chitale

We now have PMEM arch support available in RISC-V kernel so let us
enable relevant drivers in defconfig.

Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index aed332a9d4ea..010b673ebd11 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -159,6 +159,7 @@ CONFIG_VIRTIO_MMIO=y
 CONFIG_RPMSG_CHAR=y
 CONFIG_RPMSG_CTRL=y
 CONFIG_RPMSG_VIRTIO=y
+CONFIG_LIBNVDIMM=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* Re: [PATCH 0/4] Add PMEM support for RISC-V
  2022-08-29 12:52 ` Anup Patel
@ 2022-08-29 17:40   ` Conor.Dooley
  -1 siblings, 0 replies; 16+ messages in thread
From: Conor.Dooley @ 2022-08-29 17:40 UTC (permalink / raw)
  To: apatel, palmer, paul.walmsley
  Cc: atishp, heiko, anup, linux-riscv, linux-kernel

On 29/08/2022 13:52, Anup Patel wrote:
> The Linux NVDIMM PEM drivers require arch support to map and access the
> persistent memory device. This series adds RISC-V PMEM support using
> recently added Svpbmt and Zicbom support.
> 
> These patches can also be found in riscv_pmem_v1 branch at:
> https://github.com/avpatel/linux.git

Hey Anup, couple build errors here:

/stuff/linux/arch/riscv/mm/cacheflush.c:99:2: error: call to undeclared function 'for_each_of_cpu_node'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
        for_each_of_cpu_node(node) {
        ^
/stuff/linux/arch/riscv/mm/cacheflush.c:99:28: error: expected ';' after expression
        for_each_of_cpu_node(node) {
                                  ^
                                  ;
1 warning generated.
/stuff/linux/arch/riscv/mm/cacheflush.c:105:4: error: 'continue' statement not in loop statement
                        continue;
                        ^
/stuff/linux/arch/riscv/mm/cacheflush.c:108:4: error: 'continue' statement not in loop statement
                        continue;
                        ^
/stuff/linux/arch/riscv/mm/cacheflush.c:111:9: error: call to undeclared function 'of_property_read_u32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
                ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
                      ^
/stuff/linux/arch/riscv/mm/cacheflush.c:113:4: error: 'continue' statement not in loop statement
                        continue;
                        ^
6 errors generated.

LKP already complained about this prior to you posting & as it has
all the repro needed, there's not much point in me sharing my config
etc:
https://lore.kernel.org/all/202208272028.IwrNZ0Ur-lkp@intel.com/

Thanks,
Conor.

PS: I liked the last patch, must've been a hard config option to
find if it took two of you! ;)


> 
> Anup Patel (4):
>   RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt
>   RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c
>   RISC-V: Implement arch specific PMEM APIs
>   RISC-V: Enable PMEM drivers
> 
>  arch/riscv/Kconfig                  |  1 +
>  arch/riscv/configs/defconfig        |  1 +
>  arch/riscv/include/asm/cacheflush.h |  2 ++
>  arch/riscv/include/asm/io.h         | 10 ++++++++
>  arch/riscv/include/asm/pgtable.h    |  2 ++
>  arch/riscv/mm/Makefile              |  1 +
>  arch/riscv/mm/cacheflush.c          | 37 +++++++++++++++++++++++++++++
>  arch/riscv/mm/dma-noncoherent.c     | 36 ----------------------------
>  arch/riscv/mm/pmem.c                | 21 ++++++++++++++++
>  9 files changed, 75 insertions(+), 36 deletions(-)
>  create mode 100644 arch/riscv/mm/pmem.c
> 

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 0/4] Add PMEM support for RISC-V
@ 2022-08-29 17:40   ` Conor.Dooley
  0 siblings, 0 replies; 16+ messages in thread
From: Conor.Dooley @ 2022-08-29 17:40 UTC (permalink / raw)
  To: apatel, palmer, paul.walmsley
  Cc: atishp, heiko, anup, linux-riscv, linux-kernel

On 29/08/2022 13:52, Anup Patel wrote:
> The Linux NVDIMM PEM drivers require arch support to map and access the
> persistent memory device. This series adds RISC-V PMEM support using
> recently added Svpbmt and Zicbom support.
> 
> These patches can also be found in riscv_pmem_v1 branch at:
> https://github.com/avpatel/linux.git

Hey Anup, couple build errors here:

/stuff/linux/arch/riscv/mm/cacheflush.c:99:2: error: call to undeclared function 'for_each_of_cpu_node'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
        for_each_of_cpu_node(node) {
        ^
/stuff/linux/arch/riscv/mm/cacheflush.c:99:28: error: expected ';' after expression
        for_each_of_cpu_node(node) {
                                  ^
                                  ;
1 warning generated.
/stuff/linux/arch/riscv/mm/cacheflush.c:105:4: error: 'continue' statement not in loop statement
                        continue;
                        ^
/stuff/linux/arch/riscv/mm/cacheflush.c:108:4: error: 'continue' statement not in loop statement
                        continue;
                        ^
/stuff/linux/arch/riscv/mm/cacheflush.c:111:9: error: call to undeclared function 'of_property_read_u32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
                ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
                      ^
/stuff/linux/arch/riscv/mm/cacheflush.c:113:4: error: 'continue' statement not in loop statement
                        continue;
                        ^
6 errors generated.

LKP already complained about this prior to you posting & as it has
all the repro needed, there's not much point in me sharing my config
etc:
https://lore.kernel.org/all/202208272028.IwrNZ0Ur-lkp@intel.com/

Thanks,
Conor.

PS: I liked the last patch, must've been a hard config option to
find if it took two of you! ;)


> 
> Anup Patel (4):
>   RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt
>   RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c
>   RISC-V: Implement arch specific PMEM APIs
>   RISC-V: Enable PMEM drivers
> 
>  arch/riscv/Kconfig                  |  1 +
>  arch/riscv/configs/defconfig        |  1 +
>  arch/riscv/include/asm/cacheflush.h |  2 ++
>  arch/riscv/include/asm/io.h         | 10 ++++++++
>  arch/riscv/include/asm/pgtable.h    |  2 ++
>  arch/riscv/mm/Makefile              |  1 +
>  arch/riscv/mm/cacheflush.c          | 37 +++++++++++++++++++++++++++++
>  arch/riscv/mm/dma-noncoherent.c     | 36 ----------------------------
>  arch/riscv/mm/pmem.c                | 21 ++++++++++++++++
>  9 files changed, 75 insertions(+), 36 deletions(-)
>  create mode 100644 arch/riscv/mm/pmem.c
> 
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 0/4] Add PMEM support for RISC-V
  2022-08-29 17:40   ` Conor.Dooley
@ 2022-08-30  4:43     ` Anup Patel
  -1 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-08-30  4:43 UTC (permalink / raw)
  To: Conor.Dooley
  Cc: palmer, paul.walmsley, atishp, heiko, anup, linux-riscv, linux-kernel

On Mon, Aug 29, 2022 at 11:11 PM <Conor.Dooley@microchip.com> wrote:
>
> On 29/08/2022 13:52, Anup Patel wrote:
> > The Linux NVDIMM PEM drivers require arch support to map and access the
> > persistent memory device. This series adds RISC-V PMEM support using
> > recently added Svpbmt and Zicbom support.
> >
> > These patches can also be found in riscv_pmem_v1 branch at:
> > https://github.com/avpatel/linux.git
>
> Hey Anup, couple build errors here:
>
> /stuff/linux/arch/riscv/mm/cacheflush.c:99:2: error: call to undeclared function 'for_each_of_cpu_node'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
>         for_each_of_cpu_node(node) {
>         ^
> /stuff/linux/arch/riscv/mm/cacheflush.c:99:28: error: expected ';' after expression
>         for_each_of_cpu_node(node) {
>                                   ^
>                                   ;
> 1 warning generated.
> /stuff/linux/arch/riscv/mm/cacheflush.c:105:4: error: 'continue' statement not in loop statement
>                         continue;
>                         ^
> /stuff/linux/arch/riscv/mm/cacheflush.c:108:4: error: 'continue' statement not in loop statement
>                         continue;
>                         ^
> /stuff/linux/arch/riscv/mm/cacheflush.c:111:9: error: call to undeclared function 'of_property_read_u32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
>                 ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
>                       ^
> /stuff/linux/arch/riscv/mm/cacheflush.c:113:4: error: 'continue' statement not in loop statement
>                         continue;
>                         ^
> 6 errors generated.
>
> LKP already complained about this prior to you posting & as it has
> all the repro needed, there's not much point in me sharing my config
> etc:
> https://lore.kernel.org/all/202208272028.IwrNZ0Ur-lkp@intel.com/

Strange, I never got this email.

I will send v2 to fix this.

Regards,
Anup

>
> Thanks,
> Conor.
>
> PS: I liked the last patch, must've been a hard config option to
> find if it took two of you! ;)
>
>
> >
> > Anup Patel (4):
> >   RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt
> >   RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c
> >   RISC-V: Implement arch specific PMEM APIs
> >   RISC-V: Enable PMEM drivers
> >
> >  arch/riscv/Kconfig                  |  1 +
> >  arch/riscv/configs/defconfig        |  1 +
> >  arch/riscv/include/asm/cacheflush.h |  2 ++
> >  arch/riscv/include/asm/io.h         | 10 ++++++++
> >  arch/riscv/include/asm/pgtable.h    |  2 ++
> >  arch/riscv/mm/Makefile              |  1 +
> >  arch/riscv/mm/cacheflush.c          | 37 +++++++++++++++++++++++++++++
> >  arch/riscv/mm/dma-noncoherent.c     | 36 ----------------------------
> >  arch/riscv/mm/pmem.c                | 21 ++++++++++++++++
> >  9 files changed, 75 insertions(+), 36 deletions(-)
> >  create mode 100644 arch/riscv/mm/pmem.c
> >

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 0/4] Add PMEM support for RISC-V
@ 2022-08-30  4:43     ` Anup Patel
  0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-08-30  4:43 UTC (permalink / raw)
  To: Conor.Dooley
  Cc: palmer, paul.walmsley, atishp, heiko, anup, linux-riscv, linux-kernel

On Mon, Aug 29, 2022 at 11:11 PM <Conor.Dooley@microchip.com> wrote:
>
> On 29/08/2022 13:52, Anup Patel wrote:
> > The Linux NVDIMM PEM drivers require arch support to map and access the
> > persistent memory device. This series adds RISC-V PMEM support using
> > recently added Svpbmt and Zicbom support.
> >
> > These patches can also be found in riscv_pmem_v1 branch at:
> > https://github.com/avpatel/linux.git
>
> Hey Anup, couple build errors here:
>
> /stuff/linux/arch/riscv/mm/cacheflush.c:99:2: error: call to undeclared function 'for_each_of_cpu_node'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
>         for_each_of_cpu_node(node) {
>         ^
> /stuff/linux/arch/riscv/mm/cacheflush.c:99:28: error: expected ';' after expression
>         for_each_of_cpu_node(node) {
>                                   ^
>                                   ;
> 1 warning generated.
> /stuff/linux/arch/riscv/mm/cacheflush.c:105:4: error: 'continue' statement not in loop statement
>                         continue;
>                         ^
> /stuff/linux/arch/riscv/mm/cacheflush.c:108:4: error: 'continue' statement not in loop statement
>                         continue;
>                         ^
> /stuff/linux/arch/riscv/mm/cacheflush.c:111:9: error: call to undeclared function 'of_property_read_u32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
>                 ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
>                       ^
> /stuff/linux/arch/riscv/mm/cacheflush.c:113:4: error: 'continue' statement not in loop statement
>                         continue;
>                         ^
> 6 errors generated.
>
> LKP already complained about this prior to you posting & as it has
> all the repro needed, there's not much point in me sharing my config
> etc:
> https://lore.kernel.org/all/202208272028.IwrNZ0Ur-lkp@intel.com/

Strange, I never got this email.

I will send v2 to fix this.

Regards,
Anup

>
> Thanks,
> Conor.
>
> PS: I liked the last patch, must've been a hard config option to
> find if it took two of you! ;)
>
>
> >
> > Anup Patel (4):
> >   RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt
> >   RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c
> >   RISC-V: Implement arch specific PMEM APIs
> >   RISC-V: Enable PMEM drivers
> >
> >  arch/riscv/Kconfig                  |  1 +
> >  arch/riscv/configs/defconfig        |  1 +
> >  arch/riscv/include/asm/cacheflush.h |  2 ++
> >  arch/riscv/include/asm/io.h         | 10 ++++++++
> >  arch/riscv/include/asm/pgtable.h    |  2 ++
> >  arch/riscv/mm/Makefile              |  1 +
> >  arch/riscv/mm/cacheflush.c          | 37 +++++++++++++++++++++++++++++
> >  arch/riscv/mm/dma-noncoherent.c     | 36 ----------------------------
> >  arch/riscv/mm/pmem.c                | 21 ++++++++++++++++
> >  9 files changed, 75 insertions(+), 36 deletions(-)
> >  create mode 100644 arch/riscv/mm/pmem.c
> >

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 0/4] Add PMEM support for RISC-V
  2022-08-30  4:43     ` Anup Patel
@ 2022-08-30  6:23       ` Conor.Dooley
  -1 siblings, 0 replies; 16+ messages in thread
From: Conor.Dooley @ 2022-08-30  6:23 UTC (permalink / raw)
  To: apatel
  Cc: palmer, paul.walmsley, atishp, heiko, anup, linux-riscv, linux-kernel

On 30/08/2022 05:43, Anup Patel wrote:
> On Mon, Aug 29, 2022 at 11:11 PM <Conor.Dooley@microchip.com> wrote:
>> LKP already complained about this prior to you posting & as it has
>> all the repro needed, there's not much point in me sharing my config
>> etc:
>> https://lore.kernel.org/all/202208272028.IwrNZ0Ur-lkp@intel.com/
> 
> Strange, I never got this email.

Good ole corporate firewall maybe..


^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 0/4] Add PMEM support for RISC-V
@ 2022-08-30  6:23       ` Conor.Dooley
  0 siblings, 0 replies; 16+ messages in thread
From: Conor.Dooley @ 2022-08-30  6:23 UTC (permalink / raw)
  To: apatel
  Cc: palmer, paul.walmsley, atishp, heiko, anup, linux-riscv, linux-kernel

On 30/08/2022 05:43, Anup Patel wrote:
> On Mon, Aug 29, 2022 at 11:11 PM <Conor.Dooley@microchip.com> wrote:
>> LKP already complained about this prior to you posting & as it has
>> all the repro needed, there's not much point in me sharing my config
>> etc:
>> https://lore.kernel.org/all/202208272028.IwrNZ0Ur-lkp@intel.com/
> 
> Strange, I never got this email.

Good ole corporate firewall maybe..

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-08-30  6:23 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-08-29 12:52 [PATCH 0/4] Add PMEM support for RISC-V Anup Patel
2022-08-29 12:52 ` Anup Patel
2022-08-29 12:52 ` [PATCH 1/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt Anup Patel
2022-08-29 12:52   ` Anup Patel
2022-08-29 12:52 ` [PATCH 2/4] RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c Anup Patel
2022-08-29 12:52   ` Anup Patel
2022-08-29 12:52 ` [PATCH 3/4] RISC-V: Implement arch specific PMEM APIs Anup Patel
2022-08-29 12:52   ` Anup Patel
2022-08-29 12:52 ` [PATCH 4/4] RISC-V: Enable PMEM drivers Anup Patel
2022-08-29 12:52   ` Anup Patel
2022-08-29 17:40 ` [PATCH 0/4] Add PMEM support for RISC-V Conor.Dooley
2022-08-29 17:40   ` Conor.Dooley
2022-08-30  4:43   ` Anup Patel
2022-08-30  4:43     ` Anup Patel
2022-08-30  6:23     ` Conor.Dooley
2022-08-30  6:23       ` Conor.Dooley

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