From: Zong Li <zong.li@sifive.com> To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Zong Li <zong.li@sifive.com> Subject: [RFC PATCH 6/6] riscv: remove PMU menu of Kconfig Date: Mon, 29 Jun 2020 11:19:15 +0800 [thread overview] Message-ID: <f704db6a46b6c4d89fcff28433900d1357ba4f26.1593397455.git.zong.li@sifive.com> (raw) In-Reply-To: <cover.1593397455.git.zong.li@sifive.com> We only one instance of riscv_pmu now, and use DT file to describe the platform-specific information, so drop the dependency and menu of RISCV_BASE_PMU. Signed-off-by: Zong Li <zong.li@sifive.com> --- arch/riscv/Kconfig | 13 ------------- arch/riscv/include/asm/perf_event.h | 2 -- arch/riscv/kernel/Makefile | 2 +- 3 files changed, 1 insertion(+), 16 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 128192e14ff2..deec11e924ce 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -292,19 +292,6 @@ config RISCV_ISA_C If you don't know what to do here, say Y. -menu "supported PMU type" - depends on PERF_EVENTS - -config RISCV_BASE_PMU - bool "Base Performance Monitoring Unit" - def_bool y - help - A base PMU that serves as a reference implementation and has limited - feature of perf. It can run on any RISC-V machines so serves as the - fallback, but this option can also be disable to reduce kernel size. - -endmenu - config FPU bool "FPU support" default y diff --git a/arch/riscv/include/asm/perf_event.h b/arch/riscv/include/asm/perf_event.h index e95d3bbaae3e..9ee654381d8c 100644 --- a/arch/riscv/include/asm/perf_event.h +++ b/arch/riscv/include/asm/perf_event.h @@ -12,7 +12,6 @@ #include <linux/ptrace.h> #include <linux/interrupt.h> -#ifdef CONFIG_RISCV_BASE_PMU #define RISCV_BASE_COUNTERS 2 #define RISCV_EVENT_COUNTERS 29 #define RISCV_TOTAL_COUNTERS (RISCV_BASE_COUNTERS + RISCV_EVENT_COUNTERS) @@ -79,7 +78,6 @@ #define CSR_MHPMEVENT7 0x327 #define CSR_MHPMEVENT8 0x328 -#endif #ifdef CONFIG_PERF_EVENTS #define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs #endif diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index b355cf485671..1f5736e996fd 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -43,7 +43,7 @@ obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o -obj-$(CONFIG_RISCV_BASE_PMU) += perf_event.o +obj-$(CONFIG_PERF_EVENTS) += perf_event.o obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o obj-$(CONFIG_RISCV_SBI) += sbi.o -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Zong Li <zong.li@sifive.com> To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Zong Li <zong.li@sifive.com> Subject: [RFC PATCH 6/6] riscv: remove PMU menu of Kconfig Date: Mon, 29 Jun 2020 11:19:15 +0800 [thread overview] Message-ID: <f704db6a46b6c4d89fcff28433900d1357ba4f26.1593397455.git.zong.li@sifive.com> (raw) In-Reply-To: <cover.1593397455.git.zong.li@sifive.com> We only one instance of riscv_pmu now, and use DT file to describe the platform-specific information, so drop the dependency and menu of RISCV_BASE_PMU. Signed-off-by: Zong Li <zong.li@sifive.com> --- arch/riscv/Kconfig | 13 ------------- arch/riscv/include/asm/perf_event.h | 2 -- arch/riscv/kernel/Makefile | 2 +- 3 files changed, 1 insertion(+), 16 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 128192e14ff2..deec11e924ce 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -292,19 +292,6 @@ config RISCV_ISA_C If you don't know what to do here, say Y. -menu "supported PMU type" - depends on PERF_EVENTS - -config RISCV_BASE_PMU - bool "Base Performance Monitoring Unit" - def_bool y - help - A base PMU that serves as a reference implementation and has limited - feature of perf. It can run on any RISC-V machines so serves as the - fallback, but this option can also be disable to reduce kernel size. - -endmenu - config FPU bool "FPU support" default y diff --git a/arch/riscv/include/asm/perf_event.h b/arch/riscv/include/asm/perf_event.h index e95d3bbaae3e..9ee654381d8c 100644 --- a/arch/riscv/include/asm/perf_event.h +++ b/arch/riscv/include/asm/perf_event.h @@ -12,7 +12,6 @@ #include <linux/ptrace.h> #include <linux/interrupt.h> -#ifdef CONFIG_RISCV_BASE_PMU #define RISCV_BASE_COUNTERS 2 #define RISCV_EVENT_COUNTERS 29 #define RISCV_TOTAL_COUNTERS (RISCV_BASE_COUNTERS + RISCV_EVENT_COUNTERS) @@ -79,7 +78,6 @@ #define CSR_MHPMEVENT7 0x327 #define CSR_MHPMEVENT8 0x328 -#endif #ifdef CONFIG_PERF_EVENTS #define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs #endif diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index b355cf485671..1f5736e996fd 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -43,7 +43,7 @@ obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o -obj-$(CONFIG_RISCV_BASE_PMU) += perf_event.o +obj-$(CONFIG_PERF_EVENTS) += perf_event.o obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o obj-$(CONFIG_RISCV_SBI) += sbi.o -- 2.27.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2020-06-29 3:19 UTC|newest] Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-06-29 3:19 [RFC PATCH 0/6] Support raw event and DT for perf on RISC-V Zong Li 2020-06-29 3:19 ` Zong Li 2020-06-29 3:19 ` [RFC PATCH 1/6] dt-bindings: riscv: Add YAML documentation for PMU Zong Li 2020-06-29 3:19 ` Zong Li 2020-06-29 4:09 ` Anup Patel 2020-06-29 4:09 ` Anup Patel 2020-06-29 4:28 ` Zong Li 2020-06-29 4:28 ` Zong Li 2020-06-29 4:37 ` Anup Patel 2020-06-29 4:37 ` Anup Patel 2020-06-29 6:35 ` Zong Li 2020-06-29 6:35 ` Zong Li 2020-06-29 8:31 ` Anup Patel 2020-06-29 8:31 ` Anup Patel 2020-07-01 3:22 ` Zong Li 2020-07-01 3:22 ` Zong Li 2020-06-29 3:19 ` [RFC PATCH 2/6] riscv: dts: sifive: Add DT support " Zong Li 2020-06-29 3:19 ` Zong Li 2020-06-29 3:19 ` [RFC PATCH 3/6] riscv: add definition of hpmcounter CSRs Zong Li 2020-06-29 3:19 ` Zong Li 2020-06-29 3:19 ` [RFC PATCH 4/6] riscv: perf: Add raw event support Zong Li 2020-06-29 3:19 ` Zong Li 2020-06-29 4:17 ` Anup Patel 2020-06-29 4:17 ` Anup Patel 2020-06-29 4:35 ` Zong Li 2020-06-29 4:35 ` Zong Li 2020-06-29 4:40 ` Anup Patel 2020-06-29 4:40 ` Anup Patel 2020-06-29 3:19 ` [RFC PATCH 5/6] riscv: perf: introduce DT mechanism Zong Li 2020-06-29 3:19 ` Zong Li 2020-06-29 4:36 ` Anup Patel 2020-06-29 4:36 ` Anup Patel 2020-06-29 6:26 ` Zong Li 2020-06-29 6:26 ` Zong Li 2020-06-29 11:42 ` kernel test robot 2020-06-29 3:19 ` Zong Li [this message] 2020-06-29 3:19 ` [RFC PATCH 6/6] riscv: remove PMU menu of Kconfig Zong Li 2020-06-29 4:52 ` [RFC PATCH 0/6] Support raw event and DT for perf on RISC-V Anup Patel 2020-06-29 4:52 ` Anup Patel 2020-06-29 5:52 ` Zong Li 2020-06-29 5:52 ` Zong Li 2020-06-29 8:27 ` Anup Patel 2020-06-29 8:27 ` Anup Patel 2020-06-29 12:53 ` Zong Li 2020-06-29 12:53 ` Zong Li 2020-06-29 13:23 ` Anup Patel 2020-06-29 13:23 ` Anup Patel 2020-06-30 6:37 ` Zong Li 2020-06-30 6:37 ` Zong Li 2020-06-30 7:39 ` Anup Patel 2020-06-30 7:39 ` Anup Patel 2020-06-30 8:04 ` Zong Li 2020-06-30 8:04 ` Zong Li 2020-06-30 10:18 ` Anup Patel 2020-06-30 10:18 ` Anup Patel 2020-06-30 11:38 ` Anup Patel 2020-06-30 11:38 ` Anup Patel 2020-06-30 18:57 ` Atish Patra 2020-06-30 18:57 ` Atish Patra 2020-07-01 2:14 ` Zong Li 2020-07-01 2:14 ` Zong Li 2020-07-01 11:43 ` Anup Patel 2020-07-01 11:43 ` Anup Patel 2020-07-01 2:11 ` Zong Li 2020-07-01 2:11 ` Zong Li 2020-07-01 1:55 ` Zong Li 2020-07-01 1:55 ` Zong Li 2020-07-01 0:51 ` Alan Kao 2020-07-01 0:51 ` Alan Kao 2020-07-01 1:02 ` Atish Patra 2020-07-01 1:02 ` Atish Patra 2020-07-01 2:45 ` Alan Kao 2020-07-01 2:45 ` Alan Kao 2020-07-01 3:15 ` Zong Li 2020-07-01 3:15 ` Zong Li 2020-07-01 4:13 ` Anup Patel 2020-07-01 4:13 ` Anup Patel
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