[PATCH V3 00/17] Cleanup MediaTek clk reset drivers and support MT8192/MT8195

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* [PATCH V3 00/17] Cleanup MediaTek clk reset drivers and support MT8192/MT8195
@ 2022-04-22  6:01 ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

In this series, we cleanup MediaTek clock reset drivers in clk/mediatek
folder. MediaTek clock reset driver is used to provide reset control
of modules controlled in clk, like infra_ao.

Changes for V3:
1. Modify drivers for reviewers' comments.
2. Add dt-binding patch for MT8192/MT8195 infra.
3. Add reset property of infra node for MT8192.
4. Use original function for simple operation.

Changes for V2:
1. Modify drivers for reviewers' comments.
2. Use simple reset to replace v1.
3. Recover v2 to set_clr.
4. Separate error handling to another patch.
5. Add support for input offset and bit from DT.
6. Add support for MT8192 and MT8195.

Rex-BC Chen (17):
  clk: mediatek: reset: Add reset.h
  clk: mediatek: reset: Fix written reset bit offset
  clk: mediatek: reset: Refine and reorder functions in reset.c
  clk: mediatek: reset: Extract common drivers to update function
  clk: mediatek: reset: Merge and revise reset register function
  clk: mediatek: reset: Revise structure to control reset register
  clk: mediatek: reset: Add return for clock reset register function
  clk: mediatek: reset: Add new register reset function with device
  clk: mediatek: reset: Add support for input offset and bit from DT
  clk: mediatek: reset: Add reset support for simple probe
  dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
  dt-binding: mt8192: Add infra_ao reset bit
  dt-bindings: arm: mediatek: Add #reset-cells property for MT8195-sys-clock
  dt-binding: mt8195: Add infra_ao reset bit
  clk: mediatek: reset: Add infra_ao reset support for MT8192
  clk: mediatek: reset: Add infra_ao reset support for MT8195
  arm64: dts: mediatek: Add infra #reset-cells property for MT8192

 .../mediatek/mediatek,mt8192-sys-clock.yaml   |   3 +
 .../mediatek/mediatek,mt8195-sys-clock.yaml   |   3 +
 arch/arm64/boot/dts/mediatek/mt8192.dtsi      |   1 +
 drivers/clk/mediatek/clk-mt2701-eth.c         |   8 +-
 drivers/clk/mediatek/clk-mt2701-g3d.c         |   8 +-
 drivers/clk/mediatek/clk-mt2701-hif.c         |   8 +-
 drivers/clk/mediatek/clk-mt2701.c             |  19 +-
 drivers/clk/mediatek/clk-mt2712.c             |  19 +-
 drivers/clk/mediatek/clk-mt7622-eth.c         |   8 +-
 drivers/clk/mediatek/clk-mt7622-hif.c         |  10 +-
 drivers/clk/mediatek/clk-mt7622.c             |  19 +-
 drivers/clk/mediatek/clk-mt7629-eth.c         |   8 +-
 drivers/clk/mediatek/clk-mt7629-hif.c         |  10 +-
 drivers/clk/mediatek/clk-mt8135.c             |  19 +-
 drivers/clk/mediatek/clk-mt8173.c             |  19 +-
 drivers/clk/mediatek/clk-mt8183.c             |   8 +-
 drivers/clk/mediatek/clk-mt8192.c             |  11 +
 drivers/clk/mediatek/clk-mt8195-infra_ao.c    |   8 +
 drivers/clk/mediatek/clk-mtk.c                |   7 +
 drivers/clk/mediatek/clk-mtk.h                |   9 +-
 drivers/clk/mediatek/reset.c                  | 202 +++++++++++++-----
 drivers/clk/mediatek/reset.h                  |  36 ++++
 include/dt-bindings/reset/mt8192-resets.h     |  10 +
 include/dt-bindings/reset/mt8195-resets.h     |   7 +
 24 files changed, 381 insertions(+), 79 deletions(-)
 create mode 100644 drivers/clk/mediatek/reset.h

-- 
2.18.0


^ permalink raw reply	[flat|nested] 117+ messages in thread

* [PATCH V3 00/17] Cleanup MediaTek clk reset drivers and support MT8192/MT8195
@ 2022-04-22  6:01 ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

In this series, we cleanup MediaTek clock reset drivers in clk/mediatek
folder. MediaTek clock reset driver is used to provide reset control
of modules controlled in clk, like infra_ao.

Changes for V3:
1. Modify drivers for reviewers' comments.
2. Add dt-binding patch for MT8192/MT8195 infra.
3. Add reset property of infra node for MT8192.
4. Use original function for simple operation.

Changes for V2:
1. Modify drivers for reviewers' comments.
2. Use simple reset to replace v1.
3. Recover v2 to set_clr.
4. Separate error handling to another patch.
5. Add support for input offset and bit from DT.
6. Add support for MT8192 and MT8195.

Rex-BC Chen (17):
  clk: mediatek: reset: Add reset.h
  clk: mediatek: reset: Fix written reset bit offset
  clk: mediatek: reset: Refine and reorder functions in reset.c
  clk: mediatek: reset: Extract common drivers to update function
  clk: mediatek: reset: Merge and revise reset register function
  clk: mediatek: reset: Revise structure to control reset register
  clk: mediatek: reset: Add return for clock reset register function
  clk: mediatek: reset: Add new register reset function with device
  clk: mediatek: reset: Add support for input offset and bit from DT
  clk: mediatek: reset: Add reset support for simple probe
  dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
  dt-binding: mt8192: Add infra_ao reset bit
  dt-bindings: arm: mediatek: Add #reset-cells property for MT8195-sys-clock
  dt-binding: mt8195: Add infra_ao reset bit
  clk: mediatek: reset: Add infra_ao reset support for MT8192
  clk: mediatek: reset: Add infra_ao reset support for MT8195
  arm64: dts: mediatek: Add infra #reset-cells property for MT8192

 .../mediatek/mediatek,mt8192-sys-clock.yaml   |   3 +
 .../mediatek/mediatek,mt8195-sys-clock.yaml   |   3 +
 arch/arm64/boot/dts/mediatek/mt8192.dtsi      |   1 +
 drivers/clk/mediatek/clk-mt2701-eth.c         |   8 +-
 drivers/clk/mediatek/clk-mt2701-g3d.c         |   8 +-
 drivers/clk/mediatek/clk-mt2701-hif.c         |   8 +-
 drivers/clk/mediatek/clk-mt2701.c             |  19 +-
 drivers/clk/mediatek/clk-mt2712.c             |  19 +-
 drivers/clk/mediatek/clk-mt7622-eth.c         |   8 +-
 drivers/clk/mediatek/clk-mt7622-hif.c         |  10 +-
 drivers/clk/mediatek/clk-mt7622.c             |  19 +-
 drivers/clk/mediatek/clk-mt7629-eth.c         |   8 +-
 drivers/clk/mediatek/clk-mt7629-hif.c         |  10 +-
 drivers/clk/mediatek/clk-mt8135.c             |  19 +-
 drivers/clk/mediatek/clk-mt8173.c             |  19 +-
 drivers/clk/mediatek/clk-mt8183.c             |   8 +-
 drivers/clk/mediatek/clk-mt8192.c             |  11 +
 drivers/clk/mediatek/clk-mt8195-infra_ao.c    |   8 +
 drivers/clk/mediatek/clk-mtk.c                |   7 +
 drivers/clk/mediatek/clk-mtk.h                |   9 +-
 drivers/clk/mediatek/reset.c                  | 202 +++++++++++++-----
 drivers/clk/mediatek/reset.h                  |  36 ++++
 include/dt-bindings/reset/mt8192-resets.h     |  10 +
 include/dt-bindings/reset/mt8195-resets.h     |   7 +
 24 files changed, 381 insertions(+), 79 deletions(-)
 create mode 100644 drivers/clk/mediatek/reset.h

-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* [PATCH V3 00/17] Cleanup MediaTek clk reset drivers and support MT8192/MT8195
@ 2022-04-22  6:01 ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

In this series, we cleanup MediaTek clock reset drivers in clk/mediatek
folder. MediaTek clock reset driver is used to provide reset control
of modules controlled in clk, like infra_ao.

Changes for V3:
1. Modify drivers for reviewers' comments.
2. Add dt-binding patch for MT8192/MT8195 infra.
3. Add reset property of infra node for MT8192.
4. Use original function for simple operation.

Changes for V2:
1. Modify drivers for reviewers' comments.
2. Use simple reset to replace v1.
3. Recover v2 to set_clr.
4. Separate error handling to another patch.
5. Add support for input offset and bit from DT.
6. Add support for MT8192 and MT8195.

Rex-BC Chen (17):
  clk: mediatek: reset: Add reset.h
  clk: mediatek: reset: Fix written reset bit offset
  clk: mediatek: reset: Refine and reorder functions in reset.c
  clk: mediatek: reset: Extract common drivers to update function
  clk: mediatek: reset: Merge and revise reset register function
  clk: mediatek: reset: Revise structure to control reset register
  clk: mediatek: reset: Add return for clock reset register function
  clk: mediatek: reset: Add new register reset function with device
  clk: mediatek: reset: Add support for input offset and bit from DT
  clk: mediatek: reset: Add reset support for simple probe
  dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
  dt-binding: mt8192: Add infra_ao reset bit
  dt-bindings: arm: mediatek: Add #reset-cells property for MT8195-sys-clock
  dt-binding: mt8195: Add infra_ao reset bit
  clk: mediatek: reset: Add infra_ao reset support for MT8192
  clk: mediatek: reset: Add infra_ao reset support for MT8195
  arm64: dts: mediatek: Add infra #reset-cells property for MT8192

 .../mediatek/mediatek,mt8192-sys-clock.yaml   |   3 +
 .../mediatek/mediatek,mt8195-sys-clock.yaml   |   3 +
 arch/arm64/boot/dts/mediatek/mt8192.dtsi      |   1 +
 drivers/clk/mediatek/clk-mt2701-eth.c         |   8 +-
 drivers/clk/mediatek/clk-mt2701-g3d.c         |   8 +-
 drivers/clk/mediatek/clk-mt2701-hif.c         |   8 +-
 drivers/clk/mediatek/clk-mt2701.c             |  19 +-
 drivers/clk/mediatek/clk-mt2712.c             |  19 +-
 drivers/clk/mediatek/clk-mt7622-eth.c         |   8 +-
 drivers/clk/mediatek/clk-mt7622-hif.c         |  10 +-
 drivers/clk/mediatek/clk-mt7622.c             |  19 +-
 drivers/clk/mediatek/clk-mt7629-eth.c         |   8 +-
 drivers/clk/mediatek/clk-mt7629-hif.c         |  10 +-
 drivers/clk/mediatek/clk-mt8135.c             |  19 +-
 drivers/clk/mediatek/clk-mt8173.c             |  19 +-
 drivers/clk/mediatek/clk-mt8183.c             |   8 +-
 drivers/clk/mediatek/clk-mt8192.c             |  11 +
 drivers/clk/mediatek/clk-mt8195-infra_ao.c    |   8 +
 drivers/clk/mediatek/clk-mtk.c                |   7 +
 drivers/clk/mediatek/clk-mtk.h                |   9 +-
 drivers/clk/mediatek/reset.c                  | 202 +++++++++++++-----
 drivers/clk/mediatek/reset.h                  |  36 ++++
 include/dt-bindings/reset/mt8192-resets.h     |  10 +
 include/dt-bindings/reset/mt8195-resets.h     |   7 +
 24 files changed, 381 insertions(+), 79 deletions(-)
 create mode 100644 drivers/clk/mediatek/reset.h

-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* [PATCH V3 01/17] clk: mediatek: reset: Add reset.h
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

Add a new file "reset.h" to place some definitions for clock reset.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mtk.h |  8 ++------
 drivers/clk/mediatek/reset.c   |  9 +--------
 drivers/clk/mediatek/reset.h   | 24 ++++++++++++++++++++++++
 3 files changed, 27 insertions(+), 14 deletions(-)
 create mode 100644 drivers/clk/mediatek/reset.h

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index bf6565aa7319..a6d0f24c62fa 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -13,6 +13,8 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 
+#include "reset.h"
+
 #define MAX_MUX_GATE_BIT	31
 #define INVALID_MUX_GATE_BIT	(MAX_MUX_GATE_BIT + 1)
 
@@ -190,12 +192,6 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data);
 struct clk *mtk_clk_register_ref2usb_tx(const char *name,
 			const char *parent_name, void __iomem *reg);
 
-void mtk_register_reset_controller(struct device_node *np,
-			unsigned int num_regs, int regofs);
-
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-	unsigned int num_regs, int regofs);
-
 struct mtk_clk_desc {
 	const struct mtk_gate *clks;
 	size_t num_clks;
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index bcec4b89f449..9f3cb22aea1b 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -8,16 +8,9 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
-#include <linux/reset-controller.h>
 #include <linux/slab.h>
 
-#include "clk-mtk.h"
-
-struct mtk_reset {
-	struct regmap *regmap;
-	int regofs;
-	struct reset_controller_dev rcdev;
-};
+#include "reset.h"
 
 static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
 	unsigned long id)
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
new file mode 100644
index 000000000000..764a8affe206
--- /dev/null
+++ b/drivers/clk/mediatek/reset.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __DRV_CLK_MTK_RESET_H
+#define __DRV_CLK_MTK_RESET_H
+
+#include <linux/reset-controller.h>
+#include <linux/types.h>
+
+struct mtk_reset {
+	struct regmap *regmap;
+	int regofs;
+	struct reset_controller_dev rcdev;
+};
+
+void mtk_register_reset_controller(struct device_node *np,
+				   unsigned int num_regs, int regofs);
+
+void mtk_register_reset_controller_set_clr(struct device_node *np,
+					   unsigned int num_regs, int regofs);
+
+#endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 01/17] clk: mediatek: reset: Add reset.h
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

Add a new file "reset.h" to place some definitions for clock reset.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mtk.h |  8 ++------
 drivers/clk/mediatek/reset.c   |  9 +--------
 drivers/clk/mediatek/reset.h   | 24 ++++++++++++++++++++++++
 3 files changed, 27 insertions(+), 14 deletions(-)
 create mode 100644 drivers/clk/mediatek/reset.h

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index bf6565aa7319..a6d0f24c62fa 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -13,6 +13,8 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 
+#include "reset.h"
+
 #define MAX_MUX_GATE_BIT	31
 #define INVALID_MUX_GATE_BIT	(MAX_MUX_GATE_BIT + 1)
 
@@ -190,12 +192,6 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data);
 struct clk *mtk_clk_register_ref2usb_tx(const char *name,
 			const char *parent_name, void __iomem *reg);
 
-void mtk_register_reset_controller(struct device_node *np,
-			unsigned int num_regs, int regofs);
-
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-	unsigned int num_regs, int regofs);
-
 struct mtk_clk_desc {
 	const struct mtk_gate *clks;
 	size_t num_clks;
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index bcec4b89f449..9f3cb22aea1b 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -8,16 +8,9 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
-#include <linux/reset-controller.h>
 #include <linux/slab.h>
 
-#include "clk-mtk.h"
-
-struct mtk_reset {
-	struct regmap *regmap;
-	int regofs;
-	struct reset_controller_dev rcdev;
-};
+#include "reset.h"
 
 static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
 	unsigned long id)
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
new file mode 100644
index 000000000000..764a8affe206
--- /dev/null
+++ b/drivers/clk/mediatek/reset.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __DRV_CLK_MTK_RESET_H
+#define __DRV_CLK_MTK_RESET_H
+
+#include <linux/reset-controller.h>
+#include <linux/types.h>
+
+struct mtk_reset {
+	struct regmap *regmap;
+	int regofs;
+	struct reset_controller_dev rcdev;
+};
+
+void mtk_register_reset_controller(struct device_node *np,
+				   unsigned int num_regs, int regofs);
+
+void mtk_register_reset_controller_set_clr(struct device_node *np,
+					   unsigned int num_regs, int regofs);
+
+#endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 01/17] clk: mediatek: reset: Add reset.h
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

Add a new file "reset.h" to place some definitions for clock reset.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mtk.h |  8 ++------
 drivers/clk/mediatek/reset.c   |  9 +--------
 drivers/clk/mediatek/reset.h   | 24 ++++++++++++++++++++++++
 3 files changed, 27 insertions(+), 14 deletions(-)
 create mode 100644 drivers/clk/mediatek/reset.h

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index bf6565aa7319..a6d0f24c62fa 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -13,6 +13,8 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 
+#include "reset.h"
+
 #define MAX_MUX_GATE_BIT	31
 #define INVALID_MUX_GATE_BIT	(MAX_MUX_GATE_BIT + 1)
 
@@ -190,12 +192,6 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data);
 struct clk *mtk_clk_register_ref2usb_tx(const char *name,
 			const char *parent_name, void __iomem *reg);
 
-void mtk_register_reset_controller(struct device_node *np,
-			unsigned int num_regs, int regofs);
-
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-	unsigned int num_regs, int regofs);
-
 struct mtk_clk_desc {
 	const struct mtk_gate *clks;
 	size_t num_clks;
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index bcec4b89f449..9f3cb22aea1b 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -8,16 +8,9 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
-#include <linux/reset-controller.h>
 #include <linux/slab.h>
 
-#include "clk-mtk.h"
-
-struct mtk_reset {
-	struct regmap *regmap;
-	int regofs;
-	struct reset_controller_dev rcdev;
-};
+#include "reset.h"
 
 static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
 	unsigned long id)
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
new file mode 100644
index 000000000000..764a8affe206
--- /dev/null
+++ b/drivers/clk/mediatek/reset.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __DRV_CLK_MTK_RESET_H
+#define __DRV_CLK_MTK_RESET_H
+
+#include <linux/reset-controller.h>
+#include <linux/types.h>
+
+struct mtk_reset {
+	struct regmap *regmap;
+	int regofs;
+	struct reset_controller_dev rcdev;
+};
+
+void mtk_register_reset_controller(struct device_node *np,
+				   unsigned int num_regs, int regofs);
+
+void mtk_register_reset_controller_set_clr(struct device_node *np,
+					   unsigned int num_regs, int regofs);
+
+#endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 02/17] clk: mediatek: reset: Fix written reset bit offset
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

Original assert/deassert bit is BIT(0), but it's more resonable to modify
them to BIT(id % 32) which is based on id.

This patch will not influence any previous driver because the reset is
only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0.

Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver")
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/reset.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 9f3cb22aea1b..5191becb45dd 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -18,7 +18,7 @@ static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
 	unsigned int reg = data->regofs + ((id / 32) << 4);
 
-	return regmap_write(data->regmap, reg, 1);
+	return regmap_write(data->regmap, reg, BIT(id % 32));
 }
 
 static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
@@ -27,7 +27,7 @@ static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
 	unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;
 
-	return regmap_write(data->regmap, reg, 1);
+	return regmap_write(data->regmap, reg, BIT(id % 32));
 }
 
 static int mtk_reset_assert(struct reset_controller_dev *rcdev,
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 02/17] clk: mediatek: reset: Fix written reset bit offset
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

Original assert/deassert bit is BIT(0), but it's more resonable to modify
them to BIT(id % 32) which is based on id.

This patch will not influence any previous driver because the reset is
only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0.

Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver")
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/reset.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 9f3cb22aea1b..5191becb45dd 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -18,7 +18,7 @@ static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
 	unsigned int reg = data->regofs + ((id / 32) << 4);
 
-	return regmap_write(data->regmap, reg, 1);
+	return regmap_write(data->regmap, reg, BIT(id % 32));
 }
 
 static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
@@ -27,7 +27,7 @@ static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
 	unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;
 
-	return regmap_write(data->regmap, reg, 1);
+	return regmap_write(data->regmap, reg, BIT(id % 32));
 }
 
 static int mtk_reset_assert(struct reset_controller_dev *rcdev,
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 02/17] clk: mediatek: reset: Fix written reset bit offset
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

Original assert/deassert bit is BIT(0), but it's more resonable to modify
them to BIT(id % 32) which is based on id.

This patch will not influence any previous driver because the reset is
only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0.

Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver")
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/reset.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 9f3cb22aea1b..5191becb45dd 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -18,7 +18,7 @@ static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
 	unsigned int reg = data->regofs + ((id / 32) << 4);
 
-	return regmap_write(data->regmap, reg, 1);
+	return regmap_write(data->regmap, reg, BIT(id % 32));
 }
 
 static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
@@ -27,7 +27,7 @@ static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
 	unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;
 
-	return regmap_write(data->regmap, reg, 1);
+	return regmap_write(data->regmap, reg, BIT(id % 32));
 }
 
 static int mtk_reset_assert(struct reset_controller_dev *rcdev,
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 03/17] clk: mediatek: reset: Refine and reorder functions in reset.c
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To make drivers more readable, we modify the indentation of the drivers
and reorder the location of functions.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 68 +++++++++++++++++++-----------------
 1 file changed, 36 insertions(+), 32 deletions(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 5191becb45dd..5cbbcc22a4fc 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -12,56 +12,59 @@
 
 #include "reset.h"
 
-static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
-	unsigned long id)
+static int mtk_reset_assert(struct reset_controller_dev *rcdev,
+			    unsigned long id)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-	unsigned int reg = data->regofs + ((id / 32) << 4);
 
-	return regmap_write(data->regmap, reg, BIT(id % 32));
+	return regmap_update_bits(data->regmap,
+				  data->regofs + ((id / 32) << 2),
+				  BIT(id % 32), ~0);
 }
 
-static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
-	unsigned long id)
+static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-	unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;
 
-	return regmap_write(data->regmap, reg, BIT(id % 32));
+	return regmap_update_bits(data->regmap,
+				  data->regofs + ((id / 32) << 2),
+				  BIT(id % 32), 0);
 }
 
-static int mtk_reset_assert(struct reset_controller_dev *rcdev,
-			      unsigned long id)
+static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	int ret;
+
+	ret = mtk_reset_assert(rcdev, id);
+	if (ret)
+		return ret;
 
-	return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
-			BIT(id % 32), ~0);
+	return mtk_reset_deassert(rcdev, id);
 }
 
-static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
-				unsigned long id)
+static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
+				    unsigned long id)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
 
-	return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
-			BIT(id % 32), 0);
+	return regmap_write(data->regmap,
+			    data->regofs + ((id / 32) << 4),
+			    BIT(id % 32));
 }
 
-static int mtk_reset(struct reset_controller_dev *rcdev,
-			      unsigned long id)
+static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
+				      unsigned long id)
 {
-	int ret;
-
-	ret = mtk_reset_assert(rcdev, id);
-	if (ret)
-		return ret;
+	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
 
-	return mtk_reset_deassert(rcdev, id);
+	return regmap_write(data->regmap,
+			    data->regofs + ((id / 32) << 4) + 0x4,
+			    BIT(id % 32));
 }
 
 static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
-	unsigned long id)
+			     unsigned long id)
 {
 	int ret;
 
@@ -84,8 +87,9 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 };
 
 static void mtk_register_reset_controller_common(struct device_node *np,
-			unsigned int num_regs, int regofs,
-			const struct reset_control_ops *reset_ops)
+						 unsigned int num_regs,
+						 int regofs,
+						 const struct reset_control_ops *reset_ops)
 {
 	struct mtk_reset *data;
 	int ret;
@@ -117,17 +121,17 @@ static void mtk_register_reset_controller_common(struct device_node *np,
 }
 
 void mtk_register_reset_controller(struct device_node *np,
-	unsigned int num_regs, int regofs)
+				   unsigned int num_regs, int regofs)
 {
 	mtk_register_reset_controller_common(np, num_regs, regofs,
-		&mtk_reset_ops);
+					     &mtk_reset_ops);
 }
 
 void mtk_register_reset_controller_set_clr(struct device_node *np,
-	unsigned int num_regs, int regofs)
+					   unsigned int num_regs, int regofs)
 {
 	mtk_register_reset_controller_common(np, num_regs, regofs,
-		&mtk_reset_ops_set_clr);
+					     &mtk_reset_ops_set_clr);
 }
 
 MODULE_LICENSE("GPL");
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 03/17] clk: mediatek: reset: Refine and reorder functions in reset.c
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To make drivers more readable, we modify the indentation of the drivers
and reorder the location of functions.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 68 +++++++++++++++++++-----------------
 1 file changed, 36 insertions(+), 32 deletions(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 5191becb45dd..5cbbcc22a4fc 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -12,56 +12,59 @@
 
 #include "reset.h"
 
-static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
-	unsigned long id)
+static int mtk_reset_assert(struct reset_controller_dev *rcdev,
+			    unsigned long id)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-	unsigned int reg = data->regofs + ((id / 32) << 4);
 
-	return regmap_write(data->regmap, reg, BIT(id % 32));
+	return regmap_update_bits(data->regmap,
+				  data->regofs + ((id / 32) << 2),
+				  BIT(id % 32), ~0);
 }
 
-static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
-	unsigned long id)
+static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-	unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;
 
-	return regmap_write(data->regmap, reg, BIT(id % 32));
+	return regmap_update_bits(data->regmap,
+				  data->regofs + ((id / 32) << 2),
+				  BIT(id % 32), 0);
 }
 
-static int mtk_reset_assert(struct reset_controller_dev *rcdev,
-			      unsigned long id)
+static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	int ret;
+
+	ret = mtk_reset_assert(rcdev, id);
+	if (ret)
+		return ret;
 
-	return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
-			BIT(id % 32), ~0);
+	return mtk_reset_deassert(rcdev, id);
 }
 
-static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
-				unsigned long id)
+static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
+				    unsigned long id)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
 
-	return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
-			BIT(id % 32), 0);
+	return regmap_write(data->regmap,
+			    data->regofs + ((id / 32) << 4),
+			    BIT(id % 32));
 }
 
-static int mtk_reset(struct reset_controller_dev *rcdev,
-			      unsigned long id)
+static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
+				      unsigned long id)
 {
-	int ret;
-
-	ret = mtk_reset_assert(rcdev, id);
-	if (ret)
-		return ret;
+	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
 
-	return mtk_reset_deassert(rcdev, id);
+	return regmap_write(data->regmap,
+			    data->regofs + ((id / 32) << 4) + 0x4,
+			    BIT(id % 32));
 }
 
 static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
-	unsigned long id)
+			     unsigned long id)
 {
 	int ret;
 
@@ -84,8 +87,9 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 };
 
 static void mtk_register_reset_controller_common(struct device_node *np,
-			unsigned int num_regs, int regofs,
-			const struct reset_control_ops *reset_ops)
+						 unsigned int num_regs,
+						 int regofs,
+						 const struct reset_control_ops *reset_ops)
 {
 	struct mtk_reset *data;
 	int ret;
@@ -117,17 +121,17 @@ static void mtk_register_reset_controller_common(struct device_node *np,
 }
 
 void mtk_register_reset_controller(struct device_node *np,
-	unsigned int num_regs, int regofs)
+				   unsigned int num_regs, int regofs)
 {
 	mtk_register_reset_controller_common(np, num_regs, regofs,
-		&mtk_reset_ops);
+					     &mtk_reset_ops);
 }
 
 void mtk_register_reset_controller_set_clr(struct device_node *np,
-	unsigned int num_regs, int regofs)
+					   unsigned int num_regs, int regofs)
 {
 	mtk_register_reset_controller_common(np, num_regs, regofs,
-		&mtk_reset_ops_set_clr);
+					     &mtk_reset_ops_set_clr);
 }
 
 MODULE_LICENSE("GPL");
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 03/17] clk: mediatek: reset: Refine and reorder functions in reset.c
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To make drivers more readable, we modify the indentation of the drivers
and reorder the location of functions.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 68 +++++++++++++++++++-----------------
 1 file changed, 36 insertions(+), 32 deletions(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 5191becb45dd..5cbbcc22a4fc 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -12,56 +12,59 @@
 
 #include "reset.h"
 
-static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
-	unsigned long id)
+static int mtk_reset_assert(struct reset_controller_dev *rcdev,
+			    unsigned long id)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-	unsigned int reg = data->regofs + ((id / 32) << 4);
 
-	return regmap_write(data->regmap, reg, BIT(id % 32));
+	return regmap_update_bits(data->regmap,
+				  data->regofs + ((id / 32) << 2),
+				  BIT(id % 32), ~0);
 }
 
-static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
-	unsigned long id)
+static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-	unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;
 
-	return regmap_write(data->regmap, reg, BIT(id % 32));
+	return regmap_update_bits(data->regmap,
+				  data->regofs + ((id / 32) << 2),
+				  BIT(id % 32), 0);
 }
 
-static int mtk_reset_assert(struct reset_controller_dev *rcdev,
-			      unsigned long id)
+static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	int ret;
+
+	ret = mtk_reset_assert(rcdev, id);
+	if (ret)
+		return ret;
 
-	return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
-			BIT(id % 32), ~0);
+	return mtk_reset_deassert(rcdev, id);
 }
 
-static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
-				unsigned long id)
+static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
+				    unsigned long id)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
 
-	return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
-			BIT(id % 32), 0);
+	return regmap_write(data->regmap,
+			    data->regofs + ((id / 32) << 4),
+			    BIT(id % 32));
 }
 
-static int mtk_reset(struct reset_controller_dev *rcdev,
-			      unsigned long id)
+static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
+				      unsigned long id)
 {
-	int ret;
-
-	ret = mtk_reset_assert(rcdev, id);
-	if (ret)
-		return ret;
+	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
 
-	return mtk_reset_deassert(rcdev, id);
+	return regmap_write(data->regmap,
+			    data->regofs + ((id / 32) << 4) + 0x4,
+			    BIT(id % 32));
 }
 
 static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
-	unsigned long id)
+			     unsigned long id)
 {
 	int ret;
 
@@ -84,8 +87,9 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 };
 
 static void mtk_register_reset_controller_common(struct device_node *np,
-			unsigned int num_regs, int regofs,
-			const struct reset_control_ops *reset_ops)
+						 unsigned int num_regs,
+						 int regofs,
+						 const struct reset_control_ops *reset_ops)
 {
 	struct mtk_reset *data;
 	int ret;
@@ -117,17 +121,17 @@ static void mtk_register_reset_controller_common(struct device_node *np,
 }
 
 void mtk_register_reset_controller(struct device_node *np,
-	unsigned int num_regs, int regofs)
+				   unsigned int num_regs, int regofs)
 {
 	mtk_register_reset_controller_common(np, num_regs, regofs,
-		&mtk_reset_ops);
+					     &mtk_reset_ops);
 }
 
 void mtk_register_reset_controller_set_clr(struct device_node *np,
-	unsigned int num_regs, int regofs)
+					   unsigned int num_regs, int regofs)
 {
 	mtk_register_reset_controller_common(np, num_regs, regofs,
-		&mtk_reset_ops_set_clr);
+					     &mtk_reset_ops_set_clr);
 }
 
 MODULE_LICENSE("GPL");
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 04/17] clk: mediatek: reset: Extract common drivers to update function
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To make drivers more clear and readable, we extract common code
within assert and deassert to mtk_reset_update_set_clr() and
mtk_reset_update().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 38 +++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 5cbbcc22a4fc..22fa9f09752c 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -12,24 +12,27 @@
 
 #include "reset.h"
 
-static int mtk_reset_assert(struct reset_controller_dev *rcdev,
-			    unsigned long id)
+static int mtk_reset_update(struct reset_controller_dev *rcdev,
+			    unsigned long id, bool deassert)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	unsigned int val = deassert ? 0 : ~0;
 
 	return regmap_update_bits(data->regmap,
 				  data->regofs + ((id / 32) << 2),
-				  BIT(id % 32), ~0);
+				  BIT(id % 32), val);
+}
+
+static int mtk_reset_assert(struct reset_controller_dev *rcdev,
+			    unsigned long id)
+{
+	return mtk_reset_update(rcdev, id, false);
 }
 
 static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
 			      unsigned long id)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-
-	return regmap_update_bits(data->regmap,
-				  data->regofs + ((id / 32) << 2),
-				  BIT(id % 32), 0);
+	return mtk_reset_update(rcdev, id, true);
 }
 
 static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
@@ -43,24 +46,27 @@ static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
 	return mtk_reset_deassert(rcdev, id);
 }
 
-static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
-				    unsigned long id)
+static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
+				    unsigned long id, bool deassert)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	unsigned int deassert_ofs = deassert ? 0x4 : 0;
 
 	return regmap_write(data->regmap,
-			    data->regofs + ((id / 32) << 4),
+			    data->regofs + ((id / 32) << 4) + deassert_ofs,
 			    BIT(id % 32));
 }
 
+static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
+				    unsigned long id)
+{
+	return mtk_reset_update_set_clr(rcdev, id, false);
+}
+
 static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
 				      unsigned long id)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-
-	return regmap_write(data->regmap,
-			    data->regofs + ((id / 32) << 4) + 0x4,
-			    BIT(id % 32));
+	return mtk_reset_update_set_clr(rcdev, id, true);
 }
 
 static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 04/17] clk: mediatek: reset: Extract common drivers to update function
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To make drivers more clear and readable, we extract common code
within assert and deassert to mtk_reset_update_set_clr() and
mtk_reset_update().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 38 +++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 5cbbcc22a4fc..22fa9f09752c 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -12,24 +12,27 @@
 
 #include "reset.h"
 
-static int mtk_reset_assert(struct reset_controller_dev *rcdev,
-			    unsigned long id)
+static int mtk_reset_update(struct reset_controller_dev *rcdev,
+			    unsigned long id, bool deassert)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	unsigned int val = deassert ? 0 : ~0;
 
 	return regmap_update_bits(data->regmap,
 				  data->regofs + ((id / 32) << 2),
-				  BIT(id % 32), ~0);
+				  BIT(id % 32), val);
+}
+
+static int mtk_reset_assert(struct reset_controller_dev *rcdev,
+			    unsigned long id)
+{
+	return mtk_reset_update(rcdev, id, false);
 }
 
 static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
 			      unsigned long id)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-
-	return regmap_update_bits(data->regmap,
-				  data->regofs + ((id / 32) << 2),
-				  BIT(id % 32), 0);
+	return mtk_reset_update(rcdev, id, true);
 }
 
 static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
@@ -43,24 +46,27 @@ static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
 	return mtk_reset_deassert(rcdev, id);
 }
 
-static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
-				    unsigned long id)
+static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
+				    unsigned long id, bool deassert)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	unsigned int deassert_ofs = deassert ? 0x4 : 0;
 
 	return regmap_write(data->regmap,
-			    data->regofs + ((id / 32) << 4),
+			    data->regofs + ((id / 32) << 4) + deassert_ofs,
 			    BIT(id % 32));
 }
 
+static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
+				    unsigned long id)
+{
+	return mtk_reset_update_set_clr(rcdev, id, false);
+}
+
 static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
 				      unsigned long id)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-
-	return regmap_write(data->regmap,
-			    data->regofs + ((id / 32) << 4) + 0x4,
-			    BIT(id % 32));
+	return mtk_reset_update_set_clr(rcdev, id, true);
 }
 
 static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 04/17] clk: mediatek: reset: Extract common drivers to update function
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To make drivers more clear and readable, we extract common code
within assert and deassert to mtk_reset_update_set_clr() and
mtk_reset_update().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 38 +++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 5cbbcc22a4fc..22fa9f09752c 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -12,24 +12,27 @@
 
 #include "reset.h"
 
-static int mtk_reset_assert(struct reset_controller_dev *rcdev,
-			    unsigned long id)
+static int mtk_reset_update(struct reset_controller_dev *rcdev,
+			    unsigned long id, bool deassert)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	unsigned int val = deassert ? 0 : ~0;
 
 	return regmap_update_bits(data->regmap,
 				  data->regofs + ((id / 32) << 2),
-				  BIT(id % 32), ~0);
+				  BIT(id % 32), val);
+}
+
+static int mtk_reset_assert(struct reset_controller_dev *rcdev,
+			    unsigned long id)
+{
+	return mtk_reset_update(rcdev, id, false);
 }
 
 static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
 			      unsigned long id)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-
-	return regmap_update_bits(data->regmap,
-				  data->regofs + ((id / 32) << 2),
-				  BIT(id % 32), 0);
+	return mtk_reset_update(rcdev, id, true);
 }
 
 static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
@@ -43,24 +46,27 @@ static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
 	return mtk_reset_deassert(rcdev, id);
 }
 
-static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
-				    unsigned long id)
+static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
+				    unsigned long id, bool deassert)
 {
 	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	unsigned int deassert_ofs = deassert ? 0x4 : 0;
 
 	return regmap_write(data->regmap,
-			    data->regofs + ((id / 32) << 4),
+			    data->regofs + ((id / 32) << 4) + deassert_ofs,
 			    BIT(id % 32));
 }
 
+static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
+				    unsigned long id)
+{
+	return mtk_reset_update_set_clr(rcdev, id, false);
+}
+
 static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
 				      unsigned long id)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-
-	return regmap_write(data->regmap,
-			    data->regofs + ((id / 32) << 4) + 0x4,
-			    BIT(id % 32));
+	return mtk_reset_update_set_clr(rcdev, id, true);
 }
 
 static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 05/17] clk: mediatek: reset: Merge and revise reset register function
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

There are two versions for clock reset register control of MediaTek
SoCs. The old hardware is one bit per reset control, and does not
have separate registers for bit set, clear and read-back operations.
This matches the scheme supported by the simple reset driver.

However, because we need to use our data structure "struct mtk_reset",
we can not use the operation of simple reset driver. We keep the
original functions and name this version as "MTK_RST_SIMPLE".

In this patch:
- Add a version enum to separate different MediaTek reset hardware.
- Merge the reset register function of simple and set_clr into one
  function "mtk_register_reset_controller".
- Rename input variable "num_regs" to "rst_set_nr" to avoid
  confusion. This variable is used to define the number of reset set.
- Rename "regofs" to "reg_ofs".
- Adjust delaration type for mtk_register_reset_controller().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mt2701-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt2701-g3d.c |  2 +-
 drivers/clk/mediatek/clk-mt2701-hif.c |  2 +-
 drivers/clk/mediatek/clk-mt2701.c     |  4 +--
 drivers/clk/mediatek/clk-mt2712.c     |  4 +--
 drivers/clk/mediatek/clk-mt7622-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt7622-hif.c |  4 +--
 drivers/clk/mediatek/clk-mt7622.c     |  4 +--
 drivers/clk/mediatek/clk-mt7629-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt7629-hif.c |  4 +--
 drivers/clk/mediatek/clk-mt8135.c     |  4 +--
 drivers/clk/mediatek/clk-mt8173.c     |  4 +--
 drivers/clk/mediatek/clk-mt8183.c     |  3 +-
 drivers/clk/mediatek/reset.c          | 40 ++++++++++++---------------
 drivers/clk/mediatek/reset.h          | 11 +++++---
 15 files changed, 46 insertions(+), 46 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
index 100ff6ca609e..0270979ccc20 100644
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -58,7 +58,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
index 1328c112a38f..e406f863dcf0 100644
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -52,7 +52,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0xc);
+	mtk_register_reset_controller(node, 1, 0xc, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 61444881c539..352ca7a646c3 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -57,7 +57,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 1eb3e4563c3f..591479222e75 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -785,7 +785,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
 
 	return 0;
 }
@@ -908,7 +908,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x0);
+	mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index ff72b9ab945b..b311b43fbbd3 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1361,7 +1361,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
 
 	return r;
 }
@@ -1383,7 +1383,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0);
+	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
index c9947dc7ba5a..bfdd09f3b72d 100644
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -82,7 +82,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
index 628be0c9f888..892da27f6077 100644
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -93,7 +93,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
@@ -115,7 +115,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 0e1fb30a1e98..5bb3757f4217 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -663,7 +663,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 1, 0x30);
+	mtk_register_reset_controller(node, 1, 0x30, MTK_RST_SIMPLE);
 
 	return 0;
 }
@@ -714,7 +714,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 
 	clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
 
-	mtk_register_reset_controller(node, 2, 0x0);
+	mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c
index 88279d0ea1a7..1c57589b39fd 100644
--- a/drivers/clk/mediatek/clk-mt7629-eth.c
+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -92,7 +92,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c
index 5c5b37207afb..6761151ca839 100644
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -88,7 +88,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
@@ -110,7 +110,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c
index 09ad272d51f1..d95b5dfa580c 100644
--- a/drivers/clk/mediatek/clk-mt8135.c
+++ b/drivers/clk/mediatek/clk-mt8135.c
@@ -559,7 +559,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
 
@@ -587,7 +587,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0);
+	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 46b7655feeaa..56120b148761 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -882,7 +882,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
 
@@ -910,7 +910,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0);
+	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 68496554dd3d..9b27f1ffc600 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -1239,7 +1239,8 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET);
+	mtk_register_reset_controller(node, 4,
+				      INFRA_RST0_SET_OFFSET, MTK_RST_SET_CLR);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 22fa9f09752c..0c506feb8024 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -92,14 +92,25 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 	.reset = mtk_reset_set_clr,
 };
 
-static void mtk_register_reset_controller_common(struct device_node *np,
-						 unsigned int num_regs,
-						 int regofs,
-						 const struct reset_control_ops *reset_ops)
+void mtk_register_reset_controller(struct device_node *np,
+				   u32 rst_set_nr, u16 reg_ofs, u8 version)
 {
 	struct mtk_reset *data;
 	int ret;
 	struct regmap *regmap;
+	const struct reset_control_ops *rcops = NULL;
+
+	switch (version) {
+	case MTK_RST_SIMPLE:
+		rcops = &mtk_reset_ops;
+		break;
+	case MTK_RST_SET_CLR:
+		rcops = &mtk_reset_ops_set_clr;
+		break;
+	default:
+		pr_err("Unknown reset version %d\n", version);
+		return;
+	}
 
 	regmap = device_node_to_regmap(np);
 	if (IS_ERR(regmap)) {
@@ -112,32 +123,17 @@ static void mtk_register_reset_controller_common(struct device_node *np,
 		return;
 
 	data->regmap = regmap;
-	data->regofs = regofs;
+	data->regofs = reg_ofs;
 	data->rcdev.owner = THIS_MODULE;
-	data->rcdev.nr_resets = num_regs * 32;
-	data->rcdev.ops = reset_ops;
+	data->rcdev.nr_resets = rst_set_nr * 32;
+	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
 
 	ret = reset_controller_register(&data->rcdev);
 	if (ret) {
 		pr_err("could not register reset controller: %d\n", ret);
 		kfree(data);
-		return;
 	}
 }
 
-void mtk_register_reset_controller(struct device_node *np,
-				   unsigned int num_regs, int regofs)
-{
-	mtk_register_reset_controller_common(np, num_regs, regofs,
-					     &mtk_reset_ops);
-}
-
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-					   unsigned int num_regs, int regofs)
-{
-	mtk_register_reset_controller_common(np, num_regs, regofs,
-					     &mtk_reset_ops_set_clr);
-}
-
 MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 764a8affe206..95001c8044b1 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -9,6 +9,12 @@
 #include <linux/reset-controller.h>
 #include <linux/types.h>
 
+enum mtk_reset_version {
+	MTK_RST_SIMPLE = 0,
+	MTK_RST_SET_CLR,
+	MTK_RST_MAX,
+};
+
 struct mtk_reset {
 	struct regmap *regmap;
 	int regofs;
@@ -16,9 +22,6 @@ struct mtk_reset {
 };
 
 void mtk_register_reset_controller(struct device_node *np,
-				   unsigned int num_regs, int regofs);
-
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-					   unsigned int num_regs, int regofs);
+				   u32 rst_set_nr, u16 reg_ofs, u8 version);
 
 #endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 05/17] clk: mediatek: reset: Merge and revise reset register function
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

There are two versions for clock reset register control of MediaTek
SoCs. The old hardware is one bit per reset control, and does not
have separate registers for bit set, clear and read-back operations.
This matches the scheme supported by the simple reset driver.

However, because we need to use our data structure "struct mtk_reset",
we can not use the operation of simple reset driver. We keep the
original functions and name this version as "MTK_RST_SIMPLE".

In this patch:
- Add a version enum to separate different MediaTek reset hardware.
- Merge the reset register function of simple and set_clr into one
  function "mtk_register_reset_controller".
- Rename input variable "num_regs" to "rst_set_nr" to avoid
  confusion. This variable is used to define the number of reset set.
- Rename "regofs" to "reg_ofs".
- Adjust delaration type for mtk_register_reset_controller().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mt2701-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt2701-g3d.c |  2 +-
 drivers/clk/mediatek/clk-mt2701-hif.c |  2 +-
 drivers/clk/mediatek/clk-mt2701.c     |  4 +--
 drivers/clk/mediatek/clk-mt2712.c     |  4 +--
 drivers/clk/mediatek/clk-mt7622-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt7622-hif.c |  4 +--
 drivers/clk/mediatek/clk-mt7622.c     |  4 +--
 drivers/clk/mediatek/clk-mt7629-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt7629-hif.c |  4 +--
 drivers/clk/mediatek/clk-mt8135.c     |  4 +--
 drivers/clk/mediatek/clk-mt8173.c     |  4 +--
 drivers/clk/mediatek/clk-mt8183.c     |  3 +-
 drivers/clk/mediatek/reset.c          | 40 ++++++++++++---------------
 drivers/clk/mediatek/reset.h          | 11 +++++---
 15 files changed, 46 insertions(+), 46 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
index 100ff6ca609e..0270979ccc20 100644
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -58,7 +58,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
index 1328c112a38f..e406f863dcf0 100644
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -52,7 +52,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0xc);
+	mtk_register_reset_controller(node, 1, 0xc, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 61444881c539..352ca7a646c3 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -57,7 +57,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 1eb3e4563c3f..591479222e75 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -785,7 +785,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
 
 	return 0;
 }
@@ -908,7 +908,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x0);
+	mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index ff72b9ab945b..b311b43fbbd3 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1361,7 +1361,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
 
 	return r;
 }
@@ -1383,7 +1383,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0);
+	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
index c9947dc7ba5a..bfdd09f3b72d 100644
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -82,7 +82,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
index 628be0c9f888..892da27f6077 100644
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -93,7 +93,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
@@ -115,7 +115,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 0e1fb30a1e98..5bb3757f4217 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -663,7 +663,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 1, 0x30);
+	mtk_register_reset_controller(node, 1, 0x30, MTK_RST_SIMPLE);
 
 	return 0;
 }
@@ -714,7 +714,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 
 	clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
 
-	mtk_register_reset_controller(node, 2, 0x0);
+	mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c
index 88279d0ea1a7..1c57589b39fd 100644
--- a/drivers/clk/mediatek/clk-mt7629-eth.c
+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -92,7 +92,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c
index 5c5b37207afb..6761151ca839 100644
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -88,7 +88,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
@@ -110,7 +110,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c
index 09ad272d51f1..d95b5dfa580c 100644
--- a/drivers/clk/mediatek/clk-mt8135.c
+++ b/drivers/clk/mediatek/clk-mt8135.c
@@ -559,7 +559,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
 
@@ -587,7 +587,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0);
+	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 46b7655feeaa..56120b148761 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -882,7 +882,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
 
@@ -910,7 +910,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0);
+	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 68496554dd3d..9b27f1ffc600 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -1239,7 +1239,8 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET);
+	mtk_register_reset_controller(node, 4,
+				      INFRA_RST0_SET_OFFSET, MTK_RST_SET_CLR);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 22fa9f09752c..0c506feb8024 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -92,14 +92,25 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 	.reset = mtk_reset_set_clr,
 };
 
-static void mtk_register_reset_controller_common(struct device_node *np,
-						 unsigned int num_regs,
-						 int regofs,
-						 const struct reset_control_ops *reset_ops)
+void mtk_register_reset_controller(struct device_node *np,
+				   u32 rst_set_nr, u16 reg_ofs, u8 version)
 {
 	struct mtk_reset *data;
 	int ret;
 	struct regmap *regmap;
+	const struct reset_control_ops *rcops = NULL;
+
+	switch (version) {
+	case MTK_RST_SIMPLE:
+		rcops = &mtk_reset_ops;
+		break;
+	case MTK_RST_SET_CLR:
+		rcops = &mtk_reset_ops_set_clr;
+		break;
+	default:
+		pr_err("Unknown reset version %d\n", version);
+		return;
+	}
 
 	regmap = device_node_to_regmap(np);
 	if (IS_ERR(regmap)) {
@@ -112,32 +123,17 @@ static void mtk_register_reset_controller_common(struct device_node *np,
 		return;
 
 	data->regmap = regmap;
-	data->regofs = regofs;
+	data->regofs = reg_ofs;
 	data->rcdev.owner = THIS_MODULE;
-	data->rcdev.nr_resets = num_regs * 32;
-	data->rcdev.ops = reset_ops;
+	data->rcdev.nr_resets = rst_set_nr * 32;
+	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
 
 	ret = reset_controller_register(&data->rcdev);
 	if (ret) {
 		pr_err("could not register reset controller: %d\n", ret);
 		kfree(data);
-		return;
 	}
 }
 
-void mtk_register_reset_controller(struct device_node *np,
-				   unsigned int num_regs, int regofs)
-{
-	mtk_register_reset_controller_common(np, num_regs, regofs,
-					     &mtk_reset_ops);
-}
-
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-					   unsigned int num_regs, int regofs)
-{
-	mtk_register_reset_controller_common(np, num_regs, regofs,
-					     &mtk_reset_ops_set_clr);
-}
-
 MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 764a8affe206..95001c8044b1 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -9,6 +9,12 @@
 #include <linux/reset-controller.h>
 #include <linux/types.h>
 
+enum mtk_reset_version {
+	MTK_RST_SIMPLE = 0,
+	MTK_RST_SET_CLR,
+	MTK_RST_MAX,
+};
+
 struct mtk_reset {
 	struct regmap *regmap;
 	int regofs;
@@ -16,9 +22,6 @@ struct mtk_reset {
 };
 
 void mtk_register_reset_controller(struct device_node *np,
-				   unsigned int num_regs, int regofs);
-
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-					   unsigned int num_regs, int regofs);
+				   u32 rst_set_nr, u16 reg_ofs, u8 version);
 
 #endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 05/17] clk: mediatek: reset: Merge and revise reset register function
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

There are two versions for clock reset register control of MediaTek
SoCs. The old hardware is one bit per reset control, and does not
have separate registers for bit set, clear and read-back operations.
This matches the scheme supported by the simple reset driver.

However, because we need to use our data structure "struct mtk_reset",
we can not use the operation of simple reset driver. We keep the
original functions and name this version as "MTK_RST_SIMPLE".

In this patch:
- Add a version enum to separate different MediaTek reset hardware.
- Merge the reset register function of simple and set_clr into one
  function "mtk_register_reset_controller".
- Rename input variable "num_regs" to "rst_set_nr" to avoid
  confusion. This variable is used to define the number of reset set.
- Rename "regofs" to "reg_ofs".
- Adjust delaration type for mtk_register_reset_controller().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mt2701-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt2701-g3d.c |  2 +-
 drivers/clk/mediatek/clk-mt2701-hif.c |  2 +-
 drivers/clk/mediatek/clk-mt2701.c     |  4 +--
 drivers/clk/mediatek/clk-mt2712.c     |  4 +--
 drivers/clk/mediatek/clk-mt7622-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt7622-hif.c |  4 +--
 drivers/clk/mediatek/clk-mt7622.c     |  4 +--
 drivers/clk/mediatek/clk-mt7629-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt7629-hif.c |  4 +--
 drivers/clk/mediatek/clk-mt8135.c     |  4 +--
 drivers/clk/mediatek/clk-mt8173.c     |  4 +--
 drivers/clk/mediatek/clk-mt8183.c     |  3 +-
 drivers/clk/mediatek/reset.c          | 40 ++++++++++++---------------
 drivers/clk/mediatek/reset.h          | 11 +++++---
 15 files changed, 46 insertions(+), 46 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
index 100ff6ca609e..0270979ccc20 100644
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -58,7 +58,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
index 1328c112a38f..e406f863dcf0 100644
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -52,7 +52,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0xc);
+	mtk_register_reset_controller(node, 1, 0xc, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 61444881c539..352ca7a646c3 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -57,7 +57,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 1eb3e4563c3f..591479222e75 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -785,7 +785,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
 
 	return 0;
 }
@@ -908,7 +908,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x0);
+	mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index ff72b9ab945b..b311b43fbbd3 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1361,7 +1361,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
 
 	return r;
 }
@@ -1383,7 +1383,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0);
+	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
index c9947dc7ba5a..bfdd09f3b72d 100644
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -82,7 +82,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
index 628be0c9f888..892da27f6077 100644
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -93,7 +93,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
@@ -115,7 +115,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 0e1fb30a1e98..5bb3757f4217 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -663,7 +663,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 1, 0x30);
+	mtk_register_reset_controller(node, 1, 0x30, MTK_RST_SIMPLE);
 
 	return 0;
 }
@@ -714,7 +714,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 
 	clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
 
-	mtk_register_reset_controller(node, 2, 0x0);
+	mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c
index 88279d0ea1a7..1c57589b39fd 100644
--- a/drivers/clk/mediatek/clk-mt7629-eth.c
+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -92,7 +92,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c
index 5c5b37207afb..6761151ca839 100644
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -88,7 +88,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
@@ -110,7 +110,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c
index 09ad272d51f1..d95b5dfa580c 100644
--- a/drivers/clk/mediatek/clk-mt8135.c
+++ b/drivers/clk/mediatek/clk-mt8135.c
@@ -559,7 +559,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
 
@@ -587,7 +587,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0);
+	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 46b7655feeaa..56120b148761 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -882,7 +882,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
 
@@ -910,7 +910,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0);
+	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 68496554dd3d..9b27f1ffc600 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -1239,7 +1239,8 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET);
+	mtk_register_reset_controller(node, 4,
+				      INFRA_RST0_SET_OFFSET, MTK_RST_SET_CLR);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 22fa9f09752c..0c506feb8024 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -92,14 +92,25 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 	.reset = mtk_reset_set_clr,
 };
 
-static void mtk_register_reset_controller_common(struct device_node *np,
-						 unsigned int num_regs,
-						 int regofs,
-						 const struct reset_control_ops *reset_ops)
+void mtk_register_reset_controller(struct device_node *np,
+				   u32 rst_set_nr, u16 reg_ofs, u8 version)
 {
 	struct mtk_reset *data;
 	int ret;
 	struct regmap *regmap;
+	const struct reset_control_ops *rcops = NULL;
+
+	switch (version) {
+	case MTK_RST_SIMPLE:
+		rcops = &mtk_reset_ops;
+		break;
+	case MTK_RST_SET_CLR:
+		rcops = &mtk_reset_ops_set_clr;
+		break;
+	default:
+		pr_err("Unknown reset version %d\n", version);
+		return;
+	}
 
 	regmap = device_node_to_regmap(np);
 	if (IS_ERR(regmap)) {
@@ -112,32 +123,17 @@ static void mtk_register_reset_controller_common(struct device_node *np,
 		return;
 
 	data->regmap = regmap;
-	data->regofs = regofs;
+	data->regofs = reg_ofs;
 	data->rcdev.owner = THIS_MODULE;
-	data->rcdev.nr_resets = num_regs * 32;
-	data->rcdev.ops = reset_ops;
+	data->rcdev.nr_resets = rst_set_nr * 32;
+	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
 
 	ret = reset_controller_register(&data->rcdev);
 	if (ret) {
 		pr_err("could not register reset controller: %d\n", ret);
 		kfree(data);
-		return;
 	}
 }
 
-void mtk_register_reset_controller(struct device_node *np,
-				   unsigned int num_regs, int regofs)
-{
-	mtk_register_reset_controller_common(np, num_regs, regofs,
-					     &mtk_reset_ops);
-}
-
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-					   unsigned int num_regs, int regofs)
-{
-	mtk_register_reset_controller_common(np, num_regs, regofs,
-					     &mtk_reset_ops_set_clr);
-}
-
 MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 764a8affe206..95001c8044b1 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -9,6 +9,12 @@
 #include <linux/reset-controller.h>
 #include <linux/types.h>
 
+enum mtk_reset_version {
+	MTK_RST_SIMPLE = 0,
+	MTK_RST_SET_CLR,
+	MTK_RST_MAX,
+};
+
 struct mtk_reset {
 	struct regmap *regmap;
 	int regofs;
@@ -16,9 +22,6 @@ struct mtk_reset {
 };
 
 void mtk_register_reset_controller(struct device_node *np,
-				   unsigned int num_regs, int regofs);
-
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-					   unsigned int num_regs, int regofs);
+				   u32 rst_set_nr, u16 reg_ofs, u8 version);
 
 #endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 06/17] clk: mediatek: reset: Revise structure to control reset register
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To declare the reset data easier instead of using many input variables
to mtk_register_reset_controller().

- Add mtk_clk_rst_desc to input the reset register data.
- Rename "mtk_reset" to "mtk_clk_rst_data". We use it to store reset
  register data and store reset controller device. It's more easy to
  manager the data for each reset controller.
- Extract container_of in update functions to to_mtk_clk_rst_data().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mt2701-eth.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt2701-g3d.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt2701-hif.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt2701.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt2712.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt7622-eth.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt7622-hif.c | 10 +++++++--
 drivers/clk/mediatek/clk-mt7622.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt7629-eth.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt7629-hif.c | 10 +++++++--
 drivers/clk/mediatek/clk-mt8135.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt8173.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt8183.c     |  9 ++++++--
 drivers/clk/mediatek/reset.c          | 32 ++++++++++++++++++---------
 drivers/clk/mediatek/reset.h          | 12 +++++++---
 15 files changed, 173 insertions(+), 35 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
index 0270979ccc20..b651f3878267 100644
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -36,6 +36,12 @@ static const struct mtk_gate eth_clks[] = {
 	GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static const struct of_device_id of_match_clk_mt2701_eth[] = {
 	{ .compatible = "mediatek,mt2701-ethsys", },
 	{}
@@ -58,7 +64,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
index e406f863dcf0..7696870f6f23 100644
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -35,6 +35,12 @@ static const struct mtk_gate g3d_clks[] = {
 	GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0xc,
+};
+
 static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -52,7 +58,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0xc, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 352ca7a646c3..57fa63c47452 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -33,6 +33,12 @@ static const struct mtk_gate hif_clks[] = {
 	GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static const struct of_device_id of_match_clk_mt2701_hif[] = {
 	{ .compatible = "mediatek,mt2701-hifsys", },
 	{}
@@ -57,7 +63,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 591479222e75..496afc7483ae 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -735,6 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
 	FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x30,
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	},
+};
+
 static struct clk_onecell_data *infra_clk_data;
 
 static void __init mtk_infrasys_init_early(struct device_node *node)
@@ -785,7 +800,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -908,7 +923,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index b311b43fbbd3..04ff9b1327d2 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1258,6 +1258,21 @@ static const struct mtk_pll_data plls[] = {
 		0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infra */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x30,
+	},
+	/* peri */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	},
+};
+
 static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -1361,7 +1376,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 
 	return r;
 }
@@ -1383,7 +1398,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
index bfdd09f3b72d..3bf7f4610ad1 100644
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -65,6 +65,12 @@ static const struct mtk_gate sgmii_clks[] = {
 		   "ssusb_cdr_fb", 5),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -82,7 +88,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
index 892da27f6077..88fe9b447158 100644
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -76,6 +76,12 @@ static const struct mtk_gate pcie_clks[] = {
 	GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -93,7 +99,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
@@ -115,7 +121,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 5bb3757f4217..3f937723b211 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -610,6 +610,21 @@ static struct mtk_composite peri_muxes[] = {
 	MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 1,
+		.reg_ofs = 0x30,
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	},
+};
+
 static int mtk_topckgen_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -663,7 +678,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 1, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -714,7 +729,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 
 	clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
 
-	mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c
index 1c57589b39fd..079b8facf63f 100644
--- a/drivers/clk/mediatek/clk-mt7629-eth.c
+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -76,6 +76,12 @@ static const struct mtk_gate sgmii_clks[2][4] = {
 	}
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -92,7 +98,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c
index 6761151ca839..69a2ecf8d3df 100644
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -71,6 +71,12 @@ static const struct mtk_gate pcie_clks[] = {
 	GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -88,7 +94,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
@@ -110,7 +116,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c
index d95b5dfa580c..f93774ea35af 100644
--- a/drivers/clk/mediatek/clk-mt8135.c
+++ b/drivers/clk/mediatek/clk-mt8135.c
@@ -514,6 +514,21 @@ static const struct mtk_composite peri_clks[] __initconst = {
 	MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x30,
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	}
+};
+
 static void __init mtk_topckgen_init(struct device_node *node)
 {
 	struct clk_onecell_data *clk_data;
@@ -559,7 +574,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
 
@@ -587,7 +602,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 56120b148761..593a5d8ebf3d 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -819,6 +819,21 @@ static const struct mtk_gate venclt_clks[] __initconst = {
 	GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x30,
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	}
+};
+
 static struct clk_onecell_data *mt8173_top_clk_data __initdata;
 static struct clk_onecell_data *mt8173_pll_clk_data __initdata;
 
@@ -882,7 +897,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
 
@@ -910,7 +925,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 9b27f1ffc600..c957249d4cdf 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -1153,6 +1153,12 @@ static const struct mtk_pll_data plls[] = {
 		0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_set_nr = 4,
+	.reg_ofs = INFRA_RST0_SET_OFFSET,
+};
+
 static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -1239,8 +1245,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, 4,
-				      INFRA_RST0_SET_OFFSET, MTK_RST_SET_CLR);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 0c506feb8024..587cf8e626de 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -12,14 +12,19 @@
 
 #include "reset.h"
 
+static inline struct mtk_clk_rst_data *to_mtk_clk_rst_data(struct reset_controller_dev *rcdev)
+{
+	return container_of(rcdev, struct mtk_clk_rst_data, rcdev);
+}
+
 static int mtk_reset_update(struct reset_controller_dev *rcdev,
 			    unsigned long id, bool deassert)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
 	unsigned int val = deassert ? 0 : ~0;
 
 	return regmap_update_bits(data->regmap,
-				  data->regofs + ((id / 32) << 2),
+				  data->desc->reg_ofs + ((id / 32) << 2),
 				  BIT(id % 32), val);
 }
 
@@ -49,11 +54,11 @@ static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
 static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
 				    unsigned long id, bool deassert)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
 	unsigned int deassert_ofs = deassert ? 0x4 : 0;
 
 	return regmap_write(data->regmap,
-			    data->regofs + ((id / 32) << 4) + deassert_ofs,
+			    data->desc->reg_ofs + ((id / 32) << 4) + deassert_ofs,
 			    BIT(id % 32));
 }
 
@@ -93,14 +98,19 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 };
 
 void mtk_register_reset_controller(struct device_node *np,
-				   u32 rst_set_nr, u16 reg_ofs, u8 version)
+				   const struct mtk_clk_rst_desc *desc)
 {
-	struct mtk_reset *data;
-	int ret;
 	struct regmap *regmap;
 	const struct reset_control_ops *rcops = NULL;
+	struct mtk_clk_rst_data *data;
+	int ret;
+
+	if (!desc) {
+		pr_err("mtk clock reset desc is NULL\n");
+		return;
+	}
 
-	switch (version) {
+	switch (desc->version) {
 	case MTK_RST_SIMPLE:
 		rcops = &mtk_reset_ops;
 		break;
@@ -108,7 +118,7 @@ void mtk_register_reset_controller(struct device_node *np,
 		rcops = &mtk_reset_ops_set_clr;
 		break;
 	default:
-		pr_err("Unknown reset version %d\n", version);
+		pr_err("Unknown reset version %d\n", desc->version);
 		return;
 	}
 
@@ -122,10 +132,10 @@ void mtk_register_reset_controller(struct device_node *np,
 	if (!data)
 		return;
 
+	data->desc = desc;
 	data->regmap = regmap;
-	data->regofs = reg_ofs;
 	data->rcdev.owner = THIS_MODULE;
-	data->rcdev.nr_resets = rst_set_nr * 32;
+	data->rcdev.nr_resets = desc->rst_set_nr * 32;
 	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
 
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 95001c8044b1..db558ea4a474 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -15,13 +15,19 @@ enum mtk_reset_version {
 	MTK_RST_MAX,
 };
 
-struct mtk_reset {
+struct mtk_clk_rst_desc {
+	u8 version;
+	u32 rst_set_nr;
+	u16 reg_ofs;
+};
+
+struct mtk_clk_rst_data {
 	struct regmap *regmap;
-	int regofs;
 	struct reset_controller_dev rcdev;
+	const struct mtk_clk_rst_desc *desc;
 };
 
 void mtk_register_reset_controller(struct device_node *np,
-				   u32 rst_set_nr, u16 reg_ofs, u8 version);
+				   const struct mtk_clk_rst_desc *desc);
 
 #endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 06/17] clk: mediatek: reset: Revise structure to control reset register
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To declare the reset data easier instead of using many input variables
to mtk_register_reset_controller().

- Add mtk_clk_rst_desc to input the reset register data.
- Rename "mtk_reset" to "mtk_clk_rst_data". We use it to store reset
  register data and store reset controller device. It's more easy to
  manager the data for each reset controller.
- Extract container_of in update functions to to_mtk_clk_rst_data().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mt2701-eth.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt2701-g3d.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt2701-hif.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt2701.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt2712.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt7622-eth.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt7622-hif.c | 10 +++++++--
 drivers/clk/mediatek/clk-mt7622.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt7629-eth.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt7629-hif.c | 10 +++++++--
 drivers/clk/mediatek/clk-mt8135.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt8173.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt8183.c     |  9 ++++++--
 drivers/clk/mediatek/reset.c          | 32 ++++++++++++++++++---------
 drivers/clk/mediatek/reset.h          | 12 +++++++---
 15 files changed, 173 insertions(+), 35 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
index 0270979ccc20..b651f3878267 100644
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -36,6 +36,12 @@ static const struct mtk_gate eth_clks[] = {
 	GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static const struct of_device_id of_match_clk_mt2701_eth[] = {
 	{ .compatible = "mediatek,mt2701-ethsys", },
 	{}
@@ -58,7 +64,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
index e406f863dcf0..7696870f6f23 100644
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -35,6 +35,12 @@ static const struct mtk_gate g3d_clks[] = {
 	GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0xc,
+};
+
 static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -52,7 +58,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0xc, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 352ca7a646c3..57fa63c47452 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -33,6 +33,12 @@ static const struct mtk_gate hif_clks[] = {
 	GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static const struct of_device_id of_match_clk_mt2701_hif[] = {
 	{ .compatible = "mediatek,mt2701-hifsys", },
 	{}
@@ -57,7 +63,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 591479222e75..496afc7483ae 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -735,6 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
 	FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x30,
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	},
+};
+
 static struct clk_onecell_data *infra_clk_data;
 
 static void __init mtk_infrasys_init_early(struct device_node *node)
@@ -785,7 +800,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -908,7 +923,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index b311b43fbbd3..04ff9b1327d2 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1258,6 +1258,21 @@ static const struct mtk_pll_data plls[] = {
 		0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infra */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x30,
+	},
+	/* peri */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	},
+};
+
 static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -1361,7 +1376,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 
 	return r;
 }
@@ -1383,7 +1398,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
index bfdd09f3b72d..3bf7f4610ad1 100644
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -65,6 +65,12 @@ static const struct mtk_gate sgmii_clks[] = {
 		   "ssusb_cdr_fb", 5),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -82,7 +88,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
index 892da27f6077..88fe9b447158 100644
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -76,6 +76,12 @@ static const struct mtk_gate pcie_clks[] = {
 	GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -93,7 +99,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
@@ -115,7 +121,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 5bb3757f4217..3f937723b211 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -610,6 +610,21 @@ static struct mtk_composite peri_muxes[] = {
 	MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 1,
+		.reg_ofs = 0x30,
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	},
+};
+
 static int mtk_topckgen_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -663,7 +678,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 1, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -714,7 +729,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 
 	clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
 
-	mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c
index 1c57589b39fd..079b8facf63f 100644
--- a/drivers/clk/mediatek/clk-mt7629-eth.c
+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -76,6 +76,12 @@ static const struct mtk_gate sgmii_clks[2][4] = {
 	}
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -92,7 +98,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c
index 6761151ca839..69a2ecf8d3df 100644
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -71,6 +71,12 @@ static const struct mtk_gate pcie_clks[] = {
 	GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -88,7 +94,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
@@ -110,7 +116,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c
index d95b5dfa580c..f93774ea35af 100644
--- a/drivers/clk/mediatek/clk-mt8135.c
+++ b/drivers/clk/mediatek/clk-mt8135.c
@@ -514,6 +514,21 @@ static const struct mtk_composite peri_clks[] __initconst = {
 	MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x30,
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	}
+};
+
 static void __init mtk_topckgen_init(struct device_node *node)
 {
 	struct clk_onecell_data *clk_data;
@@ -559,7 +574,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
 
@@ -587,7 +602,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 56120b148761..593a5d8ebf3d 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -819,6 +819,21 @@ static const struct mtk_gate venclt_clks[] __initconst = {
 	GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x30,
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	}
+};
+
 static struct clk_onecell_data *mt8173_top_clk_data __initdata;
 static struct clk_onecell_data *mt8173_pll_clk_data __initdata;
 
@@ -882,7 +897,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
 
@@ -910,7 +925,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 9b27f1ffc600..c957249d4cdf 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -1153,6 +1153,12 @@ static const struct mtk_pll_data plls[] = {
 		0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_set_nr = 4,
+	.reg_ofs = INFRA_RST0_SET_OFFSET,
+};
+
 static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -1239,8 +1245,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, 4,
-				      INFRA_RST0_SET_OFFSET, MTK_RST_SET_CLR);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 0c506feb8024..587cf8e626de 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -12,14 +12,19 @@
 
 #include "reset.h"
 
+static inline struct mtk_clk_rst_data *to_mtk_clk_rst_data(struct reset_controller_dev *rcdev)
+{
+	return container_of(rcdev, struct mtk_clk_rst_data, rcdev);
+}
+
 static int mtk_reset_update(struct reset_controller_dev *rcdev,
 			    unsigned long id, bool deassert)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
 	unsigned int val = deassert ? 0 : ~0;
 
 	return regmap_update_bits(data->regmap,
-				  data->regofs + ((id / 32) << 2),
+				  data->desc->reg_ofs + ((id / 32) << 2),
 				  BIT(id % 32), val);
 }
 
@@ -49,11 +54,11 @@ static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
 static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
 				    unsigned long id, bool deassert)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
 	unsigned int deassert_ofs = deassert ? 0x4 : 0;
 
 	return regmap_write(data->regmap,
-			    data->regofs + ((id / 32) << 4) + deassert_ofs,
+			    data->desc->reg_ofs + ((id / 32) << 4) + deassert_ofs,
 			    BIT(id % 32));
 }
 
@@ -93,14 +98,19 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 };
 
 void mtk_register_reset_controller(struct device_node *np,
-				   u32 rst_set_nr, u16 reg_ofs, u8 version)
+				   const struct mtk_clk_rst_desc *desc)
 {
-	struct mtk_reset *data;
-	int ret;
 	struct regmap *regmap;
 	const struct reset_control_ops *rcops = NULL;
+	struct mtk_clk_rst_data *data;
+	int ret;
+
+	if (!desc) {
+		pr_err("mtk clock reset desc is NULL\n");
+		return;
+	}
 
-	switch (version) {
+	switch (desc->version) {
 	case MTK_RST_SIMPLE:
 		rcops = &mtk_reset_ops;
 		break;
@@ -108,7 +118,7 @@ void mtk_register_reset_controller(struct device_node *np,
 		rcops = &mtk_reset_ops_set_clr;
 		break;
 	default:
-		pr_err("Unknown reset version %d\n", version);
+		pr_err("Unknown reset version %d\n", desc->version);
 		return;
 	}
 
@@ -122,10 +132,10 @@ void mtk_register_reset_controller(struct device_node *np,
 	if (!data)
 		return;
 
+	data->desc = desc;
 	data->regmap = regmap;
-	data->regofs = reg_ofs;
 	data->rcdev.owner = THIS_MODULE;
-	data->rcdev.nr_resets = rst_set_nr * 32;
+	data->rcdev.nr_resets = desc->rst_set_nr * 32;
 	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
 
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 95001c8044b1..db558ea4a474 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -15,13 +15,19 @@ enum mtk_reset_version {
 	MTK_RST_MAX,
 };
 
-struct mtk_reset {
+struct mtk_clk_rst_desc {
+	u8 version;
+	u32 rst_set_nr;
+	u16 reg_ofs;
+};
+
+struct mtk_clk_rst_data {
 	struct regmap *regmap;
-	int regofs;
 	struct reset_controller_dev rcdev;
+	const struct mtk_clk_rst_desc *desc;
 };
 
 void mtk_register_reset_controller(struct device_node *np,
-				   u32 rst_set_nr, u16 reg_ofs, u8 version);
+				   const struct mtk_clk_rst_desc *desc);
 
 #endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


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* [PATCH V3 06/17] clk: mediatek: reset: Revise structure to control reset register
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To declare the reset data easier instead of using many input variables
to mtk_register_reset_controller().

- Add mtk_clk_rst_desc to input the reset register data.
- Rename "mtk_reset" to "mtk_clk_rst_data". We use it to store reset
  register data and store reset controller device. It's more easy to
  manager the data for each reset controller.
- Extract container_of in update functions to to_mtk_clk_rst_data().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mt2701-eth.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt2701-g3d.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt2701-hif.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt2701.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt2712.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt7622-eth.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt7622-hif.c | 10 +++++++--
 drivers/clk/mediatek/clk-mt7622.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt7629-eth.c |  8 ++++++-
 drivers/clk/mediatek/clk-mt7629-hif.c | 10 +++++++--
 drivers/clk/mediatek/clk-mt8135.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt8173.c     | 19 ++++++++++++++--
 drivers/clk/mediatek/clk-mt8183.c     |  9 ++++++--
 drivers/clk/mediatek/reset.c          | 32 ++++++++++++++++++---------
 drivers/clk/mediatek/reset.h          | 12 +++++++---
 15 files changed, 173 insertions(+), 35 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
index 0270979ccc20..b651f3878267 100644
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -36,6 +36,12 @@ static const struct mtk_gate eth_clks[] = {
 	GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static const struct of_device_id of_match_clk_mt2701_eth[] = {
 	{ .compatible = "mediatek,mt2701-ethsys", },
 	{}
@@ -58,7 +64,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
index e406f863dcf0..7696870f6f23 100644
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -35,6 +35,12 @@ static const struct mtk_gate g3d_clks[] = {
 	GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0xc,
+};
+
 static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -52,7 +58,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0xc, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 352ca7a646c3..57fa63c47452 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -33,6 +33,12 @@ static const struct mtk_gate hif_clks[] = {
 	GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static const struct of_device_id of_match_clk_mt2701_hif[] = {
 	{ .compatible = "mediatek,mt2701-hifsys", },
 	{}
@@ -57,7 +63,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 591479222e75..496afc7483ae 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -735,6 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
 	FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x30,
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	},
+};
+
 static struct clk_onecell_data *infra_clk_data;
 
 static void __init mtk_infrasys_init_early(struct device_node *node)
@@ -785,7 +800,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -908,7 +923,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index b311b43fbbd3..04ff9b1327d2 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1258,6 +1258,21 @@ static const struct mtk_pll_data plls[] = {
 		0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infra */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x30,
+	},
+	/* peri */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	},
+};
+
 static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -1361,7 +1376,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 
 	return r;
 }
@@ -1383,7 +1398,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
index bfdd09f3b72d..3bf7f4610ad1 100644
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -65,6 +65,12 @@ static const struct mtk_gate sgmii_clks[] = {
 		   "ssusb_cdr_fb", 5),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -82,7 +88,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
index 892da27f6077..88fe9b447158 100644
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -76,6 +76,12 @@ static const struct mtk_gate pcie_clks[] = {
 	GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -93,7 +99,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
@@ -115,7 +121,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 5bb3757f4217..3f937723b211 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -610,6 +610,21 @@ static struct mtk_composite peri_muxes[] = {
 	MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 1,
+		.reg_ofs = 0x30,
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	},
+};
+
 static int mtk_topckgen_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -663,7 +678,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 1, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -714,7 +729,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 
 	clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
 
-	mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c
index 1c57589b39fd..079b8facf63f 100644
--- a/drivers/clk/mediatek/clk-mt7629-eth.c
+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -76,6 +76,12 @@ static const struct mtk_gate sgmii_clks[2][4] = {
 	}
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -92,7 +98,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c
index 6761151ca839..69a2ecf8d3df 100644
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -71,6 +71,12 @@ static const struct mtk_gate pcie_clks[] = {
 	GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_set_nr = 1,
+	.reg_ofs = 0x34,
+};
+
 static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -88,7 +94,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
@@ -110,7 +116,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c
index d95b5dfa580c..f93774ea35af 100644
--- a/drivers/clk/mediatek/clk-mt8135.c
+++ b/drivers/clk/mediatek/clk-mt8135.c
@@ -514,6 +514,21 @@ static const struct mtk_composite peri_clks[] __initconst = {
 	MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x30,
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	}
+};
+
 static void __init mtk_topckgen_init(struct device_node *node)
 {
 	struct clk_onecell_data *clk_data;
@@ -559,7 +574,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
 
@@ -587,7 +602,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 56120b148761..593a5d8ebf3d 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -819,6 +819,21 @@ static const struct mtk_gate venclt_clks[] __initconst = {
 	GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x30,
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_set_nr = 2,
+		.reg_ofs = 0x0,
+	}
+};
+
 static struct clk_onecell_data *mt8173_top_clk_data __initdata;
 static struct clk_onecell_data *mt8173_pll_clk_data __initdata;
 
@@ -882,7 +897,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
 
@@ -910,7 +925,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 9b27f1ffc600..c957249d4cdf 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -1153,6 +1153,12 @@ static const struct mtk_pll_data plls[] = {
 		0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_set_nr = 4,
+	.reg_ofs = INFRA_RST0_SET_OFFSET,
+};
+
 static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
@@ -1239,8 +1245,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, 4,
-				      INFRA_RST0_SET_OFFSET, MTK_RST_SET_CLR);
+	mtk_register_reset_controller(node, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 0c506feb8024..587cf8e626de 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -12,14 +12,19 @@
 
 #include "reset.h"
 
+static inline struct mtk_clk_rst_data *to_mtk_clk_rst_data(struct reset_controller_dev *rcdev)
+{
+	return container_of(rcdev, struct mtk_clk_rst_data, rcdev);
+}
+
 static int mtk_reset_update(struct reset_controller_dev *rcdev,
 			    unsigned long id, bool deassert)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
 	unsigned int val = deassert ? 0 : ~0;
 
 	return regmap_update_bits(data->regmap,
-				  data->regofs + ((id / 32) << 2),
+				  data->desc->reg_ofs + ((id / 32) << 2),
 				  BIT(id % 32), val);
 }
 
@@ -49,11 +54,11 @@ static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
 static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
 				    unsigned long id, bool deassert)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
 	unsigned int deassert_ofs = deassert ? 0x4 : 0;
 
 	return regmap_write(data->regmap,
-			    data->regofs + ((id / 32) << 4) + deassert_ofs,
+			    data->desc->reg_ofs + ((id / 32) << 4) + deassert_ofs,
 			    BIT(id % 32));
 }
 
@@ -93,14 +98,19 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 };
 
 void mtk_register_reset_controller(struct device_node *np,
-				   u32 rst_set_nr, u16 reg_ofs, u8 version)
+				   const struct mtk_clk_rst_desc *desc)
 {
-	struct mtk_reset *data;
-	int ret;
 	struct regmap *regmap;
 	const struct reset_control_ops *rcops = NULL;
+	struct mtk_clk_rst_data *data;
+	int ret;
+
+	if (!desc) {
+		pr_err("mtk clock reset desc is NULL\n");
+		return;
+	}
 
-	switch (version) {
+	switch (desc->version) {
 	case MTK_RST_SIMPLE:
 		rcops = &mtk_reset_ops;
 		break;
@@ -108,7 +118,7 @@ void mtk_register_reset_controller(struct device_node *np,
 		rcops = &mtk_reset_ops_set_clr;
 		break;
 	default:
-		pr_err("Unknown reset version %d\n", version);
+		pr_err("Unknown reset version %d\n", desc->version);
 		return;
 	}
 
@@ -122,10 +132,10 @@ void mtk_register_reset_controller(struct device_node *np,
 	if (!data)
 		return;
 
+	data->desc = desc;
 	data->regmap = regmap;
-	data->regofs = reg_ofs;
 	data->rcdev.owner = THIS_MODULE;
-	data->rcdev.nr_resets = rst_set_nr * 32;
+	data->rcdev.nr_resets = desc->rst_set_nr * 32;
 	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
 
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 95001c8044b1..db558ea4a474 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -15,13 +15,19 @@ enum mtk_reset_version {
 	MTK_RST_MAX,
 };
 
-struct mtk_reset {
+struct mtk_clk_rst_desc {
+	u8 version;
+	u32 rst_set_nr;
+	u16 reg_ofs;
+};
+
+struct mtk_clk_rst_data {
 	struct regmap *regmap;
-	int regofs;
 	struct reset_controller_dev rcdev;
+	const struct mtk_clk_rst_desc *desc;
 };
 
 void mtk_register_reset_controller(struct device_node *np,
-				   u32 rst_set_nr, u16 reg_ofs, u8 version);
+				   const struct mtk_clk_rst_desc *desc);
 
 #endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 07/17] clk: mediatek: reset: Add return for clock reset register function
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To make error handling, we add return for mtk_clk_register_rst_ctrl().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 15 +++++++++------
 drivers/clk/mediatek/reset.h |  4 ++--
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 587cf8e626de..03d865f3308e 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -97,8 +97,8 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 	.reset = mtk_reset_set_clr,
 };
 
-void mtk_register_reset_controller(struct device_node *np,
-				   const struct mtk_clk_rst_desc *desc)
+int mtk_register_reset_controller(struct device_node *np,
+				  const struct mtk_clk_rst_desc *desc)
 {
 	struct regmap *regmap;
 	const struct reset_control_ops *rcops = NULL;
@@ -107,7 +107,7 @@ void mtk_register_reset_controller(struct device_node *np,
 
 	if (!desc) {
 		pr_err("mtk clock reset desc is NULL\n");
-		return;
+		return -EINVAL;
 	}
 
 	switch (desc->version) {
@@ -119,18 +119,18 @@ void mtk_register_reset_controller(struct device_node *np,
 		break;
 	default:
 		pr_err("Unknown reset version %d\n", desc->version);
-		return;
+		return -EINVAL;
 	}
 
 	regmap = device_node_to_regmap(np);
 	if (IS_ERR(regmap)) {
 		pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap);
-		return;
+		return -EINVAL;
 	}
 
 	data = kzalloc(sizeof(*data), GFP_KERNEL);
 	if (!data)
-		return;
+		return -ENOMEM;
 
 	data->desc = desc;
 	data->regmap = regmap;
@@ -143,7 +143,10 @@ void mtk_register_reset_controller(struct device_node *np,
 	if (ret) {
 		pr_err("could not register reset controller: %d\n", ret);
 		kfree(data);
+		return ret;
 	}
+
+	return 0;
 }
 
 MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index db558ea4a474..c3a2f2a4f486 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -27,7 +27,7 @@ struct mtk_clk_rst_data {
 	const struct mtk_clk_rst_desc *desc;
 };
 
-void mtk_register_reset_controller(struct device_node *np,
-				   const struct mtk_clk_rst_desc *desc);
+int mtk_register_reset_controller(struct device_node *np,
+				  const struct mtk_clk_rst_desc *desc);
 
 #endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 07/17] clk: mediatek: reset: Add return for clock reset register function
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To make error handling, we add return for mtk_clk_register_rst_ctrl().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 15 +++++++++------
 drivers/clk/mediatek/reset.h |  4 ++--
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 587cf8e626de..03d865f3308e 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -97,8 +97,8 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 	.reset = mtk_reset_set_clr,
 };
 
-void mtk_register_reset_controller(struct device_node *np,
-				   const struct mtk_clk_rst_desc *desc)
+int mtk_register_reset_controller(struct device_node *np,
+				  const struct mtk_clk_rst_desc *desc)
 {
 	struct regmap *regmap;
 	const struct reset_control_ops *rcops = NULL;
@@ -107,7 +107,7 @@ void mtk_register_reset_controller(struct device_node *np,
 
 	if (!desc) {
 		pr_err("mtk clock reset desc is NULL\n");
-		return;
+		return -EINVAL;
 	}
 
 	switch (desc->version) {
@@ -119,18 +119,18 @@ void mtk_register_reset_controller(struct device_node *np,
 		break;
 	default:
 		pr_err("Unknown reset version %d\n", desc->version);
-		return;
+		return -EINVAL;
 	}
 
 	regmap = device_node_to_regmap(np);
 	if (IS_ERR(regmap)) {
 		pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap);
-		return;
+		return -EINVAL;
 	}
 
 	data = kzalloc(sizeof(*data), GFP_KERNEL);
 	if (!data)
-		return;
+		return -ENOMEM;
 
 	data->desc = desc;
 	data->regmap = regmap;
@@ -143,7 +143,10 @@ void mtk_register_reset_controller(struct device_node *np,
 	if (ret) {
 		pr_err("could not register reset controller: %d\n", ret);
 		kfree(data);
+		return ret;
 	}
+
+	return 0;
 }
 
 MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index db558ea4a474..c3a2f2a4f486 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -27,7 +27,7 @@ struct mtk_clk_rst_data {
 	const struct mtk_clk_rst_desc *desc;
 };
 
-void mtk_register_reset_controller(struct device_node *np,
-				   const struct mtk_clk_rst_desc *desc);
+int mtk_register_reset_controller(struct device_node *np,
+				  const struct mtk_clk_rst_desc *desc);
 
 #endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 07/17] clk: mediatek: reset: Add return for clock reset register function
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To make error handling, we add return for mtk_clk_register_rst_ctrl().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 15 +++++++++------
 drivers/clk/mediatek/reset.h |  4 ++--
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 587cf8e626de..03d865f3308e 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -97,8 +97,8 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 	.reset = mtk_reset_set_clr,
 };
 
-void mtk_register_reset_controller(struct device_node *np,
-				   const struct mtk_clk_rst_desc *desc)
+int mtk_register_reset_controller(struct device_node *np,
+				  const struct mtk_clk_rst_desc *desc)
 {
 	struct regmap *regmap;
 	const struct reset_control_ops *rcops = NULL;
@@ -107,7 +107,7 @@ void mtk_register_reset_controller(struct device_node *np,
 
 	if (!desc) {
 		pr_err("mtk clock reset desc is NULL\n");
-		return;
+		return -EINVAL;
 	}
 
 	switch (desc->version) {
@@ -119,18 +119,18 @@ void mtk_register_reset_controller(struct device_node *np,
 		break;
 	default:
 		pr_err("Unknown reset version %d\n", desc->version);
-		return;
+		return -EINVAL;
 	}
 
 	regmap = device_node_to_regmap(np);
 	if (IS_ERR(regmap)) {
 		pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap);
-		return;
+		return -EINVAL;
 	}
 
 	data = kzalloc(sizeof(*data), GFP_KERNEL);
 	if (!data)
-		return;
+		return -ENOMEM;
 
 	data->desc = desc;
 	data->regmap = regmap;
@@ -143,7 +143,10 @@ void mtk_register_reset_controller(struct device_node *np,
 	if (ret) {
 		pr_err("could not register reset controller: %d\n", ret);
 		kfree(data);
+		return ret;
 	}
+
+	return 0;
 }
 
 MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index db558ea4a474..c3a2f2a4f486 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -27,7 +27,7 @@ struct mtk_clk_rst_data {
 	const struct mtk_clk_rst_desc *desc;
 };
 
-void mtk_register_reset_controller(struct device_node *np,
-				   const struct mtk_clk_rst_desc *desc);
+int mtk_register_reset_controller(struct device_node *np,
+				  const struct mtk_clk_rst_desc *desc);
 
 #endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 08/17] clk: mediatek: reset: Add new register reset function with device
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

It's a proper implementation using device to register reset controller.
Howerver, some clock drviers of MediaTeks only provide device_node.
Therefore, we still remain register reset function with device_node and
add a function with device to register reset controller.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mt2701-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt2701-g3d.c |  2 +-
 drivers/clk/mediatek/clk-mt2701-hif.c |  2 +-
 drivers/clk/mediatek/clk-mt2701.c     |  4 +-
 drivers/clk/mediatek/clk-mt2712.c     |  4 +-
 drivers/clk/mediatek/clk-mt7622-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt7622-hif.c |  4 +-
 drivers/clk/mediatek/clk-mt7622.c     |  4 +-
 drivers/clk/mediatek/clk-mt7629-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt7629-hif.c |  4 +-
 drivers/clk/mediatek/clk-mt8183.c     |  2 +-
 drivers/clk/mediatek/reset.c          | 53 +++++++++++++++++++++++++++
 drivers/clk/mediatek/reset.h          |  2 +
 13 files changed, 71 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
index b651f3878267..90d662d955a9 100644
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -64,7 +64,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
index 7696870f6f23..fc6563e29da7 100644
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -58,7 +58,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 57fa63c47452..13acc15de2e3 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -63,7 +63,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 496afc7483ae..76662d1810ab 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -800,7 +800,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, &clk_rst_desc[0]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -923,7 +923,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, &clk_rst_desc[1]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index 04ff9b1327d2..664d56d665fe 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1376,7 +1376,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc[0]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
 	return r;
 }
@@ -1398,7 +1398,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc[1]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
index 3bf7f4610ad1..88462698c2af 100644
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -88,7 +88,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
index 88fe9b447158..bb23a88a7810 100644
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -99,7 +99,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
@@ -121,7 +121,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 3f937723b211..8f2003dd1e75 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -678,7 +678,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, &clk_rst_desc[0]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -729,7 +729,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 
 	clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
 
-	mtk_register_reset_controller(node, &clk_rst_desc[1]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c
index 079b8facf63f..32f035822a9a 100644
--- a/drivers/clk/mediatek/clk-mt7629-eth.c
+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -98,7 +98,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c
index 69a2ecf8d3df..e4a5b66ac005 100644
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -94,7 +94,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
@@ -116,7 +116,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index c957249d4cdf..b8884e94604d 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -1245,7 +1245,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 03d865f3308e..fe917b2eeab4 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -149,4 +149,57 @@ int mtk_register_reset_controller(struct device_node *np,
 	return 0;
 }
 
+int mtk_register_reset_controller_with_dev(struct device *dev,
+					   const struct mtk_clk_rst_desc *desc)
+{
+	struct device_node *np = dev->of_node;
+	struct regmap *regmap;
+	const struct reset_control_ops *rcops = NULL;
+	struct mtk_clk_rst_data *data;
+	int ret;
+
+	if (!desc) {
+		dev_err(dev, "mtk clock reset desc is NULL\n");
+		return -EINVAL;
+	}
+
+	switch (desc->version) {
+	case MTK_RST_SIMPLE:
+		rcops = &mtk_reset_ops;
+		break;
+	case MTK_RST_SET_CLR:
+		rcops = &mtk_reset_ops_set_clr;
+		break;
+	default:
+		dev_err(dev, "Unknown reset version %d\n", desc->version);
+		return -EINVAL;
+	}
+
+	regmap = device_node_to_regmap(np);
+	if (IS_ERR(regmap)) {
+		dev_err(dev, "Cannot find regmap %pe\n", regmap);
+		return -EINVAL;
+	}
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->desc = desc;
+	data->regmap = regmap;
+	data->rcdev.owner = THIS_MODULE;
+	data->rcdev.nr_resets = desc->rst_set_nr * 32;
+	data->rcdev.ops = rcops;
+	data->rcdev.of_node = np;
+	data->rcdev.dev = dev;
+
+	ret = devm_reset_controller_register(dev, &data->rcdev);
+	if (ret) {
+		dev_err(dev, "could not register reset controller: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
 MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index c3a2f2a4f486..79efbea37c9b 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -29,5 +29,7 @@ struct mtk_clk_rst_data {
 
 int mtk_register_reset_controller(struct device_node *np,
 				  const struct mtk_clk_rst_desc *desc);
+int mtk_register_reset_controller_with_dev(struct device *dev,
+					   const struct mtk_clk_rst_desc *desc);
 
 #endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 08/17] clk: mediatek: reset: Add new register reset function with device
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

It's a proper implementation using device to register reset controller.
Howerver, some clock drviers of MediaTeks only provide device_node.
Therefore, we still remain register reset function with device_node and
add a function with device to register reset controller.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mt2701-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt2701-g3d.c |  2 +-
 drivers/clk/mediatek/clk-mt2701-hif.c |  2 +-
 drivers/clk/mediatek/clk-mt2701.c     |  4 +-
 drivers/clk/mediatek/clk-mt2712.c     |  4 +-
 drivers/clk/mediatek/clk-mt7622-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt7622-hif.c |  4 +-
 drivers/clk/mediatek/clk-mt7622.c     |  4 +-
 drivers/clk/mediatek/clk-mt7629-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt7629-hif.c |  4 +-
 drivers/clk/mediatek/clk-mt8183.c     |  2 +-
 drivers/clk/mediatek/reset.c          | 53 +++++++++++++++++++++++++++
 drivers/clk/mediatek/reset.h          |  2 +
 13 files changed, 71 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
index b651f3878267..90d662d955a9 100644
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -64,7 +64,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
index 7696870f6f23..fc6563e29da7 100644
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -58,7 +58,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 57fa63c47452..13acc15de2e3 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -63,7 +63,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 496afc7483ae..76662d1810ab 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -800,7 +800,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, &clk_rst_desc[0]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -923,7 +923,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, &clk_rst_desc[1]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index 04ff9b1327d2..664d56d665fe 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1376,7 +1376,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc[0]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
 	return r;
 }
@@ -1398,7 +1398,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc[1]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
index 3bf7f4610ad1..88462698c2af 100644
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -88,7 +88,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
index 88fe9b447158..bb23a88a7810 100644
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -99,7 +99,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
@@ -121,7 +121,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 3f937723b211..8f2003dd1e75 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -678,7 +678,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, &clk_rst_desc[0]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -729,7 +729,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 
 	clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
 
-	mtk_register_reset_controller(node, &clk_rst_desc[1]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c
index 079b8facf63f..32f035822a9a 100644
--- a/drivers/clk/mediatek/clk-mt7629-eth.c
+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -98,7 +98,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c
index 69a2ecf8d3df..e4a5b66ac005 100644
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -94,7 +94,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
@@ -116,7 +116,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index c957249d4cdf..b8884e94604d 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -1245,7 +1245,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 03d865f3308e..fe917b2eeab4 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -149,4 +149,57 @@ int mtk_register_reset_controller(struct device_node *np,
 	return 0;
 }
 
+int mtk_register_reset_controller_with_dev(struct device *dev,
+					   const struct mtk_clk_rst_desc *desc)
+{
+	struct device_node *np = dev->of_node;
+	struct regmap *regmap;
+	const struct reset_control_ops *rcops = NULL;
+	struct mtk_clk_rst_data *data;
+	int ret;
+
+	if (!desc) {
+		dev_err(dev, "mtk clock reset desc is NULL\n");
+		return -EINVAL;
+	}
+
+	switch (desc->version) {
+	case MTK_RST_SIMPLE:
+		rcops = &mtk_reset_ops;
+		break;
+	case MTK_RST_SET_CLR:
+		rcops = &mtk_reset_ops_set_clr;
+		break;
+	default:
+		dev_err(dev, "Unknown reset version %d\n", desc->version);
+		return -EINVAL;
+	}
+
+	regmap = device_node_to_regmap(np);
+	if (IS_ERR(regmap)) {
+		dev_err(dev, "Cannot find regmap %pe\n", regmap);
+		return -EINVAL;
+	}
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->desc = desc;
+	data->regmap = regmap;
+	data->rcdev.owner = THIS_MODULE;
+	data->rcdev.nr_resets = desc->rst_set_nr * 32;
+	data->rcdev.ops = rcops;
+	data->rcdev.of_node = np;
+	data->rcdev.dev = dev;
+
+	ret = devm_reset_controller_register(dev, &data->rcdev);
+	if (ret) {
+		dev_err(dev, "could not register reset controller: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
 MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index c3a2f2a4f486..79efbea37c9b 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -29,5 +29,7 @@ struct mtk_clk_rst_data {
 
 int mtk_register_reset_controller(struct device_node *np,
 				  const struct mtk_clk_rst_desc *desc);
+int mtk_register_reset_controller_with_dev(struct device *dev,
+					   const struct mtk_clk_rst_desc *desc);
 
 #endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 08/17] clk: mediatek: reset: Add new register reset function with device
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

It's a proper implementation using device to register reset controller.
Howerver, some clock drviers of MediaTeks only provide device_node.
Therefore, we still remain register reset function with device_node and
add a function with device to register reset controller.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mt2701-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt2701-g3d.c |  2 +-
 drivers/clk/mediatek/clk-mt2701-hif.c |  2 +-
 drivers/clk/mediatek/clk-mt2701.c     |  4 +-
 drivers/clk/mediatek/clk-mt2712.c     |  4 +-
 drivers/clk/mediatek/clk-mt7622-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt7622-hif.c |  4 +-
 drivers/clk/mediatek/clk-mt7622.c     |  4 +-
 drivers/clk/mediatek/clk-mt7629-eth.c |  2 +-
 drivers/clk/mediatek/clk-mt7629-hif.c |  4 +-
 drivers/clk/mediatek/clk-mt8183.c     |  2 +-
 drivers/clk/mediatek/reset.c          | 53 +++++++++++++++++++++++++++
 drivers/clk/mediatek/reset.h          |  2 +
 13 files changed, 71 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
index b651f3878267..90d662d955a9 100644
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -64,7 +64,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
index 7696870f6f23..fc6563e29da7 100644
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -58,7 +58,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 57fa63c47452..13acc15de2e3 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -63,7 +63,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 496afc7483ae..76662d1810ab 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -800,7 +800,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, &clk_rst_desc[0]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -923,7 +923,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, &clk_rst_desc[1]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index 04ff9b1327d2..664d56d665fe 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1376,7 +1376,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc[0]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
 	return r;
 }
@@ -1398,7 +1398,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc[1]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
index 3bf7f4610ad1..88462698c2af 100644
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -88,7 +88,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
index 88fe9b447158..bb23a88a7810 100644
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -99,7 +99,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
@@ -121,7 +121,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 3f937723b211..8f2003dd1e75 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -678,7 +678,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, &clk_rst_desc[0]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -729,7 +729,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 
 	clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
 
-	mtk_register_reset_controller(node, &clk_rst_desc[1]);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c
index 079b8facf63f..32f035822a9a 100644
--- a/drivers/clk/mediatek/clk-mt7629-eth.c
+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -98,7 +98,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c
index 69a2ecf8d3df..e4a5b66ac005 100644
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -94,7 +94,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
@@ -116,7 +116,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index c957249d4cdf..b8884e94604d 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -1245,7 +1245,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, &clk_rst_desc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 03d865f3308e..fe917b2eeab4 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -149,4 +149,57 @@ int mtk_register_reset_controller(struct device_node *np,
 	return 0;
 }
 
+int mtk_register_reset_controller_with_dev(struct device *dev,
+					   const struct mtk_clk_rst_desc *desc)
+{
+	struct device_node *np = dev->of_node;
+	struct regmap *regmap;
+	const struct reset_control_ops *rcops = NULL;
+	struct mtk_clk_rst_data *data;
+	int ret;
+
+	if (!desc) {
+		dev_err(dev, "mtk clock reset desc is NULL\n");
+		return -EINVAL;
+	}
+
+	switch (desc->version) {
+	case MTK_RST_SIMPLE:
+		rcops = &mtk_reset_ops;
+		break;
+	case MTK_RST_SET_CLR:
+		rcops = &mtk_reset_ops_set_clr;
+		break;
+	default:
+		dev_err(dev, "Unknown reset version %d\n", desc->version);
+		return -EINVAL;
+	}
+
+	regmap = device_node_to_regmap(np);
+	if (IS_ERR(regmap)) {
+		dev_err(dev, "Cannot find regmap %pe\n", regmap);
+		return -EINVAL;
+	}
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->desc = desc;
+	data->regmap = regmap;
+	data->rcdev.owner = THIS_MODULE;
+	data->rcdev.nr_resets = desc->rst_set_nr * 32;
+	data->rcdev.ops = rcops;
+	data->rcdev.of_node = np;
+	data->rcdev.dev = dev;
+
+	ret = devm_reset_controller_register(dev, &data->rcdev);
+	if (ret) {
+		dev_err(dev, "could not register reset controller: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
 MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index c3a2f2a4f486..79efbea37c9b 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -29,5 +29,7 @@ struct mtk_clk_rst_data {
 
 int mtk_register_reset_controller(struct device_node *np,
 				  const struct mtk_clk_rst_desc *desc);
+int mtk_register_reset_controller_with_dev(struct device *dev,
+					   const struct mtk_clk_rst_desc *desc);
 
 #endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 09/17] clk: mediatek: reset: Add support for input offset and bit from DT
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To use the clock reset function easier, we implement the of_xlate.
The calculation of return value is different from each reset version.

There is no impact for original use. If the argument number is not
larger than 1, it will return original id.

With this implementation if we want to set offset 0x120 and bit 16,
we can just write "resets = <&infra_rst 0x120 16>;" in the module node.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 31 +++++++++++++++++++++++++++++++
 drivers/clk/mediatek/reset.h |  1 +
 2 files changed, 32 insertions(+)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index fe917b2eeab4..2a2f3dede77f 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -97,6 +97,33 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 	.reset = mtk_reset_set_clr,
 };
 
+static int reset_xlate(struct reset_controller_dev *rcdev,
+		       const struct of_phandle_args *reset_spec)
+{
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
+	unsigned int offset, bit, shift;
+
+	if (reset_spec->args_count <= 1)
+		return reset_spec->args[0];
+
+	switch (data->desc->version) {
+	case MTK_RST_SIMPLE:
+		shift = 2;
+		break;
+	case MTK_RST_SET_CLR:
+		shift = 4;
+		break;
+	default:
+		pr_err("Unknown reset version %d\n", data->desc->version);
+		return -EINVAL;
+	}
+
+	offset = reset_spec->args[0];
+	bit = reset_spec->args[1];
+
+	return (offset >> shift) * 32 + bit;
+}
+
 int mtk_register_reset_controller(struct device_node *np,
 				  const struct mtk_clk_rst_desc *desc)
 {
@@ -138,6 +165,8 @@ int mtk_register_reset_controller(struct device_node *np,
 	data->rcdev.nr_resets = desc->rst_set_nr * 32;
 	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
+	data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 1);
+	data->rcdev.of_xlate = reset_xlate;
 
 	ret = reset_controller_register(&data->rcdev);
 	if (ret) {
@@ -192,6 +221,8 @@ int mtk_register_reset_controller_with_dev(struct device *dev,
 	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
 	data->rcdev.dev = dev;
+	data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 1);
+	data->rcdev.of_xlate = reset_xlate;
 
 	ret = devm_reset_controller_register(dev, &data->rcdev);
 	if (ret) {
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 79efbea37c9b..6838a644eaef 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -19,6 +19,7 @@ struct mtk_clk_rst_desc {
 	u8 version;
 	u32 rst_set_nr;
 	u16 reg_ofs;
+	int reset_n_cells;
 };
 
 struct mtk_clk_rst_data {
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 09/17] clk: mediatek: reset: Add support for input offset and bit from DT
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To use the clock reset function easier, we implement the of_xlate.
The calculation of return value is different from each reset version.

There is no impact for original use. If the argument number is not
larger than 1, it will return original id.

With this implementation if we want to set offset 0x120 and bit 16,
we can just write "resets = <&infra_rst 0x120 16>;" in the module node.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 31 +++++++++++++++++++++++++++++++
 drivers/clk/mediatek/reset.h |  1 +
 2 files changed, 32 insertions(+)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index fe917b2eeab4..2a2f3dede77f 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -97,6 +97,33 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 	.reset = mtk_reset_set_clr,
 };
 
+static int reset_xlate(struct reset_controller_dev *rcdev,
+		       const struct of_phandle_args *reset_spec)
+{
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
+	unsigned int offset, bit, shift;
+
+	if (reset_spec->args_count <= 1)
+		return reset_spec->args[0];
+
+	switch (data->desc->version) {
+	case MTK_RST_SIMPLE:
+		shift = 2;
+		break;
+	case MTK_RST_SET_CLR:
+		shift = 4;
+		break;
+	default:
+		pr_err("Unknown reset version %d\n", data->desc->version);
+		return -EINVAL;
+	}
+
+	offset = reset_spec->args[0];
+	bit = reset_spec->args[1];
+
+	return (offset >> shift) * 32 + bit;
+}
+
 int mtk_register_reset_controller(struct device_node *np,
 				  const struct mtk_clk_rst_desc *desc)
 {
@@ -138,6 +165,8 @@ int mtk_register_reset_controller(struct device_node *np,
 	data->rcdev.nr_resets = desc->rst_set_nr * 32;
 	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
+	data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 1);
+	data->rcdev.of_xlate = reset_xlate;
 
 	ret = reset_controller_register(&data->rcdev);
 	if (ret) {
@@ -192,6 +221,8 @@ int mtk_register_reset_controller_with_dev(struct device *dev,
 	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
 	data->rcdev.dev = dev;
+	data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 1);
+	data->rcdev.of_xlate = reset_xlate;
 
 	ret = devm_reset_controller_register(dev, &data->rcdev);
 	if (ret) {
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 79efbea37c9b..6838a644eaef 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -19,6 +19,7 @@ struct mtk_clk_rst_desc {
 	u8 version;
 	u32 rst_set_nr;
 	u16 reg_ofs;
+	int reset_n_cells;
 };
 
 struct mtk_clk_rst_data {
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 09/17] clk: mediatek: reset: Add support for input offset and bit from DT
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To use the clock reset function easier, we implement the of_xlate.
The calculation of return value is different from each reset version.

There is no impact for original use. If the argument number is not
larger than 1, it will return original id.

With this implementation if we want to set offset 0x120 and bit 16,
we can just write "resets = <&infra_rst 0x120 16>;" in the module node.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 31 +++++++++++++++++++++++++++++++
 drivers/clk/mediatek/reset.h |  1 +
 2 files changed, 32 insertions(+)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index fe917b2eeab4..2a2f3dede77f 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -97,6 +97,33 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 	.reset = mtk_reset_set_clr,
 };
 
+static int reset_xlate(struct reset_controller_dev *rcdev,
+		       const struct of_phandle_args *reset_spec)
+{
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
+	unsigned int offset, bit, shift;
+
+	if (reset_spec->args_count <= 1)
+		return reset_spec->args[0];
+
+	switch (data->desc->version) {
+	case MTK_RST_SIMPLE:
+		shift = 2;
+		break;
+	case MTK_RST_SET_CLR:
+		shift = 4;
+		break;
+	default:
+		pr_err("Unknown reset version %d\n", data->desc->version);
+		return -EINVAL;
+	}
+
+	offset = reset_spec->args[0];
+	bit = reset_spec->args[1];
+
+	return (offset >> shift) * 32 + bit;
+}
+
 int mtk_register_reset_controller(struct device_node *np,
 				  const struct mtk_clk_rst_desc *desc)
 {
@@ -138,6 +165,8 @@ int mtk_register_reset_controller(struct device_node *np,
 	data->rcdev.nr_resets = desc->rst_set_nr * 32;
 	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
+	data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 1);
+	data->rcdev.of_xlate = reset_xlate;
 
 	ret = reset_controller_register(&data->rcdev);
 	if (ret) {
@@ -192,6 +221,8 @@ int mtk_register_reset_controller_with_dev(struct device *dev,
 	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
 	data->rcdev.dev = dev;
+	data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 1);
+	data->rcdev.of_xlate = reset_xlate;
 
 	ret = devm_reset_controller_register(dev, &data->rcdev);
 	if (ret) {
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 79efbea37c9b..6838a644eaef 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -19,6 +19,7 @@ struct mtk_clk_rst_desc {
 	u8 version;
 	u32 rst_set_nr;
 	u16 reg_ofs;
+	int reset_n_cells;
 };
 
 struct mtk_clk_rst_data {
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 10/17] clk: mediatek: reset: Add reset support for simple probe
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

- Add a pointer of "mtk_clk_rst_desc" to "mtk_clk_desc".
- Add the function of registering reset with device in
  mtk_clk_simple_probe().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mtk.c | 7 +++++++
 drivers/clk/mediatek/clk-mtk.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index b4063261cf56..2c72e5839d50 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -453,6 +453,13 @@ int mtk_clk_simple_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, clk_data);
 
+	if (mcd->rst_desc) {
+		r = mtk_register_reset_controller_with_dev(&pdev->dev,
+							   mcd->rst_desc);
+		if (r)
+			goto unregister_clks;
+	}
+
 	return r;
 
 unregister_clks:
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index a6d0f24c62fa..2c7800bcb1a2 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -195,6 +195,7 @@ struct clk *mtk_clk_register_ref2usb_tx(const char *name,
 struct mtk_clk_desc {
 	const struct mtk_gate *clks;
 	size_t num_clks;
+	const struct mtk_clk_rst_desc *rst_desc;
 };
 
 int mtk_clk_simple_probe(struct platform_device *pdev);
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 10/17] clk: mediatek: reset: Add reset support for simple probe
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

- Add a pointer of "mtk_clk_rst_desc" to "mtk_clk_desc".
- Add the function of registering reset with device in
  mtk_clk_simple_probe().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mtk.c | 7 +++++++
 drivers/clk/mediatek/clk-mtk.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index b4063261cf56..2c72e5839d50 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -453,6 +453,13 @@ int mtk_clk_simple_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, clk_data);
 
+	if (mcd->rst_desc) {
+		r = mtk_register_reset_controller_with_dev(&pdev->dev,
+							   mcd->rst_desc);
+		if (r)
+			goto unregister_clks;
+	}
+
 	return r;
 
 unregister_clks:
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index a6d0f24c62fa..2c7800bcb1a2 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -195,6 +195,7 @@ struct clk *mtk_clk_register_ref2usb_tx(const char *name,
 struct mtk_clk_desc {
 	const struct mtk_gate *clks;
 	size_t num_clks;
+	const struct mtk_clk_rst_desc *rst_desc;
 };
 
 int mtk_clk_simple_probe(struct platform_device *pdev);
-- 
2.18.0


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 10/17] clk: mediatek: reset: Add reset support for simple probe
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

- Add a pointer of "mtk_clk_rst_desc" to "mtk_clk_desc".
- Add the function of registering reset with device in
  mtk_clk_simple_probe().

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mtk.c | 7 +++++++
 drivers/clk/mediatek/clk-mtk.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index b4063261cf56..2c72e5839d50 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -453,6 +453,13 @@ int mtk_clk_simple_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, clk_data);
 
+	if (mcd->rst_desc) {
+		r = mtk_register_reset_controller_with_dev(&pdev->dev,
+							   mcd->rst_desc);
+		if (r)
+			goto unregister_clks;
+	}
+
 	return r;
 
 unregister_clks:
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index a6d0f24c62fa..2c7800bcb1a2 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -195,6 +195,7 @@ struct clk *mtk_clk_register_ref2usb_tx(const char *name,
 struct mtk_clk_desc {
 	const struct mtk_gate *clks;
 	size_t num_clks;
+	const struct mtk_clk_rst_desc *rst_desc;
 };
 
 int mtk_clk_simple_probe(struct platform_device *pdev);
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

We will use the infra_ao reset which is defined in mt8192-sys-clock.
The maximum value of reset-cells is 2. Therefore, we add this patch to
define it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml       | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
index 5705bcf1fe47..28ebcecc8258 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
@@ -29,6 +29,9 @@ properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    maximum: 2
+
 required:
   - compatible
   - reg
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

We will use the infra_ao reset which is defined in mt8192-sys-clock.
The maximum value of reset-cells is 2. Therefore, we add this patch to
define it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml       | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
index 5705bcf1fe47..28ebcecc8258 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
@@ -29,6 +29,9 @@ properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    maximum: 2
+
 required:
   - compatible
   - reg
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

We will use the infra_ao reset which is defined in mt8192-sys-clock.
The maximum value of reset-cells is 2. Therefore, we add this patch to
define it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml       | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
index 5705bcf1fe47..28ebcecc8258 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
@@ -29,6 +29,9 @@ properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    maximum: 2
+
 required:
   - compatible
   - reg
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To support reset of infra_ao, add the bit definition for thermal/PCIe/SVS.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
index be9a7ca245b9..d5f3433175c1 100644
--- a/include/dt-bindings/reset/mt8192-resets.h
+++ b/include/dt-bindings/reset/mt8192-resets.h
@@ -27,4 +27,14 @@
 
 #define MT8192_TOPRGU_SW_RST_NUM				23
 
+/* INFRA RST0 */
+#define MT8192_INFRA_RST0_LVTS_AP_RST				0
+/* INFRA RST2 */
+#define MT8192_INFRA_RST2_PCIE_PHY_RST				15
+/* INFRA RST3 */
+#define MT8192_INFRA_RST3_PTP_RST				5
+/* INFRA RST4 */
+#define MT8192_INFRA_RST4_LVTS_MCU				12
+#define MT8192_INFRA_RST4_PCIE_TOP				1
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To support reset of infra_ao, add the bit definition for thermal/PCIe/SVS.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
index be9a7ca245b9..d5f3433175c1 100644
--- a/include/dt-bindings/reset/mt8192-resets.h
+++ b/include/dt-bindings/reset/mt8192-resets.h
@@ -27,4 +27,14 @@
 
 #define MT8192_TOPRGU_SW_RST_NUM				23
 
+/* INFRA RST0 */
+#define MT8192_INFRA_RST0_LVTS_AP_RST				0
+/* INFRA RST2 */
+#define MT8192_INFRA_RST2_PCIE_PHY_RST				15
+/* INFRA RST3 */
+#define MT8192_INFRA_RST3_PTP_RST				5
+/* INFRA RST4 */
+#define MT8192_INFRA_RST4_LVTS_MCU				12
+#define MT8192_INFRA_RST4_PCIE_TOP				1
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
-- 
2.18.0


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To support reset of infra_ao, add the bit definition for thermal/PCIe/SVS.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
index be9a7ca245b9..d5f3433175c1 100644
--- a/include/dt-bindings/reset/mt8192-resets.h
+++ b/include/dt-bindings/reset/mt8192-resets.h
@@ -27,4 +27,14 @@
 
 #define MT8192_TOPRGU_SW_RST_NUM				23
 
+/* INFRA RST0 */
+#define MT8192_INFRA_RST0_LVTS_AP_RST				0
+/* INFRA RST2 */
+#define MT8192_INFRA_RST2_PCIE_PHY_RST				15
+/* INFRA RST3 */
+#define MT8192_INFRA_RST3_PTP_RST				5
+/* INFRA RST4 */
+#define MT8192_INFRA_RST4_LVTS_MCU				12
+#define MT8192_INFRA_RST4_PCIE_TOP				1
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
-- 
2.18.0


_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 13/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8195-sys-clock
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

We will use the infra_ao reset which is defined in mt8195-sys-clock.
The maximum value of reset-cells is 2. Therefore, we add this patch to
define it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml       | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
index 57a1503d95fe..66b7852ce711 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
@@ -37,6 +37,9 @@ properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    maximum: 2
+
 required:
   - compatible
   - reg
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 13/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8195-sys-clock
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

We will use the infra_ao reset which is defined in mt8195-sys-clock.
The maximum value of reset-cells is 2. Therefore, we add this patch to
define it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml       | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
index 57a1503d95fe..66b7852ce711 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
@@ -37,6 +37,9 @@ properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    maximum: 2
+
 required:
   - compatible
   - reg
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 13/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8195-sys-clock
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

We will use the infra_ao reset which is defined in mt8195-sys-clock.
The maximum value of reset-cells is 2. Therefore, we add this patch to
define it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml       | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
index 57a1503d95fe..66b7852ce711 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
@@ -37,6 +37,9 @@ properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    maximum: 2
+
 required:
   - compatible
   - reg
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 14/17] dt-binding: mt8195: Add infra_ao reset bit
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To support reset of infra_ao, add the bit definition for thermal/SVS.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 include/dt-bindings/reset/mt8195-resets.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..2479680616fb 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,11 @@
 
 #define MT8195_TOPRGU_SW_RST_NUM               16
 
+/* INFRA RST0 */
+#define MT8195_INFRA_RST0_THERMAL_AP_RST       0
+/* INFRA RST3 */
+#define MT8195_INFRA_RST3_PTP_RST              5
+/* INFRA RST4 */
+#define MT8195_INFRA_RST4_THERMAL_MCU_RST      10
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 14/17] dt-binding: mt8195: Add infra_ao reset bit
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To support reset of infra_ao, add the bit definition for thermal/SVS.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 include/dt-bindings/reset/mt8195-resets.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..2479680616fb 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,11 @@
 
 #define MT8195_TOPRGU_SW_RST_NUM               16
 
+/* INFRA RST0 */
+#define MT8195_INFRA_RST0_THERMAL_AP_RST       0
+/* INFRA RST3 */
+#define MT8195_INFRA_RST3_PTP_RST              5
+/* INFRA RST4 */
+#define MT8195_INFRA_RST4_THERMAL_MCU_RST      10
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
-- 
2.18.0


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^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 14/17] dt-binding: mt8195: Add infra_ao reset bit
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To support reset of infra_ao, add the bit definition for thermal/SVS.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 include/dt-bindings/reset/mt8195-resets.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..2479680616fb 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,11 @@
 
 #define MT8195_TOPRGU_SW_RST_NUM               16
 
+/* INFRA RST0 */
+#define MT8195_INFRA_RST0_THERMAL_AP_RST       0
+/* INFRA RST3 */
+#define MT8195_INFRA_RST3_PTP_RST              5
+/* INFRA RST4 */
+#define MT8195_INFRA_RST4_THERMAL_MCU_RST      10
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
-- 
2.18.0


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http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 15/17] clk: mediatek: reset: Add infra_ao reset support for MT8192
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

The infra_ao reset is needed for MT8192. Therefore, we add this patch
to support it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mt8192.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index ab27cd66b866..92dc6a4affe3 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -1114,6 +1114,13 @@ static const struct mtk_gate top_clks[] = {
 	GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_set_nr = 4,
+	.reg_ofs = 0x0,
+	.reset_n_cells = 2,
+};
+
 #define MT8192_PLL_FMAX		(3800UL * MHZ)
 #define MT8192_PLL_FMIN		(1500UL * MHZ)
 #define MT8192_INTEGER_BITS	8
@@ -1239,6 +1246,10 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev)
 	if (r)
 		goto free_clk_data;
 
+	r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+	if (r)
+		goto free_clk_data;
+
 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 	if (r)
 		goto free_clk_data;
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 15/17] clk: mediatek: reset: Add infra_ao reset support for MT8192
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

The infra_ao reset is needed for MT8192. Therefore, we add this patch
to support it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mt8192.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index ab27cd66b866..92dc6a4affe3 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -1114,6 +1114,13 @@ static const struct mtk_gate top_clks[] = {
 	GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_set_nr = 4,
+	.reg_ofs = 0x0,
+	.reset_n_cells = 2,
+};
+
 #define MT8192_PLL_FMAX		(3800UL * MHZ)
 #define MT8192_PLL_FMIN		(1500UL * MHZ)
 #define MT8192_INTEGER_BITS	8
@@ -1239,6 +1246,10 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev)
 	if (r)
 		goto free_clk_data;
 
+	r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+	if (r)
+		goto free_clk_data;
+
 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 	if (r)
 		goto free_clk_data;
-- 
2.18.0


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^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 15/17] clk: mediatek: reset: Add infra_ao reset support for MT8192
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

The infra_ao reset is needed for MT8192. Therefore, we add this patch
to support it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mt8192.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index ab27cd66b866..92dc6a4affe3 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -1114,6 +1114,13 @@ static const struct mtk_gate top_clks[] = {
 	GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25),
 };
 
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_set_nr = 4,
+	.reg_ofs = 0x0,
+	.reset_n_cells = 2,
+};
+
 #define MT8192_PLL_FMAX		(3800UL * MHZ)
 #define MT8192_PLL_FMIN		(1500UL * MHZ)
 #define MT8192_INTEGER_BITS	8
@@ -1239,6 +1246,10 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev)
 	if (r)
 		goto free_clk_data;
 
+	r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+	if (r)
+		goto free_clk_data;
+
 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 	if (r)
 		goto free_clk_data;
-- 
2.18.0


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http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 16/17] clk: mediatek: reset: Add infra_ao reset support for MT8195
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

The infra_ao reset is needed for MT8195. Therefore, we add this patch
to support it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mt8195-infra_ao.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
index 8ebe3b9415c4..0dc9f18c762c 100644
--- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c
+++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
@@ -182,9 +182,17 @@ static const struct mtk_gate infra_ao_clks[] = {
 	GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),
 };
 
+static struct mtk_clk_rst_desc infra_ao_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_set_nr = 4,
+	.reg_ofs = 0x0,
+	.reset_n_cells = 2,
+};
+
 static const struct mtk_clk_desc infra_ao_desc = {
 	.clks = infra_ao_clks,
 	.num_clks = ARRAY_SIZE(infra_ao_clks),
+	.rst_desc = &infra_ao_rst_desc,
 };
 
 static const struct of_device_id of_match_clk_mt8195_infra_ao[] = {
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 16/17] clk: mediatek: reset: Add infra_ao reset support for MT8195
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

The infra_ao reset is needed for MT8195. Therefore, we add this patch
to support it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mt8195-infra_ao.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
index 8ebe3b9415c4..0dc9f18c762c 100644
--- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c
+++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
@@ -182,9 +182,17 @@ static const struct mtk_gate infra_ao_clks[] = {
 	GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),
 };
 
+static struct mtk_clk_rst_desc infra_ao_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_set_nr = 4,
+	.reg_ofs = 0x0,
+	.reset_n_cells = 2,
+};
+
 static const struct mtk_clk_desc infra_ao_desc = {
 	.clks = infra_ao_clks,
 	.num_clks = ARRAY_SIZE(infra_ao_clks),
+	.rst_desc = &infra_ao_rst_desc,
 };
 
 static const struct of_device_id of_match_clk_mt8195_infra_ao[] = {
-- 
2.18.0


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^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 16/17] clk: mediatek: reset: Add infra_ao reset support for MT8195
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

The infra_ao reset is needed for MT8195. Therefore, we add this patch
to support it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mt8195-infra_ao.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
index 8ebe3b9415c4..0dc9f18c762c 100644
--- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c
+++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
@@ -182,9 +182,17 @@ static const struct mtk_gate infra_ao_clks[] = {
 	GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),
 };
 
+static struct mtk_clk_rst_desc infra_ao_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_set_nr = 4,
+	.reg_ofs = 0x0,
+	.reset_n_cells = 2,
+};
+
 static const struct mtk_clk_desc infra_ao_desc = {
 	.clks = infra_ao_clks,
 	.num_clks = ARRAY_SIZE(infra_ao_clks),
+	.rst_desc = &infra_ao_rst_desc,
 };
 
 static const struct of_device_id of_match_clk_mt8195_infra_ao[] = {
-- 
2.18.0


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^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 17/17] arm64: dts: mediatek: Add infra #reset-cells property for MT8192
  2022-04-22  6:01 ` Rex-BC Chen
  (?)
@ 2022-04-22  6:01   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To support reset of infra, we add property of #reset-cells.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 411feb294613..66ff18344ac2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -269,6 +269,7 @@
 			compatible = "mediatek,mt8192-infracfg", "syscon";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <2>;
 		};
 
 		pericfg: syscon@10003000 {
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 17/17] arm64: dts: mediatek: Add infra #reset-cells property for MT8192
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To support reset of infra, we add property of #reset-cells.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 411feb294613..66ff18344ac2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -269,6 +269,7 @@
 			compatible = "mediatek,mt8192-infracfg", "syscon";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <2>;
 		};
 
 		pericfg: syscon@10003000 {
-- 
2.18.0


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^ permalink raw reply related	[flat|nested] 117+ messages in thread

* [PATCH V3 17/17] arm64: dts: mediatek: Add infra #reset-cells property for MT8192
@ 2022-04-22  6:01   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-22  6:01 UTC (permalink / raw)
  To: mturquette, sboyd, matthias.bgg, robh+dt, krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group, Rex-BC Chen

To support reset of infra, we add property of #reset-cells.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 411feb294613..66ff18344ac2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -269,6 +269,7 @@
 			compatible = "mediatek,mt8192-infracfg", "syscon";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <2>;
 		};
 
 		pericfg: syscon@10003000 {
-- 
2.18.0


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^ permalink raw reply related	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
  2022-04-22  6:01   ` Rex-BC Chen
  (?)
@ 2022-04-23 10:27     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-23 10:27 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

On 22/04/2022 08:01, Rex-BC Chen wrote:
> We will use the infra_ao reset which is defined in mt8192-sys-clock.
> The maximum value of reset-cells is 2. Therefore, we add this patch to
> define it.

Remove entire last sentence, does not make sense in the commit.

> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>  .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml       | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
> index 5705bcf1fe47..28ebcecc8258 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
> @@ -29,6 +29,9 @@ properties:
>    '#clock-cells':
>      const: 1
>  
> +  '#reset-cells':
> +    maximum: 2

Why this is a maximum? Usually this is const, so how do you use it (with
what values)?

> +
>  required:
>    - compatible
>    - reg


Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
@ 2022-04-23 10:27     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-23 10:27 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

On 22/04/2022 08:01, Rex-BC Chen wrote:
> We will use the infra_ao reset which is defined in mt8192-sys-clock.
> The maximum value of reset-cells is 2. Therefore, we add this patch to
> define it.

Remove entire last sentence, does not make sense in the commit.

> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>  .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml       | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
> index 5705bcf1fe47..28ebcecc8258 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
> @@ -29,6 +29,9 @@ properties:
>    '#clock-cells':
>      const: 1
>  
> +  '#reset-cells':
> +    maximum: 2

Why this is a maximum? Usually this is const, so how do you use it (with
what values)?

> +
>  required:
>    - compatible
>    - reg


Best regards,
Krzysztof

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
@ 2022-04-23 10:27     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-23 10:27 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

On 22/04/2022 08:01, Rex-BC Chen wrote:
> We will use the infra_ao reset which is defined in mt8192-sys-clock.
> The maximum value of reset-cells is 2. Therefore, we add this patch to
> define it.

Remove entire last sentence, does not make sense in the commit.

> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>  .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml       | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
> index 5705bcf1fe47..28ebcecc8258 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
> @@ -29,6 +29,9 @@ properties:
>    '#clock-cells':
>      const: 1
>  
> +  '#reset-cells':
> +    maximum: 2

Why this is a maximum? Usually this is const, so how do you use it (with
what values)?

> +
>  required:
>    - compatible
>    - reg


Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
  2022-04-22  6:01   ` Rex-BC Chen
  (?)
@ 2022-04-23 10:28     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-23 10:28 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

On 22/04/2022 08:01, Rex-BC Chen wrote:
> To support reset of infra_ao, add the bit definition for thermal/PCIe/SVS.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
> index be9a7ca245b9..d5f3433175c1 100644
> --- a/include/dt-bindings/reset/mt8192-resets.h
> +++ b/include/dt-bindings/reset/mt8192-resets.h
> @@ -27,4 +27,14 @@
>  
>  #define MT8192_TOPRGU_SW_RST_NUM				23
>  
> +/* INFRA RST0 */
> +#define MT8192_INFRA_RST0_LVTS_AP_RST				0
> +/* INFRA RST2 */
> +#define MT8192_INFRA_RST2_PCIE_PHY_RST				15
> +/* INFRA RST3 */
> +#define MT8192_INFRA_RST3_PTP_RST				5
> +/* INFRA RST4 */
> +#define MT8192_INFRA_RST4_LVTS_MCU				12
> +#define MT8192_INFRA_RST4_PCIE_TOP				1

These should be the IDs of reset, not some register values/offsets.
Therefore it is expected to have them incremented by 1.


> +
>  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */


Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-23 10:28     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-23 10:28 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

On 22/04/2022 08:01, Rex-BC Chen wrote:
> To support reset of infra_ao, add the bit definition for thermal/PCIe/SVS.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
> index be9a7ca245b9..d5f3433175c1 100644
> --- a/include/dt-bindings/reset/mt8192-resets.h
> +++ b/include/dt-bindings/reset/mt8192-resets.h
> @@ -27,4 +27,14 @@
>  
>  #define MT8192_TOPRGU_SW_RST_NUM				23
>  
> +/* INFRA RST0 */
> +#define MT8192_INFRA_RST0_LVTS_AP_RST				0
> +/* INFRA RST2 */
> +#define MT8192_INFRA_RST2_PCIE_PHY_RST				15
> +/* INFRA RST3 */
> +#define MT8192_INFRA_RST3_PTP_RST				5
> +/* INFRA RST4 */
> +#define MT8192_INFRA_RST4_LVTS_MCU				12
> +#define MT8192_INFRA_RST4_PCIE_TOP				1

These should be the IDs of reset, not some register values/offsets.
Therefore it is expected to have them incremented by 1.


> +
>  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */


Best regards,
Krzysztof

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-23 10:28     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-23 10:28 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

On 22/04/2022 08:01, Rex-BC Chen wrote:
> To support reset of infra_ao, add the bit definition for thermal/PCIe/SVS.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
> index be9a7ca245b9..d5f3433175c1 100644
> --- a/include/dt-bindings/reset/mt8192-resets.h
> +++ b/include/dt-bindings/reset/mt8192-resets.h
> @@ -27,4 +27,14 @@
>  
>  #define MT8192_TOPRGU_SW_RST_NUM				23
>  
> +/* INFRA RST0 */
> +#define MT8192_INFRA_RST0_LVTS_AP_RST				0
> +/* INFRA RST2 */
> +#define MT8192_INFRA_RST2_PCIE_PHY_RST				15
> +/* INFRA RST3 */
> +#define MT8192_INFRA_RST3_PTP_RST				5
> +/* INFRA RST4 */
> +#define MT8192_INFRA_RST4_LVTS_MCU				12
> +#define MT8192_INFRA_RST4_PCIE_TOP				1

These should be the IDs of reset, not some register values/offsets.
Therefore it is expected to have them incremented by 1.


> +
>  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */


Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 13/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8195-sys-clock
  2022-04-22  6:01   ` Rex-BC Chen
  (?)
@ 2022-04-23 10:28     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-23 10:28 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

On 22/04/2022 08:01, Rex-BC Chen wrote:
> We will use the infra_ao reset which is defined in mt8195-sys-clock.
> The maximum value of reset-cells is 2. Therefore, we add this patch to
> define it.

Same comments as your other reset patch.

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 13/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8195-sys-clock
@ 2022-04-23 10:28     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-23 10:28 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

On 22/04/2022 08:01, Rex-BC Chen wrote:
> We will use the infra_ao reset which is defined in mt8195-sys-clock.
> The maximum value of reset-cells is 2. Therefore, we add this patch to
> define it.

Same comments as your other reset patch.

Best regards,
Krzysztof

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 13/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8195-sys-clock
@ 2022-04-23 10:28     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-23 10:28 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

On 22/04/2022 08:01, Rex-BC Chen wrote:
> We will use the infra_ao reset which is defined in mt8195-sys-clock.
> The maximum value of reset-cells is 2. Therefore, we add this patch to
> define it.

Same comments as your other reset patch.

Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 14/17] dt-binding: mt8195: Add infra_ao reset bit
  2022-04-22  6:01   ` Rex-BC Chen
  (?)
@ 2022-04-23 10:29     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-23 10:29 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

On 22/04/2022 08:01, Rex-BC Chen wrote:
> To support reset of infra_ao, add the bit definition for thermal/SVS.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>  include/dt-bindings/reset/mt8195-resets.h | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> index a26bccc8b957..2479680616fb 100644
> --- a/include/dt-bindings/reset/mt8195-resets.h
> +++ b/include/dt-bindings/reset/mt8195-resets.h
> @@ -26,4 +26,11 @@
>  
>  #define MT8195_TOPRGU_SW_RST_NUM               16
>  
> +/* INFRA RST0 */
> +#define MT8195_INFRA_RST0_THERMAL_AP_RST       0
> +/* INFRA RST3 */
> +#define MT8195_INFRA_RST3_PTP_RST              5
> +/* INFRA RST4 */
> +#define MT8195_INFRA_RST4_THERMAL_MCU_RST      10

Same comments as for other reset.


Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 14/17] dt-binding: mt8195: Add infra_ao reset bit
@ 2022-04-23 10:29     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-23 10:29 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

On 22/04/2022 08:01, Rex-BC Chen wrote:
> To support reset of infra_ao, add the bit definition for thermal/SVS.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>  include/dt-bindings/reset/mt8195-resets.h | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> index a26bccc8b957..2479680616fb 100644
> --- a/include/dt-bindings/reset/mt8195-resets.h
> +++ b/include/dt-bindings/reset/mt8195-resets.h
> @@ -26,4 +26,11 @@
>  
>  #define MT8195_TOPRGU_SW_RST_NUM               16
>  
> +/* INFRA RST0 */
> +#define MT8195_INFRA_RST0_THERMAL_AP_RST       0
> +/* INFRA RST3 */
> +#define MT8195_INFRA_RST3_PTP_RST              5
> +/* INFRA RST4 */
> +#define MT8195_INFRA_RST4_THERMAL_MCU_RST      10

Same comments as for other reset.


Best regards,
Krzysztof

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 14/17] dt-binding: mt8195: Add infra_ao reset bit
@ 2022-04-23 10:29     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-23 10:29 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno, chun-jie.chen, wenst,
	runyang.chen, linux-kernel, devicetree, linux-clk,
	linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

On 22/04/2022 08:01, Rex-BC Chen wrote:
> To support reset of infra_ao, add the bit definition for thermal/SVS.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>  include/dt-bindings/reset/mt8195-resets.h | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> index a26bccc8b957..2479680616fb 100644
> --- a/include/dt-bindings/reset/mt8195-resets.h
> +++ b/include/dt-bindings/reset/mt8195-resets.h
> @@ -26,4 +26,11 @@
>  
>  #define MT8195_TOPRGU_SW_RST_NUM               16
>  
> +/* INFRA RST0 */
> +#define MT8195_INFRA_RST0_THERMAL_AP_RST       0
> +/* INFRA RST3 */
> +#define MT8195_INFRA_RST3_PTP_RST              5
> +/* INFRA RST4 */
> +#define MT8195_INFRA_RST4_THERMAL_MCU_RST      10

Same comments as for other reset.


Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
  2022-04-23 10:27     ` Krzysztof Kozlowski
  (?)
@ 2022-04-25  2:37       ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-25  2:37 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Sat, 2022-04-23 at 18:27 +0800, Krzysztof Kozlowski wrote:
> On 22/04/2022 08:01, Rex-BC Chen wrote:
> > We will use the infra_ao reset which is defined in mt8192-sys-
> > clock.
> > The maximum value of reset-cells is 2. Therefore, we add this patch
> > to
> > define it.
> 
> Remove entire last sentence, does not make sense in the commit.
> 

Hello Krzysztof,

Thanks for your review.
I will drop "Therefore, we add this patch to define it." and add more
detailed messages in next version.

> > 
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > ---
> >  .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml       | 3
> > +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > index 5705bcf1fe47..28ebcecc8258 100644
> > ---
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > +++
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > @@ -29,6 +29,9 @@ properties:
> >    '#clock-cells':
> >      const: 1
> >  
> > +  '#reset-cells':
> > +    maximum: 2
> 
> Why this is a maximum? Usually this is const, so how do you use it
> (with
> what values)?
> 
We need to let the driver compatible with previous setting in
drivers/clk/mediatek/reset.c

There are two use cases in our reset driver:
(Refer to [1])

1. #reset-cells = <1>
   When we input the argument, the older driver
use is to calculate  
   bank and bit by different method. From the implementation of
   reset_xlate(), we can see if the argument number is 1, it will
   return directly.

2. #reset-cells = <2>
   The input arguments is offset and bit. When we input two arguments,
   we can use reset_xlate() to calculate the corresponding id to assert
   and deassert.

[1]:
https://lore.kernel.org/all/20220422060152.13534-10-rex-bc.chen@mediatek.com/

If it's acceptable, I will add this in commit message.

BRs,
Rex
> > +
> >  required:
> >    - compatible
> >    - reg
> 
> 
> Best regards,
> Krzysztof


^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
@ 2022-04-25  2:37       ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-25  2:37 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Sat, 2022-04-23 at 18:27 +0800, Krzysztof Kozlowski wrote:
> On 22/04/2022 08:01, Rex-BC Chen wrote:
> > We will use the infra_ao reset which is defined in mt8192-sys-
> > clock.
> > The maximum value of reset-cells is 2. Therefore, we add this patch
> > to
> > define it.
> 
> Remove entire last sentence, does not make sense in the commit.
> 

Hello Krzysztof,

Thanks for your review.
I will drop "Therefore, we add this patch to define it." and add more
detailed messages in next version.

> > 
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > ---
> >  .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml       | 3
> > +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > index 5705bcf1fe47..28ebcecc8258 100644
> > ---
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > +++
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > @@ -29,6 +29,9 @@ properties:
> >    '#clock-cells':
> >      const: 1
> >  
> > +  '#reset-cells':
> > +    maximum: 2
> 
> Why this is a maximum? Usually this is const, so how do you use it
> (with
> what values)?
> 
We need to let the driver compatible with previous setting in
drivers/clk/mediatek/reset.c

There are two use cases in our reset driver:
(Refer to [1])

1. #reset-cells = <1>
   When we input the argument, the older driver
use is to calculate  
   bank and bit by different method. From the implementation of
   reset_xlate(), we can see if the argument number is 1, it will
   return directly.

2. #reset-cells = <2>
   The input arguments is offset and bit. When we input two arguments,
   we can use reset_xlate() to calculate the corresponding id to assert
   and deassert.

[1]:
https://lore.kernel.org/all/20220422060152.13534-10-rex-bc.chen@mediatek.com/

If it's acceptable, I will add this in commit message.

BRs,
Rex
> > +
> >  required:
> >    - compatible
> >    - reg
> 
> 
> Best regards,
> Krzysztof


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
@ 2022-04-25  2:37       ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-25  2:37 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Sat, 2022-04-23 at 18:27 +0800, Krzysztof Kozlowski wrote:
> On 22/04/2022 08:01, Rex-BC Chen wrote:
> > We will use the infra_ao reset which is defined in mt8192-sys-
> > clock.
> > The maximum value of reset-cells is 2. Therefore, we add this patch
> > to
> > define it.
> 
> Remove entire last sentence, does not make sense in the commit.
> 

Hello Krzysztof,

Thanks for your review.
I will drop "Therefore, we add this patch to define it." and add more
detailed messages in next version.

> > 
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > ---
> >  .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml       | 3
> > +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > index 5705bcf1fe47..28ebcecc8258 100644
> > ---
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > +++
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > @@ -29,6 +29,9 @@ properties:
> >    '#clock-cells':
> >      const: 1
> >  
> > +  '#reset-cells':
> > +    maximum: 2
> 
> Why this is a maximum? Usually this is const, so how do you use it
> (with
> what values)?
> 
We need to let the driver compatible with previous setting in
drivers/clk/mediatek/reset.c

There are two use cases in our reset driver:
(Refer to [1])

1. #reset-cells = <1>
   When we input the argument, the older driver
use is to calculate  
   bank and bit by different method. From the implementation of
   reset_xlate(), we can see if the argument number is 1, it will
   return directly.

2. #reset-cells = <2>
   The input arguments is offset and bit. When we input two arguments,
   we can use reset_xlate() to calculate the corresponding id to assert
   and deassert.

[1]:
https://lore.kernel.org/all/20220422060152.13534-10-rex-bc.chen@mediatek.com/

If it's acceptable, I will add this in commit message.

BRs,
Rex
> > +
> >  required:
> >    - compatible
> >    - reg
> 
> 
> Best regards,
> Krzysztof


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
  2022-04-23 10:28     ` Krzysztof Kozlowski
  (?)
@ 2022-04-25  5:01       ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-25  5:01 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
> On 22/04/2022 08:01, Rex-BC Chen wrote:
> > To support reset of infra_ao, add the bit definition for
> > thermal/PCIe/SVS.
> > 
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > ---
> >  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/include/dt-bindings/reset/mt8192-resets.h
> > b/include/dt-bindings/reset/mt8192-resets.h
> > index be9a7ca245b9..d5f3433175c1 100644
> > --- a/include/dt-bindings/reset/mt8192-resets.h
> > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > @@ -27,4 +27,14 @@
> >  
> >  #define MT8192_TOPRGU_SW_RST_NUM				23
> >  
> > +/* INFRA RST0 */
> > +#define MT8192_INFRA_RST0_LVTS_AP_RST				
> > 0
> > +/* INFRA RST2 */
> > +#define MT8192_INFRA_RST2_PCIE_PHY_RST				
> > 15
> > +/* INFRA RST3 */
> > +#define MT8192_INFRA_RST3_PTP_RST				5
> > +/* INFRA RST4 */
> > +#define MT8192_INFRA_RST4_LVTS_MCU				12
> > +#define MT8192_INFRA_RST4_PCIE_TOP				1
> 
> These should be the IDs of reset, not some register values/offsets.
> Therefore it is expected to have them incremented by 1.
> 
> 

Hello Krzysztof,

This is define bit.

There is serveral reset set for infra_ao while it's not serial.
For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
We are implement #reset-cells = <2>, and we can use this reset drive
more easier.

For example, in dts, we can define
infra_ao: syscon {
	compatible = "mediatek,mt8192-infracfg", "syscon";
 	reg = <0 0x10001000 0 0x1000>;
 	#clock-cells = <1>;
	#reset-cells = <2>;
};

thermal {
	...
	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
	...
};

If it's acceptabel, I can update all bit difinition from 0 to 15 for
all reset set.

BRs,
Rex
> > +
> >  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
> 
> 
> Best regards,
> Krzysztof


^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-25  5:01       ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-25  5:01 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
> On 22/04/2022 08:01, Rex-BC Chen wrote:
> > To support reset of infra_ao, add the bit definition for
> > thermal/PCIe/SVS.
> > 
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > ---
> >  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/include/dt-bindings/reset/mt8192-resets.h
> > b/include/dt-bindings/reset/mt8192-resets.h
> > index be9a7ca245b9..d5f3433175c1 100644
> > --- a/include/dt-bindings/reset/mt8192-resets.h
> > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > @@ -27,4 +27,14 @@
> >  
> >  #define MT8192_TOPRGU_SW_RST_NUM				23
> >  
> > +/* INFRA RST0 */
> > +#define MT8192_INFRA_RST0_LVTS_AP_RST				
> > 0
> > +/* INFRA RST2 */
> > +#define MT8192_INFRA_RST2_PCIE_PHY_RST				
> > 15
> > +/* INFRA RST3 */
> > +#define MT8192_INFRA_RST3_PTP_RST				5
> > +/* INFRA RST4 */
> > +#define MT8192_INFRA_RST4_LVTS_MCU				12
> > +#define MT8192_INFRA_RST4_PCIE_TOP				1
> 
> These should be the IDs of reset, not some register values/offsets.
> Therefore it is expected to have them incremented by 1.
> 
> 

Hello Krzysztof,

This is define bit.

There is serveral reset set for infra_ao while it's not serial.
For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
We are implement #reset-cells = <2>, and we can use this reset drive
more easier.

For example, in dts, we can define
infra_ao: syscon {
	compatible = "mediatek,mt8192-infracfg", "syscon";
 	reg = <0 0x10001000 0 0x1000>;
 	#clock-cells = <1>;
	#reset-cells = <2>;
};

thermal {
	...
	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
	...
};

If it's acceptabel, I can update all bit difinition from 0 to 15 for
all reset set.

BRs,
Rex
> > +
> >  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
> 
> 
> Best regards,
> Krzysztof


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-25  5:01       ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-25  5:01 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
> On 22/04/2022 08:01, Rex-BC Chen wrote:
> > To support reset of infra_ao, add the bit definition for
> > thermal/PCIe/SVS.
> > 
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > ---
> >  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/include/dt-bindings/reset/mt8192-resets.h
> > b/include/dt-bindings/reset/mt8192-resets.h
> > index be9a7ca245b9..d5f3433175c1 100644
> > --- a/include/dt-bindings/reset/mt8192-resets.h
> > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > @@ -27,4 +27,14 @@
> >  
> >  #define MT8192_TOPRGU_SW_RST_NUM				23
> >  
> > +/* INFRA RST0 */
> > +#define MT8192_INFRA_RST0_LVTS_AP_RST				
> > 0
> > +/* INFRA RST2 */
> > +#define MT8192_INFRA_RST2_PCIE_PHY_RST				
> > 15
> > +/* INFRA RST3 */
> > +#define MT8192_INFRA_RST3_PTP_RST				5
> > +/* INFRA RST4 */
> > +#define MT8192_INFRA_RST4_LVTS_MCU				12
> > +#define MT8192_INFRA_RST4_PCIE_TOP				1
> 
> These should be the IDs of reset, not some register values/offsets.
> Therefore it is expected to have them incremented by 1.
> 
> 

Hello Krzysztof,

This is define bit.

There is serveral reset set for infra_ao while it's not serial.
For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
We are implement #reset-cells = <2>, and we can use this reset drive
more easier.

For example, in dts, we can define
infra_ao: syscon {
	compatible = "mediatek,mt8192-infracfg", "syscon";
 	reg = <0 0x10001000 0 0x1000>;
 	#clock-cells = <1>;
	#reset-cells = <2>;
};

thermal {
	...
	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
	...
};

If it's acceptabel, I can update all bit difinition from 0 to 15 for
all reset set.

BRs,
Rex
> > +
> >  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
> 
> 
> Best regards,
> Krzysztof


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
  2022-04-25  2:37       ` Rex-BC Chen
  (?)
@ 2022-04-25  7:44         ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-25  7:44 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On 25/04/2022 04:37, Rex-BC Chen wrote:
>>> +  '#reset-cells':
>>> +    maximum: 2
>>
>> Why this is a maximum? Usually this is const, so how do you use it
>> (with
>> what values)?
>>
> We need to let the driver compatible with previous setting in
> drivers/clk/mediatek/reset.c

Then it should be enum [1, 2], because '0' is not valid.

> There are two use cases in our reset driver:
> (Refer to [1])
> 
> 1. #reset-cells = <1>
>    When we input the argument, the older driver
> use is to calculate  
>    bank and bit by different method. From the implementation of
>    reset_xlate(), we can see if the argument number is 1, it will
>    return directly.

I understand this is an old binding with older compatibles, so this
should be restricted per each variant (allOf:if:then)... but wait, old
binding did not allow any reset-cells! You add an entirely new binding
property and already want to support some older (deprecated?) way.

> 
> 2. #reset-cells = <2>
>    The input arguments is offset and bit. When we input two arguments,
>    we can use reset_xlate() to calculate the corresponding id to assert
>    and deassert.
> 
> [1]:
> https://lore.kernel.org/all/20220422060152.13534-10-rex-bc.chen@mediatek.com/
> 
> If it's acceptable, I will add this in commit message.


Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
@ 2022-04-25  7:44         ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-25  7:44 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On 25/04/2022 04:37, Rex-BC Chen wrote:
>>> +  '#reset-cells':
>>> +    maximum: 2
>>
>> Why this is a maximum? Usually this is const, so how do you use it
>> (with
>> what values)?
>>
> We need to let the driver compatible with previous setting in
> drivers/clk/mediatek/reset.c

Then it should be enum [1, 2], because '0' is not valid.

> There are two use cases in our reset driver:
> (Refer to [1])
> 
> 1. #reset-cells = <1>
>    When we input the argument, the older driver
> use is to calculate  
>    bank and bit by different method. From the implementation of
>    reset_xlate(), we can see if the argument number is 1, it will
>    return directly.

I understand this is an old binding with older compatibles, so this
should be restricted per each variant (allOf:if:then)... but wait, old
binding did not allow any reset-cells! You add an entirely new binding
property and already want to support some older (deprecated?) way.

> 
> 2. #reset-cells = <2>
>    The input arguments is offset and bit. When we input two arguments,
>    we can use reset_xlate() to calculate the corresponding id to assert
>    and deassert.
> 
> [1]:
> https://lore.kernel.org/all/20220422060152.13534-10-rex-bc.chen@mediatek.com/
> 
> If it's acceptable, I will add this in commit message.


Best regards,
Krzysztof

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
@ 2022-04-25  7:44         ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-25  7:44 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On 25/04/2022 04:37, Rex-BC Chen wrote:
>>> +  '#reset-cells':
>>> +    maximum: 2
>>
>> Why this is a maximum? Usually this is const, so how do you use it
>> (with
>> what values)?
>>
> We need to let the driver compatible with previous setting in
> drivers/clk/mediatek/reset.c

Then it should be enum [1, 2], because '0' is not valid.

> There are two use cases in our reset driver:
> (Refer to [1])
> 
> 1. #reset-cells = <1>
>    When we input the argument, the older driver
> use is to calculate  
>    bank and bit by different method. From the implementation of
>    reset_xlate(), we can see if the argument number is 1, it will
>    return directly.

I understand this is an old binding with older compatibles, so this
should be restricted per each variant (allOf:if:then)... but wait, old
binding did not allow any reset-cells! You add an entirely new binding
property and already want to support some older (deprecated?) way.

> 
> 2. #reset-cells = <2>
>    The input arguments is offset and bit. When we input two arguments,
>    we can use reset_xlate() to calculate the corresponding id to assert
>    and deassert.
> 
> [1]:
> https://lore.kernel.org/all/20220422060152.13534-10-rex-bc.chen@mediatek.com/
> 
> If it's acceptable, I will add this in commit message.


Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
  2022-04-25  5:01       ` Rex-BC Chen
  (?)
@ 2022-04-25  7:52         ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-25  7:52 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On 25/04/2022 07:01, Rex-BC Chen wrote:
> On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
>> On 22/04/2022 08:01, Rex-BC Chen wrote:
>>> To support reset of infra_ao, add the bit definition for
>>> thermal/PCIe/SVS.
>>>
>>> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>>> ---
>>>  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
>>>  1 file changed, 10 insertions(+)
>>>
>>> diff --git a/include/dt-bindings/reset/mt8192-resets.h
>>> b/include/dt-bindings/reset/mt8192-resets.h
>>> index be9a7ca245b9..d5f3433175c1 100644
>>> --- a/include/dt-bindings/reset/mt8192-resets.h
>>> +++ b/include/dt-bindings/reset/mt8192-resets.h
>>> @@ -27,4 +27,14 @@
>>>  
>>>  #define MT8192_TOPRGU_SW_RST_NUM				23
>>>  
>>> +/* INFRA RST0 */
>>> +#define MT8192_INFRA_RST0_LVTS_AP_RST				
>>> 0
>>> +/* INFRA RST2 */
>>> +#define MT8192_INFRA_RST2_PCIE_PHY_RST				
>>> 15
>>> +/* INFRA RST3 */
>>> +#define MT8192_INFRA_RST3_PTP_RST				5
>>> +/* INFRA RST4 */
>>> +#define MT8192_INFRA_RST4_LVTS_MCU				12
>>> +#define MT8192_INFRA_RST4_PCIE_TOP				1
>>
>> These should be the IDs of reset, not some register values/offsets.
>> Therefore it is expected to have them incremented by 1.
>>
>>
> 
> Hello Krzysztof,
> 
> This is define bit.
> 
> There is serveral reset set for infra_ao while it's not serial.
> For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
> We are implement #reset-cells = <2>, and we can use this reset drive
> more easier.
> 
> For example, in dts, we can define
> infra_ao: syscon {
> 	compatible = "mediatek,mt8192-infracfg", "syscon";
>  	reg = <0 0x10001000 0 0x1000>;
>  	#clock-cells = <1>;
> 	#reset-cells = <2>;
> };
> 
> thermal {
> 	...
> 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
> 	...
> };
> 
> If it's acceptabel, I can update all bit difinition from 0 to 15 for
> all reset set.

Bits are not acceptable, because you embed specific device programming
model (register bits) into the binding.

These should be IDs, so decimal numbers incremented from 0, so:
#define MT8192_INFRA_RST0_LVTS_AP_RST				0
#define MT8192_INFRA_RST4_LVTS_MCU				1
#define MT8192_INFRA_RST4_PCIE_TOP				2

And what is 0x730 in your example? It does not look like ID of a reset...

Entire changeset look wrong from DT point of view.

Best regards,
Krzysztof

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-25  7:52         ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-25  7:52 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On 25/04/2022 07:01, Rex-BC Chen wrote:
> On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
>> On 22/04/2022 08:01, Rex-BC Chen wrote:
>>> To support reset of infra_ao, add the bit definition for
>>> thermal/PCIe/SVS.
>>>
>>> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>>> ---
>>>  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
>>>  1 file changed, 10 insertions(+)
>>>
>>> diff --git a/include/dt-bindings/reset/mt8192-resets.h
>>> b/include/dt-bindings/reset/mt8192-resets.h
>>> index be9a7ca245b9..d5f3433175c1 100644
>>> --- a/include/dt-bindings/reset/mt8192-resets.h
>>> +++ b/include/dt-bindings/reset/mt8192-resets.h
>>> @@ -27,4 +27,14 @@
>>>  
>>>  #define MT8192_TOPRGU_SW_RST_NUM				23
>>>  
>>> +/* INFRA RST0 */
>>> +#define MT8192_INFRA_RST0_LVTS_AP_RST				
>>> 0
>>> +/* INFRA RST2 */
>>> +#define MT8192_INFRA_RST2_PCIE_PHY_RST				
>>> 15
>>> +/* INFRA RST3 */
>>> +#define MT8192_INFRA_RST3_PTP_RST				5
>>> +/* INFRA RST4 */
>>> +#define MT8192_INFRA_RST4_LVTS_MCU				12
>>> +#define MT8192_INFRA_RST4_PCIE_TOP				1
>>
>> These should be the IDs of reset, not some register values/offsets.
>> Therefore it is expected to have them incremented by 1.
>>
>>
> 
> Hello Krzysztof,
> 
> This is define bit.
> 
> There is serveral reset set for infra_ao while it's not serial.
> For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
> We are implement #reset-cells = <2>, and we can use this reset drive
> more easier.
> 
> For example, in dts, we can define
> infra_ao: syscon {
> 	compatible = "mediatek,mt8192-infracfg", "syscon";
>  	reg = <0 0x10001000 0 0x1000>;
>  	#clock-cells = <1>;
> 	#reset-cells = <2>;
> };
> 
> thermal {
> 	...
> 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
> 	...
> };
> 
> If it's acceptabel, I can update all bit difinition from 0 to 15 for
> all reset set.

Bits are not acceptable, because you embed specific device programming
model (register bits) into the binding.

These should be IDs, so decimal numbers incremented from 0, so:
#define MT8192_INFRA_RST0_LVTS_AP_RST				0
#define MT8192_INFRA_RST4_LVTS_MCU				1
#define MT8192_INFRA_RST4_PCIE_TOP				2

And what is 0x730 in your example? It does not look like ID of a reset...

Entire changeset look wrong from DT point of view.

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-25  7:52         ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-25  7:52 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On 25/04/2022 07:01, Rex-BC Chen wrote:
> On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
>> On 22/04/2022 08:01, Rex-BC Chen wrote:
>>> To support reset of infra_ao, add the bit definition for
>>> thermal/PCIe/SVS.
>>>
>>> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>>> ---
>>>  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
>>>  1 file changed, 10 insertions(+)
>>>
>>> diff --git a/include/dt-bindings/reset/mt8192-resets.h
>>> b/include/dt-bindings/reset/mt8192-resets.h
>>> index be9a7ca245b9..d5f3433175c1 100644
>>> --- a/include/dt-bindings/reset/mt8192-resets.h
>>> +++ b/include/dt-bindings/reset/mt8192-resets.h
>>> @@ -27,4 +27,14 @@
>>>  
>>>  #define MT8192_TOPRGU_SW_RST_NUM				23
>>>  
>>> +/* INFRA RST0 */
>>> +#define MT8192_INFRA_RST0_LVTS_AP_RST				
>>> 0
>>> +/* INFRA RST2 */
>>> +#define MT8192_INFRA_RST2_PCIE_PHY_RST				
>>> 15
>>> +/* INFRA RST3 */
>>> +#define MT8192_INFRA_RST3_PTP_RST				5
>>> +/* INFRA RST4 */
>>> +#define MT8192_INFRA_RST4_LVTS_MCU				12
>>> +#define MT8192_INFRA_RST4_PCIE_TOP				1
>>
>> These should be the IDs of reset, not some register values/offsets.
>> Therefore it is expected to have them incremented by 1.
>>
>>
> 
> Hello Krzysztof,
> 
> This is define bit.
> 
> There is serveral reset set for infra_ao while it's not serial.
> For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
> We are implement #reset-cells = <2>, and we can use this reset drive
> more easier.
> 
> For example, in dts, we can define
> infra_ao: syscon {
> 	compatible = "mediatek,mt8192-infracfg", "syscon";
>  	reg = <0 0x10001000 0 0x1000>;
>  	#clock-cells = <1>;
> 	#reset-cells = <2>;
> };
> 
> thermal {
> 	...
> 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
> 	...
> };
> 
> If it's acceptabel, I can update all bit difinition from 0 to 15 for
> all reset set.

Bits are not acceptable, because you embed specific device programming
model (register bits) into the binding.

These should be IDs, so decimal numbers incremented from 0, so:
#define MT8192_INFRA_RST0_LVTS_AP_RST				0
#define MT8192_INFRA_RST4_LVTS_MCU				1
#define MT8192_INFRA_RST4_PCIE_TOP				2

And what is 0x730 in your example? It does not look like ID of a reset...

Entire changeset look wrong from DT point of view.

Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
  2022-04-25  7:52         ` Krzysztof Kozlowski
  (?)
@ 2022-04-26  8:23           ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-26  8:23 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
> On 25/04/2022 07:01, Rex-BC Chen wrote:
> > On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
> > > On 22/04/2022 08:01, Rex-BC Chen wrote:
> > > > To support reset of infra_ao, add the bit definition for
> > > > thermal/PCIe/SVS.
> > > > 
> > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > > > ---
> > > >  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
> > > >  1 file changed, 10 insertions(+)
> > > > 
> > > > diff --git a/include/dt-bindings/reset/mt8192-resets.h
> > > > b/include/dt-bindings/reset/mt8192-resets.h
> > > > index be9a7ca245b9..d5f3433175c1 100644
> > > > --- a/include/dt-bindings/reset/mt8192-resets.h
> > > > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > > > @@ -27,4 +27,14 @@
> > > >  
> > > >  #define MT8192_TOPRGU_SW_RST_NUM				
> > > > 23
> > > >  
> > > > +/* INFRA RST0 */
> > > > +#define MT8192_INFRA_RST0_LVTS_AP_RST				
> > > > 0
> > > > +/* INFRA RST2 */
> > > > +#define MT8192_INFRA_RST2_PCIE_PHY_RST				
> > > > 15
> > > > +/* INFRA RST3 */
> > > > +#define MT8192_INFRA_RST3_PTP_RST				
> > > > 5
> > > > +/* INFRA RST4 */
> > > > +#define MT8192_INFRA_RST4_LVTS_MCU				
> > > > 12
> > > > +#define MT8192_INFRA_RST4_PCIE_TOP				
> > > > 1
> > > 
> > > These should be the IDs of reset, not some register
> > > values/offsets.
> > > Therefore it is expected to have them incremented by 1.
> > > 
> > > 
> > 
> > Hello Krzysztof,
> > 
> > This is define bit.
> > 
> > There is serveral reset set for infra_ao while it's not serial.
> > For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
> > We are implement #reset-cells = <2>, and we can use this reset
> > drive
> > more easier.
> > 
> > For example, in dts, we can define
> > infra_ao: syscon {
> > 	compatible = "mediatek,mt8192-infracfg", "syscon";
> >  	reg = <0 0x10001000 0 0x1000>;
> >  	#clock-cells = <1>;
> > 	#reset-cells = <2>;
> > };
> > 
> > thermal {
> > 	...
> > 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
> > 	...
> > };
> > 
> > If it's acceptabel, I can update all bit difinition from 0 to 15
> > for
> > all reset set.
> 
> Bits are not acceptable, because you embed specific device
> programming
> model (register bits) into the binding.
> 
> These should be IDs, so decimal numbers incremented from 0, so:
> #define MT8192_INFRA_RST0_LVTS_AP_RST				0
> #define MT8192_INFRA_RST4_LVTS_MCU				1
> #define MT8192_INFRA_RST4_PCIE_TOP				2
> 
> And what is 0x730 in your example? It does not look like ID of a
> reset...
> 
> Entire changeset look wrong from DT point of view.
> 
> Best regards,
> Krzysztof

Hello Krzysztof,

Got it. I will modify them to reset index.
And the dts in my next version would somthing like this:

----
#define MT8192_INFRA_THERMAL_CTRL_RST			0
#define MT8192_INFRA_PEXTP_PHY_RST			79
#define MT8192_INFRA_PTP_RST				101
#define MT8192_INFRA_RST4_PCIE_TOP			129
#define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140
----

infra_ao: syscon {
	compatible = "mediatek,mt8192-infracfg", "syscon";
	reg = <0 0x10001000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
};

thermal {
	...
	resets = <&infra_ao MT8192_INFRA_THERMAL_CTRL_MCU_RST>;
	...
};

BRs,
Rex


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-26  8:23           ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-26  8:23 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
> On 25/04/2022 07:01, Rex-BC Chen wrote:
> > On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
> > > On 22/04/2022 08:01, Rex-BC Chen wrote:
> > > > To support reset of infra_ao, add the bit definition for
> > > > thermal/PCIe/SVS.
> > > > 
> > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > > > ---
> > > >  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
> > > >  1 file changed, 10 insertions(+)
> > > > 
> > > > diff --git a/include/dt-bindings/reset/mt8192-resets.h
> > > > b/include/dt-bindings/reset/mt8192-resets.h
> > > > index be9a7ca245b9..d5f3433175c1 100644
> > > > --- a/include/dt-bindings/reset/mt8192-resets.h
> > > > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > > > @@ -27,4 +27,14 @@
> > > >  
> > > >  #define MT8192_TOPRGU_SW_RST_NUM				
> > > > 23
> > > >  
> > > > +/* INFRA RST0 */
> > > > +#define MT8192_INFRA_RST0_LVTS_AP_RST				
> > > > 0
> > > > +/* INFRA RST2 */
> > > > +#define MT8192_INFRA_RST2_PCIE_PHY_RST				
> > > > 15
> > > > +/* INFRA RST3 */
> > > > +#define MT8192_INFRA_RST3_PTP_RST				
> > > > 5
> > > > +/* INFRA RST4 */
> > > > +#define MT8192_INFRA_RST4_LVTS_MCU				
> > > > 12
> > > > +#define MT8192_INFRA_RST4_PCIE_TOP				
> > > > 1
> > > 
> > > These should be the IDs of reset, not some register
> > > values/offsets.
> > > Therefore it is expected to have them incremented by 1.
> > > 
> > > 
> > 
> > Hello Krzysztof,
> > 
> > This is define bit.
> > 
> > There is serveral reset set for infra_ao while it's not serial.
> > For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
> > We are implement #reset-cells = <2>, and we can use this reset
> > drive
> > more easier.
> > 
> > For example, in dts, we can define
> > infra_ao: syscon {
> > 	compatible = "mediatek,mt8192-infracfg", "syscon";
> >  	reg = <0 0x10001000 0 0x1000>;
> >  	#clock-cells = <1>;
> > 	#reset-cells = <2>;
> > };
> > 
> > thermal {
> > 	...
> > 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
> > 	...
> > };
> > 
> > If it's acceptabel, I can update all bit difinition from 0 to 15
> > for
> > all reset set.
> 
> Bits are not acceptable, because you embed specific device
> programming
> model (register bits) into the binding.
> 
> These should be IDs, so decimal numbers incremented from 0, so:
> #define MT8192_INFRA_RST0_LVTS_AP_RST				0
> #define MT8192_INFRA_RST4_LVTS_MCU				1
> #define MT8192_INFRA_RST4_PCIE_TOP				2
> 
> And what is 0x730 in your example? It does not look like ID of a
> reset...
> 
> Entire changeset look wrong from DT point of view.
> 
> Best regards,
> Krzysztof

Hello Krzysztof,

Got it. I will modify them to reset index.
And the dts in my next version would somthing like this:

----
#define MT8192_INFRA_THERMAL_CTRL_RST			0
#define MT8192_INFRA_PEXTP_PHY_RST			79
#define MT8192_INFRA_PTP_RST				101
#define MT8192_INFRA_RST4_PCIE_TOP			129
#define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140
----

infra_ao: syscon {
	compatible = "mediatek,mt8192-infracfg", "syscon";
	reg = <0 0x10001000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
};

thermal {
	...
	resets = <&infra_ao MT8192_INFRA_THERMAL_CTRL_MCU_RST>;
	...
};

BRs,
Rex


^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-26  8:23           ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-26  8:23 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
> On 25/04/2022 07:01, Rex-BC Chen wrote:
> > On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
> > > On 22/04/2022 08:01, Rex-BC Chen wrote:
> > > > To support reset of infra_ao, add the bit definition for
> > > > thermal/PCIe/SVS.
> > > > 
> > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > > > ---
> > > >  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
> > > >  1 file changed, 10 insertions(+)
> > > > 
> > > > diff --git a/include/dt-bindings/reset/mt8192-resets.h
> > > > b/include/dt-bindings/reset/mt8192-resets.h
> > > > index be9a7ca245b9..d5f3433175c1 100644
> > > > --- a/include/dt-bindings/reset/mt8192-resets.h
> > > > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > > > @@ -27,4 +27,14 @@
> > > >  
> > > >  #define MT8192_TOPRGU_SW_RST_NUM				
> > > > 23
> > > >  
> > > > +/* INFRA RST0 */
> > > > +#define MT8192_INFRA_RST0_LVTS_AP_RST				
> > > > 0
> > > > +/* INFRA RST2 */
> > > > +#define MT8192_INFRA_RST2_PCIE_PHY_RST				
> > > > 15
> > > > +/* INFRA RST3 */
> > > > +#define MT8192_INFRA_RST3_PTP_RST				
> > > > 5
> > > > +/* INFRA RST4 */
> > > > +#define MT8192_INFRA_RST4_LVTS_MCU				
> > > > 12
> > > > +#define MT8192_INFRA_RST4_PCIE_TOP				
> > > > 1
> > > 
> > > These should be the IDs of reset, not some register
> > > values/offsets.
> > > Therefore it is expected to have them incremented by 1.
> > > 
> > > 
> > 
> > Hello Krzysztof,
> > 
> > This is define bit.
> > 
> > There is serveral reset set for infra_ao while it's not serial.
> > For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
> > We are implement #reset-cells = <2>, and we can use this reset
> > drive
> > more easier.
> > 
> > For example, in dts, we can define
> > infra_ao: syscon {
> > 	compatible = "mediatek,mt8192-infracfg", "syscon";
> >  	reg = <0 0x10001000 0 0x1000>;
> >  	#clock-cells = <1>;
> > 	#reset-cells = <2>;
> > };
> > 
> > thermal {
> > 	...
> > 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
> > 	...
> > };
> > 
> > If it's acceptabel, I can update all bit difinition from 0 to 15
> > for
> > all reset set.
> 
> Bits are not acceptable, because you embed specific device
> programming
> model (register bits) into the binding.
> 
> These should be IDs, so decimal numbers incremented from 0, so:
> #define MT8192_INFRA_RST0_LVTS_AP_RST				0
> #define MT8192_INFRA_RST4_LVTS_MCU				1
> #define MT8192_INFRA_RST4_PCIE_TOP				2
> 
> And what is 0x730 in your example? It does not look like ID of a
> reset...
> 
> Entire changeset look wrong from DT point of view.
> 
> Best regards,
> Krzysztof

Hello Krzysztof,

Got it. I will modify them to reset index.
And the dts in my next version would somthing like this:

----
#define MT8192_INFRA_THERMAL_CTRL_RST			0
#define MT8192_INFRA_PEXTP_PHY_RST			79
#define MT8192_INFRA_PTP_RST				101
#define MT8192_INFRA_RST4_PCIE_TOP			129
#define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140
----

infra_ao: syscon {
	compatible = "mediatek,mt8192-infracfg", "syscon";
	reg = <0 0x10001000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
};

thermal {
	...
	resets = <&infra_ao MT8192_INFRA_THERMAL_CTRL_MCU_RST>;
	...
};

BRs,
Rex


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^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
  2022-04-25  7:44         ` Krzysztof Kozlowski
  (?)
@ 2022-04-26  8:24           ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-26  8:24 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Mon, 2022-04-25 at 15:44 +0800, Krzysztof Kozlowski wrote:
> On 25/04/2022 04:37, Rex-BC Chen wrote:
> > > > +  '#reset-cells':
> > > > +    maximum: 2
> > > 
> > > Why this is a maximum? Usually this is const, so how do you use
> > > it
> > > (with
> > > what values)?
> > > 
> > 
> > We need to let the driver compatible with previous setting in
> > drivers/clk/mediatek/reset.c
> 
> Then it should be enum [1, 2], because '0' is not valid.
> 
> > There are two use cases in our reset driver:
> > (Refer to [1])
> > 
> > 1. #reset-cells = <1>
> >    When we input the argument, the older driver
> > use is to calculate  
> >    bank and bit by different method. From the implementation of
> >    reset_xlate(), we can see if the argument number is 1, it will
> >    return directly.
> 
> I understand this is an old binding with older compatibles, so this
> should be restricted per each variant (allOf:if:then)... but wait,
> old
> binding did not allow any reset-cells! You add an entirely new
> binding
> property and already want to support some older (deprecated?) way.
> 
> > 
> > 2. #reset-cells = <2>
> >    The input arguments is offset and bit. When we input two
> > arguments,
> >    we can use reset_xlate() to calculate the corresponding id to
> > assert
> >    and deassert.
> > 
> > [1]:
> > 
https://urldefense.com/v3/__https://lore.kernel.org/all/20220422060152.13534-10-rex-bc.chen@mediatek.com/__;!!CTRNKA9wMg0ARbw!0U0Yrp6WQxZ0YNMjaLJbAdq6Zyc524B4CY57-TP7QJ5FoSkCM72VI7mHJyWa1SZCnYTK$
> >  
> > 
> > If it's acceptable, I will add this in commit message.
> 
> 
> Best regards,
> Krzysztof

Hello Krzysztof,

I will let #reset-cells = <1> in next version and abandon the
modification of reset_xlate().

Thanks!

BRs,
Rex


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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
@ 2022-04-26  8:24           ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-26  8:24 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Mon, 2022-04-25 at 15:44 +0800, Krzysztof Kozlowski wrote:
> On 25/04/2022 04:37, Rex-BC Chen wrote:
> > > > +  '#reset-cells':
> > > > +    maximum: 2
> > > 
> > > Why this is a maximum? Usually this is const, so how do you use
> > > it
> > > (with
> > > what values)?
> > > 
> > 
> > We need to let the driver compatible with previous setting in
> > drivers/clk/mediatek/reset.c
> 
> Then it should be enum [1, 2], because '0' is not valid.
> 
> > There are two use cases in our reset driver:
> > (Refer to [1])
> > 
> > 1. #reset-cells = <1>
> >    When we input the argument, the older driver
> > use is to calculate  
> >    bank and bit by different method. From the implementation of
> >    reset_xlate(), we can see if the argument number is 1, it will
> >    return directly.
> 
> I understand this is an old binding with older compatibles, so this
> should be restricted per each variant (allOf:if:then)... but wait,
> old
> binding did not allow any reset-cells! You add an entirely new
> binding
> property and already want to support some older (deprecated?) way.
> 
> > 
> > 2. #reset-cells = <2>
> >    The input arguments is offset and bit. When we input two
> > arguments,
> >    we can use reset_xlate() to calculate the corresponding id to
> > assert
> >    and deassert.
> > 
> > [1]:
> > 
https://urldefense.com/v3/__https://lore.kernel.org/all/20220422060152.13534-10-rex-bc.chen@mediatek.com/__;!!CTRNKA9wMg0ARbw!0U0Yrp6WQxZ0YNMjaLJbAdq6Zyc524B4CY57-TP7QJ5FoSkCM72VI7mHJyWa1SZCnYTK$
> >  
> > 
> > If it's acceptable, I will add this in commit message.
> 
> 
> Best regards,
> Krzysztof

Hello Krzysztof,

I will let #reset-cells = <1> in next version and abandon the
modification of reset_xlate().

Thanks!

BRs,
Rex


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
@ 2022-04-26  8:24           ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-26  8:24 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Mon, 2022-04-25 at 15:44 +0800, Krzysztof Kozlowski wrote:
> On 25/04/2022 04:37, Rex-BC Chen wrote:
> > > > +  '#reset-cells':
> > > > +    maximum: 2
> > > 
> > > Why this is a maximum? Usually this is const, so how do you use
> > > it
> > > (with
> > > what values)?
> > > 
> > 
> > We need to let the driver compatible with previous setting in
> > drivers/clk/mediatek/reset.c
> 
> Then it should be enum [1, 2], because '0' is not valid.
> 
> > There are two use cases in our reset driver:
> > (Refer to [1])
> > 
> > 1. #reset-cells = <1>
> >    When we input the argument, the older driver
> > use is to calculate  
> >    bank and bit by different method. From the implementation of
> >    reset_xlate(), we can see if the argument number is 1, it will
> >    return directly.
> 
> I understand this is an old binding with older compatibles, so this
> should be restricted per each variant (allOf:if:then)... but wait,
> old
> binding did not allow any reset-cells! You add an entirely new
> binding
> property and already want to support some older (deprecated?) way.
> 
> > 
> > 2. #reset-cells = <2>
> >    The input arguments is offset and bit. When we input two
> > arguments,
> >    we can use reset_xlate() to calculate the corresponding id to
> > assert
> >    and deassert.
> > 
> > [1]:
> > 
https://urldefense.com/v3/__https://lore.kernel.org/all/20220422060152.13534-10-rex-bc.chen@mediatek.com/__;!!CTRNKA9wMg0ARbw!0U0Yrp6WQxZ0YNMjaLJbAdq6Zyc524B4CY57-TP7QJ5FoSkCM72VI7mHJyWa1SZCnYTK$
> >  
> > 
> > If it's acceptable, I will add this in commit message.
> 
> 
> Best regards,
> Krzysztof

Hello Krzysztof,

I will let #reset-cells = <1> in next version and abandon the
modification of reset_xlate().

Thanks!

BRs,
Rex


^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 01/17] clk: mediatek: reset: Add reset.h
  2022-04-22  6:01   ` Rex-BC Chen
  (?)
@ 2022-04-26  9:33     ` AngeloGioacchino Del Regno
  -1 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:33 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> Add a new file "reset.h" to place some definitions for clock reset.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 01/17] clk: mediatek: reset: Add reset.h
@ 2022-04-26  9:33     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:33 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> Add a new file "reset.h" to place some definitions for clock reset.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 01/17] clk: mediatek: reset: Add reset.h
@ 2022-04-26  9:33     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:33 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> Add a new file "reset.h" to place some definitions for clock reset.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 03/17] clk: mediatek: reset: Refine and reorder functions in reset.c
  2022-04-22  6:01   ` Rex-BC Chen
  (?)
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  -1 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> To make drivers more readable, we modify the indentation of the drivers
> and reorder the location of functions.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 03/17] clk: mediatek: reset: Refine and reorder functions in reset.c
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> To make drivers more readable, we modify the indentation of the drivers
> and reorder the location of functions.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 03/17] clk: mediatek: reset: Refine and reorder functions in reset.c
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> To make drivers more readable, we modify the indentation of the drivers
> and reorder the location of functions.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 04/17] clk: mediatek: reset: Extract common drivers to update function
  2022-04-22  6:01   ` Rex-BC Chen
  (?)
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  -1 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> To make drivers more clear and readable, we extract common code
> within assert and deassert to mtk_reset_update_set_clr() and
> mtk_reset_update().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 04/17] clk: mediatek: reset: Extract common drivers to update function
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> To make drivers more clear and readable, we extract common code
> within assert and deassert to mtk_reset_update_set_clr() and
> mtk_reset_update().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 04/17] clk: mediatek: reset: Extract common drivers to update function
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> To make drivers more clear and readable, we extract common code
> within assert and deassert to mtk_reset_update_set_clr() and
> mtk_reset_update().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 06/17] clk: mediatek: reset: Revise structure to control reset register
  2022-04-22  6:01   ` Rex-BC Chen
  (?)
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  -1 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> To declare the reset data easier instead of using many input variables
> to mtk_register_reset_controller().
> 
> - Add mtk_clk_rst_desc to input the reset register data.
> - Rename "mtk_reset" to "mtk_clk_rst_data". We use it to store reset
>    register data and store reset controller device. It's more easy to
>    manager the data for each reset controller.
> - Extract container_of in update functions to to_mtk_clk_rst_data().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 06/17] clk: mediatek: reset: Revise structure to control reset register
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> To declare the reset data easier instead of using many input variables
> to mtk_register_reset_controller().
> 
> - Add mtk_clk_rst_desc to input the reset register data.
> - Rename "mtk_reset" to "mtk_clk_rst_data". We use it to store reset
>    register data and store reset controller device. It's more easy to
>    manager the data for each reset controller.
> - Extract container_of in update functions to to_mtk_clk_rst_data().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 06/17] clk: mediatek: reset: Revise structure to control reset register
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> To declare the reset data easier instead of using many input variables
> to mtk_register_reset_controller().
> 
> - Add mtk_clk_rst_desc to input the reset register data.
> - Rename "mtk_reset" to "mtk_clk_rst_data". We use it to store reset
>    register data and store reset controller device. It's more easy to
>    manager the data for each reset controller.
> - Extract container_of in update functions to to_mtk_clk_rst_data().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 07/17] clk: mediatek: reset: Add return for clock reset register function
  2022-04-22  6:01   ` Rex-BC Chen
  (?)
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  -1 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> To make error handling, we add return for mtk_clk_register_rst_ctrl().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 07/17] clk: mediatek: reset: Add return for clock reset register function
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> To make error handling, we add return for mtk_clk_register_rst_ctrl().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 07/17] clk: mediatek: reset: Add return for clock reset register function
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> To make error handling, we add return for mtk_clk_register_rst_ctrl().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 05/17] clk: mediatek: reset: Merge and revise reset register function
  2022-04-22  6:01   ` Rex-BC Chen
  (?)
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  -1 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> There are two versions for clock reset register control of MediaTek
> SoCs. The old hardware is one bit per reset control, and does not
> have separate registers for bit set, clear and read-back operations.
> This matches the scheme supported by the simple reset driver.
> 
> However, because we need to use our data structure "struct mtk_reset",
> we can not use the operation of simple reset driver. We keep the
> original functions and name this version as "MTK_RST_SIMPLE".
> 
> In this patch:
> - Add a version enum to separate different MediaTek reset hardware.
> - Merge the reset register function of simple and set_clr into one
>    function "mtk_register_reset_controller".
> - Rename input variable "num_regs" to "rst_set_nr" to avoid
>    confusion. This variable is used to define the number of reset set.
> - Rename "regofs" to "reg_ofs".
> - Adjust delaration type for mtk_register_reset_controller().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 05/17] clk: mediatek: reset: Merge and revise reset register function
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> There are two versions for clock reset register control of MediaTek
> SoCs. The old hardware is one bit per reset control, and does not
> have separate registers for bit set, clear and read-back operations.
> This matches the scheme supported by the simple reset driver.
> 
> However, because we need to use our data structure "struct mtk_reset",
> we can not use the operation of simple reset driver. We keep the
> original functions and name this version as "MTK_RST_SIMPLE".
> 
> In this patch:
> - Add a version enum to separate different MediaTek reset hardware.
> - Merge the reset register function of simple and set_clr into one
>    function "mtk_register_reset_controller".
> - Rename input variable "num_regs" to "rst_set_nr" to avoid
>    confusion. This variable is used to define the number of reset set.
> - Rename "regofs" to "reg_ofs".
> - Adjust delaration type for mtk_register_reset_controller().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 05/17] clk: mediatek: reset: Merge and revise reset register function
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> There are two versions for clock reset register control of MediaTek
> SoCs. The old hardware is one bit per reset control, and does not
> have separate registers for bit set, clear and read-back operations.
> This matches the scheme supported by the simple reset driver.
> 
> However, because we need to use our data structure "struct mtk_reset",
> we can not use the operation of simple reset driver. We keep the
> original functions and name this version as "MTK_RST_SIMPLE".
> 
> In this patch:
> - Add a version enum to separate different MediaTek reset hardware.
> - Merge the reset register function of simple and set_clr into one
>    function "mtk_register_reset_controller".
> - Rename input variable "num_regs" to "rst_set_nr" to avoid
>    confusion. This variable is used to define the number of reset set.
> - Rename "regofs" to "reg_ofs".
> - Adjust delaration type for mtk_register_reset_controller().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 08/17] clk: mediatek: reset: Add new register reset function with device
  2022-04-22  6:01   ` Rex-BC Chen
  (?)
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  -1 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> It's a proper implementation using device to register reset controller.
> Howerver, some clock drviers of MediaTeks only provide device_node.
> Therefore, we still remain register reset function with device_node and
> add a function with device to register reset controller.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 08/17] clk: mediatek: reset: Add new register reset function with device
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> It's a proper implementation using device to register reset controller.
> Howerver, some clock drviers of MediaTeks only provide device_node.
> Therefore, we still remain register reset function with device_node and
> add a function with device to register reset controller.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 08/17] clk: mediatek: reset: Add new register reset function with device
@ 2022-04-26  9:34     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 117+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-26  9:34 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, chun-jie.chen, wenst, runyang.chen, linux-kernel,
	devicetree, linux-clk, linux-arm-kernel, linux-mediatek,
	Project_Global_Chrome_Upstream_Group

Il 22/04/22 08:01, Rex-BC Chen ha scritto:
> It's a proper implementation using device to register reset controller.
> Howerver, some clock drviers of MediaTeks only provide device_node.
> Therefore, we still remain register reset function with device_node and
> add a function with device to register reset controller.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
  2022-04-26  8:23           ` Rex-BC Chen
  (?)
@ 2022-04-28  6:40             ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-28  6:40 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On 26/04/2022 10:23, Rex-BC Chen wrote:
> On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
>> On 25/04/2022 07:01, Rex-BC Chen wrote:
>>> On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
>>>> On 22/04/2022 08:01, Rex-BC Chen wrote:
>>>>> To support reset of infra_ao, add the bit definition for
>>>>> thermal/PCIe/SVS.
>>>>>
>>>>> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>>>>> ---
>>>>>  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
>>>>>  1 file changed, 10 insertions(+)
>>>>>
>>>>> diff --git a/include/dt-bindings/reset/mt8192-resets.h
>>>>> b/include/dt-bindings/reset/mt8192-resets.h
>>>>> index be9a7ca245b9..d5f3433175c1 100644
>>>>> --- a/include/dt-bindings/reset/mt8192-resets.h
>>>>> +++ b/include/dt-bindings/reset/mt8192-resets.h
>>>>> @@ -27,4 +27,14 @@
>>>>>  
>>>>>  #define MT8192_TOPRGU_SW_RST_NUM				
>>>>> 23
>>>>>  
>>>>> +/* INFRA RST0 */
>>>>> +#define MT8192_INFRA_RST0_LVTS_AP_RST				
>>>>> 0
>>>>> +/* INFRA RST2 */
>>>>> +#define MT8192_INFRA_RST2_PCIE_PHY_RST				
>>>>> 15
>>>>> +/* INFRA RST3 */
>>>>> +#define MT8192_INFRA_RST3_PTP_RST				
>>>>> 5
>>>>> +/* INFRA RST4 */
>>>>> +#define MT8192_INFRA_RST4_LVTS_MCU				
>>>>> 12
>>>>> +#define MT8192_INFRA_RST4_PCIE_TOP				
>>>>> 1
>>>>
>>>> These should be the IDs of reset, not some register
>>>> values/offsets.
>>>> Therefore it is expected to have them incremented by 1.
>>>>
>>>>
>>>
>>> Hello Krzysztof,
>>>
>>> This is define bit.
>>>
>>> There is serveral reset set for infra_ao while it's not serial.
>>> For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
>>> We are implement #reset-cells = <2>, and we can use this reset
>>> drive
>>> more easier.
>>>
>>> For example, in dts, we can define
>>> infra_ao: syscon {
>>> 	compatible = "mediatek,mt8192-infracfg", "syscon";
>>>  	reg = <0 0x10001000 0 0x1000>;
>>>  	#clock-cells = <1>;
>>> 	#reset-cells = <2>;
>>> };
>>>
>>> thermal {
>>> 	...
>>> 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
>>> 	...
>>> };
>>>
>>> If it's acceptabel, I can update all bit difinition from 0 to 15
>>> for
>>> all reset set.
>>
>> Bits are not acceptable, because you embed specific device
>> programming
>> model (register bits) into the binding.
>>
>> These should be IDs, so decimal numbers incremented from 0, so:
>> #define MT8192_INFRA_RST0_LVTS_AP_RST				0
>> #define MT8192_INFRA_RST4_LVTS_MCU				1
>> #define MT8192_INFRA_RST4_PCIE_TOP				2
>>
>> And what is 0x730 in your example? It does not look like ID of a
>> reset...
>>
>> Entire changeset look wrong from DT point of view.
>>
>> Best regards,
>> Krzysztof
> 
> Hello Krzysztof,
> 
> Got it. I will modify them to reset index.
> And the dts in my next version would somthing like this:
> 
> ----
> #define MT8192_INFRA_THERMAL_CTRL_RST			0
> #define MT8192_INFRA_PEXTP_PHY_RST			79
> #define MT8192_INFRA_PTP_RST				101
> #define MT8192_INFRA_RST4_PCIE_TOP			129
> #define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140

These are still not IDs, incremented by one.

So again from beginning:
0
1
2
...

Do not encode hardware register bits into the binding.

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-28  6:40             ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-28  6:40 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On 26/04/2022 10:23, Rex-BC Chen wrote:
> On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
>> On 25/04/2022 07:01, Rex-BC Chen wrote:
>>> On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
>>>> On 22/04/2022 08:01, Rex-BC Chen wrote:
>>>>> To support reset of infra_ao, add the bit definition for
>>>>> thermal/PCIe/SVS.
>>>>>
>>>>> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>>>>> ---
>>>>>  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
>>>>>  1 file changed, 10 insertions(+)
>>>>>
>>>>> diff --git a/include/dt-bindings/reset/mt8192-resets.h
>>>>> b/include/dt-bindings/reset/mt8192-resets.h
>>>>> index be9a7ca245b9..d5f3433175c1 100644
>>>>> --- a/include/dt-bindings/reset/mt8192-resets.h
>>>>> +++ b/include/dt-bindings/reset/mt8192-resets.h
>>>>> @@ -27,4 +27,14 @@
>>>>>  
>>>>>  #define MT8192_TOPRGU_SW_RST_NUM				
>>>>> 23
>>>>>  
>>>>> +/* INFRA RST0 */
>>>>> +#define MT8192_INFRA_RST0_LVTS_AP_RST				
>>>>> 0
>>>>> +/* INFRA RST2 */
>>>>> +#define MT8192_INFRA_RST2_PCIE_PHY_RST				
>>>>> 15
>>>>> +/* INFRA RST3 */
>>>>> +#define MT8192_INFRA_RST3_PTP_RST				
>>>>> 5
>>>>> +/* INFRA RST4 */
>>>>> +#define MT8192_INFRA_RST4_LVTS_MCU				
>>>>> 12
>>>>> +#define MT8192_INFRA_RST4_PCIE_TOP				
>>>>> 1
>>>>
>>>> These should be the IDs of reset, not some register
>>>> values/offsets.
>>>> Therefore it is expected to have them incremented by 1.
>>>>
>>>>
>>>
>>> Hello Krzysztof,
>>>
>>> This is define bit.
>>>
>>> There is serveral reset set for infra_ao while it's not serial.
>>> For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
>>> We are implement #reset-cells = <2>, and we can use this reset
>>> drive
>>> more easier.
>>>
>>> For example, in dts, we can define
>>> infra_ao: syscon {
>>> 	compatible = "mediatek,mt8192-infracfg", "syscon";
>>>  	reg = <0 0x10001000 0 0x1000>;
>>>  	#clock-cells = <1>;
>>> 	#reset-cells = <2>;
>>> };
>>>
>>> thermal {
>>> 	...
>>> 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
>>> 	...
>>> };
>>>
>>> If it's acceptabel, I can update all bit difinition from 0 to 15
>>> for
>>> all reset set.
>>
>> Bits are not acceptable, because you embed specific device
>> programming
>> model (register bits) into the binding.
>>
>> These should be IDs, so decimal numbers incremented from 0, so:
>> #define MT8192_INFRA_RST0_LVTS_AP_RST				0
>> #define MT8192_INFRA_RST4_LVTS_MCU				1
>> #define MT8192_INFRA_RST4_PCIE_TOP				2
>>
>> And what is 0x730 in your example? It does not look like ID of a
>> reset...
>>
>> Entire changeset look wrong from DT point of view.
>>
>> Best regards,
>> Krzysztof
> 
> Hello Krzysztof,
> 
> Got it. I will modify them to reset index.
> And the dts in my next version would somthing like this:
> 
> ----
> #define MT8192_INFRA_THERMAL_CTRL_RST			0
> #define MT8192_INFRA_PEXTP_PHY_RST			79
> #define MT8192_INFRA_PTP_RST				101
> #define MT8192_INFRA_RST4_PCIE_TOP			129
> #define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140

These are still not IDs, incremented by one.

So again from beginning:
0
1
2
...

Do not encode hardware register bits into the binding.

Best regards,
Krzysztof

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-28  6:40             ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-28  6:40 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On 26/04/2022 10:23, Rex-BC Chen wrote:
> On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
>> On 25/04/2022 07:01, Rex-BC Chen wrote:
>>> On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
>>>> On 22/04/2022 08:01, Rex-BC Chen wrote:
>>>>> To support reset of infra_ao, add the bit definition for
>>>>> thermal/PCIe/SVS.
>>>>>
>>>>> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>>>>> ---
>>>>>  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
>>>>>  1 file changed, 10 insertions(+)
>>>>>
>>>>> diff --git a/include/dt-bindings/reset/mt8192-resets.h
>>>>> b/include/dt-bindings/reset/mt8192-resets.h
>>>>> index be9a7ca245b9..d5f3433175c1 100644
>>>>> --- a/include/dt-bindings/reset/mt8192-resets.h
>>>>> +++ b/include/dt-bindings/reset/mt8192-resets.h
>>>>> @@ -27,4 +27,14 @@
>>>>>  
>>>>>  #define MT8192_TOPRGU_SW_RST_NUM				
>>>>> 23
>>>>>  
>>>>> +/* INFRA RST0 */
>>>>> +#define MT8192_INFRA_RST0_LVTS_AP_RST				
>>>>> 0
>>>>> +/* INFRA RST2 */
>>>>> +#define MT8192_INFRA_RST2_PCIE_PHY_RST				
>>>>> 15
>>>>> +/* INFRA RST3 */
>>>>> +#define MT8192_INFRA_RST3_PTP_RST				
>>>>> 5
>>>>> +/* INFRA RST4 */
>>>>> +#define MT8192_INFRA_RST4_LVTS_MCU				
>>>>> 12
>>>>> +#define MT8192_INFRA_RST4_PCIE_TOP				
>>>>> 1
>>>>
>>>> These should be the IDs of reset, not some register
>>>> values/offsets.
>>>> Therefore it is expected to have them incremented by 1.
>>>>
>>>>
>>>
>>> Hello Krzysztof,
>>>
>>> This is define bit.
>>>
>>> There is serveral reset set for infra_ao while it's not serial.
>>> For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
>>> We are implement #reset-cells = <2>, and we can use this reset
>>> drive
>>> more easier.
>>>
>>> For example, in dts, we can define
>>> infra_ao: syscon {
>>> 	compatible = "mediatek,mt8192-infracfg", "syscon";
>>>  	reg = <0 0x10001000 0 0x1000>;
>>>  	#clock-cells = <1>;
>>> 	#reset-cells = <2>;
>>> };
>>>
>>> thermal {
>>> 	...
>>> 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
>>> 	...
>>> };
>>>
>>> If it's acceptabel, I can update all bit difinition from 0 to 15
>>> for
>>> all reset set.
>>
>> Bits are not acceptable, because you embed specific device
>> programming
>> model (register bits) into the binding.
>>
>> These should be IDs, so decimal numbers incremented from 0, so:
>> #define MT8192_INFRA_RST0_LVTS_AP_RST				0
>> #define MT8192_INFRA_RST4_LVTS_MCU				1
>> #define MT8192_INFRA_RST4_PCIE_TOP				2
>>
>> And what is 0x730 in your example? It does not look like ID of a
>> reset...
>>
>> Entire changeset look wrong from DT point of view.
>>
>> Best regards,
>> Krzysztof
> 
> Hello Krzysztof,
> 
> Got it. I will modify them to reset index.
> And the dts in my next version would somthing like this:
> 
> ----
> #define MT8192_INFRA_THERMAL_CTRL_RST			0
> #define MT8192_INFRA_PEXTP_PHY_RST			79
> #define MT8192_INFRA_PTP_RST				101
> #define MT8192_INFRA_RST4_PCIE_TOP			129
> #define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140

These are still not IDs, incremented by one.

So again from beginning:
0
1
2
...

Do not encode hardware register bits into the binding.

Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
  2022-04-28  6:40             ` Krzysztof Kozlowski
  (?)
@ 2022-04-28  6:48               ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-28  6:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Thu, 2022-04-28 at 14:40 +0800, Krzysztof Kozlowski wrote:
> On 26/04/2022 10:23, Rex-BC Chen wrote:
> > On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
> > > On 25/04/2022 07:01, Rex-BC Chen wrote:
> > > > On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
> > > > > On 22/04/2022 08:01, Rex-BC Chen wrote:
> > > > > > To support reset of infra_ao, add the bit definition for
> > > > > > thermal/PCIe/SVS.
> > > > > > 
> > > > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > > > > > ---
> > > > > >  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
> > > > > >  1 file changed, 10 insertions(+)
> > > > > > 
> > > > > > diff --git a/include/dt-bindings/reset/mt8192-resets.h
> > > > > > b/include/dt-bindings/reset/mt8192-resets.h
> > > > > > index be9a7ca245b9..d5f3433175c1 100644
> > > > > > --- a/include/dt-bindings/reset/mt8192-resets.h
> > > > > > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > > > > > @@ -27,4 +27,14 @@
> > > > > >  
> > > > > >  #define MT8192_TOPRGU_SW_RST_NUM				
> > > > > > 23
> > > > > >  
> > > > > > +/* INFRA RST0 */
> > > > > > +#define MT8192_INFRA_RST0_LVTS_AP_RST			
> > > > > > 	
> > > > > > 0
> > > > > > +/* INFRA RST2 */
> > > > > > +#define MT8192_INFRA_RST2_PCIE_PHY_RST			
> > > > > > 	
> > > > > > 15
> > > > > > +/* INFRA RST3 */
> > > > > > +#define MT8192_INFRA_RST3_PTP_RST				
> > > > > > 5
> > > > > > +/* INFRA RST4 */
> > > > > > +#define MT8192_INFRA_RST4_LVTS_MCU				
> > > > > > 12
> > > > > > +#define MT8192_INFRA_RST4_PCIE_TOP				
> > > > > > 1
> > > > > 
> > > > > These should be the IDs of reset, not some register
> > > > > values/offsets.
> > > > > Therefore it is expected to have them incremented by 1.
> > > > > 
> > > > > 
> > > > 
> > > > Hello Krzysztof,
> > > > 
> > > > This is define bit.
> > > > 
> > > > There is serveral reset set for infra_ao while it's not serial.
> > > > For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
> > > > We are implement #reset-cells = <2>, and we can use this reset
> > > > drive
> > > > more easier.
> > > > 
> > > > For example, in dts, we can define
> > > > infra_ao: syscon {
> > > > 	compatible = "mediatek,mt8192-infracfg", "syscon";
> > > >  	reg = <0 0x10001000 0 0x1000>;
> > > >  	#clock-cells = <1>;
> > > > 	#reset-cells = <2>;
> > > > };
> > > > 
> > > > thermal {
> > > > 	...
> > > > 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
> > > > 	...
> > > > };
> > > > 
> > > > If it's acceptabel, I can update all bit difinition from 0 to
> > > > 15
> > > > for
> > > > all reset set.
> > > 
> > > Bits are not acceptable, because you embed specific device
> > > programming
> > > model (register bits) into the binding.
> > > 
> > > These should be IDs, so decimal numbers incremented from 0, so:
> > > #define MT8192_INFRA_RST0_LVTS_AP_RST				
> > > 0
> > > #define MT8192_INFRA_RST4_LVTS_MCU				
> > > 1
> > > #define MT8192_INFRA_RST4_PCIE_TOP				
> > > 2
> > > 
> > > And what is 0x730 in your example? It does not look like ID of a
> > > reset...
> > > 
> > > Entire changeset look wrong from DT point of view.
> > > 
> > > Best regards,
> > > Krzysztof
> > 
> > Hello Krzysztof,
> > 
> > Got it. I will modify them to reset index.
> > And the dts in my next version would somthing like this:
> > 
> > ----
> > #define MT8192_INFRA_THERMAL_CTRL_RST			0
> > #define MT8192_INFRA_PEXTP_PHY_RST			79
> > #define MT8192_INFRA_PTP_RST				101
> > #define MT8192_INFRA_RST4_PCIE_TOP			129
> > #define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140
> 
> These are still not IDs, incremented by one.
> 
> So again from beginning:
> 0
> 1
> 2
> ...
> 
> Do not encode hardware register bits into the binding.
> 
> Best regards,
> Krzysztof

Hello Krzysztof,

It's not bit definiton, and it's index for our reset.
We have 32*5 reset bits for infra.
But we only use these 5 index currently, I do not list all of them.

The implementation is in [1].
-----
static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
 	unsigned int deassert_ofs = deassert ? 0x4 : 0;
 
 	return regmap_write(data->regmap,
			    data->desc->rst_bank_ofs[id /          
 					RST_NR_PER_BANK] +
			    deassert_ofs,
			    BIT(id % RST_NR_PER_BANK));
 }
-----

[1]: 
https://lore.kernel.org/all/20220427030950.23395-8-rex-bc.chen@mediatek.com/

BRs,
Rex


^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-28  6:48               ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-28  6:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Thu, 2022-04-28 at 14:40 +0800, Krzysztof Kozlowski wrote:
> On 26/04/2022 10:23, Rex-BC Chen wrote:
> > On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
> > > On 25/04/2022 07:01, Rex-BC Chen wrote:
> > > > On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
> > > > > On 22/04/2022 08:01, Rex-BC Chen wrote:
> > > > > > To support reset of infra_ao, add the bit definition for
> > > > > > thermal/PCIe/SVS.
> > > > > > 
> > > > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > > > > > ---
> > > > > >  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
> > > > > >  1 file changed, 10 insertions(+)
> > > > > > 
> > > > > > diff --git a/include/dt-bindings/reset/mt8192-resets.h
> > > > > > b/include/dt-bindings/reset/mt8192-resets.h
> > > > > > index be9a7ca245b9..d5f3433175c1 100644
> > > > > > --- a/include/dt-bindings/reset/mt8192-resets.h
> > > > > > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > > > > > @@ -27,4 +27,14 @@
> > > > > >  
> > > > > >  #define MT8192_TOPRGU_SW_RST_NUM				
> > > > > > 23
> > > > > >  
> > > > > > +/* INFRA RST0 */
> > > > > > +#define MT8192_INFRA_RST0_LVTS_AP_RST			
> > > > > > 	
> > > > > > 0
> > > > > > +/* INFRA RST2 */
> > > > > > +#define MT8192_INFRA_RST2_PCIE_PHY_RST			
> > > > > > 	
> > > > > > 15
> > > > > > +/* INFRA RST3 */
> > > > > > +#define MT8192_INFRA_RST3_PTP_RST				
> > > > > > 5
> > > > > > +/* INFRA RST4 */
> > > > > > +#define MT8192_INFRA_RST4_LVTS_MCU				
> > > > > > 12
> > > > > > +#define MT8192_INFRA_RST4_PCIE_TOP				
> > > > > > 1
> > > > > 
> > > > > These should be the IDs of reset, not some register
> > > > > values/offsets.
> > > > > Therefore it is expected to have them incremented by 1.
> > > > > 
> > > > > 
> > > > 
> > > > Hello Krzysztof,
> > > > 
> > > > This is define bit.
> > > > 
> > > > There is serveral reset set for infra_ao while it's not serial.
> > > > For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
> > > > We are implement #reset-cells = <2>, and we can use this reset
> > > > drive
> > > > more easier.
> > > > 
> > > > For example, in dts, we can define
> > > > infra_ao: syscon {
> > > > 	compatible = "mediatek,mt8192-infracfg", "syscon";
> > > >  	reg = <0 0x10001000 0 0x1000>;
> > > >  	#clock-cells = <1>;
> > > > 	#reset-cells = <2>;
> > > > };
> > > > 
> > > > thermal {
> > > > 	...
> > > > 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
> > > > 	...
> > > > };
> > > > 
> > > > If it's acceptabel, I can update all bit difinition from 0 to
> > > > 15
> > > > for
> > > > all reset set.
> > > 
> > > Bits are not acceptable, because you embed specific device
> > > programming
> > > model (register bits) into the binding.
> > > 
> > > These should be IDs, so decimal numbers incremented from 0, so:
> > > #define MT8192_INFRA_RST0_LVTS_AP_RST				
> > > 0
> > > #define MT8192_INFRA_RST4_LVTS_MCU				
> > > 1
> > > #define MT8192_INFRA_RST4_PCIE_TOP				
> > > 2
> > > 
> > > And what is 0x730 in your example? It does not look like ID of a
> > > reset...
> > > 
> > > Entire changeset look wrong from DT point of view.
> > > 
> > > Best regards,
> > > Krzysztof
> > 
> > Hello Krzysztof,
> > 
> > Got it. I will modify them to reset index.
> > And the dts in my next version would somthing like this:
> > 
> > ----
> > #define MT8192_INFRA_THERMAL_CTRL_RST			0
> > #define MT8192_INFRA_PEXTP_PHY_RST			79
> > #define MT8192_INFRA_PTP_RST				101
> > #define MT8192_INFRA_RST4_PCIE_TOP			129
> > #define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140
> 
> These are still not IDs, incremented by one.
> 
> So again from beginning:
> 0
> 1
> 2
> ...
> 
> Do not encode hardware register bits into the binding.
> 
> Best regards,
> Krzysztof

Hello Krzysztof,

It's not bit definiton, and it's index for our reset.
We have 32*5 reset bits for infra.
But we only use these 5 index currently, I do not list all of them.

The implementation is in [1].
-----
static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
 	unsigned int deassert_ofs = deassert ? 0x4 : 0;
 
 	return regmap_write(data->regmap,
			    data->desc->rst_bank_ofs[id /          
 					RST_NR_PER_BANK] +
			    deassert_ofs,
			    BIT(id % RST_NR_PER_BANK));
 }
-----

[1]: 
https://lore.kernel.org/all/20220427030950.23395-8-rex-bc.chen@mediatek.com/

BRs,
Rex


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-28  6:48               ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-28  6:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Thu, 2022-04-28 at 14:40 +0800, Krzysztof Kozlowski wrote:
> On 26/04/2022 10:23, Rex-BC Chen wrote:
> > On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
> > > On 25/04/2022 07:01, Rex-BC Chen wrote:
> > > > On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
> > > > > On 22/04/2022 08:01, Rex-BC Chen wrote:
> > > > > > To support reset of infra_ao, add the bit definition for
> > > > > > thermal/PCIe/SVS.
> > > > > > 
> > > > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > > > > > ---
> > > > > >  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
> > > > > >  1 file changed, 10 insertions(+)
> > > > > > 
> > > > > > diff --git a/include/dt-bindings/reset/mt8192-resets.h
> > > > > > b/include/dt-bindings/reset/mt8192-resets.h
> > > > > > index be9a7ca245b9..d5f3433175c1 100644
> > > > > > --- a/include/dt-bindings/reset/mt8192-resets.h
> > > > > > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > > > > > @@ -27,4 +27,14 @@
> > > > > >  
> > > > > >  #define MT8192_TOPRGU_SW_RST_NUM				
> > > > > > 23
> > > > > >  
> > > > > > +/* INFRA RST0 */
> > > > > > +#define MT8192_INFRA_RST0_LVTS_AP_RST			
> > > > > > 	
> > > > > > 0
> > > > > > +/* INFRA RST2 */
> > > > > > +#define MT8192_INFRA_RST2_PCIE_PHY_RST			
> > > > > > 	
> > > > > > 15
> > > > > > +/* INFRA RST3 */
> > > > > > +#define MT8192_INFRA_RST3_PTP_RST				
> > > > > > 5
> > > > > > +/* INFRA RST4 */
> > > > > > +#define MT8192_INFRA_RST4_LVTS_MCU				
> > > > > > 12
> > > > > > +#define MT8192_INFRA_RST4_PCIE_TOP				
> > > > > > 1
> > > > > 
> > > > > These should be the IDs of reset, not some register
> > > > > values/offsets.
> > > > > Therefore it is expected to have them incremented by 1.
> > > > > 
> > > > > 
> > > > 
> > > > Hello Krzysztof,
> > > > 
> > > > This is define bit.
> > > > 
> > > > There is serveral reset set for infra_ao while it's not serial.
> > > > For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
> > > > We are implement #reset-cells = <2>, and we can use this reset
> > > > drive
> > > > more easier.
> > > > 
> > > > For example, in dts, we can define
> > > > infra_ao: syscon {
> > > > 	compatible = "mediatek,mt8192-infracfg", "syscon";
> > > >  	reg = <0 0x10001000 0 0x1000>;
> > > >  	#clock-cells = <1>;
> > > > 	#reset-cells = <2>;
> > > > };
> > > > 
> > > > thermal {
> > > > 	...
> > > > 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
> > > > 	...
> > > > };
> > > > 
> > > > If it's acceptabel, I can update all bit difinition from 0 to
> > > > 15
> > > > for
> > > > all reset set.
> > > 
> > > Bits are not acceptable, because you embed specific device
> > > programming
> > > model (register bits) into the binding.
> > > 
> > > These should be IDs, so decimal numbers incremented from 0, so:
> > > #define MT8192_INFRA_RST0_LVTS_AP_RST				
> > > 0
> > > #define MT8192_INFRA_RST4_LVTS_MCU				
> > > 1
> > > #define MT8192_INFRA_RST4_PCIE_TOP				
> > > 2
> > > 
> > > And what is 0x730 in your example? It does not look like ID of a
> > > reset...
> > > 
> > > Entire changeset look wrong from DT point of view.
> > > 
> > > Best regards,
> > > Krzysztof
> > 
> > Hello Krzysztof,
> > 
> > Got it. I will modify them to reset index.
> > And the dts in my next version would somthing like this:
> > 
> > ----
> > #define MT8192_INFRA_THERMAL_CTRL_RST			0
> > #define MT8192_INFRA_PEXTP_PHY_RST			79
> > #define MT8192_INFRA_PTP_RST				101
> > #define MT8192_INFRA_RST4_PCIE_TOP			129
> > #define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140
> 
> These are still not IDs, incremented by one.
> 
> So again from beginning:
> 0
> 1
> 2
> ...
> 
> Do not encode hardware register bits into the binding.
> 
> Best regards,
> Krzysztof

Hello Krzysztof,

It's not bit definiton, and it's index for our reset.
We have 32*5 reset bits for infra.
But we only use these 5 index currently, I do not list all of them.

The implementation is in [1].
-----
static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
 	unsigned int deassert_ofs = deassert ? 0x4 : 0;
 
 	return regmap_write(data->regmap,
			    data->desc->rst_bank_ofs[id /          
 					RST_NR_PER_BANK] +
			    deassert_ofs,
			    BIT(id % RST_NR_PER_BANK));
 }
-----

[1]: 
https://lore.kernel.org/all/20220427030950.23395-8-rex-bc.chen@mediatek.com/

BRs,
Rex


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
  2022-04-28  6:48               ` Rex-BC Chen
  (?)
@ 2022-04-28  7:23                 ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-28  7:23 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On 28/04/2022 08:48, Rex-BC Chen wrote:
> On Thu, 2022-04-28 at 14:40 +0800, Krzysztof Kozlowski wrote:
>> On 26/04/2022 10:23, Rex-BC Chen wrote:
>>> On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
>>>> On 25/04/2022 07:01, Rex-BC Chen wrote:
>>>>> On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
>>>>>> On 22/04/2022 08:01, Rex-BC Chen wrote:
>>>>>>> To support reset of infra_ao, add the bit definition for
>>>>>>> thermal/PCIe/SVS.
>>>>>>>
>>>>>>> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>>>>>>> ---
>>>>>>>  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
>>>>>>>  1 file changed, 10 insertions(+)
>>>>>>>
>>>>>>> diff --git a/include/dt-bindings/reset/mt8192-resets.h
>>>>>>> b/include/dt-bindings/reset/mt8192-resets.h
>>>>>>> index be9a7ca245b9..d5f3433175c1 100644
>>>>>>> --- a/include/dt-bindings/reset/mt8192-resets.h
>>>>>>> +++ b/include/dt-bindings/reset/mt8192-resets.h
>>>>>>> @@ -27,4 +27,14 @@
>>>>>>>  
>>>>>>>  #define MT8192_TOPRGU_SW_RST_NUM				
>>>>>>> 23
>>>>>>>  
>>>>>>> +/* INFRA RST0 */
>>>>>>> +#define MT8192_INFRA_RST0_LVTS_AP_RST			
>>>>>>> 	
>>>>>>> 0
>>>>>>> +/* INFRA RST2 */
>>>>>>> +#define MT8192_INFRA_RST2_PCIE_PHY_RST			
>>>>>>> 	
>>>>>>> 15
>>>>>>> +/* INFRA RST3 */
>>>>>>> +#define MT8192_INFRA_RST3_PTP_RST				
>>>>>>> 5
>>>>>>> +/* INFRA RST4 */
>>>>>>> +#define MT8192_INFRA_RST4_LVTS_MCU				
>>>>>>> 12
>>>>>>> +#define MT8192_INFRA_RST4_PCIE_TOP				
>>>>>>> 1
>>>>>>
>>>>>> These should be the IDs of reset, not some register
>>>>>> values/offsets.
>>>>>> Therefore it is expected to have them incremented by 1.
>>>>>>
>>>>>>
>>>>>
>>>>> Hello Krzysztof,
>>>>>
>>>>> This is define bit.
>>>>>
>>>>> There is serveral reset set for infra_ao while it's not serial.
>>>>> For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
>>>>> We are implement #reset-cells = <2>, and we can use this reset
>>>>> drive
>>>>> more easier.
>>>>>
>>>>> For example, in dts, we can define
>>>>> infra_ao: syscon {
>>>>> 	compatible = "mediatek,mt8192-infracfg", "syscon";
>>>>>  	reg = <0 0x10001000 0 0x1000>;
>>>>>  	#clock-cells = <1>;
>>>>> 	#reset-cells = <2>;
>>>>> };
>>>>>
>>>>> thermal {
>>>>> 	...
>>>>> 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
>>>>> 	...
>>>>> };
>>>>>
>>>>> If it's acceptabel, I can update all bit difinition from 0 to
>>>>> 15
>>>>> for
>>>>> all reset set.
>>>>
>>>> Bits are not acceptable, because you embed specific device
>>>> programming
>>>> model (register bits) into the binding.
>>>>
>>>> These should be IDs, so decimal numbers incremented from 0, so:
>>>> #define MT8192_INFRA_RST0_LVTS_AP_RST				
>>>> 0
>>>> #define MT8192_INFRA_RST4_LVTS_MCU				
>>>> 1
>>>> #define MT8192_INFRA_RST4_PCIE_TOP				
>>>> 2
>>>>
>>>> And what is 0x730 in your example? It does not look like ID of a
>>>> reset...
>>>>
>>>> Entire changeset look wrong from DT point of view.
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>
>>> Hello Krzysztof,
>>>
>>> Got it. I will modify them to reset index.
>>> And the dts in my next version would somthing like this:
>>>
>>> ----
>>> #define MT8192_INFRA_THERMAL_CTRL_RST			0
>>> #define MT8192_INFRA_PEXTP_PHY_RST			79
>>> #define MT8192_INFRA_PTP_RST				101
>>> #define MT8192_INFRA_RST4_PCIE_TOP			129
>>> #define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140
>>
>> These are still not IDs, incremented by one.
>>
>> So again from beginning:
>> 0
>> 1
>> 2
>> ...
>>
>> Do not encode hardware register bits into the binding.
>>
>> Best regards,
>> Krzysztof
> 
> Hello Krzysztof,
> 
> It's not bit definiton, and it's index for our reset.
> We have 32*5 reset bits for infra.
> But we only use these 5 index currently, I do not list all of them.

You do not have to list all of them. You can list three, e.g.:

#define MT8192_INFRA_THERMAL_CTRL_RST			0
#define MT8192_INFRA_PEXTP_PHY_RST			1
#define MT8192_INFRA_PTP_RST				2

and you will add all further later. This is how all dt-binding headers
are created.

> 
> The implementation is in [1].
> -----
> static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
>  	unsigned int deassert_ofs = deassert ? 0x4 : 0;
>  
>  	return regmap_write(data->regmap,
> 			    data->desc->rst_bank_ofs[id /          
>  					RST_NR_PER_BANK] +
> 			    deassert_ofs,
> 			    BIT(id % RST_NR_PER_BANK));
>  }

Exactly, you hard-code the hardware programming model - register
values/bits/whatever - in the ID, which is not correct. Additionally,
bindings are (mostly) independent of Linux implementation.


Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-28  7:23                 ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-28  7:23 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On 28/04/2022 08:48, Rex-BC Chen wrote:
> On Thu, 2022-04-28 at 14:40 +0800, Krzysztof Kozlowski wrote:
>> On 26/04/2022 10:23, Rex-BC Chen wrote:
>>> On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
>>>> On 25/04/2022 07:01, Rex-BC Chen wrote:
>>>>> On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
>>>>>> On 22/04/2022 08:01, Rex-BC Chen wrote:
>>>>>>> To support reset of infra_ao, add the bit definition for
>>>>>>> thermal/PCIe/SVS.
>>>>>>>
>>>>>>> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>>>>>>> ---
>>>>>>>  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
>>>>>>>  1 file changed, 10 insertions(+)
>>>>>>>
>>>>>>> diff --git a/include/dt-bindings/reset/mt8192-resets.h
>>>>>>> b/include/dt-bindings/reset/mt8192-resets.h
>>>>>>> index be9a7ca245b9..d5f3433175c1 100644
>>>>>>> --- a/include/dt-bindings/reset/mt8192-resets.h
>>>>>>> +++ b/include/dt-bindings/reset/mt8192-resets.h
>>>>>>> @@ -27,4 +27,14 @@
>>>>>>>  
>>>>>>>  #define MT8192_TOPRGU_SW_RST_NUM				
>>>>>>> 23
>>>>>>>  
>>>>>>> +/* INFRA RST0 */
>>>>>>> +#define MT8192_INFRA_RST0_LVTS_AP_RST			
>>>>>>> 	
>>>>>>> 0
>>>>>>> +/* INFRA RST2 */
>>>>>>> +#define MT8192_INFRA_RST2_PCIE_PHY_RST			
>>>>>>> 	
>>>>>>> 15
>>>>>>> +/* INFRA RST3 */
>>>>>>> +#define MT8192_INFRA_RST3_PTP_RST				
>>>>>>> 5
>>>>>>> +/* INFRA RST4 */
>>>>>>> +#define MT8192_INFRA_RST4_LVTS_MCU				
>>>>>>> 12
>>>>>>> +#define MT8192_INFRA_RST4_PCIE_TOP				
>>>>>>> 1
>>>>>>
>>>>>> These should be the IDs of reset, not some register
>>>>>> values/offsets.
>>>>>> Therefore it is expected to have them incremented by 1.
>>>>>>
>>>>>>
>>>>>
>>>>> Hello Krzysztof,
>>>>>
>>>>> This is define bit.
>>>>>
>>>>> There is serveral reset set for infra_ao while it's not serial.
>>>>> For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
>>>>> We are implement #reset-cells = <2>, and we can use this reset
>>>>> drive
>>>>> more easier.
>>>>>
>>>>> For example, in dts, we can define
>>>>> infra_ao: syscon {
>>>>> 	compatible = "mediatek,mt8192-infracfg", "syscon";
>>>>>  	reg = <0 0x10001000 0 0x1000>;
>>>>>  	#clock-cells = <1>;
>>>>> 	#reset-cells = <2>;
>>>>> };
>>>>>
>>>>> thermal {
>>>>> 	...
>>>>> 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
>>>>> 	...
>>>>> };
>>>>>
>>>>> If it's acceptabel, I can update all bit difinition from 0 to
>>>>> 15
>>>>> for
>>>>> all reset set.
>>>>
>>>> Bits are not acceptable, because you embed specific device
>>>> programming
>>>> model (register bits) into the binding.
>>>>
>>>> These should be IDs, so decimal numbers incremented from 0, so:
>>>> #define MT8192_INFRA_RST0_LVTS_AP_RST				
>>>> 0
>>>> #define MT8192_INFRA_RST4_LVTS_MCU				
>>>> 1
>>>> #define MT8192_INFRA_RST4_PCIE_TOP				
>>>> 2
>>>>
>>>> And what is 0x730 in your example? It does not look like ID of a
>>>> reset...
>>>>
>>>> Entire changeset look wrong from DT point of view.
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>
>>> Hello Krzysztof,
>>>
>>> Got it. I will modify them to reset index.
>>> And the dts in my next version would somthing like this:
>>>
>>> ----
>>> #define MT8192_INFRA_THERMAL_CTRL_RST			0
>>> #define MT8192_INFRA_PEXTP_PHY_RST			79
>>> #define MT8192_INFRA_PTP_RST				101
>>> #define MT8192_INFRA_RST4_PCIE_TOP			129
>>> #define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140
>>
>> These are still not IDs, incremented by one.
>>
>> So again from beginning:
>> 0
>> 1
>> 2
>> ...
>>
>> Do not encode hardware register bits into the binding.
>>
>> Best regards,
>> Krzysztof
> 
> Hello Krzysztof,
> 
> It's not bit definiton, and it's index for our reset.
> We have 32*5 reset bits for infra.
> But we only use these 5 index currently, I do not list all of them.

You do not have to list all of them. You can list three, e.g.:

#define MT8192_INFRA_THERMAL_CTRL_RST			0
#define MT8192_INFRA_PEXTP_PHY_RST			1
#define MT8192_INFRA_PTP_RST				2

and you will add all further later. This is how all dt-binding headers
are created.

> 
> The implementation is in [1].
> -----
> static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
>  	unsigned int deassert_ofs = deassert ? 0x4 : 0;
>  
>  	return regmap_write(data->regmap,
> 			    data->desc->rst_bank_ofs[id /          
>  					RST_NR_PER_BANK] +
> 			    deassert_ofs,
> 			    BIT(id % RST_NR_PER_BANK));
>  }

Exactly, you hard-code the hardware programming model - register
values/bits/whatever - in the ID, which is not correct. Additionally,
bindings are (mostly) independent of Linux implementation.


Best regards,
Krzysztof

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-28  7:23                 ` Krzysztof Kozlowski
  0 siblings, 0 replies; 117+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-28  7:23 UTC (permalink / raw)
  To: Rex-BC Chen, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On 28/04/2022 08:48, Rex-BC Chen wrote:
> On Thu, 2022-04-28 at 14:40 +0800, Krzysztof Kozlowski wrote:
>> On 26/04/2022 10:23, Rex-BC Chen wrote:
>>> On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
>>>> On 25/04/2022 07:01, Rex-BC Chen wrote:
>>>>> On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote:
>>>>>> On 22/04/2022 08:01, Rex-BC Chen wrote:
>>>>>>> To support reset of infra_ao, add the bit definition for
>>>>>>> thermal/PCIe/SVS.
>>>>>>>
>>>>>>> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>>>>>>> ---
>>>>>>>  include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++
>>>>>>>  1 file changed, 10 insertions(+)
>>>>>>>
>>>>>>> diff --git a/include/dt-bindings/reset/mt8192-resets.h
>>>>>>> b/include/dt-bindings/reset/mt8192-resets.h
>>>>>>> index be9a7ca245b9..d5f3433175c1 100644
>>>>>>> --- a/include/dt-bindings/reset/mt8192-resets.h
>>>>>>> +++ b/include/dt-bindings/reset/mt8192-resets.h
>>>>>>> @@ -27,4 +27,14 @@
>>>>>>>  
>>>>>>>  #define MT8192_TOPRGU_SW_RST_NUM				
>>>>>>> 23
>>>>>>>  
>>>>>>> +/* INFRA RST0 */
>>>>>>> +#define MT8192_INFRA_RST0_LVTS_AP_RST			
>>>>>>> 	
>>>>>>> 0
>>>>>>> +/* INFRA RST2 */
>>>>>>> +#define MT8192_INFRA_RST2_PCIE_PHY_RST			
>>>>>>> 	
>>>>>>> 15
>>>>>>> +/* INFRA RST3 */
>>>>>>> +#define MT8192_INFRA_RST3_PTP_RST				
>>>>>>> 5
>>>>>>> +/* INFRA RST4 */
>>>>>>> +#define MT8192_INFRA_RST4_LVTS_MCU				
>>>>>>> 12
>>>>>>> +#define MT8192_INFRA_RST4_PCIE_TOP				
>>>>>>> 1
>>>>>>
>>>>>> These should be the IDs of reset, not some register
>>>>>> values/offsets.
>>>>>> Therefore it is expected to have them incremented by 1.
>>>>>>
>>>>>>
>>>>>
>>>>> Hello Krzysztof,
>>>>>
>>>>> This is define bit.
>>>>>
>>>>> There is serveral reset set for infra_ao while it's not serial.
>>>>> For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
>>>>> We are implement #reset-cells = <2>, and we can use this reset
>>>>> drive
>>>>> more easier.
>>>>>
>>>>> For example, in dts, we can define
>>>>> infra_ao: syscon {
>>>>> 	compatible = "mediatek,mt8192-infracfg", "syscon";
>>>>>  	reg = <0 0x10001000 0 0x1000>;
>>>>>  	#clock-cells = <1>;
>>>>> 	#reset-cells = <2>;
>>>>> };
>>>>>
>>>>> thermal {
>>>>> 	...
>>>>> 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
>>>>> 	...
>>>>> };
>>>>>
>>>>> If it's acceptabel, I can update all bit difinition from 0 to
>>>>> 15
>>>>> for
>>>>> all reset set.
>>>>
>>>> Bits are not acceptable, because you embed specific device
>>>> programming
>>>> model (register bits) into the binding.
>>>>
>>>> These should be IDs, so decimal numbers incremented from 0, so:
>>>> #define MT8192_INFRA_RST0_LVTS_AP_RST				
>>>> 0
>>>> #define MT8192_INFRA_RST4_LVTS_MCU				
>>>> 1
>>>> #define MT8192_INFRA_RST4_PCIE_TOP				
>>>> 2
>>>>
>>>> And what is 0x730 in your example? It does not look like ID of a
>>>> reset...
>>>>
>>>> Entire changeset look wrong from DT point of view.
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>
>>> Hello Krzysztof,
>>>
>>> Got it. I will modify them to reset index.
>>> And the dts in my next version would somthing like this:
>>>
>>> ----
>>> #define MT8192_INFRA_THERMAL_CTRL_RST			0
>>> #define MT8192_INFRA_PEXTP_PHY_RST			79
>>> #define MT8192_INFRA_PTP_RST				101
>>> #define MT8192_INFRA_RST4_PCIE_TOP			129
>>> #define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140
>>
>> These are still not IDs, incremented by one.
>>
>> So again from beginning:
>> 0
>> 1
>> 2
>> ...
>>
>> Do not encode hardware register bits into the binding.
>>
>> Best regards,
>> Krzysztof
> 
> Hello Krzysztof,
> 
> It's not bit definiton, and it's index for our reset.
> We have 32*5 reset bits for infra.
> But we only use these 5 index currently, I do not list all of them.

You do not have to list all of them. You can list three, e.g.:

#define MT8192_INFRA_THERMAL_CTRL_RST			0
#define MT8192_INFRA_PEXTP_PHY_RST			1
#define MT8192_INFRA_PTP_RST				2

and you will add all further later. This is how all dt-binding headers
are created.

> 
> The implementation is in [1].
> -----
> static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
>  	unsigned int deassert_ofs = deassert ? 0x4 : 0;
>  
>  	return regmap_write(data->regmap,
> 			    data->desc->rst_bank_ofs[id /          
>  					RST_NR_PER_BANK] +
> 			    deassert_ofs,
> 			    BIT(id % RST_NR_PER_BANK));
>  }

Exactly, you hard-code the hardware programming model - register
values/bits/whatever - in the ID, which is not correct. Additionally,
bindings are (mostly) independent of Linux implementation.


Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
  2022-04-28  7:23                 ` Krzysztof Kozlowski
  (?)
@ 2022-04-28  7:36                   ` Rex-BC Chen
  -1 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-28  7:36 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Thu, 2022-04-28 at 15:23 +0800, Krzysztof Kozlowski wrote:
> On 28/04/2022 08:48, Rex-BC Chen wrote:
> > On Thu, 2022-04-28 at 14:40 +0800, Krzysztof Kozlowski wrote:
> > > On 26/04/2022 10:23, Rex-BC Chen wrote:
> > > > On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
> > > > > On 25/04/2022 07:01, Rex-BC Chen wrote:
> > > > > > On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski
> > > > > > wrote:
> > > > > > > On 22/04/2022 08:01, Rex-BC Chen wrote:
> > > > > > > > To support reset of infra_ao, add the bit definition
> > > > > > > > for
> > > > > > > > thermal/PCIe/SVS.
> > > > > > > > 
> > > > > > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > > > > > > > ---
> > > > > > > >  include/dt-bindings/reset/mt8192-resets.h | 10
> > > > > > > > ++++++++++
> > > > > > > >  1 file changed, 10 insertions(+)
> > > > > > > > 
> > > > > > > > diff --git a/include/dt-bindings/reset/mt8192-resets.h
> > > > > > > > b/include/dt-bindings/reset/mt8192-resets.h
> > > > > > > > index be9a7ca245b9..d5f3433175c1 100644
> > > > > > > > --- a/include/dt-bindings/reset/mt8192-resets.h
> > > > > > > > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > > > > > > > @@ -27,4 +27,14 @@
> > > > > > > >  
> > > > > > > >  #define MT8192_TOPRGU_SW_RST_NUM			
> > > > > > > > 	
> > > > > > > > 23
> > > > > > > >  
> > > > > > > > +/* INFRA RST0 */
> > > > > > > > +#define MT8192_INFRA_RST0_LVTS_AP_RST			
> > > > > > > > 	
> > > > > > > > 0
> > > > > > > > +/* INFRA RST2 */
> > > > > > > > +#define MT8192_INFRA_RST2_PCIE_PHY_RST			
> > > > > > > > 	
> > > > > > > > 15
> > > > > > > > +/* INFRA RST3 */
> > > > > > > > +#define MT8192_INFRA_RST3_PTP_RST			
> > > > > > > > 	
> > > > > > > > 5
> > > > > > > > +/* INFRA RST4 */
> > > > > > > > +#define MT8192_INFRA_RST4_LVTS_MCU			
> > > > > > > > 	
> > > > > > > > 12
> > > > > > > > +#define MT8192_INFRA_RST4_PCIE_TOP			
> > > > > > > > 	
> > > > > > > > 1
> > > > > > > 
> > > > > > > These should be the IDs of reset, not some register
> > > > > > > values/offsets.
> > > > > > > Therefore it is expected to have them incremented by 1.
> > > > > > > 
> > > > > > > 
> > > > > > 
> > > > > > Hello Krzysztof,
> > > > > > 
> > > > > > This is define bit.
> > > > > > 
> > > > > > There is serveral reset set for infra_ao while it's not
> > > > > > serial.
> > > > > > For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
> > > > > > We are implement #reset-cells = <2>, and we can use this
> > > > > > reset
> > > > > > drive
> > > > > > more easier.
> > > > > > 
> > > > > > For example, in dts, we can define
> > > > > > infra_ao: syscon {
> > > > > > 	compatible = "mediatek,mt8192-infracfg", "syscon";
> > > > > >  	reg = <0 0x10001000 0 0x1000>;
> > > > > >  	#clock-cells = <1>;
> > > > > > 	#reset-cells = <2>;
> > > > > > };
> > > > > > 
> > > > > > thermal {
> > > > > > 	...
> > > > > > 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
> > > > > > 	...
> > > > > > };
> > > > > > 
> > > > > > If it's acceptabel, I can update all bit difinition from 0
> > > > > > to
> > > > > > 15
> > > > > > for
> > > > > > all reset set.
> > > > > 
> > > > > Bits are not acceptable, because you embed specific device
> > > > > programming
> > > > > model (register bits) into the binding.
> > > > > 
> > > > > These should be IDs, so decimal numbers incremented from 0,
> > > > > so:
> > > > > #define MT8192_INFRA_RST0_LVTS_AP_RST				
> > > > > 0
> > > > > #define MT8192_INFRA_RST4_LVTS_MCU				
> > > > > 1
> > > > > #define MT8192_INFRA_RST4_PCIE_TOP				
> > > > > 2
> > > > > 
> > > > > And what is 0x730 in your example? It does not look like ID
> > > > > of a
> > > > > reset...
> > > > > 
> > > > > Entire changeset look wrong from DT point of view.
> > > > > 
> > > > > Best regards,
> > > > > Krzysztof
> > > > 
> > > > Hello Krzysztof,
> > > > 
> > > > Got it. I will modify them to reset index.
> > > > And the dts in my next version would somthing like this:
> > > > 
> > > > ----
> > > > #define MT8192_INFRA_THERMAL_CTRL_RST			0
> > > > #define MT8192_INFRA_PEXTP_PHY_RST			79
> > > > #define MT8192_INFRA_PTP_RST				101
> > > > #define MT8192_INFRA_RST4_PCIE_TOP			129
> > > > #define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140
> > > 
> > > These are still not IDs, incremented by one.
> > > 
> > > So again from beginning:
> > > 0
> > > 1
> > > 2
> > > ...
> > > 
> > > Do not encode hardware register bits into the binding.
> > > 
> > > Best regards,
> > > Krzysztof
> > 
> > Hello Krzysztof,
> > 
> > It's not bit definiton, and it's index for our reset.
> > We have 32*5 reset bits for infra.
> > But we only use these 5 index currently, I do not list all of them.
> 
> You do not have to list all of them. You can list three, e.g.:
> 
> #define MT8192_INFRA_THERMAL_CTRL_RST			0
> #define MT8192_INFRA_PEXTP_PHY_RST			1
> #define MT8192_INFRA_PTP_RST				2
> 
> and you will add all further later. This is how all dt-binding
> headers
> are created.
> 
> > 
> > The implementation is in [1].
> > -----
> > static int mtk_reset_update_set_clr(struct reset_controller_dev
> > *rcdev,
> >  	unsigned int deassert_ofs = deassert ? 0x4 : 0;
> >  
> >  	return regmap_write(data->regmap,
> > 			    data->desc->rst_bank_ofs[id /          
> >  					RST_NR_PER_BANK] +
> > 			    deassert_ofs,
> > 			    BIT(id % RST_NR_PER_BANK));
> >  }
> 
> Exactly, you hard-code the hardware programming model - register
> values/bits/whatever - in the ID, which is not correct. Additionally,
> bindings are (mostly) independent of Linux implementation.
> 
> 
> Best regards,
> Krzysztof

Hello Krzysztof,

The rest bits could be used in the future.
I am not sure who will use them.
I will list all 5*32 index in next version.

BRs,
Rex


^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-28  7:36                   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-28  7:36 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Thu, 2022-04-28 at 15:23 +0800, Krzysztof Kozlowski wrote:
> On 28/04/2022 08:48, Rex-BC Chen wrote:
> > On Thu, 2022-04-28 at 14:40 +0800, Krzysztof Kozlowski wrote:
> > > On 26/04/2022 10:23, Rex-BC Chen wrote:
> > > > On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
> > > > > On 25/04/2022 07:01, Rex-BC Chen wrote:
> > > > > > On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski
> > > > > > wrote:
> > > > > > > On 22/04/2022 08:01, Rex-BC Chen wrote:
> > > > > > > > To support reset of infra_ao, add the bit definition
> > > > > > > > for
> > > > > > > > thermal/PCIe/SVS.
> > > > > > > > 
> > > > > > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > > > > > > > ---
> > > > > > > >  include/dt-bindings/reset/mt8192-resets.h | 10
> > > > > > > > ++++++++++
> > > > > > > >  1 file changed, 10 insertions(+)
> > > > > > > > 
> > > > > > > > diff --git a/include/dt-bindings/reset/mt8192-resets.h
> > > > > > > > b/include/dt-bindings/reset/mt8192-resets.h
> > > > > > > > index be9a7ca245b9..d5f3433175c1 100644
> > > > > > > > --- a/include/dt-bindings/reset/mt8192-resets.h
> > > > > > > > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > > > > > > > @@ -27,4 +27,14 @@
> > > > > > > >  
> > > > > > > >  #define MT8192_TOPRGU_SW_RST_NUM			
> > > > > > > > 	
> > > > > > > > 23
> > > > > > > >  
> > > > > > > > +/* INFRA RST0 */
> > > > > > > > +#define MT8192_INFRA_RST0_LVTS_AP_RST			
> > > > > > > > 	
> > > > > > > > 0
> > > > > > > > +/* INFRA RST2 */
> > > > > > > > +#define MT8192_INFRA_RST2_PCIE_PHY_RST			
> > > > > > > > 	
> > > > > > > > 15
> > > > > > > > +/* INFRA RST3 */
> > > > > > > > +#define MT8192_INFRA_RST3_PTP_RST			
> > > > > > > > 	
> > > > > > > > 5
> > > > > > > > +/* INFRA RST4 */
> > > > > > > > +#define MT8192_INFRA_RST4_LVTS_MCU			
> > > > > > > > 	
> > > > > > > > 12
> > > > > > > > +#define MT8192_INFRA_RST4_PCIE_TOP			
> > > > > > > > 	
> > > > > > > > 1
> > > > > > > 
> > > > > > > These should be the IDs of reset, not some register
> > > > > > > values/offsets.
> > > > > > > Therefore it is expected to have them incremented by 1.
> > > > > > > 
> > > > > > > 
> > > > > > 
> > > > > > Hello Krzysztof,
> > > > > > 
> > > > > > This is define bit.
> > > > > > 
> > > > > > There is serveral reset set for infra_ao while it's not
> > > > > > serial.
> > > > > > For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
> > > > > > We are implement #reset-cells = <2>, and we can use this
> > > > > > reset
> > > > > > drive
> > > > > > more easier.
> > > > > > 
> > > > > > For example, in dts, we can define
> > > > > > infra_ao: syscon {
> > > > > > 	compatible = "mediatek,mt8192-infracfg", "syscon";
> > > > > >  	reg = <0 0x10001000 0 0x1000>;
> > > > > >  	#clock-cells = <1>;
> > > > > > 	#reset-cells = <2>;
> > > > > > };
> > > > > > 
> > > > > > thermal {
> > > > > > 	...
> > > > > > 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
> > > > > > 	...
> > > > > > };
> > > > > > 
> > > > > > If it's acceptabel, I can update all bit difinition from 0
> > > > > > to
> > > > > > 15
> > > > > > for
> > > > > > all reset set.
> > > > > 
> > > > > Bits are not acceptable, because you embed specific device
> > > > > programming
> > > > > model (register bits) into the binding.
> > > > > 
> > > > > These should be IDs, so decimal numbers incremented from 0,
> > > > > so:
> > > > > #define MT8192_INFRA_RST0_LVTS_AP_RST				
> > > > > 0
> > > > > #define MT8192_INFRA_RST4_LVTS_MCU				
> > > > > 1
> > > > > #define MT8192_INFRA_RST4_PCIE_TOP				
> > > > > 2
> > > > > 
> > > > > And what is 0x730 in your example? It does not look like ID
> > > > > of a
> > > > > reset...
> > > > > 
> > > > > Entire changeset look wrong from DT point of view.
> > > > > 
> > > > > Best regards,
> > > > > Krzysztof
> > > > 
> > > > Hello Krzysztof,
> > > > 
> > > > Got it. I will modify them to reset index.
> > > > And the dts in my next version would somthing like this:
> > > > 
> > > > ----
> > > > #define MT8192_INFRA_THERMAL_CTRL_RST			0
> > > > #define MT8192_INFRA_PEXTP_PHY_RST			79
> > > > #define MT8192_INFRA_PTP_RST				101
> > > > #define MT8192_INFRA_RST4_PCIE_TOP			129
> > > > #define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140
> > > 
> > > These are still not IDs, incremented by one.
> > > 
> > > So again from beginning:
> > > 0
> > > 1
> > > 2
> > > ...
> > > 
> > > Do not encode hardware register bits into the binding.
> > > 
> > > Best regards,
> > > Krzysztof
> > 
> > Hello Krzysztof,
> > 
> > It's not bit definiton, and it's index for our reset.
> > We have 32*5 reset bits for infra.
> > But we only use these 5 index currently, I do not list all of them.
> 
> You do not have to list all of them. You can list three, e.g.:
> 
> #define MT8192_INFRA_THERMAL_CTRL_RST			0
> #define MT8192_INFRA_PEXTP_PHY_RST			1
> #define MT8192_INFRA_PTP_RST				2
> 
> and you will add all further later. This is how all dt-binding
> headers
> are created.
> 
> > 
> > The implementation is in [1].
> > -----
> > static int mtk_reset_update_set_clr(struct reset_controller_dev
> > *rcdev,
> >  	unsigned int deassert_ofs = deassert ? 0x4 : 0;
> >  
> >  	return regmap_write(data->regmap,
> > 			    data->desc->rst_bank_ofs[id /          
> >  					RST_NR_PER_BANK] +
> > 			    deassert_ofs,
> > 			    BIT(id % RST_NR_PER_BANK));
> >  }
> 
> Exactly, you hard-code the hardware programming model - register
> values/bits/whatever - in the ID, which is not correct. Additionally,
> bindings are (mostly) independent of Linux implementation.
> 
> 
> Best regards,
> Krzysztof

Hello Krzysztof,

The rest bits could be used in the future.
I am not sure who will use them.
I will list all 5*32 index in next version.

BRs,
Rex


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 117+ messages in thread

* Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit
@ 2022-04-28  7:36                   ` Rex-BC Chen
  0 siblings, 0 replies; 117+ messages in thread
From: Rex-BC Chen @ 2022-04-28  7:36 UTC (permalink / raw)
  To: Krzysztof Kozlowski, mturquette, sboyd, matthias.bgg, robh+dt,
	krzysztof.kozlowski+dt
  Cc: p.zabel, angelogioacchino.delregno,
	Chun-Jie Chen (陳浚桀),
	wenst, Runyang Chen (陈润洋),
	linux-kernel, devicetree, linux-clk, linux-arm-kernel,
	linux-mediatek, Project_Global_Chrome_Upstream_Group

On Thu, 2022-04-28 at 15:23 +0800, Krzysztof Kozlowski wrote:
> On 28/04/2022 08:48, Rex-BC Chen wrote:
> > On Thu, 2022-04-28 at 14:40 +0800, Krzysztof Kozlowski wrote:
> > > On 26/04/2022 10:23, Rex-BC Chen wrote:
> > > > On Mon, 2022-04-25 at 15:52 +0800, Krzysztof Kozlowski wrote:
> > > > > On 25/04/2022 07:01, Rex-BC Chen wrote:
> > > > > > On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski
> > > > > > wrote:
> > > > > > > On 22/04/2022 08:01, Rex-BC Chen wrote:
> > > > > > > > To support reset of infra_ao, add the bit definition
> > > > > > > > for
> > > > > > > > thermal/PCIe/SVS.
> > > > > > > > 
> > > > > > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > > > > > > > ---
> > > > > > > >  include/dt-bindings/reset/mt8192-resets.h | 10
> > > > > > > > ++++++++++
> > > > > > > >  1 file changed, 10 insertions(+)
> > > > > > > > 
> > > > > > > > diff --git a/include/dt-bindings/reset/mt8192-resets.h
> > > > > > > > b/include/dt-bindings/reset/mt8192-resets.h
> > > > > > > > index be9a7ca245b9..d5f3433175c1 100644
> > > > > > > > --- a/include/dt-bindings/reset/mt8192-resets.h
> > > > > > > > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > > > > > > > @@ -27,4 +27,14 @@
> > > > > > > >  
> > > > > > > >  #define MT8192_TOPRGU_SW_RST_NUM			
> > > > > > > > 	
> > > > > > > > 23
> > > > > > > >  
> > > > > > > > +/* INFRA RST0 */
> > > > > > > > +#define MT8192_INFRA_RST0_LVTS_AP_RST			
> > > > > > > > 	
> > > > > > > > 0
> > > > > > > > +/* INFRA RST2 */
> > > > > > > > +#define MT8192_INFRA_RST2_PCIE_PHY_RST			
> > > > > > > > 	
> > > > > > > > 15
> > > > > > > > +/* INFRA RST3 */
> > > > > > > > +#define MT8192_INFRA_RST3_PTP_RST			
> > > > > > > > 	
> > > > > > > > 5
> > > > > > > > +/* INFRA RST4 */
> > > > > > > > +#define MT8192_INFRA_RST4_LVTS_MCU			
> > > > > > > > 	
> > > > > > > > 12
> > > > > > > > +#define MT8192_INFRA_RST4_PCIE_TOP			
> > > > > > > > 	
> > > > > > > > 1
> > > > > > > 
> > > > > > > These should be the IDs of reset, not some register
> > > > > > > values/offsets.
> > > > > > > Therefore it is expected to have them incremented by 1.
> > > > > > > 
> > > > > > > 
> > > > > > 
> > > > > > Hello Krzysztof,
> > > > > > 
> > > > > > This is define bit.
> > > > > > 
> > > > > > There is serveral reset set for infra_ao while it's not
> > > > > > serial.
> > > > > > For MT8192, it's 0x120/0x130/0x140/0x150/0x730.
> > > > > > We are implement #reset-cells = <2>, and we can use this
> > > > > > reset
> > > > > > drive
> > > > > > more easier.
> > > > > > 
> > > > > > For example, in dts, we can define
> > > > > > infra_ao: syscon {
> > > > > > 	compatible = "mediatek,mt8192-infracfg", "syscon";
> > > > > >  	reg = <0 0x10001000 0 0x1000>;
> > > > > >  	#clock-cells = <1>;
> > > > > > 	#reset-cells = <2>;
> > > > > > };
> > > > > > 
> > > > > > thermal {
> > > > > > 	...
> > > > > > 	resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>;
> > > > > > 	...
> > > > > > };
> > > > > > 
> > > > > > If it's acceptabel, I can update all bit difinition from 0
> > > > > > to
> > > > > > 15
> > > > > > for
> > > > > > all reset set.
> > > > > 
> > > > > Bits are not acceptable, because you embed specific device
> > > > > programming
> > > > > model (register bits) into the binding.
> > > > > 
> > > > > These should be IDs, so decimal numbers incremented from 0,
> > > > > so:
> > > > > #define MT8192_INFRA_RST0_LVTS_AP_RST				
> > > > > 0
> > > > > #define MT8192_INFRA_RST4_LVTS_MCU				
> > > > > 1
> > > > > #define MT8192_INFRA_RST4_PCIE_TOP				
> > > > > 2
> > > > > 
> > > > > And what is 0x730 in your example? It does not look like ID
> > > > > of a
> > > > > reset...
> > > > > 
> > > > > Entire changeset look wrong from DT point of view.
> > > > > 
> > > > > Best regards,
> > > > > Krzysztof
> > > > 
> > > > Hello Krzysztof,
> > > > 
> > > > Got it. I will modify them to reset index.
> > > > And the dts in my next version would somthing like this:
> > > > 
> > > > ----
> > > > #define MT8192_INFRA_THERMAL_CTRL_RST			0
> > > > #define MT8192_INFRA_PEXTP_PHY_RST			79
> > > > #define MT8192_INFRA_PTP_RST				101
> > > > #define MT8192_INFRA_RST4_PCIE_TOP			129
> > > > #define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140
> > > 
> > > These are still not IDs, incremented by one.
> > > 
> > > So again from beginning:
> > > 0
> > > 1
> > > 2
> > > ...
> > > 
> > > Do not encode hardware register bits into the binding.
> > > 
> > > Best regards,
> > > Krzysztof
> > 
> > Hello Krzysztof,
> > 
> > It's not bit definiton, and it's index for our reset.
> > We have 32*5 reset bits for infra.
> > But we only use these 5 index currently, I do not list all of them.
> 
> You do not have to list all of them. You can list three, e.g.:
> 
> #define MT8192_INFRA_THERMAL_CTRL_RST			0
> #define MT8192_INFRA_PEXTP_PHY_RST			1
> #define MT8192_INFRA_PTP_RST				2
> 
> and you will add all further later. This is how all dt-binding
> headers
> are created.
> 
> > 
> > The implementation is in [1].
> > -----
> > static int mtk_reset_update_set_clr(struct reset_controller_dev
> > *rcdev,
> >  	unsigned int deassert_ofs = deassert ? 0x4 : 0;
> >  
> >  	return regmap_write(data->regmap,
> > 			    data->desc->rst_bank_ofs[id /          
> >  					RST_NR_PER_BANK] +
> > 			    deassert_ofs,
> > 			    BIT(id % RST_NR_PER_BANK));
> >  }
> 
> Exactly, you hard-code the hardware programming model - register
> values/bits/whatever - in the ID, which is not correct. Additionally,
> bindings are (mostly) independent of Linux implementation.
> 
> 
> Best regards,
> Krzysztof

Hello Krzysztof,

The rest bits could be used in the future.
I am not sure who will use them.
I will list all 5*32 index in next version.

BRs,
Rex


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^ permalink raw reply	[flat|nested] 117+ messages in thread

end of thread, other threads:[~2022-04-28  7:37 UTC | newest]

Thread overview: 117+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-22  6:01 [PATCH V3 00/17] Cleanup MediaTek clk reset drivers and support MT8192/MT8195 Rex-BC Chen
2022-04-22  6:01 ` Rex-BC Chen
2022-04-22  6:01 ` Rex-BC Chen
2022-04-22  6:01 ` [PATCH V3 01/17] clk: mediatek: reset: Add reset.h Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-26  9:33   ` AngeloGioacchino Del Regno
2022-04-26  9:33     ` AngeloGioacchino Del Regno
2022-04-26  9:33     ` AngeloGioacchino Del Regno
2022-04-22  6:01 ` [PATCH V3 02/17] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01 ` [PATCH V3 03/17] clk: mediatek: reset: Refine and reorder functions in reset.c Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-26  9:34   ` AngeloGioacchino Del Regno
2022-04-26  9:34     ` AngeloGioacchino Del Regno
2022-04-26  9:34     ` AngeloGioacchino Del Regno
2022-04-22  6:01 ` [PATCH V3 04/17] clk: mediatek: reset: Extract common drivers to update function Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-26  9:34   ` AngeloGioacchino Del Regno
2022-04-26  9:34     ` AngeloGioacchino Del Regno
2022-04-26  9:34     ` AngeloGioacchino Del Regno
2022-04-22  6:01 ` [PATCH V3 05/17] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-26  9:34   ` AngeloGioacchino Del Regno
2022-04-26  9:34     ` AngeloGioacchino Del Regno
2022-04-26  9:34     ` AngeloGioacchino Del Regno
2022-04-22  6:01 ` [PATCH V3 06/17] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-26  9:34   ` AngeloGioacchino Del Regno
2022-04-26  9:34     ` AngeloGioacchino Del Regno
2022-04-26  9:34     ` AngeloGioacchino Del Regno
2022-04-22  6:01 ` [PATCH V3 07/17] clk: mediatek: reset: Add return for clock reset register function Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-26  9:34   ` AngeloGioacchino Del Regno
2022-04-26  9:34     ` AngeloGioacchino Del Regno
2022-04-26  9:34     ` AngeloGioacchino Del Regno
2022-04-22  6:01 ` [PATCH V3 08/17] clk: mediatek: reset: Add new register reset function with device Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-26  9:34   ` AngeloGioacchino Del Regno
2022-04-26  9:34     ` AngeloGioacchino Del Regno
2022-04-26  9:34     ` AngeloGioacchino Del Regno
2022-04-22  6:01 ` [PATCH V3 09/17] clk: mediatek: reset: Add support for input offset and bit from DT Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01 ` [PATCH V3 10/17] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01 ` [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-23 10:27   ` Krzysztof Kozlowski
2022-04-23 10:27     ` Krzysztof Kozlowski
2022-04-23 10:27     ` Krzysztof Kozlowski
2022-04-25  2:37     ` Rex-BC Chen
2022-04-25  2:37       ` Rex-BC Chen
2022-04-25  2:37       ` Rex-BC Chen
2022-04-25  7:44       ` Krzysztof Kozlowski
2022-04-25  7:44         ` Krzysztof Kozlowski
2022-04-25  7:44         ` Krzysztof Kozlowski
2022-04-26  8:24         ` Rex-BC Chen
2022-04-26  8:24           ` Rex-BC Chen
2022-04-26  8:24           ` Rex-BC Chen
2022-04-22  6:01 ` [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-23 10:28   ` Krzysztof Kozlowski
2022-04-23 10:28     ` Krzysztof Kozlowski
2022-04-23 10:28     ` Krzysztof Kozlowski
2022-04-25  5:01     ` Rex-BC Chen
2022-04-25  5:01       ` Rex-BC Chen
2022-04-25  5:01       ` Rex-BC Chen
2022-04-25  7:52       ` Krzysztof Kozlowski
2022-04-25  7:52         ` Krzysztof Kozlowski
2022-04-25  7:52         ` Krzysztof Kozlowski
2022-04-26  8:23         ` Rex-BC Chen
2022-04-26  8:23           ` Rex-BC Chen
2022-04-26  8:23           ` Rex-BC Chen
2022-04-28  6:40           ` Krzysztof Kozlowski
2022-04-28  6:40             ` Krzysztof Kozlowski
2022-04-28  6:40             ` Krzysztof Kozlowski
2022-04-28  6:48             ` Rex-BC Chen
2022-04-28  6:48               ` Rex-BC Chen
2022-04-28  6:48               ` Rex-BC Chen
2022-04-28  7:23               ` Krzysztof Kozlowski
2022-04-28  7:23                 ` Krzysztof Kozlowski
2022-04-28  7:23                 ` Krzysztof Kozlowski
2022-04-28  7:36                 ` Rex-BC Chen
2022-04-28  7:36                   ` Rex-BC Chen
2022-04-28  7:36                   ` Rex-BC Chen
2022-04-22  6:01 ` [PATCH V3 13/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8195-sys-clock Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-23 10:28   ` Krzysztof Kozlowski
2022-04-23 10:28     ` Krzysztof Kozlowski
2022-04-23 10:28     ` Krzysztof Kozlowski
2022-04-22  6:01 ` [PATCH V3 14/17] dt-binding: mt8195: Add infra_ao reset bit Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-23 10:29   ` Krzysztof Kozlowski
2022-04-23 10:29     ` Krzysztof Kozlowski
2022-04-23 10:29     ` Krzysztof Kozlowski
2022-04-22  6:01 ` [PATCH V3 15/17] clk: mediatek: reset: Add infra_ao reset support for MT8192 Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01 ` [PATCH V3 16/17] clk: mediatek: reset: Add infra_ao reset support for MT8195 Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01 ` [PATCH V3 17/17] arm64: dts: mediatek: Add infra #reset-cells property for MT8192 Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen
2022-04-22  6:01   ` Rex-BC Chen

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