[PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Heiko Stuebner]

Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
for things like non-cacheable pages or I/O memory pages.


So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
types) using the alternatives framework.

This includes a number of changes to the alternatives mechanism itself.
The biggest one being the move to a more central location, as I expect
in the future, nearly every chip needing some sort of patching, be it
either for erratas or for optional features (svpbmt or others).

Detection of the svpbmt functionality is done via Atish's isa extension
handling series [0] and thus does not need any dt-parsing of its own
anymore.

The series also introduces support for the memory types of the D1
which are implemented differently to svpbmt. But when patching anyway
it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
location.

The only slightly bigger difference is that the "normal" type is not 0
as with svpbmt, so kernel patches for this PMA type need to be applied
even before the MMU is brought up, so the series introduces a separate
stage for that.


In theory this series is 3 parts:
- sbi cache-flush / null-ptr
- alternatives improvements
- svpbmt+d1

So expecially patches from the first 2 areas could be applied when
deemed ready, I just thought to keep it together to show-case where
the end-goal is and not requiring jumping between different series.


I picked the recipient list from the previous versions, hopefully
I didn't forget anybody.

changes in v7:
- fix typo in patch1 (Atish)
- moved to Atish's isa-extension framework
- and therefore move regular boot-alternatives directly behind fill_hwcaps
- change T-Head errata Kconfig text (Atish)

changes in v6:
- rebase onto 5.17-rc1
- handle sbi null-ptr differently
- improve commit messages
- use riscv,mmu as property name

changes in v5:
- move to use alternatives for runtime-patching
- add D1 variant


[0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com


Heiko Stuebner (12):
  riscv: prevent null-pointer dereference with sbi_remote_fence_i
  riscv: integrate alternatives better into the main architecture
  riscv: allow different stages with alternatives
  riscv: implement module alternatives
  riscv: implement ALTERNATIVE_2 macro
  riscv: extend concatenated alternatives-lines to the same length
  riscv: prevent compressed instructions in alternatives
  riscv: move boot alternatives to after fill_hwcap
  riscv: Fix accessing pfn bits in PTEs for non-32bit variants
  riscv: add cpufeature handling via alternatives
  riscv: remove FIXMAP_PAGE_IO and fall back to its default value
  riscv: add memory-type errata for T-Head

Wei Fu (1):
  riscv: add RISC-V Svpbmt extension support

 arch/riscv/Kconfig.erratas                  |  29 +++--
 arch/riscv/Kconfig.socs                     |   1 -
 arch/riscv/Makefile                         |   2 +-
 arch/riscv/errata/Makefile                  |   2 +-
 arch/riscv/errata/sifive/errata.c           |  17 ++-
 arch/riscv/errata/thead/Makefile            |   1 +
 arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
 arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
 arch/riscv/include/asm/alternative.h        |  16 ++-
 arch/riscv/include/asm/errata_list.h        |  52 +++++++++
 arch/riscv/include/asm/fixmap.h             |   2 -
 arch/riscv/include/asm/hwcap.h              |   1 +
 arch/riscv/include/asm/pgtable-32.h         |  17 +++
 arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
 arch/riscv/include/asm/pgtable-bits.h       |  10 --
 arch/riscv/include/asm/pgtable.h            |  53 +++++++--
 arch/riscv/include/asm/vendorid_list.h      |   1 +
 arch/riscv/kernel/Makefile                  |   1 +
 arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
 arch/riscv/kernel/cpu.c                     |   1 +
 arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
 arch/riscv/kernel/module.c                  |  29 +++++
 arch/riscv/kernel/sbi.c                     |  10 +-
 arch/riscv/kernel/setup.c                   |   2 +
 arch/riscv/kernel/smpboot.c                 |   4 -
 arch/riscv/kernel/traps.c                   |   2 +-
 arch/riscv/mm/init.c                        |   1 +
 27 files changed, 546 insertions(+), 114 deletions(-)
 create mode 100644 arch/riscv/errata/thead/Makefile
 create mode 100644 arch/riscv/errata/thead/errata.c
 rename arch/riscv/{errata => kernel}/alternative.c (59%)

-- 
2.30.2

[PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Heiko Stuebner]

Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
for things like non-cacheable pages or I/O memory pages.


So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
types) using the alternatives framework.

This includes a number of changes to the alternatives mechanism itself.
The biggest one being the move to a more central location, as I expect
in the future, nearly every chip needing some sort of patching, be it
either for erratas or for optional features (svpbmt or others).

Detection of the svpbmt functionality is done via Atish's isa extension
handling series [0] and thus does not need any dt-parsing of its own
anymore.

The series also introduces support for the memory types of the D1
which are implemented differently to svpbmt. But when patching anyway
it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
location.

The only slightly bigger difference is that the "normal" type is not 0
as with svpbmt, so kernel patches for this PMA type need to be applied
even before the MMU is brought up, so the series introduces a separate
stage for that.


In theory this series is 3 parts:
- sbi cache-flush / null-ptr
- alternatives improvements
- svpbmt+d1

So expecially patches from the first 2 areas could be applied when
deemed ready, I just thought to keep it together to show-case where
the end-goal is and not requiring jumping between different series.


I picked the recipient list from the previous versions, hopefully
I didn't forget anybody.

changes in v7:
- fix typo in patch1 (Atish)
- moved to Atish's isa-extension framework
- and therefore move regular boot-alternatives directly behind fill_hwcaps
- change T-Head errata Kconfig text (Atish)

changes in v6:
- rebase onto 5.17-rc1
- handle sbi null-ptr differently
- improve commit messages
- use riscv,mmu as property name

changes in v5:
- move to use alternatives for runtime-patching
- add D1 variant


[0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com


Heiko Stuebner (12):
  riscv: prevent null-pointer dereference with sbi_remote_fence_i
  riscv: integrate alternatives better into the main architecture
  riscv: allow different stages with alternatives
  riscv: implement module alternatives
  riscv: implement ALTERNATIVE_2 macro
  riscv: extend concatenated alternatives-lines to the same length
  riscv: prevent compressed instructions in alternatives
  riscv: move boot alternatives to after fill_hwcap
  riscv: Fix accessing pfn bits in PTEs for non-32bit variants
  riscv: add cpufeature handling via alternatives
  riscv: remove FIXMAP_PAGE_IO and fall back to its default value
  riscv: add memory-type errata for T-Head

Wei Fu (1):
  riscv: add RISC-V Svpbmt extension support

 arch/riscv/Kconfig.erratas                  |  29 +++--
 arch/riscv/Kconfig.socs                     |   1 -
 arch/riscv/Makefile                         |   2 +-
 arch/riscv/errata/Makefile                  |   2 +-
 arch/riscv/errata/sifive/errata.c           |  17 ++-
 arch/riscv/errata/thead/Makefile            |   1 +
 arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
 arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
 arch/riscv/include/asm/alternative.h        |  16 ++-
 arch/riscv/include/asm/errata_list.h        |  52 +++++++++
 arch/riscv/include/asm/fixmap.h             |   2 -
 arch/riscv/include/asm/hwcap.h              |   1 +
 arch/riscv/include/asm/pgtable-32.h         |  17 +++
 arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
 arch/riscv/include/asm/pgtable-bits.h       |  10 --
 arch/riscv/include/asm/pgtable.h            |  53 +++++++--
 arch/riscv/include/asm/vendorid_list.h      |   1 +
 arch/riscv/kernel/Makefile                  |   1 +
 arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
 arch/riscv/kernel/cpu.c                     |   1 +
 arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
 arch/riscv/kernel/module.c                  |  29 +++++
 arch/riscv/kernel/sbi.c                     |  10 +-
 arch/riscv/kernel/setup.c                   |   2 +
 arch/riscv/kernel/smpboot.c                 |   4 -
 arch/riscv/kernel/traps.c                   |   2 +-
 arch/riscv/mm/init.c                        |   1 +
 27 files changed, 546 insertions(+), 114 deletions(-)
 create mode 100644 arch/riscv/errata/thead/Makefile
 create mode 100644 arch/riscv/errata/thead/errata.c
 rename arch/riscv/{errata => kernel}/alternative.c (59%)

-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 01/13] riscv: prevent null-pointer dereference with sbi_remote_fence_i

[Heiko Stuebner]

The callback used inside sbi_remote_fence_i is set at sbi probe time
to the needed variant. Before that it is a NULL pointer.

Some users like the flush_icache_*() functions suggest a generic
functionality, that doesn't depend on a specific boot-stage but
uses sbi_remote_fence_i as one option to flush other cpu cores.

So they definitely shouldn't run into null-pointer dereference
issues when called "too early" during boot.

So introduce an empty function to be the standard for the __sbi_rfence
function pointer until sbi_init has run.

Users of sbi_remote_fence_i will have separate code for the local
cpu and sbi_init() is called before other cpus are brought up.
So there are no other cpus present at the time when the issue
might happen.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/kernel/sbi.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 775d3322b422..5a60a458c0b7 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -16,11 +16,19 @@
 unsigned long sbi_spec_version __ro_after_init = SBI_SPEC_VERSION_DEFAULT;
 EXPORT_SYMBOL(sbi_spec_version);
 
+static int __sbi_rfence_none(int fid, const struct cpumask *cpu_mask,
+			     unsigned long start, unsigned long size,
+			     unsigned long arg4, unsigned long arg5)
+{
+	return -EOPNOTSUPP;
+}
+
 static void (*__sbi_set_timer)(uint64_t stime) __ro_after_init;
 static int (*__sbi_send_ipi)(const struct cpumask *cpu_mask) __ro_after_init;
 static int (*__sbi_rfence)(int fid, const struct cpumask *cpu_mask,
 			   unsigned long start, unsigned long size,
-			   unsigned long arg4, unsigned long arg5) __ro_after_init;
+			   unsigned long arg4, unsigned long arg5)
+			   __ro_after_init = __sbi_rfence_none;
 
 struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
 			unsigned long arg1, unsigned long arg2,
-- 
2.30.2

[PATCH v7 01/13] riscv: prevent null-pointer dereference with sbi_remote_fence_i

[Heiko Stuebner]

The callback used inside sbi_remote_fence_i is set at sbi probe time
to the needed variant. Before that it is a NULL pointer.

Some users like the flush_icache_*() functions suggest a generic
functionality, that doesn't depend on a specific boot-stage but
uses sbi_remote_fence_i as one option to flush other cpu cores.

So they definitely shouldn't run into null-pointer dereference
issues when called "too early" during boot.

So introduce an empty function to be the standard for the __sbi_rfence
function pointer until sbi_init has run.

Users of sbi_remote_fence_i will have separate code for the local
cpu and sbi_init() is called before other cpus are brought up.
So there are no other cpus present at the time when the issue
might happen.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/kernel/sbi.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 775d3322b422..5a60a458c0b7 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -16,11 +16,19 @@
 unsigned long sbi_spec_version __ro_after_init = SBI_SPEC_VERSION_DEFAULT;
 EXPORT_SYMBOL(sbi_spec_version);
 
+static int __sbi_rfence_none(int fid, const struct cpumask *cpu_mask,
+			     unsigned long start, unsigned long size,
+			     unsigned long arg4, unsigned long arg5)
+{
+	return -EOPNOTSUPP;
+}
+
 static void (*__sbi_set_timer)(uint64_t stime) __ro_after_init;
 static int (*__sbi_send_ipi)(const struct cpumask *cpu_mask) __ro_after_init;
 static int (*__sbi_rfence)(int fid, const struct cpumask *cpu_mask,
 			   unsigned long start, unsigned long size,
-			   unsigned long arg4, unsigned long arg5) __ro_after_init;
+			   unsigned long arg4, unsigned long arg5)
+			   __ro_after_init = __sbi_rfence_none;
 
 struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
 			unsigned long arg1, unsigned long arg2,
-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 02/13] riscv: integrate alternatives better into the main architecture

[Heiko Stuebner]

Right now the alternatives need to be explicitly enabled and
erratas are limited to SiFive ones.

Over time with more SoCs and additional RiscV extensions, many more
erratas or other patch-worthy features will emerge, so it doesn't
really make sense to have the core alternatives able to get
deactivated.

So make it part of the core RiscV kernel and drop the main
RISCV_ERRATA_ALTERNATIVES config symbol.

This mimics how i.e. arm64 handles its alternatives implementation.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/Kconfig.erratas                  | 10 ----------
 arch/riscv/Kconfig.socs                     |  1 -
 arch/riscv/Makefile                         |  2 +-
 arch/riscv/errata/Makefile                  |  1 -
 arch/riscv/include/asm/alternative-macros.h | 22 ---------------------
 arch/riscv/kernel/Makefile                  |  1 +
 arch/riscv/{errata => kernel}/alternative.c |  0
 arch/riscv/kernel/smpboot.c                 |  2 --
 arch/riscv/kernel/traps.c                   |  2 +-
 9 files changed, 3 insertions(+), 38 deletions(-)
 rename arch/riscv/{errata => kernel}/alternative.c (100%)

diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
index b44d6ecdb46e..d18be8ff0245 100644
--- a/arch/riscv/Kconfig.erratas
+++ b/arch/riscv/Kconfig.erratas
@@ -1,17 +1,7 @@
 menu "CPU errata selection"
 
-config RISCV_ERRATA_ALTERNATIVE
-	bool "RISC-V alternative scheme"
-	default y
-	help
-	  This Kconfig allows the kernel to automatically patch the
-	  errata required by the execution platform at run time. The
-	  code patching is performed once in the boot stages. It means
-	  that the overhead from this mechanism is just taken once.
-
 config ERRATA_SIFIVE
 	bool "SiFive errata"
-	depends on RISCV_ERRATA_ALTERNATIVE
 	help
 	  All SiFive errata Kconfig depend on this Kconfig. Disabling
 	  this Kconfig will disable all SiFive errata. Please say "Y"
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 6ec44a22278a..3df7f7ed0d81 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -14,7 +14,6 @@ config SOC_SIFIVE
 	select CLK_SIFIVE
 	select CLK_SIFIVE_PRCI
 	select SIFIVE_PLIC
-	select RISCV_ERRATA_ALTERNATIVE
 	select ERRATA_SIFIVE
 	help
 	  This enables support for SiFive SoC platform hardware.
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 7d81102cffd4..a7ed47ce9311 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -103,7 +103,7 @@ endif
 
 head-y := arch/riscv/kernel/head.o
 
-core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/
+core-y += arch/riscv/errata/
 core-$(CONFIG_KVM) += arch/riscv/kvm/
 
 libs-y += arch/riscv/lib/
diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
index b8f8740a3e44..0ca1c5281a2d 100644
--- a/arch/riscv/errata/Makefile
+++ b/arch/riscv/errata/Makefile
@@ -1,2 +1 @@
-obj-y	+= alternative.o
 obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index 67406c376389..92da6b3920a3 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -2,8 +2,6 @@
 #ifndef __ASM_ALTERNATIVE_MACROS_H
 #define __ASM_ALTERNATIVE_MACROS_H
 
-#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE
-
 #ifdef __ASSEMBLY__
 
 .macro ALT_ENTRY oldptr newptr vendor_id errata_id new_len
@@ -76,26 +74,6 @@
 
 #endif /* __ASSEMBLY__ */
 
-#else /* !CONFIG_RISCV_ERRATA_ALTERNATIVE*/
-#ifdef __ASSEMBLY__
-
-.macro __ALTERNATIVE_CFG old_c
-	\old_c
-.endm
-
-#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
-	__ALTERNATIVE_CFG old_c
-
-#else /* !__ASSEMBLY__ */
-
-#define __ALTERNATIVE_CFG(old_c)  \
-	old_c "\n"
-
-#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
-	__ALTERNATIVE_CFG(old_c)
-
-#endif /* __ASSEMBLY__ */
-#endif /* CONFIG_RISCV_ERRATA_ALTERNATIVE */
 /*
  * Usage:
  *   ALTERNATIVE(old_content, new_content, vendor_id, errata_id, CONFIG_k)
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index ffc87e76b1dd..b02142517f7f 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -18,6 +18,7 @@ extra-y += head.o
 extra-y += vmlinux.lds
 
 obj-y	+= soc.o
+obj-y	+= alternative.o
 obj-y	+= cpu.o
 obj-y	+= cpufeature.o
 obj-y	+= entry.o
diff --git a/arch/riscv/errata/alternative.c b/arch/riscv/kernel/alternative.c
similarity index 100%
rename from arch/riscv/errata/alternative.c
rename to arch/riscv/kernel/alternative.c
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 622f226454d5..a6d13dca1403 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -41,9 +41,7 @@ static DECLARE_COMPLETION(cpu_running);
 void __init smp_prepare_boot_cpu(void)
 {
 	init_cpu_topology();
-#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE
 	apply_boot_alternatives();
-#endif
 }
 
 void __init smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index fe92e119e6a3..9984c8622c3b 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -86,7 +86,7 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code,
 	}
 }
 
-#if defined (CONFIG_XIP_KERNEL) && defined (CONFIG_RISCV_ERRATA_ALTERNATIVE)
+#if defined (CONFIG_XIP_KERNEL)
 #define __trap_section		__section(".xip.traps")
 #else
 #define __trap_section
-- 
2.30.2

[PATCH v7 02/13] riscv: integrate alternatives better into the main architecture

[Heiko Stuebner]

Right now the alternatives need to be explicitly enabled and
erratas are limited to SiFive ones.

Over time with more SoCs and additional RiscV extensions, many more
erratas or other patch-worthy features will emerge, so it doesn't
really make sense to have the core alternatives able to get
deactivated.

So make it part of the core RiscV kernel and drop the main
RISCV_ERRATA_ALTERNATIVES config symbol.

This mimics how i.e. arm64 handles its alternatives implementation.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/Kconfig.erratas                  | 10 ----------
 arch/riscv/Kconfig.socs                     |  1 -
 arch/riscv/Makefile                         |  2 +-
 arch/riscv/errata/Makefile                  |  1 -
 arch/riscv/include/asm/alternative-macros.h | 22 ---------------------
 arch/riscv/kernel/Makefile                  |  1 +
 arch/riscv/{errata => kernel}/alternative.c |  0
 arch/riscv/kernel/smpboot.c                 |  2 --
 arch/riscv/kernel/traps.c                   |  2 +-
 9 files changed, 3 insertions(+), 38 deletions(-)
 rename arch/riscv/{errata => kernel}/alternative.c (100%)

diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
index b44d6ecdb46e..d18be8ff0245 100644
--- a/arch/riscv/Kconfig.erratas
+++ b/arch/riscv/Kconfig.erratas
@@ -1,17 +1,7 @@
 menu "CPU errata selection"
 
-config RISCV_ERRATA_ALTERNATIVE
-	bool "RISC-V alternative scheme"
-	default y
-	help
-	  This Kconfig allows the kernel to automatically patch the
-	  errata required by the execution platform at run time. The
-	  code patching is performed once in the boot stages. It means
-	  that the overhead from this mechanism is just taken once.
-
 config ERRATA_SIFIVE
 	bool "SiFive errata"
-	depends on RISCV_ERRATA_ALTERNATIVE
 	help
 	  All SiFive errata Kconfig depend on this Kconfig. Disabling
 	  this Kconfig will disable all SiFive errata. Please say "Y"
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 6ec44a22278a..3df7f7ed0d81 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -14,7 +14,6 @@ config SOC_SIFIVE
 	select CLK_SIFIVE
 	select CLK_SIFIVE_PRCI
 	select SIFIVE_PLIC
-	select RISCV_ERRATA_ALTERNATIVE
 	select ERRATA_SIFIVE
 	help
 	  This enables support for SiFive SoC platform hardware.
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 7d81102cffd4..a7ed47ce9311 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -103,7 +103,7 @@ endif
 
 head-y := arch/riscv/kernel/head.o
 
-core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/
+core-y += arch/riscv/errata/
 core-$(CONFIG_KVM) += arch/riscv/kvm/
 
 libs-y += arch/riscv/lib/
diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
index b8f8740a3e44..0ca1c5281a2d 100644
--- a/arch/riscv/errata/Makefile
+++ b/arch/riscv/errata/Makefile
@@ -1,2 +1 @@
-obj-y	+= alternative.o
 obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index 67406c376389..92da6b3920a3 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -2,8 +2,6 @@
 #ifndef __ASM_ALTERNATIVE_MACROS_H
 #define __ASM_ALTERNATIVE_MACROS_H
 
-#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE
-
 #ifdef __ASSEMBLY__
 
 .macro ALT_ENTRY oldptr newptr vendor_id errata_id new_len
@@ -76,26 +74,6 @@
 
 #endif /* __ASSEMBLY__ */
 
-#else /* !CONFIG_RISCV_ERRATA_ALTERNATIVE*/
-#ifdef __ASSEMBLY__
-
-.macro __ALTERNATIVE_CFG old_c
-	\old_c
-.endm
-
-#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
-	__ALTERNATIVE_CFG old_c
-
-#else /* !__ASSEMBLY__ */
-
-#define __ALTERNATIVE_CFG(old_c)  \
-	old_c "\n"
-
-#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
-	__ALTERNATIVE_CFG(old_c)
-
-#endif /* __ASSEMBLY__ */
-#endif /* CONFIG_RISCV_ERRATA_ALTERNATIVE */
 /*
  * Usage:
  *   ALTERNATIVE(old_content, new_content, vendor_id, errata_id, CONFIG_k)
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index ffc87e76b1dd..b02142517f7f 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -18,6 +18,7 @@ extra-y += head.o
 extra-y += vmlinux.lds
 
 obj-y	+= soc.o
+obj-y	+= alternative.o
 obj-y	+= cpu.o
 obj-y	+= cpufeature.o
 obj-y	+= entry.o
diff --git a/arch/riscv/errata/alternative.c b/arch/riscv/kernel/alternative.c
similarity index 100%
rename from arch/riscv/errata/alternative.c
rename to arch/riscv/kernel/alternative.c
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 622f226454d5..a6d13dca1403 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -41,9 +41,7 @@ static DECLARE_COMPLETION(cpu_running);
 void __init smp_prepare_boot_cpu(void)
 {
 	init_cpu_topology();
-#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE
 	apply_boot_alternatives();
-#endif
 }
 
 void __init smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index fe92e119e6a3..9984c8622c3b 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -86,7 +86,7 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code,
 	}
 }
 
-#if defined (CONFIG_XIP_KERNEL) && defined (CONFIG_RISCV_ERRATA_ALTERNATIVE)
+#if defined (CONFIG_XIP_KERNEL)
 #define __trap_section		__section(".xip.traps")
 #else
 #define __trap_section
-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 03/13] riscv: allow different stages with alternatives

[Heiko Stuebner]

Future features may need to be applied at a different
time during boot, so allow defining stages for alternatives
and handling them differently depending on the stage.

Also make the alternatives-location more flexible so that
future stages may provide their own location.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/errata/sifive/errata.c    |  3 ++-
 arch/riscv/include/asm/alternative.h |  5 ++++-
 arch/riscv/kernel/alternative.c      | 26 +++++++++++++++++---------
 3 files changed, 23 insertions(+), 11 deletions(-)

diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
index f5e5ae70e829..4fe03ac41fd7 100644
--- a/arch/riscv/errata/sifive/errata.c
+++ b/arch/riscv/errata/sifive/errata.c
@@ -80,7 +80,8 @@ static void __init warn_miss_errata(u32 miss_errata)
 }
 
 void __init sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
-				     unsigned long archid, unsigned long impid)
+				     unsigned long archid, unsigned long impid,
+				     unsigned int stage)
 {
 	struct alt_entry *alt;
 	u32 cpu_req_errata = sifive_errata_probe(archid, impid);
diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index e625d3cafbed..811bdd8027db 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -17,6 +17,8 @@
 #include <linux/stddef.h>
 #include <asm/hwcap.h>
 
+#define RISCV_ALTERNATIVES_BOOT		0 /* alternatives applied during regular boot */
+
 void __init apply_boot_alternatives(void);
 
 struct alt_entry {
@@ -33,7 +35,8 @@ struct errata_checkfunc_id {
 };
 
 void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
-			      unsigned long archid, unsigned long impid);
+			      unsigned long archid, unsigned long impid,
+			      unsigned int stage);
 
 #endif
 #endif
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index e8b4a0fe488c..02db62f55bac 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -22,8 +22,8 @@ static struct cpu_manufacturer_info_t {
 } cpu_mfr_info;
 
 static void (*vendor_patch_func)(struct alt_entry *begin, struct alt_entry *end,
-				 unsigned long archid,
-				 unsigned long impid) __initdata;
+				 unsigned long archid, unsigned long impid,
+				 unsigned int stage) __initdata;
 
 static inline void __init riscv_fill_cpu_mfr_info(void)
 {
@@ -58,6 +58,18 @@ static void __init init_alternative(void)
  * a feature detect on the boot CPU). No need to worry about other CPUs
  * here.
  */
+static void __init _apply_alternatives(struct alt_entry *begin,
+				       struct alt_entry *end,
+				       unsigned int stage)
+{
+	if (!vendor_patch_func)
+		return;
+
+	vendor_patch_func(begin, end,
+			  cpu_mfr_info.arch_id, cpu_mfr_info.imp_id,
+			  stage);
+}
+
 void __init apply_boot_alternatives(void)
 {
 	/* If called on non-boot cpu things could go wrong */
@@ -65,11 +77,7 @@ void __init apply_boot_alternatives(void)
 
 	init_alternative();
 
-	if (!vendor_patch_func)
-		return;
-
-	vendor_patch_func((struct alt_entry *)__alt_start,
-			  (struct alt_entry *)__alt_end,
-			  cpu_mfr_info.arch_id, cpu_mfr_info.imp_id);
+	_apply_alternatives((struct alt_entry *)__alt_start,
+			    (struct alt_entry *)__alt_end,
+			    RISCV_ALTERNATIVES_BOOT);
 }
-
-- 
2.30.2

[PATCH v7 03/13] riscv: allow different stages with alternatives

[Heiko Stuebner]

Future features may need to be applied at a different
time during boot, so allow defining stages for alternatives
and handling them differently depending on the stage.

Also make the alternatives-location more flexible so that
future stages may provide their own location.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/errata/sifive/errata.c    |  3 ++-
 arch/riscv/include/asm/alternative.h |  5 ++++-
 arch/riscv/kernel/alternative.c      | 26 +++++++++++++++++---------
 3 files changed, 23 insertions(+), 11 deletions(-)

diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
index f5e5ae70e829..4fe03ac41fd7 100644
--- a/arch/riscv/errata/sifive/errata.c
+++ b/arch/riscv/errata/sifive/errata.c
@@ -80,7 +80,8 @@ static void __init warn_miss_errata(u32 miss_errata)
 }
 
 void __init sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
-				     unsigned long archid, unsigned long impid)
+				     unsigned long archid, unsigned long impid,
+				     unsigned int stage)
 {
 	struct alt_entry *alt;
 	u32 cpu_req_errata = sifive_errata_probe(archid, impid);
diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index e625d3cafbed..811bdd8027db 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -17,6 +17,8 @@
 #include <linux/stddef.h>
 #include <asm/hwcap.h>
 
+#define RISCV_ALTERNATIVES_BOOT		0 /* alternatives applied during regular boot */
+
 void __init apply_boot_alternatives(void);
 
 struct alt_entry {
@@ -33,7 +35,8 @@ struct errata_checkfunc_id {
 };
 
 void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
-			      unsigned long archid, unsigned long impid);
+			      unsigned long archid, unsigned long impid,
+			      unsigned int stage);
 
 #endif
 #endif
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index e8b4a0fe488c..02db62f55bac 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -22,8 +22,8 @@ static struct cpu_manufacturer_info_t {
 } cpu_mfr_info;
 
 static void (*vendor_patch_func)(struct alt_entry *begin, struct alt_entry *end,
-				 unsigned long archid,
-				 unsigned long impid) __initdata;
+				 unsigned long archid, unsigned long impid,
+				 unsigned int stage) __initdata;
 
 static inline void __init riscv_fill_cpu_mfr_info(void)
 {
@@ -58,6 +58,18 @@ static void __init init_alternative(void)
  * a feature detect on the boot CPU). No need to worry about other CPUs
  * here.
  */
+static void __init _apply_alternatives(struct alt_entry *begin,
+				       struct alt_entry *end,
+				       unsigned int stage)
+{
+	if (!vendor_patch_func)
+		return;
+
+	vendor_patch_func(begin, end,
+			  cpu_mfr_info.arch_id, cpu_mfr_info.imp_id,
+			  stage);
+}
+
 void __init apply_boot_alternatives(void)
 {
 	/* If called on non-boot cpu things could go wrong */
@@ -65,11 +77,7 @@ void __init apply_boot_alternatives(void)
 
 	init_alternative();
 
-	if (!vendor_patch_func)
-		return;
-
-	vendor_patch_func((struct alt_entry *)__alt_start,
-			  (struct alt_entry *)__alt_end,
-			  cpu_mfr_info.arch_id, cpu_mfr_info.imp_id);
+	_apply_alternatives((struct alt_entry *)__alt_start,
+			    (struct alt_entry *)__alt_end,
+			    RISCV_ALTERNATIVES_BOOT);
 }
-
-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 04/13] riscv: implement module alternatives

[Heiko Stuebner]

This allows alternatives to also be applied when loading modules
and follows the implementation of other architectures (e.g. arm64).

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/errata/sifive/errata.c    |  7 ++++---
 arch/riscv/include/asm/alternative.h |  3 ++-
 arch/riscv/kernel/alternative.c      | 18 +++++++++++++----
 arch/riscv/kernel/module.c           | 29 ++++++++++++++++++++++++++++
 4 files changed, 49 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
index 4fe03ac41fd7..42457efcaaa3 100644
--- a/arch/riscv/errata/sifive/errata.c
+++ b/arch/riscv/errata/sifive/errata.c
@@ -4,6 +4,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/string.h>
 #include <linux/bug.h>
 #include <asm/patch.h>
@@ -54,7 +55,7 @@ static struct errata_info_t errata_list[ERRATA_SIFIVE_NUMBER] = {
 	},
 };
 
-static u32 __init sifive_errata_probe(unsigned long archid, unsigned long impid)
+static u32 __init_or_module sifive_errata_probe(unsigned long archid, unsigned long impid)
 {
 	int idx;
 	u32 cpu_req_errata = 0;
@@ -66,7 +67,7 @@ static u32 __init sifive_errata_probe(unsigned long archid, unsigned long impid)
 	return cpu_req_errata;
 }
 
-static void __init warn_miss_errata(u32 miss_errata)
+static void __init_or_module warn_miss_errata(u32 miss_errata)
 {
 	int i;
 
@@ -79,7 +80,7 @@ static void __init warn_miss_errata(u32 miss_errata)
 	pr_warn("----------------------------------------------------------------\n");
 }
 
-void __init sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+void __init_or_module sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 				     unsigned long archid, unsigned long impid,
 				     unsigned int stage)
 {
diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index 811bdd8027db..f0657b1b3174 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -18,8 +18,10 @@
 #include <asm/hwcap.h>
 
 #define RISCV_ALTERNATIVES_BOOT		0 /* alternatives applied during regular boot */
+#define RISCV_ALTERNATIVES_MODULE	1 /* alternatives applied during module-init */
 
 void __init apply_boot_alternatives(void);
+void apply_module_alternatives(void *start, size_t length);
 
 struct alt_entry {
 	void *old_ptr;		 /* address of original instruciton or data  */
@@ -37,6 +39,5 @@ struct errata_checkfunc_id {
 void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 			      unsigned long archid, unsigned long impid,
 			      unsigned int stage);
-
 #endif
 #endif
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 02db62f55bac..223770b3945c 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -7,6 +7,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/module.h>
 #include <linux/cpu.h>
 #include <linux/uaccess.h>
 #include <asm/alternative.h>
@@ -23,7 +24,7 @@ static struct cpu_manufacturer_info_t {
 
 static void (*vendor_patch_func)(struct alt_entry *begin, struct alt_entry *end,
 				 unsigned long archid, unsigned long impid,
-				 unsigned int stage) __initdata;
+				 unsigned int stage) __initdata_or_module;
 
 static inline void __init riscv_fill_cpu_mfr_info(void)
 {
@@ -58,9 +59,9 @@ static void __init init_alternative(void)
  * a feature detect on the boot CPU). No need to worry about other CPUs
  * here.
  */
-static void __init _apply_alternatives(struct alt_entry *begin,
-				       struct alt_entry *end,
-				       unsigned int stage)
+static void __init_or_module _apply_alternatives(struct alt_entry *begin,
+						 struct alt_entry *end,
+						 unsigned int stage)
 {
 	if (!vendor_patch_func)
 		return;
@@ -81,3 +82,12 @@ void __init apply_boot_alternatives(void)
 			    (struct alt_entry *)__alt_end,
 			    RISCV_ALTERNATIVES_BOOT);
 }
+
+#ifdef CONFIG_MODULES
+void apply_module_alternatives(void *start, size_t length)
+{
+	_apply_alternatives((struct alt_entry *)start,
+			    (struct alt_entry *)(start + length),
+			    RISCV_ALTERNATIVES_MODULE);
+}
+#endif
diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c
index 68a9e3d1fe16..a778abd5b8b9 100644
--- a/arch/riscv/kernel/module.c
+++ b/arch/riscv/kernel/module.c
@@ -11,6 +11,7 @@
 #include <linux/vmalloc.h>
 #include <linux/sizes.h>
 #include <linux/pgtable.h>
+#include <asm/alternative.h>
 #include <asm/sections.h>
 
 static int apply_r_riscv_32_rela(struct module *me, u32 *location, Elf_Addr v)
@@ -416,3 +417,31 @@ void *module_alloc(unsigned long size)
 				    __builtin_return_address(0));
 }
 #endif
+
+static const Elf_Shdr *find_section(const Elf_Ehdr *hdr,
+				    const Elf_Shdr *sechdrs,
+				    const char *name)
+{
+	const Elf_Shdr *s, *se;
+	const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
+
+	for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
+		if (strcmp(name, secstrs + s->sh_name) == 0)
+			return s;
+	}
+
+	return NULL;
+}
+
+int module_finalize(const Elf_Ehdr *hdr,
+		    const Elf_Shdr *sechdrs,
+		    struct module *me)
+{
+	const Elf_Shdr *s;
+
+	s = find_section(hdr, sechdrs, ".alternative");
+	if (s)
+		apply_module_alternatives((void *)s->sh_addr, s->sh_size);
+
+	return 0;
+}
-- 
2.30.2

[PATCH v7 04/13] riscv: implement module alternatives

[Heiko Stuebner]

This allows alternatives to also be applied when loading modules
and follows the implementation of other architectures (e.g. arm64).

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/errata/sifive/errata.c    |  7 ++++---
 arch/riscv/include/asm/alternative.h |  3 ++-
 arch/riscv/kernel/alternative.c      | 18 +++++++++++++----
 arch/riscv/kernel/module.c           | 29 ++++++++++++++++++++++++++++
 4 files changed, 49 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
index 4fe03ac41fd7..42457efcaaa3 100644
--- a/arch/riscv/errata/sifive/errata.c
+++ b/arch/riscv/errata/sifive/errata.c
@@ -4,6 +4,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/string.h>
 #include <linux/bug.h>
 #include <asm/patch.h>
@@ -54,7 +55,7 @@ static struct errata_info_t errata_list[ERRATA_SIFIVE_NUMBER] = {
 	},
 };
 
-static u32 __init sifive_errata_probe(unsigned long archid, unsigned long impid)
+static u32 __init_or_module sifive_errata_probe(unsigned long archid, unsigned long impid)
 {
 	int idx;
 	u32 cpu_req_errata = 0;
@@ -66,7 +67,7 @@ static u32 __init sifive_errata_probe(unsigned long archid, unsigned long impid)
 	return cpu_req_errata;
 }
 
-static void __init warn_miss_errata(u32 miss_errata)
+static void __init_or_module warn_miss_errata(u32 miss_errata)
 {
 	int i;
 
@@ -79,7 +80,7 @@ static void __init warn_miss_errata(u32 miss_errata)
 	pr_warn("----------------------------------------------------------------\n");
 }
 
-void __init sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+void __init_or_module sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 				     unsigned long archid, unsigned long impid,
 				     unsigned int stage)
 {
diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index 811bdd8027db..f0657b1b3174 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -18,8 +18,10 @@
 #include <asm/hwcap.h>
 
 #define RISCV_ALTERNATIVES_BOOT		0 /* alternatives applied during regular boot */
+#define RISCV_ALTERNATIVES_MODULE	1 /* alternatives applied during module-init */
 
 void __init apply_boot_alternatives(void);
+void apply_module_alternatives(void *start, size_t length);
 
 struct alt_entry {
 	void *old_ptr;		 /* address of original instruciton or data  */
@@ -37,6 +39,5 @@ struct errata_checkfunc_id {
 void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 			      unsigned long archid, unsigned long impid,
 			      unsigned int stage);
-
 #endif
 #endif
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 02db62f55bac..223770b3945c 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -7,6 +7,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/module.h>
 #include <linux/cpu.h>
 #include <linux/uaccess.h>
 #include <asm/alternative.h>
@@ -23,7 +24,7 @@ static struct cpu_manufacturer_info_t {
 
 static void (*vendor_patch_func)(struct alt_entry *begin, struct alt_entry *end,
 				 unsigned long archid, unsigned long impid,
-				 unsigned int stage) __initdata;
+				 unsigned int stage) __initdata_or_module;
 
 static inline void __init riscv_fill_cpu_mfr_info(void)
 {
@@ -58,9 +59,9 @@ static void __init init_alternative(void)
  * a feature detect on the boot CPU). No need to worry about other CPUs
  * here.
  */
-static void __init _apply_alternatives(struct alt_entry *begin,
-				       struct alt_entry *end,
-				       unsigned int stage)
+static void __init_or_module _apply_alternatives(struct alt_entry *begin,
+						 struct alt_entry *end,
+						 unsigned int stage)
 {
 	if (!vendor_patch_func)
 		return;
@@ -81,3 +82,12 @@ void __init apply_boot_alternatives(void)
 			    (struct alt_entry *)__alt_end,
 			    RISCV_ALTERNATIVES_BOOT);
 }
+
+#ifdef CONFIG_MODULES
+void apply_module_alternatives(void *start, size_t length)
+{
+	_apply_alternatives((struct alt_entry *)start,
+			    (struct alt_entry *)(start + length),
+			    RISCV_ALTERNATIVES_MODULE);
+}
+#endif
diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c
index 68a9e3d1fe16..a778abd5b8b9 100644
--- a/arch/riscv/kernel/module.c
+++ b/arch/riscv/kernel/module.c
@@ -11,6 +11,7 @@
 #include <linux/vmalloc.h>
 #include <linux/sizes.h>
 #include <linux/pgtable.h>
+#include <asm/alternative.h>
 #include <asm/sections.h>
 
 static int apply_r_riscv_32_rela(struct module *me, u32 *location, Elf_Addr v)
@@ -416,3 +417,31 @@ void *module_alloc(unsigned long size)
 				    __builtin_return_address(0));
 }
 #endif
+
+static const Elf_Shdr *find_section(const Elf_Ehdr *hdr,
+				    const Elf_Shdr *sechdrs,
+				    const char *name)
+{
+	const Elf_Shdr *s, *se;
+	const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
+
+	for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
+		if (strcmp(name, secstrs + s->sh_name) == 0)
+			return s;
+	}
+
+	return NULL;
+}
+
+int module_finalize(const Elf_Ehdr *hdr,
+		    const Elf_Shdr *sechdrs,
+		    struct module *me)
+{
+	const Elf_Shdr *s;
+
+	s = find_section(hdr, sechdrs, ".alternative");
+	if (s)
+		apply_module_alternatives((void *)s->sh_addr, s->sh_size);
+
+	return 0;
+}
-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 05/13] riscv: implement ALTERNATIVE_2 macro

[Heiko Stuebner]

When the alternatives were added the commit already provided a template
on how to implement 2 different alternatives for one piece of code.

Make this usable.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/include/asm/alternative-macros.h | 52 +++++++++++++--------
 1 file changed, 32 insertions(+), 20 deletions(-)

diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index 92da6b3920a3..baf649293288 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -37,6 +37,20 @@
 #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
 	__ALTERNATIVE_CFG old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k)
 
+.macro __ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
+				  new_c_2, vendor_id_2, errata_id_2, enable_2
+886 :
+	\old_c
+887 :
+	ALT_NEW_CONTENT \vendor_id_1, \errata_id_1, \enable_1, \new_c_1
+	ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
+.endm
+
+#define _ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
+				  new_c_2, vendor_id_2, errata_id_2, CONFIG_k_2) \
+	__ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1), \
+				   new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2)
+
 #else /* !__ASSEMBLY__ */
 
 #include <asm/asm.h>
@@ -72,6 +86,19 @@
 #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k)	\
 	__ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k))
 
+#define __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
+				  new_c_2, vendor_id_2, errata_id_2, enable_2) \
+	"886 :\n"	\
+	old_c "\n"	\
+	"887 :\n"	\
+	ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
+	ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
+
+#define _ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1,		\
+				  new_c_2, vendor_id_2, errata_id_2, CONFIG_k_2)		\
+	__ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1),	\
+				   new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2))
+
 #endif /* __ASSEMBLY__ */
 
 /*
@@ -96,25 +123,10 @@
  * this case, this vendor can create a new macro ALTERNATIVE_2() based
  * on the following sample code and then replace ALTERNATIVE() with
  * ALTERNATIVE_2() to append its customized content.
- *
- * .macro __ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
- *                                   new_c_2, vendor_id_2, errata_id_2, enable_2
- * 886 :
- *      \old_c
- * 887 :
- *      ALT_NEW_CONTENT \vendor_id_1, \errata_id_1, \enable_1, \new_c_1
- *      ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
- * .endm
- *
- * #define _ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
- *                                   new_c_2, vendor_id_2, errata_id_2, CONFIG_k_2) \
- *        __ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1), \
- *                                   new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2) \
- *
- * #define ALTERNATIVE_2(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
- *                                    new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2) \
- *         _ALTERNATIVE_CFG_2(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
- *                                         new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2)
- *
  */
+#define ALTERNATIVE_2(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
+				   new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2) \
+	_ALTERNATIVE_CFG_2(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
+					new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2)
+
 #endif
-- 
2.30.2

[PATCH v7 05/13] riscv: implement ALTERNATIVE_2 macro

[Heiko Stuebner]

When the alternatives were added the commit already provided a template
on how to implement 2 different alternatives for one piece of code.

Make this usable.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/include/asm/alternative-macros.h | 52 +++++++++++++--------
 1 file changed, 32 insertions(+), 20 deletions(-)

diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index 92da6b3920a3..baf649293288 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -37,6 +37,20 @@
 #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
 	__ALTERNATIVE_CFG old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k)
 
+.macro __ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
+				  new_c_2, vendor_id_2, errata_id_2, enable_2
+886 :
+	\old_c
+887 :
+	ALT_NEW_CONTENT \vendor_id_1, \errata_id_1, \enable_1, \new_c_1
+	ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
+.endm
+
+#define _ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
+				  new_c_2, vendor_id_2, errata_id_2, CONFIG_k_2) \
+	__ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1), \
+				   new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2)
+
 #else /* !__ASSEMBLY__ */
 
 #include <asm/asm.h>
@@ -72,6 +86,19 @@
 #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k)	\
 	__ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k))
 
+#define __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
+				  new_c_2, vendor_id_2, errata_id_2, enable_2) \
+	"886 :\n"	\
+	old_c "\n"	\
+	"887 :\n"	\
+	ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
+	ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
+
+#define _ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1,		\
+				  new_c_2, vendor_id_2, errata_id_2, CONFIG_k_2)		\
+	__ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1),	\
+				   new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2))
+
 #endif /* __ASSEMBLY__ */
 
 /*
@@ -96,25 +123,10 @@
  * this case, this vendor can create a new macro ALTERNATIVE_2() based
  * on the following sample code and then replace ALTERNATIVE() with
  * ALTERNATIVE_2() to append its customized content.
- *
- * .macro __ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
- *                                   new_c_2, vendor_id_2, errata_id_2, enable_2
- * 886 :
- *      \old_c
- * 887 :
- *      ALT_NEW_CONTENT \vendor_id_1, \errata_id_1, \enable_1, \new_c_1
- *      ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
- * .endm
- *
- * #define _ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
- *                                   new_c_2, vendor_id_2, errata_id_2, CONFIG_k_2) \
- *        __ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1), \
- *                                   new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2) \
- *
- * #define ALTERNATIVE_2(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
- *                                    new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2) \
- *         _ALTERNATIVE_CFG_2(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
- *                                         new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2)
- *
  */
+#define ALTERNATIVE_2(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
+				   new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2) \
+	_ALTERNATIVE_CFG_2(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
+					new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2)
+
 #endif
-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 06/13] riscv: extend concatenated alternatives-lines to the same length

[Heiko Stuebner]

ALT_NEW_CONTENT already uses same-length assembler lines, so
extend this to the other elements as well.

This makes it more readable when these elements need to be extended
in the future.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/include/asm/alternative-macros.h | 30 ++++++++++-----------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index baf649293288..c0fb11fad631 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -56,14 +56,14 @@
 #include <asm/asm.h>
 #include <linux/stringify.h>
 
-#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \
-	RISCV_PTR " " oldptr "\n" \
-	RISCV_PTR " " newptr "\n" \
-	REG_ASM " " vendor_id "\n" \
-	REG_ASM " " newlen "\n" \
+#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen)		\
+	RISCV_PTR " " oldptr "\n"					\
+	RISCV_PTR " " newptr "\n"					\
+	REG_ASM " " vendor_id "\n"					\
+	REG_ASM " " newlen "\n"						\
 	".word " errata_id "\n"
 
-#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \
+#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c)		\
 	".if " __stringify(enable) " == 1\n"				\
 	".pushsection .alternative, \"a\"\n"				\
 	ALT_ENTRY("886b", "888f", __stringify(vendor_id), __stringify(errata_id), "889f - 888f") \
@@ -77,21 +77,21 @@
 	".org	. - (889b - 888b) + (887b - 886b)\n"			\
 	".endif\n"
 
-#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
-	"886 :\n"	\
-	old_c "\n"	\
-	"887 :\n"	\
+#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable)	\
+	"886 :\n"							\
+	old_c "\n"							\
+	"887 :\n"							\
 	ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c)
 
-#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k)	\
+#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
 	__ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k))
 
 #define __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
 				  new_c_2, vendor_id_2, errata_id_2, enable_2) \
-	"886 :\n"	\
-	old_c "\n"	\
-	"887 :\n"	\
-	ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
+	"886 :\n"							\
+	old_c "\n"							\
+	"887 :\n"							\
+	ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1)	\
 	ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
 
 #define _ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1,		\
-- 
2.30.2

[PATCH v7 06/13] riscv: extend concatenated alternatives-lines to the same length

[Heiko Stuebner]

ALT_NEW_CONTENT already uses same-length assembler lines, so
extend this to the other elements as well.

This makes it more readable when these elements need to be extended
in the future.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/include/asm/alternative-macros.h | 30 ++++++++++-----------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index baf649293288..c0fb11fad631 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -56,14 +56,14 @@
 #include <asm/asm.h>
 #include <linux/stringify.h>
 
-#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \
-	RISCV_PTR " " oldptr "\n" \
-	RISCV_PTR " " newptr "\n" \
-	REG_ASM " " vendor_id "\n" \
-	REG_ASM " " newlen "\n" \
+#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen)		\
+	RISCV_PTR " " oldptr "\n"					\
+	RISCV_PTR " " newptr "\n"					\
+	REG_ASM " " vendor_id "\n"					\
+	REG_ASM " " newlen "\n"						\
 	".word " errata_id "\n"
 
-#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \
+#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c)		\
 	".if " __stringify(enable) " == 1\n"				\
 	".pushsection .alternative, \"a\"\n"				\
 	ALT_ENTRY("886b", "888f", __stringify(vendor_id), __stringify(errata_id), "889f - 888f") \
@@ -77,21 +77,21 @@
 	".org	. - (889b - 888b) + (887b - 886b)\n"			\
 	".endif\n"
 
-#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
-	"886 :\n"	\
-	old_c "\n"	\
-	"887 :\n"	\
+#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable)	\
+	"886 :\n"							\
+	old_c "\n"							\
+	"887 :\n"							\
 	ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c)
 
-#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k)	\
+#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
 	__ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k))
 
 #define __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
 				  new_c_2, vendor_id_2, errata_id_2, enable_2) \
-	"886 :\n"	\
-	old_c "\n"	\
-	"887 :\n"	\
-	ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
+	"886 :\n"							\
+	old_c "\n"							\
+	"887 :\n"							\
+	ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1)	\
 	ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
 
 #define _ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1,		\
-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 07/13] riscv: prevent compressed instructions in alternatives

[Heiko Stuebner]

Instructions are opportunistically compressed by the RISC-V assembler
when possible, but in alternatives-blocks both the old and new content
need to be the same size, so having the toolchain do somewhat random
optimizations will cause strange side-effects like
"attempt to move .org backwards" compile-time errors.

Already a simple "and" used in alternatives assembly will cause these
mismatched code sizes.

So prevent compressed instructions to be generated in alternatives-
code and use option-push and -pop to only limit this to the relevant
code blocks

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/include/asm/alternative-macros.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index c0fb11fad631..3a52884bf23d 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -19,7 +19,10 @@
 	.popsection
 	.subsection 1
 888 :
+	.option push
+	.option norvc
 	\new_c
+	.option pop
 889 :
 	.previous
 	.org    . - (889b - 888b) + (887b - 886b)
@@ -29,7 +32,10 @@
 
 .macro __ALTERNATIVE_CFG old_c, new_c, vendor_id, errata_id, enable
 886 :
+	.option push
+	.option norvc
 	\old_c
+	.option pop
 887 :
 	ALT_NEW_CONTENT \vendor_id, \errata_id, \enable, \new_c
 .endm
@@ -40,7 +46,10 @@
 .macro __ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
 				  new_c_2, vendor_id_2, errata_id_2, enable_2
 886 :
+	.option push
+	.option norvc
 	\old_c
+	.option pop
 887 :
 	ALT_NEW_CONTENT \vendor_id_1, \errata_id_1, \enable_1, \new_c_1
 	ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
@@ -70,7 +79,10 @@
 	".popsection\n"							\
 	".subsection 1\n"						\
 	"888 :\n"							\
+	".option push\n"						\
+	".option norvc\n"						\
 	new_c "\n"							\
+	".option pop\n"							\
 	"889 :\n"							\
 	".previous\n"							\
 	".org	. - (887b - 886b) + (889b - 888b)\n"			\
@@ -79,7 +91,10 @@
 
 #define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable)	\
 	"886 :\n"							\
+	".option push\n"						\
+	".option norvc\n"						\
 	old_c "\n"							\
+	".option pop\n"							\
 	"887 :\n"							\
 	ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c)
 
@@ -89,7 +104,10 @@
 #define __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
 				  new_c_2, vendor_id_2, errata_id_2, enable_2) \
 	"886 :\n"							\
+	".option push\n"						\
+	".option norvc\n"						\
 	old_c "\n"							\
+	".option pop\n"							\
 	"887 :\n"							\
 	ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1)	\
 	ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
-- 
2.30.2

[PATCH v7 07/13] riscv: prevent compressed instructions in alternatives

[Heiko Stuebner]

Instructions are opportunistically compressed by the RISC-V assembler
when possible, but in alternatives-blocks both the old and new content
need to be the same size, so having the toolchain do somewhat random
optimizations will cause strange side-effects like
"attempt to move .org backwards" compile-time errors.

Already a simple "and" used in alternatives assembly will cause these
mismatched code sizes.

So prevent compressed instructions to be generated in alternatives-
code and use option-push and -pop to only limit this to the relevant
code blocks

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/include/asm/alternative-macros.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index c0fb11fad631..3a52884bf23d 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -19,7 +19,10 @@
 	.popsection
 	.subsection 1
 888 :
+	.option push
+	.option norvc
 	\new_c
+	.option pop
 889 :
 	.previous
 	.org    . - (889b - 888b) + (887b - 886b)
@@ -29,7 +32,10 @@
 
 .macro __ALTERNATIVE_CFG old_c, new_c, vendor_id, errata_id, enable
 886 :
+	.option push
+	.option norvc
 	\old_c
+	.option pop
 887 :
 	ALT_NEW_CONTENT \vendor_id, \errata_id, \enable, \new_c
 .endm
@@ -40,7 +46,10 @@
 .macro __ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
 				  new_c_2, vendor_id_2, errata_id_2, enable_2
 886 :
+	.option push
+	.option norvc
 	\old_c
+	.option pop
 887 :
 	ALT_NEW_CONTENT \vendor_id_1, \errata_id_1, \enable_1, \new_c_1
 	ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
@@ -70,7 +79,10 @@
 	".popsection\n"							\
 	".subsection 1\n"						\
 	"888 :\n"							\
+	".option push\n"						\
+	".option norvc\n"						\
 	new_c "\n"							\
+	".option pop\n"							\
 	"889 :\n"							\
 	".previous\n"							\
 	".org	. - (887b - 886b) + (889b - 888b)\n"			\
@@ -79,7 +91,10 @@
 
 #define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable)	\
 	"886 :\n"							\
+	".option push\n"						\
+	".option norvc\n"						\
 	old_c "\n"							\
+	".option pop\n"							\
 	"887 :\n"							\
 	ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c)
 
@@ -89,7 +104,10 @@
 #define __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
 				  new_c_2, vendor_id_2, errata_id_2, enable_2) \
 	"886 :\n"							\
+	".option push\n"						\
+	".option norvc\n"						\
 	old_c "\n"							\
+	".option pop\n"							\
 	"887 :\n"							\
 	ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1)	\
 	ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 08/13] riscv: move boot alternatives to after fill_hwcap

[Heiko Stuebner]

Move the application of boot alternatives to after the hw-capabilities
are populated. This allows to check for available extensions when
determining which alternatives to apply and also makes it actually
work if CONFIG_SMP is disabled for whatever reason.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/kernel/setup.c   | 2 ++
 arch/riscv/kernel/smpboot.c | 2 --
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 339ceb595b38..b4879c942b42 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -21,6 +21,7 @@
 #include <linux/efi.h>
 #include <linux/crash_dump.h>
 
+#include <asm/alternative.h>
 #include <asm/cpu_ops.h>
 #include <asm/early_ioremap.h>
 #include <asm/pgtable.h>
@@ -295,6 +296,7 @@ void __init setup_arch(char **cmdline_p)
 #endif
 
 	riscv_fill_hwcap();
+	apply_boot_alternatives();
 }
 
 static int __init topology_init(void)
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index a6d13dca1403..f1e4948a4b52 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -32,7 +32,6 @@
 #include <asm/sections.h>
 #include <asm/sbi.h>
 #include <asm/smp.h>
-#include <asm/alternative.h>
 
 #include "head.h"
 
@@ -41,7 +40,6 @@ static DECLARE_COMPLETION(cpu_running);
 void __init smp_prepare_boot_cpu(void)
 {
 	init_cpu_topology();
-	apply_boot_alternatives();
 }
 
 void __init smp_prepare_cpus(unsigned int max_cpus)
-- 
2.30.2

[PATCH v7 08/13] riscv: move boot alternatives to after fill_hwcap

[Heiko Stuebner]

Move the application of boot alternatives to after the hw-capabilities
are populated. This allows to check for available extensions when
determining which alternatives to apply and also makes it actually
work if CONFIG_SMP is disabled for whatever reason.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/kernel/setup.c   | 2 ++
 arch/riscv/kernel/smpboot.c | 2 --
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 339ceb595b38..b4879c942b42 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -21,6 +21,7 @@
 #include <linux/efi.h>
 #include <linux/crash_dump.h>
 
+#include <asm/alternative.h>
 #include <asm/cpu_ops.h>
 #include <asm/early_ioremap.h>
 #include <asm/pgtable.h>
@@ -295,6 +296,7 @@ void __init setup_arch(char **cmdline_p)
 #endif
 
 	riscv_fill_hwcap();
+	apply_boot_alternatives();
 }
 
 static int __init topology_init(void)
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index a6d13dca1403..f1e4948a4b52 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -32,7 +32,6 @@
 #include <asm/sections.h>
 #include <asm/sbi.h>
 #include <asm/smp.h>
-#include <asm/alternative.h>
 
 #include "head.h"
 
@@ -41,7 +40,6 @@ static DECLARE_COMPLETION(cpu_running);
 void __init smp_prepare_boot_cpu(void)
 {
 	init_cpu_topology();
-	apply_boot_alternatives();
 }
 
 void __init smp_prepare_cpus(unsigned int max_cpus)
-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 09/13] riscv: Fix accessing pfn bits in PTEs for non-32bit variants

[Heiko Stuebner]

On rv32 the PFN part of PTEs is defined to use bits [xlen-1:10]
while on rv64 it is defined to use bits [53:10], leaving [63:54]
as reserved.

With upcoming optional extensions like svpbmt these previously
reserved bits will get used so simply right-shifting the PTE
to get the PFN won't be enough.

So introduce a _PAGE_PFN_MASK constant to mask the correct bits
for both rv32 and rv64 before shifting.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/include/asm/pgtable-32.h   |  8 ++++++++
 arch/riscv/include/asm/pgtable-64.h   | 14 +++++++++++---
 arch/riscv/include/asm/pgtable-bits.h |  6 ------
 arch/riscv/include/asm/pgtable.h      |  6 +++---
 4 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
index 5b2e79e5bfa5..e266a4fe7f43 100644
--- a/arch/riscv/include/asm/pgtable-32.h
+++ b/arch/riscv/include/asm/pgtable-32.h
@@ -7,6 +7,7 @@
 #define _ASM_RISCV_PGTABLE_32_H
 
 #include <asm-generic/pgtable-nopmd.h>
+#include <linux/bits.h>
 #include <linux/const.h>
 
 /* Size of region mapped by a page global directory */
@@ -16,4 +17,11 @@
 
 #define MAX_POSSIBLE_PHYSMEM_BITS 34
 
+/*
+ * rv32 PTE format:
+ * | XLEN-1  10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ *       PFN      reserved for SW   D   A   G   U   X   W   R   V
+ */
+#define _PAGE_PFN_MASK  GENMASK(31, 10)
+
 #endif /* _ASM_RISCV_PGTABLE_32_H */
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index bbbdd66e5e2f..9412c6157c88 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -6,6 +6,7 @@
 #ifndef _ASM_RISCV_PGTABLE_64_H
 #define _ASM_RISCV_PGTABLE_64_H
 
+#include <linux/bits.h>
 #include <linux/const.h>
 
 extern bool pgtable_l4_enabled;
@@ -48,6 +49,13 @@ typedef struct {
 
 #define PTRS_PER_PMD    (PAGE_SIZE / sizeof(pmd_t))
 
+/*
+ * rv64 PTE format:
+ * | 63 | 62 61 | 60 54 | 53  10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ *   N      MT     RSV    PFN      reserved for SW   D   A   G   U   X   W   R   V
+ */
+#define _PAGE_PFN_MASK  GENMASK(53, 10)
+
 static inline int pud_present(pud_t pud)
 {
 	return (pud_val(pud) & _PAGE_PRESENT);
@@ -91,12 +99,12 @@ static inline unsigned long _pud_pfn(pud_t pud)
 
 static inline pmd_t *pud_pgtable(pud_t pud)
 {
-	return (pmd_t *)pfn_to_virt(pud_val(pud) >> _PAGE_PFN_SHIFT);
+	return (pmd_t *)pfn_to_virt((pud_val(pud) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
 }
 
 static inline struct page *pud_page(pud_t pud)
 {
-	return pfn_to_page(pud_val(pud) >> _PAGE_PFN_SHIFT);
+	return pfn_to_page((pud_val(pud) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
 }
 
 #define mm_pud_folded  mm_pud_folded
@@ -117,7 +125,7 @@ static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot)
 
 static inline unsigned long _pmd_pfn(pmd_t pmd)
 {
-	return pmd_val(pmd) >> _PAGE_PFN_SHIFT;
+	return (pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT;
 }
 
 #define mk_pmd(page, prot)    pfn_pmd(page_to_pfn(page), prot)
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index a6b0c89824c2..e571fa954afc 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -6,12 +6,6 @@
 #ifndef _ASM_RISCV_PGTABLE_BITS_H
 #define _ASM_RISCV_PGTABLE_BITS_H
 
-/*
- * PTE format:
- * | XLEN-1  10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- *       PFN      reserved for SW   D   A   G   U   X   W   R   V
- */
-
 #define _PAGE_ACCESSED_OFFSET 6
 
 #define _PAGE_PRESENT   (1 << 0)
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index e3549e50de95..6d31489818cd 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -259,12 +259,12 @@ static inline unsigned long _pgd_pfn(pgd_t pgd)
 
 static inline struct page *pmd_page(pmd_t pmd)
 {
-	return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
+	return pfn_to_page((pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
 }
 
 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
 {
-	return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
+	return (unsigned long)pfn_to_virt((pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
 }
 
 static inline pte_t pmd_pte(pmd_t pmd)
@@ -280,7 +280,7 @@ static inline pte_t pud_pte(pud_t pud)
 /* Yields the page frame number (PFN) of a page table entry */
 static inline unsigned long pte_pfn(pte_t pte)
 {
-	return (pte_val(pte) >> _PAGE_PFN_SHIFT);
+	return ((pte_val(pte) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
 }
 
 #define pte_page(x)     pfn_to_page(pte_pfn(x))
-- 
2.30.2

[PATCH v7 09/13] riscv: Fix accessing pfn bits in PTEs for non-32bit variants

[Heiko Stuebner]

On rv32 the PFN part of PTEs is defined to use bits [xlen-1:10]
while on rv64 it is defined to use bits [53:10], leaving [63:54]
as reserved.

With upcoming optional extensions like svpbmt these previously
reserved bits will get used so simply right-shifting the PTE
to get the PFN won't be enough.

So introduce a _PAGE_PFN_MASK constant to mask the correct bits
for both rv32 and rv64 before shifting.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/include/asm/pgtable-32.h   |  8 ++++++++
 arch/riscv/include/asm/pgtable-64.h   | 14 +++++++++++---
 arch/riscv/include/asm/pgtable-bits.h |  6 ------
 arch/riscv/include/asm/pgtable.h      |  6 +++---
 4 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
index 5b2e79e5bfa5..e266a4fe7f43 100644
--- a/arch/riscv/include/asm/pgtable-32.h
+++ b/arch/riscv/include/asm/pgtable-32.h
@@ -7,6 +7,7 @@
 #define _ASM_RISCV_PGTABLE_32_H
 
 #include <asm-generic/pgtable-nopmd.h>
+#include <linux/bits.h>
 #include <linux/const.h>
 
 /* Size of region mapped by a page global directory */
@@ -16,4 +17,11 @@
 
 #define MAX_POSSIBLE_PHYSMEM_BITS 34
 
+/*
+ * rv32 PTE format:
+ * | XLEN-1  10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ *       PFN      reserved for SW   D   A   G   U   X   W   R   V
+ */
+#define _PAGE_PFN_MASK  GENMASK(31, 10)
+
 #endif /* _ASM_RISCV_PGTABLE_32_H */
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index bbbdd66e5e2f..9412c6157c88 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -6,6 +6,7 @@
 #ifndef _ASM_RISCV_PGTABLE_64_H
 #define _ASM_RISCV_PGTABLE_64_H
 
+#include <linux/bits.h>
 #include <linux/const.h>
 
 extern bool pgtable_l4_enabled;
@@ -48,6 +49,13 @@ typedef struct {
 
 #define PTRS_PER_PMD    (PAGE_SIZE / sizeof(pmd_t))
 
+/*
+ * rv64 PTE format:
+ * | 63 | 62 61 | 60 54 | 53  10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ *   N      MT     RSV    PFN      reserved for SW   D   A   G   U   X   W   R   V
+ */
+#define _PAGE_PFN_MASK  GENMASK(53, 10)
+
 static inline int pud_present(pud_t pud)
 {
 	return (pud_val(pud) & _PAGE_PRESENT);
@@ -91,12 +99,12 @@ static inline unsigned long _pud_pfn(pud_t pud)
 
 static inline pmd_t *pud_pgtable(pud_t pud)
 {
-	return (pmd_t *)pfn_to_virt(pud_val(pud) >> _PAGE_PFN_SHIFT);
+	return (pmd_t *)pfn_to_virt((pud_val(pud) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
 }
 
 static inline struct page *pud_page(pud_t pud)
 {
-	return pfn_to_page(pud_val(pud) >> _PAGE_PFN_SHIFT);
+	return pfn_to_page((pud_val(pud) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
 }
 
 #define mm_pud_folded  mm_pud_folded
@@ -117,7 +125,7 @@ static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot)
 
 static inline unsigned long _pmd_pfn(pmd_t pmd)
 {
-	return pmd_val(pmd) >> _PAGE_PFN_SHIFT;
+	return (pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT;
 }
 
 #define mk_pmd(page, prot)    pfn_pmd(page_to_pfn(page), prot)
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index a6b0c89824c2..e571fa954afc 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -6,12 +6,6 @@
 #ifndef _ASM_RISCV_PGTABLE_BITS_H
 #define _ASM_RISCV_PGTABLE_BITS_H
 
-/*
- * PTE format:
- * | XLEN-1  10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- *       PFN      reserved for SW   D   A   G   U   X   W   R   V
- */
-
 #define _PAGE_ACCESSED_OFFSET 6
 
 #define _PAGE_PRESENT   (1 << 0)
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index e3549e50de95..6d31489818cd 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -259,12 +259,12 @@ static inline unsigned long _pgd_pfn(pgd_t pgd)
 
 static inline struct page *pmd_page(pmd_t pmd)
 {
-	return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
+	return pfn_to_page((pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
 }
 
 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
 {
-	return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
+	return (unsigned long)pfn_to_virt((pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
 }
 
 static inline pte_t pmd_pte(pmd_t pmd)
@@ -280,7 +280,7 @@ static inline pte_t pud_pte(pud_t pud)
 /* Yields the page frame number (PFN) of a page table entry */
 static inline unsigned long pte_pfn(pte_t pte)
 {
-	return (pte_val(pte) >> _PAGE_PFN_SHIFT);
+	return ((pte_val(pte) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
 }
 
 #define pte_page(x)     pfn_to_page(pte_pfn(x))
-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 10/13] riscv: add cpufeature handling via alternatives

[Heiko Stuebner]

Some cpufeatures should be handled via the alternatives mechanism
to not incur penalties on unsupporting variants.

So add a mechanism to handle these similar to cpu erratas.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/include/asm/alternative.h |  3 ++
 arch/riscv/include/asm/errata_list.h |  2 +
 arch/riscv/kernel/alternative.c      |  2 +
 arch/riscv/kernel/cpufeature.c       | 57 +++++++++++++++++++++++++++-
 4 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index f0657b1b3174..cf3b22173834 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -39,5 +39,8 @@ struct errata_checkfunc_id {
 void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 			      unsigned long archid, unsigned long impid,
 			      unsigned int stage);
+
+void riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end,
+				 unsigned int stage);
 #endif
 #endif
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 5f1046e82d9f..6b95bd9aee82 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -14,6 +14,8 @@
 #define	ERRATA_SIFIVE_NUMBER 2
 #endif
 
+#define	CPUFEATURE_NUMBER 0
+
 #ifdef __ASSEMBLY__
 
 #define ALT_INSN_FAULT(x)						\
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 223770b3945c..e6c9de9f9ba6 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -63,6 +63,8 @@ static void __init_or_module _apply_alternatives(struct alt_entry *begin,
 						 struct alt_entry *end,
 						 unsigned int stage)
 {
+	riscv_cpufeature_patch_func(begin, end, stage);
+
 	if (!vendor_patch_func)
 		return;
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index f3a4b0619aa0..92d4b4c25d47 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -8,9 +8,14 @@
 
 #include <linux/bitmap.h>
 #include <linux/ctype.h>
+#include <linux/module.h>
 #include <linux/of.h>
-#include <asm/processor.h>
+#include <asm/alternative.h>
+#include <asm/errata_list.h>
 #include <asm/hwcap.h>
+#include <asm/patch.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
 #include <asm/smp.h>
 #include <asm/switch_to.h>
 
@@ -237,3 +242,53 @@ void __init riscv_fill_hwcap(void)
 		static_branch_enable(&cpu_hwcap_fpu);
 #endif
 }
+
+struct cpufeature_info {
+	char name[ERRATA_STRING_LENGTH_MAX];
+	bool (*check_func)(unsigned int stage);
+};
+
+static const struct cpufeature_info __initdata_or_module cpufeature_list[CPUFEATURE_NUMBER] = {
+};
+
+static u32 __init_or_module cpufeature_probe(unsigned int stage)
+{
+	const struct cpufeature_info *info;
+	u32 cpu_req_feature = 0;
+	int idx;
+
+	for (idx = 0; idx < CPUFEATURE_NUMBER; idx++) {
+		info = &cpufeature_list[idx];
+
+		if (info->check_func(stage))
+			cpu_req_feature |= (1U << idx);
+	}
+
+	return cpu_req_feature;
+}
+
+void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
+						  struct alt_entry *end,
+						  unsigned int stage)
+{
+	u32 cpu_req_feature = cpufeature_probe(stage);
+	u32 cpu_apply_feature = 0;
+	struct alt_entry *alt;
+	u32 tmp;
+
+	for (alt = begin; alt < end; alt++) {
+		if (alt->vendor_id != 0)
+			continue;
+		if (alt->errata_id >= CPUFEATURE_NUMBER) {
+			WARN(1, "This feature id:%d is not in kernel cpufeature list",
+				alt->errata_id);
+			continue;
+		}
+
+		tmp = (1U << alt->errata_id);
+		if (cpu_req_feature & tmp) {
+			patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);
+			cpu_apply_feature |= tmp;
+		}
+	}
+}
-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 10/13] riscv: add cpufeature handling via alternatives

[Heiko Stuebner]

Some cpufeatures should be handled via the alternatives mechanism
to not incur penalties on unsupporting variants.

So add a mechanism to handle these similar to cpu erratas.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/include/asm/alternative.h |  3 ++
 arch/riscv/include/asm/errata_list.h |  2 +
 arch/riscv/kernel/alternative.c      |  2 +
 arch/riscv/kernel/cpufeature.c       | 57 +++++++++++++++++++++++++++-
 4 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index f0657b1b3174..cf3b22173834 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -39,5 +39,8 @@ struct errata_checkfunc_id {
 void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 			      unsigned long archid, unsigned long impid,
 			      unsigned int stage);
+
+void riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end,
+				 unsigned int stage);
 #endif
 #endif
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 5f1046e82d9f..6b95bd9aee82 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -14,6 +14,8 @@
 #define	ERRATA_SIFIVE_NUMBER 2
 #endif
 
+#define	CPUFEATURE_NUMBER 0
+
 #ifdef __ASSEMBLY__
 
 #define ALT_INSN_FAULT(x)						\
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 223770b3945c..e6c9de9f9ba6 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -63,6 +63,8 @@ static void __init_or_module _apply_alternatives(struct alt_entry *begin,
 						 struct alt_entry *end,
 						 unsigned int stage)
 {
+	riscv_cpufeature_patch_func(begin, end, stage);
+
 	if (!vendor_patch_func)
 		return;
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index f3a4b0619aa0..92d4b4c25d47 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -8,9 +8,14 @@
 
 #include <linux/bitmap.h>
 #include <linux/ctype.h>
+#include <linux/module.h>
 #include <linux/of.h>
-#include <asm/processor.h>
+#include <asm/alternative.h>
+#include <asm/errata_list.h>
 #include <asm/hwcap.h>
+#include <asm/patch.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
 #include <asm/smp.h>
 #include <asm/switch_to.h>
 
@@ -237,3 +242,53 @@ void __init riscv_fill_hwcap(void)
 		static_branch_enable(&cpu_hwcap_fpu);
 #endif
 }
+
+struct cpufeature_info {
+	char name[ERRATA_STRING_LENGTH_MAX];
+	bool (*check_func)(unsigned int stage);
+};
+
+static const struct cpufeature_info __initdata_or_module cpufeature_list[CPUFEATURE_NUMBER] = {
+};
+
+static u32 __init_or_module cpufeature_probe(unsigned int stage)
+{
+	const struct cpufeature_info *info;
+	u32 cpu_req_feature = 0;
+	int idx;
+
+	for (idx = 0; idx < CPUFEATURE_NUMBER; idx++) {
+		info = &cpufeature_list[idx];
+
+		if (info->check_func(stage))
+			cpu_req_feature |= (1U << idx);
+	}
+
+	return cpu_req_feature;
+}
+
+void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
+						  struct alt_entry *end,
+						  unsigned int stage)
+{
+	u32 cpu_req_feature = cpufeature_probe(stage);
+	u32 cpu_apply_feature = 0;
+	struct alt_entry *alt;
+	u32 tmp;
+
+	for (alt = begin; alt < end; alt++) {
+		if (alt->vendor_id != 0)
+			continue;
+		if (alt->errata_id >= CPUFEATURE_NUMBER) {
+			WARN(1, "This feature id:%d is not in kernel cpufeature list",
+				alt->errata_id);
+			continue;
+		}
+
+		tmp = (1U << alt->errata_id);
+		if (cpu_req_feature & tmp) {
+			patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);
+			cpu_apply_feature |= tmp;
+		}
+	}
+}
-- 
2.30.2

[PATCH v7 11/13] riscv: add RISC-V Svpbmt extension support

[Heiko Stuebner]

From: Wei Fu <wefu@redhat.com>

Svpbmt (the S should be capitalized) is the
"Supervisor-mode: page-based memory types" extension
that specifies attributes for cacheability, idempotency
and ordering.

The relevant settings are done in special bits in PTEs:

Here is the svpbmt PTE format:
| 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  N     MT     RSW    D   A   G   U   X   W   R   V
        ^

Of the Reserved bits [63:54] in a leaf PTE, the high bit is already
allocated (as the N bit), so bits [62:61] are used as the MT (aka
MemType) field. This field specifies one of three memory types that
are close equivalents (or equivalent in effect) to the three main x86
and ARMv8 memory types - as shown in the following table.

RISC-V
Encoding &
MemType     RISC-V Description
----------  ------------------------------------------------
00 - PMA    Normal Cacheable, No change to implied PMA memory type
01 - NC     Non-cacheable, idempotent, weakly-ordered Main Memory
10 - IO     Non-cacheable, non-idempotent, strongly-ordered I/O memory
11 - Rsvd   Reserved for future standard use

As the extension will not be present on all implementations use
alternatives to check its existence at runtime and if needed
adapt the code to use memory-types.

Signed-off-by: Wei Fu <wefu@redhat.com>
Co-developed-by: Liu Shaohua <liush@allwinnertech.com>
Signed-off-by: Liu Shaohua <liush@allwinnertech.com>
Co-developed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Guo Ren <guoren@kernel.org>
[moved to use the alternatives mechanism]
Co-developed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Drew Fustini <drew@beagleboard.org>
Cc: Wei Fu <wefu@redhat.com>
Cc: Wei Wu <lazyparser@gmail.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime@cerno.tech>
Cc: Daniel Lustig <dlustig@nvidia.com>
Cc: Greg Favor <gfavor@ventanamicro.com>
Cc: Andrea Mondelli <andrea.mondelli@huawei.com>
Cc: Jonathan Behrens <behrensj@mit.edu>
Cc: Xinhaoqu (Freddie) <xinhaoqu@huawei.com>
Cc: Bill Huffman <huffman@cadence.com>
Cc: Nick Kossifidis <mick@ics.forth.gr>
Cc: Allen Baum <allen.baum@esperantotech.com>
Cc: Josh Scheid <jscheid@ventanamicro.com>
Cc: Richard Trauben <rtrauben@gmail.com>
---
 arch/riscv/include/asm/errata_list.h  | 13 +++++++-
 arch/riscv/include/asm/hwcap.h        |  1 +
 arch/riscv/include/asm/pgtable-32.h   |  9 +++++
 arch/riscv/include/asm/pgtable-64.h   | 47 +++++++++++++++++++++++++++
 arch/riscv/include/asm/pgtable-bits.h |  4 ---
 arch/riscv/include/asm/pgtable.h      | 29 ++++++++++++++---
 arch/riscv/kernel/cpu.c               |  1 +
 arch/riscv/kernel/cpufeature.c        | 18 ++++++++++
 8 files changed, 112 insertions(+), 10 deletions(-)

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 6b95bd9aee82..a4a9b0842922 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -14,7 +14,8 @@
 #define	ERRATA_SIFIVE_NUMBER 2
 #endif
 
-#define	CPUFEATURE_NUMBER 0
+#define	CPUFEATURE_SVPBMT 0
+#define	CPUFEATURE_NUMBER 1
 
 #ifdef __ASSEMBLY__
 
@@ -36,6 +37,16 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID,	\
 		ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200)	\
 		: : "r" (addr) : "memory")
 
+/*
+ * _val is marked as "will be overwritten", so need to set it to 0
+ * in the default case.
+ */
+#define ALT_SVPBMT_SHIFT 61
+#define ALT_SVPBMT(_val, prot)						\
+asm(ALTERNATIVE("li %0, 0\t\nnop", "li %0, %1\t\nslli %0,%0,%2", 0,	\
+		CPUFEATURE_SVPBMT, CONFIG_64BIT)			\
+		: "=r"(_val) : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), "I"(ALT_SVPBMT_SHIFT))
+
 #endif /* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 691fc9c8099b..656cd626eb1a 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -51,6 +51,7 @@ extern unsigned long elf_hwcap;
  * available logical extension id.
  */
 enum riscv_isa_ext_id {
+	RISCV_ISA_EXT_SVPBMT = RISCV_ISA_EXT_BASE,
 	RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
 };
 
diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
index e266a4fe7f43..59ba1fbaf784 100644
--- a/arch/riscv/include/asm/pgtable-32.h
+++ b/arch/riscv/include/asm/pgtable-32.h
@@ -24,4 +24,13 @@
  */
 #define _PAGE_PFN_MASK  GENMASK(31, 10)
 
+#define _PAGE_NOCACHE		0
+#define _PAGE_IO		0
+#define _PAGE_MTMASK		0
+
+/* Set of bits to preserve across pte_modify() */
+#define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
+					  _PAGE_WRITE | _PAGE_EXEC |	\
+					  _PAGE_USER | _PAGE_GLOBAL))
+
 #endif /* _ASM_RISCV_PGTABLE_32_H */
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 9412c6157c88..07ba3416cb19 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -8,6 +8,7 @@
 
 #include <linux/bits.h>
 #include <linux/const.h>
+#include <asm/errata_list.h>
 
 extern bool pgtable_l4_enabled;
 
@@ -56,6 +57,52 @@ typedef struct {
  */
 #define _PAGE_PFN_MASK  GENMASK(53, 10)
 
+/*
+ * [62:61] Svpbmt Memory Type definitions:
+ *
+ *  00 - PMA    Normal Cacheable, No change to implied PMA memory type
+ *  01 - NC     Non-cacheable, idempotent, weakly-ordered Main Memory
+ *  10 - IO     Non-cacheable, non-idempotent, strongly-ordered I/O memory
+ *  11 - Rsvd   Reserved for future standard use
+ */
+#define _PAGE_NOCACHE_SVPBMT	(1UL << 61)
+#define _PAGE_IO_SVPBMT		(1UL << 62)
+#define _PAGE_MTMASK_SVPBMT	(_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
+
+static inline u64 riscv_page_mtmask(void)
+{
+	u64 val;
+
+	ALT_SVPBMT(val, _PAGE_MTMASK);
+	return val;
+}
+
+static inline u64 riscv_page_nocache(void)
+{
+	u64 val;
+
+	ALT_SVPBMT(val, _PAGE_NOCACHE);
+	return val;
+}
+
+static inline u64 riscv_page_io(void)
+{
+	u64 val;
+
+	ALT_SVPBMT(val, _PAGE_IO);
+	return val;
+}
+
+#define _PAGE_NOCACHE		riscv_page_nocache()
+#define _PAGE_IO		riscv_page_io()
+#define _PAGE_MTMASK		riscv_page_mtmask()
+
+/* Set of bits to preserve across pte_modify() */
+#define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
+					  _PAGE_WRITE | _PAGE_EXEC |	\
+					  _PAGE_USER | _PAGE_GLOBAL |	\
+					  _PAGE_MTMASK))
+
 static inline int pud_present(pud_t pud)
 {
 	return (pud_val(pud) & _PAGE_PRESENT);
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index e571fa954afc..b9e13a8fe2b7 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -29,10 +29,6 @@
 
 #define _PAGE_PFN_SHIFT 10
 
-/* Set of bits to preserve across pte_modify() */
-#define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
-					  _PAGE_WRITE | _PAGE_EXEC |	\
-					  _PAGE_USER | _PAGE_GLOBAL))
 /*
  * when all of R/W/X are zero, the PTE is a pointer to the next level
  * of the page table; otherwise, it is a leaf PTE.
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 6d31489818cd..009a17f94b86 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -175,11 +175,8 @@ extern struct pt_alloc_ops pt_ops __initdata;
 
 #define PAGE_TABLE		__pgprot(_PAGE_TABLE)
 
-/*
- * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
- * change the properties of memory regions.
- */
-#define _PAGE_IOREMAP _PAGE_KERNEL
+#define _PAGE_IOREMAP	((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO)
+#define PAGE_KERNEL_IO		__pgprot(_PAGE_IOREMAP)
 
 extern pgd_t swapper_pg_dir[];
 
@@ -519,6 +516,28 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
 	return ptep_test_and_clear_young(vma, address, ptep);
 }
 
+#define pgprot_noncached pgprot_noncached
+static inline pgprot_t pgprot_noncached(pgprot_t _prot)
+{
+	unsigned long prot = pgprot_val(_prot);
+
+	prot &= ~_PAGE_MTMASK;
+	prot |= _PAGE_IO;
+
+	return __pgprot(prot);
+}
+
+#define pgprot_writecombine pgprot_writecombine
+static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
+{
+	unsigned long prot = pgprot_val(_prot);
+
+	prot &= ~_PAGE_MTMASK;
+	prot |= _PAGE_NOCACHE;
+
+	return __pgprot(prot);
+}
+
 /*
  * THP functions
  */
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 031ad15a059f..c582d557e555 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -71,6 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node)
 	}
 
 static struct riscv_isa_ext_data isa_ext_arr[] = {
+	__RISCV_ISA_EXT_DATA("svpbmt", RISCV_ISA_EXT_SVPBMT),
 	__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
 };
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 92d4b4c25d47..1422d9897310 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -8,6 +8,7 @@
 
 #include <linux/bitmap.h>
 #include <linux/ctype.h>
+#include <linux/libfdt.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <asm/alternative.h>
@@ -197,6 +198,8 @@ void __init riscv_fill_hwcap(void)
 			if (!ext_long) {
 				this_hwcap |= isa2hwcap[(unsigned char)(*ext)];
 				set_bit(*ext - 'a', this_isa);
+			} else {
+				SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
 			}
 #undef SET_ISA_EXT_MAP
 		}
@@ -248,7 +251,22 @@ struct cpufeature_info {
 	bool (*check_func)(unsigned int stage);
 };
 
+static bool __init_or_module cpufeature_svpbmt_check_func(unsigned int stage)
+{
+	bool ret = false;
+
+#if defined(CONFIG_MMU) && defined(CONFIG_64BIT)
+	return riscv_isa_extension_available(NULL, SVPBMT);
+#endif
+
+	return ret;
+}
+
 static const struct cpufeature_info __initdata_or_module cpufeature_list[CPUFEATURE_NUMBER] = {
+	{
+		.name = "svpbmt",
+		.check_func = cpufeature_svpbmt_check_func
+	},
 };
 
 static u32 __init_or_module cpufeature_probe(unsigned int stage)
-- 
2.30.2

[PATCH v7 11/13] riscv: add RISC-V Svpbmt extension support

[Heiko Stuebner]

From: Wei Fu <wefu@redhat.com>

Svpbmt (the S should be capitalized) is the
"Supervisor-mode: page-based memory types" extension
that specifies attributes for cacheability, idempotency
and ordering.

The relevant settings are done in special bits in PTEs:

Here is the svpbmt PTE format:
| 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  N     MT     RSW    D   A   G   U   X   W   R   V
        ^

Of the Reserved bits [63:54] in a leaf PTE, the high bit is already
allocated (as the N bit), so bits [62:61] are used as the MT (aka
MemType) field. This field specifies one of three memory types that
are close equivalents (or equivalent in effect) to the three main x86
and ARMv8 memory types - as shown in the following table.

RISC-V
Encoding &
MemType     RISC-V Description
----------  ------------------------------------------------
00 - PMA    Normal Cacheable, No change to implied PMA memory type
01 - NC     Non-cacheable, idempotent, weakly-ordered Main Memory
10 - IO     Non-cacheable, non-idempotent, strongly-ordered I/O memory
11 - Rsvd   Reserved for future standard use

As the extension will not be present on all implementations use
alternatives to check its existence at runtime and if needed
adapt the code to use memory-types.

Signed-off-by: Wei Fu <wefu@redhat.com>
Co-developed-by: Liu Shaohua <liush@allwinnertech.com>
Signed-off-by: Liu Shaohua <liush@allwinnertech.com>
Co-developed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Guo Ren <guoren@kernel.org>
[moved to use the alternatives mechanism]
Co-developed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Drew Fustini <drew@beagleboard.org>
Cc: Wei Fu <wefu@redhat.com>
Cc: Wei Wu <lazyparser@gmail.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime@cerno.tech>
Cc: Daniel Lustig <dlustig@nvidia.com>
Cc: Greg Favor <gfavor@ventanamicro.com>
Cc: Andrea Mondelli <andrea.mondelli@huawei.com>
Cc: Jonathan Behrens <behrensj@mit.edu>
Cc: Xinhaoqu (Freddie) <xinhaoqu@huawei.com>
Cc: Bill Huffman <huffman@cadence.com>
Cc: Nick Kossifidis <mick@ics.forth.gr>
Cc: Allen Baum <allen.baum@esperantotech.com>
Cc: Josh Scheid <jscheid@ventanamicro.com>
Cc: Richard Trauben <rtrauben@gmail.com>
---
 arch/riscv/include/asm/errata_list.h  | 13 +++++++-
 arch/riscv/include/asm/hwcap.h        |  1 +
 arch/riscv/include/asm/pgtable-32.h   |  9 +++++
 arch/riscv/include/asm/pgtable-64.h   | 47 +++++++++++++++++++++++++++
 arch/riscv/include/asm/pgtable-bits.h |  4 ---
 arch/riscv/include/asm/pgtable.h      | 29 ++++++++++++++---
 arch/riscv/kernel/cpu.c               |  1 +
 arch/riscv/kernel/cpufeature.c        | 18 ++++++++++
 8 files changed, 112 insertions(+), 10 deletions(-)

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 6b95bd9aee82..a4a9b0842922 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -14,7 +14,8 @@
 #define	ERRATA_SIFIVE_NUMBER 2
 #endif
 
-#define	CPUFEATURE_NUMBER 0
+#define	CPUFEATURE_SVPBMT 0
+#define	CPUFEATURE_NUMBER 1
 
 #ifdef __ASSEMBLY__
 
@@ -36,6 +37,16 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID,	\
 		ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200)	\
 		: : "r" (addr) : "memory")
 
+/*
+ * _val is marked as "will be overwritten", so need to set it to 0
+ * in the default case.
+ */
+#define ALT_SVPBMT_SHIFT 61
+#define ALT_SVPBMT(_val, prot)						\
+asm(ALTERNATIVE("li %0, 0\t\nnop", "li %0, %1\t\nslli %0,%0,%2", 0,	\
+		CPUFEATURE_SVPBMT, CONFIG_64BIT)			\
+		: "=r"(_val) : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), "I"(ALT_SVPBMT_SHIFT))
+
 #endif /* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 691fc9c8099b..656cd626eb1a 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -51,6 +51,7 @@ extern unsigned long elf_hwcap;
  * available logical extension id.
  */
 enum riscv_isa_ext_id {
+	RISCV_ISA_EXT_SVPBMT = RISCV_ISA_EXT_BASE,
 	RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
 };
 
diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
index e266a4fe7f43..59ba1fbaf784 100644
--- a/arch/riscv/include/asm/pgtable-32.h
+++ b/arch/riscv/include/asm/pgtable-32.h
@@ -24,4 +24,13 @@
  */
 #define _PAGE_PFN_MASK  GENMASK(31, 10)
 
+#define _PAGE_NOCACHE		0
+#define _PAGE_IO		0
+#define _PAGE_MTMASK		0
+
+/* Set of bits to preserve across pte_modify() */
+#define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
+					  _PAGE_WRITE | _PAGE_EXEC |	\
+					  _PAGE_USER | _PAGE_GLOBAL))
+
 #endif /* _ASM_RISCV_PGTABLE_32_H */
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 9412c6157c88..07ba3416cb19 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -8,6 +8,7 @@
 
 #include <linux/bits.h>
 #include <linux/const.h>
+#include <asm/errata_list.h>
 
 extern bool pgtable_l4_enabled;
 
@@ -56,6 +57,52 @@ typedef struct {
  */
 #define _PAGE_PFN_MASK  GENMASK(53, 10)
 
+/*
+ * [62:61] Svpbmt Memory Type definitions:
+ *
+ *  00 - PMA    Normal Cacheable, No change to implied PMA memory type
+ *  01 - NC     Non-cacheable, idempotent, weakly-ordered Main Memory
+ *  10 - IO     Non-cacheable, non-idempotent, strongly-ordered I/O memory
+ *  11 - Rsvd   Reserved for future standard use
+ */
+#define _PAGE_NOCACHE_SVPBMT	(1UL << 61)
+#define _PAGE_IO_SVPBMT		(1UL << 62)
+#define _PAGE_MTMASK_SVPBMT	(_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
+
+static inline u64 riscv_page_mtmask(void)
+{
+	u64 val;
+
+	ALT_SVPBMT(val, _PAGE_MTMASK);
+	return val;
+}
+
+static inline u64 riscv_page_nocache(void)
+{
+	u64 val;
+
+	ALT_SVPBMT(val, _PAGE_NOCACHE);
+	return val;
+}
+
+static inline u64 riscv_page_io(void)
+{
+	u64 val;
+
+	ALT_SVPBMT(val, _PAGE_IO);
+	return val;
+}
+
+#define _PAGE_NOCACHE		riscv_page_nocache()
+#define _PAGE_IO		riscv_page_io()
+#define _PAGE_MTMASK		riscv_page_mtmask()
+
+/* Set of bits to preserve across pte_modify() */
+#define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
+					  _PAGE_WRITE | _PAGE_EXEC |	\
+					  _PAGE_USER | _PAGE_GLOBAL |	\
+					  _PAGE_MTMASK))
+
 static inline int pud_present(pud_t pud)
 {
 	return (pud_val(pud) & _PAGE_PRESENT);
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index e571fa954afc..b9e13a8fe2b7 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -29,10 +29,6 @@
 
 #define _PAGE_PFN_SHIFT 10
 
-/* Set of bits to preserve across pte_modify() */
-#define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
-					  _PAGE_WRITE | _PAGE_EXEC |	\
-					  _PAGE_USER | _PAGE_GLOBAL))
 /*
  * when all of R/W/X are zero, the PTE is a pointer to the next level
  * of the page table; otherwise, it is a leaf PTE.
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 6d31489818cd..009a17f94b86 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -175,11 +175,8 @@ extern struct pt_alloc_ops pt_ops __initdata;
 
 #define PAGE_TABLE		__pgprot(_PAGE_TABLE)
 
-/*
- * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
- * change the properties of memory regions.
- */
-#define _PAGE_IOREMAP _PAGE_KERNEL
+#define _PAGE_IOREMAP	((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO)
+#define PAGE_KERNEL_IO		__pgprot(_PAGE_IOREMAP)
 
 extern pgd_t swapper_pg_dir[];
 
@@ -519,6 +516,28 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
 	return ptep_test_and_clear_young(vma, address, ptep);
 }
 
+#define pgprot_noncached pgprot_noncached
+static inline pgprot_t pgprot_noncached(pgprot_t _prot)
+{
+	unsigned long prot = pgprot_val(_prot);
+
+	prot &= ~_PAGE_MTMASK;
+	prot |= _PAGE_IO;
+
+	return __pgprot(prot);
+}
+
+#define pgprot_writecombine pgprot_writecombine
+static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
+{
+	unsigned long prot = pgprot_val(_prot);
+
+	prot &= ~_PAGE_MTMASK;
+	prot |= _PAGE_NOCACHE;
+
+	return __pgprot(prot);
+}
+
 /*
  * THP functions
  */
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 031ad15a059f..c582d557e555 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -71,6 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node)
 	}
 
 static struct riscv_isa_ext_data isa_ext_arr[] = {
+	__RISCV_ISA_EXT_DATA("svpbmt", RISCV_ISA_EXT_SVPBMT),
 	__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
 };
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 92d4b4c25d47..1422d9897310 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -8,6 +8,7 @@
 
 #include <linux/bitmap.h>
 #include <linux/ctype.h>
+#include <linux/libfdt.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <asm/alternative.h>
@@ -197,6 +198,8 @@ void __init riscv_fill_hwcap(void)
 			if (!ext_long) {
 				this_hwcap |= isa2hwcap[(unsigned char)(*ext)];
 				set_bit(*ext - 'a', this_isa);
+			} else {
+				SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
 			}
 #undef SET_ISA_EXT_MAP
 		}
@@ -248,7 +251,22 @@ struct cpufeature_info {
 	bool (*check_func)(unsigned int stage);
 };
 
+static bool __init_or_module cpufeature_svpbmt_check_func(unsigned int stage)
+{
+	bool ret = false;
+
+#if defined(CONFIG_MMU) && defined(CONFIG_64BIT)
+	return riscv_isa_extension_available(NULL, SVPBMT);
+#endif
+
+	return ret;
+}
+
 static const struct cpufeature_info __initdata_or_module cpufeature_list[CPUFEATURE_NUMBER] = {
+	{
+		.name = "svpbmt",
+		.check_func = cpufeature_svpbmt_check_func
+	},
 };
 
 static u32 __init_or_module cpufeature_probe(unsigned int stage)
-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 12/13] riscv: remove FIXMAP_PAGE_IO and fall back to its default value

[Heiko Stuebner]

If not defined in the arch, FIXMAP_PAGE_IO defaults to PAGE_KERNEL_IO,
which we defined when adding the svpbmt implementation.

So drop the FIXMAP_PAGE_IO riscv define.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/include/asm/fixmap.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h
index 58a718573ad6..692e25e56d8e 100644
--- a/arch/riscv/include/asm/fixmap.h
+++ b/arch/riscv/include/asm/fixmap.h
@@ -44,8 +44,6 @@ enum fixed_addresses {
 	__end_of_fixed_addresses
 };
 
-#define FIXMAP_PAGE_IO		PAGE_KERNEL
-
 #define __early_set_fixmap	__set_fixmap
 
 #define __late_set_fixmap	__set_fixmap
-- 
2.30.2

[PATCH v7 12/13] riscv: remove FIXMAP_PAGE_IO and fall back to its default value

[Heiko Stuebner]

If not defined in the arch, FIXMAP_PAGE_IO defaults to PAGE_KERNEL_IO,
which we defined when adding the svpbmt implementation.

So drop the FIXMAP_PAGE_IO riscv define.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/include/asm/fixmap.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h
index 58a718573ad6..692e25e56d8e 100644
--- a/arch/riscv/include/asm/fixmap.h
+++ b/arch/riscv/include/asm/fixmap.h
@@ -44,8 +44,6 @@ enum fixed_addresses {
 	__end_of_fixed_addresses
 };
 
-#define FIXMAP_PAGE_IO		PAGE_KERNEL
-
 #define __early_set_fixmap	__set_fixmap
 
 #define __late_set_fixmap	__set_fixmap
-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 13/13] riscv: add memory-type errata for T-Head

[Heiko Stuebner]

Some current cpus based on T-Head cores implement memory-types
way different than described in the svpbmt spec even going
so far as using PTE bits marked as reserved.

Add the T-Head vendor-id and necessary errata code to
replace the affected instructions.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Samuel Holland <samuel@sholland.org>
---
 arch/riscv/Kconfig.erratas             | 19 ++++++
 arch/riscv/errata/Makefile             |  1 +
 arch/riscv/errata/sifive/errata.c      |  7 ++-
 arch/riscv/errata/thead/Makefile       |  1 +
 arch/riscv/errata/thead/errata.c       | 85 ++++++++++++++++++++++++++
 arch/riscv/include/asm/alternative.h   |  5 ++
 arch/riscv/include/asm/errata_list.h   | 47 ++++++++++++--
 arch/riscv/include/asm/pgtable-64.h    | 18 +++++-
 arch/riscv/include/asm/pgtable.h       | 18 +++++-
 arch/riscv/include/asm/vendorid_list.h |  1 +
 arch/riscv/kernel/alternative.c        | 14 +++++
 arch/riscv/kernel/cpufeature.c         |  7 ++-
 arch/riscv/mm/init.c                   |  1 +
 13 files changed, 214 insertions(+), 10 deletions(-)
 create mode 100644 arch/riscv/errata/thead/Makefile
 create mode 100644 arch/riscv/errata/thead/errata.c

diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
index d18be8ff0245..de4002baa1d0 100644
--- a/arch/riscv/Kconfig.erratas
+++ b/arch/riscv/Kconfig.erratas
@@ -31,4 +31,23 @@ config ERRATA_SIFIVE_CIP_1200
 
 	  If you don't know what to do here, say "Y".
 
+config ERRATA_THEAD
+	bool "T-HEAD errata"
+	help
+	  All T-HEAD errata Kconfig depend on this Kconfig. Disabling
+	  this Kconfig will disable all T-HEAD errata. Please say "Y"
+	  here if your platform uses T-HEAD CPU cores.
+
+	  Otherwise, please say "N" here to avoid unnecessary overhead.
+
+config ERRATA_THEAD_PBMT
+	bool "Apply T-Head memory type errata"
+	depends on ERRATA_THEAD && 64BIT
+	default y
+	help
+	  This will apply the memory type errata to handle the non-standard
+	  memory type bits in page-table-entries on T-Head SoCs.
+
+	  If you don't know what to do here, say "Y".
+
 endmenu
diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
index 0ca1c5281a2d..a1055965fbee 100644
--- a/arch/riscv/errata/Makefile
+++ b/arch/riscv/errata/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
+obj-$(CONFIG_ERRATA_THEAD) += thead/
diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
index 42457efcaaa3..0b14d5475573 100644
--- a/arch/riscv/errata/sifive/errata.c
+++ b/arch/riscv/errata/sifive/errata.c
@@ -85,10 +85,15 @@ void __init_or_module sifive_errata_patch_func(struct alt_entry *begin, struct a
 				     unsigned int stage)
 {
 	struct alt_entry *alt;
-	u32 cpu_req_errata = sifive_errata_probe(archid, impid);
+	u32 cpu_req_errata;
 	u32 cpu_apply_errata = 0;
 	u32 tmp;
 
+	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+		return;
+
+	cpu_req_errata = sifive_errata_probe(archid, impid);
+
 	for (alt = begin; alt < end; alt++) {
 		if (alt->vendor_id != SIFIVE_VENDOR_ID)
 			continue;
diff --git a/arch/riscv/errata/thead/Makefile b/arch/riscv/errata/thead/Makefile
new file mode 100644
index 000000000000..2d644e19caef
--- /dev/null
+++ b/arch/riscv/errata/thead/Makefile
@@ -0,0 +1 @@
+obj-y += errata.o
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
new file mode 100644
index 000000000000..fd8e0538a3f0
--- /dev/null
+++ b/arch/riscv/errata/thead/errata.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 Heiko Stuebner <heiko@sntech.de>
+ */
+
+#include <linux/bug.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <asm/alternative.h>
+#include <asm/cacheflush.h>
+#include <asm/errata_list.h>
+#include <asm/patch.h>
+#include <asm/vendorid_list.h>
+
+struct errata_info {
+	char name[ERRATA_STRING_LENGTH_MAX];
+	bool (*check_func)(unsigned long arch_id, unsigned long impid);
+	unsigned int stage;
+};
+
+static bool errata_mt_check_func(unsigned long  arch_id, unsigned long impid)
+{
+	if (arch_id != 0 || impid != 0)
+		return false;
+	return true;
+}
+
+static const struct errata_info errata_list[ERRATA_THEAD_NUMBER] = {
+	{
+		.name = "memory-types",
+		.stage = RISCV_ALTERNATIVES_EARLY_BOOT,
+		.check_func = errata_mt_check_func
+	},
+};
+
+static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid)
+{
+	const struct errata_info *info;
+	u32 cpu_req_errata = 0;
+	int idx;
+
+	for (idx = 0; idx < ERRATA_THEAD_NUMBER; idx++) {
+		info = &errata_list[idx];
+
+		if ((stage == RISCV_ALTERNATIVES_MODULE ||
+		     info->stage == stage) && info->check_func(archid, impid))
+			cpu_req_errata |= (1U << idx);
+	}
+
+	return cpu_req_errata;
+}
+
+void __init_or_module thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+					      unsigned long archid, unsigned long impid,
+					      unsigned int stage)
+{
+	struct alt_entry *alt;
+	u32 cpu_req_errata = thead_errata_probe(stage, archid, impid);
+	u32 cpu_apply_errata = 0;
+	u32 tmp;
+
+	for (alt = begin; alt < end; alt++) {
+		if (alt->vendor_id != THEAD_VENDOR_ID)
+			continue;
+		if (alt->errata_id >= ERRATA_THEAD_NUMBER)
+			continue;
+
+		tmp = (1U << alt->errata_id);
+		if (cpu_req_errata & tmp) {
+			/* On vm-alternatives, the mmu isn't running yet */
+			if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+				memcpy((void *)__pa_symbol(alt->old_ptr),
+				       (void *)__pa_symbol(alt->alt_ptr), alt->alt_len);
+			else
+				patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);
+
+			cpu_apply_errata |= tmp;
+		}
+	}
+
+	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+		local_flush_icache_all();
+}
diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index cf3b22173834..d1154c91ab03 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -19,8 +19,10 @@
 
 #define RISCV_ALTERNATIVES_BOOT		0 /* alternatives applied during regular boot */
 #define RISCV_ALTERNATIVES_MODULE	1 /* alternatives applied during module-init */
+#define RISCV_ALTERNATIVES_EARLY_BOOT	2 /* alternatives applied before mmu start */
 
 void __init apply_boot_alternatives(void);
+void __init apply_early_boot_alternatives(void);
 void apply_module_alternatives(void *start, size_t length);
 
 struct alt_entry {
@@ -39,6 +41,9 @@ struct errata_checkfunc_id {
 void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 			      unsigned long archid, unsigned long impid,
 			      unsigned int stage);
+void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+			     unsigned long archid, unsigned long impid,
+			     unsigned int stage);
 
 void riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end,
 				 unsigned int stage);
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index a4a9b0842922..4fac46b82c16 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -14,6 +14,11 @@
 #define	ERRATA_SIFIVE_NUMBER 2
 #endif
 
+#ifdef CONFIG_ERRATA_THEAD
+#define	ERRATA_THEAD_PBMT 0
+#define	ERRATA_THEAD_NUMBER 1
+#endif
+
 #define	CPUFEATURE_SVPBMT 0
 #define	CPUFEATURE_NUMBER 1
 
@@ -42,10 +47,44 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID,	\
  * in the default case.
  */
 #define ALT_SVPBMT_SHIFT 61
-#define ALT_SVPBMT(_val, prot)						\
-asm(ALTERNATIVE("li %0, 0\t\nnop", "li %0, %1\t\nslli %0,%0,%2", 0,	\
-		CPUFEATURE_SVPBMT, CONFIG_64BIT)			\
-		: "=r"(_val) : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), "I"(ALT_SVPBMT_SHIFT))
+#define ALT_THEAD_PBMT_SHIFT 59
+#define ALT_SVPBMT(_val, prot)								\
+asm(ALTERNATIVE_2("li %0, 0\t\nnop",							\
+		  "li %0, %1\t\nslli %0,%0,%3", 0, CPUFEATURE_SVPBMT, CONFIG_64BIT,	\
+		  "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, ERRATA_THEAD_PBMT,	\
+						CONFIG_ERRATA_THEAD_PBMT)		\
+		: "=r"(_val) : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),			\
+			       "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
+			       "I"(ALT_SVPBMT_SHIFT), "I"(ALT_THEAD_PBMT_SHIFT))
+
+#ifdef CONFIG_ERRATA_THEAD_PBMT
+/*
+ * IO/NOCACHE memory types are handled together with svpbmt,
+ * so on T-Head chips, check if no other memory type is set,
+ * and set the non-0 PMA type if applicable.
+ */
+#define ALT_THEAD_PMA(_val)								\
+asm volatile(ALTERNATIVE(								\
+	"nop\n\t"									\
+	"nop\n\t"									\
+	"nop\n\t"									\
+	"nop\n\t"									\
+	"nop\n\t"									\
+	"nop\n\t"									\
+	"nop",										\
+	"li      t3, %2\n\t"								\
+	"slli    t3, t3, %4\n\t"							\
+	"and     t3, %0, t3\n\t"							\
+	"bne     t3, zero, 2f\n\t"							\
+	"li      t3, %3\n\t"								\
+	"slli    t3, t3, %4\n\t"							\
+	"or      %0, %0, t3\n\t"							\
+	"2:",  THEAD_VENDOR_ID, ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)		\
+	: "+r"(_val) : "0"(_val), "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT),	\
+		       "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT),  "I"(ALT_THEAD_PBMT_SHIFT))
+#else
+#define ALT_THEAD_PMA(_val)
+#endif
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 07ba3416cb19..6d59e4695200 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -69,6 +69,18 @@ typedef struct {
 #define _PAGE_IO_SVPBMT		(1UL << 62)
 #define _PAGE_MTMASK_SVPBMT	(_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
 
+/*
+ * [63:59] T-Head Memory Type definitions:
+ *
+ * 00000 - NC   Weakly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
+ * 01110 - PMA  Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable
+ * 10000 - IO   Strongly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
+ */
+#define _PAGE_PMA_THEAD		((1UL << 62) | (1UL << 61) | (1UL << 60))
+#define _PAGE_NOCACHE_THEAD	0UL
+#define _PAGE_IO_THEAD		(1UL << 63)
+#define _PAGE_MTMASK_THEAD	(_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
+
 static inline u64 riscv_page_mtmask(void)
 {
 	u64 val;
@@ -167,7 +179,11 @@ static inline bool mm_pud_folded(struct mm_struct *mm)
 
 static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot)
 {
-	return __pmd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+	unsigned long prot_val = pgprot_val(prot);
+
+	ALT_THEAD_PMA(prot_val);
+
+	return __pmd((pfn << _PAGE_PFN_SHIFT) | prot_val);
 }
 
 static inline unsigned long _pmd_pfn(pmd_t pmd)
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 009a17f94b86..e2658a25f06d 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -246,7 +246,11 @@ static inline void pmd_clear(pmd_t *pmdp)
 
 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot)
 {
-	return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+	unsigned long prot_val = pgprot_val(prot);
+
+	ALT_THEAD_PMA(prot_val);
+
+	return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val);
 }
 
 static inline unsigned long _pgd_pfn(pgd_t pgd)
@@ -285,7 +289,11 @@ static inline unsigned long pte_pfn(pte_t pte)
 /* Constructs a page table entry */
 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
 {
-	return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+	unsigned long prot_val = pgprot_val(prot);
+
+	ALT_THEAD_PMA(prot_val);
+
+	return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val);
 }
 
 #define mk_pte(page, prot)       pfn_pte(page_to_pfn(page), prot)
@@ -394,7 +402,11 @@ static inline int pmd_protnone(pmd_t pmd)
 /* Modify page protection bits */
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
-	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
+	unsigned long newprot_val = pgprot_val(newprot);
+
+	ALT_THEAD_PMA(newprot_val);
+
+	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val);
 }
 
 #define pgd_ERROR(e) \
diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index 9d934215b3c8..cb89af3f0704 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -6,5 +6,6 @@
 #define ASM_VENDOR_LIST_H
 
 #define SIFIVE_VENDOR_ID	0x489
+#define THEAD_VENDOR_ID		0x5b7
 
 #endif
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index e6c9de9f9ba6..3f6ad91f524c 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -48,6 +48,11 @@ static void __init init_alternative(void)
 	case SIFIVE_VENDOR_ID:
 		vendor_patch_func = sifive_errata_patch_func;
 		break;
+#endif
+#ifdef CONFIG_ERRATA_THEAD
+	case THEAD_VENDOR_ID:
+		vendor_patch_func = thead_errata_patch_func;
+		break;
 #endif
 	default:
 		vendor_patch_func = NULL;
@@ -85,6 +90,15 @@ void __init apply_boot_alternatives(void)
 			    RISCV_ALTERNATIVES_BOOT);
 }
 
+void __init apply_early_boot_alternatives(void)
+{
+	init_alternative();
+
+	_apply_alternatives((struct alt_entry *)__alt_start,
+			    (struct alt_entry *)__alt_end,
+			    RISCV_ALTERNATIVES_EARLY_BOOT);
+}
+
 #ifdef CONFIG_MODULES
 void apply_module_alternatives(void *start, size_t length)
 {
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 1422d9897310..5c5e6e7488ce 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -256,7 +256,12 @@ static bool __init_or_module cpufeature_svpbmt_check_func(unsigned int stage)
 	bool ret = false;
 
 #if defined(CONFIG_MMU) && defined(CONFIG_64BIT)
-	return riscv_isa_extension_available(NULL, SVPBMT);
+	switch (stage) {
+	case RISCV_ALTERNATIVES_EARLY_BOOT:
+		return false;
+	default:
+		return riscv_isa_extension_available(NULL, SVPBMT);
+	}
 #endif
 
 	return ret;
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 0d588032d6e6..245d54a3616c 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -821,6 +821,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
 	BUG_ON((kernel_map.virt_addr + kernel_map.size) > ADDRESS_SPACE_END - SZ_4K);
 #endif
 
+	apply_early_boot_alternatives();
 	pt_ops_set_early();
 
 	/* Setup early PGD for fixmap */
-- 
2.30.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v7 13/13] riscv: add memory-type errata for T-Head

[Heiko Stuebner]

Some current cpus based on T-Head cores implement memory-types
way different than described in the svpbmt spec even going
so far as using PTE bits marked as reserved.

Add the T-Head vendor-id and necessary errata code to
replace the affected instructions.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Samuel Holland <samuel@sholland.org>
---
 arch/riscv/Kconfig.erratas             | 19 ++++++
 arch/riscv/errata/Makefile             |  1 +
 arch/riscv/errata/sifive/errata.c      |  7 ++-
 arch/riscv/errata/thead/Makefile       |  1 +
 arch/riscv/errata/thead/errata.c       | 85 ++++++++++++++++++++++++++
 arch/riscv/include/asm/alternative.h   |  5 ++
 arch/riscv/include/asm/errata_list.h   | 47 ++++++++++++--
 arch/riscv/include/asm/pgtable-64.h    | 18 +++++-
 arch/riscv/include/asm/pgtable.h       | 18 +++++-
 arch/riscv/include/asm/vendorid_list.h |  1 +
 arch/riscv/kernel/alternative.c        | 14 +++++
 arch/riscv/kernel/cpufeature.c         |  7 ++-
 arch/riscv/mm/init.c                   |  1 +
 13 files changed, 214 insertions(+), 10 deletions(-)
 create mode 100644 arch/riscv/errata/thead/Makefile
 create mode 100644 arch/riscv/errata/thead/errata.c

diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
index d18be8ff0245..de4002baa1d0 100644
--- a/arch/riscv/Kconfig.erratas
+++ b/arch/riscv/Kconfig.erratas
@@ -31,4 +31,23 @@ config ERRATA_SIFIVE_CIP_1200
 
 	  If you don't know what to do here, say "Y".
 
+config ERRATA_THEAD
+	bool "T-HEAD errata"
+	help
+	  All T-HEAD errata Kconfig depend on this Kconfig. Disabling
+	  this Kconfig will disable all T-HEAD errata. Please say "Y"
+	  here if your platform uses T-HEAD CPU cores.
+
+	  Otherwise, please say "N" here to avoid unnecessary overhead.
+
+config ERRATA_THEAD_PBMT
+	bool "Apply T-Head memory type errata"
+	depends on ERRATA_THEAD && 64BIT
+	default y
+	help
+	  This will apply the memory type errata to handle the non-standard
+	  memory type bits in page-table-entries on T-Head SoCs.
+
+	  If you don't know what to do here, say "Y".
+
 endmenu
diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
index 0ca1c5281a2d..a1055965fbee 100644
--- a/arch/riscv/errata/Makefile
+++ b/arch/riscv/errata/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
+obj-$(CONFIG_ERRATA_THEAD) += thead/
diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
index 42457efcaaa3..0b14d5475573 100644
--- a/arch/riscv/errata/sifive/errata.c
+++ b/arch/riscv/errata/sifive/errata.c
@@ -85,10 +85,15 @@ void __init_or_module sifive_errata_patch_func(struct alt_entry *begin, struct a
 				     unsigned int stage)
 {
 	struct alt_entry *alt;
-	u32 cpu_req_errata = sifive_errata_probe(archid, impid);
+	u32 cpu_req_errata;
 	u32 cpu_apply_errata = 0;
 	u32 tmp;
 
+	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+		return;
+
+	cpu_req_errata = sifive_errata_probe(archid, impid);
+
 	for (alt = begin; alt < end; alt++) {
 		if (alt->vendor_id != SIFIVE_VENDOR_ID)
 			continue;
diff --git a/arch/riscv/errata/thead/Makefile b/arch/riscv/errata/thead/Makefile
new file mode 100644
index 000000000000..2d644e19caef
--- /dev/null
+++ b/arch/riscv/errata/thead/Makefile
@@ -0,0 +1 @@
+obj-y += errata.o
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
new file mode 100644
index 000000000000..fd8e0538a3f0
--- /dev/null
+++ b/arch/riscv/errata/thead/errata.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 Heiko Stuebner <heiko@sntech.de>
+ */
+
+#include <linux/bug.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <asm/alternative.h>
+#include <asm/cacheflush.h>
+#include <asm/errata_list.h>
+#include <asm/patch.h>
+#include <asm/vendorid_list.h>
+
+struct errata_info {
+	char name[ERRATA_STRING_LENGTH_MAX];
+	bool (*check_func)(unsigned long arch_id, unsigned long impid);
+	unsigned int stage;
+};
+
+static bool errata_mt_check_func(unsigned long  arch_id, unsigned long impid)
+{
+	if (arch_id != 0 || impid != 0)
+		return false;
+	return true;
+}
+
+static const struct errata_info errata_list[ERRATA_THEAD_NUMBER] = {
+	{
+		.name = "memory-types",
+		.stage = RISCV_ALTERNATIVES_EARLY_BOOT,
+		.check_func = errata_mt_check_func
+	},
+};
+
+static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid)
+{
+	const struct errata_info *info;
+	u32 cpu_req_errata = 0;
+	int idx;
+
+	for (idx = 0; idx < ERRATA_THEAD_NUMBER; idx++) {
+		info = &errata_list[idx];
+
+		if ((stage == RISCV_ALTERNATIVES_MODULE ||
+		     info->stage == stage) && info->check_func(archid, impid))
+			cpu_req_errata |= (1U << idx);
+	}
+
+	return cpu_req_errata;
+}
+
+void __init_or_module thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+					      unsigned long archid, unsigned long impid,
+					      unsigned int stage)
+{
+	struct alt_entry *alt;
+	u32 cpu_req_errata = thead_errata_probe(stage, archid, impid);
+	u32 cpu_apply_errata = 0;
+	u32 tmp;
+
+	for (alt = begin; alt < end; alt++) {
+		if (alt->vendor_id != THEAD_VENDOR_ID)
+			continue;
+		if (alt->errata_id >= ERRATA_THEAD_NUMBER)
+			continue;
+
+		tmp = (1U << alt->errata_id);
+		if (cpu_req_errata & tmp) {
+			/* On vm-alternatives, the mmu isn't running yet */
+			if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+				memcpy((void *)__pa_symbol(alt->old_ptr),
+				       (void *)__pa_symbol(alt->alt_ptr), alt->alt_len);
+			else
+				patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);
+
+			cpu_apply_errata |= tmp;
+		}
+	}
+
+	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+		local_flush_icache_all();
+}
diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index cf3b22173834..d1154c91ab03 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -19,8 +19,10 @@
 
 #define RISCV_ALTERNATIVES_BOOT		0 /* alternatives applied during regular boot */
 #define RISCV_ALTERNATIVES_MODULE	1 /* alternatives applied during module-init */
+#define RISCV_ALTERNATIVES_EARLY_BOOT	2 /* alternatives applied before mmu start */
 
 void __init apply_boot_alternatives(void);
+void __init apply_early_boot_alternatives(void);
 void apply_module_alternatives(void *start, size_t length);
 
 struct alt_entry {
@@ -39,6 +41,9 @@ struct errata_checkfunc_id {
 void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 			      unsigned long archid, unsigned long impid,
 			      unsigned int stage);
+void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+			     unsigned long archid, unsigned long impid,
+			     unsigned int stage);
 
 void riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end,
 				 unsigned int stage);
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index a4a9b0842922..4fac46b82c16 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -14,6 +14,11 @@
 #define	ERRATA_SIFIVE_NUMBER 2
 #endif
 
+#ifdef CONFIG_ERRATA_THEAD
+#define	ERRATA_THEAD_PBMT 0
+#define	ERRATA_THEAD_NUMBER 1
+#endif
+
 #define	CPUFEATURE_SVPBMT 0
 #define	CPUFEATURE_NUMBER 1
 
@@ -42,10 +47,44 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID,	\
  * in the default case.
  */
 #define ALT_SVPBMT_SHIFT 61
-#define ALT_SVPBMT(_val, prot)						\
-asm(ALTERNATIVE("li %0, 0\t\nnop", "li %0, %1\t\nslli %0,%0,%2", 0,	\
-		CPUFEATURE_SVPBMT, CONFIG_64BIT)			\
-		: "=r"(_val) : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), "I"(ALT_SVPBMT_SHIFT))
+#define ALT_THEAD_PBMT_SHIFT 59
+#define ALT_SVPBMT(_val, prot)								\
+asm(ALTERNATIVE_2("li %0, 0\t\nnop",							\
+		  "li %0, %1\t\nslli %0,%0,%3", 0, CPUFEATURE_SVPBMT, CONFIG_64BIT,	\
+		  "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, ERRATA_THEAD_PBMT,	\
+						CONFIG_ERRATA_THEAD_PBMT)		\
+		: "=r"(_val) : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),			\
+			       "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
+			       "I"(ALT_SVPBMT_SHIFT), "I"(ALT_THEAD_PBMT_SHIFT))
+
+#ifdef CONFIG_ERRATA_THEAD_PBMT
+/*
+ * IO/NOCACHE memory types are handled together with svpbmt,
+ * so on T-Head chips, check if no other memory type is set,
+ * and set the non-0 PMA type if applicable.
+ */
+#define ALT_THEAD_PMA(_val)								\
+asm volatile(ALTERNATIVE(								\
+	"nop\n\t"									\
+	"nop\n\t"									\
+	"nop\n\t"									\
+	"nop\n\t"									\
+	"nop\n\t"									\
+	"nop\n\t"									\
+	"nop",										\
+	"li      t3, %2\n\t"								\
+	"slli    t3, t3, %4\n\t"							\
+	"and     t3, %0, t3\n\t"							\
+	"bne     t3, zero, 2f\n\t"							\
+	"li      t3, %3\n\t"								\
+	"slli    t3, t3, %4\n\t"							\
+	"or      %0, %0, t3\n\t"							\
+	"2:",  THEAD_VENDOR_ID, ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)		\
+	: "+r"(_val) : "0"(_val), "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT),	\
+		       "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT),  "I"(ALT_THEAD_PBMT_SHIFT))
+#else
+#define ALT_THEAD_PMA(_val)
+#endif
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 07ba3416cb19..6d59e4695200 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -69,6 +69,18 @@ typedef struct {
 #define _PAGE_IO_SVPBMT		(1UL << 62)
 #define _PAGE_MTMASK_SVPBMT	(_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
 
+/*
+ * [63:59] T-Head Memory Type definitions:
+ *
+ * 00000 - NC   Weakly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
+ * 01110 - PMA  Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable
+ * 10000 - IO   Strongly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
+ */
+#define _PAGE_PMA_THEAD		((1UL << 62) | (1UL << 61) | (1UL << 60))
+#define _PAGE_NOCACHE_THEAD	0UL
+#define _PAGE_IO_THEAD		(1UL << 63)
+#define _PAGE_MTMASK_THEAD	(_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
+
 static inline u64 riscv_page_mtmask(void)
 {
 	u64 val;
@@ -167,7 +179,11 @@ static inline bool mm_pud_folded(struct mm_struct *mm)
 
 static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot)
 {
-	return __pmd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+	unsigned long prot_val = pgprot_val(prot);
+
+	ALT_THEAD_PMA(prot_val);
+
+	return __pmd((pfn << _PAGE_PFN_SHIFT) | prot_val);
 }
 
 static inline unsigned long _pmd_pfn(pmd_t pmd)
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 009a17f94b86..e2658a25f06d 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -246,7 +246,11 @@ static inline void pmd_clear(pmd_t *pmdp)
 
 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot)
 {
-	return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+	unsigned long prot_val = pgprot_val(prot);
+
+	ALT_THEAD_PMA(prot_val);
+
+	return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val);
 }
 
 static inline unsigned long _pgd_pfn(pgd_t pgd)
@@ -285,7 +289,11 @@ static inline unsigned long pte_pfn(pte_t pte)
 /* Constructs a page table entry */
 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
 {
-	return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
+	unsigned long prot_val = pgprot_val(prot);
+
+	ALT_THEAD_PMA(prot_val);
+
+	return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val);
 }
 
 #define mk_pte(page, prot)       pfn_pte(page_to_pfn(page), prot)
@@ -394,7 +402,11 @@ static inline int pmd_protnone(pmd_t pmd)
 /* Modify page protection bits */
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
-	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
+	unsigned long newprot_val = pgprot_val(newprot);
+
+	ALT_THEAD_PMA(newprot_val);
+
+	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val);
 }
 
 #define pgd_ERROR(e) \
diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index 9d934215b3c8..cb89af3f0704 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -6,5 +6,6 @@
 #define ASM_VENDOR_LIST_H
 
 #define SIFIVE_VENDOR_ID	0x489
+#define THEAD_VENDOR_ID		0x5b7
 
 #endif
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index e6c9de9f9ba6..3f6ad91f524c 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -48,6 +48,11 @@ static void __init init_alternative(void)
 	case SIFIVE_VENDOR_ID:
 		vendor_patch_func = sifive_errata_patch_func;
 		break;
+#endif
+#ifdef CONFIG_ERRATA_THEAD
+	case THEAD_VENDOR_ID:
+		vendor_patch_func = thead_errata_patch_func;
+		break;
 #endif
 	default:
 		vendor_patch_func = NULL;
@@ -85,6 +90,15 @@ void __init apply_boot_alternatives(void)
 			    RISCV_ALTERNATIVES_BOOT);
 }
 
+void __init apply_early_boot_alternatives(void)
+{
+	init_alternative();
+
+	_apply_alternatives((struct alt_entry *)__alt_start,
+			    (struct alt_entry *)__alt_end,
+			    RISCV_ALTERNATIVES_EARLY_BOOT);
+}
+
 #ifdef CONFIG_MODULES
 void apply_module_alternatives(void *start, size_t length)
 {
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 1422d9897310..5c5e6e7488ce 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -256,7 +256,12 @@ static bool __init_or_module cpufeature_svpbmt_check_func(unsigned int stage)
 	bool ret = false;
 
 #if defined(CONFIG_MMU) && defined(CONFIG_64BIT)
-	return riscv_isa_extension_available(NULL, SVPBMT);
+	switch (stage) {
+	case RISCV_ALTERNATIVES_EARLY_BOOT:
+		return false;
+	default:
+		return riscv_isa_extension_available(NULL, SVPBMT);
+	}
 #endif
 
 	return ret;
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 0d588032d6e6..245d54a3616c 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -821,6 +821,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
 	BUG_ON((kernel_map.virt_addr + kernel_map.size) > ADDRESS_SPACE_END - SZ_4K);
 #endif
 
+	apply_early_boot_alternatives();
 	pt_ops_set_early();
 
 	/* Setup early PGD for fixmap */
-- 
2.30.2

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Palmer Dabbelt]

On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
> Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> for things like non-cacheable pages or I/O memory pages.
>
>
> So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> types) using the alternatives framework.
>
> This includes a number of changes to the alternatives mechanism itself.
> The biggest one being the move to a more central location, as I expect
> in the future, nearly every chip needing some sort of patching, be it
> either for erratas or for optional features (svpbmt or others).
>
> Detection of the svpbmt functionality is done via Atish's isa extension
> handling series [0] and thus does not need any dt-parsing of its own
> anymore.
>
> The series also introduces support for the memory types of the D1
> which are implemented differently to svpbmt. But when patching anyway
> it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> location.
>
> The only slightly bigger difference is that the "normal" type is not 0
> as with svpbmt, so kernel patches for this PMA type need to be applied
> even before the MMU is brought up, so the series introduces a separate
> stage for that.
>
>
> In theory this series is 3 parts:
> - sbi cache-flush / null-ptr

That first patch looks like an acceptable candidate for fixes.  If 
there's a regression that manifests I'm happy to take it, but if it's 
only possible to manifest a crash with the new stuff then I'm OK just 
holding off until the merge window.

> - alternatives improvements
> - svpbmt+d1
>
> So expecially patches from the first 2 areas could be applied when
> deemed ready, I just thought to keep it together to show-case where
> the end-goal is and not requiring jumping between different series.
>
>
> I picked the recipient list from the previous versions, hopefully
> I didn't forget anybody.
>
> changes in v7:
> - fix typo in patch1 (Atish)
> - moved to Atish's isa-extension framework
> - and therefore move regular boot-alternatives directly behind fill_hwcaps
> - change T-Head errata Kconfig text (Atish)

I was just poking around v6, so I have some minor comments there.  None 
of those need to block merging this, but I am getting a bunch of build 
failures under allmodconfig

    $ make.riscv allmodconfig
    #
    # configuration written to .config
    #
    $ make.riscv mm/kasan/init.o
      SYNC    include/config/auto.conf.cmd
      CALL    scripts/atomic/check-atomics.sh
      CC      arch/riscv/kernel/asm-offsets.s
      CALL    scripts/checksyscalls.sh
      CC      mm/kasan/init.o
    ./arch/riscv/include/asm/pgtable.h: Assembler messages:
    ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
    make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
    make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
    make: *** [Makefile:1831: mm] Error 2

Unfortunately my build box just blew up so I haven't had time to confim 
this still exists on v7, but nothing's jumping out as a fix.  I've put 
this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
what's going on but I'm guessing one of the macros has gone off the 
rails.  I'm going to look at something else (as this one at least 
depends on Atish's patches), but LMK if you've got the time to look into 
this or if I should.

Thanks!

>
> changes in v6:
> - rebase onto 5.17-rc1
> - handle sbi null-ptr differently
> - improve commit messages
> - use riscv,mmu as property name
>
> changes in v5:
> - move to use alternatives for runtime-patching
> - add D1 variant
>
>
> [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
>
>
> Heiko Stuebner (12):
>   riscv: prevent null-pointer dereference with sbi_remote_fence_i
>   riscv: integrate alternatives better into the main architecture
>   riscv: allow different stages with alternatives
>   riscv: implement module alternatives
>   riscv: implement ALTERNATIVE_2 macro
>   riscv: extend concatenated alternatives-lines to the same length
>   riscv: prevent compressed instructions in alternatives
>   riscv: move boot alternatives to after fill_hwcap
>   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
>   riscv: add cpufeature handling via alternatives
>   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
>   riscv: add memory-type errata for T-Head
>
> Wei Fu (1):
>   riscv: add RISC-V Svpbmt extension support
>
>  arch/riscv/Kconfig.erratas                  |  29 +++--
>  arch/riscv/Kconfig.socs                     |   1 -
>  arch/riscv/Makefile                         |   2 +-
>  arch/riscv/errata/Makefile                  |   2 +-
>  arch/riscv/errata/sifive/errata.c           |  17 ++-
>  arch/riscv/errata/thead/Makefile            |   1 +
>  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
>  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
>  arch/riscv/include/asm/alternative.h        |  16 ++-
>  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
>  arch/riscv/include/asm/fixmap.h             |   2 -
>  arch/riscv/include/asm/hwcap.h              |   1 +
>  arch/riscv/include/asm/pgtable-32.h         |  17 +++
>  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
>  arch/riscv/include/asm/pgtable-bits.h       |  10 --
>  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
>  arch/riscv/include/asm/vendorid_list.h      |   1 +
>  arch/riscv/kernel/Makefile                  |   1 +
>  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
>  arch/riscv/kernel/cpu.c                     |   1 +
>  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
>  arch/riscv/kernel/module.c                  |  29 +++++
>  arch/riscv/kernel/sbi.c                     |  10 +-
>  arch/riscv/kernel/setup.c                   |   2 +
>  arch/riscv/kernel/smpboot.c                 |   4 -
>  arch/riscv/kernel/traps.c                   |   2 +-
>  arch/riscv/mm/init.c                        |   1 +
>  27 files changed, 546 insertions(+), 114 deletions(-)
>  create mode 100644 arch/riscv/errata/thead/Makefile
>  create mode 100644 arch/riscv/errata/thead/errata.c
>  rename arch/riscv/{errata => kernel}/alternative.c (59%)

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Palmer Dabbelt]

On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
> Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> for things like non-cacheable pages or I/O memory pages.
>
>
> So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> types) using the alternatives framework.
>
> This includes a number of changes to the alternatives mechanism itself.
> The biggest one being the move to a more central location, as I expect
> in the future, nearly every chip needing some sort of patching, be it
> either for erratas or for optional features (svpbmt or others).
>
> Detection of the svpbmt functionality is done via Atish's isa extension
> handling series [0] and thus does not need any dt-parsing of its own
> anymore.
>
> The series also introduces support for the memory types of the D1
> which are implemented differently to svpbmt. But when patching anyway
> it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> location.
>
> The only slightly bigger difference is that the "normal" type is not 0
> as with svpbmt, so kernel patches for this PMA type need to be applied
> even before the MMU is brought up, so the series introduces a separate
> stage for that.
>
>
> In theory this series is 3 parts:
> - sbi cache-flush / null-ptr

That first patch looks like an acceptable candidate for fixes.  If 
there's a regression that manifests I'm happy to take it, but if it's 
only possible to manifest a crash with the new stuff then I'm OK just 
holding off until the merge window.

> - alternatives improvements
> - svpbmt+d1
>
> So expecially patches from the first 2 areas could be applied when
> deemed ready, I just thought to keep it together to show-case where
> the end-goal is and not requiring jumping between different series.
>
>
> I picked the recipient list from the previous versions, hopefully
> I didn't forget anybody.
>
> changes in v7:
> - fix typo in patch1 (Atish)
> - moved to Atish's isa-extension framework
> - and therefore move regular boot-alternatives directly behind fill_hwcaps
> - change T-Head errata Kconfig text (Atish)

I was just poking around v6, so I have some minor comments there.  None 
of those need to block merging this, but I am getting a bunch of build 
failures under allmodconfig

    $ make.riscv allmodconfig
    #
    # configuration written to .config
    #
    $ make.riscv mm/kasan/init.o
      SYNC    include/config/auto.conf.cmd
      CALL    scripts/atomic/check-atomics.sh
      CC      arch/riscv/kernel/asm-offsets.s
      CALL    scripts/checksyscalls.sh
      CC      mm/kasan/init.o
    ./arch/riscv/include/asm/pgtable.h: Assembler messages:
    ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
    make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
    make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
    make: *** [Makefile:1831: mm] Error 2

Unfortunately my build box just blew up so I haven't had time to confim 
this still exists on v7, but nothing's jumping out as a fix.  I've put 
this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
what's going on but I'm guessing one of the macros has gone off the 
rails.  I'm going to look at something else (as this one at least 
depends on Atish's patches), but LMK if you've got the time to look into 
this or if I should.

Thanks!

>
> changes in v6:
> - rebase onto 5.17-rc1
> - handle sbi null-ptr differently
> - improve commit messages
> - use riscv,mmu as property name
>
> changes in v5:
> - move to use alternatives for runtime-patching
> - add D1 variant
>
>
> [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
>
>
> Heiko Stuebner (12):
>   riscv: prevent null-pointer dereference with sbi_remote_fence_i
>   riscv: integrate alternatives better into the main architecture
>   riscv: allow different stages with alternatives
>   riscv: implement module alternatives
>   riscv: implement ALTERNATIVE_2 macro
>   riscv: extend concatenated alternatives-lines to the same length
>   riscv: prevent compressed instructions in alternatives
>   riscv: move boot alternatives to after fill_hwcap
>   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
>   riscv: add cpufeature handling via alternatives
>   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
>   riscv: add memory-type errata for T-Head
>
> Wei Fu (1):
>   riscv: add RISC-V Svpbmt extension support
>
>  arch/riscv/Kconfig.erratas                  |  29 +++--
>  arch/riscv/Kconfig.socs                     |   1 -
>  arch/riscv/Makefile                         |   2 +-
>  arch/riscv/errata/Makefile                  |   2 +-
>  arch/riscv/errata/sifive/errata.c           |  17 ++-
>  arch/riscv/errata/thead/Makefile            |   1 +
>  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
>  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
>  arch/riscv/include/asm/alternative.h        |  16 ++-
>  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
>  arch/riscv/include/asm/fixmap.h             |   2 -
>  arch/riscv/include/asm/hwcap.h              |   1 +
>  arch/riscv/include/asm/pgtable-32.h         |  17 +++
>  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
>  arch/riscv/include/asm/pgtable-bits.h       |  10 --
>  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
>  arch/riscv/include/asm/vendorid_list.h      |   1 +
>  arch/riscv/kernel/Makefile                  |   1 +
>  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
>  arch/riscv/kernel/cpu.c                     |   1 +
>  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
>  arch/riscv/kernel/module.c                  |  29 +++++
>  arch/riscv/kernel/sbi.c                     |  10 +-
>  arch/riscv/kernel/setup.c                   |   2 +
>  arch/riscv/kernel/smpboot.c                 |   4 -
>  arch/riscv/kernel/traps.c                   |   2 +-
>  arch/riscv/mm/init.c                        |   1 +
>  27 files changed, 546 insertions(+), 114 deletions(-)
>  create mode 100644 arch/riscv/errata/thead/Makefile
>  create mode 100644 arch/riscv/errata/thead/errata.c
>  rename arch/riscv/{errata => kernel}/alternative.c (59%)

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Heiko Stübner]

Hi Palmer,

Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
> On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
> > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> > for things like non-cacheable pages or I/O memory pages.
> >
> >
> > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> > types) using the alternatives framework.
> >
> > This includes a number of changes to the alternatives mechanism itself.
> > The biggest one being the move to a more central location, as I expect
> > in the future, nearly every chip needing some sort of patching, be it
> > either for erratas or for optional features (svpbmt or others).
> >
> > Detection of the svpbmt functionality is done via Atish's isa extension
> > handling series [0] and thus does not need any dt-parsing of its own
> > anymore.
> >
> > The series also introduces support for the memory types of the D1
> > which are implemented differently to svpbmt. But when patching anyway
> > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> > location.
> >
> > The only slightly bigger difference is that the "normal" type is not 0
> > as with svpbmt, so kernel patches for this PMA type need to be applied
> > even before the MMU is brought up, so the series introduces a separate
> > stage for that.
> >
> >
> > In theory this series is 3 parts:
> > - sbi cache-flush / null-ptr
> 
> That first patch looks like an acceptable candidate for fixes.  If 
> there's a regression that manifests I'm happy to take it, but if it's 
> only possible to manifest a crash with the new stuff then I'm OK just 
> holding off until the merge window.

While right now only my poking around the early init via alternatives
is affected, the problem exists for everyone.

I.e. I do consider flush_icache_all() to be generic enough that we
should expect someone trying to call this in some early code-path
as well.

But any call to flush_icache_all() before sbi_init() ran will cause the
breakage that is fixed by patch1 .


So it doesn't look like any _current_ code path has that issue, but
it might be good to just pick patch1 for the next merge window
individually?



> > - alternatives improvements
> > - svpbmt+d1
> >
> > So expecially patches from the first 2 areas could be applied when
> > deemed ready, I just thought to keep it together to show-case where
> > the end-goal is and not requiring jumping between different series.
> >
> >
> > I picked the recipient list from the previous versions, hopefully
> > I didn't forget anybody.
> >
> > changes in v7:
> > - fix typo in patch1 (Atish)
> > - moved to Atish's isa-extension framework
> > - and therefore move regular boot-alternatives directly behind fill_hwcaps
> > - change T-Head errata Kconfig text (Atish)
> 
> I was just poking around v6, so I have some minor comments there.  None 
> of those need to block merging this, but I am getting a bunch of build 
> failures under allmodconfig
> 
>     $ make.riscv allmodconfig
>     #
>     # configuration written to .config
>     #
>     $ make.riscv mm/kasan/init.o
>       SYNC    include/config/auto.conf.cmd
>       CALL    scripts/atomic/check-atomics.sh
>       CC      arch/riscv/kernel/asm-offsets.s
>       CALL    scripts/checksyscalls.sh
>       CC      mm/kasan/init.o
>     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
>     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
>     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
>     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
>     make: *** [Makefile:1831: mm] Error 2
> 
> Unfortunately my build box just blew up so I haven't had time to confim 
> this still exists on v7, but nothing's jumping out as a fix.  I've put 
> this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
> what's going on but I'm guessing one of the macros has gone off the 
> rails.  I'm going to look at something else (as this one at least 
> depends on Atish's patches), but LMK if you've got the time to look into 
> this or if I should.

Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
series and some more series I saw on the list), so getting that into a
mergeable position would be really great :-)

"attempt to move .org backwards" seems to be the telltale sign of the
alternatives blocks not matching up in size. While I definitly didn't see
anything like this in my tests on qemu + d1, I'll try to investigate where
that comes from.


Heiko



> > changes in v6:
> > - rebase onto 5.17-rc1
> > - handle sbi null-ptr differently
> > - improve commit messages
> > - use riscv,mmu as property name
> >
> > changes in v5:
> > - move to use alternatives for runtime-patching
> > - add D1 variant
> >
> >
> > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
> >
> >
> > Heiko Stuebner (12):
> >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
> >   riscv: integrate alternatives better into the main architecture
> >   riscv: allow different stages with alternatives
> >   riscv: implement module alternatives
> >   riscv: implement ALTERNATIVE_2 macro
> >   riscv: extend concatenated alternatives-lines to the same length
> >   riscv: prevent compressed instructions in alternatives
> >   riscv: move boot alternatives to after fill_hwcap
> >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> >   riscv: add cpufeature handling via alternatives
> >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> >   riscv: add memory-type errata for T-Head
> >
> > Wei Fu (1):
> >   riscv: add RISC-V Svpbmt extension support
> >
> >  arch/riscv/Kconfig.erratas                  |  29 +++--
> >  arch/riscv/Kconfig.socs                     |   1 -
> >  arch/riscv/Makefile                         |   2 +-
> >  arch/riscv/errata/Makefile                  |   2 +-
> >  arch/riscv/errata/sifive/errata.c           |  17 ++-
> >  arch/riscv/errata/thead/Makefile            |   1 +
> >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
> >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
> >  arch/riscv/include/asm/alternative.h        |  16 ++-
> >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
> >  arch/riscv/include/asm/fixmap.h             |   2 -
> >  arch/riscv/include/asm/hwcap.h              |   1 +
> >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
> >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
> >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
> >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
> >  arch/riscv/include/asm/vendorid_list.h      |   1 +
> >  arch/riscv/kernel/Makefile                  |   1 +
> >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
> >  arch/riscv/kernel/cpu.c                     |   1 +
> >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
> >  arch/riscv/kernel/module.c                  |  29 +++++
> >  arch/riscv/kernel/sbi.c                     |  10 +-
> >  arch/riscv/kernel/setup.c                   |   2 +
> >  arch/riscv/kernel/smpboot.c                 |   4 -
> >  arch/riscv/kernel/traps.c                   |   2 +-
> >  arch/riscv/mm/init.c                        |   1 +
> >  27 files changed, 546 insertions(+), 114 deletions(-)
> >  create mode 100644 arch/riscv/errata/thead/Makefile
> >  create mode 100644 arch/riscv/errata/thead/errata.c
> >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
> 

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Heiko Stübner]

Hi Palmer,

Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
> On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
> > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> > for things like non-cacheable pages or I/O memory pages.
> >
> >
> > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> > types) using the alternatives framework.
> >
> > This includes a number of changes to the alternatives mechanism itself.
> > The biggest one being the move to a more central location, as I expect
> > in the future, nearly every chip needing some sort of patching, be it
> > either for erratas or for optional features (svpbmt or others).
> >
> > Detection of the svpbmt functionality is done via Atish's isa extension
> > handling series [0] and thus does not need any dt-parsing of its own
> > anymore.
> >
> > The series also introduces support for the memory types of the D1
> > which are implemented differently to svpbmt. But when patching anyway
> > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> > location.
> >
> > The only slightly bigger difference is that the "normal" type is not 0
> > as with svpbmt, so kernel patches for this PMA type need to be applied
> > even before the MMU is brought up, so the series introduces a separate
> > stage for that.
> >
> >
> > In theory this series is 3 parts:
> > - sbi cache-flush / null-ptr
> 
> That first patch looks like an acceptable candidate for fixes.  If 
> there's a regression that manifests I'm happy to take it, but if it's 
> only possible to manifest a crash with the new stuff then I'm OK just 
> holding off until the merge window.

While right now only my poking around the early init via alternatives
is affected, the problem exists for everyone.

I.e. I do consider flush_icache_all() to be generic enough that we
should expect someone trying to call this in some early code-path
as well.

But any call to flush_icache_all() before sbi_init() ran will cause the
breakage that is fixed by patch1 .


So it doesn't look like any _current_ code path has that issue, but
it might be good to just pick patch1 for the next merge window
individually?



> > - alternatives improvements
> > - svpbmt+d1
> >
> > So expecially patches from the first 2 areas could be applied when
> > deemed ready, I just thought to keep it together to show-case where
> > the end-goal is and not requiring jumping between different series.
> >
> >
> > I picked the recipient list from the previous versions, hopefully
> > I didn't forget anybody.
> >
> > changes in v7:
> > - fix typo in patch1 (Atish)
> > - moved to Atish's isa-extension framework
> > - and therefore move regular boot-alternatives directly behind fill_hwcaps
> > - change T-Head errata Kconfig text (Atish)
> 
> I was just poking around v6, so I have some minor comments there.  None 
> of those need to block merging this, but I am getting a bunch of build 
> failures under allmodconfig
> 
>     $ make.riscv allmodconfig
>     #
>     # configuration written to .config
>     #
>     $ make.riscv mm/kasan/init.o
>       SYNC    include/config/auto.conf.cmd
>       CALL    scripts/atomic/check-atomics.sh
>       CC      arch/riscv/kernel/asm-offsets.s
>       CALL    scripts/checksyscalls.sh
>       CC      mm/kasan/init.o
>     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
>     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
>     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
>     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
>     make: *** [Makefile:1831: mm] Error 2
> 
> Unfortunately my build box just blew up so I haven't had time to confim 
> this still exists on v7, but nothing's jumping out as a fix.  I've put 
> this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
> what's going on but I'm guessing one of the macros has gone off the 
> rails.  I'm going to look at something else (as this one at least 
> depends on Atish's patches), but LMK if you've got the time to look into 
> this or if I should.

Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
series and some more series I saw on the list), so getting that into a
mergeable position would be really great :-)

"attempt to move .org backwards" seems to be the telltale sign of the
alternatives blocks not matching up in size. While I definitly didn't see
anything like this in my tests on qemu + d1, I'll try to investigate where
that comes from.


Heiko



> > changes in v6:
> > - rebase onto 5.17-rc1
> > - handle sbi null-ptr differently
> > - improve commit messages
> > - use riscv,mmu as property name
> >
> > changes in v5:
> > - move to use alternatives for runtime-patching
> > - add D1 variant
> >
> >
> > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
> >
> >
> > Heiko Stuebner (12):
> >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
> >   riscv: integrate alternatives better into the main architecture
> >   riscv: allow different stages with alternatives
> >   riscv: implement module alternatives
> >   riscv: implement ALTERNATIVE_2 macro
> >   riscv: extend concatenated alternatives-lines to the same length
> >   riscv: prevent compressed instructions in alternatives
> >   riscv: move boot alternatives to after fill_hwcap
> >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> >   riscv: add cpufeature handling via alternatives
> >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> >   riscv: add memory-type errata for T-Head
> >
> > Wei Fu (1):
> >   riscv: add RISC-V Svpbmt extension support
> >
> >  arch/riscv/Kconfig.erratas                  |  29 +++--
> >  arch/riscv/Kconfig.socs                     |   1 -
> >  arch/riscv/Makefile                         |   2 +-
> >  arch/riscv/errata/Makefile                  |   2 +-
> >  arch/riscv/errata/sifive/errata.c           |  17 ++-
> >  arch/riscv/errata/thead/Makefile            |   1 +
> >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
> >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
> >  arch/riscv/include/asm/alternative.h        |  16 ++-
> >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
> >  arch/riscv/include/asm/fixmap.h             |   2 -
> >  arch/riscv/include/asm/hwcap.h              |   1 +
> >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
> >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
> >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
> >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
> >  arch/riscv/include/asm/vendorid_list.h      |   1 +
> >  arch/riscv/kernel/Makefile                  |   1 +
> >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
> >  arch/riscv/kernel/cpu.c                     |   1 +
> >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
> >  arch/riscv/kernel/module.c                  |  29 +++++
> >  arch/riscv/kernel/sbi.c                     |  10 +-
> >  arch/riscv/kernel/setup.c                   |   2 +
> >  arch/riscv/kernel/smpboot.c                 |   4 -
> >  arch/riscv/kernel/traps.c                   |   2 +-
> >  arch/riscv/mm/init.c                        |   1 +
> >  27 files changed, 546 insertions(+), 114 deletions(-)
> >  create mode 100644 arch/riscv/errata/thead/Makefile
> >  create mode 100644 arch/riscv/errata/thead/errata.c
> >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
> 





_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Heiko Stübner]

Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
> Hi Palmer,
> 
> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> > > for things like non-cacheable pages or I/O memory pages.
> > >
> > >
> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> > > types) using the alternatives framework.
> > >
> > > This includes a number of changes to the alternatives mechanism itself.
> > > The biggest one being the move to a more central location, as I expect
> > > in the future, nearly every chip needing some sort of patching, be it
> > > either for erratas or for optional features (svpbmt or others).
> > >
> > > Detection of the svpbmt functionality is done via Atish's isa extension
> > > handling series [0] and thus does not need any dt-parsing of its own
> > > anymore.
> > >
> > > The series also introduces support for the memory types of the D1
> > > which are implemented differently to svpbmt. But when patching anyway
> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> > > location.
> > >
> > > The only slightly bigger difference is that the "normal" type is not 0
> > > as with svpbmt, so kernel patches for this PMA type need to be applied
> > > even before the MMU is brought up, so the series introduces a separate
> > > stage for that.
> > >
> > >
> > > In theory this series is 3 parts:
> > > - sbi cache-flush / null-ptr
> > 
> > That first patch looks like an acceptable candidate for fixes.  If 
> > there's a regression that manifests I'm happy to take it, but if it's 
> > only possible to manifest a crash with the new stuff then I'm OK just 
> > holding off until the merge window.
> 
> While right now only my poking around the early init via alternatives
> is affected, the problem exists for everyone.
> 
> I.e. I do consider flush_icache_all() to be generic enough that we
> should expect someone trying to call this in some early code-path
> as well.
> 
> But any call to flush_icache_all() before sbi_init() ran will cause the
> breakage that is fixed by patch1 .
> 
> 
> So it doesn't look like any _current_ code path has that issue, but
> it might be good to just pick patch1 for the next merge window
> individually?
> 
> 
> 
> > > - alternatives improvements
> > > - svpbmt+d1
> > >
> > > So expecially patches from the first 2 areas could be applied when
> > > deemed ready, I just thought to keep it together to show-case where
> > > the end-goal is and not requiring jumping between different series.
> > >
> > >
> > > I picked the recipient list from the previous versions, hopefully
> > > I didn't forget anybody.
> > >
> > > changes in v7:
> > > - fix typo in patch1 (Atish)
> > > - moved to Atish's isa-extension framework
> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
> > > - change T-Head errata Kconfig text (Atish)
> > 
> > I was just poking around v6, so I have some minor comments there.  None 
> > of those need to block merging this, but I am getting a bunch of build 
> > failures under allmodconfig
> > 
> >     $ make.riscv allmodconfig
> >     #
> >     # configuration written to .config
> >     #
> >     $ make.riscv mm/kasan/init.o
> >       SYNC    include/config/auto.conf.cmd
> >       CALL    scripts/atomic/check-atomics.sh
> >       CC      arch/riscv/kernel/asm-offsets.s
> >       CALL    scripts/checksyscalls.sh
> >       CC      mm/kasan/init.o
> >     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
> >     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
> >     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
> >     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
> >     make: *** [Makefile:1831: mm] Error 2
> > 
> > Unfortunately my build box just blew up so I haven't had time to confim 
> > this still exists on v7, but nothing's jumping out as a fix.  I've put 
> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
> > what's going on but I'm guessing one of the macros has gone off the 
> > rails.  I'm going to look at something else (as this one at least 
> > depends on Atish's patches), but LMK if you've got the time to look into 
> > this or if I should.
> 
> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
> series and some more series I saw on the list), so getting that into a
> mergeable position would be really great :-)
> 
> "attempt to move .org backwards" seems to be the telltale sign of the
> alternatives blocks not matching up in size. While I definitly didn't see
> anything like this in my tests on qemu + d1, I'll try to investigate where
> that comes from.

Hmm, looking at your branch [0] it seems that you're missing
patch7 that introduces the no-compressed-instruction thingy
for alternatives.

And missing that patch will of course cause the size issue.

The patch has made its way to the actual mailing lists [1], so I guess
it "just" somehow didn't reach your inbox due to some mail hickup?


Heiko


[0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
[1] https://lore.kernel.org/all/20220307205310.1905628-8-heiko@sntech.de/


> > > changes in v6:
> > > - rebase onto 5.17-rc1
> > > - handle sbi null-ptr differently
> > > - improve commit messages
> > > - use riscv,mmu as property name
> > >
> > > changes in v5:
> > > - move to use alternatives for runtime-patching
> > > - add D1 variant
> > >
> > >
> > > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
> > >
> > >
> > > Heiko Stuebner (12):
> > >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
> > >   riscv: integrate alternatives better into the main architecture
> > >   riscv: allow different stages with alternatives
> > >   riscv: implement module alternatives
> > >   riscv: implement ALTERNATIVE_2 macro
> > >   riscv: extend concatenated alternatives-lines to the same length
> > >   riscv: prevent compressed instructions in alternatives
> > >   riscv: move boot alternatives to after fill_hwcap
> > >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> > >   riscv: add cpufeature handling via alternatives
> > >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> > >   riscv: add memory-type errata for T-Head
> > >
> > > Wei Fu (1):
> > >   riscv: add RISC-V Svpbmt extension support
> > >
> > >  arch/riscv/Kconfig.erratas                  |  29 +++--
> > >  arch/riscv/Kconfig.socs                     |   1 -
> > >  arch/riscv/Makefile                         |   2 +-
> > >  arch/riscv/errata/Makefile                  |   2 +-
> > >  arch/riscv/errata/sifive/errata.c           |  17 ++-
> > >  arch/riscv/errata/thead/Makefile            |   1 +
> > >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
> > >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
> > >  arch/riscv/include/asm/alternative.h        |  16 ++-
> > >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
> > >  arch/riscv/include/asm/fixmap.h             |   2 -
> > >  arch/riscv/include/asm/hwcap.h              |   1 +
> > >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
> > >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
> > >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
> > >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
> > >  arch/riscv/include/asm/vendorid_list.h      |   1 +
> > >  arch/riscv/kernel/Makefile                  |   1 +
> > >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
> > >  arch/riscv/kernel/cpu.c                     |   1 +
> > >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
> > >  arch/riscv/kernel/module.c                  |  29 +++++
> > >  arch/riscv/kernel/sbi.c                     |  10 +-
> > >  arch/riscv/kernel/setup.c                   |   2 +
> > >  arch/riscv/kernel/smpboot.c                 |   4 -
> > >  arch/riscv/kernel/traps.c                   |   2 +-
> > >  arch/riscv/mm/init.c                        |   1 +
> > >  27 files changed, 546 insertions(+), 114 deletions(-)
> > >  create mode 100644 arch/riscv/errata/thead/Makefile
> > >  create mode 100644 arch/riscv/errata/thead/errata.c
> > >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
> > 
> 
> 

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Heiko Stübner]

Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
> Hi Palmer,
> 
> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> > > for things like non-cacheable pages or I/O memory pages.
> > >
> > >
> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> > > types) using the alternatives framework.
> > >
> > > This includes a number of changes to the alternatives mechanism itself.
> > > The biggest one being the move to a more central location, as I expect
> > > in the future, nearly every chip needing some sort of patching, be it
> > > either for erratas or for optional features (svpbmt or others).
> > >
> > > Detection of the svpbmt functionality is done via Atish's isa extension
> > > handling series [0] and thus does not need any dt-parsing of its own
> > > anymore.
> > >
> > > The series also introduces support for the memory types of the D1
> > > which are implemented differently to svpbmt. But when patching anyway
> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> > > location.
> > >
> > > The only slightly bigger difference is that the "normal" type is not 0
> > > as with svpbmt, so kernel patches for this PMA type need to be applied
> > > even before the MMU is brought up, so the series introduces a separate
> > > stage for that.
> > >
> > >
> > > In theory this series is 3 parts:
> > > - sbi cache-flush / null-ptr
> > 
> > That first patch looks like an acceptable candidate for fixes.  If 
> > there's a regression that manifests I'm happy to take it, but if it's 
> > only possible to manifest a crash with the new stuff then I'm OK just 
> > holding off until the merge window.
> 
> While right now only my poking around the early init via alternatives
> is affected, the problem exists for everyone.
> 
> I.e. I do consider flush_icache_all() to be generic enough that we
> should expect someone trying to call this in some early code-path
> as well.
> 
> But any call to flush_icache_all() before sbi_init() ran will cause the
> breakage that is fixed by patch1 .
> 
> 
> So it doesn't look like any _current_ code path has that issue, but
> it might be good to just pick patch1 for the next merge window
> individually?
> 
> 
> 
> > > - alternatives improvements
> > > - svpbmt+d1
> > >
> > > So expecially patches from the first 2 areas could be applied when
> > > deemed ready, I just thought to keep it together to show-case where
> > > the end-goal is and not requiring jumping between different series.
> > >
> > >
> > > I picked the recipient list from the previous versions, hopefully
> > > I didn't forget anybody.
> > >
> > > changes in v7:
> > > - fix typo in patch1 (Atish)
> > > - moved to Atish's isa-extension framework
> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
> > > - change T-Head errata Kconfig text (Atish)
> > 
> > I was just poking around v6, so I have some minor comments there.  None 
> > of those need to block merging this, but I am getting a bunch of build 
> > failures under allmodconfig
> > 
> >     $ make.riscv allmodconfig
> >     #
> >     # configuration written to .config
> >     #
> >     $ make.riscv mm/kasan/init.o
> >       SYNC    include/config/auto.conf.cmd
> >       CALL    scripts/atomic/check-atomics.sh
> >       CC      arch/riscv/kernel/asm-offsets.s
> >       CALL    scripts/checksyscalls.sh
> >       CC      mm/kasan/init.o
> >     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
> >     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
> >     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
> >     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
> >     make: *** [Makefile:1831: mm] Error 2
> > 
> > Unfortunately my build box just blew up so I haven't had time to confim 
> > this still exists on v7, but nothing's jumping out as a fix.  I've put 
> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
> > what's going on but I'm guessing one of the macros has gone off the 
> > rails.  I'm going to look at something else (as this one at least 
> > depends on Atish's patches), but LMK if you've got the time to look into 
> > this or if I should.
> 
> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
> series and some more series I saw on the list), so getting that into a
> mergeable position would be really great :-)
> 
> "attempt to move .org backwards" seems to be the telltale sign of the
> alternatives blocks not matching up in size. While I definitly didn't see
> anything like this in my tests on qemu + d1, I'll try to investigate where
> that comes from.

Hmm, looking at your branch [0] it seems that you're missing
patch7 that introduces the no-compressed-instruction thingy
for alternatives.

And missing that patch will of course cause the size issue.

The patch has made its way to the actual mailing lists [1], so I guess
it "just" somehow didn't reach your inbox due to some mail hickup?


Heiko


[0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
[1] https://lore.kernel.org/all/20220307205310.1905628-8-heiko@sntech.de/


> > > changes in v6:
> > > - rebase onto 5.17-rc1
> > > - handle sbi null-ptr differently
> > > - improve commit messages
> > > - use riscv,mmu as property name
> > >
> > > changes in v5:
> > > - move to use alternatives for runtime-patching
> > > - add D1 variant
> > >
> > >
> > > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
> > >
> > >
> > > Heiko Stuebner (12):
> > >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
> > >   riscv: integrate alternatives better into the main architecture
> > >   riscv: allow different stages with alternatives
> > >   riscv: implement module alternatives
> > >   riscv: implement ALTERNATIVE_2 macro
> > >   riscv: extend concatenated alternatives-lines to the same length
> > >   riscv: prevent compressed instructions in alternatives
> > >   riscv: move boot alternatives to after fill_hwcap
> > >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> > >   riscv: add cpufeature handling via alternatives
> > >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> > >   riscv: add memory-type errata for T-Head
> > >
> > > Wei Fu (1):
> > >   riscv: add RISC-V Svpbmt extension support
> > >
> > >  arch/riscv/Kconfig.erratas                  |  29 +++--
> > >  arch/riscv/Kconfig.socs                     |   1 -
> > >  arch/riscv/Makefile                         |   2 +-
> > >  arch/riscv/errata/Makefile                  |   2 +-
> > >  arch/riscv/errata/sifive/errata.c           |  17 ++-
> > >  arch/riscv/errata/thead/Makefile            |   1 +
> > >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
> > >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
> > >  arch/riscv/include/asm/alternative.h        |  16 ++-
> > >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
> > >  arch/riscv/include/asm/fixmap.h             |   2 -
> > >  arch/riscv/include/asm/hwcap.h              |   1 +
> > >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
> > >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
> > >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
> > >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
> > >  arch/riscv/include/asm/vendorid_list.h      |   1 +
> > >  arch/riscv/kernel/Makefile                  |   1 +
> > >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
> > >  arch/riscv/kernel/cpu.c                     |   1 +
> > >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
> > >  arch/riscv/kernel/module.c                  |  29 +++++
> > >  arch/riscv/kernel/sbi.c                     |  10 +-
> > >  arch/riscv/kernel/setup.c                   |   2 +
> > >  arch/riscv/kernel/smpboot.c                 |   4 -
> > >  arch/riscv/kernel/traps.c                   |   2 +-
> > >  arch/riscv/mm/init.c                        |   1 +
> > >  27 files changed, 546 insertions(+), 114 deletions(-)
> > >  create mode 100644 arch/riscv/errata/thead/Makefile
> > >  create mode 100644 arch/riscv/errata/thead/errata.c
> > >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
> > 
> 
> 





_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Palmer Dabbelt]

On Wed, 09 Mar 2022 14:06:55 PST (-0800), heiko@sntech.de wrote:
> Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
>> Hi Palmer,
>> 
>> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
>> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
>> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
>> > > for things like non-cacheable pages or I/O memory pages.
>> > >
>> > >
>> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
>> > > types) using the alternatives framework.
>> > >
>> > > This includes a number of changes to the alternatives mechanism itself.
>> > > The biggest one being the move to a more central location, as I expect
>> > > in the future, nearly every chip needing some sort of patching, be it
>> > > either for erratas or for optional features (svpbmt or others).
>> > >
>> > > Detection of the svpbmt functionality is done via Atish's isa extension
>> > > handling series [0] and thus does not need any dt-parsing of its own
>> > > anymore.
>> > >
>> > > The series also introduces support for the memory types of the D1
>> > > which are implemented differently to svpbmt. But when patching anyway
>> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
>> > > location.
>> > >
>> > > The only slightly bigger difference is that the "normal" type is not 0
>> > > as with svpbmt, so kernel patches for this PMA type need to be applied
>> > > even before the MMU is brought up, so the series introduces a separate
>> > > stage for that.
>> > >
>> > >
>> > > In theory this series is 3 parts:
>> > > - sbi cache-flush / null-ptr
>> > 
>> > That first patch looks like an acceptable candidate for fixes.  If 
>> > there's a regression that manifests I'm happy to take it, but if it's 
>> > only possible to manifest a crash with the new stuff then I'm OK just 
>> > holding off until the merge window.
>> 
>> While right now only my poking around the early init via alternatives
>> is affected, the problem exists for everyone.
>> 
>> I.e. I do consider flush_icache_all() to be generic enough that we
>> should expect someone trying to call this in some early code-path
>> as well.
>> 
>> But any call to flush_icache_all() before sbi_init() ran will cause the
>> breakage that is fixed by patch1 .
>> 
>> 
>> So it doesn't look like any _current_ code path has that issue, but
>> it might be good to just pick patch1 for the next merge window
>> individually?
>> 
>> 
>> 
>> > > - alternatives improvements
>> > > - svpbmt+d1
>> > >
>> > > So expecially patches from the first 2 areas could be applied when
>> > > deemed ready, I just thought to keep it together to show-case where
>> > > the end-goal is and not requiring jumping between different series.
>> > >
>> > >
>> > > I picked the recipient list from the previous versions, hopefully
>> > > I didn't forget anybody.
>> > >
>> > > changes in v7:
>> > > - fix typo in patch1 (Atish)
>> > > - moved to Atish's isa-extension framework
>> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
>> > > - change T-Head errata Kconfig text (Atish)
>> > 
>> > I was just poking around v6, so I have some minor comments there.  None 
>> > of those need to block merging this, but I am getting a bunch of build 
>> > failures under allmodconfig
>> > 
>> >     $ make.riscv allmodconfig
>> >     #
>> >     # configuration written to .config
>> >     #
>> >     $ make.riscv mm/kasan/init.o
>> >       SYNC    include/config/auto.conf.cmd
>> >       CALL    scripts/atomic/check-atomics.sh
>> >       CC      arch/riscv/kernel/asm-offsets.s
>> >       CALL    scripts/checksyscalls.sh
>> >       CC      mm/kasan/init.o
>> >     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
>> >     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
>> >     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
>> >     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
>> >     make: *** [Makefile:1831: mm] Error 2
>> > 
>> > Unfortunately my build box just blew up so I haven't had time to confim 
>> > this still exists on v7, but nothing's jumping out as a fix.  I've put 
>> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
>> > what's going on but I'm guessing one of the macros has gone off the 
>> > rails.  I'm going to look at something else (as this one at least 
>> > depends on Atish's patches), but LMK if you've got the time to look into 
>> > this or if I should.
>> 
>> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
>> series and some more series I saw on the list), so getting that into a
>> mergeable position would be really great :-)
>> 
>> "attempt to move .org backwards" seems to be the telltale sign of the
>> alternatives blocks not matching up in size. While I definitly didn't see
>> anything like this in my tests on qemu + d1, I'll try to investigate where
>> that comes from.
>
> Hmm, looking at your branch [0] it seems that you're missing
> patch7 that introduces the no-compressed-instruction thingy
> for alternatives.
>
> And missing that patch will of course cause the size issue.
>
> The patch has made its way to the actual mailing lists [1], so I guess
> it "just" somehow didn't reach your inbox due to some mail hickup?

Sorry about that, I'm not sure what happened.

Unfortunately I'm now getting some even trickier failures: a handful of 
configurations are failing very early in boot.  There doesn't seem to be 
much pattern to the configs that fail, but at least rv32 defconfig (on 
QEMU's virt board) is doing so.  I've tried poking around a bit and 
can't figure out what's going on.  I'll try and look again tomorrow 
morning.

I've put my somewhat messy merged test branch at 
kernel.org/palmer/riscv-d1-merge .  Happy to hear if you have any 
insights, otherwise I'l give it another shot (possibly after looking at 
some other patches, there's quite a bit of a queue for this late).

>
>
> Heiko
>
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
> [1] https://lore.kernel.org/all/20220307205310.1905628-8-heiko@sntech.de/
>
>
>> > > changes in v6:
>> > > - rebase onto 5.17-rc1
>> > > - handle sbi null-ptr differently
>> > > - improve commit messages
>> > > - use riscv,mmu as property name
>> > >
>> > > changes in v5:
>> > > - move to use alternatives for runtime-patching
>> > > - add D1 variant
>> > >
>> > >
>> > > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
>> > >
>> > >
>> > > Heiko Stuebner (12):
>> > >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
>> > >   riscv: integrate alternatives better into the main architecture
>> > >   riscv: allow different stages with alternatives
>> > >   riscv: implement module alternatives
>> > >   riscv: implement ALTERNATIVE_2 macro
>> > >   riscv: extend concatenated alternatives-lines to the same length
>> > >   riscv: prevent compressed instructions in alternatives
>> > >   riscv: move boot alternatives to after fill_hwcap
>> > >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
>> > >   riscv: add cpufeature handling via alternatives
>> > >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
>> > >   riscv: add memory-type errata for T-Head
>> > >
>> > > Wei Fu (1):
>> > >   riscv: add RISC-V Svpbmt extension support
>> > >
>> > >  arch/riscv/Kconfig.erratas                  |  29 +++--
>> > >  arch/riscv/Kconfig.socs                     |   1 -
>> > >  arch/riscv/Makefile                         |   2 +-
>> > >  arch/riscv/errata/Makefile                  |   2 +-
>> > >  arch/riscv/errata/sifive/errata.c           |  17 ++-
>> > >  arch/riscv/errata/thead/Makefile            |   1 +
>> > >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
>> > >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
>> > >  arch/riscv/include/asm/alternative.h        |  16 ++-
>> > >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
>> > >  arch/riscv/include/asm/fixmap.h             |   2 -
>> > >  arch/riscv/include/asm/hwcap.h              |   1 +
>> > >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
>> > >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
>> > >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
>> > >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
>> > >  arch/riscv/include/asm/vendorid_list.h      |   1 +
>> > >  arch/riscv/kernel/Makefile                  |   1 +
>> > >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
>> > >  arch/riscv/kernel/cpu.c                     |   1 +
>> > >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
>> > >  arch/riscv/kernel/module.c                  |  29 +++++
>> > >  arch/riscv/kernel/sbi.c                     |  10 +-
>> > >  arch/riscv/kernel/setup.c                   |   2 +
>> > >  arch/riscv/kernel/smpboot.c                 |   4 -
>> > >  arch/riscv/kernel/traps.c                   |   2 +-
>> > >  arch/riscv/mm/init.c                        |   1 +
>> > >  27 files changed, 546 insertions(+), 114 deletions(-)
>> > >  create mode 100644 arch/riscv/errata/thead/Makefile
>> > >  create mode 100644 arch/riscv/errata/thead/errata.c
>> > >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
>> > 
>> 
>> 

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Palmer Dabbelt]

On Wed, 09 Mar 2022 14:06:55 PST (-0800), heiko@sntech.de wrote:
> Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
>> Hi Palmer,
>> 
>> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
>> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
>> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
>> > > for things like non-cacheable pages or I/O memory pages.
>> > >
>> > >
>> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
>> > > types) using the alternatives framework.
>> > >
>> > > This includes a number of changes to the alternatives mechanism itself.
>> > > The biggest one being the move to a more central location, as I expect
>> > > in the future, nearly every chip needing some sort of patching, be it
>> > > either for erratas or for optional features (svpbmt or others).
>> > >
>> > > Detection of the svpbmt functionality is done via Atish's isa extension
>> > > handling series [0] and thus does not need any dt-parsing of its own
>> > > anymore.
>> > >
>> > > The series also introduces support for the memory types of the D1
>> > > which are implemented differently to svpbmt. But when patching anyway
>> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
>> > > location.
>> > >
>> > > The only slightly bigger difference is that the "normal" type is not 0
>> > > as with svpbmt, so kernel patches for this PMA type need to be applied
>> > > even before the MMU is brought up, so the series introduces a separate
>> > > stage for that.
>> > >
>> > >
>> > > In theory this series is 3 parts:
>> > > - sbi cache-flush / null-ptr
>> > 
>> > That first patch looks like an acceptable candidate for fixes.  If 
>> > there's a regression that manifests I'm happy to take it, but if it's 
>> > only possible to manifest a crash with the new stuff then I'm OK just 
>> > holding off until the merge window.
>> 
>> While right now only my poking around the early init via alternatives
>> is affected, the problem exists for everyone.
>> 
>> I.e. I do consider flush_icache_all() to be generic enough that we
>> should expect someone trying to call this in some early code-path
>> as well.
>> 
>> But any call to flush_icache_all() before sbi_init() ran will cause the
>> breakage that is fixed by patch1 .
>> 
>> 
>> So it doesn't look like any _current_ code path has that issue, but
>> it might be good to just pick patch1 for the next merge window
>> individually?
>> 
>> 
>> 
>> > > - alternatives improvements
>> > > - svpbmt+d1
>> > >
>> > > So expecially patches from the first 2 areas could be applied when
>> > > deemed ready, I just thought to keep it together to show-case where
>> > > the end-goal is and not requiring jumping between different series.
>> > >
>> > >
>> > > I picked the recipient list from the previous versions, hopefully
>> > > I didn't forget anybody.
>> > >
>> > > changes in v7:
>> > > - fix typo in patch1 (Atish)
>> > > - moved to Atish's isa-extension framework
>> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
>> > > - change T-Head errata Kconfig text (Atish)
>> > 
>> > I was just poking around v6, so I have some minor comments there.  None 
>> > of those need to block merging this, but I am getting a bunch of build 
>> > failures under allmodconfig
>> > 
>> >     $ make.riscv allmodconfig
>> >     #
>> >     # configuration written to .config
>> >     #
>> >     $ make.riscv mm/kasan/init.o
>> >       SYNC    include/config/auto.conf.cmd
>> >       CALL    scripts/atomic/check-atomics.sh
>> >       CC      arch/riscv/kernel/asm-offsets.s
>> >       CALL    scripts/checksyscalls.sh
>> >       CC      mm/kasan/init.o
>> >     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
>> >     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
>> >     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
>> >     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
>> >     make: *** [Makefile:1831: mm] Error 2
>> > 
>> > Unfortunately my build box just blew up so I haven't had time to confim 
>> > this still exists on v7, but nothing's jumping out as a fix.  I've put 
>> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
>> > what's going on but I'm guessing one of the macros has gone off the 
>> > rails.  I'm going to look at something else (as this one at least 
>> > depends on Atish's patches), but LMK if you've got the time to look into 
>> > this or if I should.
>> 
>> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
>> series and some more series I saw on the list), so getting that into a
>> mergeable position would be really great :-)
>> 
>> "attempt to move .org backwards" seems to be the telltale sign of the
>> alternatives blocks not matching up in size. While I definitly didn't see
>> anything like this in my tests on qemu + d1, I'll try to investigate where
>> that comes from.
>
> Hmm, looking at your branch [0] it seems that you're missing
> patch7 that introduces the no-compressed-instruction thingy
> for alternatives.
>
> And missing that patch will of course cause the size issue.
>
> The patch has made its way to the actual mailing lists [1], so I guess
> it "just" somehow didn't reach your inbox due to some mail hickup?

Sorry about that, I'm not sure what happened.

Unfortunately I'm now getting some even trickier failures: a handful of 
configurations are failing very early in boot.  There doesn't seem to be 
much pattern to the configs that fail, but at least rv32 defconfig (on 
QEMU's virt board) is doing so.  I've tried poking around a bit and 
can't figure out what's going on.  I'll try and look again tomorrow 
morning.

I've put my somewhat messy merged test branch at 
kernel.org/palmer/riscv-d1-merge .  Happy to hear if you have any 
insights, otherwise I'l give it another shot (possibly after looking at 
some other patches, there's quite a bit of a queue for this late).

>
>
> Heiko
>
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
> [1] https://lore.kernel.org/all/20220307205310.1905628-8-heiko@sntech.de/
>
>
>> > > changes in v6:
>> > > - rebase onto 5.17-rc1
>> > > - handle sbi null-ptr differently
>> > > - improve commit messages
>> > > - use riscv,mmu as property name
>> > >
>> > > changes in v5:
>> > > - move to use alternatives for runtime-patching
>> > > - add D1 variant
>> > >
>> > >
>> > > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
>> > >
>> > >
>> > > Heiko Stuebner (12):
>> > >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
>> > >   riscv: integrate alternatives better into the main architecture
>> > >   riscv: allow different stages with alternatives
>> > >   riscv: implement module alternatives
>> > >   riscv: implement ALTERNATIVE_2 macro
>> > >   riscv: extend concatenated alternatives-lines to the same length
>> > >   riscv: prevent compressed instructions in alternatives
>> > >   riscv: move boot alternatives to after fill_hwcap
>> > >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
>> > >   riscv: add cpufeature handling via alternatives
>> > >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
>> > >   riscv: add memory-type errata for T-Head
>> > >
>> > > Wei Fu (1):
>> > >   riscv: add RISC-V Svpbmt extension support
>> > >
>> > >  arch/riscv/Kconfig.erratas                  |  29 +++--
>> > >  arch/riscv/Kconfig.socs                     |   1 -
>> > >  arch/riscv/Makefile                         |   2 +-
>> > >  arch/riscv/errata/Makefile                  |   2 +-
>> > >  arch/riscv/errata/sifive/errata.c           |  17 ++-
>> > >  arch/riscv/errata/thead/Makefile            |   1 +
>> > >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
>> > >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
>> > >  arch/riscv/include/asm/alternative.h        |  16 ++-
>> > >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
>> > >  arch/riscv/include/asm/fixmap.h             |   2 -
>> > >  arch/riscv/include/asm/hwcap.h              |   1 +
>> > >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
>> > >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
>> > >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
>> > >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
>> > >  arch/riscv/include/asm/vendorid_list.h      |   1 +
>> > >  arch/riscv/kernel/Makefile                  |   1 +
>> > >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
>> > >  arch/riscv/kernel/cpu.c                     |   1 +
>> > >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
>> > >  arch/riscv/kernel/module.c                  |  29 +++++
>> > >  arch/riscv/kernel/sbi.c                     |  10 +-
>> > >  arch/riscv/kernel/setup.c                   |   2 +
>> > >  arch/riscv/kernel/smpboot.c                 |   4 -
>> > >  arch/riscv/kernel/traps.c                   |   2 +-
>> > >  arch/riscv/mm/init.c                        |   1 +
>> > >  27 files changed, 546 insertions(+), 114 deletions(-)
>> > >  create mode 100644 arch/riscv/errata/thead/Makefile
>> > >  create mode 100644 arch/riscv/errata/thead/errata.c
>> > >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
>> > 
>> 
>> 

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Heiko Stübner]

Hi Palmer,

Am Freitag, 18. März 2022, 04:40:23 CET schrieb Palmer Dabbelt:
> On Wed, 09 Mar 2022 14:06:55 PST (-0800), heiko@sntech.de wrote:
> > Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
> >> Hi Palmer,
> >> 
> >> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
> >> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
> >> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> >> > > for things like non-cacheable pages or I/O memory pages.
> >> > >
> >> > >
> >> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> >> > > types) using the alternatives framework.
> >> > >
> >> > > This includes a number of changes to the alternatives mechanism itself.
> >> > > The biggest one being the move to a more central location, as I expect
> >> > > in the future, nearly every chip needing some sort of patching, be it
> >> > > either for erratas or for optional features (svpbmt or others).
> >> > >
> >> > > Detection of the svpbmt functionality is done via Atish's isa extension
> >> > > handling series [0] and thus does not need any dt-parsing of its own
> >> > > anymore.
> >> > >
> >> > > The series also introduces support for the memory types of the D1
> >> > > which are implemented differently to svpbmt. But when patching anyway
> >> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> >> > > location.
> >> > >
> >> > > The only slightly bigger difference is that the "normal" type is not 0
> >> > > as with svpbmt, so kernel patches for this PMA type need to be applied
> >> > > even before the MMU is brought up, so the series introduces a separate
> >> > > stage for that.
> >> > >
> >> > >
> >> > > In theory this series is 3 parts:
> >> > > - sbi cache-flush / null-ptr
> >> > 
> >> > That first patch looks like an acceptable candidate for fixes.  If 
> >> > there's a regression that manifests I'm happy to take it, but if it's 
> >> > only possible to manifest a crash with the new stuff then I'm OK just 
> >> > holding off until the merge window.
> >> 
> >> While right now only my poking around the early init via alternatives
> >> is affected, the problem exists for everyone.
> >> 
> >> I.e. I do consider flush_icache_all() to be generic enough that we
> >> should expect someone trying to call this in some early code-path
> >> as well.
> >> 
> >> But any call to flush_icache_all() before sbi_init() ran will cause the
> >> breakage that is fixed by patch1 .
> >> 
> >> 
> >> So it doesn't look like any _current_ code path has that issue, but
> >> it might be good to just pick patch1 for the next merge window
> >> individually?
> >> 
> >> 
> >> 
> >> > > - alternatives improvements
> >> > > - svpbmt+d1
> >> > >
> >> > > So expecially patches from the first 2 areas could be applied when
> >> > > deemed ready, I just thought to keep it together to show-case where
> >> > > the end-goal is and not requiring jumping between different series.
> >> > >
> >> > >
> >> > > I picked the recipient list from the previous versions, hopefully
> >> > > I didn't forget anybody.
> >> > >
> >> > > changes in v7:
> >> > > - fix typo in patch1 (Atish)
> >> > > - moved to Atish's isa-extension framework
> >> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
> >> > > - change T-Head errata Kconfig text (Atish)
> >> > 
> >> > I was just poking around v6, so I have some minor comments there.  None 
> >> > of those need to block merging this, but I am getting a bunch of build 
> >> > failures under allmodconfig
> >> > 
> >> >     $ make.riscv allmodconfig
> >> >     #
> >> >     # configuration written to .config
> >> >     #
> >> >     $ make.riscv mm/kasan/init.o
> >> >       SYNC    include/config/auto.conf.cmd
> >> >       CALL    scripts/atomic/check-atomics.sh
> >> >       CC      arch/riscv/kernel/asm-offsets.s
> >> >       CALL    scripts/checksyscalls.sh
> >> >       CC      mm/kasan/init.o
> >> >     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
> >> >     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
> >> >     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
> >> >     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
> >> >     make: *** [Makefile:1831: mm] Error 2
> >> > 
> >> > Unfortunately my build box just blew up so I haven't had time to confim 
> >> > this still exists on v7, but nothing's jumping out as a fix.  I've put 
> >> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
> >> > what's going on but I'm guessing one of the macros has gone off the 
> >> > rails.  I'm going to look at something else (as this one at least 
> >> > depends on Atish's patches), but LMK if you've got the time to look into 
> >> > this or if I should.
> >> 
> >> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
> >> series and some more series I saw on the list), so getting that into a
> >> mergeable position would be really great :-)
> >> 
> >> "attempt to move .org backwards" seems to be the telltale sign of the
> >> alternatives blocks not matching up in size. While I definitly didn't see
> >> anything like this in my tests on qemu + d1, I'll try to investigate where
> >> that comes from.
> >
> > Hmm, looking at your branch [0] it seems that you're missing
> > patch7 that introduces the no-compressed-instruction thingy
> > for alternatives.
> >
> > And missing that patch will of course cause the size issue.
> >
> > The patch has made its way to the actual mailing lists [1], so I guess
> > it "just" somehow didn't reach your inbox due to some mail hickup?
> 
> Sorry about that, I'm not sure what happened.

no worries :-) . And I also have no clue where the hickup happened
but am thankful that there is no general problem with mails.


> Unfortunately I'm now getting some even trickier failures: a handful of 
> configurations are failing very early in boot.  There doesn't seem to be 
> much pattern to the configs that fail, but at least rv32 defconfig (on 
> QEMU's virt board) is doing so.  I've tried poking around a bit and 
> can't figure out what's going on.  I'll try and look again tomorrow 
> morning.

Hmm, really strange especially as the whole thing is somewhat
limited to 64bit anyway.

I guess it would be interesting if it's in the alternative-basics
part of the svpbmt implementation.

My short try on getting a (any) rv32 kernel boot in qemu wasn't sucessful
yet, so I'll need to poke that more next week.

Heiko


> I've put my somewhat messy merged test branch at 
> kernel.org/palmer/riscv-d1-merge .  Happy to hear if you have any 
> insights, otherwise I'l give it another shot (possibly after looking at 
> some other patches, there's quite a bit of a queue for this late).
> 
> >
> >
> > Heiko
> >
> >
> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
> > [1] https://lore.kernel.org/all/20220307205310.1905628-8-heiko@sntech.de/
> >
> >
> >> > > changes in v6:
> >> > > - rebase onto 5.17-rc1
> >> > > - handle sbi null-ptr differently
> >> > > - improve commit messages
> >> > > - use riscv,mmu as property name
> >> > >
> >> > > changes in v5:
> >> > > - move to use alternatives for runtime-patching
> >> > > - add D1 variant
> >> > >
> >> > >
> >> > > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
> >> > >
> >> > >
> >> > > Heiko Stuebner (12):
> >> > >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
> >> > >   riscv: integrate alternatives better into the main architecture
> >> > >   riscv: allow different stages with alternatives
> >> > >   riscv: implement module alternatives
> >> > >   riscv: implement ALTERNATIVE_2 macro
> >> > >   riscv: extend concatenated alternatives-lines to the same length
> >> > >   riscv: prevent compressed instructions in alternatives
> >> > >   riscv: move boot alternatives to after fill_hwcap
> >> > >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> >> > >   riscv: add cpufeature handling via alternatives
> >> > >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> >> > >   riscv: add memory-type errata for T-Head
> >> > >
> >> > > Wei Fu (1):
> >> > >   riscv: add RISC-V Svpbmt extension support
> >> > >
> >> > >  arch/riscv/Kconfig.erratas                  |  29 +++--
> >> > >  arch/riscv/Kconfig.socs                     |   1 -
> >> > >  arch/riscv/Makefile                         |   2 +-
> >> > >  arch/riscv/errata/Makefile                  |   2 +-
> >> > >  arch/riscv/errata/sifive/errata.c           |  17 ++-
> >> > >  arch/riscv/errata/thead/Makefile            |   1 +
> >> > >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
> >> > >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
> >> > >  arch/riscv/include/asm/alternative.h        |  16 ++-
> >> > >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
> >> > >  arch/riscv/include/asm/fixmap.h             |   2 -
> >> > >  arch/riscv/include/asm/hwcap.h              |   1 +
> >> > >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
> >> > >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
> >> > >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
> >> > >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
> >> > >  arch/riscv/include/asm/vendorid_list.h      |   1 +
> >> > >  arch/riscv/kernel/Makefile                  |   1 +
> >> > >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
> >> > >  arch/riscv/kernel/cpu.c                     |   1 +
> >> > >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
> >> > >  arch/riscv/kernel/module.c                  |  29 +++++
> >> > >  arch/riscv/kernel/sbi.c                     |  10 +-
> >> > >  arch/riscv/kernel/setup.c                   |   2 +
> >> > >  arch/riscv/kernel/smpboot.c                 |   4 -
> >> > >  arch/riscv/kernel/traps.c                   |   2 +-
> >> > >  arch/riscv/mm/init.c                        |   1 +
> >> > >  27 files changed, 546 insertions(+), 114 deletions(-)
> >> > >  create mode 100644 arch/riscv/errata/thead/Makefile
> >> > >  create mode 100644 arch/riscv/errata/thead/errata.c
> >> > >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
> >> > 
> >> 
> >> 
> 





_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Heiko Stübner]

Hi Palmer,

Am Freitag, 18. März 2022, 04:40:23 CET schrieb Palmer Dabbelt:
> On Wed, 09 Mar 2022 14:06:55 PST (-0800), heiko@sntech.de wrote:
> > Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
> >> Hi Palmer,
> >> 
> >> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
> >> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
> >> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> >> > > for things like non-cacheable pages or I/O memory pages.
> >> > >
> >> > >
> >> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> >> > > types) using the alternatives framework.
> >> > >
> >> > > This includes a number of changes to the alternatives mechanism itself.
> >> > > The biggest one being the move to a more central location, as I expect
> >> > > in the future, nearly every chip needing some sort of patching, be it
> >> > > either for erratas or for optional features (svpbmt or others).
> >> > >
> >> > > Detection of the svpbmt functionality is done via Atish's isa extension
> >> > > handling series [0] and thus does not need any dt-parsing of its own
> >> > > anymore.
> >> > >
> >> > > The series also introduces support for the memory types of the D1
> >> > > which are implemented differently to svpbmt. But when patching anyway
> >> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> >> > > location.
> >> > >
> >> > > The only slightly bigger difference is that the "normal" type is not 0
> >> > > as with svpbmt, so kernel patches for this PMA type need to be applied
> >> > > even before the MMU is brought up, so the series introduces a separate
> >> > > stage for that.
> >> > >
> >> > >
> >> > > In theory this series is 3 parts:
> >> > > - sbi cache-flush / null-ptr
> >> > 
> >> > That first patch looks like an acceptable candidate for fixes.  If 
> >> > there's a regression that manifests I'm happy to take it, but if it's 
> >> > only possible to manifest a crash with the new stuff then I'm OK just 
> >> > holding off until the merge window.
> >> 
> >> While right now only my poking around the early init via alternatives
> >> is affected, the problem exists for everyone.
> >> 
> >> I.e. I do consider flush_icache_all() to be generic enough that we
> >> should expect someone trying to call this in some early code-path
> >> as well.
> >> 
> >> But any call to flush_icache_all() before sbi_init() ran will cause the
> >> breakage that is fixed by patch1 .
> >> 
> >> 
> >> So it doesn't look like any _current_ code path has that issue, but
> >> it might be good to just pick patch1 for the next merge window
> >> individually?
> >> 
> >> 
> >> 
> >> > > - alternatives improvements
> >> > > - svpbmt+d1
> >> > >
> >> > > So expecially patches from the first 2 areas could be applied when
> >> > > deemed ready, I just thought to keep it together to show-case where
> >> > > the end-goal is and not requiring jumping between different series.
> >> > >
> >> > >
> >> > > I picked the recipient list from the previous versions, hopefully
> >> > > I didn't forget anybody.
> >> > >
> >> > > changes in v7:
> >> > > - fix typo in patch1 (Atish)
> >> > > - moved to Atish's isa-extension framework
> >> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
> >> > > - change T-Head errata Kconfig text (Atish)
> >> > 
> >> > I was just poking around v6, so I have some minor comments there.  None 
> >> > of those need to block merging this, but I am getting a bunch of build 
> >> > failures under allmodconfig
> >> > 
> >> >     $ make.riscv allmodconfig
> >> >     #
> >> >     # configuration written to .config
> >> >     #
> >> >     $ make.riscv mm/kasan/init.o
> >> >       SYNC    include/config/auto.conf.cmd
> >> >       CALL    scripts/atomic/check-atomics.sh
> >> >       CC      arch/riscv/kernel/asm-offsets.s
> >> >       CALL    scripts/checksyscalls.sh
> >> >       CC      mm/kasan/init.o
> >> >     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
> >> >     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
> >> >     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
> >> >     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
> >> >     make: *** [Makefile:1831: mm] Error 2
> >> > 
> >> > Unfortunately my build box just blew up so I haven't had time to confim 
> >> > this still exists on v7, but nothing's jumping out as a fix.  I've put 
> >> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
> >> > what's going on but I'm guessing one of the macros has gone off the 
> >> > rails.  I'm going to look at something else (as this one at least 
> >> > depends on Atish's patches), but LMK if you've got the time to look into 
> >> > this or if I should.
> >> 
> >> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
> >> series and some more series I saw on the list), so getting that into a
> >> mergeable position would be really great :-)
> >> 
> >> "attempt to move .org backwards" seems to be the telltale sign of the
> >> alternatives blocks not matching up in size. While I definitly didn't see
> >> anything like this in my tests on qemu + d1, I'll try to investigate where
> >> that comes from.
> >
> > Hmm, looking at your branch [0] it seems that you're missing
> > patch7 that introduces the no-compressed-instruction thingy
> > for alternatives.
> >
> > And missing that patch will of course cause the size issue.
> >
> > The patch has made its way to the actual mailing lists [1], so I guess
> > it "just" somehow didn't reach your inbox due to some mail hickup?
> 
> Sorry about that, I'm not sure what happened.

no worries :-) . And I also have no clue where the hickup happened
but am thankful that there is no general problem with mails.


> Unfortunately I'm now getting some even trickier failures: a handful of 
> configurations are failing very early in boot.  There doesn't seem to be 
> much pattern to the configs that fail, but at least rv32 defconfig (on 
> QEMU's virt board) is doing so.  I've tried poking around a bit and 
> can't figure out what's going on.  I'll try and look again tomorrow 
> morning.

Hmm, really strange especially as the whole thing is somewhat
limited to 64bit anyway.

I guess it would be interesting if it's in the alternative-basics
part of the svpbmt implementation.

My short try on getting a (any) rv32 kernel boot in qemu wasn't sucessful
yet, so I'll need to poke that more next week.

Heiko


> I've put my somewhat messy merged test branch at 
> kernel.org/palmer/riscv-d1-merge .  Happy to hear if you have any 
> insights, otherwise I'l give it another shot (possibly after looking at 
> some other patches, there's quite a bit of a queue for this late).
> 
> >
> >
> > Heiko
> >
> >
> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
> > [1] https://lore.kernel.org/all/20220307205310.1905628-8-heiko@sntech.de/
> >
> >
> >> > > changes in v6:
> >> > > - rebase onto 5.17-rc1
> >> > > - handle sbi null-ptr differently
> >> > > - improve commit messages
> >> > > - use riscv,mmu as property name
> >> > >
> >> > > changes in v5:
> >> > > - move to use alternatives for runtime-patching
> >> > > - add D1 variant
> >> > >
> >> > >
> >> > > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
> >> > >
> >> > >
> >> > > Heiko Stuebner (12):
> >> > >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
> >> > >   riscv: integrate alternatives better into the main architecture
> >> > >   riscv: allow different stages with alternatives
> >> > >   riscv: implement module alternatives
> >> > >   riscv: implement ALTERNATIVE_2 macro
> >> > >   riscv: extend concatenated alternatives-lines to the same length
> >> > >   riscv: prevent compressed instructions in alternatives
> >> > >   riscv: move boot alternatives to after fill_hwcap
> >> > >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> >> > >   riscv: add cpufeature handling via alternatives
> >> > >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> >> > >   riscv: add memory-type errata for T-Head
> >> > >
> >> > > Wei Fu (1):
> >> > >   riscv: add RISC-V Svpbmt extension support
> >> > >
> >> > >  arch/riscv/Kconfig.erratas                  |  29 +++--
> >> > >  arch/riscv/Kconfig.socs                     |   1 -
> >> > >  arch/riscv/Makefile                         |   2 +-
> >> > >  arch/riscv/errata/Makefile                  |   2 +-
> >> > >  arch/riscv/errata/sifive/errata.c           |  17 ++-
> >> > >  arch/riscv/errata/thead/Makefile            |   1 +
> >> > >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
> >> > >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
> >> > >  arch/riscv/include/asm/alternative.h        |  16 ++-
> >> > >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
> >> > >  arch/riscv/include/asm/fixmap.h             |   2 -
> >> > >  arch/riscv/include/asm/hwcap.h              |   1 +
> >> > >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
> >> > >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
> >> > >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
> >> > >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
> >> > >  arch/riscv/include/asm/vendorid_list.h      |   1 +
> >> > >  arch/riscv/kernel/Makefile                  |   1 +
> >> > >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
> >> > >  arch/riscv/kernel/cpu.c                     |   1 +
> >> > >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
> >> > >  arch/riscv/kernel/module.c                  |  29 +++++
> >> > >  arch/riscv/kernel/sbi.c                     |  10 +-
> >> > >  arch/riscv/kernel/setup.c                   |   2 +
> >> > >  arch/riscv/kernel/smpboot.c                 |   4 -
> >> > >  arch/riscv/kernel/traps.c                   |   2 +-
> >> > >  arch/riscv/mm/init.c                        |   1 +
> >> > >  27 files changed, 546 insertions(+), 114 deletions(-)
> >> > >  create mode 100644 arch/riscv/errata/thead/Makefile
> >> > >  create mode 100644 arch/riscv/errata/thead/errata.c
> >> > >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
> >> > 
> >> 
> >> 
> 

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Palmer Dabbelt]

On Fri, 18 Mar 2022 09:22:29 PDT (-0700), heiko@sntech.de wrote:
> Hi Palmer,
>
> Am Freitag, 18. März 2022, 04:40:23 CET schrieb Palmer Dabbelt:
>> On Wed, 09 Mar 2022 14:06:55 PST (-0800), heiko@sntech.de wrote:
>> > Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
>> >> Hi Palmer,
>> >> 
>> >> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
>> >> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
>> >> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
>> >> > > for things like non-cacheable pages or I/O memory pages.
>> >> > >
>> >> > >
>> >> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
>> >> > > types) using the alternatives framework.
>> >> > >
>> >> > > This includes a number of changes to the alternatives mechanism itself.
>> >> > > The biggest one being the move to a more central location, as I expect
>> >> > > in the future, nearly every chip needing some sort of patching, be it
>> >> > > either for erratas or for optional features (svpbmt or others).
>> >> > >
>> >> > > Detection of the svpbmt functionality is done via Atish's isa extension
>> >> > > handling series [0] and thus does not need any dt-parsing of its own
>> >> > > anymore.
>> >> > >
>> >> > > The series also introduces support for the memory types of the D1
>> >> > > which are implemented differently to svpbmt. But when patching anyway
>> >> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
>> >> > > location.
>> >> > >
>> >> > > The only slightly bigger difference is that the "normal" type is not 0
>> >> > > as with svpbmt, so kernel patches for this PMA type need to be applied
>> >> > > even before the MMU is brought up, so the series introduces a separate
>> >> > > stage for that.
>> >> > >
>> >> > >
>> >> > > In theory this series is 3 parts:
>> >> > > - sbi cache-flush / null-ptr
>> >> > 
>> >> > That first patch looks like an acceptable candidate for fixes.  If 
>> >> > there's a regression that manifests I'm happy to take it, but if it's 
>> >> > only possible to manifest a crash with the new stuff then I'm OK just 
>> >> > holding off until the merge window.
>> >> 
>> >> While right now only my poking around the early init via alternatives
>> >> is affected, the problem exists for everyone.
>> >> 
>> >> I.e. I do consider flush_icache_all() to be generic enough that we
>> >> should expect someone trying to call this in some early code-path
>> >> as well.
>> >> 
>> >> But any call to flush_icache_all() before sbi_init() ran will cause the
>> >> breakage that is fixed by patch1 .
>> >> 
>> >> 
>> >> So it doesn't look like any _current_ code path has that issue, but
>> >> it might be good to just pick patch1 for the next merge window
>> >> individually?
>> >> 
>> >> 
>> >> 
>> >> > > - alternatives improvements
>> >> > > - svpbmt+d1
>> >> > >
>> >> > > So expecially patches from the first 2 areas could be applied when
>> >> > > deemed ready, I just thought to keep it together to show-case where
>> >> > > the end-goal is and not requiring jumping between different series.
>> >> > >
>> >> > >
>> >> > > I picked the recipient list from the previous versions, hopefully
>> >> > > I didn't forget anybody.
>> >> > >
>> >> > > changes in v7:
>> >> > > - fix typo in patch1 (Atish)
>> >> > > - moved to Atish's isa-extension framework
>> >> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
>> >> > > - change T-Head errata Kconfig text (Atish)
>> >> > 
>> >> > I was just poking around v6, so I have some minor comments there.  None 
>> >> > of those need to block merging this, but I am getting a bunch of build 
>> >> > failures under allmodconfig
>> >> > 
>> >> >     $ make.riscv allmodconfig
>> >> >     #
>> >> >     # configuration written to .config
>> >> >     #
>> >> >     $ make.riscv mm/kasan/init.o
>> >> >       SYNC    include/config/auto.conf.cmd
>> >> >       CALL    scripts/atomic/check-atomics.sh
>> >> >       CC      arch/riscv/kernel/asm-offsets.s
>> >> >       CALL    scripts/checksyscalls.sh
>> >> >       CC      mm/kasan/init.o
>> >> >     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
>> >> >     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
>> >> >     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
>> >> >     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
>> >> >     make: *** [Makefile:1831: mm] Error 2
>> >> > 
>> >> > Unfortunately my build box just blew up so I haven't had time to confim 
>> >> > this still exists on v7, but nothing's jumping out as a fix.  I've put 
>> >> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
>> >> > what's going on but I'm guessing one of the macros has gone off the 
>> >> > rails.  I'm going to look at something else (as this one at least 
>> >> > depends on Atish's patches), but LMK if you've got the time to look into 
>> >> > this or if I should.
>> >> 
>> >> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
>> >> series and some more series I saw on the list), so getting that into a
>> >> mergeable position would be really great :-)
>> >> 
>> >> "attempt to move .org backwards" seems to be the telltale sign of the
>> >> alternatives blocks not matching up in size. While I definitly didn't see
>> >> anything like this in my tests on qemu + d1, I'll try to investigate where
>> >> that comes from.
>> >
>> > Hmm, looking at your branch [0] it seems that you're missing
>> > patch7 that introduces the no-compressed-instruction thingy
>> > for alternatives.
>> >
>> > And missing that patch will of course cause the size issue.
>> >
>> > The patch has made its way to the actual mailing lists [1], so I guess
>> > it "just" somehow didn't reach your inbox due to some mail hickup?
>> 
>> Sorry about that, I'm not sure what happened.
>
> no worries :-) . And I also have no clue where the hickup happened
> but am thankful that there is no general problem with mails.
>
>
>> Unfortunately I'm now getting some even trickier failures: a handful of 
>> configurations are failing very early in boot.  There doesn't seem to be 
>> much pattern to the configs that fail, but at least rv32 defconfig (on 
>> QEMU's virt board) is doing so.  I've tried poking around a bit and 
>> can't figure out what's going on.  I'll try and look again tomorrow 
>> morning.

(I guess morning means 2pm these days...)

> Hmm, really strange especially as the whole thing is somewhat
> limited to 64bit anyway.
>
> I guess it would be interesting if it's in the alternative-basics
> part of the svpbmt implementation.

Oddly enough it seems to be hanging as soon as I call into any of the 
m*id SBI routines, but I'm not entierly sure what's up and I've been 
bouncing between things so I might just be crazy.

I did bisect the rv32-defconfig failure down to the last patch.

>
> My short try on getting a (any) rv32 kernel boot in qemu wasn't sucessful
> yet, so I'll need to poke that more next week.

There's a bunch of failing cases, not just rv32, but I can't figure out 
what logic there is behind the failing cases.  They're all in my 
riscv-system-ci repo, it's a mess but should at least build.  I see the 
following hang:

    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-strict_rwx/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-strict_rwx/initrd -serial mon:pipe:/tmp/tmp.BM8zYJCKKZ/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/initrd -serial mon:pipe:/tmp/tmp.x7BL4Y1UsX/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.I9NZ3ow1GY/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.c9UPXaNcfR/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.AkLFnd3IDt/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.TbUWlXHDtO/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.E4h3Gw5Ecv/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab/initrd -serial mon:pipe:/tmp/tmp.anq8X90A1C/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.4MK3Xys4YL/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-vmap_stack/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-vmap_stack/initrd -serial mon:pipe:/tmp/tmp.fC0b16uUpo/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.t8nlK1Cvkk/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.stV634slMi/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.D0M6BSjwo2/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.x9AoOydj6h/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.cYwEP0Xod2/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.EmYY46ZyFw/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.UGF8OoNOXr/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.E540ImVMDZ/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.Hg8iJhkm2R/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.4KQh2WmFWc/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M spike -m 1G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-spike/halt-legacy_sbi/kernel -initrd check/qemu-rv64gc-spike/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.Ore2LcgxNR/guest -bios default -nographic -append console=hvc0
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.jnvHnbSJKT/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.30Kl16f7mY/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.ojW4EsFqOX/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.iKrvig4P7H/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.LGrpnHKQXO/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/initrd -serial mon:pipe:/tmp/tmp.0RO7a4EUiB/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-defconfig/initrd -serial mon:pipe:/tmp/tmp.Ltd1s19HqT/guest -bios default -nographic

rv32 defconfig seemed like the simplest, but there's a bunch of rv64 
configs that fail too (though not defconfig, and the earlycon configs 
don't hang).

I'm going to go look at that other stuff I wanted to, but I'll try and 
find some time this weekend if nobody else can figure out what's up.


>
> Heiko
>
>
>> I've put my somewhat messy merged test branch at 
>> kernel.org/palmer/riscv-d1-merge .  Happy to hear if you have any 
>> insights, otherwise I'l give it another shot (possibly after looking at 
>> some other patches, there's quite a bit of a queue for this late).
>> 
>> >
>> >
>> > Heiko
>> >
>> >
>> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
>> > [1] https://lore.kernel.org/all/20220307205310.1905628-8-heiko@sntech.de/
>> >
>> >
>> >> > > changes in v6:
>> >> > > - rebase onto 5.17-rc1
>> >> > > - handle sbi null-ptr differently
>> >> > > - improve commit messages
>> >> > > - use riscv,mmu as property name
>> >> > >
>> >> > > changes in v5:
>> >> > > - move to use alternatives for runtime-patching
>> >> > > - add D1 variant
>> >> > >
>> >> > >
>> >> > > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
>> >> > >
>> >> > >
>> >> > > Heiko Stuebner (12):
>> >> > >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
>> >> > >   riscv: integrate alternatives better into the main architecture
>> >> > >   riscv: allow different stages with alternatives
>> >> > >   riscv: implement module alternatives
>> >> > >   riscv: implement ALTERNATIVE_2 macro
>> >> > >   riscv: extend concatenated alternatives-lines to the same length
>> >> > >   riscv: prevent compressed instructions in alternatives
>> >> > >   riscv: move boot alternatives to after fill_hwcap
>> >> > >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
>> >> > >   riscv: add cpufeature handling via alternatives
>> >> > >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
>> >> > >   riscv: add memory-type errata for T-Head
>> >> > >
>> >> > > Wei Fu (1):
>> >> > >   riscv: add RISC-V Svpbmt extension support
>> >> > >
>> >> > >  arch/riscv/Kconfig.erratas                  |  29 +++--
>> >> > >  arch/riscv/Kconfig.socs                     |   1 -
>> >> > >  arch/riscv/Makefile                         |   2 +-
>> >> > >  arch/riscv/errata/Makefile                  |   2 +-
>> >> > >  arch/riscv/errata/sifive/errata.c           |  17 ++-
>> >> > >  arch/riscv/errata/thead/Makefile            |   1 +
>> >> > >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
>> >> > >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
>> >> > >  arch/riscv/include/asm/alternative.h        |  16 ++-
>> >> > >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
>> >> > >  arch/riscv/include/asm/fixmap.h             |   2 -
>> >> > >  arch/riscv/include/asm/hwcap.h              |   1 +
>> >> > >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
>> >> > >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
>> >> > >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
>> >> > >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
>> >> > >  arch/riscv/include/asm/vendorid_list.h      |   1 +
>> >> > >  arch/riscv/kernel/Makefile                  |   1 +
>> >> > >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
>> >> > >  arch/riscv/kernel/cpu.c                     |   1 +
>> >> > >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
>> >> > >  arch/riscv/kernel/module.c                  |  29 +++++
>> >> > >  arch/riscv/kernel/sbi.c                     |  10 +-
>> >> > >  arch/riscv/kernel/setup.c                   |   2 +
>> >> > >  arch/riscv/kernel/smpboot.c                 |   4 -
>> >> > >  arch/riscv/kernel/traps.c                   |   2 +-
>> >> > >  arch/riscv/mm/init.c                        |   1 +
>> >> > >  27 files changed, 546 insertions(+), 114 deletions(-)
>> >> > >  create mode 100644 arch/riscv/errata/thead/Makefile
>> >> > >  create mode 100644 arch/riscv/errata/thead/errata.c
>> >> > >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
>> >> > 
>> >> 
>> >> 
>> 

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Palmer Dabbelt]

On Fri, 18 Mar 2022 09:22:29 PDT (-0700), heiko@sntech.de wrote:
> Hi Palmer,
>
> Am Freitag, 18. März 2022, 04:40:23 CET schrieb Palmer Dabbelt:
>> On Wed, 09 Mar 2022 14:06:55 PST (-0800), heiko@sntech.de wrote:
>> > Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
>> >> Hi Palmer,
>> >> 
>> >> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
>> >> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
>> >> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
>> >> > > for things like non-cacheable pages or I/O memory pages.
>> >> > >
>> >> > >
>> >> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
>> >> > > types) using the alternatives framework.
>> >> > >
>> >> > > This includes a number of changes to the alternatives mechanism itself.
>> >> > > The biggest one being the move to a more central location, as I expect
>> >> > > in the future, nearly every chip needing some sort of patching, be it
>> >> > > either for erratas or for optional features (svpbmt or others).
>> >> > >
>> >> > > Detection of the svpbmt functionality is done via Atish's isa extension
>> >> > > handling series [0] and thus does not need any dt-parsing of its own
>> >> > > anymore.
>> >> > >
>> >> > > The series also introduces support for the memory types of the D1
>> >> > > which are implemented differently to svpbmt. But when patching anyway
>> >> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
>> >> > > location.
>> >> > >
>> >> > > The only slightly bigger difference is that the "normal" type is not 0
>> >> > > as with svpbmt, so kernel patches for this PMA type need to be applied
>> >> > > even before the MMU is brought up, so the series introduces a separate
>> >> > > stage for that.
>> >> > >
>> >> > >
>> >> > > In theory this series is 3 parts:
>> >> > > - sbi cache-flush / null-ptr
>> >> > 
>> >> > That first patch looks like an acceptable candidate for fixes.  If 
>> >> > there's a regression that manifests I'm happy to take it, but if it's 
>> >> > only possible to manifest a crash with the new stuff then I'm OK just 
>> >> > holding off until the merge window.
>> >> 
>> >> While right now only my poking around the early init via alternatives
>> >> is affected, the problem exists for everyone.
>> >> 
>> >> I.e. I do consider flush_icache_all() to be generic enough that we
>> >> should expect someone trying to call this in some early code-path
>> >> as well.
>> >> 
>> >> But any call to flush_icache_all() before sbi_init() ran will cause the
>> >> breakage that is fixed by patch1 .
>> >> 
>> >> 
>> >> So it doesn't look like any _current_ code path has that issue, but
>> >> it might be good to just pick patch1 for the next merge window
>> >> individually?
>> >> 
>> >> 
>> >> 
>> >> > > - alternatives improvements
>> >> > > - svpbmt+d1
>> >> > >
>> >> > > So expecially patches from the first 2 areas could be applied when
>> >> > > deemed ready, I just thought to keep it together to show-case where
>> >> > > the end-goal is and not requiring jumping between different series.
>> >> > >
>> >> > >
>> >> > > I picked the recipient list from the previous versions, hopefully
>> >> > > I didn't forget anybody.
>> >> > >
>> >> > > changes in v7:
>> >> > > - fix typo in patch1 (Atish)
>> >> > > - moved to Atish's isa-extension framework
>> >> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
>> >> > > - change T-Head errata Kconfig text (Atish)
>> >> > 
>> >> > I was just poking around v6, so I have some minor comments there.  None 
>> >> > of those need to block merging this, but I am getting a bunch of build 
>> >> > failures under allmodconfig
>> >> > 
>> >> >     $ make.riscv allmodconfig
>> >> >     #
>> >> >     # configuration written to .config
>> >> >     #
>> >> >     $ make.riscv mm/kasan/init.o
>> >> >       SYNC    include/config/auto.conf.cmd
>> >> >       CALL    scripts/atomic/check-atomics.sh
>> >> >       CC      arch/riscv/kernel/asm-offsets.s
>> >> >       CALL    scripts/checksyscalls.sh
>> >> >       CC      mm/kasan/init.o
>> >> >     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
>> >> >     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
>> >> >     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
>> >> >     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
>> >> >     make: *** [Makefile:1831: mm] Error 2
>> >> > 
>> >> > Unfortunately my build box just blew up so I haven't had time to confim 
>> >> > this still exists on v7, but nothing's jumping out as a fix.  I've put 
>> >> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
>> >> > what's going on but I'm guessing one of the macros has gone off the 
>> >> > rails.  I'm going to look at something else (as this one at least 
>> >> > depends on Atish's patches), but LMK if you've got the time to look into 
>> >> > this or if I should.
>> >> 
>> >> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
>> >> series and some more series I saw on the list), so getting that into a
>> >> mergeable position would be really great :-)
>> >> 
>> >> "attempt to move .org backwards" seems to be the telltale sign of the
>> >> alternatives blocks not matching up in size. While I definitly didn't see
>> >> anything like this in my tests on qemu + d1, I'll try to investigate where
>> >> that comes from.
>> >
>> > Hmm, looking at your branch [0] it seems that you're missing
>> > patch7 that introduces the no-compressed-instruction thingy
>> > for alternatives.
>> >
>> > And missing that patch will of course cause the size issue.
>> >
>> > The patch has made its way to the actual mailing lists [1], so I guess
>> > it "just" somehow didn't reach your inbox due to some mail hickup?
>> 
>> Sorry about that, I'm not sure what happened.
>
> no worries :-) . And I also have no clue where the hickup happened
> but am thankful that there is no general problem with mails.
>
>
>> Unfortunately I'm now getting some even trickier failures: a handful of 
>> configurations are failing very early in boot.  There doesn't seem to be 
>> much pattern to the configs that fail, but at least rv32 defconfig (on 
>> QEMU's virt board) is doing so.  I've tried poking around a bit and 
>> can't figure out what's going on.  I'll try and look again tomorrow 
>> morning.

(I guess morning means 2pm these days...)

> Hmm, really strange especially as the whole thing is somewhat
> limited to 64bit anyway.
>
> I guess it would be interesting if it's in the alternative-basics
> part of the svpbmt implementation.

Oddly enough it seems to be hanging as soon as I call into any of the 
m*id SBI routines, but I'm not entierly sure what's up and I've been 
bouncing between things so I might just be crazy.

I did bisect the rv32-defconfig failure down to the last patch.

>
> My short try on getting a (any) rv32 kernel boot in qemu wasn't sucessful
> yet, so I'll need to poke that more next week.

There's a bunch of failing cases, not just rv32, but I can't figure out 
what logic there is behind the failing cases.  They're all in my 
riscv-system-ci repo, it's a mess but should at least build.  I see the 
following hang:

    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-strict_rwx/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-strict_rwx/initrd -serial mon:pipe:/tmp/tmp.BM8zYJCKKZ/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/initrd -serial mon:pipe:/tmp/tmp.x7BL4Y1UsX/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.I9NZ3ow1GY/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.c9UPXaNcfR/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.AkLFnd3IDt/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.TbUWlXHDtO/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.E4h3Gw5Ecv/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab/initrd -serial mon:pipe:/tmp/tmp.anq8X90A1C/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.4MK3Xys4YL/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-vmap_stack/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-vmap_stack/initrd -serial mon:pipe:/tmp/tmp.fC0b16uUpo/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.t8nlK1Cvkk/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.stV634slMi/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.D0M6BSjwo2/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.x9AoOydj6h/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.cYwEP0Xod2/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.EmYY46ZyFw/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.UGF8OoNOXr/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.E540ImVMDZ/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.Hg8iJhkm2R/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.4KQh2WmFWc/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M spike -m 1G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-spike/halt-legacy_sbi/kernel -initrd check/qemu-rv64gc-spike/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.Ore2LcgxNR/guest -bios default -nographic -append console=hvc0
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.jnvHnbSJKT/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.30Kl16f7mY/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.ojW4EsFqOX/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.iKrvig4P7H/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.LGrpnHKQXO/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/initrd -serial mon:pipe:/tmp/tmp.0RO7a4EUiB/guest -bios default -nographic
    qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-defconfig/initrd -serial mon:pipe:/tmp/tmp.Ltd1s19HqT/guest -bios default -nographic

rv32 defconfig seemed like the simplest, but there's a bunch of rv64 
configs that fail too (though not defconfig, and the earlycon configs 
don't hang).

I'm going to go look at that other stuff I wanted to, but I'll try and 
find some time this weekend if nobody else can figure out what's up.


>
> Heiko
>
>
>> I've put my somewhat messy merged test branch at 
>> kernel.org/palmer/riscv-d1-merge .  Happy to hear if you have any 
>> insights, otherwise I'l give it another shot (possibly after looking at 
>> some other patches, there's quite a bit of a queue for this late).
>> 
>> >
>> >
>> > Heiko
>> >
>> >
>> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
>> > [1] https://lore.kernel.org/all/20220307205310.1905628-8-heiko@sntech.de/
>> >
>> >
>> >> > > changes in v6:
>> >> > > - rebase onto 5.17-rc1
>> >> > > - handle sbi null-ptr differently
>> >> > > - improve commit messages
>> >> > > - use riscv,mmu as property name
>> >> > >
>> >> > > changes in v5:
>> >> > > - move to use alternatives for runtime-patching
>> >> > > - add D1 variant
>> >> > >
>> >> > >
>> >> > > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
>> >> > >
>> >> > >
>> >> > > Heiko Stuebner (12):
>> >> > >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
>> >> > >   riscv: integrate alternatives better into the main architecture
>> >> > >   riscv: allow different stages with alternatives
>> >> > >   riscv: implement module alternatives
>> >> > >   riscv: implement ALTERNATIVE_2 macro
>> >> > >   riscv: extend concatenated alternatives-lines to the same length
>> >> > >   riscv: prevent compressed instructions in alternatives
>> >> > >   riscv: move boot alternatives to after fill_hwcap
>> >> > >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
>> >> > >   riscv: add cpufeature handling via alternatives
>> >> > >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
>> >> > >   riscv: add memory-type errata for T-Head
>> >> > >
>> >> > > Wei Fu (1):
>> >> > >   riscv: add RISC-V Svpbmt extension support
>> >> > >
>> >> > >  arch/riscv/Kconfig.erratas                  |  29 +++--
>> >> > >  arch/riscv/Kconfig.socs                     |   1 -
>> >> > >  arch/riscv/Makefile                         |   2 +-
>> >> > >  arch/riscv/errata/Makefile                  |   2 +-
>> >> > >  arch/riscv/errata/sifive/errata.c           |  17 ++-
>> >> > >  arch/riscv/errata/thead/Makefile            |   1 +
>> >> > >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
>> >> > >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
>> >> > >  arch/riscv/include/asm/alternative.h        |  16 ++-
>> >> > >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
>> >> > >  arch/riscv/include/asm/fixmap.h             |   2 -
>> >> > >  arch/riscv/include/asm/hwcap.h              |   1 +
>> >> > >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
>> >> > >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
>> >> > >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
>> >> > >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
>> >> > >  arch/riscv/include/asm/vendorid_list.h      |   1 +
>> >> > >  arch/riscv/kernel/Makefile                  |   1 +
>> >> > >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
>> >> > >  arch/riscv/kernel/cpu.c                     |   1 +
>> >> > >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
>> >> > >  arch/riscv/kernel/module.c                  |  29 +++++
>> >> > >  arch/riscv/kernel/sbi.c                     |  10 +-
>> >> > >  arch/riscv/kernel/setup.c                   |   2 +
>> >> > >  arch/riscv/kernel/smpboot.c                 |   4 -
>> >> > >  arch/riscv/kernel/traps.c                   |   2 +-
>> >> > >  arch/riscv/mm/init.c                        |   1 +
>> >> > >  27 files changed, 546 insertions(+), 114 deletions(-)
>> >> > >  create mode 100644 arch/riscv/errata/thead/Makefile
>> >> > >  create mode 100644 arch/riscv/errata/thead/errata.c
>> >> > >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
>> >> > 
>> >> 
>> >> 
>> 

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Heiko Stübner]

Am Freitag, 18. März 2022, 22:50:05 CET schrieb Palmer Dabbelt:
> On Fri, 18 Mar 2022 09:22:29 PDT (-0700), heiko@sntech.de wrote:
> > Hi Palmer,
> >
> > Am Freitag, 18. März 2022, 04:40:23 CET schrieb Palmer Dabbelt:
> >> On Wed, 09 Mar 2022 14:06:55 PST (-0800), heiko@sntech.de wrote:
> >> > Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
> >> >> Hi Palmer,
> >> >> 
> >> >> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
> >> >> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
> >> >> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> >> >> > > for things like non-cacheable pages or I/O memory pages.
> >> >> > >
> >> >> > >
> >> >> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> >> >> > > types) using the alternatives framework.
> >> >> > >
> >> >> > > This includes a number of changes to the alternatives mechanism itself.
> >> >> > > The biggest one being the move to a more central location, as I expect
> >> >> > > in the future, nearly every chip needing some sort of patching, be it
> >> >> > > either for erratas or for optional features (svpbmt or others).
> >> >> > >
> >> >> > > Detection of the svpbmt functionality is done via Atish's isa extension
> >> >> > > handling series [0] and thus does not need any dt-parsing of its own
> >> >> > > anymore.
> >> >> > >
> >> >> > > The series also introduces support for the memory types of the D1
> >> >> > > which are implemented differently to svpbmt. But when patching anyway
> >> >> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> >> >> > > location.
> >> >> > >
> >> >> > > The only slightly bigger difference is that the "normal" type is not 0
> >> >> > > as with svpbmt, so kernel patches for this PMA type need to be applied
> >> >> > > even before the MMU is brought up, so the series introduces a separate
> >> >> > > stage for that.
> >> >> > >
> >> >> > >
> >> >> > > In theory this series is 3 parts:
> >> >> > > - sbi cache-flush / null-ptr
> >> >> > 
> >> >> > That first patch looks like an acceptable candidate for fixes.  If 
> >> >> > there's a regression that manifests I'm happy to take it, but if it's 
> >> >> > only possible to manifest a crash with the new stuff then I'm OK just 
> >> >> > holding off until the merge window.
> >> >> 
> >> >> While right now only my poking around the early init via alternatives
> >> >> is affected, the problem exists for everyone.
> >> >> 
> >> >> I.e. I do consider flush_icache_all() to be generic enough that we
> >> >> should expect someone trying to call this in some early code-path
> >> >> as well.
> >> >> 
> >> >> But any call to flush_icache_all() before sbi_init() ran will cause the
> >> >> breakage that is fixed by patch1 .
> >> >> 
> >> >> 
> >> >> So it doesn't look like any _current_ code path has that issue, but
> >> >> it might be good to just pick patch1 for the next merge window
> >> >> individually?
> >> >> 
> >> >> 
> >> >> 
> >> >> > > - alternatives improvements
> >> >> > > - svpbmt+d1
> >> >> > >
> >> >> > > So expecially patches from the first 2 areas could be applied when
> >> >> > > deemed ready, I just thought to keep it together to show-case where
> >> >> > > the end-goal is and not requiring jumping between different series.
> >> >> > >
> >> >> > >
> >> >> > > I picked the recipient list from the previous versions, hopefully
> >> >> > > I didn't forget anybody.
> >> >> > >
> >> >> > > changes in v7:
> >> >> > > - fix typo in patch1 (Atish)
> >> >> > > - moved to Atish's isa-extension framework
> >> >> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
> >> >> > > - change T-Head errata Kconfig text (Atish)
> >> >> > 
> >> >> > I was just poking around v6, so I have some minor comments there.  None 
> >> >> > of those need to block merging this, but I am getting a bunch of build 
> >> >> > failures under allmodconfig
> >> >> > 
> >> >> >     $ make.riscv allmodconfig
> >> >> >     #
> >> >> >     # configuration written to .config
> >> >> >     #
> >> >> >     $ make.riscv mm/kasan/init.o
> >> >> >       SYNC    include/config/auto.conf.cmd
> >> >> >       CALL    scripts/atomic/check-atomics.sh
> >> >> >       CC      arch/riscv/kernel/asm-offsets.s
> >> >> >       CALL    scripts/checksyscalls.sh
> >> >> >       CC      mm/kasan/init.o
> >> >> >     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
> >> >> >     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
> >> >> >     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
> >> >> >     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
> >> >> >     make: *** [Makefile:1831: mm] Error 2
> >> >> > 
> >> >> > Unfortunately my build box just blew up so I haven't had time to confim 
> >> >> > this still exists on v7, but nothing's jumping out as a fix.  I've put 
> >> >> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
> >> >> > what's going on but I'm guessing one of the macros has gone off the 
> >> >> > rails.  I'm going to look at something else (as this one at least 
> >> >> > depends on Atish's patches), but LMK if you've got the time to look into 
> >> >> > this or if I should.
> >> >> 
> >> >> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
> >> >> series and some more series I saw on the list), so getting that into a
> >> >> mergeable position would be really great :-)
> >> >> 
> >> >> "attempt to move .org backwards" seems to be the telltale sign of the
> >> >> alternatives blocks not matching up in size. While I definitly didn't see
> >> >> anything like this in my tests on qemu + d1, I'll try to investigate where
> >> >> that comes from.
> >> >
> >> > Hmm, looking at your branch [0] it seems that you're missing
> >> > patch7 that introduces the no-compressed-instruction thingy
> >> > for alternatives.
> >> >
> >> > And missing that patch will of course cause the size issue.
> >> >
> >> > The patch has made its way to the actual mailing lists [1], so I guess
> >> > it "just" somehow didn't reach your inbox due to some mail hickup?
> >> 
> >> Sorry about that, I'm not sure what happened.
> >
> > no worries :-) . And I also have no clue where the hickup happened
> > but am thankful that there is no general problem with mails.
> >
> >
> >> Unfortunately I'm now getting some even trickier failures: a handful of 
> >> configurations are failing very early in boot.  There doesn't seem to be 
> >> much pattern to the configs that fail, but at least rv32 defconfig (on 
> >> QEMU's virt board) is doing so.  I've tried poking around a bit and 
> >> can't figure out what's going on.  I'll try and look again tomorrow 
> >> morning.
> 
> (I guess morning means 2pm these days...)
> 
> > Hmm, really strange especially as the whole thing is somewhat
> > limited to 64bit anyway.
> >
> > I guess it would be interesting if it's in the alternative-basics
> > part of the svpbmt implementation.
> 
> Oddly enough it seems to be hanging as soon as I call into any of the 
> m*id SBI routines, but I'm not entierly sure what's up and I've been 
> bouncing between things so I might just be crazy.

You're defintily not crazy here :-) .

I.e. I didn't notice your reply from friday until now and so did the same
stepping through the code myself as well, after finally getting a rv32
build working.

Similarly I ended up at sbi_get_mvendorid() being the first failing function.

_But_ ... sbi isn't at fault here. What is causing the issue is the writes
to the static global variables. And I guess that will also be the issue
you saw on the other platforms.

The early-alternatives-mechanism runs before the kernel relocation,
so likely triggers some memory protection, which I didn't think of.

I'll just rework the code to not use static variables for storing both
the architecture-ids as well as the patch-func, which I think should
solve that issue for all platforms.


Heiko


> I did bisect the rv32-defconfig failure down to the last patch.
> 
> >
> > My short try on getting a (any) rv32 kernel boot in qemu wasn't sucessful
> > yet, so I'll need to poke that more next week.
> 
> There's a bunch of failing cases, not just rv32, but I can't figure out 
> what logic there is behind the failing cases.  They're all in my 
> riscv-system-ci repo, it's a mess but should at least build.  I see the 
> following hang:
> 
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-strict_rwx/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-strict_rwx/initrd -serial mon:pipe:/tmp/tmp.BM8zYJCKKZ/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/initrd -serial mon:pipe:/tmp/tmp.x7BL4Y1UsX/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.I9NZ3ow1GY/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.c9UPXaNcfR/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.AkLFnd3IDt/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.TbUWlXHDtO/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.E4h3Gw5Ecv/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab/initrd -serial mon:pipe:/tmp/tmp.anq8X90A1C/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.4MK3Xys4YL/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-vmap_stack/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-vmap_stack/initrd -serial mon:pipe:/tmp/tmp.fC0b16uUpo/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.t8nlK1Cvkk/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.stV634slMi/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.D0M6BSjwo2/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.x9AoOydj6h/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.cYwEP0Xod2/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.EmYY46ZyFw/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.UGF8OoNOXr/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.E540ImVMDZ/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.Hg8iJhkm2R/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.4KQh2WmFWc/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M spike -m 1G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-spike/halt-legacy_sbi/kernel -initrd check/qemu-rv64gc-spike/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.Ore2LcgxNR/guest -bios default -nographic -append console=hvc0
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.jnvHnbSJKT/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.30Kl16f7mY/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.ojW4EsFqOX/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.iKrvig4P7H/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.LGrpnHKQXO/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/initrd -serial mon:pipe:/tmp/tmp.0RO7a4EUiB/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-defconfig/initrd -serial mon:pipe:/tmp/tmp.Ltd1s19HqT/guest -bios default -nographic
> 
> rv32 defconfig seemed like the simplest, but there's a bunch of rv64 
> configs that fail too (though not defconfig, and the earlycon configs 
> don't hang).
> 
> I'm going to go look at that other stuff I wanted to, but I'll try and 
> find some time this weekend if nobody else can figure out what's up.
> 
> 
> >
> > Heiko
> >
> >
> >> I've put my somewhat messy merged test branch at 
> >> kernel.org/palmer/riscv-d1-merge .  Happy to hear if you have any 
> >> insights, otherwise I'l give it another shot (possibly after looking at 
> >> some other patches, there's quite a bit of a queue for this late).
> >> 
> >> >
> >> >
> >> > Heiko
> >> >
> >> >
> >> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
> >> > [1] https://lore.kernel.org/all/20220307205310.1905628-8-heiko@sntech.de/
> >> >
> >> >
> >> >> > > changes in v6:
> >> >> > > - rebase onto 5.17-rc1
> >> >> > > - handle sbi null-ptr differently
> >> >> > > - improve commit messages
> >> >> > > - use riscv,mmu as property name
> >> >> > >
> >> >> > > changes in v5:
> >> >> > > - move to use alternatives for runtime-patching
> >> >> > > - add D1 variant
> >> >> > >
> >> >> > >
> >> >> > > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
> >> >> > >
> >> >> > >
> >> >> > > Heiko Stuebner (12):
> >> >> > >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
> >> >> > >   riscv: integrate alternatives better into the main architecture
> >> >> > >   riscv: allow different stages with alternatives
> >> >> > >   riscv: implement module alternatives
> >> >> > >   riscv: implement ALTERNATIVE_2 macro
> >> >> > >   riscv: extend concatenated alternatives-lines to the same length
> >> >> > >   riscv: prevent compressed instructions in alternatives
> >> >> > >   riscv: move boot alternatives to after fill_hwcap
> >> >> > >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> >> >> > >   riscv: add cpufeature handling via alternatives
> >> >> > >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> >> >> > >   riscv: add memory-type errata for T-Head
> >> >> > >
> >> >> > > Wei Fu (1):
> >> >> > >   riscv: add RISC-V Svpbmt extension support
> >> >> > >
> >> >> > >  arch/riscv/Kconfig.erratas                  |  29 +++--
> >> >> > >  arch/riscv/Kconfig.socs                     |   1 -
> >> >> > >  arch/riscv/Makefile                         |   2 +-
> >> >> > >  arch/riscv/errata/Makefile                  |   2 +-
> >> >> > >  arch/riscv/errata/sifive/errata.c           |  17 ++-
> >> >> > >  arch/riscv/errata/thead/Makefile            |   1 +
> >> >> > >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
> >> >> > >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
> >> >> > >  arch/riscv/include/asm/alternative.h        |  16 ++-
> >> >> > >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
> >> >> > >  arch/riscv/include/asm/fixmap.h             |   2 -
> >> >> > >  arch/riscv/include/asm/hwcap.h              |   1 +
> >> >> > >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
> >> >> > >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
> >> >> > >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
> >> >> > >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
> >> >> > >  arch/riscv/include/asm/vendorid_list.h      |   1 +
> >> >> > >  arch/riscv/kernel/Makefile                  |   1 +
> >> >> > >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
> >> >> > >  arch/riscv/kernel/cpu.c                     |   1 +
> >> >> > >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
> >> >> > >  arch/riscv/kernel/module.c                  |  29 +++++
> >> >> > >  arch/riscv/kernel/sbi.c                     |  10 +-
> >> >> > >  arch/riscv/kernel/setup.c                   |   2 +
> >> >> > >  arch/riscv/kernel/smpboot.c                 |   4 -
> >> >> > >  arch/riscv/kernel/traps.c                   |   2 +-
> >> >> > >  arch/riscv/mm/init.c                        |   1 +
> >> >> > >  27 files changed, 546 insertions(+), 114 deletions(-)
> >> >> > >  create mode 100644 arch/riscv/errata/thead/Makefile
> >> >> > >  create mode 100644 arch/riscv/errata/thead/errata.c
> >> >> > >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
> >> >> > 
> >> >> 
> >> >> 
> >> 
> 

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Heiko Stübner]

Am Freitag, 18. März 2022, 22:50:05 CET schrieb Palmer Dabbelt:
> On Fri, 18 Mar 2022 09:22:29 PDT (-0700), heiko@sntech.de wrote:
> > Hi Palmer,
> >
> > Am Freitag, 18. März 2022, 04:40:23 CET schrieb Palmer Dabbelt:
> >> On Wed, 09 Mar 2022 14:06:55 PST (-0800), heiko@sntech.de wrote:
> >> > Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
> >> >> Hi Palmer,
> >> >> 
> >> >> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
> >> >> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
> >> >> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> >> >> > > for things like non-cacheable pages or I/O memory pages.
> >> >> > >
> >> >> > >
> >> >> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> >> >> > > types) using the alternatives framework.
> >> >> > >
> >> >> > > This includes a number of changes to the alternatives mechanism itself.
> >> >> > > The biggest one being the move to a more central location, as I expect
> >> >> > > in the future, nearly every chip needing some sort of patching, be it
> >> >> > > either for erratas or for optional features (svpbmt or others).
> >> >> > >
> >> >> > > Detection of the svpbmt functionality is done via Atish's isa extension
> >> >> > > handling series [0] and thus does not need any dt-parsing of its own
> >> >> > > anymore.
> >> >> > >
> >> >> > > The series also introduces support for the memory types of the D1
> >> >> > > which are implemented differently to svpbmt. But when patching anyway
> >> >> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> >> >> > > location.
> >> >> > >
> >> >> > > The only slightly bigger difference is that the "normal" type is not 0
> >> >> > > as with svpbmt, so kernel patches for this PMA type need to be applied
> >> >> > > even before the MMU is brought up, so the series introduces a separate
> >> >> > > stage for that.
> >> >> > >
> >> >> > >
> >> >> > > In theory this series is 3 parts:
> >> >> > > - sbi cache-flush / null-ptr
> >> >> > 
> >> >> > That first patch looks like an acceptable candidate for fixes.  If 
> >> >> > there's a regression that manifests I'm happy to take it, but if it's 
> >> >> > only possible to manifest a crash with the new stuff then I'm OK just 
> >> >> > holding off until the merge window.
> >> >> 
> >> >> While right now only my poking around the early init via alternatives
> >> >> is affected, the problem exists for everyone.
> >> >> 
> >> >> I.e. I do consider flush_icache_all() to be generic enough that we
> >> >> should expect someone trying to call this in some early code-path
> >> >> as well.
> >> >> 
> >> >> But any call to flush_icache_all() before sbi_init() ran will cause the
> >> >> breakage that is fixed by patch1 .
> >> >> 
> >> >> 
> >> >> So it doesn't look like any _current_ code path has that issue, but
> >> >> it might be good to just pick patch1 for the next merge window
> >> >> individually?
> >> >> 
> >> >> 
> >> >> 
> >> >> > > - alternatives improvements
> >> >> > > - svpbmt+d1
> >> >> > >
> >> >> > > So expecially patches from the first 2 areas could be applied when
> >> >> > > deemed ready, I just thought to keep it together to show-case where
> >> >> > > the end-goal is and not requiring jumping between different series.
> >> >> > >
> >> >> > >
> >> >> > > I picked the recipient list from the previous versions, hopefully
> >> >> > > I didn't forget anybody.
> >> >> > >
> >> >> > > changes in v7:
> >> >> > > - fix typo in patch1 (Atish)
> >> >> > > - moved to Atish's isa-extension framework
> >> >> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
> >> >> > > - change T-Head errata Kconfig text (Atish)
> >> >> > 
> >> >> > I was just poking around v6, so I have some minor comments there.  None 
> >> >> > of those need to block merging this, but I am getting a bunch of build 
> >> >> > failures under allmodconfig
> >> >> > 
> >> >> >     $ make.riscv allmodconfig
> >> >> >     #
> >> >> >     # configuration written to .config
> >> >> >     #
> >> >> >     $ make.riscv mm/kasan/init.o
> >> >> >       SYNC    include/config/auto.conf.cmd
> >> >> >       CALL    scripts/atomic/check-atomics.sh
> >> >> >       CC      arch/riscv/kernel/asm-offsets.s
> >> >> >       CALL    scripts/checksyscalls.sh
> >> >> >       CC      mm/kasan/init.o
> >> >> >     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
> >> >> >     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
> >> >> >     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
> >> >> >     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
> >> >> >     make: *** [Makefile:1831: mm] Error 2
> >> >> > 
> >> >> > Unfortunately my build box just blew up so I haven't had time to confim 
> >> >> > this still exists on v7, but nothing's jumping out as a fix.  I've put 
> >> >> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
> >> >> > what's going on but I'm guessing one of the macros has gone off the 
> >> >> > rails.  I'm going to look at something else (as this one at least 
> >> >> > depends on Atish's patches), but LMK if you've got the time to look into 
> >> >> > this or if I should.
> >> >> 
> >> >> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
> >> >> series and some more series I saw on the list), so getting that into a
> >> >> mergeable position would be really great :-)
> >> >> 
> >> >> "attempt to move .org backwards" seems to be the telltale sign of the
> >> >> alternatives blocks not matching up in size. While I definitly didn't see
> >> >> anything like this in my tests on qemu + d1, I'll try to investigate where
> >> >> that comes from.
> >> >
> >> > Hmm, looking at your branch [0] it seems that you're missing
> >> > patch7 that introduces the no-compressed-instruction thingy
> >> > for alternatives.
> >> >
> >> > And missing that patch will of course cause the size issue.
> >> >
> >> > The patch has made its way to the actual mailing lists [1], so I guess
> >> > it "just" somehow didn't reach your inbox due to some mail hickup?
> >> 
> >> Sorry about that, I'm not sure what happened.
> >
> > no worries :-) . And I also have no clue where the hickup happened
> > but am thankful that there is no general problem with mails.
> >
> >
> >> Unfortunately I'm now getting some even trickier failures: a handful of 
> >> configurations are failing very early in boot.  There doesn't seem to be 
> >> much pattern to the configs that fail, but at least rv32 defconfig (on 
> >> QEMU's virt board) is doing so.  I've tried poking around a bit and 
> >> can't figure out what's going on.  I'll try and look again tomorrow 
> >> morning.
> 
> (I guess morning means 2pm these days...)
> 
> > Hmm, really strange especially as the whole thing is somewhat
> > limited to 64bit anyway.
> >
> > I guess it would be interesting if it's in the alternative-basics
> > part of the svpbmt implementation.
> 
> Oddly enough it seems to be hanging as soon as I call into any of the 
> m*id SBI routines, but I'm not entierly sure what's up and I've been 
> bouncing between things so I might just be crazy.

You're defintily not crazy here :-) .

I.e. I didn't notice your reply from friday until now and so did the same
stepping through the code myself as well, after finally getting a rv32
build working.

Similarly I ended up at sbi_get_mvendorid() being the first failing function.

_But_ ... sbi isn't at fault here. What is causing the issue is the writes
to the static global variables. And I guess that will also be the issue
you saw on the other platforms.

The early-alternatives-mechanism runs before the kernel relocation,
so likely triggers some memory protection, which I didn't think of.

I'll just rework the code to not use static variables for storing both
the architecture-ids as well as the patch-func, which I think should
solve that issue for all platforms.


Heiko


> I did bisect the rv32-defconfig failure down to the last patch.
> 
> >
> > My short try on getting a (any) rv32 kernel boot in qemu wasn't sucessful
> > yet, so I'll need to poke that more next week.
> 
> There's a bunch of failing cases, not just rv32, but I can't figure out 
> what logic there is behind the failing cases.  They're all in my 
> riscv-system-ci repo, it's a mess but should at least build.  I see the 
> following hang:
> 
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-strict_rwx/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-strict_rwx/initrd -serial mon:pipe:/tmp/tmp.BM8zYJCKKZ/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/initrd -serial mon:pipe:/tmp/tmp.x7BL4Y1UsX/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.I9NZ3ow1GY/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.c9UPXaNcfR/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.AkLFnd3IDt/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.TbUWlXHDtO/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.E4h3Gw5Ecv/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab/initrd -serial mon:pipe:/tmp/tmp.anq8X90A1C/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.4MK3Xys4YL/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-vmap_stack/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-vmap_stack/initrd -serial mon:pipe:/tmp/tmp.fC0b16uUpo/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.t8nlK1Cvkk/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.stV634slMi/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.D0M6BSjwo2/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.x9AoOydj6h/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.cYwEP0Xod2/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.EmYY46ZyFw/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.UGF8OoNOXr/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.E540ImVMDZ/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.Hg8iJhkm2R/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.4KQh2WmFWc/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M spike -m 1G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-spike/halt-legacy_sbi/kernel -initrd check/qemu-rv64gc-spike/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.Ore2LcgxNR/guest -bios default -nographic -append console=hvc0
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.jnvHnbSJKT/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.30Kl16f7mY/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.ojW4EsFqOX/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.iKrvig4P7H/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.LGrpnHKQXO/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/initrd -serial mon:pipe:/tmp/tmp.0RO7a4EUiB/guest -bios default -nographic
>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-defconfig/initrd -serial mon:pipe:/tmp/tmp.Ltd1s19HqT/guest -bios default -nographic
> 
> rv32 defconfig seemed like the simplest, but there's a bunch of rv64 
> configs that fail too (though not defconfig, and the earlycon configs 
> don't hang).
> 
> I'm going to go look at that other stuff I wanted to, but I'll try and 
> find some time this weekend if nobody else can figure out what's up.
> 
> 
> >
> > Heiko
> >
> >
> >> I've put my somewhat messy merged test branch at 
> >> kernel.org/palmer/riscv-d1-merge .  Happy to hear if you have any 
> >> insights, otherwise I'l give it another shot (possibly after looking at 
> >> some other patches, there's quite a bit of a queue for this late).
> >> 
> >> >
> >> >
> >> > Heiko
> >> >
> >> >
> >> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
> >> > [1] https://lore.kernel.org/all/20220307205310.1905628-8-heiko@sntech.de/
> >> >
> >> >
> >> >> > > changes in v6:
> >> >> > > - rebase onto 5.17-rc1
> >> >> > > - handle sbi null-ptr differently
> >> >> > > - improve commit messages
> >> >> > > - use riscv,mmu as property name
> >> >> > >
> >> >> > > changes in v5:
> >> >> > > - move to use alternatives for runtime-patching
> >> >> > > - add D1 variant
> >> >> > >
> >> >> > >
> >> >> > > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
> >> >> > >
> >> >> > >
> >> >> > > Heiko Stuebner (12):
> >> >> > >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
> >> >> > >   riscv: integrate alternatives better into the main architecture
> >> >> > >   riscv: allow different stages with alternatives
> >> >> > >   riscv: implement module alternatives
> >> >> > >   riscv: implement ALTERNATIVE_2 macro
> >> >> > >   riscv: extend concatenated alternatives-lines to the same length
> >> >> > >   riscv: prevent compressed instructions in alternatives
> >> >> > >   riscv: move boot alternatives to after fill_hwcap
> >> >> > >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> >> >> > >   riscv: add cpufeature handling via alternatives
> >> >> > >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> >> >> > >   riscv: add memory-type errata for T-Head
> >> >> > >
> >> >> > > Wei Fu (1):
> >> >> > >   riscv: add RISC-V Svpbmt extension support
> >> >> > >
> >> >> > >  arch/riscv/Kconfig.erratas                  |  29 +++--
> >> >> > >  arch/riscv/Kconfig.socs                     |   1 -
> >> >> > >  arch/riscv/Makefile                         |   2 +-
> >> >> > >  arch/riscv/errata/Makefile                  |   2 +-
> >> >> > >  arch/riscv/errata/sifive/errata.c           |  17 ++-
> >> >> > >  arch/riscv/errata/thead/Makefile            |   1 +
> >> >> > >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
> >> >> > >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
> >> >> > >  arch/riscv/include/asm/alternative.h        |  16 ++-
> >> >> > >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
> >> >> > >  arch/riscv/include/asm/fixmap.h             |   2 -
> >> >> > >  arch/riscv/include/asm/hwcap.h              |   1 +
> >> >> > >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
> >> >> > >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
> >> >> > >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
> >> >> > >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
> >> >> > >  arch/riscv/include/asm/vendorid_list.h      |   1 +
> >> >> > >  arch/riscv/kernel/Makefile                  |   1 +
> >> >> > >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
> >> >> > >  arch/riscv/kernel/cpu.c                     |   1 +
> >> >> > >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
> >> >> > >  arch/riscv/kernel/module.c                  |  29 +++++
> >> >> > >  arch/riscv/kernel/sbi.c                     |  10 +-
> >> >> > >  arch/riscv/kernel/setup.c                   |   2 +
> >> >> > >  arch/riscv/kernel/smpboot.c                 |   4 -
> >> >> > >  arch/riscv/kernel/traps.c                   |   2 +-
> >> >> > >  arch/riscv/mm/init.c                        |   1 +
> >> >> > >  27 files changed, 546 insertions(+), 114 deletions(-)
> >> >> > >  create mode 100644 arch/riscv/errata/thead/Makefile
> >> >> > >  create mode 100644 arch/riscv/errata/thead/errata.c
> >> >> > >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
> >> >> > 
> >> >> 
> >> >> 
> >> 
> 





_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Palmer Dabbelt]

On Tue, 22 Mar 2022 09:09:04 PDT (-0700), heiko@sntech.de wrote:
> Am Freitag, 18. März 2022, 22:50:05 CET schrieb Palmer Dabbelt:
>> On Fri, 18 Mar 2022 09:22:29 PDT (-0700), heiko@sntech.de wrote:
>> > Hi Palmer,
>> >
>> > Am Freitag, 18. März 2022, 04:40:23 CET schrieb Palmer Dabbelt:
>> >> On Wed, 09 Mar 2022 14:06:55 PST (-0800), heiko@sntech.de wrote:
>> >> > Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
>> >> >> Hi Palmer,
>> >> >> 
>> >> >> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
>> >> >> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
>> >> >> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
>> >> >> > > for things like non-cacheable pages or I/O memory pages.
>> >> >> > >
>> >> >> > >
>> >> >> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
>> >> >> > > types) using the alternatives framework.
>> >> >> > >
>> >> >> > > This includes a number of changes to the alternatives mechanism itself.
>> >> >> > > The biggest one being the move to a more central location, as I expect
>> >> >> > > in the future, nearly every chip needing some sort of patching, be it
>> >> >> > > either for erratas or for optional features (svpbmt or others).
>> >> >> > >
>> >> >> > > Detection of the svpbmt functionality is done via Atish's isa extension
>> >> >> > > handling series [0] and thus does not need any dt-parsing of its own
>> >> >> > > anymore.
>> >> >> > >
>> >> >> > > The series also introduces support for the memory types of the D1
>> >> >> > > which are implemented differently to svpbmt. But when patching anyway
>> >> >> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
>> >> >> > > location.
>> >> >> > >
>> >> >> > > The only slightly bigger difference is that the "normal" type is not 0
>> >> >> > > as with svpbmt, so kernel patches for this PMA type need to be applied
>> >> >> > > even before the MMU is brought up, so the series introduces a separate
>> >> >> > > stage for that.
>> >> >> > >
>> >> >> > >
>> >> >> > > In theory this series is 3 parts:
>> >> >> > > - sbi cache-flush / null-ptr
>> >> >> > 
>> >> >> > That first patch looks like an acceptable candidate for fixes.  If 
>> >> >> > there's a regression that manifests I'm happy to take it, but if it's 
>> >> >> > only possible to manifest a crash with the new stuff then I'm OK just 
>> >> >> > holding off until the merge window.
>> >> >> 
>> >> >> While right now only my poking around the early init via alternatives
>> >> >> is affected, the problem exists for everyone.
>> >> >> 
>> >> >> I.e. I do consider flush_icache_all() to be generic enough that we
>> >> >> should expect someone trying to call this in some early code-path
>> >> >> as well.
>> >> >> 
>> >> >> But any call to flush_icache_all() before sbi_init() ran will cause the
>> >> >> breakage that is fixed by patch1 .
>> >> >> 
>> >> >> 
>> >> >> So it doesn't look like any _current_ code path has that issue, but
>> >> >> it might be good to just pick patch1 for the next merge window
>> >> >> individually?
>> >> >> 
>> >> >> 
>> >> >> 
>> >> >> > > - alternatives improvements
>> >> >> > > - svpbmt+d1
>> >> >> > >
>> >> >> > > So expecially patches from the first 2 areas could be applied when
>> >> >> > > deemed ready, I just thought to keep it together to show-case where
>> >> >> > > the end-goal is and not requiring jumping between different series.
>> >> >> > >
>> >> >> > >
>> >> >> > > I picked the recipient list from the previous versions, hopefully
>> >> >> > > I didn't forget anybody.
>> >> >> > >
>> >> >> > > changes in v7:
>> >> >> > > - fix typo in patch1 (Atish)
>> >> >> > > - moved to Atish's isa-extension framework
>> >> >> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
>> >> >> > > - change T-Head errata Kconfig text (Atish)
>> >> >> > 
>> >> >> > I was just poking around v6, so I have some minor comments there.  None 
>> >> >> > of those need to block merging this, but I am getting a bunch of build 
>> >> >> > failures under allmodconfig
>> >> >> > 
>> >> >> >     $ make.riscv allmodconfig
>> >> >> >     #
>> >> >> >     # configuration written to .config
>> >> >> >     #
>> >> >> >     $ make.riscv mm/kasan/init.o
>> >> >> >       SYNC    include/config/auto.conf.cmd
>> >> >> >       CALL    scripts/atomic/check-atomics.sh
>> >> >> >       CC      arch/riscv/kernel/asm-offsets.s
>> >> >> >       CALL    scripts/checksyscalls.sh
>> >> >> >       CC      mm/kasan/init.o
>> >> >> >     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
>> >> >> >     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
>> >> >> >     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
>> >> >> >     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
>> >> >> >     make: *** [Makefile:1831: mm] Error 2
>> >> >> > 
>> >> >> > Unfortunately my build box just blew up so I haven't had time to confim 
>> >> >> > this still exists on v7, but nothing's jumping out as a fix.  I've put 
>> >> >> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
>> >> >> > what's going on but I'm guessing one of the macros has gone off the 
>> >> >> > rails.  I'm going to look at something else (as this one at least 
>> >> >> > depends on Atish's patches), but LMK if you've got the time to look into 
>> >> >> > this or if I should.
>> >> >> 
>> >> >> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
>> >> >> series and some more series I saw on the list), so getting that into a
>> >> >> mergeable position would be really great :-)
>> >> >> 
>> >> >> "attempt to move .org backwards" seems to be the telltale sign of the
>> >> >> alternatives blocks not matching up in size. While I definitly didn't see
>> >> >> anything like this in my tests on qemu + d1, I'll try to investigate where
>> >> >> that comes from.
>> >> >
>> >> > Hmm, looking at your branch [0] it seems that you're missing
>> >> > patch7 that introduces the no-compressed-instruction thingy
>> >> > for alternatives.
>> >> >
>> >> > And missing that patch will of course cause the size issue.
>> >> >
>> >> > The patch has made its way to the actual mailing lists [1], so I guess
>> >> > it "just" somehow didn't reach your inbox due to some mail hickup?
>> >> 
>> >> Sorry about that, I'm not sure what happened.
>> >
>> > no worries :-) . And I also have no clue where the hickup happened
>> > but am thankful that there is no general problem with mails.
>> >
>> >
>> >> Unfortunately I'm now getting some even trickier failures: a handful of 
>> >> configurations are failing very early in boot.  There doesn't seem to be 
>> >> much pattern to the configs that fail, but at least rv32 defconfig (on 
>> >> QEMU's virt board) is doing so.  I've tried poking around a bit and 
>> >> can't figure out what's going on.  I'll try and look again tomorrow 
>> >> morning.
>> 
>> (I guess morning means 2pm these days...)
>> 
>> > Hmm, really strange especially as the whole thing is somewhat
>> > limited to 64bit anyway.
>> >
>> > I guess it would be interesting if it's in the alternative-basics
>> > part of the svpbmt implementation.
>> 
>> Oddly enough it seems to be hanging as soon as I call into any of the 
>> m*id SBI routines, but I'm not entierly sure what's up and I've been 
>> bouncing between things so I might just be crazy.
>
> You're defintily not crazy here :-) .
>
> I.e. I didn't notice your reply from friday until now and so did the same
> stepping through the code myself as well, after finally getting a rv32
> build working.
>
> Similarly I ended up at sbi_get_mvendorid() being the first failing function.
>
> _But_ ... sbi isn't at fault here. What is causing the issue is the writes
> to the static global variables. And I guess that will also be the issue
> you saw on the other platforms.
>
> The early-alternatives-mechanism runs before the kernel relocation,
> so likely triggers some memory protection, which I didn't think of.
>
> I'll just rework the code to not use static variables for storing both
> the architecture-ids as well as the patch-func, which I think should
> solve that issue for all platforms.

Awesome, thanks for looking at this.

> Heiko
>
>
>> I did bisect the rv32-defconfig failure down to the last patch.
>> 
>> >
>> > My short try on getting a (any) rv32 kernel boot in qemu wasn't sucessful
>> > yet, so I'll need to poke that more next week.
>> 
>> There's a bunch of failing cases, not just rv32, but I can't figure out 
>> what logic there is behind the failing cases.  They're all in my 
>> riscv-system-ci repo, it's a mess but should at least build.  I see the 
>> following hang:
>> 
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-strict_rwx/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-strict_rwx/initrd -serial mon:pipe:/tmp/tmp.BM8zYJCKKZ/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/initrd -serial mon:pipe:/tmp/tmp.x7BL4Y1UsX/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.I9NZ3ow1GY/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.c9UPXaNcfR/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.AkLFnd3IDt/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.TbUWlXHDtO/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.E4h3Gw5Ecv/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab/initrd -serial mon:pipe:/tmp/tmp.anq8X90A1C/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.4MK3Xys4YL/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-vmap_stack/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-vmap_stack/initrd -serial mon:pipe:/tmp/tmp.fC0b16uUpo/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.t8nlK1Cvkk/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.stV634slMi/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.D0M6BSjwo2/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.x9AoOydj6h/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.cYwEP0Xod2/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.EmYY46ZyFw/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.UGF8OoNOXr/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.E540ImVMDZ/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.Hg8iJhkm2R/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.4KQh2WmFWc/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M spike -m 1G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-spike/halt-legacy_sbi/kernel -initrd check/qemu-rv64gc-spike/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.Ore2LcgxNR/guest -bios default -nographic -append console=hvc0
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.jnvHnbSJKT/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.30Kl16f7mY/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.ojW4EsFqOX/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.iKrvig4P7H/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.LGrpnHKQXO/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/initrd -serial mon:pipe:/tmp/tmp.0RO7a4EUiB/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-defconfig/initrd -serial mon:pipe:/tmp/tmp.Ltd1s19HqT/guest -bios default -nographic
>> 
>> rv32 defconfig seemed like the simplest, but there's a bunch of rv64 
>> configs that fail too (though not defconfig, and the earlycon configs 
>> don't hang).
>> 
>> I'm going to go look at that other stuff I wanted to, but I'll try and 
>> find some time this weekend if nobody else can figure out what's up.
>> 
>> 
>> >
>> > Heiko
>> >
>> >
>> >> I've put my somewhat messy merged test branch at 
>> >> kernel.org/palmer/riscv-d1-merge .  Happy to hear if you have any 
>> >> insights, otherwise I'l give it another shot (possibly after looking at 
>> >> some other patches, there's quite a bit of a queue for this late).
>> >> 
>> >> >
>> >> >
>> >> > Heiko
>> >> >
>> >> >
>> >> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
>> >> > [1] https://lore.kernel.org/all/20220307205310.1905628-8-heiko@sntech.de/
>> >> >
>> >> >
>> >> >> > > changes in v6:
>> >> >> > > - rebase onto 5.17-rc1
>> >> >> > > - handle sbi null-ptr differently
>> >> >> > > - improve commit messages
>> >> >> > > - use riscv,mmu as property name
>> >> >> > >
>> >> >> > > changes in v5:
>> >> >> > > - move to use alternatives for runtime-patching
>> >> >> > > - add D1 variant
>> >> >> > >
>> >> >> > >
>> >> >> > > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
>> >> >> > >
>> >> >> > >
>> >> >> > > Heiko Stuebner (12):
>> >> >> > >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
>> >> >> > >   riscv: integrate alternatives better into the main architecture
>> >> >> > >   riscv: allow different stages with alternatives
>> >> >> > >   riscv: implement module alternatives
>> >> >> > >   riscv: implement ALTERNATIVE_2 macro
>> >> >> > >   riscv: extend concatenated alternatives-lines to the same length
>> >> >> > >   riscv: prevent compressed instructions in alternatives
>> >> >> > >   riscv: move boot alternatives to after fill_hwcap
>> >> >> > >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
>> >> >> > >   riscv: add cpufeature handling via alternatives
>> >> >> > >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
>> >> >> > >   riscv: add memory-type errata for T-Head
>> >> >> > >
>> >> >> > > Wei Fu (1):
>> >> >> > >   riscv: add RISC-V Svpbmt extension support
>> >> >> > >
>> >> >> > >  arch/riscv/Kconfig.erratas                  |  29 +++--
>> >> >> > >  arch/riscv/Kconfig.socs                     |   1 -
>> >> >> > >  arch/riscv/Makefile                         |   2 +-
>> >> >> > >  arch/riscv/errata/Makefile                  |   2 +-
>> >> >> > >  arch/riscv/errata/sifive/errata.c           |  17 ++-
>> >> >> > >  arch/riscv/errata/thead/Makefile            |   1 +
>> >> >> > >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
>> >> >> > >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
>> >> >> > >  arch/riscv/include/asm/alternative.h        |  16 ++-
>> >> >> > >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
>> >> >> > >  arch/riscv/include/asm/fixmap.h             |   2 -
>> >> >> > >  arch/riscv/include/asm/hwcap.h              |   1 +
>> >> >> > >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
>> >> >> > >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
>> >> >> > >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
>> >> >> > >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
>> >> >> > >  arch/riscv/include/asm/vendorid_list.h      |   1 +
>> >> >> > >  arch/riscv/kernel/Makefile                  |   1 +
>> >> >> > >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
>> >> >> > >  arch/riscv/kernel/cpu.c                     |   1 +
>> >> >> > >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
>> >> >> > >  arch/riscv/kernel/module.c                  |  29 +++++
>> >> >> > >  arch/riscv/kernel/sbi.c                     |  10 +-
>> >> >> > >  arch/riscv/kernel/setup.c                   |   2 +
>> >> >> > >  arch/riscv/kernel/smpboot.c                 |   4 -
>> >> >> > >  arch/riscv/kernel/traps.c                   |   2 +-
>> >> >> > >  arch/riscv/mm/init.c                        |   1 +
>> >> >> > >  27 files changed, 546 insertions(+), 114 deletions(-)
>> >> >> > >  create mode 100644 arch/riscv/errata/thead/Makefile
>> >> >> > >  create mode 100644 arch/riscv/errata/thead/errata.c
>> >> >> > >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
>> >> >> > 
>> >> >> 
>> >> >> 
>> >> 
>> 

Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

[Palmer Dabbelt]

On Tue, 22 Mar 2022 09:09:04 PDT (-0700), heiko@sntech.de wrote:
> Am Freitag, 18. März 2022, 22:50:05 CET schrieb Palmer Dabbelt:
>> On Fri, 18 Mar 2022 09:22:29 PDT (-0700), heiko@sntech.de wrote:
>> > Hi Palmer,
>> >
>> > Am Freitag, 18. März 2022, 04:40:23 CET schrieb Palmer Dabbelt:
>> >> On Wed, 09 Mar 2022 14:06:55 PST (-0800), heiko@sntech.de wrote:
>> >> > Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
>> >> >> Hi Palmer,
>> >> >> 
>> >> >> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
>> >> >> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), heiko@sntech.de wrote:
>> >> >> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
>> >> >> > > for things like non-cacheable pages or I/O memory pages.
>> >> >> > >
>> >> >> > >
>> >> >> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
>> >> >> > > types) using the alternatives framework.
>> >> >> > >
>> >> >> > > This includes a number of changes to the alternatives mechanism itself.
>> >> >> > > The biggest one being the move to a more central location, as I expect
>> >> >> > > in the future, nearly every chip needing some sort of patching, be it
>> >> >> > > either for erratas or for optional features (svpbmt or others).
>> >> >> > >
>> >> >> > > Detection of the svpbmt functionality is done via Atish's isa extension
>> >> >> > > handling series [0] and thus does not need any dt-parsing of its own
>> >> >> > > anymore.
>> >> >> > >
>> >> >> > > The series also introduces support for the memory types of the D1
>> >> >> > > which are implemented differently to svpbmt. But when patching anyway
>> >> >> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
>> >> >> > > location.
>> >> >> > >
>> >> >> > > The only slightly bigger difference is that the "normal" type is not 0
>> >> >> > > as with svpbmt, so kernel patches for this PMA type need to be applied
>> >> >> > > even before the MMU is brought up, so the series introduces a separate
>> >> >> > > stage for that.
>> >> >> > >
>> >> >> > >
>> >> >> > > In theory this series is 3 parts:
>> >> >> > > - sbi cache-flush / null-ptr
>> >> >> > 
>> >> >> > That first patch looks like an acceptable candidate for fixes.  If 
>> >> >> > there's a regression that manifests I'm happy to take it, but if it's 
>> >> >> > only possible to manifest a crash with the new stuff then I'm OK just 
>> >> >> > holding off until the merge window.
>> >> >> 
>> >> >> While right now only my poking around the early init via alternatives
>> >> >> is affected, the problem exists for everyone.
>> >> >> 
>> >> >> I.e. I do consider flush_icache_all() to be generic enough that we
>> >> >> should expect someone trying to call this in some early code-path
>> >> >> as well.
>> >> >> 
>> >> >> But any call to flush_icache_all() before sbi_init() ran will cause the
>> >> >> breakage that is fixed by patch1 .
>> >> >> 
>> >> >> 
>> >> >> So it doesn't look like any _current_ code path has that issue, but
>> >> >> it might be good to just pick patch1 for the next merge window
>> >> >> individually?
>> >> >> 
>> >> >> 
>> >> >> 
>> >> >> > > - alternatives improvements
>> >> >> > > - svpbmt+d1
>> >> >> > >
>> >> >> > > So expecially patches from the first 2 areas could be applied when
>> >> >> > > deemed ready, I just thought to keep it together to show-case where
>> >> >> > > the end-goal is and not requiring jumping between different series.
>> >> >> > >
>> >> >> > >
>> >> >> > > I picked the recipient list from the previous versions, hopefully
>> >> >> > > I didn't forget anybody.
>> >> >> > >
>> >> >> > > changes in v7:
>> >> >> > > - fix typo in patch1 (Atish)
>> >> >> > > - moved to Atish's isa-extension framework
>> >> >> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
>> >> >> > > - change T-Head errata Kconfig text (Atish)
>> >> >> > 
>> >> >> > I was just poking around v6, so I have some minor comments there.  None 
>> >> >> > of those need to block merging this, but I am getting a bunch of build 
>> >> >> > failures under allmodconfig
>> >> >> > 
>> >> >> >     $ make.riscv allmodconfig
>> >> >> >     #
>> >> >> >     # configuration written to .config
>> >> >> >     #
>> >> >> >     $ make.riscv mm/kasan/init.o
>> >> >> >       SYNC    include/config/auto.conf.cmd
>> >> >> >       CALL    scripts/atomic/check-atomics.sh
>> >> >> >       CC      arch/riscv/kernel/asm-offsets.s
>> >> >> >       CALL    scripts/checksyscalls.sh
>> >> >> >       CC      mm/kasan/init.o
>> >> >> >     ./arch/riscv/include/asm/pgtable.h: Assembler messages:
>> >> >> >     ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
>> >> >> >     make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
>> >> >> >     make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
>> >> >> >     make: *** [Makefile:1831: mm] Error 2
>> >> >> > 
>> >> >> > Unfortunately my build box just blew up so I haven't had time to confim 
>> >> >> > this still exists on v7, but nothing's jumping out as a fix.  I've put 
>> >> >> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly 
>> >> >> > what's going on but I'm guessing one of the macros has gone off the 
>> >> >> > rails.  I'm going to look at something else (as this one at least 
>> >> >> > depends on Atish's patches), but LMK if you've got the time to look into 
>> >> >> > this or if I should.
>> >> >> 
>> >> >> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
>> >> >> series and some more series I saw on the list), so getting that into a
>> >> >> mergeable position would be really great :-)
>> >> >> 
>> >> >> "attempt to move .org backwards" seems to be the telltale sign of the
>> >> >> alternatives blocks not matching up in size. While I definitly didn't see
>> >> >> anything like this in my tests on qemu + d1, I'll try to investigate where
>> >> >> that comes from.
>> >> >
>> >> > Hmm, looking at your branch [0] it seems that you're missing
>> >> > patch7 that introduces the no-compressed-instruction thingy
>> >> > for alternatives.
>> >> >
>> >> > And missing that patch will of course cause the size issue.
>> >> >
>> >> > The patch has made its way to the actual mailing lists [1], so I guess
>> >> > it "just" somehow didn't reach your inbox due to some mail hickup?
>> >> 
>> >> Sorry about that, I'm not sure what happened.
>> >
>> > no worries :-) . And I also have no clue where the hickup happened
>> > but am thankful that there is no general problem with mails.
>> >
>> >
>> >> Unfortunately I'm now getting some even trickier failures: a handful of 
>> >> configurations are failing very early in boot.  There doesn't seem to be 
>> >> much pattern to the configs that fail, but at least rv32 defconfig (on 
>> >> QEMU's virt board) is doing so.  I've tried poking around a bit and 
>> >> can't figure out what's going on.  I'll try and look again tomorrow 
>> >> morning.
>> 
>> (I guess morning means 2pm these days...)
>> 
>> > Hmm, really strange especially as the whole thing is somewhat
>> > limited to 64bit anyway.
>> >
>> > I guess it would be interesting if it's in the alternative-basics
>> > part of the svpbmt implementation.
>> 
>> Oddly enough it seems to be hanging as soon as I call into any of the 
>> m*id SBI routines, but I'm not entierly sure what's up and I've been 
>> bouncing between things so I might just be crazy.
>
> You're defintily not crazy here :-) .
>
> I.e. I didn't notice your reply from friday until now and so did the same
> stepping through the code myself as well, after finally getting a rv32
> build working.
>
> Similarly I ended up at sbi_get_mvendorid() being the first failing function.
>
> _But_ ... sbi isn't at fault here. What is causing the issue is the writes
> to the static global variables. And I guess that will also be the issue
> you saw on the other platforms.
>
> The early-alternatives-mechanism runs before the kernel relocation,
> so likely triggers some memory protection, which I didn't think of.
>
> I'll just rework the code to not use static variables for storing both
> the architecture-ids as well as the patch-func, which I think should
> solve that issue for all platforms.

Awesome, thanks for looking at this.

> Heiko
>
>
>> I did bisect the rv32-defconfig failure down to the last patch.
>> 
>> >
>> > My short try on getting a (any) rv32 kernel boot in qemu wasn't sucessful
>> > yet, so I'll need to poke that more next week.
>> 
>> There's a bunch of failing cases, not just rv32, but I can't figure out 
>> what logic there is behind the failing cases.  They're all in my 
>> riscv-system-ci repo, it's a mess but should at least build.  I see the 
>> following hang:
>> 
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-strict_rwx/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-strict_rwx/initrd -serial mon:pipe:/tmp/tmp.BM8zYJCKKZ/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/initrd -serial mon:pipe:/tmp/tmp.x7BL4Y1UsX/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.I9NZ3ow1GY/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.c9UPXaNcfR/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.AkLFnd3IDt/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.TbUWlXHDtO/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.E4h3Gw5Ecv/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab/initrd -serial mon:pipe:/tmp/tmp.anq8X90A1C/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.4MK3Xys4YL/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-vmap_stack/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-vmap_stack/initrd -serial mon:pipe:/tmp/tmp.fC0b16uUpo/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.t8nlK1Cvkk/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.stV634slMi/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.D0M6BSjwo2/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.x9AoOydj6h/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.cYwEP0Xod2/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.EmYY46ZyFw/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.UGF8OoNOXr/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.E540ImVMDZ/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.Hg8iJhkm2R/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.4KQh2WmFWc/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M spike -m 1G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-spike/halt-legacy_sbi/kernel -initrd check/qemu-rv64gc-spike/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.Ore2LcgxNR/guest -bios default -nographic -append console=hvc0
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.jnvHnbSJKT/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.30Kl16f7mY/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.ojW4EsFqOX/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.iKrvig4P7H/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.LGrpnHKQXO/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/initrd -serial mon:pipe:/tmp/tmp.0RO7a4EUiB/guest -bios default -nographic
>>     qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-defconfig/initrd -serial mon:pipe:/tmp/tmp.Ltd1s19HqT/guest -bios default -nographic
>> 
>> rv32 defconfig seemed like the simplest, but there's a bunch of rv64 
>> configs that fail too (though not defconfig, and the earlycon configs 
>> don't hang).
>> 
>> I'm going to go look at that other stuff I wanted to, but I'll try and 
>> find some time this weekend if nobody else can figure out what's up.
>> 
>> 
>> >
>> > Heiko
>> >
>> >
>> >> I've put my somewhat messy merged test branch at 
>> >> kernel.org/palmer/riscv-d1-merge .  Happy to hear if you have any 
>> >> insights, otherwise I'l give it another shot (possibly after looking at 
>> >> some other patches, there's quite a bit of a queue for this late).
>> >> 
>> >> >
>> >> >
>> >> > Heiko
>> >> >
>> >> >
>> >> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
>> >> > [1] https://lore.kernel.org/all/20220307205310.1905628-8-heiko@sntech.de/
>> >> >
>> >> >
>> >> >> > > changes in v6:
>> >> >> > > - rebase onto 5.17-rc1
>> >> >> > > - handle sbi null-ptr differently
>> >> >> > > - improve commit messages
>> >> >> > > - use riscv,mmu as property name
>> >> >> > >
>> >> >> > > changes in v5:
>> >> >> > > - move to use alternatives for runtime-patching
>> >> >> > > - add D1 variant
>> >> >> > >
>> >> >> > >
>> >> >> > > [0] https://lore.kernel.org/r/20220222204811.2281949-2-atishp@rivosinc.com
>> >> >> > >
>> >> >> > >
>> >> >> > > Heiko Stuebner (12):
>> >> >> > >   riscv: prevent null-pointer dereference with sbi_remote_fence_i
>> >> >> > >   riscv: integrate alternatives better into the main architecture
>> >> >> > >   riscv: allow different stages with alternatives
>> >> >> > >   riscv: implement module alternatives
>> >> >> > >   riscv: implement ALTERNATIVE_2 macro
>> >> >> > >   riscv: extend concatenated alternatives-lines to the same length
>> >> >> > >   riscv: prevent compressed instructions in alternatives
>> >> >> > >   riscv: move boot alternatives to after fill_hwcap
>> >> >> > >   riscv: Fix accessing pfn bits in PTEs for non-32bit variants
>> >> >> > >   riscv: add cpufeature handling via alternatives
>> >> >> > >   riscv: remove FIXMAP_PAGE_IO and fall back to its default value
>> >> >> > >   riscv: add memory-type errata for T-Head
>> >> >> > >
>> >> >> > > Wei Fu (1):
>> >> >> > >   riscv: add RISC-V Svpbmt extension support
>> >> >> > >
>> >> >> > >  arch/riscv/Kconfig.erratas                  |  29 +++--
>> >> >> > >  arch/riscv/Kconfig.socs                     |   1 -
>> >> >> > >  arch/riscv/Makefile                         |   2 +-
>> >> >> > >  arch/riscv/errata/Makefile                  |   2 +-
>> >> >> > >  arch/riscv/errata/sifive/errata.c           |  17 ++-
>> >> >> > >  arch/riscv/errata/thead/Makefile            |   1 +
>> >> >> > >  arch/riscv/errata/thead/errata.c            |  85 +++++++++++++++
>> >> >> > >  arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
>> >> >> > >  arch/riscv/include/asm/alternative.h        |  16 ++-
>> >> >> > >  arch/riscv/include/asm/errata_list.h        |  52 +++++++++
>> >> >> > >  arch/riscv/include/asm/fixmap.h             |   2 -
>> >> >> > >  arch/riscv/include/asm/hwcap.h              |   1 +
>> >> >> > >  arch/riscv/include/asm/pgtable-32.h         |  17 +++
>> >> >> > >  arch/riscv/include/asm/pgtable-64.h         |  79 +++++++++++++-
>> >> >> > >  arch/riscv/include/asm/pgtable-bits.h       |  10 --
>> >> >> > >  arch/riscv/include/asm/pgtable.h            |  53 +++++++--
>> >> >> > >  arch/riscv/include/asm/vendorid_list.h      |   1 +
>> >> >> > >  arch/riscv/kernel/Makefile                  |   1 +
>> >> >> > >  arch/riscv/{errata => kernel}/alternative.c |  48 +++++++--
>> >> >> > >  arch/riscv/kernel/cpu.c                     |   1 +
>> >> >> > >  arch/riscv/kernel/cpufeature.c              |  80 +++++++++++++-
>> >> >> > >  arch/riscv/kernel/module.c                  |  29 +++++
>> >> >> > >  arch/riscv/kernel/sbi.c                     |  10 +-
>> >> >> > >  arch/riscv/kernel/setup.c                   |   2 +
>> >> >> > >  arch/riscv/kernel/smpboot.c                 |   4 -
>> >> >> > >  arch/riscv/kernel/traps.c                   |   2 +-
>> >> >> > >  arch/riscv/mm/init.c                        |   1 +
>> >> >> > >  27 files changed, 546 insertions(+), 114 deletions(-)
>> >> >> > >  create mode 100644 arch/riscv/errata/thead/Makefile
>> >> >> > >  create mode 100644 arch/riscv/errata/thead/errata.c
>> >> >> > >  rename arch/riscv/{errata => kernel}/alternative.c (59%)
>> >> >> > 
>> >> >> 
>> >> >> 
>> >> 
>> 

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv