From: Palmer Dabbelt <palmer@dabbelt.com> To: apatel@ventanamicro.com Cc: Paul Walmsley <paul.walmsley@sifive.com>, atishp@atishpatra.org, heiko@sntech.de, anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, mchitale@ventanamicro.com Subject: Re: [PATCH v2 1/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt Date: Thu, 22 Sep 2022 09:35:56 -0700 (PDT) [thread overview] Message-ID: <mhng-37586d5e-5576-448a-8d9c-4d277c252365@palmer-ri-x1c9> (raw) In-Reply-To: <CAK9=C2WkqVgg58sKyDEMWue_vL8Pz7bCfERuaW_4DGnYTpcSMw@mail.gmail.com> On Thu, 15 Sep 2022 19:24:55 PDT (-0700), apatel@ventanamicro.com wrote: > Hi Palmer, > > On Tue, Aug 30, 2022 at 10:17 AM Anup Patel <apatel@ventanamicro.com> wrote: >> >> Currently, all flavors of ioremap_xyz() function maps to the generic >> ioremap() which means any ioremap_xyz() call will always map the >> target memory as IO using _PAGE_IOREMAP page attributes. This breaks >> ioremap_cache() and ioremap_wc() on systems with Svpbmt because memory >> remapped using ioremap_cache() and ioremap_wc() will use _PAGE_IOREMAP >> page attributes. >> >> To address above (just like other architectures), we implement RISC-V >> specific ioremap_cache() and ioremap_wc() which maps memory using page >> attributes as defined by the Svpbmt specification. >> >> Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support") >> Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com> >> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> >> Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > This is a crucial RC fix. Can you please take this ? Sorry I missed this, I thought it was just part of the rest of this patch set. That said, I'm not actually sure this is a critical fix: sure it's a performance problem, and if some driver is expecting ioremap_cache() to go fast then possibly a pretty big one, but the only Svpmbt hardware that exists is the D1 and that was just supported this release so it's not a regression. Maybe that's a bit pedantic, but all this travel has kind of made things a mess and I'm trying to make sure nothing goes off the rails. Probably a pointless distinction as it'll just get backported anyway, but I'm going to hold off on this for now -- it generally looks OK, but I don't get back until this weekend and I'm super tired so I'm trying to avoid screwing anything up. > > Regards, > Anup > >> --- >> arch/riscv/include/asm/io.h | 10 ++++++++++ >> arch/riscv/include/asm/pgtable.h | 2 ++ >> 2 files changed, 12 insertions(+) >> >> diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h >> index 69605a474270..07ac63999575 100644 >> --- a/arch/riscv/include/asm/io.h >> +++ b/arch/riscv/include/asm/io.h >> @@ -133,6 +133,16 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) >> #define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count) >> #endif >> >> +#ifdef CONFIG_MMU >> +#define ioremap_wc(addr, size) \ >> + ioremap_prot((addr), (size), _PAGE_IOREMAP_WC) >> +#endif >> + >> #include <asm-generic/io.h> >> >> +#ifdef CONFIG_MMU >> +#define ioremap_cache(addr, size) \ >> + ioremap_prot((addr), (size), _PAGE_KERNEL) >> +#endif >> + >> #endif /* _ASM_RISCV_IO_H */ >> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h >> index 7ec936910a96..346b7c1a3eeb 100644 >> --- a/arch/riscv/include/asm/pgtable.h >> +++ b/arch/riscv/include/asm/pgtable.h >> @@ -182,6 +182,8 @@ extern struct pt_alloc_ops pt_ops __initdata; >> #define PAGE_TABLE __pgprot(_PAGE_TABLE) >> >> #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) >> +#define _PAGE_IOREMAP_WC ((_PAGE_KERNEL & ~_PAGE_MTMASK) | \ >> + _PAGE_NOCACHE) >> #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) >> >> extern pgd_t swapper_pg_dir[]; >> -- >> 2.34.1 >>
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@dabbelt.com> To: apatel@ventanamicro.com Cc: Paul Walmsley <paul.walmsley@sifive.com>, atishp@atishpatra.org, heiko@sntech.de, anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, mchitale@ventanamicro.com Subject: Re: [PATCH v2 1/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt Date: Thu, 22 Sep 2022 09:35:56 -0700 (PDT) [thread overview] Message-ID: <mhng-37586d5e-5576-448a-8d9c-4d277c252365@palmer-ri-x1c9> (raw) In-Reply-To: <CAK9=C2WkqVgg58sKyDEMWue_vL8Pz7bCfERuaW_4DGnYTpcSMw@mail.gmail.com> On Thu, 15 Sep 2022 19:24:55 PDT (-0700), apatel@ventanamicro.com wrote: > Hi Palmer, > > On Tue, Aug 30, 2022 at 10:17 AM Anup Patel <apatel@ventanamicro.com> wrote: >> >> Currently, all flavors of ioremap_xyz() function maps to the generic >> ioremap() which means any ioremap_xyz() call will always map the >> target memory as IO using _PAGE_IOREMAP page attributes. This breaks >> ioremap_cache() and ioremap_wc() on systems with Svpbmt because memory >> remapped using ioremap_cache() and ioremap_wc() will use _PAGE_IOREMAP >> page attributes. >> >> To address above (just like other architectures), we implement RISC-V >> specific ioremap_cache() and ioremap_wc() which maps memory using page >> attributes as defined by the Svpbmt specification. >> >> Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support") >> Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com> >> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> >> Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > This is a crucial RC fix. Can you please take this ? Sorry I missed this, I thought it was just part of the rest of this patch set. That said, I'm not actually sure this is a critical fix: sure it's a performance problem, and if some driver is expecting ioremap_cache() to go fast then possibly a pretty big one, but the only Svpmbt hardware that exists is the D1 and that was just supported this release so it's not a regression. Maybe that's a bit pedantic, but all this travel has kind of made things a mess and I'm trying to make sure nothing goes off the rails. Probably a pointless distinction as it'll just get backported anyway, but I'm going to hold off on this for now -- it generally looks OK, but I don't get back until this weekend and I'm super tired so I'm trying to avoid screwing anything up. > > Regards, > Anup > >> --- >> arch/riscv/include/asm/io.h | 10 ++++++++++ >> arch/riscv/include/asm/pgtable.h | 2 ++ >> 2 files changed, 12 insertions(+) >> >> diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h >> index 69605a474270..07ac63999575 100644 >> --- a/arch/riscv/include/asm/io.h >> +++ b/arch/riscv/include/asm/io.h >> @@ -133,6 +133,16 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) >> #define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count) >> #endif >> >> +#ifdef CONFIG_MMU >> +#define ioremap_wc(addr, size) \ >> + ioremap_prot((addr), (size), _PAGE_IOREMAP_WC) >> +#endif >> + >> #include <asm-generic/io.h> >> >> +#ifdef CONFIG_MMU >> +#define ioremap_cache(addr, size) \ >> + ioremap_prot((addr), (size), _PAGE_KERNEL) >> +#endif >> + >> #endif /* _ASM_RISCV_IO_H */ >> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h >> index 7ec936910a96..346b7c1a3eeb 100644 >> --- a/arch/riscv/include/asm/pgtable.h >> +++ b/arch/riscv/include/asm/pgtable.h >> @@ -182,6 +182,8 @@ extern struct pt_alloc_ops pt_ops __initdata; >> #define PAGE_TABLE __pgprot(_PAGE_TABLE) >> >> #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) >> +#define _PAGE_IOREMAP_WC ((_PAGE_KERNEL & ~_PAGE_MTMASK) | \ >> + _PAGE_NOCACHE) >> #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) >> >> extern pgd_t swapper_pg_dir[]; >> -- >> 2.34.1 >> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-09-22 16:36 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-30 4:46 [PATCH v2 0/4] Add PMEM support for RISC-V Anup Patel 2022-08-30 4:46 ` Anup Patel 2022-08-30 4:46 ` [PATCH v2 1/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt Anup Patel 2022-08-30 4:46 ` Anup Patel 2022-09-01 15:25 ` Heiko Stübner 2022-09-01 15:25 ` Heiko Stübner 2022-09-01 16:07 ` Conor.Dooley 2022-09-01 16:07 ` Conor.Dooley 2022-09-09 8:10 ` Anup Patel 2022-09-09 8:10 ` Anup Patel 2022-09-16 2:24 ` Anup Patel 2022-09-16 2:24 ` Anup Patel 2022-09-22 16:35 ` Palmer Dabbelt [this message] 2022-09-22 16:35 ` Palmer Dabbelt 2022-09-23 10:35 ` Arnd Bergmann 2022-09-23 10:35 ` Arnd Bergmann 2022-09-23 10:45 ` Palmer Dabbelt 2022-09-23 10:45 ` Palmer Dabbelt 2022-09-28 12:14 ` Christoph Hellwig 2022-09-28 12:14 ` Christoph Hellwig 2022-10-07 3:50 ` Palmer Dabbelt 2022-10-07 3:50 ` Palmer Dabbelt 2022-10-07 5:34 ` Anup Patel 2022-10-07 5:34 ` Anup Patel 2022-08-30 4:46 ` [PATCH v2 2/4] RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c Anup Patel 2022-08-30 4:46 ` Anup Patel 2022-09-01 15:29 ` Heiko Stübner 2022-09-01 15:29 ` Heiko Stübner 2022-09-01 15:49 ` Conor.Dooley 2022-09-01 15:49 ` Conor.Dooley 2022-08-30 4:46 ` [PATCH v2 3/4] RISC-V: Implement arch specific PMEM APIs Anup Patel 2022-08-30 4:46 ` Anup Patel 2022-09-01 15:38 ` Heiko Stübner 2022-09-01 15:38 ` Heiko Stübner 2022-09-03 16:03 ` Anup Patel 2022-09-03 16:03 ` Anup Patel 2022-08-30 4:46 ` [PATCH v2 4/4] RISC-V: Enable PMEM drivers Anup Patel 2022-08-30 4:46 ` Anup Patel 2022-09-01 16:11 ` Conor.Dooley 2022-09-01 16:11 ` Conor.Dooley
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