[PATCH 00/10] riscv: make riscv build happier

[PATCH 00/10] riscv: make riscv build happier

[Kefeng Wang]

When add RISCV arch to huawei build test, there are some build
issue, let's fix them to make riscv build happier :) 

Those patches is rebased on next-20200508.

Kefeng Wang (10):
  riscv: Fix unmet direct dependencies built based on SOC_VIRT
  riscv: stacktrace: Fix undefined reference to `walk_stackframe'
  riscv: Add pgprot_writecombine/device and PAGE_SHARED defination if
    NOMMU
  riscv: Fix print_vm_layout build error if NOMMU
  riscv: Disable ARCH_HAS_DEBUG_WX if NOMMU
  riscv: Disable ARCH_HAS_DEBUG_VIRTUAL if NOMMU
  riscv: Make SYS_SUPPORTS_HUGETLBFS depends on MMU
  riscv: pgtable: Fix __kernel_map_pages build error if NOMMU
  timer-riscv: Fix undefined riscv_time_val
  riscv: mmiowb: Fix implicit declaration of function 'smp_processor_id'

 arch/riscv/Kconfig                |  5 +++--
 arch/riscv/Kconfig.socs           | 17 +++++++++--------
 arch/riscv/include/asm/mmio.h     |  2 ++
 arch/riscv/include/asm/mmiowb.h   |  1 +
 arch/riscv/include/asm/pgtable.h  |  3 +++
 arch/riscv/kernel/stacktrace.c    |  2 +-
 arch/riscv/mm/init.c              |  2 +-
 drivers/clocksource/timer-riscv.c |  1 +
 8 files changed, 21 insertions(+), 12 deletions(-)

-- 
2.26.2

[PATCH 01/10] riscv: Fix unmet direct dependencies built based on SOC_VIRT

[Kefeng Wang]

Fix unmet direct dependencies Warning and fix Kconfig indent.

WARNING: unmet direct dependencies detected for POWER_RESET_SYSCON
  Depends on [n]: POWER_RESET [=n] && OF [=y] && HAS_IOMEM [=y]
  Selected by [y]:
  - SOC_VIRT [=y]

WARNING: unmet direct dependencies detected for POWER_RESET_SYSCON_POWEROFF
  Depends on [n]: POWER_RESET [=n] && OF [=y] && HAS_IOMEM [=y]
  Selected by [y]:
  - SOC_VIRT [=y]

WARNING: unmet direct dependencies detected for RTC_DRV_GOLDFISH
  Depends on [n]: RTC_CLASS [=n] && OF [=y] && HAS_IOMEM [=y] && (GOLDFISH [=y] || COMPILE_TEST [=n])
  Selected by [y]:
  - SOC_VIRT [=y]

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/Kconfig.socs | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 4b2303ca20b9..6c88148f1b9b 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -11,14 +11,15 @@ config SOC_SIFIVE
 	  This enables support for SiFive SoC platform hardware.
 
 config SOC_VIRT
-       bool "QEMU Virt Machine"
-       select POWER_RESET_SYSCON
-       select POWER_RESET_SYSCON_POWEROFF
-       select GOLDFISH
-       select RTC_DRV_GOLDFISH
-       select SIFIVE_PLIC
-       help
-         This enables support for QEMU Virt Machine.
+	bool "QEMU Virt Machine"
+	select POWER_RESET
+	select POWER_RESET_SYSCON
+	select POWER_RESET_SYSCON_POWEROFF
+	select GOLDFISH
+	select RTC_DRV_GOLDFISH if RTC_CLASS
+	select SIFIVE_PLIC
+	help
+	  This enables support for QEMU Virt Machine.
 
 config SOC_KENDRYTE
 	bool "Kendryte K210 SoC"
-- 
2.26.2

[PATCH 01/10] riscv: Fix unmet direct dependencies built based on SOC_VIRT

[Kefeng Wang]

Fix unmet direct dependencies Warning and fix Kconfig indent.

WARNING: unmet direct dependencies detected for POWER_RESET_SYSCON
  Depends on [n]: POWER_RESET [=n] && OF [=y] && HAS_IOMEM [=y]
  Selected by [y]:
  - SOC_VIRT [=y]

WARNING: unmet direct dependencies detected for POWER_RESET_SYSCON_POWEROFF
  Depends on [n]: POWER_RESET [=n] && OF [=y] && HAS_IOMEM [=y]
  Selected by [y]:
  - SOC_VIRT [=y]

WARNING: unmet direct dependencies detected for RTC_DRV_GOLDFISH
  Depends on [n]: RTC_CLASS [=n] && OF [=y] && HAS_IOMEM [=y] && (GOLDFISH [=y] || COMPILE_TEST [=n])
  Selected by [y]:
  - SOC_VIRT [=y]

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/Kconfig.socs | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 4b2303ca20b9..6c88148f1b9b 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -11,14 +11,15 @@ config SOC_SIFIVE
 	  This enables support for SiFive SoC platform hardware.
 
 config SOC_VIRT
-       bool "QEMU Virt Machine"
-       select POWER_RESET_SYSCON
-       select POWER_RESET_SYSCON_POWEROFF
-       select GOLDFISH
-       select RTC_DRV_GOLDFISH
-       select SIFIVE_PLIC
-       help
-         This enables support for QEMU Virt Machine.
+	bool "QEMU Virt Machine"
+	select POWER_RESET
+	select POWER_RESET_SYSCON
+	select POWER_RESET_SYSCON_POWEROFF
+	select GOLDFISH
+	select RTC_DRV_GOLDFISH if RTC_CLASS
+	select SIFIVE_PLIC
+	help
+	  This enables support for QEMU Virt Machine.
 
 config SOC_KENDRYTE
 	bool "Kendryte K210 SoC"
-- 
2.26.2

Re: [PATCH 01/10] riscv: Fix unmet direct dependencies built based on SOC_VIRT

[Palmer Dabbelt]

On Sun, 10 May 2020 19:19:52 PDT (-0700), wangkefeng.wang@huawei.com wrote:
> Fix unmet direct dependencies Warning and fix Kconfig indent.
>
> WARNING: unmet direct dependencies detected for POWER_RESET_SYSCON
>   Depends on [n]: POWER_RESET [=n] && OF [=y] && HAS_IOMEM [=y]
>   Selected by [y]:
>   - SOC_VIRT [=y]
>
> WARNING: unmet direct dependencies detected for POWER_RESET_SYSCON_POWEROFF
>   Depends on [n]: POWER_RESET [=n] && OF [=y] && HAS_IOMEM [=y]
>   Selected by [y]:
>   - SOC_VIRT [=y]
>
> WARNING: unmet direct dependencies detected for RTC_DRV_GOLDFISH
>   Depends on [n]: RTC_CLASS [=n] && OF [=y] && HAS_IOMEM [=y] && (GOLDFISH [=y] || COMPILE_TEST [=n])
>   Selected by [y]:
>   - SOC_VIRT [=y]
>
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>  arch/riscv/Kconfig.socs | 17 +++++++++--------
>  1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 4b2303ca20b9..6c88148f1b9b 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -11,14 +11,15 @@ config SOC_SIFIVE
>  	  This enables support for SiFive SoC platform hardware.
>
>  config SOC_VIRT
> -       bool "QEMU Virt Machine"
> -       select POWER_RESET_SYSCON
> -       select POWER_RESET_SYSCON_POWEROFF
> -       select GOLDFISH
> -       select RTC_DRV_GOLDFISH
> -       select SIFIVE_PLIC
> -       help
> -         This enables support for QEMU Virt Machine.
> +	bool "QEMU Virt Machine"
> +	select POWER_RESET
> +	select POWER_RESET_SYSCON
> +	select POWER_RESET_SYSCON_POWEROFF
> +	select GOLDFISH
> +	select RTC_DRV_GOLDFISH if RTC_CLASS
> +	select SIFIVE_PLIC
> +	help
> +	  This enables support for QEMU Virt Machine.
>
>  config SOC_KENDRYTE
>  	bool "Kendryte K210 SoC"

This is another area we need to clean up (maybe converting from select to
imply?), but given this fixes likely build errors I'm going to take it onto
fixes.

Thanks!

Re: [PATCH 01/10] riscv: Fix unmet direct dependencies built based on SOC_VIRT

[Palmer Dabbelt]

On Sun, 10 May 2020 19:19:52 PDT (-0700), wangkefeng.wang@huawei.com wrote:
> Fix unmet direct dependencies Warning and fix Kconfig indent.
>
> WARNING: unmet direct dependencies detected for POWER_RESET_SYSCON
>   Depends on [n]: POWER_RESET [=n] && OF [=y] && HAS_IOMEM [=y]
>   Selected by [y]:
>   - SOC_VIRT [=y]
>
> WARNING: unmet direct dependencies detected for POWER_RESET_SYSCON_POWEROFF
>   Depends on [n]: POWER_RESET [=n] && OF [=y] && HAS_IOMEM [=y]
>   Selected by [y]:
>   - SOC_VIRT [=y]
>
> WARNING: unmet direct dependencies detected for RTC_DRV_GOLDFISH
>   Depends on [n]: RTC_CLASS [=n] && OF [=y] && HAS_IOMEM [=y] && (GOLDFISH [=y] || COMPILE_TEST [=n])
>   Selected by [y]:
>   - SOC_VIRT [=y]
>
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>  arch/riscv/Kconfig.socs | 17 +++++++++--------
>  1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 4b2303ca20b9..6c88148f1b9b 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -11,14 +11,15 @@ config SOC_SIFIVE
>  	  This enables support for SiFive SoC platform hardware.
>
>  config SOC_VIRT
> -       bool "QEMU Virt Machine"
> -       select POWER_RESET_SYSCON
> -       select POWER_RESET_SYSCON_POWEROFF
> -       select GOLDFISH
> -       select RTC_DRV_GOLDFISH
> -       select SIFIVE_PLIC
> -       help
> -         This enables support for QEMU Virt Machine.
> +	bool "QEMU Virt Machine"
> +	select POWER_RESET
> +	select POWER_RESET_SYSCON
> +	select POWER_RESET_SYSCON_POWEROFF
> +	select GOLDFISH
> +	select RTC_DRV_GOLDFISH if RTC_CLASS
> +	select SIFIVE_PLIC
> +	help
> +	  This enables support for QEMU Virt Machine.
>
>  config SOC_KENDRYTE
>  	bool "Kendryte K210 SoC"

This is another area we need to clean up (maybe converting from select to
imply?), but given this fixes likely build errors I'm going to take it onto
fixes.

Thanks!

[PATCH 02/10] riscv: stacktrace: Fix undefined reference to `walk_stackframe'

Drop static declaration to fix following build error if FRAME_POINTER disabled,
  riscv64-linux-ld: arch/riscv/kernel/perf_callchain.o: in function `.L0':
  perf_callchain.c:(.text+0x2b8): undefined reference to `walk_stackframe'

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/kernel/stacktrace.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/stacktrace.c b/arch/riscv/kernel/stacktrace.c
index 38141a3c70f7..595342910c3f 100644
--- a/arch/riscv/kernel/stacktrace.c
+++ b/arch/riscv/kernel/stacktrace.c
@@ -65,7 +65,7 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
 
 #else /* !CONFIG_FRAME_POINTER */
 
-static void notrace walk_stackframe(struct task_struct *task,
+void notrace walk_stackframe(struct task_struct *task,
 	struct pt_regs *regs, bool (*fn)(unsigned long, void *), void *arg)
 {
 	unsigned long sp, pc;
-- 
2.26.2

[PATCH 02/10] riscv: stacktrace: Fix undefined reference to `walk_stackframe'

[Kefeng Wang]

Drop static declaration to fix following build error if FRAME_POINTER disabled,
  riscv64-linux-ld: arch/riscv/kernel/perf_callchain.o: in function `.L0':
  perf_callchain.c:(.text+0x2b8): undefined reference to `walk_stackframe'

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/kernel/stacktrace.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/stacktrace.c b/arch/riscv/kernel/stacktrace.c
index 38141a3c70f7..595342910c3f 100644
--- a/arch/riscv/kernel/stacktrace.c
+++ b/arch/riscv/kernel/stacktrace.c
@@ -65,7 +65,7 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
 
 #else /* !CONFIG_FRAME_POINTER */
 
-static void notrace walk_stackframe(struct task_struct *task,
+void notrace walk_stackframe(struct task_struct *task,
 	struct pt_regs *regs, bool (*fn)(unsigned long, void *), void *arg)
 {
 	unsigned long sp, pc;
-- 
2.26.2

[PATCH 03/10] riscv: Add pgprot_writecombine/device and PAGE_SHARED defination if NOMMU

[Kefeng Wang]

Some drivers use PAGE_SHARED, pgprot_writecombine()/pgprot_device(),
add the defination to fix build error if NOMMU.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/include/asm/mmio.h    | 2 ++
 arch/riscv/include/asm/pgtable.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h
index a2c809df2733..56053c9838b2 100644
--- a/arch/riscv/include/asm/mmio.h
+++ b/arch/riscv/include/asm/mmio.h
@@ -16,6 +16,8 @@
 
 #ifndef CONFIG_MMU
 #define pgprot_noncached(x)	(x)
+#define pgprot_writecombine(x)	(x)
+#define pgprot_device(x)	(x)
 #endif /* CONFIG_MMU */
 
 /* Generic IO read/write.  These perform native-endian accesses. */
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 780dd1d4f720..a12d343e080a 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -470,6 +470,7 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
 
 #else /* CONFIG_MMU */
 
+#define PAGE_SHARED		__pgprot(0)
 #define PAGE_KERNEL		__pgprot(0)
 #define swapper_pg_dir		NULL
 #define TASK_SIZE		0xffffffffUL
-- 
2.26.2

[PATCH 03/10] riscv: Add pgprot_writecombine/device and PAGE_SHARED defination if NOMMU

[Kefeng Wang]

Some drivers use PAGE_SHARED, pgprot_writecombine()/pgprot_device(),
add the defination to fix build error if NOMMU.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/include/asm/mmio.h    | 2 ++
 arch/riscv/include/asm/pgtable.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h
index a2c809df2733..56053c9838b2 100644
--- a/arch/riscv/include/asm/mmio.h
+++ b/arch/riscv/include/asm/mmio.h
@@ -16,6 +16,8 @@
 
 #ifndef CONFIG_MMU
 #define pgprot_noncached(x)	(x)
+#define pgprot_writecombine(x)	(x)
+#define pgprot_device(x)	(x)
 #endif /* CONFIG_MMU */
 
 /* Generic IO read/write.  These perform native-endian accesses. */
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 780dd1d4f720..a12d343e080a 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -470,6 +470,7 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
 
 #else /* CONFIG_MMU */
 
+#define PAGE_SHARED		__pgprot(0)
 #define PAGE_KERNEL		__pgprot(0)
 #define swapper_pg_dir		NULL
 #define TASK_SIZE		0xffffffffUL
-- 
2.26.2

[PATCH 04/10] riscv: Fix print_vm_layout build error if NOMMU

[Kefeng Wang]

arch/riscv/mm/init.c: In function ‘print_vm_layout’:
arch/riscv/mm/init.c:68:37: error: ‘FIXADDR_START’ undeclared (first use in this function);
arch/riscv/mm/init.c:69:20: error: ‘FIXADDR_TOP’ undeclared
arch/riscv/mm/init.c:70:37: error: ‘PCI_IO_START’ undeclared
arch/riscv/mm/init.c:71:20: error: ‘PCI_IO_END’ undeclared
arch/riscv/mm/init.c:72:38: error: ‘VMEMMAP_START’ undeclared
arch/riscv/mm/init.c:73:20: error: ‘VMEMMAP_END’ undeclared (first use in this function);

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/mm/init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index dfcaebc3928f..58c39c44b9c9 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -49,7 +49,7 @@ static void setup_zero_page(void)
 	memset((void *)empty_zero_page, 0, PAGE_SIZE);
 }
 
-#ifdef CONFIG_DEBUG_VM
+#if defined(CONFIG_MMU) && defined(DEBUG_VM)
 static inline void print_mlk(char *name, unsigned long b, unsigned long t)
 {
 	pr_notice("%12s : 0x%08lx - 0x%08lx   (%4ld kB)\n", name, b, t,
-- 
2.26.2

[PATCH 04/10] riscv: Fix print_vm_layout build error if NOMMU

[Kefeng Wang]

arch/riscv/mm/init.c: In function ‘print_vm_layout’:
arch/riscv/mm/init.c:68:37: error: ‘FIXADDR_START’ undeclared (first use in this function);
arch/riscv/mm/init.c:69:20: error: ‘FIXADDR_TOP’ undeclared
arch/riscv/mm/init.c:70:37: error: ‘PCI_IO_START’ undeclared
arch/riscv/mm/init.c:71:20: error: ‘PCI_IO_END’ undeclared
arch/riscv/mm/init.c:72:38: error: ‘VMEMMAP_START’ undeclared
arch/riscv/mm/init.c:73:20: error: ‘VMEMMAP_END’ undeclared (first use in this function);

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/mm/init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index dfcaebc3928f..58c39c44b9c9 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -49,7 +49,7 @@ static void setup_zero_page(void)
 	memset((void *)empty_zero_page, 0, PAGE_SIZE);
 }
 
-#ifdef CONFIG_DEBUG_VM
+#if defined(CONFIG_MMU) && defined(DEBUG_VM)
 static inline void print_mlk(char *name, unsigned long b, unsigned long t)
 {
 	pr_notice("%12s : 0x%08lx - 0x%08lx   (%4ld kB)\n", name, b, t,
-- 
2.26.2

Re: [PATCH 04/10] riscv: Fix print_vm_layout build error if NOMMU

[Alex Ghiti]

Hi,

On 5/10/20 10:19 PM, Kefeng Wang wrote:
> arch/riscv/mm/init.c: In function ‘print_vm_layout’:
> arch/riscv/mm/init.c:68:37: error: ‘FIXADDR_START’ undeclared (first use in this function);
> arch/riscv/mm/init.c:69:20: error: ‘FIXADDR_TOP’ undeclared
> arch/riscv/mm/init.c:70:37: error: ‘PCI_IO_START’ undeclared
> arch/riscv/mm/init.c:71:20: error: ‘PCI_IO_END’ undeclared
> arch/riscv/mm/init.c:72:38: error: ‘VMEMMAP_START’ undeclared
> arch/riscv/mm/init.c:73:20: error: ‘VMEMMAP_END’ undeclared (first use in this function);
>
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>   arch/riscv/mm/init.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index dfcaebc3928f..58c39c44b9c9 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -49,7 +49,7 @@ static void setup_zero_page(void)
>   	memset((void *)empty_zero_page, 0, PAGE_SIZE);
>   }
>   
> -#ifdef CONFIG_DEBUG_VM
> +#if defined(CONFIG_MMU) && defined(DEBUG_VM)


Shouldn't it be CONFIG_DEBUG_VM ?


>   static inline void print_mlk(char *name, unsigned long b, unsigned long t)
>   {
>   	pr_notice("%12s : 0x%08lx - 0x%08lx   (%4ld kB)\n", name, b, t,


Alex

Re: [PATCH 04/10] riscv: Fix print_vm_layout build error if NOMMU

[Kefeng Wang]

On 2020/5/14 18:10, Alex Ghiti wrote:
> Hi,
>
> On 5/10/20 10:19 PM, Kefeng Wang wrote:
>> arch/riscv/mm/init.c: In function ‘print_vm_layout’:
>> arch/riscv/mm/init.c:68:37: error: ‘FIXADDR_START’ undeclared (first 
>> use in this function);
>> arch/riscv/mm/init.c:69:20: error: ‘FIXADDR_TOP’ undeclared
>> arch/riscv/mm/init.c:70:37: error: ‘PCI_IO_START’ undeclared
>> arch/riscv/mm/init.c:71:20: error: ‘PCI_IO_END’ undeclared
>> arch/riscv/mm/init.c:72:38: error: ‘VMEMMAP_START’ undeclared
>> arch/riscv/mm/init.c:73:20: error: ‘VMEMMAP_END’ undeclared (first 
>> use in this function);
>>
>> Reported-by: Hulk Robot <hulkci@huawei.com>
>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>> ---
>>   arch/riscv/mm/init.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
>> index dfcaebc3928f..58c39c44b9c9 100644
>> --- a/arch/riscv/mm/init.c
>> +++ b/arch/riscv/mm/init.c
>> @@ -49,7 +49,7 @@ static void setup_zero_page(void)
>>       memset((void *)empty_zero_page, 0, PAGE_SIZE);
>>   }
>>   -#ifdef CONFIG_DEBUG_VM
>> +#if defined(CONFIG_MMU) && defined(DEBUG_VM)
>
>
> Shouldn't it be CONFIG_DEBUG_VM ?
oops, should be CONFIG_DEBUG_VM, will send v2, thanks.
>
>
>>   static inline void print_mlk(char *name, unsigned long b, unsigned 
>> long t)
>>   {
>>       pr_notice("%12s : 0x%08lx - 0x%08lx   (%4ld kB)\n", name, b, t,
>
>
> Alex
>
>
> .
>

[PATCH v2] riscv: Fix print_vm_layout build error if NOMMU

[Kefeng Wang]

arch/riscv/mm/init.c: In function ‘print_vm_layout’:
arch/riscv/mm/init.c:68:37: error: ‘FIXADDR_START’ undeclared (first use in this function);
arch/riscv/mm/init.c:69:20: error: ‘FIXADDR_TOP’ undeclared
arch/riscv/mm/init.c:70:37: error: ‘PCI_IO_START’ undeclared
arch/riscv/mm/init.c:71:20: error: ‘PCI_IO_END’ undeclared
arch/riscv/mm/init.c:72:38: error: ‘VMEMMAP_START’ undeclared
arch/riscv/mm/init.c:73:20: error: ‘VMEMMAP_END’ undeclared (first use in this function);

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
v2: 
- Should CONFIG_DEBUG_VM instead of DEBUG_VM
- Based on riscv fixes branch

 arch/riscv/mm/init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 27a334106708..736de6c8739f 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -47,7 +47,7 @@ static void setup_zero_page(void)
 	memset((void *)empty_zero_page, 0, PAGE_SIZE);
 }
 
-#ifdef CONFIG_DEBUG_VM
+#if defined(CONFIG_MMU) && defined(CONFIG_DEBUG_VM)
 static inline void print_mlk(char *name, unsigned long b, unsigned long t)
 {
 	pr_notice("%12s : 0x%08lx - 0x%08lx   (%4ld kB)\n", name, b, t,
-- 
2.26.2

[PATCH v2] riscv: Fix print_vm_layout build error if NOMMU

[Kefeng Wang]

arch/riscv/mm/init.c: In function ‘print_vm_layout’:
arch/riscv/mm/init.c:68:37: error: ‘FIXADDR_START’ undeclared (first use in this function);
arch/riscv/mm/init.c:69:20: error: ‘FIXADDR_TOP’ undeclared
arch/riscv/mm/init.c:70:37: error: ‘PCI_IO_START’ undeclared
arch/riscv/mm/init.c:71:20: error: ‘PCI_IO_END’ undeclared
arch/riscv/mm/init.c:72:38: error: ‘VMEMMAP_START’ undeclared
arch/riscv/mm/init.c:73:20: error: ‘VMEMMAP_END’ undeclared (first use in this function);

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
v2: 
- Should CONFIG_DEBUG_VM instead of DEBUG_VM
- Based on riscv fixes branch

 arch/riscv/mm/init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 27a334106708..736de6c8739f 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -47,7 +47,7 @@ static void setup_zero_page(void)
 	memset((void *)empty_zero_page, 0, PAGE_SIZE);
 }
 
-#ifdef CONFIG_DEBUG_VM
+#if defined(CONFIG_MMU) && defined(CONFIG_DEBUG_VM)
 static inline void print_mlk(char *name, unsigned long b, unsigned long t)
 {
 	pr_notice("%12s : 0x%08lx - 0x%08lx   (%4ld kB)\n", name, b, t,
-- 
2.26.2

Re: [PATCH v2] riscv: Fix print_vm_layout build error if NOMMU

[Palmer Dabbelt]

On Thu, 14 May 2020 04:53:35 PDT (-0700), wangkefeng.wang@huawei.com wrote:
> arch/riscv/mm/init.c: In function ‘print_vm_layout’:
> arch/riscv/mm/init.c:68:37: error: ‘FIXADDR_START’ undeclared (first use in this function);
> arch/riscv/mm/init.c:69:20: error: ‘FIXADDR_TOP’ undeclared
> arch/riscv/mm/init.c:70:37: error: ‘PCI_IO_START’ undeclared
> arch/riscv/mm/init.c:71:20: error: ‘PCI_IO_END’ undeclared
> arch/riscv/mm/init.c:72:38: error: ‘VMEMMAP_START’ undeclared
> arch/riscv/mm/init.c:73:20: error: ‘VMEMMAP_END’ undeclared (first use in this function);
>
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
> v2:
> - Should CONFIG_DEBUG_VM instead of DEBUG_VM
> - Based on riscv fixes branch
>
>  arch/riscv/mm/init.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index 27a334106708..736de6c8739f 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -47,7 +47,7 @@ static void setup_zero_page(void)
>  	memset((void *)empty_zero_page, 0, PAGE_SIZE);
>  }
>
> -#ifdef CONFIG_DEBUG_VM
> +#if defined(CONFIG_MMU) && defined(CONFIG_DEBUG_VM)
>  static inline void print_mlk(char *name, unsigned long b, unsigned long t)
>  {
>  	pr_notice("%12s : 0x%08lx - 0x%08lx   (%4ld kB)\n", name, b, t,

Thanks, this is on fixes.

Re: [PATCH v2] riscv: Fix print_vm_layout build error if NOMMU

[Palmer Dabbelt]

On Thu, 14 May 2020 04:53:35 PDT (-0700), wangkefeng.wang@huawei.com wrote:
> arch/riscv/mm/init.c: In function ‘print_vm_layout’:
> arch/riscv/mm/init.c:68:37: error: ‘FIXADDR_START’ undeclared (first use in this function);
> arch/riscv/mm/init.c:69:20: error: ‘FIXADDR_TOP’ undeclared
> arch/riscv/mm/init.c:70:37: error: ‘PCI_IO_START’ undeclared
> arch/riscv/mm/init.c:71:20: error: ‘PCI_IO_END’ undeclared
> arch/riscv/mm/init.c:72:38: error: ‘VMEMMAP_START’ undeclared
> arch/riscv/mm/init.c:73:20: error: ‘VMEMMAP_END’ undeclared (first use in this function);
>
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
> v2:
> - Should CONFIG_DEBUG_VM instead of DEBUG_VM
> - Based on riscv fixes branch
>
>  arch/riscv/mm/init.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index 27a334106708..736de6c8739f 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -47,7 +47,7 @@ static void setup_zero_page(void)
>  	memset((void *)empty_zero_page, 0, PAGE_SIZE);
>  }
>
> -#ifdef CONFIG_DEBUG_VM
> +#if defined(CONFIG_MMU) && defined(CONFIG_DEBUG_VM)
>  static inline void print_mlk(char *name, unsigned long b, unsigned long t)
>  {
>  	pr_notice("%12s : 0x%08lx - 0x%08lx   (%4ld kB)\n", name, b, t,

Thanks, this is on fixes.

[PATCH 05/10] riscv: Disable ARCH_HAS_DEBUG_WX if NOMMU

[Kefeng Wang]

DEBUG_WX is only useful when MMU enabled, diable it if nommu
and fix the build error.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 78f30f2fdd51..7da0a36a8df0 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -69,7 +69,7 @@ config RISCV
 	select HAVE_ARCH_KASAN if MMU && 64BIT
 	select HAVE_ARCH_KGDB
 	select HAVE_ARCH_KGDB_QXFER_PKT
-	select ARCH_HAS_DEBUG_WX
+	select ARCH_HAS_DEBUG_WX if MMU
 
 config ARCH_MMAP_RND_BITS_MIN
 	default 18 if 64BIT
-- 
2.26.2

[PATCH 05/10] riscv: Disable ARCH_HAS_DEBUG_WX if NOMMU

[Kefeng Wang]

DEBUG_WX is only useful when MMU enabled, diable it if nommu
and fix the build error.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 78f30f2fdd51..7da0a36a8df0 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -69,7 +69,7 @@ config RISCV
 	select HAVE_ARCH_KASAN if MMU && 64BIT
 	select HAVE_ARCH_KGDB
 	select HAVE_ARCH_KGDB_QXFER_PKT
-	select ARCH_HAS_DEBUG_WX
+	select ARCH_HAS_DEBUG_WX if MMU
 
 config ARCH_MMAP_RND_BITS_MIN
 	default 18 if 64BIT
-- 
2.26.2

Re: [PATCH 05/10] riscv: Disable ARCH_HAS_DEBUG_WX if NOMMU

[Palmer Dabbelt]

On Sun, 10 May 2020 19:19:56 PDT (-0700), wangkefeng.wang@huawei.com wrote:
> DEBUG_WX is only useful when MMU enabled, diable it if nommu
> and fix the build error.
>
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>  arch/riscv/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 78f30f2fdd51..7da0a36a8df0 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -69,7 +69,7 @@ config RISCV
>  	select HAVE_ARCH_KASAN if MMU && 64BIT
>  	select HAVE_ARCH_KGDB
>  	select HAVE_ARCH_KGDB_QXFER_PKT
> -	select ARCH_HAS_DEBUG_WX
> +	select ARCH_HAS_DEBUG_WX if MMU
>
>  config ARCH_MMAP_RND_BITS_MIN
>  	default 18 if 64BIT

Looks like this depends on something that isn't in any of my trees yet.

Re: [PATCH 05/10] riscv: Disable ARCH_HAS_DEBUG_WX if NOMMU

[Palmer Dabbelt]

On Sun, 10 May 2020 19:19:56 PDT (-0700), wangkefeng.wang@huawei.com wrote:
> DEBUG_WX is only useful when MMU enabled, diable it if nommu
> and fix the build error.
>
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>  arch/riscv/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 78f30f2fdd51..7da0a36a8df0 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -69,7 +69,7 @@ config RISCV
>  	select HAVE_ARCH_KASAN if MMU && 64BIT
>  	select HAVE_ARCH_KGDB
>  	select HAVE_ARCH_KGDB_QXFER_PKT
> -	select ARCH_HAS_DEBUG_WX
> +	select ARCH_HAS_DEBUG_WX if MMU
>
>  config ARCH_MMAP_RND_BITS_MIN
>  	default 18 if 64BIT

Looks like this depends on something that isn't in any of my trees yet.

Re: [PATCH 05/10] riscv: Disable ARCH_HAS_DEBUG_WX if NOMMU

[Kefeng Wang]

On 2020/5/14 5:14, Palmer Dabbelt wrote:
> On Sun, 10 May 2020 19:19:56 PDT (-0700), wangkefeng.wang@huawei.com 
> wrote:
>> DEBUG_WX is only useful when MMU enabled, diable it if nommu
>> and fix the build error.
>>
>> Reported-by: Hulk Robot <hulkci@huawei.com>
>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>> ---
>>  arch/riscv/Kconfig | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index 78f30f2fdd51..7da0a36a8df0 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -69,7 +69,7 @@ config RISCV
>>      select HAVE_ARCH_KASAN if MMU && 64BIT
>>      select HAVE_ARCH_KGDB
>>      select HAVE_ARCH_KGDB_QXFER_PKT
>> -    select ARCH_HAS_DEBUG_WX
>> +    select ARCH_HAS_DEBUG_WX if MMU
>>
>>  config ARCH_MMAP_RND_BITS_MIN
>>      default 18 if 64BIT
>
> Looks like this depends on something that isn't in any of my trees yet.
as said in cover letter, the patch is based on linux-next, tag 
next-20200508 :)
>
>

Re: [PATCH 05/10] riscv: Disable ARCH_HAS_DEBUG_WX if NOMMU

[Kefeng Wang]

On 2020/5/14 5:14, Palmer Dabbelt wrote:
> On Sun, 10 May 2020 19:19:56 PDT (-0700), wangkefeng.wang@huawei.com 
> wrote:
>> DEBUG_WX is only useful when MMU enabled, diable it if nommu
>> and fix the build error.
>>
>> Reported-by: Hulk Robot <hulkci@huawei.com>
>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>> ---
>>  arch/riscv/Kconfig | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index 78f30f2fdd51..7da0a36a8df0 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -69,7 +69,7 @@ config RISCV
>>      select HAVE_ARCH_KASAN if MMU && 64BIT
>>      select HAVE_ARCH_KGDB
>>      select HAVE_ARCH_KGDB_QXFER_PKT
>> -    select ARCH_HAS_DEBUG_WX
>> +    select ARCH_HAS_DEBUG_WX if MMU
>>
>>  config ARCH_MMAP_RND_BITS_MIN
>>      default 18 if 64BIT
>
> Looks like this depends on something that isn't in any of my trees yet.
as said in cover letter, the patch is based on linux-next, tag 
next-20200508 :)
>
>

[PATCH 06/10] riscv: Disable ARCH_HAS_DEBUG_VIRTUAL if NOMMU

[Kefeng Wang]

DEBUG_VIRTUAL should only used when MMU enabled, add the dependence.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7da0a36a8df0..494e670520ae 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -53,7 +53,7 @@ config RISCV
 	select GENERIC_ARCH_TOPOLOGY if SMP
 	select ARCH_HAS_PTE_SPECIAL
 	select ARCH_HAS_MMIOWB
-	select ARCH_HAS_DEBUG_VIRTUAL
+	select ARCH_HAS_DEBUG_VIRTUAL if MMU
 	select HAVE_EBPF_JIT if MMU
 	select EDAC_SUPPORT
 	select ARCH_HAS_GIGANTIC_PAGE
-- 
2.26.2

[PATCH 07/10] riscv: Make SYS_SUPPORTS_HUGETLBFS depends on MMU

[Kefeng Wang]

HUGETLBFS only used when MMU enabled, add the dependence.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 494e670520ae..d0010ed8e0f4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -138,6 +138,7 @@ config ARCH_SUPPORTS_DEBUG_PAGEALLOC
 	def_bool y
 
 config SYS_SUPPORTS_HUGETLBFS
+	depends on MMU
 	def_bool y
 
 config STACKTRACE_SUPPORT
-- 
2.26.2

[PATCH 07/10] riscv: Make SYS_SUPPORTS_HUGETLBFS depends on MMU

[Kefeng Wang]

HUGETLBFS only used when MMU enabled, add the dependence.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 494e670520ae..d0010ed8e0f4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -138,6 +138,7 @@ config ARCH_SUPPORTS_DEBUG_PAGEALLOC
 	def_bool y
 
 config SYS_SUPPORTS_HUGETLBFS
+	depends on MMU
 	def_bool y
 
 config STACKTRACE_SUPPORT
-- 
2.26.2

Re: [PATCH 07/10] riscv: Make SYS_SUPPORTS_HUGETLBFS depends on MMU

[Palmer Dabbelt]

On Sun, 10 May 2020 19:19:58 PDT (-0700), wangkefeng.wang@huawei.com wrote:
> HUGETLBFS only used when MMU enabled, add the dependence.
>
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>  arch/riscv/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 494e670520ae..d0010ed8e0f4 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -138,6 +138,7 @@ config ARCH_SUPPORTS_DEBUG_PAGEALLOC
>  	def_bool y
>
>  config SYS_SUPPORTS_HUGETLBFS
> +	depends on MMU
>  	def_bool y

I don't think this is the right way to do this: there's nothing specific to the
RISC-V implementation that makes HUGETLBFS depend on MMU.  That said, SH
appears to do it this way so I'm OK taking this for now.

>
>  config STACKTRACE_SUPPORT

Re: [PATCH 07/10] riscv: Make SYS_SUPPORTS_HUGETLBFS depends on MMU

[Palmer Dabbelt]

On Sun, 10 May 2020 19:19:58 PDT (-0700), wangkefeng.wang@huawei.com wrote:
> HUGETLBFS only used when MMU enabled, add the dependence.
>
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>  arch/riscv/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 494e670520ae..d0010ed8e0f4 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -138,6 +138,7 @@ config ARCH_SUPPORTS_DEBUG_PAGEALLOC
>  	def_bool y
>
>  config SYS_SUPPORTS_HUGETLBFS
> +	depends on MMU
>  	def_bool y

I don't think this is the right way to do this: there's nothing specific to the
RISC-V implementation that makes HUGETLBFS depend on MMU.  That said, SH
appears to do it this way so I'm OK taking this for now.

>
>  config STACKTRACE_SUPPORT

[PATCH 08/10] riscv: pgtable: Fix __kernel_map_pages build error if NOMMU

[Kefeng Wang]

riscv64-none-linux-gnu-ld: mm/page_alloc.o: in function `.L0 ':
page_alloc.c:(.text+0xd34): undefined reference to `__kernel_map_pages'
riscv64-none-linux-gnu-ld: page_alloc.c:(.text+0x104a): undefined reference to `__kernel_map_pages'
riscv64-none-linux-gnu-ld: mm/page_alloc.o: in function `__pageblock_pfn_to_page':
page_alloc.c:(.text+0x145e): undefined reference to `__kernel_map_pages'

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/include/asm/pgtable.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index a12d343e080a..d50706ea1c94 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -477,6 +477,8 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
 #define VMALLOC_START		0
 #define VMALLOC_END		TASK_SIZE
 
+static inline void __kernel_map_pages(struct page *page, int numpages, int enable) {}
+
 #endif /* !CONFIG_MMU */
 
 #define kern_addr_valid(addr)   (1) /* FIXME */
-- 
2.26.2

[PATCH 08/10] riscv: pgtable: Fix __kernel_map_pages build error if NOMMU

[Kefeng Wang]

riscv64-none-linux-gnu-ld: mm/page_alloc.o: in function `.L0 ':
page_alloc.c:(.text+0xd34): undefined reference to `__kernel_map_pages'
riscv64-none-linux-gnu-ld: page_alloc.c:(.text+0x104a): undefined reference to `__kernel_map_pages'
riscv64-none-linux-gnu-ld: mm/page_alloc.o: in function `__pageblock_pfn_to_page':
page_alloc.c:(.text+0x145e): undefined reference to `__kernel_map_pages'

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/include/asm/pgtable.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index a12d343e080a..d50706ea1c94 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -477,6 +477,8 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
 #define VMALLOC_START		0
 #define VMALLOC_END		TASK_SIZE
 
+static inline void __kernel_map_pages(struct page *page, int numpages, int enable) {}
+
 #endif /* !CONFIG_MMU */
 
 #define kern_addr_valid(addr)   (1) /* FIXME */
-- 
2.26.2

[PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Kefeng Wang]

ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 drivers/clocksource/timer-riscv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index c4f15c4068c0..071b8c144027 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -19,6 +19,7 @@
 
 u64 __iomem *riscv_time_cmp;
 u64 __iomem *riscv_time_val;
+EXPORT_SYMBOL(riscv_time_val);
 
 static inline void mmio_set_timer(u64 val)
 {
-- 
2.26.2

[PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Kefeng Wang]

ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 drivers/clocksource/timer-riscv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index c4f15c4068c0..071b8c144027 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -19,6 +19,7 @@
 
 u64 __iomem *riscv_time_cmp;
 u64 __iomem *riscv_time_val;
+EXPORT_SYMBOL(riscv_time_val);
 
 static inline void mmio_set_timer(u64 val)
 {
-- 
2.26.2

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Palmer Dabbelt]

On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com wrote:
> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>  drivers/clocksource/timer-riscv.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index c4f15c4068c0..071b8c144027 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -19,6 +19,7 @@
>
>  u64 __iomem *riscv_time_cmp;
>  u64 __iomem *riscv_time_val;
> +EXPORT_SYMBOL(riscv_time_val);
>
>  static inline void mmio_set_timer(u64 val)
>  {

Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>

Adding the clocksource maintainers.  Let me know if you want this through my
tree, I'm assuming you want it through your tree.

Thanks!

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Palmer Dabbelt]

On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com wrote:
> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>  drivers/clocksource/timer-riscv.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index c4f15c4068c0..071b8c144027 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -19,6 +19,7 @@
>
>  u64 __iomem *riscv_time_cmp;
>  u64 __iomem *riscv_time_val;
> +EXPORT_SYMBOL(riscv_time_val);
>
>  static inline void mmio_set_timer(u64 val)
>  {

Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>

Adding the clocksource maintainers.  Let me know if you want this through my
tree, I'm assuming you want it through your tree.

Thanks!

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Daniel Lezcano]

On 13/05/2020 23:14, Palmer Dabbelt wrote:
> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com wrote:
>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>>
>> Reported-by: Hulk Robot <hulkci@huawei.com>
>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>> ---
>>  drivers/clocksource/timer-riscv.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/clocksource/timer-riscv.c
>> b/drivers/clocksource/timer-riscv.c
>> index c4f15c4068c0..071b8c144027 100644
>> --- a/drivers/clocksource/timer-riscv.c
>> +++ b/drivers/clocksource/timer-riscv.c
>> @@ -19,6 +19,7 @@
>>
>>  u64 __iomem *riscv_time_cmp;
>>  u64 __iomem *riscv_time_val;
>> +EXPORT_SYMBOL(riscv_time_val);
>>
>>  static inline void mmio_set_timer(u64 val)
>>  {
> 
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
> 
> Adding the clocksource maintainers.  Let me know if you want this
> through my
> tree, I'm assuming you want it through your tree.

How can we end up by an export symbol here ?!


-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Daniel Lezcano]

On 13/05/2020 23:14, Palmer Dabbelt wrote:
> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com wrote:
>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>>
>> Reported-by: Hulk Robot <hulkci@huawei.com>
>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>> ---
>>  drivers/clocksource/timer-riscv.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/clocksource/timer-riscv.c
>> b/drivers/clocksource/timer-riscv.c
>> index c4f15c4068c0..071b8c144027 100644
>> --- a/drivers/clocksource/timer-riscv.c
>> +++ b/drivers/clocksource/timer-riscv.c
>> @@ -19,6 +19,7 @@
>>
>>  u64 __iomem *riscv_time_cmp;
>>  u64 __iomem *riscv_time_val;
>> +EXPORT_SYMBOL(riscv_time_val);
>>
>>  static inline void mmio_set_timer(u64 val)
>>  {
> 
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
> 
> Adding the clocksource maintainers.  Let me know if you want this
> through my
> tree, I'm assuming you want it through your tree.

How can we end up by an export symbol here ?!


-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Kefeng Wang]

On 2020/5/18 22:09, Daniel Lezcano wrote:
> On 13/05/2020 23:14, Palmer Dabbelt wrote:
>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com wrote:
>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>>>
>>> Reported-by: Hulk Robot <hulkci@huawei.com>
>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>>> ---
>>>   drivers/clocksource/timer-riscv.c | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/clocksource/timer-riscv.c
>>> b/drivers/clocksource/timer-riscv.c
>>> index c4f15c4068c0..071b8c144027 100644
>>> --- a/drivers/clocksource/timer-riscv.c
>>> +++ b/drivers/clocksource/timer-riscv.c
>>> @@ -19,6 +19,7 @@
>>>
>>>   u64 __iomem *riscv_time_cmp;
>>>   u64 __iomem *riscv_time_val;
>>> +EXPORT_SYMBOL(riscv_time_val);
>>>
>>>   static inline void mmio_set_timer(u64 val)
>>>   {
>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>
>> Adding the clocksource maintainers.  Let me know if you want this
>> through my
>> tree, I'm assuming you want it through your tree.
> How can we end up by an export symbol here ?!

Hi Danile,

Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI 
is not,

see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer 
registers"

thanks.

>
>

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Kefeng Wang]

On 2020/5/18 22:09, Daniel Lezcano wrote:
> On 13/05/2020 23:14, Palmer Dabbelt wrote:
>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com wrote:
>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>>>
>>> Reported-by: Hulk Robot <hulkci@huawei.com>
>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>>> ---
>>>   drivers/clocksource/timer-riscv.c | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/clocksource/timer-riscv.c
>>> b/drivers/clocksource/timer-riscv.c
>>> index c4f15c4068c0..071b8c144027 100644
>>> --- a/drivers/clocksource/timer-riscv.c
>>> +++ b/drivers/clocksource/timer-riscv.c
>>> @@ -19,6 +19,7 @@
>>>
>>>   u64 __iomem *riscv_time_cmp;
>>>   u64 __iomem *riscv_time_val;
>>> +EXPORT_SYMBOL(riscv_time_val);
>>>
>>>   static inline void mmio_set_timer(u64 val)
>>>   {
>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>
>> Adding the clocksource maintainers.  Let me know if you want this
>> through my
>> tree, I'm assuming you want it through your tree.
> How can we end up by an export symbol here ?!

Hi Danile,

Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI 
is not,

see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer 
registers"

thanks.

>
>

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Daniel Lezcano]

Hi Kefeng,

On 18/05/2020 17:40, Kefeng Wang wrote:
> 
> On 2020/5/18 22:09, Daniel Lezcano wrote:
>> On 13/05/2020 23:14, Palmer Dabbelt wrote:
>>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com
>>> wrote:
>>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>>>>
>>>> Reported-by: Hulk Robot <hulkci@huawei.com>
>>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>>>> ---
>>>>   drivers/clocksource/timer-riscv.c | 1 +
>>>>   1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/drivers/clocksource/timer-riscv.c
>>>> b/drivers/clocksource/timer-riscv.c
>>>> index c4f15c4068c0..071b8c144027 100644
>>>> --- a/drivers/clocksource/timer-riscv.c
>>>> +++ b/drivers/clocksource/timer-riscv.c
>>>> @@ -19,6 +19,7 @@
>>>>
>>>>   u64 __iomem *riscv_time_cmp;
>>>>   u64 __iomem *riscv_time_val;
>>>> +EXPORT_SYMBOL(riscv_time_val);
>>>>
>>>>   static inline void mmio_set_timer(u64 val)
>>>>   {
>>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>
>>> Adding the clocksource maintainers.  Let me know if you want this
>>> through my
>>> tree, I'm assuming you want it through your tree.
>> How can we end up by an export symbol here ?!
> 
> Hi Danile,

s/Danile/Daniel/

> Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI
> is not,
> 
> see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer
> registers"

Thanks for the pointer.

The question still remains, how do we end up with this EXPORT_SYMBOL?

There is something wrong if the fix is an EXPORT_SYMBOL for a global
variable.



-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Daniel Lezcano]

Hi Kefeng,

On 18/05/2020 17:40, Kefeng Wang wrote:
> 
> On 2020/5/18 22:09, Daniel Lezcano wrote:
>> On 13/05/2020 23:14, Palmer Dabbelt wrote:
>>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com
>>> wrote:
>>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>>>>
>>>> Reported-by: Hulk Robot <hulkci@huawei.com>
>>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>>>> ---
>>>>   drivers/clocksource/timer-riscv.c | 1 +
>>>>   1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/drivers/clocksource/timer-riscv.c
>>>> b/drivers/clocksource/timer-riscv.c
>>>> index c4f15c4068c0..071b8c144027 100644
>>>> --- a/drivers/clocksource/timer-riscv.c
>>>> +++ b/drivers/clocksource/timer-riscv.c
>>>> @@ -19,6 +19,7 @@
>>>>
>>>>   u64 __iomem *riscv_time_cmp;
>>>>   u64 __iomem *riscv_time_val;
>>>> +EXPORT_SYMBOL(riscv_time_val);
>>>>
>>>>   static inline void mmio_set_timer(u64 val)
>>>>   {
>>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>
>>> Adding the clocksource maintainers.  Let me know if you want this
>>> through my
>>> tree, I'm assuming you want it through your tree.
>> How can we end up by an export symbol here ?!
> 
> Hi Danile,

s/Danile/Daniel/

> Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI
> is not,
> 
> see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer
> registers"

Thanks for the pointer.

The question still remains, how do we end up with this EXPORT_SYMBOL?

There is something wrong if the fix is an EXPORT_SYMBOL for a global
variable.



-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Kefeng Wang]

On 2020/5/19 4:23, Daniel Lezcano wrote:
> Hi Kefeng,
>
> On 18/05/2020 17:40, Kefeng Wang wrote:
>> On 2020/5/18 22:09, Daniel Lezcano wrote:
>>> On 13/05/2020 23:14, Palmer Dabbelt wrote:
>>>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com
>>>> wrote:
>>>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>>>>>
>>>>> Reported-by: Hulk Robot <hulkci@huawei.com>
>>>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>>>>> ---
>>>>>    drivers/clocksource/timer-riscv.c | 1 +
>>>>>    1 file changed, 1 insertion(+)
>>>>>
>>>>> diff --git a/drivers/clocksource/timer-riscv.c
>>>>> b/drivers/clocksource/timer-riscv.c
>>>>> index c4f15c4068c0..071b8c144027 100644
>>>>> --- a/drivers/clocksource/timer-riscv.c
>>>>> +++ b/drivers/clocksource/timer-riscv.c
>>>>> @@ -19,6 +19,7 @@
>>>>>
>>>>>    u64 __iomem *riscv_time_cmp;
>>>>>    u64 __iomem *riscv_time_val;
>>>>> +EXPORT_SYMBOL(riscv_time_val);
>>>>>
>>>>>    static inline void mmio_set_timer(u64 val)
>>>>>    {
>>>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>>
>>>> Adding the clocksource maintainers.  Let me know if you want this
>>>> through my
>>>> tree, I'm assuming you want it through your tree.
>>> How can we end up by an export symbol here ?!
>> Hi Danile,
> s/Danile/Daniel/
Sorry for typing error.
>
>> Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI
>> is not,
>>
>> see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer
>> registers"
> Thanks for the pointer.
>
> The question still remains, how do we end up with this EXPORT_SYMBOL?
>
> There is something wrong if the fix is an EXPORT_SYMBOL for a global
> variable.

Not very clear, there are some global variable( eg, acpi_disabled, 
memstart_addr in arm64,) is exported by EXPORT_SYMBOL,  do you mean that 
export riscv_time_val is wrong way?



>
>
>

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Kefeng Wang]

On 2020/5/19 4:23, Daniel Lezcano wrote:
> Hi Kefeng,
>
> On 18/05/2020 17:40, Kefeng Wang wrote:
>> On 2020/5/18 22:09, Daniel Lezcano wrote:
>>> On 13/05/2020 23:14, Palmer Dabbelt wrote:
>>>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com
>>>> wrote:
>>>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>>>>>
>>>>> Reported-by: Hulk Robot <hulkci@huawei.com>
>>>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>>>>> ---
>>>>>    drivers/clocksource/timer-riscv.c | 1 +
>>>>>    1 file changed, 1 insertion(+)
>>>>>
>>>>> diff --git a/drivers/clocksource/timer-riscv.c
>>>>> b/drivers/clocksource/timer-riscv.c
>>>>> index c4f15c4068c0..071b8c144027 100644
>>>>> --- a/drivers/clocksource/timer-riscv.c
>>>>> +++ b/drivers/clocksource/timer-riscv.c
>>>>> @@ -19,6 +19,7 @@
>>>>>
>>>>>    u64 __iomem *riscv_time_cmp;
>>>>>    u64 __iomem *riscv_time_val;
>>>>> +EXPORT_SYMBOL(riscv_time_val);
>>>>>
>>>>>    static inline void mmio_set_timer(u64 val)
>>>>>    {
>>>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>>
>>>> Adding the clocksource maintainers.  Let me know if you want this
>>>> through my
>>>> tree, I'm assuming you want it through your tree.
>>> How can we end up by an export symbol here ?!
>> Hi Danile,
> s/Danile/Daniel/
Sorry for typing error.
>
>> Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI
>> is not,
>>
>> see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer
>> registers"
> Thanks for the pointer.
>
> The question still remains, how do we end up with this EXPORT_SYMBOL?
>
> There is something wrong if the fix is an EXPORT_SYMBOL for a global
> variable.

Not very clear, there are some global variable( eg, acpi_disabled, 
memstart_addr in arm64,) is exported by EXPORT_SYMBOL,  do you mean that 
export riscv_time_val is wrong way?



>
>
>

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Daniel Lezcano]

On 19/05/2020 14:39, Kefeng Wang wrote:
> 
> On 2020/5/19 4:23, Daniel Lezcano wrote:
>> Hi Kefeng,
>>
>> On 18/05/2020 17:40, Kefeng Wang wrote:
>>> On 2020/5/18 22:09, Daniel Lezcano wrote:
>>>> On 13/05/2020 23:14, Palmer Dabbelt wrote:
>>>>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com
>>>>> wrote:
>>>>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>>>>>>
>>>>>> Reported-by: Hulk Robot <hulkci@huawei.com>
>>>>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>>>>>> ---
>>>>>>    drivers/clocksource/timer-riscv.c | 1 +
>>>>>>    1 file changed, 1 insertion(+)
>>>>>>
>>>>>> diff --git a/drivers/clocksource/timer-riscv.c
>>>>>> b/drivers/clocksource/timer-riscv.c
>>>>>> index c4f15c4068c0..071b8c144027 100644
>>>>>> --- a/drivers/clocksource/timer-riscv.c
>>>>>> +++ b/drivers/clocksource/timer-riscv.c
>>>>>> @@ -19,6 +19,7 @@
>>>>>>
>>>>>>    u64 __iomem *riscv_time_cmp;
>>>>>>    u64 __iomem *riscv_time_val;
>>>>>> +EXPORT_SYMBOL(riscv_time_val);
>>>>>>
>>>>>>    static inline void mmio_set_timer(u64 val)
>>>>>>    {
>>>>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>>> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>>>
>>>>> Adding the clocksource maintainers.  Let me know if you want this
>>>>> through my
>>>>> tree, I'm assuming you want it through your tree.
>>>> How can we end up by an export symbol here ?!
>>> Hi Danile,
>> s/Danile/Daniel/
> Sorry for typing error.
>>
>>> Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI
>>> is not,
>>>
>>> see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer
>>> registers"
>> Thanks for the pointer.
>>
>> The question still remains, how do we end up with this EXPORT_SYMBOL?
>>
>> There is something wrong if the fix is an EXPORT_SYMBOL for a global
>> variable.
> 
> Not very clear, there are some global variable( eg, acpi_disabled,
> memstart_addr in arm64,) is exported by EXPORT_SYMBOL,  do you mean that
> export riscv_time_val is wrong way?

I do not maintain acpi neither arm64.mm.

AFAICT, riscv_time_val is globally declared in
drivers/clocksource/timer-riscv.c

The driver does not use this variable at all. Then there is a readl on
it in the header file arch/riscv/include/asm/timex.h

And finally it is initialized in arch/riscv/kernel/clint.c

Same thing for riscv_time_cmp.

The correct fix is to initialize the variables in the place where they
belong to (drivers/clocksource/timer-riscv.c), create a function to read
their content and export-symbol-gpl the function.


-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Daniel Lezcano]

On 19/05/2020 14:39, Kefeng Wang wrote:
> 
> On 2020/5/19 4:23, Daniel Lezcano wrote:
>> Hi Kefeng,
>>
>> On 18/05/2020 17:40, Kefeng Wang wrote:
>>> On 2020/5/18 22:09, Daniel Lezcano wrote:
>>>> On 13/05/2020 23:14, Palmer Dabbelt wrote:
>>>>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com
>>>>> wrote:
>>>>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>>>>>>
>>>>>> Reported-by: Hulk Robot <hulkci@huawei.com>
>>>>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>>>>>> ---
>>>>>>    drivers/clocksource/timer-riscv.c | 1 +
>>>>>>    1 file changed, 1 insertion(+)
>>>>>>
>>>>>> diff --git a/drivers/clocksource/timer-riscv.c
>>>>>> b/drivers/clocksource/timer-riscv.c
>>>>>> index c4f15c4068c0..071b8c144027 100644
>>>>>> --- a/drivers/clocksource/timer-riscv.c
>>>>>> +++ b/drivers/clocksource/timer-riscv.c
>>>>>> @@ -19,6 +19,7 @@
>>>>>>
>>>>>>    u64 __iomem *riscv_time_cmp;
>>>>>>    u64 __iomem *riscv_time_val;
>>>>>> +EXPORT_SYMBOL(riscv_time_val);
>>>>>>
>>>>>>    static inline void mmio_set_timer(u64 val)
>>>>>>    {
>>>>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>>> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>>>
>>>>> Adding the clocksource maintainers.  Let me know if you want this
>>>>> through my
>>>>> tree, I'm assuming you want it through your tree.
>>>> How can we end up by an export symbol here ?!
>>> Hi Danile,
>> s/Danile/Daniel/
> Sorry for typing error.
>>
>>> Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI
>>> is not,
>>>
>>> see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer
>>> registers"
>> Thanks for the pointer.
>>
>> The question still remains, how do we end up with this EXPORT_SYMBOL?
>>
>> There is something wrong if the fix is an EXPORT_SYMBOL for a global
>> variable.
> 
> Not very clear, there are some global variable( eg, acpi_disabled,
> memstart_addr in arm64,) is exported by EXPORT_SYMBOL,  do you mean that
> export riscv_time_val is wrong way?

I do not maintain acpi neither arm64.mm.

AFAICT, riscv_time_val is globally declared in
drivers/clocksource/timer-riscv.c

The driver does not use this variable at all. Then there is a readl on
it in the header file arch/riscv/include/asm/timex.h

And finally it is initialized in arch/riscv/kernel/clint.c

Same thing for riscv_time_cmp.

The correct fix is to initialize the variables in the place where they
belong to (drivers/clocksource/timer-riscv.c), create a function to read
their content and export-symbol-gpl the function.


-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Anup Patel]

On Tue, May 19, 2020 at 7:21 PM Daniel Lezcano
<daniel.lezcano@linaro.org> wrote:
>
> On 19/05/2020 14:39, Kefeng Wang wrote:
> >
> > On 2020/5/19 4:23, Daniel Lezcano wrote:
> >> Hi Kefeng,
> >>
> >> On 18/05/2020 17:40, Kefeng Wang wrote:
> >>> On 2020/5/18 22:09, Daniel Lezcano wrote:
> >>>> On 13/05/2020 23:14, Palmer Dabbelt wrote:
> >>>>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com
> >>>>> wrote:
> >>>>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
> >>>>>>
> >>>>>> Reported-by: Hulk Robot <hulkci@huawei.com>
> >>>>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> >>>>>> ---
> >>>>>>    drivers/clocksource/timer-riscv.c | 1 +
> >>>>>>    1 file changed, 1 insertion(+)
> >>>>>>
> >>>>>> diff --git a/drivers/clocksource/timer-riscv.c
> >>>>>> b/drivers/clocksource/timer-riscv.c
> >>>>>> index c4f15c4068c0..071b8c144027 100644
> >>>>>> --- a/drivers/clocksource/timer-riscv.c
> >>>>>> +++ b/drivers/clocksource/timer-riscv.c
> >>>>>> @@ -19,6 +19,7 @@
> >>>>>>
> >>>>>>    u64 __iomem *riscv_time_cmp;
> >>>>>>    u64 __iomem *riscv_time_val;
> >>>>>> +EXPORT_SYMBOL(riscv_time_val);
> >>>>>>
> >>>>>>    static inline void mmio_set_timer(u64 val)
> >>>>>>    {
> >>>>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> >>>>> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
> >>>>>
> >>>>> Adding the clocksource maintainers.  Let me know if you want this
> >>>>> through my
> >>>>> tree, I'm assuming you want it through your tree.
> >>>> How can we end up by an export symbol here ?!
> >>> Hi Danile,
> >> s/Danile/Daniel/
> > Sorry for typing error.
> >>
> >>> Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI
> >>> is not,
> >>>
> >>> see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer
> >>> registers"
> >> Thanks for the pointer.
> >>
> >> The question still remains, how do we end up with this EXPORT_SYMBOL?
> >>
> >> There is something wrong if the fix is an EXPORT_SYMBOL for a global
> >> variable.
> >
> > Not very clear, there are some global variable( eg, acpi_disabled,
> > memstart_addr in arm64,) is exported by EXPORT_SYMBOL,  do you mean that
> > export riscv_time_val is wrong way?
>
> I do not maintain acpi neither arm64.mm.
>
> AFAICT, riscv_time_val is globally declared in
> drivers/clocksource/timer-riscv.c
>
> The driver does not use this variable at all. Then there is a readl on
> it in the header file arch/riscv/include/asm/timex.h
>
> And finally it is initialized in arch/riscv/kernel/clint.c
>
> Same thing for riscv_time_cmp.
>
> The correct fix is to initialize the variables in the place where they
> belong to (drivers/clocksource/timer-riscv.c), create a function to read
> their content and export-symbol-gpl the function.

I agree with Daniel. Exporting riscv_time_val is a temporary fix.

The problem is timer-riscv.c is pretty convoluted right now. It is
implementing two different clocksources and clockevents in one-place.

I think we need two separate drivers for RISC-V world.

1. timer-riscv: This for regular S-mode kernel with MMU. The clocksource
will use TIME CSR and the clockevent device will use SBI calls.

2. timer-clint: This for M-mode kernel without MMU (or NoMMU kernel).
The clocksource will use MMIO counter for clocksource and the
clockevent device will use MMIO compare registers.

I will send a patch to have a separate timer-clint driver under
drivers/clocksource. (@Daniel, I hope you will be fine with this?)

Regards,
Anup

>
>
> --
> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Anup Patel]

On Tue, May 19, 2020 at 7:21 PM Daniel Lezcano
<daniel.lezcano@linaro.org> wrote:
>
> On 19/05/2020 14:39, Kefeng Wang wrote:
> >
> > On 2020/5/19 4:23, Daniel Lezcano wrote:
> >> Hi Kefeng,
> >>
> >> On 18/05/2020 17:40, Kefeng Wang wrote:
> >>> On 2020/5/18 22:09, Daniel Lezcano wrote:
> >>>> On 13/05/2020 23:14, Palmer Dabbelt wrote:
> >>>>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com
> >>>>> wrote:
> >>>>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
> >>>>>>
> >>>>>> Reported-by: Hulk Robot <hulkci@huawei.com>
> >>>>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> >>>>>> ---
> >>>>>>    drivers/clocksource/timer-riscv.c | 1 +
> >>>>>>    1 file changed, 1 insertion(+)
> >>>>>>
> >>>>>> diff --git a/drivers/clocksource/timer-riscv.c
> >>>>>> b/drivers/clocksource/timer-riscv.c
> >>>>>> index c4f15c4068c0..071b8c144027 100644
> >>>>>> --- a/drivers/clocksource/timer-riscv.c
> >>>>>> +++ b/drivers/clocksource/timer-riscv.c
> >>>>>> @@ -19,6 +19,7 @@
> >>>>>>
> >>>>>>    u64 __iomem *riscv_time_cmp;
> >>>>>>    u64 __iomem *riscv_time_val;
> >>>>>> +EXPORT_SYMBOL(riscv_time_val);
> >>>>>>
> >>>>>>    static inline void mmio_set_timer(u64 val)
> >>>>>>    {
> >>>>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> >>>>> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
> >>>>>
> >>>>> Adding the clocksource maintainers.  Let me know if you want this
> >>>>> through my
> >>>>> tree, I'm assuming you want it through your tree.
> >>>> How can we end up by an export symbol here ?!
> >>> Hi Danile,
> >> s/Danile/Daniel/
> > Sorry for typing error.
> >>
> >>> Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI
> >>> is not,
> >>>
> >>> see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer
> >>> registers"
> >> Thanks for the pointer.
> >>
> >> The question still remains, how do we end up with this EXPORT_SYMBOL?
> >>
> >> There is something wrong if the fix is an EXPORT_SYMBOL for a global
> >> variable.
> >
> > Not very clear, there are some global variable( eg, acpi_disabled,
> > memstart_addr in arm64,) is exported by EXPORT_SYMBOL,  do you mean that
> > export riscv_time_val is wrong way?
>
> I do not maintain acpi neither arm64.mm.
>
> AFAICT, riscv_time_val is globally declared in
> drivers/clocksource/timer-riscv.c
>
> The driver does not use this variable at all. Then there is a readl on
> it in the header file arch/riscv/include/asm/timex.h
>
> And finally it is initialized in arch/riscv/kernel/clint.c
>
> Same thing for riscv_time_cmp.
>
> The correct fix is to initialize the variables in the place where they
> belong to (drivers/clocksource/timer-riscv.c), create a function to read
> their content and export-symbol-gpl the function.

I agree with Daniel. Exporting riscv_time_val is a temporary fix.

The problem is timer-riscv.c is pretty convoluted right now. It is
implementing two different clocksources and clockevents in one-place.

I think we need two separate drivers for RISC-V world.

1. timer-riscv: This for regular S-mode kernel with MMU. The clocksource
will use TIME CSR and the clockevent device will use SBI calls.

2. timer-clint: This for M-mode kernel without MMU (or NoMMU kernel).
The clocksource will use MMIO counter for clocksource and the
clockevent device will use MMIO compare registers.

I will send a patch to have a separate timer-clint driver under
drivers/clocksource. (@Daniel, I hope you will be fine with this?)

Regards,
Anup

>
>
> --
> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Kefeng Wang]

On 2020/5/20 9:14, Anup Patel wrote:
> On Tue, May 19, 2020 at 7:21 PM Daniel Lezcano
> <daniel.lezcano@linaro.org> wrote:
>> On 19/05/2020 14:39, Kefeng Wang wrote:
>>> On 2020/5/19 4:23, Daniel Lezcano wrote:
>>>> Hi Kefeng,
>>>>
>>>> On 18/05/2020 17:40, Kefeng Wang wrote:
>>>>> On 2020/5/18 22:09, Daniel Lezcano wrote:
>>>>>> On 13/05/2020 23:14, Palmer Dabbelt wrote:
>>>>>>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com
>>>>>>> wrote:
>>>>>>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>>>>>>>>
>>>>>>>> Reported-by: Hulk Robot <hulkci@huawei.com>
>>>>>>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>>>>>>>> ---
>>>>>>>>     drivers/clocksource/timer-riscv.c | 1 +
>>>>>>>>     1 file changed, 1 insertion(+)
>>>>>>>>
>>>>>>>> diff --git a/drivers/clocksource/timer-riscv.c
>>>>>>>> b/drivers/clocksource/timer-riscv.c
>>>>>>>> index c4f15c4068c0..071b8c144027 100644
>>>>>>>> --- a/drivers/clocksource/timer-riscv.c
>>>>>>>> +++ b/drivers/clocksource/timer-riscv.c
>>>>>>>> @@ -19,6 +19,7 @@
>>>>>>>>
>>>>>>>>     u64 __iomem *riscv_time_cmp;
>>>>>>>>     u64 __iomem *riscv_time_val;
>>>>>>>> +EXPORT_SYMBOL(riscv_time_val);
>>>>>>>>
>>>>>>>>     static inline void mmio_set_timer(u64 val)
>>>>>>>>     {
>>>>>>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>>>>> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>>>>>
>>>>>>> Adding the clocksource maintainers.  Let me know if you want this
>>>>>>> through my
>>>>>>> tree, I'm assuming you want it through your tree.
>>>>>> How can we end up by an export symbol here ?!
>>>>> Hi Danile,
>>>> s/Danile/Daniel/
>>> Sorry for typing error.
>>>>> Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI
>>>>> is not,
>>>>>
>>>>> see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer
>>>>> registers"
>>>> Thanks for the pointer.
>>>>
>>>> The question still remains, how do we end up with this EXPORT_SYMBOL?
>>>>
>>>> There is something wrong if the fix is an EXPORT_SYMBOL for a global
>>>> variable.
>>> Not very clear, there are some global variable( eg, acpi_disabled,
>>> memstart_addr in arm64,) is exported by EXPORT_SYMBOL,  do you mean that
>>> export riscv_time_val is wrong way?
>> I do not maintain acpi neither arm64.mm.
>>
>> AFAICT, riscv_time_val is globally declared in
>> drivers/clocksource/timer-riscv.c
>>
>> The driver does not use this variable at all. Then there is a readl on
>> it in the header file arch/riscv/include/asm/timex.h
>>
>> And finally it is initialized in arch/riscv/kernel/clint.c
>>
>> Same thing for riscv_time_cmp.
>>
>> The correct fix is to initialize the variables in the place where they
>> belong to (drivers/clocksource/timer-riscv.c), create a function to read
>> their content and export-symbol-gpl the function.

ok, it's better.  thanks for your explanation.


> I agree with Daniel. Exporting riscv_time_val is a temporary fix.

yes.  it's only for build,  let's wait for Anup's patch.

>
> The problem is timer-riscv.c is pretty convoluted right now. It is
> implementing two different clocksources and clockevents in one-place.
>
> I think we need two separate drivers for RISC-V world.
>
> 1. timer-riscv: This for regular S-mode kernel with MMU. The clocksource
> will use TIME CSR and the clockevent device will use SBI calls.
>
> 2. timer-clint: This for M-mode kernel without MMU (or NoMMU kernel).
> The clocksource will use MMIO counter for clocksource and the
> clockevent device will use MMIO compare registers.
>
> I will send a patch to have a separate timer-clint driver under
> drivers/clocksource. (@Daniel, I hope you will be fine with this?)
> Regards,
> Anup
>
>>
>> --
>> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>>
>> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
>> <http://twitter.com/#!/linaroorg> Twitter |
>> <http://www.linaro.org/linaro-blog/> Blog
> .
>

Re: [PATCH 09/10] timer-riscv: Fix undefined riscv_time_val

[Kefeng Wang]

On 2020/5/20 9:14, Anup Patel wrote:
> On Tue, May 19, 2020 at 7:21 PM Daniel Lezcano
> <daniel.lezcano@linaro.org> wrote:
>> On 19/05/2020 14:39, Kefeng Wang wrote:
>>> On 2020/5/19 4:23, Daniel Lezcano wrote:
>>>> Hi Kefeng,
>>>>
>>>> On 18/05/2020 17:40, Kefeng Wang wrote:
>>>>> On 2020/5/18 22:09, Daniel Lezcano wrote:
>>>>>> On 13/05/2020 23:14, Palmer Dabbelt wrote:
>>>>>>> On Sun, 10 May 2020 19:20:00 PDT (-0700), wangkefeng.wang@huawei.com
>>>>>>> wrote:
>>>>>>>> ERROR: modpost: "riscv_time_val" [crypto/tcrypt.ko] undefined!
>>>>>>>>
>>>>>>>> Reported-by: Hulk Robot <hulkci@huawei.com>
>>>>>>>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>>>>>>>> ---
>>>>>>>>     drivers/clocksource/timer-riscv.c | 1 +
>>>>>>>>     1 file changed, 1 insertion(+)
>>>>>>>>
>>>>>>>> diff --git a/drivers/clocksource/timer-riscv.c
>>>>>>>> b/drivers/clocksource/timer-riscv.c
>>>>>>>> index c4f15c4068c0..071b8c144027 100644
>>>>>>>> --- a/drivers/clocksource/timer-riscv.c
>>>>>>>> +++ b/drivers/clocksource/timer-riscv.c
>>>>>>>> @@ -19,6 +19,7 @@
>>>>>>>>
>>>>>>>>     u64 __iomem *riscv_time_cmp;
>>>>>>>>     u64 __iomem *riscv_time_val;
>>>>>>>> +EXPORT_SYMBOL(riscv_time_val);
>>>>>>>>
>>>>>>>>     static inline void mmio_set_timer(u64 val)
>>>>>>>>     {
>>>>>>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>>>>> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>>>>>>
>>>>>>> Adding the clocksource maintainers.  Let me know if you want this
>>>>>>> through my
>>>>>>> tree, I'm assuming you want it through your tree.
>>>>>> How can we end up by an export symbol here ?!
>>>>> Hi Danile,
>>>> s/Danile/Daniel/
>>> Sorry for typing error.
>>>>> Found this build error when CONFIG_RISCV_M_MODE=y and CONFIG_RISCV_SBI
>>>>> is not,
>>>>>
>>>>> see patch "4f9bbcefa142 riscv: add support for MMIO access to the timer
>>>>> registers"
>>>> Thanks for the pointer.
>>>>
>>>> The question still remains, how do we end up with this EXPORT_SYMBOL?
>>>>
>>>> There is something wrong if the fix is an EXPORT_SYMBOL for a global
>>>> variable.
>>> Not very clear, there are some global variable( eg, acpi_disabled,
>>> memstart_addr in arm64,) is exported by EXPORT_SYMBOL,  do you mean that
>>> export riscv_time_val is wrong way?
>> I do not maintain acpi neither arm64.mm.
>>
>> AFAICT, riscv_time_val is globally declared in
>> drivers/clocksource/timer-riscv.c
>>
>> The driver does not use this variable at all. Then there is a readl on
>> it in the header file arch/riscv/include/asm/timex.h
>>
>> And finally it is initialized in arch/riscv/kernel/clint.c
>>
>> Same thing for riscv_time_cmp.
>>
>> The correct fix is to initialize the variables in the place where they
>> belong to (drivers/clocksource/timer-riscv.c), create a function to read
>> their content and export-symbol-gpl the function.

ok, it's better.  thanks for your explanation.


> I agree with Daniel. Exporting riscv_time_val is a temporary fix.

yes.  it's only for build,  let's wait for Anup's patch.

>
> The problem is timer-riscv.c is pretty convoluted right now. It is
> implementing two different clocksources and clockevents in one-place.
>
> I think we need two separate drivers for RISC-V world.
>
> 1. timer-riscv: This for regular S-mode kernel with MMU. The clocksource
> will use TIME CSR and the clockevent device will use SBI calls.
>
> 2. timer-clint: This for M-mode kernel without MMU (or NoMMU kernel).
> The clocksource will use MMIO counter for clocksource and the
> clockevent device will use MMIO compare registers.
>
> I will send a patch to have a separate timer-clint driver under
> drivers/clocksource. (@Daniel, I hope you will be fine with this?)
> Regards,
> Anup
>
>>
>> --
>> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>>
>> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
>> <http://twitter.com/#!/linaroorg> Twitter |
>> <http://www.linaro.org/linaro-blog/> Blog
> .
>

[PATCH 10/10] riscv: mmiowb: Fix implicit declaration of function 'smp_processor_id'

[Kefeng Wang]

In file included from ./../include/linux/compiler_types.h:68,
                 from <command-line>:
../include/asm-generic/mmiowb.h: In function ‘mmiowb_set_pending’:
../include/asm-generic/percpu.h:34:38: error: implicit declaration of function ‘smp_processor_id’; did you mean ‘raw_smp_processor_id’? [-Werror=implicit-function-declaration]
 #define my_cpu_offset per_cpu_offset(smp_processor_id())
                                      ^~~~~~~~~~~~~~~~
../include/linux/compiler-gcc.h:58:26: note: in definition of macro ‘RELOC_HIDE’
  (typeof(ptr)) (__ptr + (off));     \
                          ^~~
../include/linux/percpu-defs.h:249:2: note: in expansion of macro ‘SHIFT_PERCPU_PTR’
  SHIFT_PERCPU_PTR(ptr, my_cpu_offset);    \
  ^~~~~~~~~~~~~~~~
../include/asm-generic/percpu.h:34:23: note: in expansion of macro ‘per_cpu_offset’
 #define my_cpu_offset per_cpu_offset(smp_processor_id())
                       ^~~~~~~~~~~~~~
../include/linux/percpu-defs.h:249:24: note: in expansion of macro ‘my_cpu_offset’
  SHIFT_PERCPU_PTR(ptr, my_cpu_offset);    \
                        ^~~~~~~~~~~~~
../include/asm-generic/mmiowb.h:30:26: note: in expansion of macro ‘this_cpu_ptr’
 #define __mmiowb_state() this_cpu_ptr(&__mmiowb_state)
                          ^~~~~~~~~~~~
../include/asm-generic/mmiowb.h:37:28: note: in expansion of macro ‘__mmiowb_state’
  struct mmiowb_state *ms = __mmiowb_state();
                            ^~~~~~~~~~~~~~

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/include/asm/mmiowb.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/include/asm/mmiowb.h b/arch/riscv/include/asm/mmiowb.h
index bb4091ff4a21..0b2333e71fdc 100644
--- a/arch/riscv/include/asm/mmiowb.h
+++ b/arch/riscv/include/asm/mmiowb.h
@@ -9,6 +9,7 @@
  */
 #define mmiowb()	__asm__ __volatile__ ("fence o,w" : : : "memory");
 
+#include <linux/smp.h>
 #include <asm-generic/mmiowb.h>
 
 #endif	/* _ASM_RISCV_MMIOWB_H */
-- 
2.26.2

[PATCH 10/10] riscv: mmiowb: Fix implicit declaration of function 'smp_processor_id'

[Kefeng Wang]

In file included from ./../include/linux/compiler_types.h:68,
                 from <command-line>:
../include/asm-generic/mmiowb.h: In function ‘mmiowb_set_pending’:
../include/asm-generic/percpu.h:34:38: error: implicit declaration of function ‘smp_processor_id’; did you mean ‘raw_smp_processor_id’? [-Werror=implicit-function-declaration]
 #define my_cpu_offset per_cpu_offset(smp_processor_id())
                                      ^~~~~~~~~~~~~~~~
../include/linux/compiler-gcc.h:58:26: note: in definition of macro ‘RELOC_HIDE’
  (typeof(ptr)) (__ptr + (off));     \
                          ^~~
../include/linux/percpu-defs.h:249:2: note: in expansion of macro ‘SHIFT_PERCPU_PTR’
  SHIFT_PERCPU_PTR(ptr, my_cpu_offset);    \
  ^~~~~~~~~~~~~~~~
../include/asm-generic/percpu.h:34:23: note: in expansion of macro ‘per_cpu_offset’
 #define my_cpu_offset per_cpu_offset(smp_processor_id())
                       ^~~~~~~~~~~~~~
../include/linux/percpu-defs.h:249:24: note: in expansion of macro ‘my_cpu_offset’
  SHIFT_PERCPU_PTR(ptr, my_cpu_offset);    \
                        ^~~~~~~~~~~~~
../include/asm-generic/mmiowb.h:30:26: note: in expansion of macro ‘this_cpu_ptr’
 #define __mmiowb_state() this_cpu_ptr(&__mmiowb_state)
                          ^~~~~~~~~~~~
../include/asm-generic/mmiowb.h:37:28: note: in expansion of macro ‘__mmiowb_state’
  struct mmiowb_state *ms = __mmiowb_state();
                            ^~~~~~~~~~~~~~

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/include/asm/mmiowb.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/include/asm/mmiowb.h b/arch/riscv/include/asm/mmiowb.h
index bb4091ff4a21..0b2333e71fdc 100644
--- a/arch/riscv/include/asm/mmiowb.h
+++ b/arch/riscv/include/asm/mmiowb.h
@@ -9,6 +9,7 @@
  */
 #define mmiowb()	__asm__ __volatile__ ("fence o,w" : : : "memory");
 
+#include <linux/smp.h>
 #include <asm-generic/mmiowb.h>
 
 #endif	/* _ASM_RISCV_MMIOWB_H */
-- 
2.26.2

Re: [PATCH 00/10] riscv: make riscv build happier

[Palmer Dabbelt]

On Sun, 10 May 2020 19:19:51 PDT (-0700), wangkefeng.wang@huawei.com wrote:
> When add RISCV arch to huawei build test, there are some build
> issue, let's fix them to make riscv build happier :)
>
> Those patches is rebased on next-20200508.
>
> Kefeng Wang (10):
>   riscv: Fix unmet direct dependencies built based on SOC_VIRT
>   riscv: stacktrace: Fix undefined reference to `walk_stackframe'
>   riscv: Add pgprot_writecombine/device and PAGE_SHARED defination if
>     NOMMU
>   riscv: Fix print_vm_layout build error if NOMMU
>   riscv: Disable ARCH_HAS_DEBUG_WX if NOMMU
>   riscv: Disable ARCH_HAS_DEBUG_VIRTUAL if NOMMU
>   riscv: Make SYS_SUPPORTS_HUGETLBFS depends on MMU
>   riscv: pgtable: Fix __kernel_map_pages build error if NOMMU
>   timer-riscv: Fix undefined riscv_time_val
>   riscv: mmiowb: Fix implicit declaration of function 'smp_processor_id'
>
>  arch/riscv/Kconfig                |  5 +++--
>  arch/riscv/Kconfig.socs           | 17 +++++++++--------
>  arch/riscv/include/asm/mmio.h     |  2 ++
>  arch/riscv/include/asm/mmiowb.h   |  1 +
>  arch/riscv/include/asm/pgtable.h  |  3 +++
>  arch/riscv/kernel/stacktrace.c    |  2 +-
>  arch/riscv/mm/init.c              |  2 +-
>  drivers/clocksource/timer-riscv.c |  1 +
>  8 files changed, 21 insertions(+), 12 deletions(-)

Unless I said otherwise in the patch reviews, these are all on fixes.

Thanks!

Re: [PATCH 00/10] riscv: make riscv build happier

[Palmer Dabbelt]

On Sun, 10 May 2020 19:19:51 PDT (-0700), wangkefeng.wang@huawei.com wrote:
> When add RISCV arch to huawei build test, there are some build
> issue, let's fix them to make riscv build happier :)
>
> Those patches is rebased on next-20200508.
>
> Kefeng Wang (10):
>   riscv: Fix unmet direct dependencies built based on SOC_VIRT
>   riscv: stacktrace: Fix undefined reference to `walk_stackframe'
>   riscv: Add pgprot_writecombine/device and PAGE_SHARED defination if
>     NOMMU
>   riscv: Fix print_vm_layout build error if NOMMU
>   riscv: Disable ARCH_HAS_DEBUG_WX if NOMMU
>   riscv: Disable ARCH_HAS_DEBUG_VIRTUAL if NOMMU
>   riscv: Make SYS_SUPPORTS_HUGETLBFS depends on MMU
>   riscv: pgtable: Fix __kernel_map_pages build error if NOMMU
>   timer-riscv: Fix undefined riscv_time_val
>   riscv: mmiowb: Fix implicit declaration of function 'smp_processor_id'
>
>  arch/riscv/Kconfig                |  5 +++--
>  arch/riscv/Kconfig.socs           | 17 +++++++++--------
>  arch/riscv/include/asm/mmio.h     |  2 ++
>  arch/riscv/include/asm/mmiowb.h   |  1 +
>  arch/riscv/include/asm/pgtable.h  |  3 +++
>  arch/riscv/kernel/stacktrace.c    |  2 +-
>  arch/riscv/mm/init.c              |  2 +-
>  drivers/clocksource/timer-riscv.c |  1 +
>  8 files changed, 21 insertions(+), 12 deletions(-)

Unless I said otherwise in the patch reviews, these are all on fixes.

Thanks!