* [PATCH v3 00/11] perf events patches for improved ARM64 support
@ 2018-03-08 10:58 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: linux-arm-kernel
This patchset adds support for some perf events features,
targeted at ARM64, implemented in a generic fashion.
The two main features are as follows:
- support for arch/vendor/platform pmu events directory structure
- to support this, topic subdirectory support needs to be dropped
- support for parsing standard architecture pmu events
On the back of these, the Cavium ThunderX2, ARM Cortex-A53,
and HiSilicon hip08 JSONs are relocated/added/updated.
In addition, there is a patch to drop mutli-mapfile.csv support and
also a bugfix in jevents.c for an error code value.
Note: Patch #5 will conflict with https://lkml.org/lkml/2018/3/7/183
The simple merge resolution is:
0x00000000420f5160,v1,cavium/thunderx2,core
+0x00000000430f0af0,v1,cavium/thunderx2,core
Differences to v2:
- Change standard arch event matching to use EventName
- update JSONs based on this
- add review tags from Jiri Olsa
Differences to v1:
- Address coding issues from Jiri Olsa in adding arch std event
support (https://lkml.org/lkml/2018/2/6/501)
- add patch to drop topic subdirectory support
- add patch for bug fix in json_events()
- add review tags from Jiri Olsa
Differences to RFC:
- reworked patch for arch standard events
- added arch standard event keyword support
- use some macros to make the code more condense
- use <linux/list_head.h>
- standardised some function names
- updated README
- for patch to support vendor subdir, add check for
unknown dirent type
-add patch to drop mutliple mapfile.csv support
- dealt with new cortex a53 JSONs
John Garry (11):
perf vendor events: drop incomplete multiple mapfile support
perf vendor events: fix error code in json_events()
perf vendor events: drop support for unused topic directories
perf vendor events: add support for pmu events vendor subdirectory
perf vendor events arm64: Relocate ThunderX2 JSON to cavium
subdirectory
perf vendor events arm64: Relocate Cortex A53 JSONs to arm
subdirectory
perf vendor events: add support for arch standard events
perf vendor events arm64: add armv8-recommended.json
perf vendor events arm64: fixup ThunderX2 to use recommended events
perf vendor events arm64: fixup A53 to use recommended events
perf vendor events arm64: add HiSilicon hip08 JSON file
tools/perf/pmu-events/Build | 2 +
tools/perf/pmu-events/README | 15 +-
.../arch/arm64/arm/cortex-a53/branch.json | 25 ++
.../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 8 +
.../arch/arm64/arm/cortex-a53/cache.json | 27 ++
.../arch/arm64/arm/cortex-a53/memory.json | 12 +
.../arch/arm64/arm/cortex-a53/other.json | 28 ++
.../arch/arm64/arm/cortex-a53/pipeline.json | 52 +++
.../pmu-events/arch/arm64/armv8-recommended.json | 452 +++++++++++++++++++++
.../arch/arm64/cavium/thunderx2-imp-def.json | 62 ---
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 32 ++
.../pmu-events/arch/arm64/cortex-a53/branch.json | 27 --
.../perf/pmu-events/arch/arm64/cortex-a53/bus.json | 22 -
.../pmu-events/arch/arm64/cortex-a53/cache.json | 27 --
.../pmu-events/arch/arm64/cortex-a53/memory.json | 22 -
.../pmu-events/arch/arm64/cortex-a53/other.json | 32 --
.../pmu-events/arch/arm64/cortex-a53/pipeline.json | 52 ---
.../arch/arm64/hisilicon/hip08/core-imp-def.json | 122 ++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 5 +-
tools/perf/pmu-events/jevents.c | 287 ++++++++++---
20 files changed, 1014 insertions(+), 297 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/armv8-recommended.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
--
1.9.1
^ permalink raw reply [flat|nested] 47+ messages in thread* [PATCH v3 01/11] perf vendor events: drop incomplete multiple mapfile support
2018-03-08 10:58 ` John Garry
@ 2018-03-08 10:58 ` John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: jolsa, ak, peterz, mingo, acme, alexander.shishkin, namhyung,
wcohen, will.deacon, ganapatrao.kulkarni
Cc: linuxarm, linux-kernel, linux-arm-kernel, zhangshaokun, John Garry
Currently jevents supports multiple mapfiles, but this
is only in the form where mapfile basename starts with
'mapfile.csv'
At the moment, no architectures actually use multiple mapfiles,
so drop the support for now.
This patch also solves a nuisance where, when the mapfile is
edited and the text editor may create a backup, jevents may
use the backup, as shown:
jevents: Many mapfiles? Using pmu-events/arch/arm64/mapfile.csv~, ignoring pmu-events/arch/arm64/mapfile.csv
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
---
tools/perf/pmu-events/README | 5 ++---
tools/perf/pmu-events/jevents.c | 10 ++--------
2 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
index c2ee3e4..2407abc 100644
--- a/tools/perf/pmu-events/README
+++ b/tools/perf/pmu-events/README
@@ -11,9 +11,8 @@ tree tools/perf/pmu-events/arch/foo.
- Regular files with '.json' extension in the name are assumed to be
JSON files, each of which describes a set of PMU events.
- - Regular files with basename starting with 'mapfile.csv' are assumed
- to be a CSV file that maps a specific CPU to its set of PMU events.
- (see below for mapfile format)
+ - The CSV file that maps a specific CPU to its set of PMU events is to
+ be named 'mapfile.csv' (see below for mapfile format).
- Directories are traversed, but all other files are ignored.
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index b578aa2..9e0a21e 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -798,16 +798,10 @@ static int process_one_file(const char *fpath, const struct stat *sb,
* after processing all JSON files (so we can write out the
* mapping table after all PMU events tables).
*
- * TODO: Allow for multiple mapfiles? Punt for now.
*/
if (level == 1 && is_file) {
- if (!strncmp(bname, "mapfile.csv", 11)) {
- if (mapfile) {
- pr_info("%s: Many mapfiles? Using %s, ignoring %s\n",
- prog, mapfile, fpath);
- } else {
- mapfile = strdup(fpath);
- }
+ if (!strcmp(bname, "mapfile.csv")) {
+ mapfile = strdup(fpath);
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v3 01/11] perf vendor events: drop incomplete multiple mapfile support
@ 2018-03-08 10:58 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: linux-arm-kernel
Currently jevents supports multiple mapfiles, but this
is only in the form where mapfile basename starts with
'mapfile.csv'
At the moment, no architectures actually use multiple mapfiles,
so drop the support for now.
This patch also solves a nuisance where, when the mapfile is
edited and the text editor may create a backup, jevents may
use the backup, as shown:
jevents: Many mapfiles? Using pmu-events/arch/arm64/mapfile.csv~, ignoring pmu-events/arch/arm64/mapfile.csv
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
---
tools/perf/pmu-events/README | 5 ++---
tools/perf/pmu-events/jevents.c | 10 ++--------
2 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
index c2ee3e4..2407abc 100644
--- a/tools/perf/pmu-events/README
+++ b/tools/perf/pmu-events/README
@@ -11,9 +11,8 @@ tree tools/perf/pmu-events/arch/foo.
- Regular files with '.json' extension in the name are assumed to be
JSON files, each of which describes a set of PMU events.
- - Regular files with basename starting with 'mapfile.csv' are assumed
- to be a CSV file that maps a specific CPU to its set of PMU events.
- (see below for mapfile format)
+ - The CSV file that maps a specific CPU to its set of PMU events is to
+ be named 'mapfile.csv' (see below for mapfile format).
- Directories are traversed, but all other files are ignored.
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index b578aa2..9e0a21e 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -798,16 +798,10 @@ static int process_one_file(const char *fpath, const struct stat *sb,
* after processing all JSON files (so we can write out the
* mapping table after all PMU events tables).
*
- * TODO: Allow for multiple mapfiles? Punt for now.
*/
if (level == 1 && is_file) {
- if (!strncmp(bname, "mapfile.csv", 11)) {
- if (mapfile) {
- pr_info("%s: Many mapfiles? Using %s, ignoring %s\n",
- prog, mapfile, fpath);
- } else {
- mapfile = strdup(fpath);
- }
+ if (!strcmp(bname, "mapfile.csv")) {
+ mapfile = strdup(fpath);
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [tip:perf/core] perf vendor events: Drop incomplete multiple mapfile support
2018-03-08 10:58 ` John Garry
(?)
@ 2018-03-20 6:21 ` tip-bot for John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: tip-bot for John Garry @ 2018-03-20 6:21 UTC (permalink / raw)
To: linux-tip-commits
Cc: john.garry, ak, mingo, jolsa, wcohen, linux-kernel, will.deacon,
namhyung, acme, alexander.shishkin, zhangshaokun, peterz,
ganapatrao.kulkarni, hpa, tglx
Commit-ID: 4c0ab16052054946b7b28f8b0ceee57c10d64cc7
Gitweb: https://git.kernel.org/tip/4c0ab16052054946b7b28f8b0ceee57c10d64cc7
Author: John Garry <john.garry@huawei.com>
AuthorDate: Thu, 8 Mar 2018 18:58:26 +0800
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Fri, 16 Mar 2018 13:53:55 -0300
perf vendor events: Drop incomplete multiple mapfile support
Currently jevents supports multiple mapfiles, but this is only in the
form where mapfile basename starts with 'mapfile.csv'
At the moment, no architectures actually use multiple mapfiles, so drop
the support for now.
This patch also solves a nuisance where, when the mapfile is edited and
the text editor may create a backup, jevents may use the backup, as
shown:
jevents: Many mapfiles? Using pmu-events/arch/arm64/mapfile.csv~, ignoring pmu-events/arch/arm64/mapfile.csv
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-2-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/README | 5 ++---
tools/perf/pmu-events/jevents.c | 10 ++--------
2 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
index c2ee3e4417fe..2407abc1d441 100644
--- a/tools/perf/pmu-events/README
+++ b/tools/perf/pmu-events/README
@@ -11,9 +11,8 @@ tree tools/perf/pmu-events/arch/foo.
- Regular files with '.json' extension in the name are assumed to be
JSON files, each of which describes a set of PMU events.
- - Regular files with basename starting with 'mapfile.csv' are assumed
- to be a CSV file that maps a specific CPU to its set of PMU events.
- (see below for mapfile format)
+ - The CSV file that maps a specific CPU to its set of PMU events is to
+ be named 'mapfile.csv' (see below for mapfile format).
- Directories are traversed, but all other files are ignored.
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index b578aa26e375..9e0a21e74a67 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -798,16 +798,10 @@ static int process_one_file(const char *fpath, const struct stat *sb,
* after processing all JSON files (so we can write out the
* mapping table after all PMU events tables).
*
- * TODO: Allow for multiple mapfiles? Punt for now.
*/
if (level == 1 && is_file) {
- if (!strncmp(bname, "mapfile.csv", 11)) {
- if (mapfile) {
- pr_info("%s: Many mapfiles? Using %s, ignoring %s\n",
- prog, mapfile, fpath);
- } else {
- mapfile = strdup(fpath);
- }
+ if (!strcmp(bname, "mapfile.csv")) {
+ mapfile = strdup(fpath);
return 0;
}
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v3 02/11] perf vendor events: fix error code in json_events()
2018-03-08 10:58 ` John Garry
@ 2018-03-08 10:58 ` John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: jolsa, ak, peterz, mingo, acme, alexander.shishkin, namhyung,
wcohen, will.deacon, ganapatrao.kulkarni
Cc: linuxarm, linux-kernel, linux-arm-kernel, zhangshaokun, John Garry
When EXPECT macro fails an assertion, the error code is
not properly set after the first loop of tokens in function
json_events().
This is because err is set to the return value from func
function pointer call, which must be 0 to continue to loop,
yet it is not reset for for each loop. I assume that this was
not the intention, so change the code so err is set
appropriately in EXPECT macro itself.
In addition to this, the indention in EXPECT macro is
tidied. The current indention alludes that the 2 statements
following the if statement are in the body, which is not
true.
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
---
tools/perf/pmu-events/jevents.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 9e0a21e..edff989 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -249,9 +249,10 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val)
jsmntok_t *loc = (t); \
if (!(t)->start && (t) > tokens) \
loc = (t) - 1; \
- pr_err("%s:%d: " m ", got %s\n", fn, \
- json_line(map, loc), \
- json_name(t)); \
+ pr_err("%s:%d: " m ", got %s\n", fn, \
+ json_line(map, loc), \
+ json_name(t)); \
+ err = -EIO; \
goto out_free; \
} } while (0)
@@ -416,7 +417,7 @@ int json_events(const char *fn,
char *metric_name, char *metric_group),
void *data)
{
- int err = -EIO;
+ int err;
size_t size;
jsmntok_t *tokens, *tok;
int i, j, len;
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v3 02/11] perf vendor events: fix error code in json_events()
@ 2018-03-08 10:58 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: linux-arm-kernel
When EXPECT macro fails an assertion, the error code is
not properly set after the first loop of tokens in function
json_events().
This is because err is set to the return value from func
function pointer call, which must be 0 to continue to loop,
yet it is not reset for for each loop. I assume that this was
not the intention, so change the code so err is set
appropriately in EXPECT macro itself.
In addition to this, the indention in EXPECT macro is
tidied. The current indention alludes that the 2 statements
following the if statement are in the body, which is not
true.
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
---
tools/perf/pmu-events/jevents.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 9e0a21e..edff989 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -249,9 +249,10 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val)
jsmntok_t *loc = (t); \
if (!(t)->start && (t) > tokens) \
loc = (t) - 1; \
- pr_err("%s:%d: " m ", got %s\n", fn, \
- json_line(map, loc), \
- json_name(t)); \
+ pr_err("%s:%d: " m ", got %s\n", fn, \
+ json_line(map, loc), \
+ json_name(t)); \
+ err = -EIO; \
goto out_free; \
} } while (0)
@@ -416,7 +417,7 @@ int json_events(const char *fn,
char *metric_name, char *metric_group),
void *data)
{
- int err = -EIO;
+ int err;
size_t size;
jsmntok_t *tokens, *tok;
int i, j, len;
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [tip:perf/core] perf vendor events: Fix error code in json_events()
2018-03-08 10:58 ` John Garry
(?)
@ 2018-03-20 6:21 ` tip-bot for John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: tip-bot for John Garry @ 2018-03-20 6:21 UTC (permalink / raw)
To: linux-tip-commits
Cc: acme, zhangshaokun, jolsa, tglx, ganapatrao.kulkarni, namhyung,
peterz, linux-kernel, ak, mingo, john.garry, hpa, wcohen,
will.deacon, alexander.shishkin
Commit-ID: 931ef5dc5c18717d24e5b8d8a968e35638508051
Gitweb: https://git.kernel.org/tip/931ef5dc5c18717d24e5b8d8a968e35638508051
Author: John Garry <john.garry@huawei.com>
AuthorDate: Thu, 8 Mar 2018 18:58:27 +0800
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Fri, 16 Mar 2018 13:54:03 -0300
perf vendor events: Fix error code in json_events()
When EXPECT macro fails an assertion, the error code is not properly set
after the first loop of tokens in function json_events().
This is because err is set to the return value from func function
pointer call, which must be 0 to continue to loop, yet it is not reset
for for each loop. I assume that this was not the intention, so change
the code so err is set appropriately in EXPECT macro itself.
In addition to this, the indention in EXPECT macro is tidied. The
current indention alludes that the 2 statements following the if
statement are in the body, which is not true.
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-3-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/jevents.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 9e0a21e74a67..edff989fbcea 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -249,9 +249,10 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val)
jsmntok_t *loc = (t); \
if (!(t)->start && (t) > tokens) \
loc = (t) - 1; \
- pr_err("%s:%d: " m ", got %s\n", fn, \
- json_line(map, loc), \
- json_name(t)); \
+ pr_err("%s:%d: " m ", got %s\n", fn, \
+ json_line(map, loc), \
+ json_name(t)); \
+ err = -EIO; \
goto out_free; \
} } while (0)
@@ -416,7 +417,7 @@ int json_events(const char *fn,
char *metric_name, char *metric_group),
void *data)
{
- int err = -EIO;
+ int err;
size_t size;
jsmntok_t *tokens, *tok;
int i, j, len;
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v3 03/11] perf vendor events: drop support for unused topic directories
2018-03-08 10:58 ` John Garry
@ 2018-03-08 10:58 ` John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: jolsa, ak, peterz, mingo, acme, alexander.shishkin, namhyung,
wcohen, will.deacon, ganapatrao.kulkarni
Cc: linuxarm, linux-kernel, linux-arm-kernel, zhangshaokun, John Garry
Currently a topic subdirectory is supported in the
pmu-events dir, in the following sample structure:
/arch/platform/subtopic/mysubtopic.json
Upto 256 levels of topic subdirectories are supported. So this
means that JSONs may be located in a topic dir as well as the
platform dir.
This topic subdirectory causes problems if we want to add support
for a vendor dir in the pmu-events structure (in the form
arch/platform/vendor), in that we cannot differentiate between
a vendor dir and a topic dir.
Since the topic dir feature is not used, drop it so it
does not block adding vendor subdirectory support.
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
---
NOTE: There was a bug in this code with how add_topic()
sets topic_level. Also a delimiter could be added in printing
the "topic" in get_topic().
tools/perf/pmu-events/jevents.c | 37 ++++++++++---------------------------
1 file changed, 10 insertions(+), 27 deletions(-)
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index edff989..1d02faf 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -256,25 +256,18 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val)
goto out_free; \
} } while (0)
-#define TOPIC_DEPTH 256
-static char *topic_array[TOPIC_DEPTH];
-static int topic_level;
+static char *topic;
static char *get_topic(void)
{
- char *tp_old, *tp = NULL;
+ char *tp;
int i;
- for (i = 0; i < topic_level + 1; i++) {
- int n;
-
- tp_old = tp;
- n = asprintf(&tp, "%s%s", tp ?: "", topic_array[i]);
- if (n < 0) {
- pr_info("%s: asprintf() error %s\n", prog);
- return NULL;
- }
- free(tp_old);
+ /* tp is free'd in process_one_file() */
+ i = asprintf(&tp, "%s", topic);
+ if (i < 0) {
+ pr_info("%s: asprintf() error %s\n", prog);
+ return NULL;
}
for (i = 0; i < (int) strlen(tp); i++) {
@@ -291,25 +284,15 @@ static char *get_topic(void)
return tp;
}
-static int add_topic(int level, char *bname)
+static int add_topic(char *bname)
{
- char *topic;
-
- level -= 2;
-
- if (level >= TOPIC_DEPTH)
- return -EINVAL;
-
+ free(topic);
topic = strdup(bname);
if (!topic) {
pr_info("%s: strdup() error %s for file %s\n", prog,
strerror(errno), bname);
return -ENOMEM;
}
-
- free(topic_array[topic_level]);
- topic_array[topic_level] = topic;
- topic_level = level;
return 0;
}
@@ -824,7 +807,7 @@ static int process_one_file(const char *fpath, const struct stat *sb,
}
}
- if (level > 1 && add_topic(level, bname))
+ if (level > 1 && add_topic(bname))
return -ENOMEM;
/*
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v3 03/11] perf vendor events: drop support for unused topic directories
@ 2018-03-08 10:58 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: linux-arm-kernel
Currently a topic subdirectory is supported in the
pmu-events dir, in the following sample structure:
/arch/platform/subtopic/mysubtopic.json
Upto 256 levels of topic subdirectories are supported. So this
means that JSONs may be located in a topic dir as well as the
platform dir.
This topic subdirectory causes problems if we want to add support
for a vendor dir in the pmu-events structure (in the form
arch/platform/vendor), in that we cannot differentiate between
a vendor dir and a topic dir.
Since the topic dir feature is not used, drop it so it
does not block adding vendor subdirectory support.
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
---
NOTE: There was a bug in this code with how add_topic()
sets topic_level. Also a delimiter could be added in printing
the "topic" in get_topic().
tools/perf/pmu-events/jevents.c | 37 ++++++++++---------------------------
1 file changed, 10 insertions(+), 27 deletions(-)
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index edff989..1d02faf 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -256,25 +256,18 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val)
goto out_free; \
} } while (0)
-#define TOPIC_DEPTH 256
-static char *topic_array[TOPIC_DEPTH];
-static int topic_level;
+static char *topic;
static char *get_topic(void)
{
- char *tp_old, *tp = NULL;
+ char *tp;
int i;
- for (i = 0; i < topic_level + 1; i++) {
- int n;
-
- tp_old = tp;
- n = asprintf(&tp, "%s%s", tp ?: "", topic_array[i]);
- if (n < 0) {
- pr_info("%s: asprintf() error %s\n", prog);
- return NULL;
- }
- free(tp_old);
+ /* tp is free'd in process_one_file() */
+ i = asprintf(&tp, "%s", topic);
+ if (i < 0) {
+ pr_info("%s: asprintf() error %s\n", prog);
+ return NULL;
}
for (i = 0; i < (int) strlen(tp); i++) {
@@ -291,25 +284,15 @@ static char *get_topic(void)
return tp;
}
-static int add_topic(int level, char *bname)
+static int add_topic(char *bname)
{
- char *topic;
-
- level -= 2;
-
- if (level >= TOPIC_DEPTH)
- return -EINVAL;
-
+ free(topic);
topic = strdup(bname);
if (!topic) {
pr_info("%s: strdup() error %s for file %s\n", prog,
strerror(errno), bname);
return -ENOMEM;
}
-
- free(topic_array[topic_level]);
- topic_array[topic_level] = topic;
- topic_level = level;
return 0;
}
@@ -824,7 +807,7 @@ static int process_one_file(const char *fpath, const struct stat *sb,
}
}
- if (level > 1 && add_topic(level, bname))
+ if (level > 1 && add_topic(bname))
return -ENOMEM;
/*
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [tip:perf/core] perf vendor events: Drop support for unused topic directories
2018-03-08 10:58 ` John Garry
(?)
@ 2018-03-20 6:22 ` tip-bot for John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: tip-bot for John Garry @ 2018-03-20 6:22 UTC (permalink / raw)
To: linux-tip-commits
Cc: alexander.shishkin, acme, zhangshaokun, tglx, john.garry,
ganapatrao.kulkarni, peterz, will.deacon, wcohen, linux-kernel,
hpa, namhyung, ak, mingo, jolsa
Commit-ID: 6f2f2ca3454ec4fa03fcd4507bdd7fe97303065b
Gitweb: https://git.kernel.org/tip/6f2f2ca3454ec4fa03fcd4507bdd7fe97303065b
Author: John Garry <john.garry@huawei.com>
AuthorDate: Thu, 8 Mar 2018 18:58:28 +0800
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Fri, 16 Mar 2018 13:54:09 -0300
perf vendor events: Drop support for unused topic directories
Currently a topic subdirectory is supported in the pmu-events dir, in
the following sample structure: /arch/platform/subtopic/mysubtopic.json
Upto 256 levels of topic subdirectories are supported. So this means
that JSONs may be located in a topic dir as well as the platform dir.
This topic subdirectory causes problems if we want to add support for a
vendor dir in the pmu-events structure (in the form
arch/platform/vendor), in that we cannot differentiate between a vendor
dir and a topic dir.
Since the topic dir feature is not used, drop it so it does not block
adding vendor subdirectory support.
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-4-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/jevents.c | 37 ++++++++++---------------------------
1 file changed, 10 insertions(+), 27 deletions(-)
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index edff989fbcea..1d02fafdc34d 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -256,25 +256,18 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val)
goto out_free; \
} } while (0)
-#define TOPIC_DEPTH 256
-static char *topic_array[TOPIC_DEPTH];
-static int topic_level;
+static char *topic;
static char *get_topic(void)
{
- char *tp_old, *tp = NULL;
+ char *tp;
int i;
- for (i = 0; i < topic_level + 1; i++) {
- int n;
-
- tp_old = tp;
- n = asprintf(&tp, "%s%s", tp ?: "", topic_array[i]);
- if (n < 0) {
- pr_info("%s: asprintf() error %s\n", prog);
- return NULL;
- }
- free(tp_old);
+ /* tp is free'd in process_one_file() */
+ i = asprintf(&tp, "%s", topic);
+ if (i < 0) {
+ pr_info("%s: asprintf() error %s\n", prog);
+ return NULL;
}
for (i = 0; i < (int) strlen(tp); i++) {
@@ -291,25 +284,15 @@ static char *get_topic(void)
return tp;
}
-static int add_topic(int level, char *bname)
+static int add_topic(char *bname)
{
- char *topic;
-
- level -= 2;
-
- if (level >= TOPIC_DEPTH)
- return -EINVAL;
-
+ free(topic);
topic = strdup(bname);
if (!topic) {
pr_info("%s: strdup() error %s for file %s\n", prog,
strerror(errno), bname);
return -ENOMEM;
}
-
- free(topic_array[topic_level]);
- topic_array[topic_level] = topic;
- topic_level = level;
return 0;
}
@@ -824,7 +807,7 @@ static int process_one_file(const char *fpath, const struct stat *sb,
}
}
- if (level > 1 && add_topic(level, bname))
+ if (level > 1 && add_topic(bname))
return -ENOMEM;
/*
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v3 04/11] perf vendor events: add support for pmu events vendor subdirectory
2018-03-08 10:58 ` John Garry
@ 2018-03-08 10:58 ` John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: jolsa, ak, peterz, mingo, acme, alexander.shishkin, namhyung,
wcohen, will.deacon, ganapatrao.kulkarni
Cc: linuxarm, linux-kernel, linux-arm-kernel, zhangshaokun, John Garry
For some architectures (like arm), it is required to support
a vendor subdirectory and not locate all the JSONs for a
specific vendor in the same folder.
This is because all the events for the same vendor will be
placed in the same pmu events table, which may cause conflict.
This conflict would be in the instance that a vendor's custom
implemented events do have the same meaning on different platforms,
so events in the pmu table would conflict. In addition, per list
command may show events which are not even supported for a given
platform.
This patch adds support for a arch/vendor/platform directory
hierarchy, while maintaining backwards-compatibility for existing
arch/platform structure. In this, each platform would always have
its own pmu events table.
In generated file pmu_events.c, each platform table name is in
the format pme{_vendor}_platform, like this:
struct pmu_events_map pmu_events_map[] = {
{
.cpuid = "0x00000000420f5160",
.version = "v1",
.type = "core",
.table = pme_cavium_thunderx2
},
{
.cpuid = 0,
.version = 0,
.type = 0,
.table = 0,
},
};
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
---
tools/perf/pmu-events/README | 4 +++
tools/perf/pmu-events/jevents.c | 64 +++++++++++++++++++++++++++++++++++++----
2 files changed, 62 insertions(+), 6 deletions(-)
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
index 2407abc..655286f 100644
--- a/tools/perf/pmu-events/README
+++ b/tools/perf/pmu-events/README
@@ -28,6 +28,10 @@ sub directory. Thus for the Silvermont X86 CPU:
Cache.json Memory.json Virtual-Memory.json
Frontend.json Pipeline.json
+The JSONs folder for a CPU model/family may be placed in the root arch
+folder, or may be placed in a vendor sub-folder under the arch folder
+for instances where the arch and vendor are not the same.
+
Using the JSON files and the mapfile, 'jevents' generates the C source file,
'pmu-events.c', which encodes the two sets of tables:
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 1d02faf..7b9e210 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -572,7 +572,7 @@ static char *file_name_to_table_name(char *fname)
* Derive rest of table name from basename of the JSON file,
* replacing hyphens and stripping out .json suffix.
*/
- n = asprintf(&tblname, "pme_%s", basename(fname));
+ n = asprintf(&tblname, "pme_%s", fname);
if (n < 0) {
pr_info("%s: asprintf() error %s for file %s\n", prog,
strerror(errno), fname);
@@ -582,7 +582,7 @@ static char *file_name_to_table_name(char *fname)
for (i = 0; i < strlen(tblname); i++) {
c = tblname[i];
- if (c == '-')
+ if (c == '-' || c == '/')
tblname[i] = '_';
else if (c == '.') {
tblname[i] = '\0';
@@ -739,25 +739,77 @@ static int get_maxfds(void)
static FILE *eventsfp;
static char *mapfile;
+static int is_leaf_dir(const char *fpath)
+{
+ DIR *d;
+ struct dirent *dir;
+ int res = 1;
+
+ d = opendir(fpath);
+ if (!d)
+ return 0;
+
+ while ((dir = readdir(d)) != NULL) {
+ if (dir->d_type == DT_DIR && dir->d_name[0] != '.') {
+ res = 0;
+ break;
+ } else if (dir->d_type == DT_UNKNOWN) {
+ char path[PATH_MAX];
+ struct stat st;
+
+ sprintf(path, "%s/%s", fpath, dir->d_name);
+ if (stat(path, &st))
+ break;
+
+ if (S_ISDIR(st.st_mode)) {
+ res = 0;
+ break;
+ }
+ }
+ }
+
+ closedir(d);
+
+ return res;
+}
+
static int process_one_file(const char *fpath, const struct stat *sb,
int typeflag, struct FTW *ftwbuf)
{
- char *tblname, *bname = (char *) fpath + ftwbuf->base;
+ char *tblname, *bname;
int is_dir = typeflag == FTW_D;
int is_file = typeflag == FTW_F;
int level = ftwbuf->level;
int err = 0;
+ if (level == 2 && is_dir) {
+ /*
+ * For level 2 directory, bname will include parent name,
+ * like vendor/platform. So search back from platform dir
+ * to find this.
+ */
+ bname = (char *) fpath + ftwbuf->base - 2;
+ for (;;) {
+ if (*bname == '/')
+ break;
+ bname--;
+ }
+ bname++;
+ } else
+ bname = (char *) fpath + ftwbuf->base;
+
pr_debug("%s %d %7jd %-20s %s\n",
is_file ? "f" : is_dir ? "d" : "x",
level, sb->st_size, bname, fpath);
- /* base dir */
- if (level == 0)
+ /* base dir or too deep */
+ if (level == 0 || level > 3)
return 0;
+
/* model directory, reset topic */
- if (level == 1 && is_dir) {
+ if ((level == 1 && is_dir && is_leaf_dir(fpath)) ||
+ (level == 2 && is_dir)) {
if (close_table)
print_events_table_suffix(eventsfp);
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v3 04/11] perf vendor events: add support for pmu events vendor subdirectory
@ 2018-03-08 10:58 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: linux-arm-kernel
For some architectures (like arm), it is required to support
a vendor subdirectory and not locate all the JSONs for a
specific vendor in the same folder.
This is because all the events for the same vendor will be
placed in the same pmu events table, which may cause conflict.
This conflict would be in the instance that a vendor's custom
implemented events do have the same meaning on different platforms,
so events in the pmu table would conflict. In addition, per list
command may show events which are not even supported for a given
platform.
This patch adds support for a arch/vendor/platform directory
hierarchy, while maintaining backwards-compatibility for existing
arch/platform structure. In this, each platform would always have
its own pmu events table.
In generated file pmu_events.c, each platform table name is in
the format pme{_vendor}_platform, like this:
struct pmu_events_map pmu_events_map[] = {
{
.cpuid = "0x00000000420f5160",
.version = "v1",
.type = "core",
.table = pme_cavium_thunderx2
},
{
.cpuid = 0,
.version = 0,
.type = 0,
.table = 0,
},
};
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
---
tools/perf/pmu-events/README | 4 +++
tools/perf/pmu-events/jevents.c | 64 +++++++++++++++++++++++++++++++++++++----
2 files changed, 62 insertions(+), 6 deletions(-)
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
index 2407abc..655286f 100644
--- a/tools/perf/pmu-events/README
+++ b/tools/perf/pmu-events/README
@@ -28,6 +28,10 @@ sub directory. Thus for the Silvermont X86 CPU:
Cache.json Memory.json Virtual-Memory.json
Frontend.json Pipeline.json
+The JSONs folder for a CPU model/family may be placed in the root arch
+folder, or may be placed in a vendor sub-folder under the arch folder
+for instances where the arch and vendor are not the same.
+
Using the JSON files and the mapfile, 'jevents' generates the C source file,
'pmu-events.c', which encodes the two sets of tables:
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 1d02faf..7b9e210 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -572,7 +572,7 @@ static char *file_name_to_table_name(char *fname)
* Derive rest of table name from basename of the JSON file,
* replacing hyphens and stripping out .json suffix.
*/
- n = asprintf(&tblname, "pme_%s", basename(fname));
+ n = asprintf(&tblname, "pme_%s", fname);
if (n < 0) {
pr_info("%s: asprintf() error %s for file %s\n", prog,
strerror(errno), fname);
@@ -582,7 +582,7 @@ static char *file_name_to_table_name(char *fname)
for (i = 0; i < strlen(tblname); i++) {
c = tblname[i];
- if (c == '-')
+ if (c == '-' || c == '/')
tblname[i] = '_';
else if (c == '.') {
tblname[i] = '\0';
@@ -739,25 +739,77 @@ static int get_maxfds(void)
static FILE *eventsfp;
static char *mapfile;
+static int is_leaf_dir(const char *fpath)
+{
+ DIR *d;
+ struct dirent *dir;
+ int res = 1;
+
+ d = opendir(fpath);
+ if (!d)
+ return 0;
+
+ while ((dir = readdir(d)) != NULL) {
+ if (dir->d_type == DT_DIR && dir->d_name[0] != '.') {
+ res = 0;
+ break;
+ } else if (dir->d_type == DT_UNKNOWN) {
+ char path[PATH_MAX];
+ struct stat st;
+
+ sprintf(path, "%s/%s", fpath, dir->d_name);
+ if (stat(path, &st))
+ break;
+
+ if (S_ISDIR(st.st_mode)) {
+ res = 0;
+ break;
+ }
+ }
+ }
+
+ closedir(d);
+
+ return res;
+}
+
static int process_one_file(const char *fpath, const struct stat *sb,
int typeflag, struct FTW *ftwbuf)
{
- char *tblname, *bname = (char *) fpath + ftwbuf->base;
+ char *tblname, *bname;
int is_dir = typeflag == FTW_D;
int is_file = typeflag == FTW_F;
int level = ftwbuf->level;
int err = 0;
+ if (level == 2 && is_dir) {
+ /*
+ * For level 2 directory, bname will include parent name,
+ * like vendor/platform. So search back from platform dir
+ * to find this.
+ */
+ bname = (char *) fpath + ftwbuf->base - 2;
+ for (;;) {
+ if (*bname == '/')
+ break;
+ bname--;
+ }
+ bname++;
+ } else
+ bname = (char *) fpath + ftwbuf->base;
+
pr_debug("%s %d %7jd %-20s %s\n",
is_file ? "f" : is_dir ? "d" : "x",
level, sb->st_size, bname, fpath);
- /* base dir */
- if (level == 0)
+ /* base dir or too deep */
+ if (level == 0 || level > 3)
return 0;
+
/* model directory, reset topic */
- if (level == 1 && is_dir) {
+ if ((level == 1 && is_dir && is_leaf_dir(fpath)) ||
+ (level == 2 && is_dir)) {
if (close_table)
print_events_table_suffix(eventsfp);
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v3 04/11] perf vendor events: add support for pmu events vendor subdirectory
2018-03-08 10:58 ` John Garry
@ 2018-03-12 18:28 ` Arnaldo Carvalho de Melo
-1 siblings, 0 replies; 47+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-12 18:28 UTC (permalink / raw)
To: John Garry
Cc: jolsa, ak, peterz, mingo, alexander.shishkin, namhyung, wcohen,
will.deacon, ganapatrao.kulkarni, linuxarm, linux-kernel,
linux-arm-kernel, zhangshaokun
Em Thu, Mar 08, 2018 at 06:58:29PM +0800, John Garry escreveu:
> index 1d02faf..7b9e210 100644
> --- a/tools/perf/pmu-events/jevents.c
> @@ -739,25 +739,77 @@ static int get_maxfds(void)
> static FILE *eventsfp;
> static char *mapfile;
>
> +static int is_leaf_dir(const char *fpath)
> +{
> + DIR *d;
> + struct dirent *dir;
> + int res = 1;
> +
> + d = opendir(fpath);
> + if (!d)
> + return 0;
> +
> + while ((dir = readdir(d)) != NULL) {
> + if (dir->d_type == DT_DIR && dir->d_name[0] != '.') {
> + res = 0;
> + break;
> + } else if (dir->d_type == DT_UNKNOWN) {
> + char path[PATH_MAX];
You forgot to add:
#include <limits.h>
Which broke the build on at least:
[root@jouet ~]# time dm
1 13.78 alpine:3.4 : FAIL gcc (Alpine 5.3.0) 5.3.0
2 14.40 alpine:3.5 : FAIL gcc (Alpine 6.2.1) 6.2.1 20160822
3 13.59 alpine:3.6 : FAIL gcc (Alpine 6.3.0) 6.3.0
4 14.94 alpine:3.7 : FAIL gcc (Alpine 6.4.0) 6.4.0
5 14.70 alpine:edge : FAIL gcc (Alpine 6.4.0) 6.4.0
6: amazonlinux:1^C^C
I just fixed it.
build failure:
MKDIR /tmp/build/perf/pmu-events/
HOSTCC /tmp/build/perf/pmu-events/json.o
MKDIR /tmp/build/perf/pmu-events/
HOSTCC /tmp/build/perf/pmu-events/jsmn.o
HOSTCC /tmp/build/perf/pmu-events/jevents.o
LD /tmp/build/perf/libtraceevent-in.o
LINK /tmp/build/perf/libtraceevent.a
LD /tmp/build/perf/libsubcmd-in.o
CC /tmp/build/perf/plugin_jbd2.o
CC /tmp/build/perf/plugin_hrtimer.o
pmu-events/jevents.c: In function 'is_leaf_dir':
pmu-events/jevents.c:879:14: error: 'PATH_MAX' undeclared (first use in this function)
char path[PATH_MAX];
^~~~~~~~
pmu-events/jevents.c:879:14: note: each undeclared identifier is reported only once for each function it appears in
AR /tmp/build/perf/libsubcmd.a
mv: can't rename '/tmp/build/perf/pmu-events/.jevents.o.tmp': No such file or directory
make[3]: *** [/git/linux/tools/build/Makefile.build:96: /tmp/build/perf/pmu-events/jevents.o] Error 1
CC /tmp/build/perf/plugin_kmem.o
LD /tmp/build/perf/plugin_jbd2-in.o
make[2]: *** [Makefile.perf:501: /tmp/build/perf/pmu-events/jevents-in.o] Error 2
make[2]: *** Waiting for unfinished jobs....
GEN perf-archive
CC /tmp/build/perf/plugin_kvm.o
^ permalink raw reply [flat|nested] 47+ messages in thread* [PATCH v3 04/11] perf vendor events: add support for pmu events vendor subdirectory
@ 2018-03-12 18:28 ` Arnaldo Carvalho de Melo
0 siblings, 0 replies; 47+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-12 18:28 UTC (permalink / raw)
To: linux-arm-kernel
Em Thu, Mar 08, 2018 at 06:58:29PM +0800, John Garry escreveu:
> index 1d02faf..7b9e210 100644
> --- a/tools/perf/pmu-events/jevents.c
> @@ -739,25 +739,77 @@ static int get_maxfds(void)
> static FILE *eventsfp;
> static char *mapfile;
>
> +static int is_leaf_dir(const char *fpath)
> +{
> + DIR *d;
> + struct dirent *dir;
> + int res = 1;
> +
> + d = opendir(fpath);
> + if (!d)
> + return 0;
> +
> + while ((dir = readdir(d)) != NULL) {
> + if (dir->d_type == DT_DIR && dir->d_name[0] != '.') {
> + res = 0;
> + break;
> + } else if (dir->d_type == DT_UNKNOWN) {
> + char path[PATH_MAX];
You forgot to add:
#include <limits.h>
Which broke the build on at least:
[root at jouet ~]# time dm
1 13.78 alpine:3.4 : FAIL gcc (Alpine 5.3.0) 5.3.0
2 14.40 alpine:3.5 : FAIL gcc (Alpine 6.2.1) 6.2.1 20160822
3 13.59 alpine:3.6 : FAIL gcc (Alpine 6.3.0) 6.3.0
4 14.94 alpine:3.7 : FAIL gcc (Alpine 6.4.0) 6.4.0
5 14.70 alpine:edge : FAIL gcc (Alpine 6.4.0) 6.4.0
6: amazonlinux:1^C^C
I just fixed it.
build failure:
MKDIR /tmp/build/perf/pmu-events/
HOSTCC /tmp/build/perf/pmu-events/json.o
MKDIR /tmp/build/perf/pmu-events/
HOSTCC /tmp/build/perf/pmu-events/jsmn.o
HOSTCC /tmp/build/perf/pmu-events/jevents.o
LD /tmp/build/perf/libtraceevent-in.o
LINK /tmp/build/perf/libtraceevent.a
LD /tmp/build/perf/libsubcmd-in.o
CC /tmp/build/perf/plugin_jbd2.o
CC /tmp/build/perf/plugin_hrtimer.o
pmu-events/jevents.c: In function 'is_leaf_dir':
pmu-events/jevents.c:879:14: error: 'PATH_MAX' undeclared (first use in this function)
char path[PATH_MAX];
^~~~~~~~
pmu-events/jevents.c:879:14: note: each undeclared identifier is reported only once for each function it appears in
AR /tmp/build/perf/libsubcmd.a
mv: can't rename '/tmp/build/perf/pmu-events/.jevents.o.tmp': No such file or directory
make[3]: *** [/git/linux/tools/build/Makefile.build:96: /tmp/build/perf/pmu-events/jevents.o] Error 1
CC /tmp/build/perf/plugin_kmem.o
LD /tmp/build/perf/plugin_jbd2-in.o
make[2]: *** [Makefile.perf:501: /tmp/build/perf/pmu-events/jevents-in.o] Error 2
make[2]: *** Waiting for unfinished jobs....
GEN perf-archive
CC /tmp/build/perf/plugin_kvm.o
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [PATCH v3 04/11] perf vendor events: add support for pmu events vendor subdirectory
2018-03-12 18:28 ` Arnaldo Carvalho de Melo
@ 2018-03-13 9:36 ` John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-13 9:36 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo
Cc: jolsa, ak, peterz, mingo, alexander.shishkin, namhyung, wcohen,
will.deacon, ganapatrao.kulkarni, linuxarm, linux-kernel,
linux-arm-kernel, zhangshaokun
On 12/03/2018 18:28, Arnaldo Carvalho de Melo wrote:
> Em Thu, Mar 08, 2018 at 06:58:29PM +0800, John Garry escreveu:
>> index 1d02faf..7b9e210 100644
>> --- a/tools/perf/pmu-events/jevents.c
>> @@ -739,25 +739,77 @@ static int get_maxfds(void)
>> static FILE *eventsfp;
>> static char *mapfile;
>>
>> +static int is_leaf_dir(const char *fpath)
>> +{
>> + DIR *d;
>> + struct dirent *dir;
>> + int res = 1;
>> +
>> + d = opendir(fpath);
>> + if (!d)
>> + return 0;
>> +
>> + while ((dir = readdir(d)) != NULL) {
>> + if (dir->d_type == DT_DIR && dir->d_name[0] != '.') {
>> + res = 0;
>> + break;
>> + } else if (dir->d_type == DT_UNKNOWN) {
>> + char path[PATH_MAX];
>
>
> You forgot to add:
>
> #include <limits.h>
>
> Which broke the build on at least:
>
> [root@jouet ~]# time dm
> 1 13.78 alpine:3.4 : FAIL gcc (Alpine 5.3.0) 5.3.0
> 2 14.40 alpine:3.5 : FAIL gcc (Alpine 6.2.1) 6.2.1 20160822
> 3 13.59 alpine:3.6 : FAIL gcc (Alpine 6.3.0) 6.3.0
> 4 14.94 alpine:3.7 : FAIL gcc (Alpine 6.4.0) 6.4.0
> 5 14.70 alpine:edge : FAIL gcc (Alpine 6.4.0) 6.4.0
> 6: amazonlinux:1^C^C
>
> I just fixed it.
>
> build failure:
>
> MKDIR /tmp/build/perf/pmu-events/
> HOSTCC /tmp/build/perf/pmu-events/json.o
> MKDIR /tmp/build/perf/pmu-events/
> HOSTCC /tmp/build/perf/pmu-events/jsmn.o
> HOSTCC /tmp/build/perf/pmu-events/jevents.o
> LD /tmp/build/perf/libtraceevent-in.o
> LINK /tmp/build/perf/libtraceevent.a
> LD /tmp/build/perf/libsubcmd-in.o
> CC /tmp/build/perf/plugin_jbd2.o
> CC /tmp/build/perf/plugin_hrtimer.o
> pmu-events/jevents.c: In function 'is_leaf_dir':
> pmu-events/jevents.c:879:14: error: 'PATH_MAX' undeclared (first use in this function)
> char path[PATH_MAX];
> ^~~~~~~~
> pmu-events/jevents.c:879:14: note: each undeclared identifier is reported only once for each function it appears in
> AR /tmp/build/perf/libsubcmd.a
> mv: can't rename '/tmp/build/perf/pmu-events/.jevents.o.tmp': No such file or directory
> make[3]: *** [/git/linux/tools/build/Makefile.build:96: /tmp/build/perf/pmu-events/jevents.o] Error 1
> CC /tmp/build/perf/plugin_kmem.o
> LD /tmp/build/perf/plugin_jbd2-in.o
> make[2]: *** [Makefile.perf:501: /tmp/build/perf/pmu-events/jevents-in.o] Error 2
> make[2]: *** Waiting for unfinished jobs....
> GEN perf-archive
> CC /tmp/build/perf/plugin_kvm.o
>
>
> .
>
OK, thanks for the notification.
I will check this.
All the best,
John
^ permalink raw reply [flat|nested] 47+ messages in thread* [PATCH v3 04/11] perf vendor events: add support for pmu events vendor subdirectory
@ 2018-03-13 9:36 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-13 9:36 UTC (permalink / raw)
To: linux-arm-kernel
On 12/03/2018 18:28, Arnaldo Carvalho de Melo wrote:
> Em Thu, Mar 08, 2018 at 06:58:29PM +0800, John Garry escreveu:
>> index 1d02faf..7b9e210 100644
>> --- a/tools/perf/pmu-events/jevents.c
>> @@ -739,25 +739,77 @@ static int get_maxfds(void)
>> static FILE *eventsfp;
>> static char *mapfile;
>>
>> +static int is_leaf_dir(const char *fpath)
>> +{
>> + DIR *d;
>> + struct dirent *dir;
>> + int res = 1;
>> +
>> + d = opendir(fpath);
>> + if (!d)
>> + return 0;
>> +
>> + while ((dir = readdir(d)) != NULL) {
>> + if (dir->d_type == DT_DIR && dir->d_name[0] != '.') {
>> + res = 0;
>> + break;
>> + } else if (dir->d_type == DT_UNKNOWN) {
>> + char path[PATH_MAX];
>
>
> You forgot to add:
>
> #include <limits.h>
>
> Which broke the build on at least:
>
> [root at jouet ~]# time dm
> 1 13.78 alpine:3.4 : FAIL gcc (Alpine 5.3.0) 5.3.0
> 2 14.40 alpine:3.5 : FAIL gcc (Alpine 6.2.1) 6.2.1 20160822
> 3 13.59 alpine:3.6 : FAIL gcc (Alpine 6.3.0) 6.3.0
> 4 14.94 alpine:3.7 : FAIL gcc (Alpine 6.4.0) 6.4.0
> 5 14.70 alpine:edge : FAIL gcc (Alpine 6.4.0) 6.4.0
> 6: amazonlinux:1^C^C
>
> I just fixed it.
>
> build failure:
>
> MKDIR /tmp/build/perf/pmu-events/
> HOSTCC /tmp/build/perf/pmu-events/json.o
> MKDIR /tmp/build/perf/pmu-events/
> HOSTCC /tmp/build/perf/pmu-events/jsmn.o
> HOSTCC /tmp/build/perf/pmu-events/jevents.o
> LD /tmp/build/perf/libtraceevent-in.o
> LINK /tmp/build/perf/libtraceevent.a
> LD /tmp/build/perf/libsubcmd-in.o
> CC /tmp/build/perf/plugin_jbd2.o
> CC /tmp/build/perf/plugin_hrtimer.o
> pmu-events/jevents.c: In function 'is_leaf_dir':
> pmu-events/jevents.c:879:14: error: 'PATH_MAX' undeclared (first use in this function)
> char path[PATH_MAX];
> ^~~~~~~~
> pmu-events/jevents.c:879:14: note: each undeclared identifier is reported only once for each function it appears in
> AR /tmp/build/perf/libsubcmd.a
> mv: can't rename '/tmp/build/perf/pmu-events/.jevents.o.tmp': No such file or directory
> make[3]: *** [/git/linux/tools/build/Makefile.build:96: /tmp/build/perf/pmu-events/jevents.o] Error 1
> CC /tmp/build/perf/plugin_kmem.o
> LD /tmp/build/perf/plugin_jbd2-in.o
> make[2]: *** [Makefile.perf:501: /tmp/build/perf/pmu-events/jevents-in.o] Error 2
> make[2]: *** Waiting for unfinished jobs....
> GEN perf-archive
> CC /tmp/build/perf/plugin_kvm.o
>
>
> .
>
OK, thanks for the notification.
I will check this.
All the best,
John
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] perf vendor events: fix processing for xfs
@ 2018-03-14 17:10 ` John Garry
2018-03-14 17:42 ` Sukadev Bhattiprolu
` (2 more replies)
0 siblings, 3 replies; 47+ messages in thread
From: John Garry @ 2018-03-14 17:10 UTC (permalink / raw)
To: peterz, mingo, acme, alexander.shishkin, jolsa, namhyung, ak,
wcohen, sukadev
Cc: linux-kernel, linuxarm, John Garry
In the recently introduced support for vendor subdirectory,
the checking for directory entries under xfs (or any other fs
which does not support dirent.d_type) is missing the check
for links for current and parent directory. This can result
in a broken pmu_events.c being generated.
Fix this by adding the appropriate check in is_leaf_dir().
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: John Garry <john.garry@huawei.com>
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 1c01844..db3a594 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -873,7 +873,10 @@ static int is_leaf_dir(const char *fpath)
return 0;
while ((dir = readdir(d)) != NULL) {
- if (dir->d_type == DT_DIR && dir->d_name[0] != '.') {
+ if (!strcmp(dir->d_name, ".") || !strcmp(dir->d_name, ".."))
+ continue;
+
+ if (dir->d_type == DT_DIR) {
res = 0;
break;
} else if (dir->d_type == DT_UNKNOWN) {
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH] perf vendor events: fix processing for xfs
2018-03-14 17:10 ` [PATCH] perf vendor events: fix processing for xfs John Garry
@ 2018-03-14 17:42 ` Sukadev Bhattiprolu
2018-03-14 18:53 ` Arnaldo Carvalho de Melo
2018-03-20 6:22 ` [tip:perf/core] perf vendor events: Add support for pmu events vendor subdirectory tip-bot for John Garry
2 siblings, 0 replies; 47+ messages in thread
From: Sukadev Bhattiprolu @ 2018-03-14 17:42 UTC (permalink / raw)
To: John Garry
Cc: peterz, mingo, acme, alexander.shishkin, jolsa, namhyung, ak,
wcohen, linux-kernel, linuxarm
John Garry [john.garry@huawei.com] wrote:
> In the recently introduced support for vendor subdirectory,
> the checking for directory entries under xfs (or any other fs
> which does not support dirent.d_type) is missing the check
> for links for current and parent directory. This can result
> in a broken pmu_events.c being generated.
I run into the problem on a 4.15-based kernel/xfs but not on a
3.10-based kernel! Have not investigated, but this fix is good.
>
> Fix this by adding the appropriate check in is_leaf_dir().
>
> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
> Signed-off-by: John Garry <john.garry@huawei.com>
Tested-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Thanks John.
Sukadev
>
> diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
> index 1c01844..db3a594 100644
> --- a/tools/perf/pmu-events/jevents.c
> +++ b/tools/perf/pmu-events/jevents.c
> @@ -873,7 +873,10 @@ static int is_leaf_dir(const char *fpath)
> return 0;
>
> while ((dir = readdir(d)) != NULL) {
> - if (dir->d_type == DT_DIR && dir->d_name[0] != '.') {
> + if (!strcmp(dir->d_name, ".") || !strcmp(dir->d_name, ".."))
> + continue;
> +
> + if (dir->d_type == DT_DIR) {
> res = 0;
> break;
> } else if (dir->d_type == DT_UNKNOWN) {
> --
> 1.9.1
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [PATCH] perf vendor events: fix processing for xfs
2018-03-14 17:10 ` [PATCH] perf vendor events: fix processing for xfs John Garry
2018-03-14 17:42 ` Sukadev Bhattiprolu
@ 2018-03-14 18:53 ` Arnaldo Carvalho de Melo
2018-03-14 19:39 ` John Garry
2018-03-20 6:22 ` [tip:perf/core] perf vendor events: Add support for pmu events vendor subdirectory tip-bot for John Garry
2 siblings, 1 reply; 47+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-14 18:53 UTC (permalink / raw)
To: John Garry
Cc: peterz, mingo, alexander.shishkin, jolsa, namhyung, ak, wcohen,
sukadev, linux-kernel, linuxarm
Em Thu, Mar 15, 2018 at 01:10:52AM +0800, John Garry escreveu:
> In the recently introduced support for vendor subdirectory,
> the checking for directory entries under xfs (or any other fs
> which does not support dirent.d_type) is missing the check
> for links for current and parent directory. This can result
> in a broken pmu_events.c being generated.
>
> Fix this by adding the appropriate check in is_leaf_dir().
So I'll lookup the patch that introduced the patch and squash this one
with it, so that we don't break 'git bisect' on ppc.
- Arnaldo
> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
> Signed-off-by: John Garry <john.garry@huawei.com>
>
> diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
> index 1c01844..db3a594 100644
> --- a/tools/perf/pmu-events/jevents.c
> +++ b/tools/perf/pmu-events/jevents.c
> @@ -873,7 +873,10 @@ static int is_leaf_dir(const char *fpath)
> return 0;
>
> while ((dir = readdir(d)) != NULL) {
> - if (dir->d_type == DT_DIR && dir->d_name[0] != '.') {
> + if (!strcmp(dir->d_name, ".") || !strcmp(dir->d_name, ".."))
> + continue;
> +
> + if (dir->d_type == DT_DIR) {
> res = 0;
> break;
> } else if (dir->d_type == DT_UNKNOWN) {
> --
> 1.9.1
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [PATCH] perf vendor events: fix processing for xfs
2018-03-14 18:53 ` Arnaldo Carvalho de Melo
@ 2018-03-14 19:39 ` John Garry
2018-03-14 20:26 ` Arnaldo Carvalho de Melo
0 siblings, 1 reply; 47+ messages in thread
From: John Garry @ 2018-03-14 19:39 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo
Cc: peterz, mingo, alexander.shishkin, jolsa, namhyung, ak, wcohen,
sukadev, linux-kernel, linuxarm
On 14/03/2018 18:53, Arnaldo Carvalho de Melo wrote:
> Em Thu, Mar 15, 2018 at 01:10:52AM +0800, John Garry escreveu:
>> In the recently introduced support for vendor subdirectory,
>> the checking for directory entries under xfs (or any other fs
>> which does not support dirent.d_type) is missing the check
>> for links for current and parent directory. This can result
>> in a broken pmu_events.c being generated.
>>
>> Fix this by adding the appropriate check in is_leaf_dir().
>
> So I'll lookup the patch that introduced the patch and squash this one
> with it, so that we don't break 'git bisect' on ppc.
Right, so it's going to be "perf vendor events: add support for pmu
events vendor subdirectory".
BTW, I don't think it's specifically ppc which was broken, but just when
building from xfs.
Much appreciated,
John
>
> - Arnaldo
>
>> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
>> Signed-off-by: John Garry <john.garry@huawei.com>
>>
>> diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
>> index 1c01844..db3a594 100644
>> --- a/tools/perf/pmu-events/jevents.c
>> +++ b/tools/perf/pmu-events/jevents.c
>> @@ -873,7 +873,10 @@ static int is_leaf_dir(const char *fpath)
>> return 0;
>>
>> while ((dir = readdir(d)) != NULL) {
>> - if (dir->d_type == DT_DIR && dir->d_name[0] != '.') {
>> + if (!strcmp(dir->d_name, ".") || !strcmp(dir->d_name, ".."))
>> + continue;
>> +
>> + if (dir->d_type == DT_DIR) {
>> res = 0;
>> break;
>> } else if (dir->d_type == DT_UNKNOWN) {
>> --
>> 1.9.1
>
> .
>
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [PATCH] perf vendor events: fix processing for xfs
2018-03-14 19:39 ` John Garry
@ 2018-03-14 20:26 ` Arnaldo Carvalho de Melo
2018-03-14 20:58 ` John Garry
0 siblings, 1 reply; 47+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-14 20:26 UTC (permalink / raw)
To: John Garry
Cc: peterz, mingo, alexander.shishkin, jolsa, namhyung, ak, wcohen,
sukadev, linux-kernel, linuxarm
Em Wed, Mar 14, 2018 at 07:39:25PM +0000, John Garry escreveu:
> On 14/03/2018 18:53, Arnaldo Carvalho de Melo wrote:
> > Em Thu, Mar 15, 2018 at 01:10:52AM +0800, John Garry escreveu:
> > > In the recently introduced support for vendor subdirectory,
> > > the checking for directory entries under xfs (or any other fs
> > > which does not support dirent.d_type) is missing the check
> > > for links for current and parent directory. This can result
> > > in a broken pmu_events.c being generated.
> > >
> > > Fix this by adding the appropriate check in is_leaf_dir().
> >
> > So I'll lookup the patch that introduced the patch and squash this one
> > with it, so that we don't break 'git bisect' on ppc.
>
> Right, so it's going to be "perf vendor events: add support for pmu events
> vendor subdirectory".
>
> BTW, I don't think it's specifically ppc which was broken, but just when
> building from xfs.
>
> Much appreciated,
> John
This is the ammended cset, and yes, I mentioned just XFS not ppc, added
Sukadev to the CC list and the link to your patch that he tested. Also
stamped his Tested-by there.
This will all go again the container build test set before a new pull
req to Ingo, where I'll avoid sending the previous 31 patches to the
mailing list, just the ones that came after it, as perf/core keeps
growing :-)
- Arnaldo
commit d24081387a00d2e10789eb012429144c549598be
Author: John Garry <john.garry@huawei.com>
Date: Thu Mar 8 18:58:29 2018 +0800
perf vendor events: Add support for pmu events vendor subdirectory
For some architectures (like arm), it is required to support a vendor
subdirectory and not locate all the JSONs for a specific vendor in the
same folder.
This is because all the events for the same vendor will be placed in the
same pmu events table, which may cause conflict. This conflict would be
in the instance that a vendor's custom implemented events do have the
same meaning on different platforms, so events in the pmu table would
conflict. In addition, per list command may show events which are not
even supported for a given platform.
This patch adds support for a arch/vendor/platform directory hierarchy,
while maintaining backwards-compatibility for existing arch/platform
structure. In this, each platform would always have its own pmu events
table.
In generated file pmu_events.c, each platform table name is in the
format pme{_vendor}_platform, like this:
struct pmu_events_map pmu_events_map[] = {
{
.cpuid = "0x00000000420f5160",
.version = "v1",
.type = "core",
.table = pme_cavium_thunderx2
},
{
.cpuid = 0,
.version = 0,
.type = 0,
.table = 0,
},
};
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Tested-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-5-git-send-email-john.garry@huawei.com
Link: http://lkml.kernel.org/r/1521047452-28565-1-git-send-email-john.garry@huawei.com
[ Add missing limits.h include, fixing the build on at least all Alpine Linux versions tested (3.4 to 3.7 + edge), ]
[ Applied a patch to fix reading ./.. directories in XFS, see second Link tag ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
index 2407abc1d441..655286ff8767 100644
--- a/tools/perf/pmu-events/README
+++ b/tools/perf/pmu-events/README
@@ -28,6 +28,10 @@ sub directory. Thus for the Silvermont X86 CPU:
Cache.json Memory.json Virtual-Memory.json
Frontend.json Pipeline.json
+The JSONs folder for a CPU model/family may be placed in the root arch
+folder, or may be placed in a vendor sub-folder under the arch folder
+for instances where the arch and vendor are not the same.
+
Using the JSON files and the mapfile, 'jevents' generates the C source file,
'pmu-events.c', which encodes the two sets of tables:
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 1d02fafdc34d..0981d313064f 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -39,6 +39,7 @@
#include <unistd.h>
#include <stdarg.h>
#include <libgen.h>
+#include <limits.h>
#include <dirent.h>
#include <sys/time.h> /* getrlimit */
#include <sys/resource.h> /* getrlimit */
@@ -572,7 +573,7 @@ static char *file_name_to_table_name(char *fname)
* Derive rest of table name from basename of the JSON file,
* replacing hyphens and stripping out .json suffix.
*/
- n = asprintf(&tblname, "pme_%s", basename(fname));
+ n = asprintf(&tblname, "pme_%s", fname);
if (n < 0) {
pr_info("%s: asprintf() error %s for file %s\n", prog,
strerror(errno), fname);
@@ -582,7 +583,7 @@ static char *file_name_to_table_name(char *fname)
for (i = 0; i < strlen(tblname); i++) {
c = tblname[i];
- if (c == '-')
+ if (c == '-' || c == '/')
tblname[i] = '_';
else if (c == '.') {
tblname[i] = '\0';
@@ -739,25 +740,80 @@ static int get_maxfds(void)
static FILE *eventsfp;
static char *mapfile;
+static int is_leaf_dir(const char *fpath)
+{
+ DIR *d;
+ struct dirent *dir;
+ int res = 1;
+
+ d = opendir(fpath);
+ if (!d)
+ return 0;
+
+ while ((dir = readdir(d)) != NULL) {
+ if (!strcmp(dir->d_name, ".") || !strcmp(dir->d_name, ".."))
+ continue;
+
+ if (dir->d_type == DT_DIR) {
+ res = 0;
+ break;
+ } else if (dir->d_type == DT_UNKNOWN) {
+ char path[PATH_MAX];
+ struct stat st;
+
+ sprintf(path, "%s/%s", fpath, dir->d_name);
+ if (stat(path, &st))
+ break;
+
+ if (S_ISDIR(st.st_mode)) {
+ res = 0;
+ break;
+ }
+ }
+ }
+
+ closedir(d);
+
+ return res;
+}
+
static int process_one_file(const char *fpath, const struct stat *sb,
int typeflag, struct FTW *ftwbuf)
{
- char *tblname, *bname = (char *) fpath + ftwbuf->base;
+ char *tblname, *bname;
int is_dir = typeflag == FTW_D;
int is_file = typeflag == FTW_F;
int level = ftwbuf->level;
int err = 0;
+ if (level == 2 && is_dir) {
+ /*
+ * For level 2 directory, bname will include parent name,
+ * like vendor/platform. So search back from platform dir
+ * to find this.
+ */
+ bname = (char *) fpath + ftwbuf->base - 2;
+ for (;;) {
+ if (*bname == '/')
+ break;
+ bname--;
+ }
+ bname++;
+ } else
+ bname = (char *) fpath + ftwbuf->base;
+
pr_debug("%s %d %7jd %-20s %s\n",
is_file ? "f" : is_dir ? "d" : "x",
level, sb->st_size, bname, fpath);
- /* base dir */
- if (level == 0)
+ /* base dir or too deep */
+ if (level == 0 || level > 3)
return 0;
+
/* model directory, reset topic */
- if (level == 1 && is_dir) {
+ if ((level == 1 && is_dir && is_leaf_dir(fpath)) ||
+ (level == 2 && is_dir)) {
if (close_table)
print_events_table_suffix(eventsfp);
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH] perf vendor events: fix processing for xfs
2018-03-14 20:26 ` Arnaldo Carvalho de Melo
@ 2018-03-14 20:58 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-14 20:58 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo
Cc: peterz, mingo, alexander.shishkin, jolsa, namhyung, ak, wcohen,
sukadev, linux-kernel, linuxarm
On 14/03/2018 20:26, Arnaldo Carvalho de Melo wrote:
> Em Wed, Mar 14, 2018 at 07:39:25PM +0000, John Garry escreveu:
>> On 14/03/2018 18:53, Arnaldo Carvalho de Melo wrote:
>>> Em Thu, Mar 15, 2018 at 01:10:52AM +0800, John Garry escreveu:
>>>> In the recently introduced support for vendor subdirectory,
>>>> the checking for directory entries under xfs (or any other fs
>>>> which does not support dirent.d_type) is missing the check
>>>> for links for current and parent directory. This can result
>>>> in a broken pmu_events.c being generated.
>>>>
>>>> Fix this by adding the appropriate check in is_leaf_dir().
>>>
>>> So I'll lookup the patch that introduced the patch and squash this one
>>> with it, so that we don't break 'git bisect' on ppc.
>>
>> Right, so it's going to be "perf vendor events: add support for pmu events
>> vendor subdirectory".
>>
>> BTW, I don't think it's specifically ppc which was broken, but just when
>> building from xfs.
>>
>> Much appreciated,
>> John
>
> This is the ammended cset, and yes, I mentioned just XFS not ppc, added
> Sukadev to the CC list and the link to your patch that he tested. Also
> stamped his Tested-by there.
>
> This will all go again the container build test set before a new pull
> req to Ingo, where I'll avoid sending the previous 31 patches to the
> mailing list, just the ones that came after it, as perf/core keeps
> growing :-)
It looks ok,
Thanks a lot,
John
>
> - Arnaldo
>
> commit d24081387a00d2e10789eb012429144c549598be
> Author: John Garry <john.garry@huawei.com>
> Date: Thu Mar 8 18:58:29 2018 +0800
>
> perf vendor events: Add support for pmu events vendor subdirectory
>
> For some architectures (like arm), it is required to support a vendor
> subdirectory and not locate all the JSONs for a specific vendor in the
> same folder.
>
> This is because all the events for the same vendor will be placed in the
> same pmu events table, which may cause conflict. This conflict would be
> in the instance that a vendor's custom implemented events do have the
> same meaning on different platforms, so events in the pmu table would
> conflict. In addition, per list command may show events which are not
> even supported for a given platform.
>
> This patch adds support for a arch/vendor/platform directory hierarchy,
> while maintaining backwards-compatibility for existing arch/platform
> structure. In this, each platform would always have its own pmu events
> table.
>
> In generated file pmu_events.c, each platform table name is in the
> format pme{_vendor}_platform, like this:
>
> struct pmu_events_map pmu_events_map[] = {
> {
> .cpuid = "0x00000000420f5160",
> .version = "v1",
> .type = "core",
> .table = pme_cavium_thunderx2
> },
> {
> .cpuid = 0,
> .version = 0,
> .type = 0,
> .table = 0,
> },
> };
>
> Signed-off-by: John Garry <john.garry@huawei.com>
> Acked-by: Jiri Olsa <jolsa@kernel.org>
> Tested-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> Cc: Andi Kleen <ak@linux.intel.com>
> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> Cc: Namhyung Kim <namhyung@kernel.org>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: William Cohen <wcohen@redhat.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linuxarm@huawei.com
> Link: http://lkml.kernel.org/r/1520506716-197429-5-git-send-email-john.garry@huawei.com
> Link: http://lkml.kernel.org/r/1521047452-28565-1-git-send-email-john.garry@huawei.com
> [ Add missing limits.h include, fixing the build on at least all Alpine Linux versions tested (3.4 to 3.7 + edge), ]
> [ Applied a patch to fix reading ./.. directories in XFS, see second Link tag ]
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
>
> diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
> index 2407abc1d441..655286ff8767 100644
> --- a/tools/perf/pmu-events/README
> +++ b/tools/perf/pmu-events/README
> @@ -28,6 +28,10 @@ sub directory. Thus for the Silvermont X86 CPU:
> Cache.json Memory.json Virtual-Memory.json
> Frontend.json Pipeline.json
>
> +The JSONs folder for a CPU model/family may be placed in the root arch
> +folder, or may be placed in a vendor sub-folder under the arch folder
> +for instances where the arch and vendor are not the same.
> +
> Using the JSON files and the mapfile, 'jevents' generates the C source file,
> 'pmu-events.c', which encodes the two sets of tables:
>
> diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
> index 1d02fafdc34d..0981d313064f 100644
> --- a/tools/perf/pmu-events/jevents.c
> +++ b/tools/perf/pmu-events/jevents.c
> @@ -39,6 +39,7 @@
> #include <unistd.h>
> #include <stdarg.h>
> #include <libgen.h>
> +#include <limits.h>
> #include <dirent.h>
> #include <sys/time.h> /* getrlimit */
> #include <sys/resource.h> /* getrlimit */
> @@ -572,7 +573,7 @@ static char *file_name_to_table_name(char *fname)
> * Derive rest of table name from basename of the JSON file,
> * replacing hyphens and stripping out .json suffix.
> */
> - n = asprintf(&tblname, "pme_%s", basename(fname));
> + n = asprintf(&tblname, "pme_%s", fname);
> if (n < 0) {
> pr_info("%s: asprintf() error %s for file %s\n", prog,
> strerror(errno), fname);
> @@ -582,7 +583,7 @@ static char *file_name_to_table_name(char *fname)
> for (i = 0; i < strlen(tblname); i++) {
> c = tblname[i];
>
> - if (c == '-')
> + if (c == '-' || c == '/')
> tblname[i] = '_';
> else if (c == '.') {
> tblname[i] = '\0';
> @@ -739,25 +740,80 @@ static int get_maxfds(void)
> static FILE *eventsfp;
> static char *mapfile;
>
> +static int is_leaf_dir(const char *fpath)
> +{
> + DIR *d;
> + struct dirent *dir;
> + int res = 1;
> +
> + d = opendir(fpath);
> + if (!d)
> + return 0;
> +
> + while ((dir = readdir(d)) != NULL) {
> + if (!strcmp(dir->d_name, ".") || !strcmp(dir->d_name, ".."))
> + continue;
> +
> + if (dir->d_type == DT_DIR) {
> + res = 0;
> + break;
> + } else if (dir->d_type == DT_UNKNOWN) {
> + char path[PATH_MAX];
> + struct stat st;
> +
> + sprintf(path, "%s/%s", fpath, dir->d_name);
> + if (stat(path, &st))
> + break;
> +
> + if (S_ISDIR(st.st_mode)) {
> + res = 0;
> + break;
> + }
> + }
> + }
> +
> + closedir(d);
> +
> + return res;
> +}
> +
> static int process_one_file(const char *fpath, const struct stat *sb,
> int typeflag, struct FTW *ftwbuf)
> {
> - char *tblname, *bname = (char *) fpath + ftwbuf->base;
> + char *tblname, *bname;
> int is_dir = typeflag == FTW_D;
> int is_file = typeflag == FTW_F;
> int level = ftwbuf->level;
> int err = 0;
>
> + if (level == 2 && is_dir) {
> + /*
> + * For level 2 directory, bname will include parent name,
> + * like vendor/platform. So search back from platform dir
> + * to find this.
> + */
> + bname = (char *) fpath + ftwbuf->base - 2;
> + for (;;) {
> + if (*bname == '/')
> + break;
> + bname--;
> + }
> + bname++;
> + } else
> + bname = (char *) fpath + ftwbuf->base;
> +
> pr_debug("%s %d %7jd %-20s %s\n",
> is_file ? "f" : is_dir ? "d" : "x",
> level, sb->st_size, bname, fpath);
>
> - /* base dir */
> - if (level == 0)
> + /* base dir or too deep */
> + if (level == 0 || level > 3)
> return 0;
>
> +
> /* model directory, reset topic */
> - if (level == 1 && is_dir) {
> + if ((level == 1 && is_dir && is_leaf_dir(fpath)) ||
> + (level == 2 && is_dir)) {
> if (close_table)
> print_events_table_suffix(eventsfp);
>
>
> .
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* [tip:perf/core] perf vendor events: Add support for pmu events vendor subdirectory
2018-03-14 17:10 ` [PATCH] perf vendor events: fix processing for xfs John Garry
2018-03-14 17:42 ` Sukadev Bhattiprolu
2018-03-14 18:53 ` Arnaldo Carvalho de Melo
@ 2018-03-20 6:22 ` tip-bot for John Garry
2 siblings, 0 replies; 47+ messages in thread
From: tip-bot for John Garry @ 2018-03-20 6:22 UTC (permalink / raw)
To: linux-tip-commits
Cc: ak, sukadev, peterz, acme, hpa, jolsa, wcohen, will.deacon, tglx,
john.garry, alexander.shishkin, namhyung, ganapatrao.kulkarni,
linux-kernel, mingo, zhangshaokun
Commit-ID: 51ce1dcc5d0d3e40e26893a7fa9e30538960ee7e
Gitweb: https://git.kernel.org/tip/51ce1dcc5d0d3e40e26893a7fa9e30538960ee7e
Author: John Garry <john.garry@huawei.com>
AuthorDate: Thu, 8 Mar 2018 18:58:29 +0800
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Fri, 16 Mar 2018 13:54:16 -0300
perf vendor events: Add support for pmu events vendor subdirectory
For some architectures (like arm), it is required to support a vendor
subdirectory and not locate all the JSONs for a specific vendor in the
same folder.
This is because all the events for the same vendor will be placed in the
same pmu events table, which may cause conflict. This conflict would be
in the instance that a vendor's custom implemented events do have the
same meaning on different platforms, so events in the pmu table would
conflict. In addition, per list command may show events which are not
even supported for a given platform.
This patch adds support for a arch/vendor/platform directory hierarchy,
while maintaining backwards-compatibility for existing arch/platform
structure. In this, each platform would always have its own pmu events
table.
In generated file pmu_events.c, each platform table name is in the
format pme{_vendor}_platform, like this:
struct pmu_events_map pmu_events_map[] = {
{
.cpuid = "0x00000000420f5160",
.version = "v1",
.type = "core",
.table = pme_cavium_thunderx2
},
{
.cpuid = 0,
.version = 0,
.type = 0,
.table = 0,
},
};
Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Tested-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-5-git-send-email-john.garry@huawei.com
Link: http://lkml.kernel.org/r/1521047452-28565-1-git-send-email-john.garry@huawei.com
[ Add missing limits.h include, fixing the build on at least all Alpine Linux versions tested (3.4 to 3.7 + edge), ]
[ Applied a patch to fix reading ./.. directories in XFS, see second Link tag ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/README | 4 +++
tools/perf/pmu-events/jevents.c | 68 +++++++++++++++++++++++++++++++++++++----
2 files changed, 66 insertions(+), 6 deletions(-)
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
index 2407abc1d441..655286ff8767 100644
--- a/tools/perf/pmu-events/README
+++ b/tools/perf/pmu-events/README
@@ -28,6 +28,10 @@ sub directory. Thus for the Silvermont X86 CPU:
Cache.json Memory.json Virtual-Memory.json
Frontend.json Pipeline.json
+The JSONs folder for a CPU model/family may be placed in the root arch
+folder, or may be placed in a vendor sub-folder under the arch folder
+for instances where the arch and vendor are not the same.
+
Using the JSON files and the mapfile, 'jevents' generates the C source file,
'pmu-events.c', which encodes the two sets of tables:
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 1d02fafdc34d..0981d313064f 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -39,6 +39,7 @@
#include <unistd.h>
#include <stdarg.h>
#include <libgen.h>
+#include <limits.h>
#include <dirent.h>
#include <sys/time.h> /* getrlimit */
#include <sys/resource.h> /* getrlimit */
@@ -572,7 +573,7 @@ static char *file_name_to_table_name(char *fname)
* Derive rest of table name from basename of the JSON file,
* replacing hyphens and stripping out .json suffix.
*/
- n = asprintf(&tblname, "pme_%s", basename(fname));
+ n = asprintf(&tblname, "pme_%s", fname);
if (n < 0) {
pr_info("%s: asprintf() error %s for file %s\n", prog,
strerror(errno), fname);
@@ -582,7 +583,7 @@ static char *file_name_to_table_name(char *fname)
for (i = 0; i < strlen(tblname); i++) {
c = tblname[i];
- if (c == '-')
+ if (c == '-' || c == '/')
tblname[i] = '_';
else if (c == '.') {
tblname[i] = '\0';
@@ -739,25 +740,80 @@ static int get_maxfds(void)
static FILE *eventsfp;
static char *mapfile;
+static int is_leaf_dir(const char *fpath)
+{
+ DIR *d;
+ struct dirent *dir;
+ int res = 1;
+
+ d = opendir(fpath);
+ if (!d)
+ return 0;
+
+ while ((dir = readdir(d)) != NULL) {
+ if (!strcmp(dir->d_name, ".") || !strcmp(dir->d_name, ".."))
+ continue;
+
+ if (dir->d_type == DT_DIR) {
+ res = 0;
+ break;
+ } else if (dir->d_type == DT_UNKNOWN) {
+ char path[PATH_MAX];
+ struct stat st;
+
+ sprintf(path, "%s/%s", fpath, dir->d_name);
+ if (stat(path, &st))
+ break;
+
+ if (S_ISDIR(st.st_mode)) {
+ res = 0;
+ break;
+ }
+ }
+ }
+
+ closedir(d);
+
+ return res;
+}
+
static int process_one_file(const char *fpath, const struct stat *sb,
int typeflag, struct FTW *ftwbuf)
{
- char *tblname, *bname = (char *) fpath + ftwbuf->base;
+ char *tblname, *bname;
int is_dir = typeflag == FTW_D;
int is_file = typeflag == FTW_F;
int level = ftwbuf->level;
int err = 0;
+ if (level == 2 && is_dir) {
+ /*
+ * For level 2 directory, bname will include parent name,
+ * like vendor/platform. So search back from platform dir
+ * to find this.
+ */
+ bname = (char *) fpath + ftwbuf->base - 2;
+ for (;;) {
+ if (*bname == '/')
+ break;
+ bname--;
+ }
+ bname++;
+ } else
+ bname = (char *) fpath + ftwbuf->base;
+
pr_debug("%s %d %7jd %-20s %s\n",
is_file ? "f" : is_dir ? "d" : "x",
level, sb->st_size, bname, fpath);
- /* base dir */
- if (level == 0)
+ /* base dir or too deep */
+ if (level == 0 || level > 3)
return 0;
+
/* model directory, reset topic */
- if (level == 1 && is_dir) {
+ if ((level == 1 && is_dir && is_leaf_dir(fpath)) ||
+ (level == 2 && is_dir)) {
if (close_table)
print_events_table_suffix(eventsfp);
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v3 05/11] perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory
2018-03-08 10:58 ` John Garry
@ 2018-03-08 10:58 ` John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: jolsa, ak, peterz, mingo, acme, alexander.shishkin, namhyung,
wcohen, will.deacon, ganapatrao.kulkarni
Cc: linuxarm, linux-kernel, linux-arm-kernel, zhangshaokun, John Garry
Since jevents now supports vendor subdirectory, relocate
the ThunderX2 JSON to Cavium subdirectory.
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
.../arch/arm64/cavium/thunderx2-imp-def.json | 62 ----------------------
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 62 ++++++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
3 files changed, 63 insertions(+), 63 deletions(-)
delete mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
deleted file mode 100644
index 2db45c4..0000000
--- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
+++ /dev/null
@@ -1,62 +0,0 @@
-[
- {
- "PublicDescription": "Attributable Level 1 data cache access, read",
- "EventCode": "0x40",
- "EventName": "l1d_cache_rd",
- "BriefDescription": "L1D cache read",
- },
- {
- "PublicDescription": "Attributable Level 1 data cache access, write ",
- "EventCode": "0x41",
- "EventName": "l1d_cache_wr",
- "BriefDescription": "L1D cache write",
- },
- {
- "PublicDescription": "Attributable Level 1 data cache refill, read",
- "EventCode": "0x42",
- "EventName": "l1d_cache_refill_rd",
- "BriefDescription": "L1D cache refill read",
- },
- {
- "PublicDescription": "Attributable Level 1 data cache refill, write",
- "EventCode": "0x43",
- "EventName": "l1d_cache_refill_wr",
- "BriefDescription": "L1D refill write",
- },
- {
- "PublicDescription": "Attributable Level 1 data TLB refill, read",
- "EventCode": "0x4C",
- "EventName": "l1d_tlb_refill_rd",
- "BriefDescription": "L1D tlb refill read",
- },
- {
- "PublicDescription": "Attributable Level 1 data TLB refill, write",
- "EventCode": "0x4D",
- "EventName": "l1d_tlb_refill_wr",
- "BriefDescription": "L1D tlb refill write",
- },
- {
- "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
- "EventCode": "0x4E",
- "EventName": "l1d_tlb_rd",
- "BriefDescription": "L1D tlb read",
- },
- {
- "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
- "EventCode": "0x4F",
- "EventName": "l1d_tlb_wr",
- "BriefDescription": "L1D tlb write",
- },
- {
- "PublicDescription": "Bus access read",
- "EventCode": "0x60",
- "EventName": "bus_access_rd",
- "BriefDescription": "Bus access read",
- },
- {
- "PublicDescription": "Bus access write",
- "EventCode": "0x61",
- "EventName": "bus_access_wr",
- "BriefDescription": "Bus access write",
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
new file mode 100644
index 0000000..2db45c4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
@@ -0,0 +1,62 @@
+[
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, read",
+ "EventCode": "0x40",
+ "EventName": "l1d_cache_rd",
+ "BriefDescription": "L1D cache read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, write ",
+ "EventCode": "0x41",
+ "EventName": "l1d_cache_wr",
+ "BriefDescription": "L1D cache write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, read",
+ "EventCode": "0x42",
+ "EventName": "l1d_cache_refill_rd",
+ "BriefDescription": "L1D cache refill read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, write",
+ "EventCode": "0x43",
+ "EventName": "l1d_cache_refill_wr",
+ "BriefDescription": "L1D refill write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, read",
+ "EventCode": "0x4C",
+ "EventName": "l1d_tlb_refill_rd",
+ "BriefDescription": "L1D tlb refill read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, write",
+ "EventCode": "0x4D",
+ "EventName": "l1d_tlb_refill_wr",
+ "BriefDescription": "L1D tlb refill write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+ "EventCode": "0x4E",
+ "EventName": "l1d_tlb_rd",
+ "BriefDescription": "L1D tlb read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+ "EventCode": "0x4F",
+ "EventName": "l1d_tlb_wr",
+ "BriefDescription": "L1D tlb write",
+ },
+ {
+ "PublicDescription": "Bus access read",
+ "EventCode": "0x60",
+ "EventName": "bus_access_rd",
+ "BriefDescription": "Bus access read",
+ },
+ {
+ "PublicDescription": "Bus access write",
+ "EventCode": "0x61",
+ "EventName": "bus_access_wr",
+ "BriefDescription": "Bus access write",
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index e61c9ca..952a05c 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -12,5 +12,5 @@
#
#
#Family-model,Version,Filename,EventType
-0x00000000420f5160,v1,cavium,core
+0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v3 05/11] perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory
@ 2018-03-08 10:58 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: linux-arm-kernel
Since jevents now supports vendor subdirectory, relocate
the ThunderX2 JSON to Cavium subdirectory.
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
.../arch/arm64/cavium/thunderx2-imp-def.json | 62 ----------------------
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 62 ++++++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
3 files changed, 63 insertions(+), 63 deletions(-)
delete mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
deleted file mode 100644
index 2db45c4..0000000
--- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
+++ /dev/null
@@ -1,62 +0,0 @@
-[
- {
- "PublicDescription": "Attributable Level 1 data cache access, read",
- "EventCode": "0x40",
- "EventName": "l1d_cache_rd",
- "BriefDescription": "L1D cache read",
- },
- {
- "PublicDescription": "Attributable Level 1 data cache access, write ",
- "EventCode": "0x41",
- "EventName": "l1d_cache_wr",
- "BriefDescription": "L1D cache write",
- },
- {
- "PublicDescription": "Attributable Level 1 data cache refill, read",
- "EventCode": "0x42",
- "EventName": "l1d_cache_refill_rd",
- "BriefDescription": "L1D cache refill read",
- },
- {
- "PublicDescription": "Attributable Level 1 data cache refill, write",
- "EventCode": "0x43",
- "EventName": "l1d_cache_refill_wr",
- "BriefDescription": "L1D refill write",
- },
- {
- "PublicDescription": "Attributable Level 1 data TLB refill, read",
- "EventCode": "0x4C",
- "EventName": "l1d_tlb_refill_rd",
- "BriefDescription": "L1D tlb refill read",
- },
- {
- "PublicDescription": "Attributable Level 1 data TLB refill, write",
- "EventCode": "0x4D",
- "EventName": "l1d_tlb_refill_wr",
- "BriefDescription": "L1D tlb refill write",
- },
- {
- "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
- "EventCode": "0x4E",
- "EventName": "l1d_tlb_rd",
- "BriefDescription": "L1D tlb read",
- },
- {
- "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
- "EventCode": "0x4F",
- "EventName": "l1d_tlb_wr",
- "BriefDescription": "L1D tlb write",
- },
- {
- "PublicDescription": "Bus access read",
- "EventCode": "0x60",
- "EventName": "bus_access_rd",
- "BriefDescription": "Bus access read",
- },
- {
- "PublicDescription": "Bus access write",
- "EventCode": "0x61",
- "EventName": "bus_access_wr",
- "BriefDescription": "Bus access write",
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
new file mode 100644
index 0000000..2db45c4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
@@ -0,0 +1,62 @@
+[
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, read",
+ "EventCode": "0x40",
+ "EventName": "l1d_cache_rd",
+ "BriefDescription": "L1D cache read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, write ",
+ "EventCode": "0x41",
+ "EventName": "l1d_cache_wr",
+ "BriefDescription": "L1D cache write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, read",
+ "EventCode": "0x42",
+ "EventName": "l1d_cache_refill_rd",
+ "BriefDescription": "L1D cache refill read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, write",
+ "EventCode": "0x43",
+ "EventName": "l1d_cache_refill_wr",
+ "BriefDescription": "L1D refill write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, read",
+ "EventCode": "0x4C",
+ "EventName": "l1d_tlb_refill_rd",
+ "BriefDescription": "L1D tlb refill read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, write",
+ "EventCode": "0x4D",
+ "EventName": "l1d_tlb_refill_wr",
+ "BriefDescription": "L1D tlb refill write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+ "EventCode": "0x4E",
+ "EventName": "l1d_tlb_rd",
+ "BriefDescription": "L1D tlb read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+ "EventCode": "0x4F",
+ "EventName": "l1d_tlb_wr",
+ "BriefDescription": "L1D tlb write",
+ },
+ {
+ "PublicDescription": "Bus access read",
+ "EventCode": "0x60",
+ "EventName": "bus_access_rd",
+ "BriefDescription": "Bus access read",
+ },
+ {
+ "PublicDescription": "Bus access write",
+ "EventCode": "0x61",
+ "EventName": "bus_access_wr",
+ "BriefDescription": "Bus access write",
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index e61c9ca..952a05c 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -12,5 +12,5 @@
#
#
#Family-model,Version,Filename,EventType
-0x00000000420f5160,v1,cavium,core
+0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [tip:perf/core] perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory
2018-03-08 10:58 ` John Garry
(?)
@ 2018-03-20 6:23 ` tip-bot for John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: tip-bot for John Garry @ 2018-03-20 6:23 UTC (permalink / raw)
To: linux-tip-commits
Cc: peterz, namhyung, jolsa, john.garry, tglx, linux-kernel, wcohen,
ganapatrao.kulkarni, alexander.shishkin, zhangshaokun, hpa, acme,
ak, mingo, will.deacon
Commit-ID: e3b9f1e81de2083f359bacd2a94bf1c024f2ede0
Gitweb: https://git.kernel.org/tip/e3b9f1e81de2083f359bacd2a94bf1c024f2ede0
Author: John Garry <john.garry@huawei.com>
AuthorDate: Thu, 8 Mar 2018 18:58:30 +0800
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Fri, 16 Mar 2018 13:54:23 -0300
perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory
Since jevents now supports vendor subdirectory, relocate
the ThunderX2 JSON to Cavium subdirectory.
Signed-off-by: John Garry <john.garry@huawei.com>
Tested-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-6-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../cavium/{thunderx2-imp-def.json => thunderx2/core-imp-def.json} | 0
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
rename to tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index e61c9ca6cf9e..952a05cbf675 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -12,5 +12,5 @@
#
#
#Family-model,Version,Filename,EventType
-0x00000000420f5160,v1,cavium,core
+0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v3 06/11] perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory
2018-03-08 10:58 ` John Garry
@ 2018-03-08 10:58 ` John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: jolsa, ak, peterz, mingo, acme, alexander.shishkin, namhyung,
wcohen, will.deacon, ganapatrao.kulkarni
Cc: linuxarm, linux-kernel, linux-arm-kernel, zhangshaokun, John Garry
Since jevents now supports vendor subdirectory, relocate
the Cortex-A53 JSONs to arm subdirectory.
Cc: William Cohen <wcohen@redhat.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
.../arch/arm64/arm/cortex-a53/branch.json | 27 +++++++++++
.../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 22 +++++++++
.../arch/arm64/arm/cortex-a53/cache.json | 27 +++++++++++
.../arch/arm64/arm/cortex-a53/memory.json | 22 +++++++++
.../arch/arm64/arm/cortex-a53/other.json | 32 +++++++++++++
.../arch/arm64/arm/cortex-a53/pipeline.json | 52 ++++++++++++++++++++++
.../pmu-events/arch/arm64/cortex-a53/branch.json | 27 -----------
.../perf/pmu-events/arch/arm64/cortex-a53/bus.json | 22 ---------
.../pmu-events/arch/arm64/cortex-a53/cache.json | 27 -----------
.../pmu-events/arch/arm64/cortex-a53/memory.json | 22 ---------
.../pmu-events/arch/arm64/cortex-a53/other.json | 32 -------------
.../pmu-events/arch/arm64/cortex-a53/pipeline.json | 52 ----------------------
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
13 files changed, 183 insertions(+), 183 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
new file mode 100644
index 0000000..3b62087
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
@@ -0,0 +1,27 @@
+[
+ {,
+ "EventCode": "0x7A",
+ "EventName": "BR_INDIRECT_SPEC",
+ "BriefDescription": "Branch speculatively executed - Indirect branch"
+ },
+ {,
+ "EventCode": "0xC9",
+ "EventName": "BR_COND",
+ "BriefDescription": "Conditional branch executed"
+ },
+ {,
+ "EventCode": "0xCA",
+ "EventName": "BR_INDIRECT_MISPRED",
+ "BriefDescription": "Indirect branch mispredicted"
+ },
+ {,
+ "EventCode": "0xCB",
+ "EventName": "BR_INDIRECT_MISPRED_ADDR",
+ "BriefDescription": "Indirect branch mispredicted because of address miscompare"
+ },
+ {,
+ "EventCode": "0xCC",
+ "EventName": "BR_COND_MISPRED",
+ "BriefDescription": "Conditional branch mispredicted"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
new file mode 100644
index 0000000..480d9f7
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
@@ -0,0 +1,22 @@
+[
+ {,
+ "EventCode": "0x60",
+ "EventName": "BUS_ACCESS_LD",
+ "BriefDescription": "Bus access - Read"
+ },
+ {,
+ "EventCode": "0x61",
+ "EventName": "BUS_ACCESS_ST",
+ "BriefDescription": "Bus access - Write"
+ },
+ {,
+ "EventCode": "0xC0",
+ "EventName": "EXT_MEM_REQ",
+ "BriefDescription": "External memory request"
+ },
+ {,
+ "EventCode": "0xC1",
+ "EventName": "EXT_MEM_REQ_NC",
+ "BriefDescription": "Non-cacheable external memory request"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
new file mode 100644
index 0000000..11baad6
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
@@ -0,0 +1,27 @@
+[
+ {,
+ "EventCode": "0xC2",
+ "EventName": "PREFETCH_LINEFILL",
+ "BriefDescription": "Linefill because of prefetch"
+ },
+ {,
+ "EventCode": "0xC3",
+ "EventName": "PREFETCH_LINEFILL_DROP",
+ "BriefDescription": "Instruction Cache Throttle occurred"
+ },
+ {,
+ "EventCode": "0xC4",
+ "EventName": "READ_ALLOC_ENTER",
+ "BriefDescription": "Entering read allocate mode"
+ },
+ {,
+ "EventCode": "0xC5",
+ "EventName": "READ_ALLOC",
+ "BriefDescription": "Read allocate mode"
+ },
+ {,
+ "EventCode": "0xC8",
+ "EventName": "EXT_SNOOP",
+ "BriefDescription": "SCU Snooped data from another CPU for this CPU"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
new file mode 100644
index 0000000..480d9f7
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
@@ -0,0 +1,22 @@
+[
+ {,
+ "EventCode": "0x60",
+ "EventName": "BUS_ACCESS_LD",
+ "BriefDescription": "Bus access - Read"
+ },
+ {,
+ "EventCode": "0x61",
+ "EventName": "BUS_ACCESS_ST",
+ "BriefDescription": "Bus access - Write"
+ },
+ {,
+ "EventCode": "0xC0",
+ "EventName": "EXT_MEM_REQ",
+ "BriefDescription": "External memory request"
+ },
+ {,
+ "EventCode": "0xC1",
+ "EventName": "EXT_MEM_REQ_NC",
+ "BriefDescription": "Non-cacheable external memory request"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
new file mode 100644
index 0000000..73a2240
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
@@ -0,0 +1,32 @@
+[
+ {,
+ "EventCode": "0x86",
+ "EventName": "EXC_IRQ",
+ "BriefDescription": "Exception taken, IRQ"
+ },
+ {,
+ "EventCode": "0x87",
+ "EventName": "EXC_FIQ",
+ "BriefDescription": "Exception taken, FIQ"
+ },
+ {,
+ "EventCode": "0xC6",
+ "EventName": "PRE_DECODE_ERR",
+ "BriefDescription": "Pre-decode error"
+ },
+ {,
+ "EventCode": "0xD0",
+ "EventName": "L1I_CACHE_ERR",
+ "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
+ },
+ {,
+ "EventCode": "0xD1",
+ "EventName": "L1D_CACHE_ERR",
+ "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
+ },
+ {,
+ "EventCode": "0xD2",
+ "EventName": "TLB_ERR",
+ "BriefDescription": "TLB memory error"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
new file mode 100644
index 0000000..3149fb9
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
@@ -0,0 +1,52 @@
+[
+ {,
+ "EventCode": "0xC7",
+ "EventName": "STALL_SB_FULL",
+ "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
+ },
+ {,
+ "EventCode": "0xE0",
+ "EventName": "OTHER_IQ_DEP_STALL",
+ "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
+ },
+ {,
+ "EventCode": "0xE1",
+ "EventName": "IC_DEP_STALL",
+ "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
+ },
+ {,
+ "EventCode": "0xE2",
+ "EventName": "IUTLB_DEP_STALL",
+ "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
+ },
+ {,
+ "EventCode": "0xE3",
+ "EventName": "DECODE_DEP_STALL",
+ "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
+ },
+ {,
+ "EventCode": "0xE4",
+ "EventName": "OTHER_INTERLOCK_STALL",
+ "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction"
+ },
+ {,
+ "EventCode": "0xE5",
+ "EventName": "AGU_DEP_STALL",
+ "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
+ },
+ {,
+ "EventCode": "0xE6",
+ "EventName": "SIMD_DEP_STALL",
+ "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
+ },
+ {,
+ "EventCode": "0xE7",
+ "EventName": "LD_DEP_STALL",
+ "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
+ },
+ {,
+ "EventCode": "0xE8",
+ "EventName": "ST_DEP_STALL",
+ "BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
deleted file mode 100644
index 3b62087..0000000
--- a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
+++ /dev/null
@@ -1,27 +0,0 @@
-[
- {,
- "EventCode": "0x7A",
- "EventName": "BR_INDIRECT_SPEC",
- "BriefDescription": "Branch speculatively executed - Indirect branch"
- },
- {,
- "EventCode": "0xC9",
- "EventName": "BR_COND",
- "BriefDescription": "Conditional branch executed"
- },
- {,
- "EventCode": "0xCA",
- "EventName": "BR_INDIRECT_MISPRED",
- "BriefDescription": "Indirect branch mispredicted"
- },
- {,
- "EventCode": "0xCB",
- "EventName": "BR_INDIRECT_MISPRED_ADDR",
- "BriefDescription": "Indirect branch mispredicted because of address miscompare"
- },
- {,
- "EventCode": "0xCC",
- "EventName": "BR_COND_MISPRED",
- "BriefDescription": "Conditional branch mispredicted"
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
deleted file mode 100644
index 480d9f7..0000000
--- a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
+++ /dev/null
@@ -1,22 +0,0 @@
-[
- {,
- "EventCode": "0x60",
- "EventName": "BUS_ACCESS_LD",
- "BriefDescription": "Bus access - Read"
- },
- {,
- "EventCode": "0x61",
- "EventName": "BUS_ACCESS_ST",
- "BriefDescription": "Bus access - Write"
- },
- {,
- "EventCode": "0xC0",
- "EventName": "EXT_MEM_REQ",
- "BriefDescription": "External memory request"
- },
- {,
- "EventCode": "0xC1",
- "EventName": "EXT_MEM_REQ_NC",
- "BriefDescription": "Non-cacheable external memory request"
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
deleted file mode 100644
index 11baad6..0000000
--- a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
+++ /dev/null
@@ -1,27 +0,0 @@
-[
- {,
- "EventCode": "0xC2",
- "EventName": "PREFETCH_LINEFILL",
- "BriefDescription": "Linefill because of prefetch"
- },
- {,
- "EventCode": "0xC3",
- "EventName": "PREFETCH_LINEFILL_DROP",
- "BriefDescription": "Instruction Cache Throttle occurred"
- },
- {,
- "EventCode": "0xC4",
- "EventName": "READ_ALLOC_ENTER",
- "BriefDescription": "Entering read allocate mode"
- },
- {,
- "EventCode": "0xC5",
- "EventName": "READ_ALLOC",
- "BriefDescription": "Read allocate mode"
- },
- {,
- "EventCode": "0xC8",
- "EventName": "EXT_SNOOP",
- "BriefDescription": "SCU Snooped data from another CPU for this CPU"
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
deleted file mode 100644
index 480d9f7..0000000
--- a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
+++ /dev/null
@@ -1,22 +0,0 @@
-[
- {,
- "EventCode": "0x60",
- "EventName": "BUS_ACCESS_LD",
- "BriefDescription": "Bus access - Read"
- },
- {,
- "EventCode": "0x61",
- "EventName": "BUS_ACCESS_ST",
- "BriefDescription": "Bus access - Write"
- },
- {,
- "EventCode": "0xC0",
- "EventName": "EXT_MEM_REQ",
- "BriefDescription": "External memory request"
- },
- {,
- "EventCode": "0xC1",
- "EventName": "EXT_MEM_REQ_NC",
- "BriefDescription": "Non-cacheable external memory request"
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
deleted file mode 100644
index 73a2240..0000000
--- a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
+++ /dev/null
@@ -1,32 +0,0 @@
-[
- {,
- "EventCode": "0x86",
- "EventName": "EXC_IRQ",
- "BriefDescription": "Exception taken, IRQ"
- },
- {,
- "EventCode": "0x87",
- "EventName": "EXC_FIQ",
- "BriefDescription": "Exception taken, FIQ"
- },
- {,
- "EventCode": "0xC6",
- "EventName": "PRE_DECODE_ERR",
- "BriefDescription": "Pre-decode error"
- },
- {,
- "EventCode": "0xD0",
- "EventName": "L1I_CACHE_ERR",
- "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
- },
- {,
- "EventCode": "0xD1",
- "EventName": "L1D_CACHE_ERR",
- "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
- },
- {,
- "EventCode": "0xD2",
- "EventName": "TLB_ERR",
- "BriefDescription": "TLB memory error"
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json
deleted file mode 100644
index 3149fb9..0000000
--- a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json
+++ /dev/null
@@ -1,52 +0,0 @@
-[
- {,
- "EventCode": "0xC7",
- "EventName": "STALL_SB_FULL",
- "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
- },
- {,
- "EventCode": "0xE0",
- "EventName": "OTHER_IQ_DEP_STALL",
- "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
- },
- {,
- "EventCode": "0xE1",
- "EventName": "IC_DEP_STALL",
- "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
- },
- {,
- "EventCode": "0xE2",
- "EventName": "IUTLB_DEP_STALL",
- "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
- },
- {,
- "EventCode": "0xE3",
- "EventName": "DECODE_DEP_STALL",
- "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
- },
- {,
- "EventCode": "0xE4",
- "EventName": "OTHER_INTERLOCK_STALL",
- "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction"
- },
- {,
- "EventCode": "0xE5",
- "EventName": "AGU_DEP_STALL",
- "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
- },
- {,
- "EventCode": "0xE6",
- "EventName": "SIMD_DEP_STALL",
- "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
- },
- {,
- "EventCode": "0xE7",
- "EventName": "LD_DEP_STALL",
- "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
- },
- {,
- "EventCode": "0xE8",
- "EventName": "ST_DEP_STALL",
- "BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 952a05c..cf14e23 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -12,5 +12,5 @@
#
#
#Family-model,Version,Filename,EventType
+0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
-0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v3 06/11] perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory
@ 2018-03-08 10:58 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: linux-arm-kernel
Since jevents now supports vendor subdirectory, relocate
the Cortex-A53 JSONs to arm subdirectory.
Cc: William Cohen <wcohen@redhat.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
.../arch/arm64/arm/cortex-a53/branch.json | 27 +++++++++++
.../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 22 +++++++++
.../arch/arm64/arm/cortex-a53/cache.json | 27 +++++++++++
.../arch/arm64/arm/cortex-a53/memory.json | 22 +++++++++
.../arch/arm64/arm/cortex-a53/other.json | 32 +++++++++++++
.../arch/arm64/arm/cortex-a53/pipeline.json | 52 ++++++++++++++++++++++
.../pmu-events/arch/arm64/cortex-a53/branch.json | 27 -----------
.../perf/pmu-events/arch/arm64/cortex-a53/bus.json | 22 ---------
.../pmu-events/arch/arm64/cortex-a53/cache.json | 27 -----------
.../pmu-events/arch/arm64/cortex-a53/memory.json | 22 ---------
.../pmu-events/arch/arm64/cortex-a53/other.json | 32 -------------
.../pmu-events/arch/arm64/cortex-a53/pipeline.json | 52 ----------------------
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
13 files changed, 183 insertions(+), 183 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
new file mode 100644
index 0000000..3b62087
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
@@ -0,0 +1,27 @@
+[
+ {,
+ "EventCode": "0x7A",
+ "EventName": "BR_INDIRECT_SPEC",
+ "BriefDescription": "Branch speculatively executed - Indirect branch"
+ },
+ {,
+ "EventCode": "0xC9",
+ "EventName": "BR_COND",
+ "BriefDescription": "Conditional branch executed"
+ },
+ {,
+ "EventCode": "0xCA",
+ "EventName": "BR_INDIRECT_MISPRED",
+ "BriefDescription": "Indirect branch mispredicted"
+ },
+ {,
+ "EventCode": "0xCB",
+ "EventName": "BR_INDIRECT_MISPRED_ADDR",
+ "BriefDescription": "Indirect branch mispredicted because of address miscompare"
+ },
+ {,
+ "EventCode": "0xCC",
+ "EventName": "BR_COND_MISPRED",
+ "BriefDescription": "Conditional branch mispredicted"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
new file mode 100644
index 0000000..480d9f7
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
@@ -0,0 +1,22 @@
+[
+ {,
+ "EventCode": "0x60",
+ "EventName": "BUS_ACCESS_LD",
+ "BriefDescription": "Bus access - Read"
+ },
+ {,
+ "EventCode": "0x61",
+ "EventName": "BUS_ACCESS_ST",
+ "BriefDescription": "Bus access - Write"
+ },
+ {,
+ "EventCode": "0xC0",
+ "EventName": "EXT_MEM_REQ",
+ "BriefDescription": "External memory request"
+ },
+ {,
+ "EventCode": "0xC1",
+ "EventName": "EXT_MEM_REQ_NC",
+ "BriefDescription": "Non-cacheable external memory request"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
new file mode 100644
index 0000000..11baad6
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
@@ -0,0 +1,27 @@
+[
+ {,
+ "EventCode": "0xC2",
+ "EventName": "PREFETCH_LINEFILL",
+ "BriefDescription": "Linefill because of prefetch"
+ },
+ {,
+ "EventCode": "0xC3",
+ "EventName": "PREFETCH_LINEFILL_DROP",
+ "BriefDescription": "Instruction Cache Throttle occurred"
+ },
+ {,
+ "EventCode": "0xC4",
+ "EventName": "READ_ALLOC_ENTER",
+ "BriefDescription": "Entering read allocate mode"
+ },
+ {,
+ "EventCode": "0xC5",
+ "EventName": "READ_ALLOC",
+ "BriefDescription": "Read allocate mode"
+ },
+ {,
+ "EventCode": "0xC8",
+ "EventName": "EXT_SNOOP",
+ "BriefDescription": "SCU Snooped data from another CPU for this CPU"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
new file mode 100644
index 0000000..480d9f7
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
@@ -0,0 +1,22 @@
+[
+ {,
+ "EventCode": "0x60",
+ "EventName": "BUS_ACCESS_LD",
+ "BriefDescription": "Bus access - Read"
+ },
+ {,
+ "EventCode": "0x61",
+ "EventName": "BUS_ACCESS_ST",
+ "BriefDescription": "Bus access - Write"
+ },
+ {,
+ "EventCode": "0xC0",
+ "EventName": "EXT_MEM_REQ",
+ "BriefDescription": "External memory request"
+ },
+ {,
+ "EventCode": "0xC1",
+ "EventName": "EXT_MEM_REQ_NC",
+ "BriefDescription": "Non-cacheable external memory request"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
new file mode 100644
index 0000000..73a2240
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
@@ -0,0 +1,32 @@
+[
+ {,
+ "EventCode": "0x86",
+ "EventName": "EXC_IRQ",
+ "BriefDescription": "Exception taken, IRQ"
+ },
+ {,
+ "EventCode": "0x87",
+ "EventName": "EXC_FIQ",
+ "BriefDescription": "Exception taken, FIQ"
+ },
+ {,
+ "EventCode": "0xC6",
+ "EventName": "PRE_DECODE_ERR",
+ "BriefDescription": "Pre-decode error"
+ },
+ {,
+ "EventCode": "0xD0",
+ "EventName": "L1I_CACHE_ERR",
+ "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
+ },
+ {,
+ "EventCode": "0xD1",
+ "EventName": "L1D_CACHE_ERR",
+ "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
+ },
+ {,
+ "EventCode": "0xD2",
+ "EventName": "TLB_ERR",
+ "BriefDescription": "TLB memory error"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
new file mode 100644
index 0000000..3149fb9
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
@@ -0,0 +1,52 @@
+[
+ {,
+ "EventCode": "0xC7",
+ "EventName": "STALL_SB_FULL",
+ "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
+ },
+ {,
+ "EventCode": "0xE0",
+ "EventName": "OTHER_IQ_DEP_STALL",
+ "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
+ },
+ {,
+ "EventCode": "0xE1",
+ "EventName": "IC_DEP_STALL",
+ "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
+ },
+ {,
+ "EventCode": "0xE2",
+ "EventName": "IUTLB_DEP_STALL",
+ "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
+ },
+ {,
+ "EventCode": "0xE3",
+ "EventName": "DECODE_DEP_STALL",
+ "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
+ },
+ {,
+ "EventCode": "0xE4",
+ "EventName": "OTHER_INTERLOCK_STALL",
+ "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction"
+ },
+ {,
+ "EventCode": "0xE5",
+ "EventName": "AGU_DEP_STALL",
+ "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
+ },
+ {,
+ "EventCode": "0xE6",
+ "EventName": "SIMD_DEP_STALL",
+ "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
+ },
+ {,
+ "EventCode": "0xE7",
+ "EventName": "LD_DEP_STALL",
+ "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
+ },
+ {,
+ "EventCode": "0xE8",
+ "EventName": "ST_DEP_STALL",
+ "BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
deleted file mode 100644
index 3b62087..0000000
--- a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
+++ /dev/null
@@ -1,27 +0,0 @@
-[
- {,
- "EventCode": "0x7A",
- "EventName": "BR_INDIRECT_SPEC",
- "BriefDescription": "Branch speculatively executed - Indirect branch"
- },
- {,
- "EventCode": "0xC9",
- "EventName": "BR_COND",
- "BriefDescription": "Conditional branch executed"
- },
- {,
- "EventCode": "0xCA",
- "EventName": "BR_INDIRECT_MISPRED",
- "BriefDescription": "Indirect branch mispredicted"
- },
- {,
- "EventCode": "0xCB",
- "EventName": "BR_INDIRECT_MISPRED_ADDR",
- "BriefDescription": "Indirect branch mispredicted because of address miscompare"
- },
- {,
- "EventCode": "0xCC",
- "EventName": "BR_COND_MISPRED",
- "BriefDescription": "Conditional branch mispredicted"
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
deleted file mode 100644
index 480d9f7..0000000
--- a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
+++ /dev/null
@@ -1,22 +0,0 @@
-[
- {,
- "EventCode": "0x60",
- "EventName": "BUS_ACCESS_LD",
- "BriefDescription": "Bus access - Read"
- },
- {,
- "EventCode": "0x61",
- "EventName": "BUS_ACCESS_ST",
- "BriefDescription": "Bus access - Write"
- },
- {,
- "EventCode": "0xC0",
- "EventName": "EXT_MEM_REQ",
- "BriefDescription": "External memory request"
- },
- {,
- "EventCode": "0xC1",
- "EventName": "EXT_MEM_REQ_NC",
- "BriefDescription": "Non-cacheable external memory request"
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
deleted file mode 100644
index 11baad6..0000000
--- a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
+++ /dev/null
@@ -1,27 +0,0 @@
-[
- {,
- "EventCode": "0xC2",
- "EventName": "PREFETCH_LINEFILL",
- "BriefDescription": "Linefill because of prefetch"
- },
- {,
- "EventCode": "0xC3",
- "EventName": "PREFETCH_LINEFILL_DROP",
- "BriefDescription": "Instruction Cache Throttle occurred"
- },
- {,
- "EventCode": "0xC4",
- "EventName": "READ_ALLOC_ENTER",
- "BriefDescription": "Entering read allocate mode"
- },
- {,
- "EventCode": "0xC5",
- "EventName": "READ_ALLOC",
- "BriefDescription": "Read allocate mode"
- },
- {,
- "EventCode": "0xC8",
- "EventName": "EXT_SNOOP",
- "BriefDescription": "SCU Snooped data from another CPU for this CPU"
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
deleted file mode 100644
index 480d9f7..0000000
--- a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
+++ /dev/null
@@ -1,22 +0,0 @@
-[
- {,
- "EventCode": "0x60",
- "EventName": "BUS_ACCESS_LD",
- "BriefDescription": "Bus access - Read"
- },
- {,
- "EventCode": "0x61",
- "EventName": "BUS_ACCESS_ST",
- "BriefDescription": "Bus access - Write"
- },
- {,
- "EventCode": "0xC0",
- "EventName": "EXT_MEM_REQ",
- "BriefDescription": "External memory request"
- },
- {,
- "EventCode": "0xC1",
- "EventName": "EXT_MEM_REQ_NC",
- "BriefDescription": "Non-cacheable external memory request"
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
deleted file mode 100644
index 73a2240..0000000
--- a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
+++ /dev/null
@@ -1,32 +0,0 @@
-[
- {,
- "EventCode": "0x86",
- "EventName": "EXC_IRQ",
- "BriefDescription": "Exception taken, IRQ"
- },
- {,
- "EventCode": "0x87",
- "EventName": "EXC_FIQ",
- "BriefDescription": "Exception taken, FIQ"
- },
- {,
- "EventCode": "0xC6",
- "EventName": "PRE_DECODE_ERR",
- "BriefDescription": "Pre-decode error"
- },
- {,
- "EventCode": "0xD0",
- "EventName": "L1I_CACHE_ERR",
- "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
- },
- {,
- "EventCode": "0xD1",
- "EventName": "L1D_CACHE_ERR",
- "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
- },
- {,
- "EventCode": "0xD2",
- "EventName": "TLB_ERR",
- "BriefDescription": "TLB memory error"
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json
deleted file mode 100644
index 3149fb9..0000000
--- a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json
+++ /dev/null
@@ -1,52 +0,0 @@
-[
- {,
- "EventCode": "0xC7",
- "EventName": "STALL_SB_FULL",
- "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
- },
- {,
- "EventCode": "0xE0",
- "EventName": "OTHER_IQ_DEP_STALL",
- "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
- },
- {,
- "EventCode": "0xE1",
- "EventName": "IC_DEP_STALL",
- "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
- },
- {,
- "EventCode": "0xE2",
- "EventName": "IUTLB_DEP_STALL",
- "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
- },
- {,
- "EventCode": "0xE3",
- "EventName": "DECODE_DEP_STALL",
- "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
- },
- {,
- "EventCode": "0xE4",
- "EventName": "OTHER_INTERLOCK_STALL",
- "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction"
- },
- {,
- "EventCode": "0xE5",
- "EventName": "AGU_DEP_STALL",
- "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
- },
- {,
- "EventCode": "0xE6",
- "EventName": "SIMD_DEP_STALL",
- "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
- },
- {,
- "EventCode": "0xE7",
- "EventName": "LD_DEP_STALL",
- "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
- },
- {,
- "EventCode": "0xE8",
- "EventName": "ST_DEP_STALL",
- "BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
- }
-]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 952a05c..cf14e23 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -12,5 +12,5 @@
#
#
#Family-model,Version,Filename,EventType
+0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
-0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [tip:perf/core] perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory
2018-03-08 10:58 ` John Garry
(?)
@ 2018-03-20 6:23 ` tip-bot for John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: tip-bot for John Garry @ 2018-03-20 6:23 UTC (permalink / raw)
To: linux-tip-commits
Cc: ganapatrao.kulkarni, wcohen, mingo, peterz, namhyung, tglx,
jolsa, will.deacon, alexander.shishkin, john.garry, ak, hpa,
zhangshaokun, linux-kernel, acme
Commit-ID: 82e6fdd6c01257d64009defbbea19d12ba667670
Gitweb: https://git.kernel.org/tip/82e6fdd6c01257d64009defbbea19d12ba667670
Author: John Garry <john.garry@huawei.com>
AuthorDate: Thu, 8 Mar 2018 18:58:31 +0800
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Fri, 16 Mar 2018 13:54:29 -0300
perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory
Since jevents now supports vendor subdirectory, relocate the Cortex-A53
JSONs to arm subdirectory.
Signed-off-by: John Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-7-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/branch.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/bus.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/cache.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/memory.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/other.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/pipeline.json | 0
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
7 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json
rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 952a05cbf675..cf14e23b6404 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -12,5 +12,5 @@
#
#
#Family-model,Version,Filename,EventType
+0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
-0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v3 07/11] perf vendor events: add support for arch standard events
2018-03-08 10:58 ` John Garry
@ 2018-03-08 10:58 ` John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: jolsa, ak, peterz, mingo, acme, alexander.shishkin, namhyung,
wcohen, will.deacon, ganapatrao.kulkarni
Cc: linuxarm, linux-kernel, linux-arm-kernel, zhangshaokun, John Garry
For some architectures (like arm), there are architecture-
defined events. Sometimes these events may be "recommended"
according to the architecture standard, in that the
implementer is free ignore the "recommendation" and create
its custom event.
This patch adds support for parsing standard events from
arch-defined JSONs, and fixing up vendor events when they
have implemented these events as standard.
Support is also ensured that the vendor may implement their
own custom events.
A new step is added to the pmu events parsing to fix up the
vendor events with the arch-standard events.
The arch-defined JSONs must be placed in the arch root
folder for preprocessing prior to tree JSON processing.
In the vendor JSON, to specify that the arch event is
supported, the keyword "ArchStdEvent" should be used,
like this:
[
{
"ArchStdEvent": "L1D_CACHE_WR",
},
]
Matching is based on the "EventName" field in the
architecture JSON.
No other JSON objects are strictly required. However,
for other objects added, these take precedence over
architecture defined standard events, thus supporting
separate events which have the same event code.
Signed-off-by: John Garry <john.garry@huawei.com>
---
tools/perf/pmu-events/Build | 2 +
tools/perf/pmu-events/README | 6 ++
tools/perf/pmu-events/jevents.c | 167 +++++++++++++++++++++++++++++++++++++++-
3 files changed, 172 insertions(+), 3 deletions(-)
diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build
index 999a4e8..1778391 100644
--- a/tools/perf/pmu-events/Build
+++ b/tools/perf/pmu-events/Build
@@ -1,10 +1,12 @@
hostprogs := jevents
jevents-y += json.o jsmn.o jevents.o
+CHOSTFLAGS_jevents.o = -I$(srctree)/tools/include
pmu-events-y += pmu-events.o
JDIR = pmu-events/arch/$(SRCARCH)
JSON = $(shell [ -d $(JDIR) ] && \
find $(JDIR) -name '*.json' -o -name 'mapfile.csv')
+
#
# Locate/process JSON files in pmu-events/arch/
# directory and create tables in pmu-events.c.
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
index 655286f..e62b09b 100644
--- a/tools/perf/pmu-events/README
+++ b/tools/perf/pmu-events/README
@@ -16,6 +16,12 @@ tree tools/perf/pmu-events/arch/foo.
- Directories are traversed, but all other files are ignored.
+ - To reduce JSON event duplication per architecture, platform JSONs may
+ use "ArchStdEvent" keyword to dereference an "Architecture standard
+ events", defined in architecture standard JSONs.
+ Architecture standard JSONs must be located in the architecture root
+ folder. Matching is based on the "EventName" field.
+
The PMU events supported by a CPU model are expected to grouped into topics
such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic
should be placed in a separate JSON file - where the file name identifies
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 7b9e210..9b970a0 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -44,6 +44,7 @@
#include <sys/resource.h> /* getrlimit */
#include <ftw.h>
#include <sys/stat.h>
+#include <linux/list.h>
#include "jsmn.h"
#include "json.h"
#include "jevents.h"
@@ -350,6 +351,81 @@ static int print_events_table_entry(void *data, char *name, char *event,
return 0;
}
+struct event_struct {
+ struct list_head list;
+ char *name;
+ char *event;
+ char *desc;
+ char *long_desc;
+ char *pmu;
+ char *unit;
+ char *perpkg;
+ char *metric_expr;
+ char *metric_name;
+ char *metric_group;
+};
+
+#define ADD_EVENT_FIELD(field) do { if (field) { \
+ es->field = strdup(field); \
+ if (!es->field) \
+ goto out_free; \
+} } while (0)
+
+#define FREE_EVENT_FIELD(field) free(es->field)
+
+#define TRY_FIXUP_FIELD(field) do { if (es->field && !*field) {\
+ *field = strdup(es->field); \
+ if (!*field) \
+ return -ENOMEM; \
+} } while (0)
+
+#define FOR_ALL_EVENT_STRUCT_FIELDS(op) do { \
+ op(name); \
+ op(event); \
+ op(desc); \
+ op(long_desc); \
+ op(pmu); \
+ op(unit); \
+ op(perpkg); \
+ op(metric_expr); \
+ op(metric_name); \
+ op(metric_group); \
+} while (0)
+
+static LIST_HEAD(arch_std_events);
+
+static void free_arch_std_events(void)
+{
+ struct event_struct *es, *next;
+
+ list_for_each_entry_safe(es, next, &arch_std_events, list) {
+ FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD);
+ list_del(&es->list);
+ free(es);
+ }
+}
+
+static int save_arch_std_events(void *data, char *name, char *event,
+ char *desc, char *long_desc, char *pmu,
+ char *unit, char *perpkg, char *metric_expr,
+ char *metric_name, char *metric_group)
+{
+ struct event_struct *es;
+ struct stat *sb = data;
+
+ es = malloc(sizeof(*es));
+ if (!es)
+ return -ENOMEM;
+ memset(es, 0, sizeof(*es));
+ FOR_ALL_EVENT_STRUCT_FIELDS(ADD_EVENT_FIELD);
+ list_add_tail(&es->list, &arch_std_events);
+ return 0;
+out_free:
+ FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD);
+ free(es);
+ return -ENOMEM;
+}
+
static void print_events_table_suffix(FILE *outfp)
{
fprintf(outfp, "{\n");
@@ -391,6 +467,32 @@ static char *real_event(const char *name, char *event)
return event;
}
+static int
+try_fixup(const char *fn, char *arch_std, char **event, char **desc,
+ char **name, char **long_desc, char **pmu, char **filter,
+ char **perpkg, char **unit, char **metric_expr, char **metric_name,
+ char **metric_group, unsigned long long eventcode)
+{
+ /* try to find matching event from arch standard values */
+ struct event_struct *es;
+
+ list_for_each_entry(es, &arch_std_events, list) {
+ if (!strcmp(arch_std, es->name)) {
+ if (!eventcode && es->event) {
+ /* allow EventCode to be overridden */
+ free(*event);
+ *event = NULL;
+ }
+ FOR_ALL_EVENT_STRUCT_FIELDS(TRY_FIXUP_FIELD);
+ return 0;
+ }
+ }
+
+ pr_err("%s: could not find matching %s for %s\n",
+ prog, arch_std, fn);
+ return -1;
+}
+
/* Call func with each event in the json file */
int json_events(const char *fn,
int (*func)(void *data, char *name, char *event, char *desc,
@@ -426,6 +528,7 @@ int json_events(const char *fn,
char *metric_expr = NULL;
char *metric_name = NULL;
char *metric_group = NULL;
+ char *arch_std = NULL;
unsigned long long eventcode = 0;
struct msrmap *msr = NULL;
jsmntok_t *msrval = NULL;
@@ -511,6 +614,10 @@ int json_events(const char *fn,
addfield(map, &metric_expr, "", "", val);
for (s = metric_expr; *s; s++)
*s = tolower(*s);
+ } else if (json_streq(map, field, "ArchStdEvent")) {
+ addfield(map, &arch_std, "", "", val);
+ for (s = arch_std; *s; s++)
+ *s = tolower(*s);
}
/* ignore unknown fields */
}
@@ -535,8 +642,21 @@ int json_events(const char *fn,
if (name)
fixname(name);
+ if (arch_std) {
+ /*
+ * An arch standard event is referenced, so try to
+ * fixup any unassigned values.
+ */
+ err = try_fixup(fn, arch_std, &event, &desc, &name,
+ &long_desc, &pmu, &filter, &perpkg,
+ &unit, &metric_expr, &metric_name,
+ &metric_group, eventcode);
+ if (err)
+ goto free_strings;
+ }
err = func(data, name, real_event(name, event), desc, long_desc,
pmu, unit, perpkg, metric_expr, metric_name, metric_group);
+free_strings:
free(event);
free(desc);
free(name);
@@ -549,6 +669,8 @@ int json_events(const char *fn,
free(metric_expr);
free(metric_name);
free(metric_group);
+ free(arch_std);
+
if (err)
break;
tok += j;
@@ -773,6 +895,32 @@ static int is_leaf_dir(const char *fpath)
return res;
}
+static int is_json_file(const char *name)
+{
+ const char *suffix;
+
+ if (strlen(name) < 5)
+ return 0;
+
+ suffix = name + strlen(name) - 5;
+
+ if (strncmp(suffix, ".json", 5) == 0)
+ return 1;
+ return 0;
+}
+
+static int preprocess_arch_std_files(const char *fpath, const struct stat *sb,
+ int typeflag, struct FTW *ftwbuf)
+{
+ int level = ftwbuf->level;
+ int is_file = typeflag == FTW_F;
+
+ if (level == 1 && is_file && is_json_file(fpath))
+ return json_events(fpath, save_arch_std_events, (void *)sb);
+
+ return 0;
+}
+
static int process_one_file(const char *fpath, const struct stat *sb,
int typeflag, struct FTW *ftwbuf)
{
@@ -850,9 +998,7 @@ static int process_one_file(const char *fpath, const struct stat *sb,
* ignore it. It could be a readme.txt for instance.
*/
if (is_file) {
- char *suffix = bname + strlen(bname) - 5;
-
- if (strncmp(suffix, ".json", 5)) {
+ if (!is_json_file(bname)) {
pr_info("%s: Ignoring file without .json suffix %s\n", prog,
fpath);
return 0;
@@ -958,12 +1104,26 @@ int main(int argc, char *argv[])
maxfds = get_maxfds();
mapfile = NULL;
+ rc = nftw(ldirname, preprocess_arch_std_files, maxfds, 0);
+ if (rc && verbose) {
+ pr_info("%s: Error preprocessing arch standard files %s\n",
+ prog, ldirname);
+ goto empty_map;
+ } else if (rc < 0) {
+ /* Make build fail */
+ free_arch_std_events();
+ return 1;
+ } else if (rc) {
+ goto empty_map;
+ }
+
rc = nftw(ldirname, process_one_file, maxfds, 0);
if (rc && verbose) {
pr_info("%s: Error walking file tree %s\n", prog, ldirname);
goto empty_map;
} else if (rc < 0) {
/* Make build fail */
+ free_arch_std_events();
return 1;
} else if (rc) {
goto empty_map;
@@ -988,5 +1148,6 @@ int main(int argc, char *argv[])
empty_map:
fclose(eventsfp);
create_empty_mapping(output_file);
+ free_arch_std_events();
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v3 07/11] perf vendor events: add support for arch standard events
@ 2018-03-08 10:58 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: linux-arm-kernel
For some architectures (like arm), there are architecture-
defined events. Sometimes these events may be "recommended"
according to the architecture standard, in that the
implementer is free ignore the "recommendation" and create
its custom event.
This patch adds support for parsing standard events from
arch-defined JSONs, and fixing up vendor events when they
have implemented these events as standard.
Support is also ensured that the vendor may implement their
own custom events.
A new step is added to the pmu events parsing to fix up the
vendor events with the arch-standard events.
The arch-defined JSONs must be placed in the arch root
folder for preprocessing prior to tree JSON processing.
In the vendor JSON, to specify that the arch event is
supported, the keyword "ArchStdEvent" should be used,
like this:
[
{
"ArchStdEvent": "L1D_CACHE_WR",
},
]
Matching is based on the "EventName" field in the
architecture JSON.
No other JSON objects are strictly required. However,
for other objects added, these take precedence over
architecture defined standard events, thus supporting
separate events which have the same event code.
Signed-off-by: John Garry <john.garry@huawei.com>
---
tools/perf/pmu-events/Build | 2 +
tools/perf/pmu-events/README | 6 ++
tools/perf/pmu-events/jevents.c | 167 +++++++++++++++++++++++++++++++++++++++-
3 files changed, 172 insertions(+), 3 deletions(-)
diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build
index 999a4e8..1778391 100644
--- a/tools/perf/pmu-events/Build
+++ b/tools/perf/pmu-events/Build
@@ -1,10 +1,12 @@
hostprogs := jevents
jevents-y += json.o jsmn.o jevents.o
+CHOSTFLAGS_jevents.o = -I$(srctree)/tools/include
pmu-events-y += pmu-events.o
JDIR = pmu-events/arch/$(SRCARCH)
JSON = $(shell [ -d $(JDIR) ] && \
find $(JDIR) -name '*.json' -o -name 'mapfile.csv')
+
#
# Locate/process JSON files in pmu-events/arch/
# directory and create tables in pmu-events.c.
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
index 655286f..e62b09b 100644
--- a/tools/perf/pmu-events/README
+++ b/tools/perf/pmu-events/README
@@ -16,6 +16,12 @@ tree tools/perf/pmu-events/arch/foo.
- Directories are traversed, but all other files are ignored.
+ - To reduce JSON event duplication per architecture, platform JSONs may
+ use "ArchStdEvent" keyword to dereference an "Architecture standard
+ events", defined in architecture standard JSONs.
+ Architecture standard JSONs must be located in the architecture root
+ folder. Matching is based on the "EventName" field.
+
The PMU events supported by a CPU model are expected to grouped into topics
such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic
should be placed in a separate JSON file - where the file name identifies
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 7b9e210..9b970a0 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -44,6 +44,7 @@
#include <sys/resource.h> /* getrlimit */
#include <ftw.h>
#include <sys/stat.h>
+#include <linux/list.h>
#include "jsmn.h"
#include "json.h"
#include "jevents.h"
@@ -350,6 +351,81 @@ static int print_events_table_entry(void *data, char *name, char *event,
return 0;
}
+struct event_struct {
+ struct list_head list;
+ char *name;
+ char *event;
+ char *desc;
+ char *long_desc;
+ char *pmu;
+ char *unit;
+ char *perpkg;
+ char *metric_expr;
+ char *metric_name;
+ char *metric_group;
+};
+
+#define ADD_EVENT_FIELD(field) do { if (field) { \
+ es->field = strdup(field); \
+ if (!es->field) \
+ goto out_free; \
+} } while (0)
+
+#define FREE_EVENT_FIELD(field) free(es->field)
+
+#define TRY_FIXUP_FIELD(field) do { if (es->field && !*field) {\
+ *field = strdup(es->field); \
+ if (!*field) \
+ return -ENOMEM; \
+} } while (0)
+
+#define FOR_ALL_EVENT_STRUCT_FIELDS(op) do { \
+ op(name); \
+ op(event); \
+ op(desc); \
+ op(long_desc); \
+ op(pmu); \
+ op(unit); \
+ op(perpkg); \
+ op(metric_expr); \
+ op(metric_name); \
+ op(metric_group); \
+} while (0)
+
+static LIST_HEAD(arch_std_events);
+
+static void free_arch_std_events(void)
+{
+ struct event_struct *es, *next;
+
+ list_for_each_entry_safe(es, next, &arch_std_events, list) {
+ FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD);
+ list_del(&es->list);
+ free(es);
+ }
+}
+
+static int save_arch_std_events(void *data, char *name, char *event,
+ char *desc, char *long_desc, char *pmu,
+ char *unit, char *perpkg, char *metric_expr,
+ char *metric_name, char *metric_group)
+{
+ struct event_struct *es;
+ struct stat *sb = data;
+
+ es = malloc(sizeof(*es));
+ if (!es)
+ return -ENOMEM;
+ memset(es, 0, sizeof(*es));
+ FOR_ALL_EVENT_STRUCT_FIELDS(ADD_EVENT_FIELD);
+ list_add_tail(&es->list, &arch_std_events);
+ return 0;
+out_free:
+ FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD);
+ free(es);
+ return -ENOMEM;
+}
+
static void print_events_table_suffix(FILE *outfp)
{
fprintf(outfp, "{\n");
@@ -391,6 +467,32 @@ static char *real_event(const char *name, char *event)
return event;
}
+static int
+try_fixup(const char *fn, char *arch_std, char **event, char **desc,
+ char **name, char **long_desc, char **pmu, char **filter,
+ char **perpkg, char **unit, char **metric_expr, char **metric_name,
+ char **metric_group, unsigned long long eventcode)
+{
+ /* try to find matching event from arch standard values */
+ struct event_struct *es;
+
+ list_for_each_entry(es, &arch_std_events, list) {
+ if (!strcmp(arch_std, es->name)) {
+ if (!eventcode && es->event) {
+ /* allow EventCode to be overridden */
+ free(*event);
+ *event = NULL;
+ }
+ FOR_ALL_EVENT_STRUCT_FIELDS(TRY_FIXUP_FIELD);
+ return 0;
+ }
+ }
+
+ pr_err("%s: could not find matching %s for %s\n",
+ prog, arch_std, fn);
+ return -1;
+}
+
/* Call func with each event in the json file */
int json_events(const char *fn,
int (*func)(void *data, char *name, char *event, char *desc,
@@ -426,6 +528,7 @@ int json_events(const char *fn,
char *metric_expr = NULL;
char *metric_name = NULL;
char *metric_group = NULL;
+ char *arch_std = NULL;
unsigned long long eventcode = 0;
struct msrmap *msr = NULL;
jsmntok_t *msrval = NULL;
@@ -511,6 +614,10 @@ int json_events(const char *fn,
addfield(map, &metric_expr, "", "", val);
for (s = metric_expr; *s; s++)
*s = tolower(*s);
+ } else if (json_streq(map, field, "ArchStdEvent")) {
+ addfield(map, &arch_std, "", "", val);
+ for (s = arch_std; *s; s++)
+ *s = tolower(*s);
}
/* ignore unknown fields */
}
@@ -535,8 +642,21 @@ int json_events(const char *fn,
if (name)
fixname(name);
+ if (arch_std) {
+ /*
+ * An arch standard event is referenced, so try to
+ * fixup any unassigned values.
+ */
+ err = try_fixup(fn, arch_std, &event, &desc, &name,
+ &long_desc, &pmu, &filter, &perpkg,
+ &unit, &metric_expr, &metric_name,
+ &metric_group, eventcode);
+ if (err)
+ goto free_strings;
+ }
err = func(data, name, real_event(name, event), desc, long_desc,
pmu, unit, perpkg, metric_expr, metric_name, metric_group);
+free_strings:
free(event);
free(desc);
free(name);
@@ -549,6 +669,8 @@ int json_events(const char *fn,
free(metric_expr);
free(metric_name);
free(metric_group);
+ free(arch_std);
+
if (err)
break;
tok += j;
@@ -773,6 +895,32 @@ static int is_leaf_dir(const char *fpath)
return res;
}
+static int is_json_file(const char *name)
+{
+ const char *suffix;
+
+ if (strlen(name) < 5)
+ return 0;
+
+ suffix = name + strlen(name) - 5;
+
+ if (strncmp(suffix, ".json", 5) == 0)
+ return 1;
+ return 0;
+}
+
+static int preprocess_arch_std_files(const char *fpath, const struct stat *sb,
+ int typeflag, struct FTW *ftwbuf)
+{
+ int level = ftwbuf->level;
+ int is_file = typeflag == FTW_F;
+
+ if (level == 1 && is_file && is_json_file(fpath))
+ return json_events(fpath, save_arch_std_events, (void *)sb);
+
+ return 0;
+}
+
static int process_one_file(const char *fpath, const struct stat *sb,
int typeflag, struct FTW *ftwbuf)
{
@@ -850,9 +998,7 @@ static int process_one_file(const char *fpath, const struct stat *sb,
* ignore it. It could be a readme.txt for instance.
*/
if (is_file) {
- char *suffix = bname + strlen(bname) - 5;
-
- if (strncmp(suffix, ".json", 5)) {
+ if (!is_json_file(bname)) {
pr_info("%s: Ignoring file without .json suffix %s\n", prog,
fpath);
return 0;
@@ -958,12 +1104,26 @@ int main(int argc, char *argv[])
maxfds = get_maxfds();
mapfile = NULL;
+ rc = nftw(ldirname, preprocess_arch_std_files, maxfds, 0);
+ if (rc && verbose) {
+ pr_info("%s: Error preprocessing arch standard files %s\n",
+ prog, ldirname);
+ goto empty_map;
+ } else if (rc < 0) {
+ /* Make build fail */
+ free_arch_std_events();
+ return 1;
+ } else if (rc) {
+ goto empty_map;
+ }
+
rc = nftw(ldirname, process_one_file, maxfds, 0);
if (rc && verbose) {
pr_info("%s: Error walking file tree %s\n", prog, ldirname);
goto empty_map;
} else if (rc < 0) {
/* Make build fail */
+ free_arch_std_events();
return 1;
} else if (rc) {
goto empty_map;
@@ -988,5 +1148,6 @@ int main(int argc, char *argv[])
empty_map:
fclose(eventsfp);
create_empty_mapping(output_file);
+ free_arch_std_events();
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [tip:perf/core] perf vendor events: Add support for arch standard events
2018-03-08 10:58 ` John Garry
(?)
@ 2018-03-20 6:24 ` tip-bot for John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: tip-bot for John Garry @ 2018-03-20 6:24 UTC (permalink / raw)
To: linux-tip-commits
Cc: hpa, acme, ganapatrao.kulkarni, jolsa, will.deacon, mingo,
john.garry, tglx, wcohen, peterz, ak, zhangshaokun, linux-kernel,
alexander.shishkin, namhyung
Commit-ID: e9d32c1bf0cd7a98358ec4aa1625bf2b3459b9ac
Gitweb: https://git.kernel.org/tip/e9d32c1bf0cd7a98358ec4aa1625bf2b3459b9ac
Author: John Garry <john.garry@huawei.com>
AuthorDate: Thu, 8 Mar 2018 18:58:32 +0800
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Fri, 16 Mar 2018 13:54:35 -0300
perf vendor events: Add support for arch standard events
For some architectures (like arm), there are architecture- defined
events. Sometimes these events may be "recommended" according to the
architecture standard, in that the implementer is free ignore the
"recommendation" and create its custom event.
This patch adds support for parsing standard events from arch-defined
JSONs, and fixing up vendor events when they have implemented these
events as standard.
Support is also ensured that the vendor may implement their own custom
events.
A new step is added to the pmu events parsing to fix up the vendor
events with the arch-standard events.
The arch-defined JSONs must be placed in the arch root folder for
preprocessing prior to tree JSON processing.
In the vendor JSON, to specify that the arch event is supported, the
keyword "ArchStdEvent" should be used, like this:
[
{
"ArchStdEvent": "L1D_CACHE_WR",
},
]
Matching is based on the "EventName" field in the architecture JSON.
No other JSON objects are strictly required. However, for other objects
added, these take precedence over architecture defined standard events,
thus supporting separate events which have the same event code.
Signed-off-by: John Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-8-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/Build | 2 +
tools/perf/pmu-events/README | 6 ++
tools/perf/pmu-events/jevents.c | 167 +++++++++++++++++++++++++++++++++++++++-
3 files changed, 172 insertions(+), 3 deletions(-)
diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build
index 999a4e878162..17783913d330 100644
--- a/tools/perf/pmu-events/Build
+++ b/tools/perf/pmu-events/Build
@@ -1,10 +1,12 @@
hostprogs := jevents
jevents-y += json.o jsmn.o jevents.o
+CHOSTFLAGS_jevents.o = -I$(srctree)/tools/include
pmu-events-y += pmu-events.o
JDIR = pmu-events/arch/$(SRCARCH)
JSON = $(shell [ -d $(JDIR) ] && \
find $(JDIR) -name '*.json' -o -name 'mapfile.csv')
+
#
# Locate/process JSON files in pmu-events/arch/
# directory and create tables in pmu-events.c.
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
index 655286ff8767..e62b09b6a844 100644
--- a/tools/perf/pmu-events/README
+++ b/tools/perf/pmu-events/README
@@ -16,6 +16,12 @@ tree tools/perf/pmu-events/arch/foo.
- Directories are traversed, but all other files are ignored.
+ - To reduce JSON event duplication per architecture, platform JSONs may
+ use "ArchStdEvent" keyword to dereference an "Architecture standard
+ events", defined in architecture standard JSONs.
+ Architecture standard JSONs must be located in the architecture root
+ folder. Matching is based on the "EventName" field.
+
The PMU events supported by a CPU model are expected to grouped into topics
such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic
should be placed in a separate JSON file - where the file name identifies
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 0981d313064f..db3a594ee1e4 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -45,6 +45,7 @@
#include <sys/resource.h> /* getrlimit */
#include <ftw.h>
#include <sys/stat.h>
+#include <linux/list.h>
#include "jsmn.h"
#include "json.h"
#include "jevents.h"
@@ -351,6 +352,81 @@ static int print_events_table_entry(void *data, char *name, char *event,
return 0;
}
+struct event_struct {
+ struct list_head list;
+ char *name;
+ char *event;
+ char *desc;
+ char *long_desc;
+ char *pmu;
+ char *unit;
+ char *perpkg;
+ char *metric_expr;
+ char *metric_name;
+ char *metric_group;
+};
+
+#define ADD_EVENT_FIELD(field) do { if (field) { \
+ es->field = strdup(field); \
+ if (!es->field) \
+ goto out_free; \
+} } while (0)
+
+#define FREE_EVENT_FIELD(field) free(es->field)
+
+#define TRY_FIXUP_FIELD(field) do { if (es->field && !*field) {\
+ *field = strdup(es->field); \
+ if (!*field) \
+ return -ENOMEM; \
+} } while (0)
+
+#define FOR_ALL_EVENT_STRUCT_FIELDS(op) do { \
+ op(name); \
+ op(event); \
+ op(desc); \
+ op(long_desc); \
+ op(pmu); \
+ op(unit); \
+ op(perpkg); \
+ op(metric_expr); \
+ op(metric_name); \
+ op(metric_group); \
+} while (0)
+
+static LIST_HEAD(arch_std_events);
+
+static void free_arch_std_events(void)
+{
+ struct event_struct *es, *next;
+
+ list_for_each_entry_safe(es, next, &arch_std_events, list) {
+ FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD);
+ list_del(&es->list);
+ free(es);
+ }
+}
+
+static int save_arch_std_events(void *data, char *name, char *event,
+ char *desc, char *long_desc, char *pmu,
+ char *unit, char *perpkg, char *metric_expr,
+ char *metric_name, char *metric_group)
+{
+ struct event_struct *es;
+ struct stat *sb = data;
+
+ es = malloc(sizeof(*es));
+ if (!es)
+ return -ENOMEM;
+ memset(es, 0, sizeof(*es));
+ FOR_ALL_EVENT_STRUCT_FIELDS(ADD_EVENT_FIELD);
+ list_add_tail(&es->list, &arch_std_events);
+ return 0;
+out_free:
+ FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD);
+ free(es);
+ return -ENOMEM;
+}
+
static void print_events_table_suffix(FILE *outfp)
{
fprintf(outfp, "{\n");
@@ -392,6 +468,32 @@ static char *real_event(const char *name, char *event)
return event;
}
+static int
+try_fixup(const char *fn, char *arch_std, char **event, char **desc,
+ char **name, char **long_desc, char **pmu, char **filter,
+ char **perpkg, char **unit, char **metric_expr, char **metric_name,
+ char **metric_group, unsigned long long eventcode)
+{
+ /* try to find matching event from arch standard values */
+ struct event_struct *es;
+
+ list_for_each_entry(es, &arch_std_events, list) {
+ if (!strcmp(arch_std, es->name)) {
+ if (!eventcode && es->event) {
+ /* allow EventCode to be overridden */
+ free(*event);
+ *event = NULL;
+ }
+ FOR_ALL_EVENT_STRUCT_FIELDS(TRY_FIXUP_FIELD);
+ return 0;
+ }
+ }
+
+ pr_err("%s: could not find matching %s for %s\n",
+ prog, arch_std, fn);
+ return -1;
+}
+
/* Call func with each event in the json file */
int json_events(const char *fn,
int (*func)(void *data, char *name, char *event, char *desc,
@@ -427,6 +529,7 @@ int json_events(const char *fn,
char *metric_expr = NULL;
char *metric_name = NULL;
char *metric_group = NULL;
+ char *arch_std = NULL;
unsigned long long eventcode = 0;
struct msrmap *msr = NULL;
jsmntok_t *msrval = NULL;
@@ -512,6 +615,10 @@ int json_events(const char *fn,
addfield(map, &metric_expr, "", "", val);
for (s = metric_expr; *s; s++)
*s = tolower(*s);
+ } else if (json_streq(map, field, "ArchStdEvent")) {
+ addfield(map, &arch_std, "", "", val);
+ for (s = arch_std; *s; s++)
+ *s = tolower(*s);
}
/* ignore unknown fields */
}
@@ -536,8 +643,21 @@ int json_events(const char *fn,
if (name)
fixname(name);
+ if (arch_std) {
+ /*
+ * An arch standard event is referenced, so try to
+ * fixup any unassigned values.
+ */
+ err = try_fixup(fn, arch_std, &event, &desc, &name,
+ &long_desc, &pmu, &filter, &perpkg,
+ &unit, &metric_expr, &metric_name,
+ &metric_group, eventcode);
+ if (err)
+ goto free_strings;
+ }
err = func(data, name, real_event(name, event), desc, long_desc,
pmu, unit, perpkg, metric_expr, metric_name, metric_group);
+free_strings:
free(event);
free(desc);
free(name);
@@ -550,6 +670,8 @@ int json_events(const char *fn,
free(metric_expr);
free(metric_name);
free(metric_group);
+ free(arch_std);
+
if (err)
break;
tok += j;
@@ -777,6 +899,32 @@ static int is_leaf_dir(const char *fpath)
return res;
}
+static int is_json_file(const char *name)
+{
+ const char *suffix;
+
+ if (strlen(name) < 5)
+ return 0;
+
+ suffix = name + strlen(name) - 5;
+
+ if (strncmp(suffix, ".json", 5) == 0)
+ return 1;
+ return 0;
+}
+
+static int preprocess_arch_std_files(const char *fpath, const struct stat *sb,
+ int typeflag, struct FTW *ftwbuf)
+{
+ int level = ftwbuf->level;
+ int is_file = typeflag == FTW_F;
+
+ if (level == 1 && is_file && is_json_file(fpath))
+ return json_events(fpath, save_arch_std_events, (void *)sb);
+
+ return 0;
+}
+
static int process_one_file(const char *fpath, const struct stat *sb,
int typeflag, struct FTW *ftwbuf)
{
@@ -854,9 +1002,7 @@ static int process_one_file(const char *fpath, const struct stat *sb,
* ignore it. It could be a readme.txt for instance.
*/
if (is_file) {
- char *suffix = bname + strlen(bname) - 5;
-
- if (strncmp(suffix, ".json", 5)) {
+ if (!is_json_file(bname)) {
pr_info("%s: Ignoring file without .json suffix %s\n", prog,
fpath);
return 0;
@@ -962,12 +1108,26 @@ int main(int argc, char *argv[])
maxfds = get_maxfds();
mapfile = NULL;
+ rc = nftw(ldirname, preprocess_arch_std_files, maxfds, 0);
+ if (rc && verbose) {
+ pr_info("%s: Error preprocessing arch standard files %s\n",
+ prog, ldirname);
+ goto empty_map;
+ } else if (rc < 0) {
+ /* Make build fail */
+ free_arch_std_events();
+ return 1;
+ } else if (rc) {
+ goto empty_map;
+ }
+
rc = nftw(ldirname, process_one_file, maxfds, 0);
if (rc && verbose) {
pr_info("%s: Error walking file tree %s\n", prog, ldirname);
goto empty_map;
} else if (rc < 0) {
/* Make build fail */
+ free_arch_std_events();
return 1;
} else if (rc) {
goto empty_map;
@@ -992,5 +1152,6 @@ int main(int argc, char *argv[])
empty_map:
fclose(eventsfp);
create_empty_mapping(output_file);
+ free_arch_std_events();
return 0;
}
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v3 08/11] perf vendor events arm64: add armv8-recommended.json
2018-03-08 10:58 ` John Garry
@ 2018-03-08 10:58 ` John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: jolsa, ak, peterz, mingo, acme, alexander.shishkin, namhyung,
wcohen, will.deacon, ganapatrao.kulkarni
Cc: linuxarm, linux-kernel, linux-arm-kernel, zhangshaokun, John Garry
Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
The JSON is copied from ARMv8 architecture reference manual,
available here:
https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
.../pmu-events/arch/arm64/armv8-recommended.json | 452 +++++++++++++++++++++
1 file changed, 452 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/armv8-recommended.json
diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
new file mode 100644
index 0000000..6328828
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
@@ -0,0 +1,452 @@
+[
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, read",
+ "EventCode": "0x40",
+ "EventName": "L1D_CACHE_RD",
+ "BriefDescription": "L1D cache access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, write",
+ "EventCode": "0x41",
+ "EventName": "L1D_CACHE_WR",
+ "BriefDescription": "L1D cache access, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, read",
+ "EventCode": "0x42",
+ "EventName": "L1D_CACHE_REFILL_RD",
+ "BriefDescription": "L1D cache refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, write",
+ "EventCode": "0x43",
+ "EventName": "L1D_CACHE_REFILL_WR",
+ "BriefDescription": "L1D cache refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, inner",
+ "EventCode": "0x44",
+ "EventName": "L1D_CACHE_REFILL_INNER",
+ "BriefDescription": "L1D cache refill, inner"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, outer",
+ "EventCode": "0x45",
+ "EventName": "L1D_CACHE_REFILL_OUTER",
+ "BriefDescription": "L1D cache refill, outer"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
+ "EventCode": "0x46",
+ "EventName": "L1D_CACHE_WB_VICTIM",
+ "BriefDescription": "L1D cache Write-Back, victim"
+ },
+ {
+ "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
+ "EventCode": "0x47",
+ "EventName": "L1D_CACHE_WB_CLEAN",
+ "BriefDescription": "L1D cache Write-Back, cleaning and coherency"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache invalidate",
+ "EventCode": "0x48",
+ "EventName": "L1D_CACHE_INVAL",
+ "BriefDescription": "L1D cache invalidate"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, read",
+ "EventCode": "0x4C",
+ "EventName": "L1D_TLB_REFILL_RD",
+ "BriefDescription": "L1D tlb refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, write",
+ "EventCode": "0x4D",
+ "EventName": "L1D_TLB_REFILL_WR",
+ "BriefDescription": "L1D tlb refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+ "EventCode": "0x4E",
+ "EventName": "L1D_TLB_RD",
+ "BriefDescription": "L1D tlb access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+ "EventCode": "0x4F",
+ "EventName": "L1D_TLB_WR",
+ "BriefDescription": "L1D tlb access, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache access, read",
+ "EventCode": "0x50",
+ "EventName": "L2D_CACHE_RD",
+ "BriefDescription": "L2D cache access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache access, write",
+ "EventCode": "0x51",
+ "EventName": "L2D_CACHE_WR",
+ "BriefDescription": "L2D cache access, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache refill, read",
+ "EventCode": "0x52",
+ "EventName": "L2D_CACHE_REFILL_RD",
+ "BriefDescription": "L2D cache refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache refill, write",
+ "EventCode": "0x53",
+ "EventName": "L2D_CACHE_REFILL_WR",
+ "BriefDescription": "L2D cache refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache Write-Back, victim",
+ "EventCode": "0x56",
+ "EventName": "L2D_CACHE_WB_VICTIM",
+ "BriefDescription": "L2D cache Write-Back, victim"
+ },
+ {
+ "PublicDescription": "Level 2 data cache Write-Back, cleaning and coherency",
+ "EventCode": "0x57",
+ "EventName": "L2D_CACHE_WB_CLEAN",
+ "BriefDescription": "L2D cache Write-Back, cleaning and coherency"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache invalidate",
+ "EventCode": "0x58",
+ "EventName": "L2D_CACHE_INVAL",
+ "BriefDescription": "L2D cache invalidate"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB refill, read",
+ "EventCode": "0x5c",
+ "EventName": "L2D_TLB_REFILL_RD",
+ "BriefDescription": "L2D cache refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB refill, write",
+ "EventCode": "0x5d",
+ "EventName": "L2D_TLB_REFILL_WR",
+ "BriefDescription": "L2D cache refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB access, read",
+ "EventCode": "0x5e",
+ "EventName": "L2D_TLB_RD",
+ "BriefDescription": "L2D cache access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB access, write",
+ "EventCode": "0x5f",
+ "EventName": "L2D_TLB_WR",
+ "BriefDescription": "L2D cache access, write"
+ },
+ {
+ "PublicDescription": "Bus access read",
+ "EventCode": "0x60",
+ "EventName": "BUS_ACCESS_RD",
+ "BriefDescription": "Bus access read"
+ },
+ {
+ "PublicDescription": "Bus access write",
+ "EventCode": "0x61",
+ "EventName": "BUS_ACCESS_WR",
+ "BriefDescription": "Bus access write"
+ }
+ {
+ "PublicDescription": "Bus access, Normal, Cacheable, Shareable",
+ "EventCode": "0x62",
+ "EventName": "BUS_ACCESS_SHARED",
+ "BriefDescription": "Bus access, Normal, Cacheable, Shareable"
+ }
+ {
+ "PublicDescription": "Bus access, not Normal, Cacheable, Shareable",
+ "EventCode": "0x63",
+ "EventName": "BUS_ACCESS_NOT_SHARED",
+ "BriefDescription": "Bus access, not Normal, Cacheable, Shareable"
+ }
+ {
+ "PublicDescription": "Bus access, Normal",
+ "EventCode": "0x64",
+ "EventName": "BUS_ACCESS_NORMAL",
+ "BriefDescription": "Bus access, Normal"
+ }
+ {
+ "PublicDescription": "Bus access, peripheral",
+ "EventCode": "0x65",
+ "EventName": "BUS_ACCESS_PERIPH",
+ "BriefDescription": "Bus access, peripheral"
+ }
+ {
+ "PublicDescription": "Data memory access, read",
+ "EventCode": "0x66",
+ "EventName": "MEM_ACCESS_RD",
+ "BriefDescription": "Data memory access, read"
+ }
+ {
+ "PublicDescription": "Data memory access, write",
+ "EventCode": "0x67",
+ "EventName": "MEM_ACCESS_WR",
+ "BriefDescription": "Data memory access, write"
+ }
+ {
+ "PublicDescription": "Unaligned access, read",
+ "EventCode": "0x68",
+ "EventName": "UNALIGNED_LD_SPEC",
+ "BriefDescription": "Unaligned access, read"
+ }
+ {
+ "PublicDescription": "Unaligned access, write",
+ "EventCode": "0x69",
+ "EventName": "UNALIGNED_ST_SPEC",
+ "BriefDescription": "Unaligned access, write"
+ }
+ {
+ "PublicDescription": "Unaligned access",
+ "EventCode": "0x6a",
+ "EventName": "UNALIGNED_LDST_SPEC",
+ "BriefDescription": "Unaligned access"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, LDREX or LDX",
+ "EventCode": "0x6c",
+ "EventName": "LDREX_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, LDREX or LDX"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, STREX or STX pass",
+ "EventCode": "0x6d",
+ "EventName": "STREX_PASS_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, STREX or STX pass"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, STREX or STX fail",
+ "EventCode": "0x6e",
+ "EventName": "STREX_FAIL_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, STREX or STX fail"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, STREX or STX",
+ "EventCode": "0x6f",
+ "EventName": "STREX_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, STREX or STX"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, load",
+ "EventCode": "0x70",
+ "EventName": "LD_SPEC",
+ "BriefDescription": "Operation speculatively executed, load"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, store"
+ "EventCode": "0x71",
+ "EventName": "ST_SPEC",
+ "BriefDescription": "Operation speculatively executed, store"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, load or store",
+ "EventCode": "0x72",
+ "EventName": "LDST_SPEC",
+ "BriefDescription": "Operation speculatively executed, load or store"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, integer data processing",
+ "EventCode": "0x73",
+ "EventName": "DP_SPEC",
+ "BriefDescription": "Operation speculatively executed, integer data processing"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, Advanced SIMD instruction",
+ "EventCode": "0x74",
+ "EventName": "ASE_SPEC",
+ "BriefDescription": "Operation speculatively executed, Advanced SIMD instruction",
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, floating-point instruction",
+ "EventCode": "0x75",
+ "EventName": "VFP_SPEC",
+ "BriefDescription": "Operation speculatively executed, floating-point instruction"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, software change of the PC",
+ "EventCode": "0x76",
+ "EventName": "PC_WRITE_SPEC",
+ "BriefDescription": "Operation speculatively executed, software change of the PC"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, Cryptographic instruction",
+ "EventCode": "0x77",
+ "EventName": "CRYPTO_SPEC",
+ "BriefDescription": "Operation speculatively executed, Cryptographic instruction"
+ }
+ {
+ "PublicDescription": "Branch speculatively executed, immediate branch"
+ "EventCode": "0x78",
+ "EventName": "BR_IMMED_SPEC",
+ "BriefDescription": "Branch speculatively executed, immediate branch"
+ }
+ {
+ "PublicDescription": "Branch speculatively executed, procedure return"
+ "EventCode": "0x79",
+ "EventName": "BR_RETURN_SPEC",
+ "BriefDescription": "Branch speculatively executed, procedure return"
+ }
+ {
+ "PublicDescription": "Branch speculatively executed, indirect branch"
+ "EventCode": "0x7a",
+ "EventName": "BR_INDIRECT_SPEC",
+ "BriefDescription": "Branch speculatively executed, indirect branch"
+ }
+ {
+ "PublicDescription": "Barrier speculatively executed, ISB"
+ "EventCode": "0x7c",
+ "EventName": "ISB_SPEC",
+ "BriefDescription": "Barrier speculatively executed, ISB"
+ }
+ {
+ "PublicDescription": "Barrier speculatively executed, DSB"
+ "EventCode": "0x7d",
+ "EventName": "DSB_SPEC",
+ "BriefDescription": "Barrier speculatively executed, DSB"
+ }
+ {
+ "PublicDescription": "Barrier speculatively executed, DMB"
+ "EventCode": "0x7e",
+ "EventName": "DMB_SPEC",
+ "BriefDescription": "Barrier speculatively executed, DMB"
+ }
+ {
+ "PublicDescription": "Exception taken, Other synchronous"
+ "EventCode": "0x81",
+ "EventName": "EXC_UNDEF",
+ "BriefDescription": "Exception taken, Other synchronous"
+ }
+ {
+ "PublicDescription": "Exception taken, Supervisor Call"
+ "EventCode": "0x82",
+ "EventName": "EXC_SVC",
+ "BriefDescription": "Exception taken, Supervisor Call"
+ }
+ {
+ "PublicDescription": "Exception taken, Instruction Abort"
+ "EventCode": "0x83",
+ "EventName": "EXC_PABORT",
+ "BriefDescription": "Exception taken, Instruction Abort"
+ }
+ {
+ "PublicDescription": "Exception taken, Data Abort and SError"
+ "EventCode": "0x84",
+ "EventName": "EXC_DABORT",
+ "BriefDescription": "Exception taken, Data Abort and SError"
+ }
+ {
+ "PublicDescription": "Exception taken, IRQ"
+ "EventCode": "0x86",
+ "EventName": "EXC_IRQ",
+ "BriefDescription": "Exception taken, IRQ"
+ }
+ {
+ "PublicDescription": "Exception taken, FIQ"
+ "EventCode": "0x87",
+ "EventName": "EXC_FIQ",
+ "BriefDescription": "Exception taken, FIQ"
+ }
+ {
+ "PublicDescription": "Exception taken, Secure Monitor Call"
+ "EventCode": "0x88",
+ "EventName": "EXC_SMC",
+ "BriefDescription": "Exception taken, Secure Monitor Call"
+ }
+ {
+ "PublicDescription": "Exception taken, Hypervisor Call"
+ "EventCode": "0x8a",
+ "EventName": "EXC_HVC",
+ "BriefDescription": "Exception taken, Hypervisor Call"
+ }
+ {
+ "PublicDescription": "Exception taken, Instruction Abort not taken locally"
+ "EventCode": "0x8b",
+ "EventName": "EXC_TRAP_PABORT",
+ "BriefDescription": "Exception taken, Instruction Abort not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, Data Abort or SError not taken locally"
+ "EventCode": "0x8c",
+ "EventName": "EXC_TRAP_DABORT",
+ "BriefDescription": "Exception taken, Data Abort or SError not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, Other traps not taken locally"
+ "EventCode": "0x8d",
+ "EventName": "EXC_TRAP_OTHER",
+ "BriefDescription": "Exception taken, Other traps not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, IRQ not taken locally"
+ "EventCode": "0x8e",
+ "EventName": "EXC_TRAP_IRQ",
+ "BriefDescription": "Exception taken, IRQ not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, FIQ not taken locally"
+ "EventCode": "0x8f",
+ "EventName": "EXC_TRAP_FIQ",
+ "BriefDescription": "Exception taken, FIQ not taken locally"
+ }
+ {
+ "PublicDescription": "Release consistency operation speculatively executed, Load-Acquire"
+ "EventCode": "0x90",
+ "EventName": "RC_LD_SPEC",
+ "BriefDescription": "Release consistency operation speculatively executed, Load-Acquire"
+ }
+ {
+ "PublicDescription": "Release consistency operation speculatively executed, Store-Release"
+ "EventCode": "0x91",
+ "EventName": "RC_ST_SPEC",
+ "BriefDescription": "Release consistency operation speculatively executed, Store-Release"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache access, read"
+ "EventCode": "0xa0",
+ "EventName": "L3D_CACHE_RD",
+ "BriefDescription": "Attributable Level 3 data or unified cache access, read"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache access, write"
+ "EventCode": "0xa1",
+ "EventName": "L3D_CACHE_WR",
+ "BriefDescription": "Attributable Level 3 data or unified cache access, write"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache refill, read"
+ "EventCode": "0xa2",
+ "EventName": "L3D_CACHE_REFILL_RD",
+ "BriefDescription": "Attributable Level 3 data or unified cache refill, read"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache refill, write"
+ "EventCode": "0xa3",
+ "EventName": "L3D_CACHE_REFILL_WR",
+ "BriefDescription": "Attributable Level 3 data or unified cache refill, write"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, victim"
+ "EventCode": "0xa6",
+ "EventName": "L3D_CACHE_WB_VICTIM",
+ "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, victim"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean"
+ "EventCode": "0xa7",
+ "EventName": "L3D_CACHE_WB_CLEAN",
+ "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache access, invalidate"
+ "EventCode": "0xa8",
+ "EventName": "L3D_CACHE_INVAL",
+ "BriefDescription": "Attributable Level 3 data or unified cache access, invalidate"
+ }
+]
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v3 08/11] perf vendor events arm64: add armv8-recommended.json
@ 2018-03-08 10:58 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: linux-arm-kernel
Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
The JSON is copied from ARMv8 architecture reference manual,
available here:
https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
.../pmu-events/arch/arm64/armv8-recommended.json | 452 +++++++++++++++++++++
1 file changed, 452 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/armv8-recommended.json
diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
new file mode 100644
index 0000000..6328828
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
@@ -0,0 +1,452 @@
+[
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, read",
+ "EventCode": "0x40",
+ "EventName": "L1D_CACHE_RD",
+ "BriefDescription": "L1D cache access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, write",
+ "EventCode": "0x41",
+ "EventName": "L1D_CACHE_WR",
+ "BriefDescription": "L1D cache access, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, read",
+ "EventCode": "0x42",
+ "EventName": "L1D_CACHE_REFILL_RD",
+ "BriefDescription": "L1D cache refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, write",
+ "EventCode": "0x43",
+ "EventName": "L1D_CACHE_REFILL_WR",
+ "BriefDescription": "L1D cache refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, inner",
+ "EventCode": "0x44",
+ "EventName": "L1D_CACHE_REFILL_INNER",
+ "BriefDescription": "L1D cache refill, inner"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, outer",
+ "EventCode": "0x45",
+ "EventName": "L1D_CACHE_REFILL_OUTER",
+ "BriefDescription": "L1D cache refill, outer"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
+ "EventCode": "0x46",
+ "EventName": "L1D_CACHE_WB_VICTIM",
+ "BriefDescription": "L1D cache Write-Back, victim"
+ },
+ {
+ "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
+ "EventCode": "0x47",
+ "EventName": "L1D_CACHE_WB_CLEAN",
+ "BriefDescription": "L1D cache Write-Back, cleaning and coherency"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache invalidate",
+ "EventCode": "0x48",
+ "EventName": "L1D_CACHE_INVAL",
+ "BriefDescription": "L1D cache invalidate"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, read",
+ "EventCode": "0x4C",
+ "EventName": "L1D_TLB_REFILL_RD",
+ "BriefDescription": "L1D tlb refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, write",
+ "EventCode": "0x4D",
+ "EventName": "L1D_TLB_REFILL_WR",
+ "BriefDescription": "L1D tlb refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+ "EventCode": "0x4E",
+ "EventName": "L1D_TLB_RD",
+ "BriefDescription": "L1D tlb access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+ "EventCode": "0x4F",
+ "EventName": "L1D_TLB_WR",
+ "BriefDescription": "L1D tlb access, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache access, read",
+ "EventCode": "0x50",
+ "EventName": "L2D_CACHE_RD",
+ "BriefDescription": "L2D cache access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache access, write",
+ "EventCode": "0x51",
+ "EventName": "L2D_CACHE_WR",
+ "BriefDescription": "L2D cache access, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache refill, read",
+ "EventCode": "0x52",
+ "EventName": "L2D_CACHE_REFILL_RD",
+ "BriefDescription": "L2D cache refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache refill, write",
+ "EventCode": "0x53",
+ "EventName": "L2D_CACHE_REFILL_WR",
+ "BriefDescription": "L2D cache refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache Write-Back, victim",
+ "EventCode": "0x56",
+ "EventName": "L2D_CACHE_WB_VICTIM",
+ "BriefDescription": "L2D cache Write-Back, victim"
+ },
+ {
+ "PublicDescription": "Level 2 data cache Write-Back, cleaning and coherency",
+ "EventCode": "0x57",
+ "EventName": "L2D_CACHE_WB_CLEAN",
+ "BriefDescription": "L2D cache Write-Back, cleaning and coherency"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache invalidate",
+ "EventCode": "0x58",
+ "EventName": "L2D_CACHE_INVAL",
+ "BriefDescription": "L2D cache invalidate"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB refill, read",
+ "EventCode": "0x5c",
+ "EventName": "L2D_TLB_REFILL_RD",
+ "BriefDescription": "L2D cache refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB refill, write",
+ "EventCode": "0x5d",
+ "EventName": "L2D_TLB_REFILL_WR",
+ "BriefDescription": "L2D cache refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB access, read",
+ "EventCode": "0x5e",
+ "EventName": "L2D_TLB_RD",
+ "BriefDescription": "L2D cache access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB access, write",
+ "EventCode": "0x5f",
+ "EventName": "L2D_TLB_WR",
+ "BriefDescription": "L2D cache access, write"
+ },
+ {
+ "PublicDescription": "Bus access read",
+ "EventCode": "0x60",
+ "EventName": "BUS_ACCESS_RD",
+ "BriefDescription": "Bus access read"
+ },
+ {
+ "PublicDescription": "Bus access write",
+ "EventCode": "0x61",
+ "EventName": "BUS_ACCESS_WR",
+ "BriefDescription": "Bus access write"
+ }
+ {
+ "PublicDescription": "Bus access, Normal, Cacheable, Shareable",
+ "EventCode": "0x62",
+ "EventName": "BUS_ACCESS_SHARED",
+ "BriefDescription": "Bus access, Normal, Cacheable, Shareable"
+ }
+ {
+ "PublicDescription": "Bus access, not Normal, Cacheable, Shareable",
+ "EventCode": "0x63",
+ "EventName": "BUS_ACCESS_NOT_SHARED",
+ "BriefDescription": "Bus access, not Normal, Cacheable, Shareable"
+ }
+ {
+ "PublicDescription": "Bus access, Normal",
+ "EventCode": "0x64",
+ "EventName": "BUS_ACCESS_NORMAL",
+ "BriefDescription": "Bus access, Normal"
+ }
+ {
+ "PublicDescription": "Bus access, peripheral",
+ "EventCode": "0x65",
+ "EventName": "BUS_ACCESS_PERIPH",
+ "BriefDescription": "Bus access, peripheral"
+ }
+ {
+ "PublicDescription": "Data memory access, read",
+ "EventCode": "0x66",
+ "EventName": "MEM_ACCESS_RD",
+ "BriefDescription": "Data memory access, read"
+ }
+ {
+ "PublicDescription": "Data memory access, write",
+ "EventCode": "0x67",
+ "EventName": "MEM_ACCESS_WR",
+ "BriefDescription": "Data memory access, write"
+ }
+ {
+ "PublicDescription": "Unaligned access, read",
+ "EventCode": "0x68",
+ "EventName": "UNALIGNED_LD_SPEC",
+ "BriefDescription": "Unaligned access, read"
+ }
+ {
+ "PublicDescription": "Unaligned access, write",
+ "EventCode": "0x69",
+ "EventName": "UNALIGNED_ST_SPEC",
+ "BriefDescription": "Unaligned access, write"
+ }
+ {
+ "PublicDescription": "Unaligned access",
+ "EventCode": "0x6a",
+ "EventName": "UNALIGNED_LDST_SPEC",
+ "BriefDescription": "Unaligned access"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, LDREX or LDX",
+ "EventCode": "0x6c",
+ "EventName": "LDREX_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, LDREX or LDX"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, STREX or STX pass",
+ "EventCode": "0x6d",
+ "EventName": "STREX_PASS_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, STREX or STX pass"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, STREX or STX fail",
+ "EventCode": "0x6e",
+ "EventName": "STREX_FAIL_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, STREX or STX fail"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, STREX or STX",
+ "EventCode": "0x6f",
+ "EventName": "STREX_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, STREX or STX"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, load",
+ "EventCode": "0x70",
+ "EventName": "LD_SPEC",
+ "BriefDescription": "Operation speculatively executed, load"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, store"
+ "EventCode": "0x71",
+ "EventName": "ST_SPEC",
+ "BriefDescription": "Operation speculatively executed, store"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, load or store",
+ "EventCode": "0x72",
+ "EventName": "LDST_SPEC",
+ "BriefDescription": "Operation speculatively executed, load or store"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, integer data processing",
+ "EventCode": "0x73",
+ "EventName": "DP_SPEC",
+ "BriefDescription": "Operation speculatively executed, integer data processing"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, Advanced SIMD instruction",
+ "EventCode": "0x74",
+ "EventName": "ASE_SPEC",
+ "BriefDescription": "Operation speculatively executed, Advanced SIMD instruction",
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, floating-point instruction",
+ "EventCode": "0x75",
+ "EventName": "VFP_SPEC",
+ "BriefDescription": "Operation speculatively executed, floating-point instruction"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, software change of the PC",
+ "EventCode": "0x76",
+ "EventName": "PC_WRITE_SPEC",
+ "BriefDescription": "Operation speculatively executed, software change of the PC"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, Cryptographic instruction",
+ "EventCode": "0x77",
+ "EventName": "CRYPTO_SPEC",
+ "BriefDescription": "Operation speculatively executed, Cryptographic instruction"
+ }
+ {
+ "PublicDescription": "Branch speculatively executed, immediate branch"
+ "EventCode": "0x78",
+ "EventName": "BR_IMMED_SPEC",
+ "BriefDescription": "Branch speculatively executed, immediate branch"
+ }
+ {
+ "PublicDescription": "Branch speculatively executed, procedure return"
+ "EventCode": "0x79",
+ "EventName": "BR_RETURN_SPEC",
+ "BriefDescription": "Branch speculatively executed, procedure return"
+ }
+ {
+ "PublicDescription": "Branch speculatively executed, indirect branch"
+ "EventCode": "0x7a",
+ "EventName": "BR_INDIRECT_SPEC",
+ "BriefDescription": "Branch speculatively executed, indirect branch"
+ }
+ {
+ "PublicDescription": "Barrier speculatively executed, ISB"
+ "EventCode": "0x7c",
+ "EventName": "ISB_SPEC",
+ "BriefDescription": "Barrier speculatively executed, ISB"
+ }
+ {
+ "PublicDescription": "Barrier speculatively executed, DSB"
+ "EventCode": "0x7d",
+ "EventName": "DSB_SPEC",
+ "BriefDescription": "Barrier speculatively executed, DSB"
+ }
+ {
+ "PublicDescription": "Barrier speculatively executed, DMB"
+ "EventCode": "0x7e",
+ "EventName": "DMB_SPEC",
+ "BriefDescription": "Barrier speculatively executed, DMB"
+ }
+ {
+ "PublicDescription": "Exception taken, Other synchronous"
+ "EventCode": "0x81",
+ "EventName": "EXC_UNDEF",
+ "BriefDescription": "Exception taken, Other synchronous"
+ }
+ {
+ "PublicDescription": "Exception taken, Supervisor Call"
+ "EventCode": "0x82",
+ "EventName": "EXC_SVC",
+ "BriefDescription": "Exception taken, Supervisor Call"
+ }
+ {
+ "PublicDescription": "Exception taken, Instruction Abort"
+ "EventCode": "0x83",
+ "EventName": "EXC_PABORT",
+ "BriefDescription": "Exception taken, Instruction Abort"
+ }
+ {
+ "PublicDescription": "Exception taken, Data Abort and SError"
+ "EventCode": "0x84",
+ "EventName": "EXC_DABORT",
+ "BriefDescription": "Exception taken, Data Abort and SError"
+ }
+ {
+ "PublicDescription": "Exception taken, IRQ"
+ "EventCode": "0x86",
+ "EventName": "EXC_IRQ",
+ "BriefDescription": "Exception taken, IRQ"
+ }
+ {
+ "PublicDescription": "Exception taken, FIQ"
+ "EventCode": "0x87",
+ "EventName": "EXC_FIQ",
+ "BriefDescription": "Exception taken, FIQ"
+ }
+ {
+ "PublicDescription": "Exception taken, Secure Monitor Call"
+ "EventCode": "0x88",
+ "EventName": "EXC_SMC",
+ "BriefDescription": "Exception taken, Secure Monitor Call"
+ }
+ {
+ "PublicDescription": "Exception taken, Hypervisor Call"
+ "EventCode": "0x8a",
+ "EventName": "EXC_HVC",
+ "BriefDescription": "Exception taken, Hypervisor Call"
+ }
+ {
+ "PublicDescription": "Exception taken, Instruction Abort not taken locally"
+ "EventCode": "0x8b",
+ "EventName": "EXC_TRAP_PABORT",
+ "BriefDescription": "Exception taken, Instruction Abort not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, Data Abort or SError not taken locally"
+ "EventCode": "0x8c",
+ "EventName": "EXC_TRAP_DABORT",
+ "BriefDescription": "Exception taken, Data Abort or SError not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, Other traps not taken locally"
+ "EventCode": "0x8d",
+ "EventName": "EXC_TRAP_OTHER",
+ "BriefDescription": "Exception taken, Other traps not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, IRQ not taken locally"
+ "EventCode": "0x8e",
+ "EventName": "EXC_TRAP_IRQ",
+ "BriefDescription": "Exception taken, IRQ not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, FIQ not taken locally"
+ "EventCode": "0x8f",
+ "EventName": "EXC_TRAP_FIQ",
+ "BriefDescription": "Exception taken, FIQ not taken locally"
+ }
+ {
+ "PublicDescription": "Release consistency operation speculatively executed, Load-Acquire"
+ "EventCode": "0x90",
+ "EventName": "RC_LD_SPEC",
+ "BriefDescription": "Release consistency operation speculatively executed, Load-Acquire"
+ }
+ {
+ "PublicDescription": "Release consistency operation speculatively executed, Store-Release"
+ "EventCode": "0x91",
+ "EventName": "RC_ST_SPEC",
+ "BriefDescription": "Release consistency operation speculatively executed, Store-Release"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache access, read"
+ "EventCode": "0xa0",
+ "EventName": "L3D_CACHE_RD",
+ "BriefDescription": "Attributable Level 3 data or unified cache access, read"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache access, write"
+ "EventCode": "0xa1",
+ "EventName": "L3D_CACHE_WR",
+ "BriefDescription": "Attributable Level 3 data or unified cache access, write"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache refill, read"
+ "EventCode": "0xa2",
+ "EventName": "L3D_CACHE_REFILL_RD",
+ "BriefDescription": "Attributable Level 3 data or unified cache refill, read"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache refill, write"
+ "EventCode": "0xa3",
+ "EventName": "L3D_CACHE_REFILL_WR",
+ "BriefDescription": "Attributable Level 3 data or unified cache refill, write"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, victim"
+ "EventCode": "0xa6",
+ "EventName": "L3D_CACHE_WB_VICTIM",
+ "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, victim"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean"
+ "EventCode": "0xa7",
+ "EventName": "L3D_CACHE_WB_CLEAN",
+ "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache access, invalidate"
+ "EventCode": "0xa8",
+ "EventName": "L3D_CACHE_INVAL",
+ "BriefDescription": "Attributable Level 3 data or unified cache access, invalidate"
+ }
+]
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [tip:perf/core] perf vendor events arm64: Add armv8-recommended.json
2018-03-08 10:58 ` John Garry
(?)
@ 2018-03-20 6:24 ` tip-bot for John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: tip-bot for John Garry @ 2018-03-20 6:24 UTC (permalink / raw)
To: linux-tip-commits
Cc: alexander.shishkin, ak, john.garry, jolsa, linux-kernel, hpa,
ganapatrao.kulkarni, mingo, tglx, acme, namhyung, peterz, wcohen,
will.deacon
Commit-ID: 360b7b03afee042d71ab54ba6ea55daf53edf538
Gitweb: https://git.kernel.org/tip/360b7b03afee042d71ab54ba6ea55daf53edf538
Author: John Garry <john.garry@huawei.com>
AuthorDate: Thu, 8 Mar 2018 18:58:33 +0800
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Fri, 16 Mar 2018 13:54:41 -0300
perf vendor events arm64: Add armv8-recommended.json
Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
The JSON is copied from ARMv8 architecture reference manual, available
here:
https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf
Originally-from: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../pmu-events/arch/arm64/armv8-recommended.json | 452 +++++++++++++++++++++
1 file changed, 452 insertions(+)
diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
new file mode 100644
index 000000000000..6328828c018c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
@@ -0,0 +1,452 @@
+[
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, read",
+ "EventCode": "0x40",
+ "EventName": "L1D_CACHE_RD",
+ "BriefDescription": "L1D cache access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, write",
+ "EventCode": "0x41",
+ "EventName": "L1D_CACHE_WR",
+ "BriefDescription": "L1D cache access, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, read",
+ "EventCode": "0x42",
+ "EventName": "L1D_CACHE_REFILL_RD",
+ "BriefDescription": "L1D cache refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, write",
+ "EventCode": "0x43",
+ "EventName": "L1D_CACHE_REFILL_WR",
+ "BriefDescription": "L1D cache refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, inner",
+ "EventCode": "0x44",
+ "EventName": "L1D_CACHE_REFILL_INNER",
+ "BriefDescription": "L1D cache refill, inner"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, outer",
+ "EventCode": "0x45",
+ "EventName": "L1D_CACHE_REFILL_OUTER",
+ "BriefDescription": "L1D cache refill, outer"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
+ "EventCode": "0x46",
+ "EventName": "L1D_CACHE_WB_VICTIM",
+ "BriefDescription": "L1D cache Write-Back, victim"
+ },
+ {
+ "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
+ "EventCode": "0x47",
+ "EventName": "L1D_CACHE_WB_CLEAN",
+ "BriefDescription": "L1D cache Write-Back, cleaning and coherency"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache invalidate",
+ "EventCode": "0x48",
+ "EventName": "L1D_CACHE_INVAL",
+ "BriefDescription": "L1D cache invalidate"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, read",
+ "EventCode": "0x4C",
+ "EventName": "L1D_TLB_REFILL_RD",
+ "BriefDescription": "L1D tlb refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, write",
+ "EventCode": "0x4D",
+ "EventName": "L1D_TLB_REFILL_WR",
+ "BriefDescription": "L1D tlb refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+ "EventCode": "0x4E",
+ "EventName": "L1D_TLB_RD",
+ "BriefDescription": "L1D tlb access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+ "EventCode": "0x4F",
+ "EventName": "L1D_TLB_WR",
+ "BriefDescription": "L1D tlb access, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache access, read",
+ "EventCode": "0x50",
+ "EventName": "L2D_CACHE_RD",
+ "BriefDescription": "L2D cache access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache access, write",
+ "EventCode": "0x51",
+ "EventName": "L2D_CACHE_WR",
+ "BriefDescription": "L2D cache access, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache refill, read",
+ "EventCode": "0x52",
+ "EventName": "L2D_CACHE_REFILL_RD",
+ "BriefDescription": "L2D cache refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache refill, write",
+ "EventCode": "0x53",
+ "EventName": "L2D_CACHE_REFILL_WR",
+ "BriefDescription": "L2D cache refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache Write-Back, victim",
+ "EventCode": "0x56",
+ "EventName": "L2D_CACHE_WB_VICTIM",
+ "BriefDescription": "L2D cache Write-Back, victim"
+ },
+ {
+ "PublicDescription": "Level 2 data cache Write-Back, cleaning and coherency",
+ "EventCode": "0x57",
+ "EventName": "L2D_CACHE_WB_CLEAN",
+ "BriefDescription": "L2D cache Write-Back, cleaning and coherency"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache invalidate",
+ "EventCode": "0x58",
+ "EventName": "L2D_CACHE_INVAL",
+ "BriefDescription": "L2D cache invalidate"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB refill, read",
+ "EventCode": "0x5c",
+ "EventName": "L2D_TLB_REFILL_RD",
+ "BriefDescription": "L2D cache refill, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB refill, write",
+ "EventCode": "0x5d",
+ "EventName": "L2D_TLB_REFILL_WR",
+ "BriefDescription": "L2D cache refill, write"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB access, read",
+ "EventCode": "0x5e",
+ "EventName": "L2D_TLB_RD",
+ "BriefDescription": "L2D cache access, read"
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data or unified TLB access, write",
+ "EventCode": "0x5f",
+ "EventName": "L2D_TLB_WR",
+ "BriefDescription": "L2D cache access, write"
+ },
+ {
+ "PublicDescription": "Bus access read",
+ "EventCode": "0x60",
+ "EventName": "BUS_ACCESS_RD",
+ "BriefDescription": "Bus access read"
+ },
+ {
+ "PublicDescription": "Bus access write",
+ "EventCode": "0x61",
+ "EventName": "BUS_ACCESS_WR",
+ "BriefDescription": "Bus access write"
+ }
+ {
+ "PublicDescription": "Bus access, Normal, Cacheable, Shareable",
+ "EventCode": "0x62",
+ "EventName": "BUS_ACCESS_SHARED",
+ "BriefDescription": "Bus access, Normal, Cacheable, Shareable"
+ }
+ {
+ "PublicDescription": "Bus access, not Normal, Cacheable, Shareable",
+ "EventCode": "0x63",
+ "EventName": "BUS_ACCESS_NOT_SHARED",
+ "BriefDescription": "Bus access, not Normal, Cacheable, Shareable"
+ }
+ {
+ "PublicDescription": "Bus access, Normal",
+ "EventCode": "0x64",
+ "EventName": "BUS_ACCESS_NORMAL",
+ "BriefDescription": "Bus access, Normal"
+ }
+ {
+ "PublicDescription": "Bus access, peripheral",
+ "EventCode": "0x65",
+ "EventName": "BUS_ACCESS_PERIPH",
+ "BriefDescription": "Bus access, peripheral"
+ }
+ {
+ "PublicDescription": "Data memory access, read",
+ "EventCode": "0x66",
+ "EventName": "MEM_ACCESS_RD",
+ "BriefDescription": "Data memory access, read"
+ }
+ {
+ "PublicDescription": "Data memory access, write",
+ "EventCode": "0x67",
+ "EventName": "MEM_ACCESS_WR",
+ "BriefDescription": "Data memory access, write"
+ }
+ {
+ "PublicDescription": "Unaligned access, read",
+ "EventCode": "0x68",
+ "EventName": "UNALIGNED_LD_SPEC",
+ "BriefDescription": "Unaligned access, read"
+ }
+ {
+ "PublicDescription": "Unaligned access, write",
+ "EventCode": "0x69",
+ "EventName": "UNALIGNED_ST_SPEC",
+ "BriefDescription": "Unaligned access, write"
+ }
+ {
+ "PublicDescription": "Unaligned access",
+ "EventCode": "0x6a",
+ "EventName": "UNALIGNED_LDST_SPEC",
+ "BriefDescription": "Unaligned access"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, LDREX or LDX",
+ "EventCode": "0x6c",
+ "EventName": "LDREX_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, LDREX or LDX"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, STREX or STX pass",
+ "EventCode": "0x6d",
+ "EventName": "STREX_PASS_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, STREX or STX pass"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, STREX or STX fail",
+ "EventCode": "0x6e",
+ "EventName": "STREX_FAIL_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, STREX or STX fail"
+ }
+ {
+ "PublicDescription": "Exclusive operation speculatively executed, STREX or STX",
+ "EventCode": "0x6f",
+ "EventName": "STREX_SPEC",
+ "BriefDescription": "Exclusive operation speculatively executed, STREX or STX"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, load",
+ "EventCode": "0x70",
+ "EventName": "LD_SPEC",
+ "BriefDescription": "Operation speculatively executed, load"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, store"
+ "EventCode": "0x71",
+ "EventName": "ST_SPEC",
+ "BriefDescription": "Operation speculatively executed, store"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, load or store",
+ "EventCode": "0x72",
+ "EventName": "LDST_SPEC",
+ "BriefDescription": "Operation speculatively executed, load or store"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, integer data processing",
+ "EventCode": "0x73",
+ "EventName": "DP_SPEC",
+ "BriefDescription": "Operation speculatively executed, integer data processing"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, Advanced SIMD instruction",
+ "EventCode": "0x74",
+ "EventName": "ASE_SPEC",
+ "BriefDescription": "Operation speculatively executed, Advanced SIMD instruction",
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, floating-point instruction",
+ "EventCode": "0x75",
+ "EventName": "VFP_SPEC",
+ "BriefDescription": "Operation speculatively executed, floating-point instruction"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, software change of the PC",
+ "EventCode": "0x76",
+ "EventName": "PC_WRITE_SPEC",
+ "BriefDescription": "Operation speculatively executed, software change of the PC"
+ }
+ {
+ "PublicDescription": "Operation speculatively executed, Cryptographic instruction",
+ "EventCode": "0x77",
+ "EventName": "CRYPTO_SPEC",
+ "BriefDescription": "Operation speculatively executed, Cryptographic instruction"
+ }
+ {
+ "PublicDescription": "Branch speculatively executed, immediate branch"
+ "EventCode": "0x78",
+ "EventName": "BR_IMMED_SPEC",
+ "BriefDescription": "Branch speculatively executed, immediate branch"
+ }
+ {
+ "PublicDescription": "Branch speculatively executed, procedure return"
+ "EventCode": "0x79",
+ "EventName": "BR_RETURN_SPEC",
+ "BriefDescription": "Branch speculatively executed, procedure return"
+ }
+ {
+ "PublicDescription": "Branch speculatively executed, indirect branch"
+ "EventCode": "0x7a",
+ "EventName": "BR_INDIRECT_SPEC",
+ "BriefDescription": "Branch speculatively executed, indirect branch"
+ }
+ {
+ "PublicDescription": "Barrier speculatively executed, ISB"
+ "EventCode": "0x7c",
+ "EventName": "ISB_SPEC",
+ "BriefDescription": "Barrier speculatively executed, ISB"
+ }
+ {
+ "PublicDescription": "Barrier speculatively executed, DSB"
+ "EventCode": "0x7d",
+ "EventName": "DSB_SPEC",
+ "BriefDescription": "Barrier speculatively executed, DSB"
+ }
+ {
+ "PublicDescription": "Barrier speculatively executed, DMB"
+ "EventCode": "0x7e",
+ "EventName": "DMB_SPEC",
+ "BriefDescription": "Barrier speculatively executed, DMB"
+ }
+ {
+ "PublicDescription": "Exception taken, Other synchronous"
+ "EventCode": "0x81",
+ "EventName": "EXC_UNDEF",
+ "BriefDescription": "Exception taken, Other synchronous"
+ }
+ {
+ "PublicDescription": "Exception taken, Supervisor Call"
+ "EventCode": "0x82",
+ "EventName": "EXC_SVC",
+ "BriefDescription": "Exception taken, Supervisor Call"
+ }
+ {
+ "PublicDescription": "Exception taken, Instruction Abort"
+ "EventCode": "0x83",
+ "EventName": "EXC_PABORT",
+ "BriefDescription": "Exception taken, Instruction Abort"
+ }
+ {
+ "PublicDescription": "Exception taken, Data Abort and SError"
+ "EventCode": "0x84",
+ "EventName": "EXC_DABORT",
+ "BriefDescription": "Exception taken, Data Abort and SError"
+ }
+ {
+ "PublicDescription": "Exception taken, IRQ"
+ "EventCode": "0x86",
+ "EventName": "EXC_IRQ",
+ "BriefDescription": "Exception taken, IRQ"
+ }
+ {
+ "PublicDescription": "Exception taken, FIQ"
+ "EventCode": "0x87",
+ "EventName": "EXC_FIQ",
+ "BriefDescription": "Exception taken, FIQ"
+ }
+ {
+ "PublicDescription": "Exception taken, Secure Monitor Call"
+ "EventCode": "0x88",
+ "EventName": "EXC_SMC",
+ "BriefDescription": "Exception taken, Secure Monitor Call"
+ }
+ {
+ "PublicDescription": "Exception taken, Hypervisor Call"
+ "EventCode": "0x8a",
+ "EventName": "EXC_HVC",
+ "BriefDescription": "Exception taken, Hypervisor Call"
+ }
+ {
+ "PublicDescription": "Exception taken, Instruction Abort not taken locally"
+ "EventCode": "0x8b",
+ "EventName": "EXC_TRAP_PABORT",
+ "BriefDescription": "Exception taken, Instruction Abort not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, Data Abort or SError not taken locally"
+ "EventCode": "0x8c",
+ "EventName": "EXC_TRAP_DABORT",
+ "BriefDescription": "Exception taken, Data Abort or SError not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, Other traps not taken locally"
+ "EventCode": "0x8d",
+ "EventName": "EXC_TRAP_OTHER",
+ "BriefDescription": "Exception taken, Other traps not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, IRQ not taken locally"
+ "EventCode": "0x8e",
+ "EventName": "EXC_TRAP_IRQ",
+ "BriefDescription": "Exception taken, IRQ not taken locally"
+ }
+ {
+ "PublicDescription": "Exception taken, FIQ not taken locally"
+ "EventCode": "0x8f",
+ "EventName": "EXC_TRAP_FIQ",
+ "BriefDescription": "Exception taken, FIQ not taken locally"
+ }
+ {
+ "PublicDescription": "Release consistency operation speculatively executed, Load-Acquire"
+ "EventCode": "0x90",
+ "EventName": "RC_LD_SPEC",
+ "BriefDescription": "Release consistency operation speculatively executed, Load-Acquire"
+ }
+ {
+ "PublicDescription": "Release consistency operation speculatively executed, Store-Release"
+ "EventCode": "0x91",
+ "EventName": "RC_ST_SPEC",
+ "BriefDescription": "Release consistency operation speculatively executed, Store-Release"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache access, read"
+ "EventCode": "0xa0",
+ "EventName": "L3D_CACHE_RD",
+ "BriefDescription": "Attributable Level 3 data or unified cache access, read"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache access, write"
+ "EventCode": "0xa1",
+ "EventName": "L3D_CACHE_WR",
+ "BriefDescription": "Attributable Level 3 data or unified cache access, write"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache refill, read"
+ "EventCode": "0xa2",
+ "EventName": "L3D_CACHE_REFILL_RD",
+ "BriefDescription": "Attributable Level 3 data or unified cache refill, read"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache refill, write"
+ "EventCode": "0xa3",
+ "EventName": "L3D_CACHE_REFILL_WR",
+ "BriefDescription": "Attributable Level 3 data or unified cache refill, write"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, victim"
+ "EventCode": "0xa6",
+ "EventName": "L3D_CACHE_WB_VICTIM",
+ "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, victim"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean"
+ "EventCode": "0xa7",
+ "EventName": "L3D_CACHE_WB_CLEAN",
+ "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean"
+ }
+ {
+ "PublicDescription": "Attributable Level 3 data or unified cache access, invalidate"
+ "EventCode": "0xa8",
+ "EventName": "L3D_CACHE_INVAL",
+ "BriefDescription": "Attributable Level 3 data or unified cache access, invalidate"
+ }
+]
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v3 09/11] perf vendor events arm64: fixup ThunderX2 to use recommended events
2018-03-08 10:58 ` John Garry
@ 2018-03-08 10:58 ` John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: jolsa, ak, peterz, mingo, acme, alexander.shishkin, namhyung,
wcohen, will.deacon, ganapatrao.kulkarni
Cc: linuxarm, linux-kernel, linux-arm-kernel, zhangshaokun, John Garry
This patch fixes the Cavium ThunderX2 JSON to use event definitions
from the ARMv8 recommended events.
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 50 +++++-----------------
1 file changed, 10 insertions(+), 40 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
index 2db45c4..bc03c06 100644
--- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
@@ -1,62 +1,32 @@
[
{
- "PublicDescription": "Attributable Level 1 data cache access, read",
- "EventCode": "0x40",
- "EventName": "l1d_cache_rd",
- "BriefDescription": "L1D cache read",
+ "ArchStdEvent": "L1D_CACHE_RD",
},
{
- "PublicDescription": "Attributable Level 1 data cache access, write ",
- "EventCode": "0x41",
- "EventName": "l1d_cache_wr",
- "BriefDescription": "L1D cache write",
+ "ArchStdEvent": "L1D_CACHE_WR",
},
{
- "PublicDescription": "Attributable Level 1 data cache refill, read",
- "EventCode": "0x42",
- "EventName": "l1d_cache_refill_rd",
- "BriefDescription": "L1D cache refill read",
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD",
},
{
- "PublicDescription": "Attributable Level 1 data cache refill, write",
- "EventCode": "0x43",
- "EventName": "l1d_cache_refill_wr",
- "BriefDescription": "L1D refill write",
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR",
},
{
- "PublicDescription": "Attributable Level 1 data TLB refill, read",
- "EventCode": "0x4C",
- "EventName": "l1d_tlb_refill_rd",
- "BriefDescription": "L1D tlb refill read",
+ "ArchStdEvent": "L1D_TLB_REFILL_RD",
},
{
- "PublicDescription": "Attributable Level 1 data TLB refill, write",
- "EventCode": "0x4D",
- "EventName": "l1d_tlb_refill_wr",
- "BriefDescription": "L1D tlb refill write",
+ "ArchStdEvent": "L1D_TLB_REFILL_WR",
},
{
- "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
- "EventCode": "0x4E",
- "EventName": "l1d_tlb_rd",
- "BriefDescription": "L1D tlb read",
+ "ArchStdEvent": "L1D_TLB_RD",
},
{
- "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
- "EventCode": "0x4F",
- "EventName": "l1d_tlb_wr",
- "BriefDescription": "L1D tlb write",
+ "ArchStdEvent": "L1D_TLB_WR",
},
{
- "PublicDescription": "Bus access read",
- "EventCode": "0x60",
- "EventName": "bus_access_rd",
- "BriefDescription": "Bus access read",
+ "ArchStdEvent": "BUS_ACCESS_RD",
},
{
- "PublicDescription": "Bus access write",
- "EventCode": "0x61",
- "EventName": "bus_access_wr",
- "BriefDescription": "Bus access write",
+ "ArchStdEvent": "BUS_ACCESS_WR",
}
]
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v3 09/11] perf vendor events arm64: fixup ThunderX2 to use recommended events
@ 2018-03-08 10:58 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: linux-arm-kernel
This patch fixes the Cavium ThunderX2 JSON to use event definitions
from the ARMv8 recommended events.
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 50 +++++-----------------
1 file changed, 10 insertions(+), 40 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
index 2db45c4..bc03c06 100644
--- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
@@ -1,62 +1,32 @@
[
{
- "PublicDescription": "Attributable Level 1 data cache access, read",
- "EventCode": "0x40",
- "EventName": "l1d_cache_rd",
- "BriefDescription": "L1D cache read",
+ "ArchStdEvent": "L1D_CACHE_RD",
},
{
- "PublicDescription": "Attributable Level 1 data cache access, write ",
- "EventCode": "0x41",
- "EventName": "l1d_cache_wr",
- "BriefDescription": "L1D cache write",
+ "ArchStdEvent": "L1D_CACHE_WR",
},
{
- "PublicDescription": "Attributable Level 1 data cache refill, read",
- "EventCode": "0x42",
- "EventName": "l1d_cache_refill_rd",
- "BriefDescription": "L1D cache refill read",
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD",
},
{
- "PublicDescription": "Attributable Level 1 data cache refill, write",
- "EventCode": "0x43",
- "EventName": "l1d_cache_refill_wr",
- "BriefDescription": "L1D refill write",
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR",
},
{
- "PublicDescription": "Attributable Level 1 data TLB refill, read",
- "EventCode": "0x4C",
- "EventName": "l1d_tlb_refill_rd",
- "BriefDescription": "L1D tlb refill read",
+ "ArchStdEvent": "L1D_TLB_REFILL_RD",
},
{
- "PublicDescription": "Attributable Level 1 data TLB refill, write",
- "EventCode": "0x4D",
- "EventName": "l1d_tlb_refill_wr",
- "BriefDescription": "L1D tlb refill write",
+ "ArchStdEvent": "L1D_TLB_REFILL_WR",
},
{
- "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
- "EventCode": "0x4E",
- "EventName": "l1d_tlb_rd",
- "BriefDescription": "L1D tlb read",
+ "ArchStdEvent": "L1D_TLB_RD",
},
{
- "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
- "EventCode": "0x4F",
- "EventName": "l1d_tlb_wr",
- "BriefDescription": "L1D tlb write",
+ "ArchStdEvent": "L1D_TLB_WR",
},
{
- "PublicDescription": "Bus access read",
- "EventCode": "0x60",
- "EventName": "bus_access_rd",
- "BriefDescription": "Bus access read",
+ "ArchStdEvent": "BUS_ACCESS_RD",
},
{
- "PublicDescription": "Bus access write",
- "EventCode": "0x61",
- "EventName": "bus_access_wr",
- "BriefDescription": "Bus access write",
+ "ArchStdEvent": "BUS_ACCESS_WR",
}
]
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v3 09/11] perf vendor events arm64: fixup ThunderX2 to use recommended events
2018-03-08 10:58 ` John Garry
@ 2018-03-09 14:36 ` Ganapatrao Kulkarni
-1 siblings, 0 replies; 47+ messages in thread
From: Ganapatrao Kulkarni @ 2018-03-09 14:36 UTC (permalink / raw)
To: John Garry
Cc: Jiri Olsa, ak, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin, namhyung,
William Cohen, Will Deacon, Ganapatrao Kulkarni, Linuxarm,
linux-kernel, linux-arm-kernel, Zhangshaokun
Hi John,
On Thu, Mar 8, 2018 at 4:28 PM, John Garry <john.garry@huawei.com> wrote:
> This patch fixes the Cavium ThunderX2 JSON to use event definitions
> from the ARMv8 recommended events.
>
> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> Signed-off-by: John Garry <john.garry@huawei.com>
> ---
> .../arch/arm64/cavium/thunderx2/core-imp-def.json | 50 +++++-----------------
> 1 file changed, 10 insertions(+), 40 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> index 2db45c4..bc03c06 100644
> --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> @@ -1,62 +1,32 @@
> [
> {
> - "PublicDescription": "Attributable Level 1 data cache access, read",
> - "EventCode": "0x40",
> - "EventName": "l1d_cache_rd",
> - "BriefDescription": "L1D cache read",
> + "ArchStdEvent": "L1D_CACHE_RD",
> },
> {
> - "PublicDescription": "Attributable Level 1 data cache access, write ",
> - "EventCode": "0x41",
> - "EventName": "l1d_cache_wr",
> - "BriefDescription": "L1D cache write",
> + "ArchStdEvent": "L1D_CACHE_WR",
> },
> {
> - "PublicDescription": "Attributable Level 1 data cache refill, read",
> - "EventCode": "0x42",
> - "EventName": "l1d_cache_refill_rd",
> - "BriefDescription": "L1D cache refill read",
> + "ArchStdEvent": "L1D_CACHE_REFILL_RD",
> },
> {
> - "PublicDescription": "Attributable Level 1 data cache refill, write",
> - "EventCode": "0x43",
> - "EventName": "l1d_cache_refill_wr",
> - "BriefDescription": "L1D refill write",
> + "ArchStdEvent": "L1D_CACHE_REFILL_WR",
> },
> {
> - "PublicDescription": "Attributable Level 1 data TLB refill, read",
> - "EventCode": "0x4C",
> - "EventName": "l1d_tlb_refill_rd",
> - "BriefDescription": "L1D tlb refill read",
> + "ArchStdEvent": "L1D_TLB_REFILL_RD",
> },
> {
> - "PublicDescription": "Attributable Level 1 data TLB refill, write",
> - "EventCode": "0x4D",
> - "EventName": "l1d_tlb_refill_wr",
> - "BriefDescription": "L1D tlb refill write",
> + "ArchStdEvent": "L1D_TLB_REFILL_WR",
> },
> {
> - "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
> - "EventCode": "0x4E",
> - "EventName": "l1d_tlb_rd",
> - "BriefDescription": "L1D tlb read",
> + "ArchStdEvent": "L1D_TLB_RD",
> },
> {
> - "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
> - "EventCode": "0x4F",
> - "EventName": "l1d_tlb_wr",
> - "BriefDescription": "L1D tlb write",
> + "ArchStdEvent": "L1D_TLB_WR",
> },
> {
> - "PublicDescription": "Bus access read",
> - "EventCode": "0x60",
> - "EventName": "bus_access_rd",
> - "BriefDescription": "Bus access read",
> + "ArchStdEvent": "BUS_ACCESS_RD",
> },
> {
> - "PublicDescription": "Bus access write",
> - "EventCode": "0x61",
> - "EventName": "bus_access_wr",
> - "BriefDescription": "Bus access write",
> + "ArchStdEvent": "BUS_ACCESS_WR",
> }
> ]
This patch looks ok to me.
i have tried on thunderx2 for few events and it is working fine.
Tested-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> --
> 1.9.1
>
thanks
Ganapat
^ permalink raw reply [flat|nested] 47+ messages in thread* [PATCH v3 09/11] perf vendor events arm64: fixup ThunderX2 to use recommended events
@ 2018-03-09 14:36 ` Ganapatrao Kulkarni
0 siblings, 0 replies; 47+ messages in thread
From: Ganapatrao Kulkarni @ 2018-03-09 14:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi John,
On Thu, Mar 8, 2018 at 4:28 PM, John Garry <john.garry@huawei.com> wrote:
> This patch fixes the Cavium ThunderX2 JSON to use event definitions
> from the ARMv8 recommended events.
>
> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> Signed-off-by: John Garry <john.garry@huawei.com>
> ---
> .../arch/arm64/cavium/thunderx2/core-imp-def.json | 50 +++++-----------------
> 1 file changed, 10 insertions(+), 40 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> index 2db45c4..bc03c06 100644
> --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> @@ -1,62 +1,32 @@
> [
> {
> - "PublicDescription": "Attributable Level 1 data cache access, read",
> - "EventCode": "0x40",
> - "EventName": "l1d_cache_rd",
> - "BriefDescription": "L1D cache read",
> + "ArchStdEvent": "L1D_CACHE_RD",
> },
> {
> - "PublicDescription": "Attributable Level 1 data cache access, write ",
> - "EventCode": "0x41",
> - "EventName": "l1d_cache_wr",
> - "BriefDescription": "L1D cache write",
> + "ArchStdEvent": "L1D_CACHE_WR",
> },
> {
> - "PublicDescription": "Attributable Level 1 data cache refill, read",
> - "EventCode": "0x42",
> - "EventName": "l1d_cache_refill_rd",
> - "BriefDescription": "L1D cache refill read",
> + "ArchStdEvent": "L1D_CACHE_REFILL_RD",
> },
> {
> - "PublicDescription": "Attributable Level 1 data cache refill, write",
> - "EventCode": "0x43",
> - "EventName": "l1d_cache_refill_wr",
> - "BriefDescription": "L1D refill write",
> + "ArchStdEvent": "L1D_CACHE_REFILL_WR",
> },
> {
> - "PublicDescription": "Attributable Level 1 data TLB refill, read",
> - "EventCode": "0x4C",
> - "EventName": "l1d_tlb_refill_rd",
> - "BriefDescription": "L1D tlb refill read",
> + "ArchStdEvent": "L1D_TLB_REFILL_RD",
> },
> {
> - "PublicDescription": "Attributable Level 1 data TLB refill, write",
> - "EventCode": "0x4D",
> - "EventName": "l1d_tlb_refill_wr",
> - "BriefDescription": "L1D tlb refill write",
> + "ArchStdEvent": "L1D_TLB_REFILL_WR",
> },
> {
> - "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
> - "EventCode": "0x4E",
> - "EventName": "l1d_tlb_rd",
> - "BriefDescription": "L1D tlb read",
> + "ArchStdEvent": "L1D_TLB_RD",
> },
> {
> - "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
> - "EventCode": "0x4F",
> - "EventName": "l1d_tlb_wr",
> - "BriefDescription": "L1D tlb write",
> + "ArchStdEvent": "L1D_TLB_WR",
> },
> {
> - "PublicDescription": "Bus access read",
> - "EventCode": "0x60",
> - "EventName": "bus_access_rd",
> - "BriefDescription": "Bus access read",
> + "ArchStdEvent": "BUS_ACCESS_RD",
> },
> {
> - "PublicDescription": "Bus access write",
> - "EventCode": "0x61",
> - "EventName": "bus_access_wr",
> - "BriefDescription": "Bus access write",
> + "ArchStdEvent": "BUS_ACCESS_WR",
> }
> ]
This patch looks ok to me.
i have tried on thunderx2 for few events and it is working fine.
Tested-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> --
> 1.9.1
>
thanks
Ganapat
^ permalink raw reply [flat|nested] 47+ messages in thread
* [tip:perf/core] perf vendor events arm64: Fixup ThunderX2 to use recommended events
2018-03-08 10:58 ` John Garry
(?)
(?)
@ 2018-03-20 6:25 ` tip-bot for John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: tip-bot for John Garry @ 2018-03-20 6:25 UTC (permalink / raw)
To: linux-tip-commits
Cc: namhyung, ak, alexander.shishkin, wcohen, ganapatrao.kulkarni,
hpa, linux-kernel, tglx, acme, john.garry, jolsa, zhangshaokun,
mingo, will.deacon, peterz
Commit-ID: ae43053bd2595dc98f0909505dc1d7e1ed8bd239
Gitweb: https://git.kernel.org/tip/ae43053bd2595dc98f0909505dc1d7e1ed8bd239
Author: John Garry <john.garry@huawei.com>
AuthorDate: Thu, 8 Mar 2018 18:58:34 +0800
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Fri, 16 Mar 2018 13:54:48 -0300
perf vendor events arm64: Fixup ThunderX2 to use recommended events
This patch fixes the Cavium ThunderX2 JSON to use event definitions from
the ARMv8 recommended events.
Signed-off-by: John Garry <john.garry@huawei.com>
Tested-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-10-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 50 +++++-----------------
1 file changed, 10 insertions(+), 40 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
index 2db45c40ebc7..bc03c06c3918 100644
--- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
@@ -1,62 +1,32 @@
[
{
- "PublicDescription": "Attributable Level 1 data cache access, read",
- "EventCode": "0x40",
- "EventName": "l1d_cache_rd",
- "BriefDescription": "L1D cache read",
+ "ArchStdEvent": "L1D_CACHE_RD",
},
{
- "PublicDescription": "Attributable Level 1 data cache access, write ",
- "EventCode": "0x41",
- "EventName": "l1d_cache_wr",
- "BriefDescription": "L1D cache write",
+ "ArchStdEvent": "L1D_CACHE_WR",
},
{
- "PublicDescription": "Attributable Level 1 data cache refill, read",
- "EventCode": "0x42",
- "EventName": "l1d_cache_refill_rd",
- "BriefDescription": "L1D cache refill read",
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD",
},
{
- "PublicDescription": "Attributable Level 1 data cache refill, write",
- "EventCode": "0x43",
- "EventName": "l1d_cache_refill_wr",
- "BriefDescription": "L1D refill write",
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR",
},
{
- "PublicDescription": "Attributable Level 1 data TLB refill, read",
- "EventCode": "0x4C",
- "EventName": "l1d_tlb_refill_rd",
- "BriefDescription": "L1D tlb refill read",
+ "ArchStdEvent": "L1D_TLB_REFILL_RD",
},
{
- "PublicDescription": "Attributable Level 1 data TLB refill, write",
- "EventCode": "0x4D",
- "EventName": "l1d_tlb_refill_wr",
- "BriefDescription": "L1D tlb refill write",
+ "ArchStdEvent": "L1D_TLB_REFILL_WR",
},
{
- "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
- "EventCode": "0x4E",
- "EventName": "l1d_tlb_rd",
- "BriefDescription": "L1D tlb read",
+ "ArchStdEvent": "L1D_TLB_RD",
},
{
- "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
- "EventCode": "0x4F",
- "EventName": "l1d_tlb_wr",
- "BriefDescription": "L1D tlb write",
+ "ArchStdEvent": "L1D_TLB_WR",
},
{
- "PublicDescription": "Bus access read",
- "EventCode": "0x60",
- "EventName": "bus_access_rd",
- "BriefDescription": "Bus access read",
+ "ArchStdEvent": "BUS_ACCESS_RD",
},
{
- "PublicDescription": "Bus access write",
- "EventCode": "0x61",
- "EventName": "bus_access_wr",
- "BriefDescription": "Bus access write",
+ "ArchStdEvent": "BUS_ACCESS_WR",
}
]
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v3 10/11] perf vendor events arm64: fixup A53 to use recommended events
2018-03-08 10:58 ` John Garry
@ 2018-03-08 10:58 ` John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: jolsa, ak, peterz, mingo, acme, alexander.shishkin, namhyung,
wcohen, will.deacon, ganapatrao.kulkarni
Cc: linuxarm, linux-kernel, linux-arm-kernel, zhangshaokun, John Garry
This patch fixes the ARM Cortex-A53 json to use event definition
from the ARMv8 recommended events.
In addition to this change, other changes were made:
- remove stray ','
- remove mirrored events in memory.json and bus.json
- fixed indentation to be consistent with other ARM
JSONs
Cc: William Cohen <wcohen@redhat.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
.../arch/arm64/arm/cortex-a53/branch.json | 14 +++----
.../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 22 ++---------
.../arch/arm64/arm/cortex-a53/cache.json | 40 ++++++++++----------
.../arch/arm64/arm/cortex-a53/memory.json | 14 +------
.../arch/arm64/arm/cortex-a53/other.json | 44 ++++++++++------------
.../arch/arm64/arm/cortex-a53/pipeline.json | 20 +++++-----
6 files changed, 62 insertions(+), 92 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
index 3b62087..0b0e6b2 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
@@ -1,25 +1,23 @@
[
- {,
- "EventCode": "0x7A",
- "EventName": "BR_INDIRECT_SPEC",
- "BriefDescription": "Branch speculatively executed - Indirect branch"
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC",
},
- {,
+ {
"EventCode": "0xC9",
"EventName": "BR_COND",
"BriefDescription": "Conditional branch executed"
},
- {,
+ {
"EventCode": "0xCA",
"EventName": "BR_INDIRECT_MISPRED",
"BriefDescription": "Indirect branch mispredicted"
},
- {,
+ {
"EventCode": "0xCB",
"EventName": "BR_INDIRECT_MISPRED_ADDR",
"BriefDescription": "Indirect branch mispredicted because of address miscompare"
},
- {,
+ {
"EventCode": "0xCC",
"EventName": "BR_COND_MISPRED",
"BriefDescription": "Conditional branch mispredicted"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
index 480d9f7..ce33b25 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
@@ -1,22 +1,8 @@
[
- {,
- "EventCode": "0x60",
- "EventName": "BUS_ACCESS_LD",
- "BriefDescription": "Bus access - Read"
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD",
},
- {,
- "EventCode": "0x61",
- "EventName": "BUS_ACCESS_ST",
- "BriefDescription": "Bus access - Write"
- },
- {,
- "EventCode": "0xC0",
- "EventName": "EXT_MEM_REQ",
- "BriefDescription": "External memory request"
- },
- {,
- "EventCode": "0xC1",
- "EventName": "EXT_MEM_REQ_NC",
- "BriefDescription": "Non-cacheable external memory request"
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR",
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
index 11baad6..5dfbec4 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
@@ -1,27 +1,27 @@
[
- {,
- "EventCode": "0xC2",
- "EventName": "PREFETCH_LINEFILL",
- "BriefDescription": "Linefill because of prefetch"
+ {
+ "EventCode": "0xC2",
+ "EventName": "PREFETCH_LINEFILL",
+ "BriefDescription": "Linefill because of prefetch"
},
- {,
- "EventCode": "0xC3",
- "EventName": "PREFETCH_LINEFILL_DROP",
- "BriefDescription": "Instruction Cache Throttle occurred"
+ {
+ "EventCode": "0xC3",
+ "EventName": "PREFETCH_LINEFILL_DROP",
+ "BriefDescription": "Instruction Cache Throttle occurred"
},
- {,
- "EventCode": "0xC4",
- "EventName": "READ_ALLOC_ENTER",
- "BriefDescription": "Entering read allocate mode"
+ {
+ "EventCode": "0xC4",
+ "EventName": "READ_ALLOC_ENTER",
+ "BriefDescription": "Entering read allocate mode"
},
- {,
- "EventCode": "0xC5",
- "EventName": "READ_ALLOC",
- "BriefDescription": "Read allocate mode"
+ {
+ "EventCode": "0xC5",
+ "EventName": "READ_ALLOC",
+ "BriefDescription": "Read allocate mode"
},
- {,
- "EventCode": "0xC8",
- "EventName": "EXT_SNOOP",
- "BriefDescription": "SCU Snooped data from another CPU for this CPU"
+ {
+ "EventCode": "0xC8",
+ "EventName": "EXT_SNOOP",
+ "BriefDescription": "SCU Snooped data from another CPU for this CPU"
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
index 480d9f7..25ae642 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
@@ -1,20 +1,10 @@
[
- {,
- "EventCode": "0x60",
- "EventName": "BUS_ACCESS_LD",
- "BriefDescription": "Bus access - Read"
- },
- {,
- "EventCode": "0x61",
- "EventName": "BUS_ACCESS_ST",
- "BriefDescription": "Bus access - Write"
- },
- {,
+ {
"EventCode": "0xC0",
"EventName": "EXT_MEM_REQ",
"BriefDescription": "External memory request"
},
- {,
+ {
"EventCode": "0xC1",
"EventName": "EXT_MEM_REQ_NC",
"BriefDescription": "Non-cacheable external memory request"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
index 73a2240..6cc6cbd 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
@@ -1,32 +1,28 @@
[
- {,
- "EventCode": "0x86",
- "EventName": "EXC_IRQ",
- "BriefDescription": "Exception taken, IRQ"
+ {
+ "ArchStdEvent": "EXC_IRQ",
},
- {,
- "EventCode": "0x87",
- "EventName": "EXC_FIQ",
- "BriefDescription": "Exception taken, FIQ"
+ {
+ "ArchStdEvent": "EXC_FIQ",
},
- {,
- "EventCode": "0xC6",
- "EventName": "PRE_DECODE_ERR",
- "BriefDescription": "Pre-decode error"
+ {
+ "EventCode": "0xC6",
+ "EventName": "PRE_DECODE_ERR",
+ "BriefDescription": "Pre-decode error"
},
- {,
- "EventCode": "0xD0",
- "EventName": "L1I_CACHE_ERR",
- "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
+ {
+ "EventCode": "0xD0",
+ "EventName": "L1I_CACHE_ERR",
+ "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
},
- {,
- "EventCode": "0xD1",
- "EventName": "L1D_CACHE_ERR",
- "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
+ {
+ "EventCode": "0xD1",
+ "EventName": "L1D_CACHE_ERR",
+ "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
},
- {,
- "EventCode": "0xD2",
- "EventName": "TLB_ERR",
- "BriefDescription": "TLB memory error"
+ {
+ "EventCode": "0xD2",
+ "EventName": "TLB_ERR",
+ "BriefDescription": "TLB memory error"
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
index 3149fb9..f45a6b5 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
@@ -1,50 +1,50 @@
[
- {,
+ {
"EventCode": "0xC7",
"EventName": "STALL_SB_FULL",
"BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
},
- {,
+ {
"EventCode": "0xE0",
"EventName": "OTHER_IQ_DEP_STALL",
"BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
},
- {,
+ {
"EventCode": "0xE1",
"EventName": "IC_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
},
- {,
+ {
"EventCode": "0xE2",
"EventName": "IUTLB_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
},
- {,
+ {
"EventCode": "0xE3",
"EventName": "DECODE_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
},
- {,
+ {
"EventCode": "0xE4",
"EventName": "OTHER_INTERLOCK_STALL",
"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction"
},
- {,
+ {
"EventCode": "0xE5",
"EventName": "AGU_DEP_STALL",
"BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
},
- {,
+ {
"EventCode": "0xE6",
"EventName": "SIMD_DEP_STALL",
"BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
},
- {,
+ {
"EventCode": "0xE7",
"EventName": "LD_DEP_STALL",
"BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
},
- {,
+ {
"EventCode": "0xE8",
"EventName": "ST_DEP_STALL",
"BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v3 10/11] perf vendor events arm64: fixup A53 to use recommended events
@ 2018-03-08 10:58 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: linux-arm-kernel
This patch fixes the ARM Cortex-A53 json to use event definition
from the ARMv8 recommended events.
In addition to this change, other changes were made:
- remove stray ','
- remove mirrored events in memory.json and bus.json
- fixed indentation to be consistent with other ARM
JSONs
Cc: William Cohen <wcohen@redhat.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
.../arch/arm64/arm/cortex-a53/branch.json | 14 +++----
.../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 22 ++---------
.../arch/arm64/arm/cortex-a53/cache.json | 40 ++++++++++----------
.../arch/arm64/arm/cortex-a53/memory.json | 14 +------
.../arch/arm64/arm/cortex-a53/other.json | 44 ++++++++++------------
.../arch/arm64/arm/cortex-a53/pipeline.json | 20 +++++-----
6 files changed, 62 insertions(+), 92 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
index 3b62087..0b0e6b2 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
@@ -1,25 +1,23 @@
[
- {,
- "EventCode": "0x7A",
- "EventName": "BR_INDIRECT_SPEC",
- "BriefDescription": "Branch speculatively executed - Indirect branch"
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC",
},
- {,
+ {
"EventCode": "0xC9",
"EventName": "BR_COND",
"BriefDescription": "Conditional branch executed"
},
- {,
+ {
"EventCode": "0xCA",
"EventName": "BR_INDIRECT_MISPRED",
"BriefDescription": "Indirect branch mispredicted"
},
- {,
+ {
"EventCode": "0xCB",
"EventName": "BR_INDIRECT_MISPRED_ADDR",
"BriefDescription": "Indirect branch mispredicted because of address miscompare"
},
- {,
+ {
"EventCode": "0xCC",
"EventName": "BR_COND_MISPRED",
"BriefDescription": "Conditional branch mispredicted"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
index 480d9f7..ce33b25 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
@@ -1,22 +1,8 @@
[
- {,
- "EventCode": "0x60",
- "EventName": "BUS_ACCESS_LD",
- "BriefDescription": "Bus access - Read"
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD",
},
- {,
- "EventCode": "0x61",
- "EventName": "BUS_ACCESS_ST",
- "BriefDescription": "Bus access - Write"
- },
- {,
- "EventCode": "0xC0",
- "EventName": "EXT_MEM_REQ",
- "BriefDescription": "External memory request"
- },
- {,
- "EventCode": "0xC1",
- "EventName": "EXT_MEM_REQ_NC",
- "BriefDescription": "Non-cacheable external memory request"
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR",
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
index 11baad6..5dfbec4 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
@@ -1,27 +1,27 @@
[
- {,
- "EventCode": "0xC2",
- "EventName": "PREFETCH_LINEFILL",
- "BriefDescription": "Linefill because of prefetch"
+ {
+ "EventCode": "0xC2",
+ "EventName": "PREFETCH_LINEFILL",
+ "BriefDescription": "Linefill because of prefetch"
},
- {,
- "EventCode": "0xC3",
- "EventName": "PREFETCH_LINEFILL_DROP",
- "BriefDescription": "Instruction Cache Throttle occurred"
+ {
+ "EventCode": "0xC3",
+ "EventName": "PREFETCH_LINEFILL_DROP",
+ "BriefDescription": "Instruction Cache Throttle occurred"
},
- {,
- "EventCode": "0xC4",
- "EventName": "READ_ALLOC_ENTER",
- "BriefDescription": "Entering read allocate mode"
+ {
+ "EventCode": "0xC4",
+ "EventName": "READ_ALLOC_ENTER",
+ "BriefDescription": "Entering read allocate mode"
},
- {,
- "EventCode": "0xC5",
- "EventName": "READ_ALLOC",
- "BriefDescription": "Read allocate mode"
+ {
+ "EventCode": "0xC5",
+ "EventName": "READ_ALLOC",
+ "BriefDescription": "Read allocate mode"
},
- {,
- "EventCode": "0xC8",
- "EventName": "EXT_SNOOP",
- "BriefDescription": "SCU Snooped data from another CPU for this CPU"
+ {
+ "EventCode": "0xC8",
+ "EventName": "EXT_SNOOP",
+ "BriefDescription": "SCU Snooped data from another CPU for this CPU"
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
index 480d9f7..25ae642 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
@@ -1,20 +1,10 @@
[
- {,
- "EventCode": "0x60",
- "EventName": "BUS_ACCESS_LD",
- "BriefDescription": "Bus access - Read"
- },
- {,
- "EventCode": "0x61",
- "EventName": "BUS_ACCESS_ST",
- "BriefDescription": "Bus access - Write"
- },
- {,
+ {
"EventCode": "0xC0",
"EventName": "EXT_MEM_REQ",
"BriefDescription": "External memory request"
},
- {,
+ {
"EventCode": "0xC1",
"EventName": "EXT_MEM_REQ_NC",
"BriefDescription": "Non-cacheable external memory request"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
index 73a2240..6cc6cbd 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
@@ -1,32 +1,28 @@
[
- {,
- "EventCode": "0x86",
- "EventName": "EXC_IRQ",
- "BriefDescription": "Exception taken, IRQ"
+ {
+ "ArchStdEvent": "EXC_IRQ",
},
- {,
- "EventCode": "0x87",
- "EventName": "EXC_FIQ",
- "BriefDescription": "Exception taken, FIQ"
+ {
+ "ArchStdEvent": "EXC_FIQ",
},
- {,
- "EventCode": "0xC6",
- "EventName": "PRE_DECODE_ERR",
- "BriefDescription": "Pre-decode error"
+ {
+ "EventCode": "0xC6",
+ "EventName": "PRE_DECODE_ERR",
+ "BriefDescription": "Pre-decode error"
},
- {,
- "EventCode": "0xD0",
- "EventName": "L1I_CACHE_ERR",
- "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
+ {
+ "EventCode": "0xD0",
+ "EventName": "L1I_CACHE_ERR",
+ "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
},
- {,
- "EventCode": "0xD1",
- "EventName": "L1D_CACHE_ERR",
- "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
+ {
+ "EventCode": "0xD1",
+ "EventName": "L1D_CACHE_ERR",
+ "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
},
- {,
- "EventCode": "0xD2",
- "EventName": "TLB_ERR",
- "BriefDescription": "TLB memory error"
+ {
+ "EventCode": "0xD2",
+ "EventName": "TLB_ERR",
+ "BriefDescription": "TLB memory error"
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
index 3149fb9..f45a6b5 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
@@ -1,50 +1,50 @@
[
- {,
+ {
"EventCode": "0xC7",
"EventName": "STALL_SB_FULL",
"BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
},
- {,
+ {
"EventCode": "0xE0",
"EventName": "OTHER_IQ_DEP_STALL",
"BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
},
- {,
+ {
"EventCode": "0xE1",
"EventName": "IC_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
},
- {,
+ {
"EventCode": "0xE2",
"EventName": "IUTLB_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
},
- {,
+ {
"EventCode": "0xE3",
"EventName": "DECODE_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
},
- {,
+ {
"EventCode": "0xE4",
"EventName": "OTHER_INTERLOCK_STALL",
"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction"
},
- {,
+ {
"EventCode": "0xE5",
"EventName": "AGU_DEP_STALL",
"BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
},
- {,
+ {
"EventCode": "0xE6",
"EventName": "SIMD_DEP_STALL",
"BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
},
- {,
+ {
"EventCode": "0xE7",
"EventName": "LD_DEP_STALL",
"BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
},
- {,
+ {
"EventCode": "0xE8",
"EventName": "ST_DEP_STALL",
"BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [tip:perf/core] perf vendor events arm64: fixup A53 to use recommended events
2018-03-08 10:58 ` John Garry
(?)
@ 2018-03-20 6:25 ` tip-bot for John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: tip-bot for John Garry @ 2018-03-20 6:25 UTC (permalink / raw)
To: linux-tip-commits
Cc: wcohen, hpa, zhangshaokun, will.deacon, linux-kernel, jolsa,
tglx, ganapatrao.kulkarni, peterz, namhyung, ak, acme, mingo,
alexander.shishkin, john.garry
Commit-ID: afe4d089621d4d90ac0e089b83752ea4515325ac
Gitweb: https://git.kernel.org/tip/afe4d089621d4d90ac0e089b83752ea4515325ac
Author: John Garry <john.garry@huawei.com>
AuthorDate: Thu, 8 Mar 2018 18:58:35 +0800
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Fri, 16 Mar 2018 13:54:53 -0300
perf vendor events arm64: fixup A53 to use recommended events
This patch fixes the ARM Cortex-A53 json to use event definition from
the ARMv8 recommended events.
In addition to this change, other changes were made:
- remove stray ','
- remove mirrored events in memory.json and bus.json
- fixed indentation to be consistent with other ARM
JSONs
Signed-off-by: John Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-11-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../arch/arm64/arm/cortex-a53/branch.json | 14 +++----
.../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 22 ++---------
.../arch/arm64/arm/cortex-a53/cache.json | 40 ++++++++++----------
.../arch/arm64/arm/cortex-a53/memory.json | 14 +------
.../arch/arm64/arm/cortex-a53/other.json | 44 ++++++++++------------
.../arch/arm64/arm/cortex-a53/pipeline.json | 20 +++++-----
6 files changed, 62 insertions(+), 92 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
index 3b6208763e50..0b0e6b26605b 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
@@ -1,25 +1,23 @@
[
- {,
- "EventCode": "0x7A",
- "EventName": "BR_INDIRECT_SPEC",
- "BriefDescription": "Branch speculatively executed - Indirect branch"
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC",
},
- {,
+ {
"EventCode": "0xC9",
"EventName": "BR_COND",
"BriefDescription": "Conditional branch executed"
},
- {,
+ {
"EventCode": "0xCA",
"EventName": "BR_INDIRECT_MISPRED",
"BriefDescription": "Indirect branch mispredicted"
},
- {,
+ {
"EventCode": "0xCB",
"EventName": "BR_INDIRECT_MISPRED_ADDR",
"BriefDescription": "Indirect branch mispredicted because of address miscompare"
},
- {,
+ {
"EventCode": "0xCC",
"EventName": "BR_COND_MISPRED",
"BriefDescription": "Conditional branch mispredicted"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
index 480d9f7460ab..ce33b2553277 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
@@ -1,22 +1,8 @@
[
- {,
- "EventCode": "0x60",
- "EventName": "BUS_ACCESS_LD",
- "BriefDescription": "Bus access - Read"
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD",
},
- {,
- "EventCode": "0x61",
- "EventName": "BUS_ACCESS_ST",
- "BriefDescription": "Bus access - Write"
- },
- {,
- "EventCode": "0xC0",
- "EventName": "EXT_MEM_REQ",
- "BriefDescription": "External memory request"
- },
- {,
- "EventCode": "0xC1",
- "EventName": "EXT_MEM_REQ_NC",
- "BriefDescription": "Non-cacheable external memory request"
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR",
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
index 11baad6344b9..5dfbec43c9f9 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
@@ -1,27 +1,27 @@
[
- {,
- "EventCode": "0xC2",
- "EventName": "PREFETCH_LINEFILL",
- "BriefDescription": "Linefill because of prefetch"
+ {
+ "EventCode": "0xC2",
+ "EventName": "PREFETCH_LINEFILL",
+ "BriefDescription": "Linefill because of prefetch"
},
- {,
- "EventCode": "0xC3",
- "EventName": "PREFETCH_LINEFILL_DROP",
- "BriefDescription": "Instruction Cache Throttle occurred"
+ {
+ "EventCode": "0xC3",
+ "EventName": "PREFETCH_LINEFILL_DROP",
+ "BriefDescription": "Instruction Cache Throttle occurred"
},
- {,
- "EventCode": "0xC4",
- "EventName": "READ_ALLOC_ENTER",
- "BriefDescription": "Entering read allocate mode"
+ {
+ "EventCode": "0xC4",
+ "EventName": "READ_ALLOC_ENTER",
+ "BriefDescription": "Entering read allocate mode"
},
- {,
- "EventCode": "0xC5",
- "EventName": "READ_ALLOC",
- "BriefDescription": "Read allocate mode"
+ {
+ "EventCode": "0xC5",
+ "EventName": "READ_ALLOC",
+ "BriefDescription": "Read allocate mode"
},
- {,
- "EventCode": "0xC8",
- "EventName": "EXT_SNOOP",
- "BriefDescription": "SCU Snooped data from another CPU for this CPU"
+ {
+ "EventCode": "0xC8",
+ "EventName": "EXT_SNOOP",
+ "BriefDescription": "SCU Snooped data from another CPU for this CPU"
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
index 480d9f7460ab..25ae642ba381 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json
@@ -1,20 +1,10 @@
[
- {,
- "EventCode": "0x60",
- "EventName": "BUS_ACCESS_LD",
- "BriefDescription": "Bus access - Read"
- },
- {,
- "EventCode": "0x61",
- "EventName": "BUS_ACCESS_ST",
- "BriefDescription": "Bus access - Write"
- },
- {,
+ {
"EventCode": "0xC0",
"EventName": "EXT_MEM_REQ",
"BriefDescription": "External memory request"
},
- {,
+ {
"EventCode": "0xC1",
"EventName": "EXT_MEM_REQ_NC",
"BriefDescription": "Non-cacheable external memory request"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
index 73a22402d003..6cc6cbd7bf0b 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
@@ -1,32 +1,28 @@
[
- {,
- "EventCode": "0x86",
- "EventName": "EXC_IRQ",
- "BriefDescription": "Exception taken, IRQ"
+ {
+ "ArchStdEvent": "EXC_IRQ",
},
- {,
- "EventCode": "0x87",
- "EventName": "EXC_FIQ",
- "BriefDescription": "Exception taken, FIQ"
+ {
+ "ArchStdEvent": "EXC_FIQ",
},
- {,
- "EventCode": "0xC6",
- "EventName": "PRE_DECODE_ERR",
- "BriefDescription": "Pre-decode error"
+ {
+ "EventCode": "0xC6",
+ "EventName": "PRE_DECODE_ERR",
+ "BriefDescription": "Pre-decode error"
},
- {,
- "EventCode": "0xD0",
- "EventName": "L1I_CACHE_ERR",
- "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
+ {
+ "EventCode": "0xD0",
+ "EventName": "L1I_CACHE_ERR",
+ "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
},
- {,
- "EventCode": "0xD1",
- "EventName": "L1D_CACHE_ERR",
- "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
+ {
+ "EventCode": "0xD1",
+ "EventName": "L1D_CACHE_ERR",
+ "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
},
- {,
- "EventCode": "0xD2",
- "EventName": "TLB_ERR",
- "BriefDescription": "TLB memory error"
+ {
+ "EventCode": "0xD2",
+ "EventName": "TLB_ERR",
+ "BriefDescription": "TLB memory error"
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
index 3149fb90555a..f45a6b5d0025 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json
@@ -1,50 +1,50 @@
[
- {,
+ {
"EventCode": "0xC7",
"EventName": "STALL_SB_FULL",
"BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
},
- {,
+ {
"EventCode": "0xE0",
"EventName": "OTHER_IQ_DEP_STALL",
"BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
},
- {,
+ {
"EventCode": "0xE1",
"EventName": "IC_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
},
- {,
+ {
"EventCode": "0xE2",
"EventName": "IUTLB_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
},
- {,
+ {
"EventCode": "0xE3",
"EventName": "DECODE_DEP_STALL",
"BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
},
- {,
+ {
"EventCode": "0xE4",
"EventName": "OTHER_INTERLOCK_STALL",
"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction"
},
- {,
+ {
"EventCode": "0xE5",
"EventName": "AGU_DEP_STALL",
"BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
},
- {,
+ {
"EventCode": "0xE6",
"EventName": "SIMD_DEP_STALL",
"BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
},
- {,
+ {
"EventCode": "0xE7",
"EventName": "LD_DEP_STALL",
"BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
},
- {,
+ {
"EventCode": "0xE8",
"EventName": "ST_DEP_STALL",
"BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v3 11/11] perf vendor events arm64: add HiSilicon hip08 JSON file
2018-03-08 10:58 ` John Garry
@ 2018-03-08 10:58 ` John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: jolsa, ak, peterz, mingo, acme, alexander.shishkin, namhyung,
wcohen, will.deacon, ganapatrao.kulkarni
Cc: linuxarm, linux-kernel, linux-arm-kernel, zhangshaokun, John Garry
This patch adds the HiSilicon hip08 JSON file. This platform
follows the ARMv8 recommended IMPLEMENTATION DEFINED events, where
applicable.
Signed-off-by: John Garry <john.garry@huawei.com>
---
.../arch/arm64/hisilicon/hip08/core-imp-def.json | 122 +++++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
2 files changed, 123 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
new file mode 100644
index 0000000..9f0f15d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
@@ -0,0 +1,122 @@
+[
+ {
+ "ArchStdEvent": "L1D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_INVAL",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL",
+ },
+ {
+ "PublicDescription": "Level 1 instruction cache prefetch access count",
+ "EventCode": "0x102e",
+ "EventName": "L1I_CACHE_PRF",
+ "BriefDescription": "L1I cache prefetch access count",
+ },
+ {
+ "PublicDescription": "Level 1 instruction cache miss due to prefetch access count",
+ "EventCode": "0x102f",
+ "EventName": "L1I_CACHE_PRF_REFILL",
+ "BriefDescription": "L1I cache miss due to prefetch access count",
+ },
+ {
+ "PublicDescription": "Instruction queue is empty",
+ "EventCode": "0x1043",
+ "EventName": "IQ_IS_EMPTY",
+ "BriefDescription": "Instruction queue is empty",
+ },
+ {
+ "PublicDescription": "Instruction fetch stall cycles",
+ "EventCode": "0x1044",
+ "EventName": "IF_IS_STALL",
+ "BriefDescription": "Instruction fetch stall cycles",
+ },
+ {
+ "PublicDescription": "Instructions can receive, but not send",
+ "EventCode": "0x2014",
+ "EventName": "FETCH_BUBBLE",
+ "BriefDescription": "Instructions can receive, but not send",
+ },
+ {
+ "PublicDescription": "Prefetch request from LSU",
+ "EventCode": "0x6013",
+ "EventName": "PRF_REQ",
+ "BriefDescription": "Prefetch request from LSU",
+ },
+ {
+ "PublicDescription": "Hit on prefetched data",
+ "EventCode": "0x6014",
+ "EventName": "HIT_ON_PRF",
+ "BriefDescription": "Hit on prefetched data",
+ },
+ {
+ "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
+ "EventCode": "0x7001",
+ "EventName": "EXE_STALL_CYCLE",
+ "BriefDescription": "Cycles of that the number of issue ups are less than 4",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
+ "EventCode": "0x7004",
+ "EventName": "MEM_STALL_ANYLOAD",
+ "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
+ "EventCode": "0x7006",
+ "EventName": "MEM_STALL_L1MISS",
+ "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
+ "EventCode": "0x7007",
+ "EventName": "MEM_STALL_L2MISS",
+ "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
+ },
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index cf14e23..8f11aeb 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -14,3 +14,4 @@
#Family-model,Version,Filename,EventType
0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
+0x00000000480fd010,v1,hisilicon/hip08,core
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v3 11/11] perf vendor events arm64: add HiSilicon hip08 JSON file
@ 2018-03-08 10:58 ` John Garry
0 siblings, 0 replies; 47+ messages in thread
From: John Garry @ 2018-03-08 10:58 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the HiSilicon hip08 JSON file. This platform
follows the ARMv8 recommended IMPLEMENTATION DEFINED events, where
applicable.
Signed-off-by: John Garry <john.garry@huawei.com>
---
.../arch/arm64/hisilicon/hip08/core-imp-def.json | 122 +++++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
2 files changed, 123 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
new file mode 100644
index 0000000..9f0f15d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
@@ -0,0 +1,122 @@
+[
+ {
+ "ArchStdEvent": "L1D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_INVAL",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL",
+ },
+ {
+ "PublicDescription": "Level 1 instruction cache prefetch access count",
+ "EventCode": "0x102e",
+ "EventName": "L1I_CACHE_PRF",
+ "BriefDescription": "L1I cache prefetch access count",
+ },
+ {
+ "PublicDescription": "Level 1 instruction cache miss due to prefetch access count",
+ "EventCode": "0x102f",
+ "EventName": "L1I_CACHE_PRF_REFILL",
+ "BriefDescription": "L1I cache miss due to prefetch access count",
+ },
+ {
+ "PublicDescription": "Instruction queue is empty",
+ "EventCode": "0x1043",
+ "EventName": "IQ_IS_EMPTY",
+ "BriefDescription": "Instruction queue is empty",
+ },
+ {
+ "PublicDescription": "Instruction fetch stall cycles",
+ "EventCode": "0x1044",
+ "EventName": "IF_IS_STALL",
+ "BriefDescription": "Instruction fetch stall cycles",
+ },
+ {
+ "PublicDescription": "Instructions can receive, but not send",
+ "EventCode": "0x2014",
+ "EventName": "FETCH_BUBBLE",
+ "BriefDescription": "Instructions can receive, but not send",
+ },
+ {
+ "PublicDescription": "Prefetch request from LSU",
+ "EventCode": "0x6013",
+ "EventName": "PRF_REQ",
+ "BriefDescription": "Prefetch request from LSU",
+ },
+ {
+ "PublicDescription": "Hit on prefetched data",
+ "EventCode": "0x6014",
+ "EventName": "HIT_ON_PRF",
+ "BriefDescription": "Hit on prefetched data",
+ },
+ {
+ "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
+ "EventCode": "0x7001",
+ "EventName": "EXE_STALL_CYCLE",
+ "BriefDescription": "Cycles of that the number of issue ups are less than 4",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
+ "EventCode": "0x7004",
+ "EventName": "MEM_STALL_ANYLOAD",
+ "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
+ "EventCode": "0x7006",
+ "EventName": "MEM_STALL_L1MISS",
+ "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
+ "EventCode": "0x7007",
+ "EventName": "MEM_STALL_L2MISS",
+ "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
+ },
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index cf14e23..8f11aeb 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -14,3 +14,4 @@
#Family-model,Version,Filename,EventType
0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
+0x00000000480fd010,v1,hisilicon/hip08,core
--
1.9.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [tip:perf/core] perf vendor events arm64: add HiSilicon hip08 JSON file
2018-03-08 10:58 ` John Garry
(?)
@ 2018-03-20 6:26 ` tip-bot for John Garry
-1 siblings, 0 replies; 47+ messages in thread
From: tip-bot for John Garry @ 2018-03-20 6:26 UTC (permalink / raw)
To: linux-tip-commits
Cc: alexander.shishkin, hpa, namhyung, john.garry, will.deacon, tglx,
peterz, linux-kernel, ak, mingo, jolsa, ganapatrao.kulkarni,
wcohen, acme, zhangshaokun
Commit-ID: 3d4caec1600e0bf34600a7b700599a20df03629e
Gitweb: https://git.kernel.org/tip/3d4caec1600e0bf34600a7b700599a20df03629e
Author: John Garry <john.garry@huawei.com>
AuthorDate: Thu, 8 Mar 2018 18:58:36 +0800
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Fri, 16 Mar 2018 13:54:59 -0300
perf vendor events arm64: add HiSilicon hip08 JSON file
This patch adds the HiSilicon hip08 JSON file. This platform follows the
ARMv8 recommended IMPLEMENTATION DEFINED events, where applicable.
Signed-off-by: John Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-12-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../arch/arm64/hisilicon/hip08/core-imp-def.json | 122 +++++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
2 files changed, 123 insertions(+)
diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
new file mode 100644
index 000000000000..9f0f15d15f75
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
@@ -0,0 +1,122 @@
+[
+ {
+ "ArchStdEvent": "L1D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_INVAL",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL",
+ },
+ {
+ "PublicDescription": "Level 1 instruction cache prefetch access count",
+ "EventCode": "0x102e",
+ "EventName": "L1I_CACHE_PRF",
+ "BriefDescription": "L1I cache prefetch access count",
+ },
+ {
+ "PublicDescription": "Level 1 instruction cache miss due to prefetch access count",
+ "EventCode": "0x102f",
+ "EventName": "L1I_CACHE_PRF_REFILL",
+ "BriefDescription": "L1I cache miss due to prefetch access count",
+ },
+ {
+ "PublicDescription": "Instruction queue is empty",
+ "EventCode": "0x1043",
+ "EventName": "IQ_IS_EMPTY",
+ "BriefDescription": "Instruction queue is empty",
+ },
+ {
+ "PublicDescription": "Instruction fetch stall cycles",
+ "EventCode": "0x1044",
+ "EventName": "IF_IS_STALL",
+ "BriefDescription": "Instruction fetch stall cycles",
+ },
+ {
+ "PublicDescription": "Instructions can receive, but not send",
+ "EventCode": "0x2014",
+ "EventName": "FETCH_BUBBLE",
+ "BriefDescription": "Instructions can receive, but not send",
+ },
+ {
+ "PublicDescription": "Prefetch request from LSU",
+ "EventCode": "0x6013",
+ "EventName": "PRF_REQ",
+ "BriefDescription": "Prefetch request from LSU",
+ },
+ {
+ "PublicDescription": "Hit on prefetched data",
+ "EventCode": "0x6014",
+ "EventName": "HIT_ON_PRF",
+ "BriefDescription": "Hit on prefetched data",
+ },
+ {
+ "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
+ "EventCode": "0x7001",
+ "EventName": "EXE_STALL_CYCLE",
+ "BriefDescription": "Cycles of that the number of issue ups are less than 4",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
+ "EventCode": "0x7004",
+ "EventName": "MEM_STALL_ANYLOAD",
+ "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
+ "EventCode": "0x7006",
+ "EventName": "MEM_STALL_L1MISS",
+ "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
+ "EventCode": "0x7007",
+ "EventName": "MEM_STALL_L2MISS",
+ "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
+ },
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index cf14e23b6404..8f11aeb003a9 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -14,3 +14,4 @@
#Family-model,Version,Filename,EventType
0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
+0x00000000480fd010,v1,hisilicon/hip08,core
^ permalink raw reply related [flat|nested] 47+ messages in thread