Re: [PATCH 19/19] PCI: Set bridge map_irq and swizzle_irq to default functions

From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Rob Herring" <robh@kernel.org>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Jonathan Hunter" <jonathanh@nvidia.com>,
	"Thierry Reding" <thierry.reding@gmail.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Tiezhu Yang" <yangtiezhu@loongson.cn>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Huacai Chen" <chenhuacai@kernel.org>,
	"Ray Jui" <rjui@broadcom.com>,
	"Scott Branden" <sbranden@broadcom.com>,
	bcm-kernel-feedback-list@broadcom.com,
	linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH 19/19] PCI: Set bridge map_irq and swizzle_irq to default functions
Date: Sat, 29 Jan 2022 22:34:03 +0000 (GMT)	[thread overview]
Message-ID: <alpine.DEB.2.21.2201220459090.58572@angie.orcam.me.uk> (raw)
In-Reply-To: <20220111214608.GA169999@bhelgaas>

On Tue, 11 Jan 2022, Bjorn Helgaas wrote:

> This patch removed all the ->swizzle_irq users in drivers/pci/, which
> is great -- IIUC swizzling is specified by the PCI-to-PCI Bridge Spec,
> r1.2, sec 9.1, and should not be device-specific.  I assume the few
> remaining arch/ users (arm and alpha) are either bugs or workarounds
> for broken devices.

 I skimmed over the Alpha stuff and it seems to mostly care about setting 
the slot value returned differently and defers to `pci_common_swizzle' for 
actual pin determination.  This could be moderately easy to sort out.

 One exception is `takara_swizzle' which looks incomplete to me; as this 
is a PICMG device[1] someone would have to fill in the missing details as 
AFAICT the PICMG connector is supposed to provide all the INT# A-D lines 
and then routing is done on the backplane using binding defined by PICMG.

 According to DEC documentation there's an alternative interrupt routing 
mode available too, using a external interrupt controller FPGA placed on 
the backplane[2], where no swizzling is done and instead each of the four 
INT# lines across all the PCI slots, up to 16, provided by a backplane is 
individually routed to 64 inputs of the interrupt controller.

 There is a paper by DEC available online[3] that could help filling in 
the missing details for either mode, especially someone who has access to 
such a system and could verify it in reality.

References:

[1] "DIGITAL 21164 PICMG SBC, User Information for the EBM21 and EBM23",
    V1.0, Digital Equipment Corporation, June 1997, Part Number: 
    EK-A0937-UG. A01

[2] "DIGITAL Modular Computing Components, OEM Information for DMCC 
    Backplanes", Version 4.1, Compaq Computer Corporation, January 1999, 
    Order Number: EK-A0929-TM. C01

[3] Ross L. Armstrong, "PCI Interrupt Controller for Industry Standard 
    PCI-ISA Bus Architecture using PCI-to-PCI Bridge Technology", Digital 
    Equipment Corporation (Scotland) Ltd., 1996

 FWIW,

  Maciej