Re: [PATCH v3 2/2] ASoC: Intel: Add period size constraint on strago board

From: Takashi Iwai <tiwai@suse.de>
To: "Lu, Brent" <brent.lu@intel.com>
Cc: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>,
	"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
	Kai Vehmanen <kai.vehmanen@linux.intel.com>,
	Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"yuhsuan@google.com" <yuhsuan@google.com>,
	Takashi Iwai <tiwai@suse.com>,
	Jie Yang <yang.jie@linux.intel.com>,
	"Rojewski, Cezary" <cezary.rojewski@intel.com>,
	Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>,
	Liam Girdwood <liam.r.girdwood@linux.intel.com>,
	Sam McNally <sammc@chromium.org>, Mark Brown <broonie@kernel.org>,
	Ranjani Sridharan <ranjani.sridharan@linux.intel.com>,
	Daniel Stuart <daniel.stuart14@gmail.com>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Yu-Hsuan Hsu <yuhsuan@chromium.org>,
	Damian van Soelen <dj.vsoelen@gmail.com>
Subject: Re: [PATCH v3 2/2] ASoC: Intel: Add period size constraint on strago board
Date: Mon, 03 Aug 2020 18:56:33 +0200	[thread overview]
Message-ID: <s5hpn873by6.wl-tiwai@suse.de> (raw)
In-Reply-To: <DM6PR11MB3642D9BE1E5DAAB8B78B84B0974D0@DM6PR11MB3642.namprd11.prod.outlook.com>

On Mon, 03 Aug 2020 18:45:29 +0200,
Lu, Brent wrote:
> 
> > > Hi Takashi,
> > >
> > > I've double checked with google. It's a must for Chromebooks due to
> > > low latency use case.
> > 
> > I wonder if there's a misunderstanding here?
> > 
> > I believe Takashi's question was "is this a must to ONLY accept 240 samples
> > for the period size", there was no pushback on the value itself.
> > Are those boards broken with e.g. 960 samples?
> 
> I've added google people to discuss directly.
> 
> Hi Yuhsuan,
> Would you explain why CRAS needs to use such short period size? Thanks.

For avoid further misunderstanding: it's fine that CRAS *uses* such a
short period.  It's often required for achieving a short latency.

However, the question is whether the driver can set *only* this value
for making it working.  IOW, if we don't have this constraint, what
actually happens?  If the driver gives the period size alignment,
wouldn't CRAS choose 240?

Takashi