* [PATCH 01/24] drm/amd/display: use correct vpg instance for 128b/132b encoding
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 02/24] drm/amd/display: [FW Promotion] Release 0.0.85 Anson Jacob
` (23 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Wenjing Liu,
Michael Strauss
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
128b/132b uses the vpg instance assigned to hpo dp stream encoder.
The current vpg used is assigned to dio stream encoder.
This is incorrect and cause display black screen because the
actual vpg is powered off.
Reviewed-by: Michael Strauss <michael.strauss@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 2bd38d19a447..cab7993b4cc5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3608,6 +3608,9 @@ void core_link_enable_stream(
#if defined(CONFIG_DRM_AMD_DC_DCN)
enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
+
+ if (is_dp_128b_132b_signal(pipe_ctx))
+ vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
#endif
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
@@ -3853,6 +3856,9 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
struct dc_link *link = stream->sink->link;
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
+
+ if (is_dp_128b_132b_signal(pipe_ctx))
+ vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
#endif
if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 02/24] drm/amd/display: [FW Promotion] Release 0.0.85
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
2021-09-24 19:09 ` [PATCH 01/24] drm/amd/display: use correct vpg instance for 128b/132b encoding Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 03/24] drm/amd/display: Don't enable AFMT for DP audio stream Anson Jacob
` (22 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 359f091e37f1..03110f59b50d 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x607c9623
+#define DMUB_FW_VERSION_GIT_HASH 0xeb0940cc
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 84
+#define DMUB_FW_VERSION_REVISION 85
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 03/24] drm/amd/display: Don't enable AFMT for DP audio stream
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
2021-09-24 19:09 ` [PATCH 01/24] drm/amd/display: use correct vpg instance for 128b/132b encoding Anson Jacob
2021-09-24 19:09 ` [PATCH 02/24] drm/amd/display: [FW Promotion] Release 0.0.85 Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 04/24] drm/amd/display: add vsync notify to dmub for abm pause Anson Jacob
` (21 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu,
Michael Strauss, Wenjing Liu
From: Michael Strauss <michael.strauss@amd.com>
[WHY]
AFMT is unused for DP audio, so powering it on for DP is unnecessary.
[HOW]
APG block should be powered down instead, however HW defaults to shutdown
state when not enabled so no further work is required.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 5 -----
.../gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c | 2 --
2 files changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index a97bdaa54f73..687c3c6881a9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -1402,11 +1402,6 @@ static void enc1_se_disable_dp_audio(
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
uint32_t value = 0;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
- if (enc->afmt && enc->afmt->funcs->afmt_powerdown)
- enc->afmt->funcs->afmt_powerdown(enc->afmt);
-#endif
-
/* Disable Audio packets */
REG_UPDATE_5(DP_SEC_CNTL,
DP_SEC_ASP_ENABLE, 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
index 3ea6dacec80c..ebd9c35c914f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
@@ -710,8 +710,6 @@ static void enc3_se_setup_dp_audio(
static void enc3_se_dp_audio_enable(
struct stream_encoder *enc)
{
- if (enc->afmt->funcs->afmt_poweron)
- enc->afmt->funcs->afmt_poweron(enc->afmt);
enc1_se_enable_audio_clock(enc, true);
enc3_se_setup_dp_audio(enc);
enc1_se_enable_dp_audio(enc);
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 04/24] drm/amd/display: add vsync notify to dmub for abm pause
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (2 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 03/24] drm/amd/display: Don't enable AFMT for DP audio stream Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 05/24] drm/amd/display: Add debug support to override the Minimum DRAM Clock Anson Jacob
` (20 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Eric Yang,
Nicholas Kazlauskas
From: Eric Yang <Eric.Yang2@amd.com>
[Why]
To prevent unnecessary wake up of DMCUB when ABM is enabled without PSR
enabled, driver will notify DMCUB to stop ABM's vertical interrupts
if vsync is disabled and steady state is reached.
[How]
Send inbox message to notify ABM pause based on vsync on/off
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 54 +++++++++++++++++++
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 21 ++++++++
drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 1 +
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 54 +++++++++++++++++++
5 files changed, 132 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 331a7517176b..644005846433 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3536,3 +3536,57 @@ void dc_disable_accelerated_mode(struct dc *dc)
{
bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);
}
+
+
+/**
+ *****************************************************************************
+ * dc_notify_vsync_int_state() - notifies vsync enable/disable state
+ * @dc: dc structure
+ * @stream: stream where vsync int state changed
+ * @enable: whether vsync is enabled or disabled
+ *
+ * Called when vsync is enabled/disabled
+ * Will notify DMUB to start/stop ABM interrupts after steady state is reached
+ *
+ *****************************************************************************
+ */
+void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable)
+{
+ int i;
+ int edp_num;
+ struct pipe_ctx *pipe = NULL;
+ struct dc_link *link = stream->sink->link;
+ struct dc_link *edp_links[MAX_NUM_EDP];
+
+
+ if (link->psr_settings.psr_feature_enabled)
+ return;
+
+ /*find primary pipe associated with stream*/
+ for (i = 0; i < MAX_PIPES; i++) {
+ pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+
+ if (pipe->stream == stream && pipe->stream_res.tg)
+ break;
+ }
+
+ if (i == MAX_PIPES) {
+ ASSERT(0);
+ return;
+ }
+
+ get_edp_links(dc, edp_links, &edp_num);
+
+ /* Determine panel inst */
+ for (i = 0; i < edp_num; i++) {
+ if (edp_links[i] == link)
+ break;
+ }
+
+ if (i == edp_num) {
+ return;
+ }
+
+ if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause)
+ pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e5dcbee6e672..b194a2727bd8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1313,6 +1313,8 @@ void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
enum dc_irq_source dc_get_hpd_irq_source_at_index(
struct dc *dc, uint32_t link_index);
+void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
+
/*******************************************************************************
* Power Interfaces
******************************************************************************/
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index 54a1408c8015..fb0dec4ed3a6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -203,12 +203,33 @@ static bool dmub_abm_init_config(struct abm *abm,
return true;
}
+static bool dmub_abm_set_pause(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int stream_inst)
+{
+ union dmub_rb_cmd cmd;
+ struct dc_context *dc = abm->ctx;
+ uint8_t panel_mask = 0x01 << panel_inst;
+
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.abm_pause.header.type = DMUB_CMD__ABM;
+ cmd.abm_pause.header.sub_type = DMUB_CMD__ABM_PAUSE;
+ cmd.abm_pause.abm_pause_data.enable = pause;
+ cmd.abm_pause.abm_pause_data.panel_mask = panel_mask;
+ cmd.abm_set_level.header.payload_bytes = sizeof(struct dmub_cmd_abm_pause_data);
+
+ dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
+ dc_dmub_srv_cmd_execute(dc->dmub_srv);
+ dc_dmub_srv_wait_idle(dc->dmub_srv);
+
+ return true;
+}
+
static const struct abm_funcs abm_funcs = {
.abm_init = dmub_abm_init,
.set_abm_level = dmub_abm_set_level,
.get_current_backlight = dmub_abm_get_current_backlight,
.get_target_backlight = dmub_abm_get_target_backlight,
.init_abm_config = dmub_abm_init_config,
+ .set_abm_pause = dmub_abm_set_pause,
};
static void dmub_abm_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
index 142753644377..ecb4191b6e64 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
@@ -54,6 +54,7 @@ struct abm_funcs {
const char *src,
unsigned int bytes,
unsigned int inst);
+ bool (*set_abm_pause)(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int otg_inst);
};
#endif
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 03110f59b50d..4a41549109dd 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -1732,6 +1732,11 @@ enum dmub_cmd_abm_type {
* Enable/disable fractional duty cycle for backlight PWM.
*/
DMUB_CMD__ABM_SET_PWM_FRAC = 5,
+
+ /**
+ * unregister vertical interrupt after steady state is reached
+ */
+ DMUB_CMD__ABM_PAUSE = 6,
};
/**
@@ -2087,6 +2092,50 @@ struct dmub_rb_cmd_abm_init_config {
struct dmub_cmd_abm_init_config_data abm_init_config_data;
};
+/**
+ * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
+ */
+
+struct dmub_cmd_abm_pause_data {
+
+ /**
+ * Panel Control HW instance mask.
+ * Bit 0 is Panel Control HW instance 0.
+ * Bit 1 is Panel Control HW instance 1.
+ */
+ uint8_t panel_mask;
+
+ /**
+ * OTG hw instance
+ */
+ uint8_t otg_inst;
+
+ /**
+ * Enable or disable ABM pause
+ */
+ uint8_t enable;
+
+ /**
+ * Explicit padding to 4 byte boundary.
+ */
+ uint8_t pad[1];
+};
+
+/**
+ * Definition of a DMUB_CMD__ABM_PAUSE command.
+ */
+struct dmub_rb_cmd_abm_pause {
+ /**
+ * Command header.
+ */
+ struct dmub_cmd_header header;
+
+ /**
+ * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
+ */
+ struct dmub_cmd_abm_pause_data abm_pause_data;
+};
+
/**
* Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
*/
@@ -2365,6 +2414,11 @@ union dmub_rb_cmd {
*/
struct dmub_rb_cmd_abm_init_config abm_init_config;
+ /**
+ * Definition of a DMUB_CMD__ABM_PAUSE command.
+ */
+ struct dmub_rb_cmd_abm_pause abm_pause;
+
/**
* Definition of a DMUB_CMD__DP_AUX_ACCESS command.
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 05/24] drm/amd/display: Add debug support to override the Minimum DRAM Clock
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (3 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 04/24] drm/amd/display: add vsync notify to dmub for abm pause Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 06/24] drm/amd/display: update cur_lane_setting to an array one for each lane Anson Jacob
` (19 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, David Galiffi,
Alvin Lee
From: David Galiffi <David.Galiffi@amd.com>
[Why]
Requested feature to assist with Thermal, Acoustic, Power, and
Performance tuning.
[How]
Add a debug field that will override calculated minimum DRAM clock,
if the debug value is larger than the calculate value.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index b194a2727bd8..a46c663ed8c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -565,6 +565,7 @@ struct dc_debug_options {
enum wm_report_mode pplib_wm_report_mode;
unsigned int min_disp_clk_khz;
unsigned int min_dpp_clk_khz;
+ unsigned int min_dram_clk_khz;
int sr_exit_time_dpm0_ns;
int sr_enter_plus_exit_time_dpm0_ns;
int sr_exit_time_ns;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 3c388afa06dc..aeb868ace31c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3117,6 +3117,10 @@ void dcn20_calculate_dlg_params(
context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
+
+ if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)
+ context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;
+
context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
context->bw_ctx.bw.dcn.clk.p_state_change_support =
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 06/24] drm/amd/display: update cur_lane_setting to an array one for each lane
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (4 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 05/24] drm/amd/display: Add debug support to override the Minimum DRAM Clock Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 07/24] drm/amd/display: add function to convert hw to dpcd lane settings Anson Jacob
` (18 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Wenjing Liu,
Jun Lei
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
To support per lane lane setting adjustment, we need to change cur_lane_setting
to an array one for each lane as the first step.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ++++----
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 ---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
drivers/gpu/drm/amd/display/dc/dc_link.h | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index f3ada9b6be5a..814f67d86a3c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -379,9 +379,9 @@ static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
return -EINVAL;
snprintf(rd_buf, rd_buf_size, " %d %d %d\n",
- link->cur_lane_setting.VOLTAGE_SWING,
- link->cur_lane_setting.PRE_EMPHASIS,
- link->cur_lane_setting.POST_CURSOR2);
+ link->cur_lane_setting[0].VOLTAGE_SWING,
+ link->cur_lane_setting[0].PRE_EMPHASIS,
+ link->cur_lane_setting[0].POST_CURSOR2);
while (size) {
if (*pos >= rd_buf_size)
@@ -733,7 +733,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
}
for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
- link_training_settings.lane_settings[i] = link->cur_lane_setting;
+ link_training_settings.lane_settings[i] = link->cur_lane_setting[i];
dc_link_set_test_pattern(
link,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 6421c896f2a1..750f1ae268c3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -676,8 +676,6 @@ static void dpcd_set_lt_pattern_and_lane_settings(
dpcd_base_lt_offset,
dpcd_lt_buffer,
size_in_bytes + sizeof(dpcd_pattern.raw));
-
- link->cur_lane_setting = lt_settings->lane_settings[0];
}
bool dp_is_cr_done(enum dc_lane_count ln_count,
@@ -1145,7 +1143,6 @@ enum dc_status dpcd_set_lane_settings(
dpcd_lane[0].bits.MAX_SWING_REACHED,
dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
}
- link->cur_lane_setting = link_training_setting->lane_settings[0];
return status;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index cc4b28e94727..368e834c6809 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -372,6 +372,9 @@ void dp_set_hw_lane_settings(
#else
encoder->funcs->dp_set_lane_settings(encoder, link_settings);
#endif
+ memmove(link->cur_lane_setting,
+ link_settings->lane_settings,
+ sizeof(link->cur_lane_setting));
}
void dp_set_hw_test_pattern(
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 56340a176554..a73d64b1fd33 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -121,7 +121,7 @@ struct dc_link {
struct dc_link_settings reported_link_cap;
struct dc_link_settings verified_link_cap;
struct dc_link_settings cur_link_settings;
- struct dc_lane_settings cur_lane_setting;
+ struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];
struct dc_link_settings preferred_link_setting;
struct dc_link_training_overrides preferred_training_settings;
struct dp_audio_test_data audio_test_data;
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 07/24] drm/amd/display: add function to convert hw to dpcd lane settings
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (5 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 06/24] drm/amd/display: update cur_lane_setting to an array one for each lane Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 08/24] drm/amd/display: implement decide " Anson Jacob
` (17 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Wenjing Liu,
Jun Lei
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
Unify the code which handles the conversion between hw lane setting
and dpcd lane setting.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 113 ++++++------------
.../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 5 +-
2 files changed, 39 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 750f1ae268c3..f7be58800da6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -553,45 +553,8 @@ static void dpcd_set_lt_pattern_and_lane_settings(
dpcd_base_lt_offset,
dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
}
- /*****************************************************************
- * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
- *****************************************************************/
- for (lane = 0; lane <
- (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
- if (dp_get_link_encoding_format(<_settings->link_settings) ==
- DP_128b_132b_ENCODING) {
- dpcd_lane[lane].tx_ffe.PRESET_VALUE =
- lt_settings->lane_settings[lane].FFE_PRESET.settings.level;
- } else if (dp_get_link_encoding_format(<_settings->link_settings) ==
- DP_8b_10b_ENCODING) {
- dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
- (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
- dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
- (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
-
- dpcd_lane[lane].bits.MAX_SWING_REACHED =
- (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
- VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
- dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
- (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
- PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
- }
-#else
- dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
- (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
- dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
- (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
-
- dpcd_lane[lane].bits.MAX_SWING_REACHED =
- (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
- VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
- dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
- (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
- PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
-#endif
- }
+ dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->lane_settings, dpcd_lane);
/* concatenate everything into one buffer*/
@@ -717,6 +680,37 @@ bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
return align_status.bits.INTERLANE_ALIGN_DONE == 1;
}
+void dp_hw_to_dpcd_lane_settings(
+ const struct link_training_settings *lt_settings,
+ const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
+ union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])
+{
+ uint8_t lane = 0;
+
+ for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
+ if (dp_get_link_encoding_format(<_settings->link_settings) ==
+ DP_8b_10b_ENCODING) {
+ dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET =
+ (uint8_t)(hw_lane_settings[lane].VOLTAGE_SWING);
+ dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET =
+ (uint8_t)(hw_lane_settings[lane].PRE_EMPHASIS);
+ dpcd_lane_settings[lane].bits.MAX_SWING_REACHED =
+ (hw_lane_settings[lane].VOLTAGE_SWING ==
+ VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
+ dpcd_lane_settings[lane].bits.MAX_PRE_EMPHASIS_REACHED =
+ (hw_lane_settings[lane].PRE_EMPHASIS ==
+ PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
+ }
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+ else if (dp_get_link_encoding_format(<_settings->link_settings) ==
+ DP_128b_132b_ENCODING) {
+ dpcd_lane_settings[lane].tx_ffe.PRESET_VALUE =
+ hw_lane_settings[lane].FFE_PRESET.settings.level;
+ }
+#endif
+ }
+}
+
void dp_update_drive_settings(
struct link_training_settings *dest,
struct link_training_settings src)
@@ -1036,46 +1030,9 @@ enum dc_status dpcd_set_lane_settings(
lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
- for (lane = 0; lane <
- (uint32_t)(link_training_setting->
- link_settings.lane_count);
- lane++) {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
- if (dp_get_link_encoding_format(&link_training_setting->link_settings) ==
- DP_128b_132b_ENCODING) {
- dpcd_lane[lane].tx_ffe.PRESET_VALUE =
- link_training_setting->lane_settings[lane].FFE_PRESET.settings.level;
- } else if (dp_get_link_encoding_format(&link_training_setting->link_settings) ==
- DP_8b_10b_ENCODING) {
- dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
- (uint8_t)(link_training_setting->lane_settings[lane].VOLTAGE_SWING);
- dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
- (uint8_t)(link_training_setting->lane_settings[lane].PRE_EMPHASIS);
-
- dpcd_lane[lane].bits.MAX_SWING_REACHED =
- (link_training_setting->lane_settings[lane].VOLTAGE_SWING ==
- VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
- dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
- (link_training_setting->lane_settings[lane].PRE_EMPHASIS ==
- PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
- }
-#else
- dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
- (uint8_t)(link_training_setting->
- lane_settings[lane].VOLTAGE_SWING);
- dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
- (uint8_t)(link_training_setting->
- lane_settings[lane].PRE_EMPHASIS);
- dpcd_lane[lane].bits.MAX_SWING_REACHED =
- (link_training_setting->
- lane_settings[lane].VOLTAGE_SWING ==
- VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
- dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
- (link_training_setting->
- lane_settings[lane].PRE_EMPHASIS ==
- PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
-#endif
- }
+ dp_hw_to_dpcd_lane_settings(link_training_setting,
+ link_training_setting->lane_settings,
+ dpcd_lane);
status = core_link_write_dpcd(link,
lane0_set_address,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index cb8e785a866e..c70375117519 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -147,7 +147,10 @@ bool dp_is_interlane_aligned(union lane_align_status_updated align_status);
bool dp_is_max_vs_reached(
const struct link_training_settings *lt_settings);
-
+void dp_hw_to_dpcd_lane_settings(
+ const struct link_training_settings *lt_settings,
+ const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
+ union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]);
void dp_update_drive_settings(
struct link_training_settings *dest,
struct link_training_settings src);
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 08/24] drm/amd/display: implement decide lane settings
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (6 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 07/24] drm/amd/display: add function to convert hw to dpcd lane settings Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 09/24] drm/amd/display: rename lane_settings to hw_lane_settings Anson Jacob
` (16 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Wenjing Liu,
Jun Lei
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
Decouple lane settings decision logic all to its own function.
The function takes in lane adjust array and link training settings
and decide what hw lane setting and dpcd lane setting should be used.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 292 ++++++------------
.../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 16 +-
2 files changed, 102 insertions(+), 206 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index f7be58800da6..8e6af080cbe9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -105,6 +105,7 @@ static bool decide_fallback_link_setting(
static struct dc_link_settings get_common_supported_link_settings(
struct dc_link_settings link_setting_a,
struct dc_link_settings link_setting_b);
+static void maximize_lane_settings(struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
const struct dc_link_settings *link_settings)
@@ -520,7 +521,6 @@ static void dpcd_set_lt_pattern_and_lane_settings(
uint8_t dpcd_lt_buffer[5] = {0};
union dpcd_training_pattern dpcd_pattern = { {0} };
- uint32_t lane;
uint32_t size_in_bytes;
bool edp_workaround = false; /* TODO link_prop.INTERNAL */
dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
@@ -711,34 +711,39 @@ void dp_hw_to_dpcd_lane_settings(
}
}
-void dp_update_drive_settings(
- struct link_training_settings *dest,
- struct link_training_settings src)
+void dp_decide_lane_settings(
+ const struct link_training_settings *lt_settings,
+ const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
+ struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
+ union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])
{
uint32_t lane;
- for (lane = 0; lane < src.link_settings.lane_count; lane++) {
- if (dest->voltage_swing == NULL)
- dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
- else
- dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
-
- if (dest->pre_emphasis == NULL)
- dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
- else
- dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
-
- if (dest->post_cursor2 == NULL)
- dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
- else
- dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
+ for (lane = 0; lane < (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
+ if (dp_get_link_encoding_format(<_settings->link_settings) ==
+ DP_8b_10b_ENCODING) {
+ hw_lane_settings[lane].VOLTAGE_SWING =
+ (enum dc_voltage_swing)(ln_adjust[lane].bits.
+ VOLTAGE_SWING_LANE);
+ hw_lane_settings[lane].PRE_EMPHASIS =
+ (enum dc_pre_emphasis)(ln_adjust[lane].bits.
+ PRE_EMPHASIS_LANE);
+ }
#if defined(CONFIG_DRM_AMD_DC_DCN)
- if (dest->ffe_preset == NULL)
- dest->lane_settings[lane].FFE_PRESET = src.lane_settings[lane].FFE_PRESET;
- else
- dest->lane_settings[lane].FFE_PRESET = *dest->ffe_preset;
+ else if (dp_get_link_encoding_format(<_settings->link_settings) ==
+ DP_128b_132b_ENCODING) {
+ hw_lane_settings[lane].FFE_PRESET.raw =
+ ln_adjust[lane].tx_ffe.PRESET_VALUE;
+ }
#endif
}
+
+ /*
+ * We find the maximum of the requested settings across all lanes
+ * and set this maximum for all lanes
+ */
+ maximize_lane_settings(hw_lane_settings);
+ dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings);
}
static uint8_t get_nibble_at_index(const uint8_t *buf,
@@ -768,55 +773,28 @@ static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
}
-static void find_max_drive_settings(
- const struct link_training_settings *link_training_setting,
- struct link_training_settings *max_lt_setting)
+static void maximize_lane_settings(struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
{
uint32_t lane;
struct dc_lane_settings max_requested;
- max_requested.VOLTAGE_SWING =
- link_training_setting->
- lane_settings[0].VOLTAGE_SWING;
- max_requested.PRE_EMPHASIS =
- link_training_setting->
- lane_settings[0].PRE_EMPHASIS;
- /*max_requested.postCursor2 =
- * link_training_setting->laneSettings[0].postCursor2;*/
+ max_requested.VOLTAGE_SWING = lane_settings[0].VOLTAGE_SWING;
+ max_requested.PRE_EMPHASIS = lane_settings[0].PRE_EMPHASIS;
#if defined(CONFIG_DRM_AMD_DC_DCN)
- max_requested.FFE_PRESET =
- link_training_setting->lane_settings[0].FFE_PRESET;
+ max_requested.FFE_PRESET = lane_settings[0].FFE_PRESET;
#endif
/* Determine what the maximum of the requested settings are*/
- for (lane = 1; lane < link_training_setting->link_settings.lane_count;
- lane++) {
- if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
- max_requested.VOLTAGE_SWING)
-
- max_requested.VOLTAGE_SWING =
- link_training_setting->
- lane_settings[lane].VOLTAGE_SWING;
-
- if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
- max_requested.PRE_EMPHASIS)
- max_requested.PRE_EMPHASIS =
- link_training_setting->
- lane_settings[lane].PRE_EMPHASIS;
+ for (lane = 1; lane < LANE_COUNT_DP_MAX; lane++) {
+ if (lane_settings[lane].VOLTAGE_SWING > max_requested.VOLTAGE_SWING)
+ max_requested.VOLTAGE_SWING = lane_settings[lane].VOLTAGE_SWING;
- /*
- if (link_training_setting->laneSettings[lane].postCursor2 >
- max_requested.postCursor2)
- {
- max_requested.postCursor2 =
- link_training_setting->laneSettings[lane].postCursor2;
- }
- */
+ if (lane_settings[lane].PRE_EMPHASIS > max_requested.PRE_EMPHASIS)
+ max_requested.PRE_EMPHASIS = lane_settings[lane].PRE_EMPHASIS;
#if defined(CONFIG_DRM_AMD_DC_DCN)
- if (link_training_setting->lane_settings[lane].FFE_PRESET.settings.level >
+ if (lane_settings[lane].FFE_PRESET.settings.level >
max_requested.FFE_PRESET.settings.level)
max_requested.FFE_PRESET.settings.level =
- link_training_setting->
lane_settings[lane].FFE_PRESET.settings.level;
#endif
}
@@ -828,10 +806,7 @@ static void find_max_drive_settings(
if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
- /*
- if (max_requested.postCursor2 > PostCursor2_MaxLevel)
- max_requested.postCursor2 = PostCursor2_MaxLevel;
- */
+
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (max_requested.FFE_PRESET.settings.level > DP_FFE_PRESET_MAX_LEVEL)
max_requested.FFE_PRESET.settings.level = DP_FFE_PRESET_MAX_LEVEL;
@@ -845,61 +820,31 @@ static void find_max_drive_settings(
get_max_pre_emphasis_for_voltage_swing(
max_requested.VOLTAGE_SWING);
- /*
- * Post Cursor2 levels are completely independent from
- * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
- * can only be applied to each allowable combination of voltage
- * swing and pre-emphasis levels */
- /* if ( max_requested.postCursor2 >
- * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
- * max_requested.postCursor2 =
- * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
- */
-
- max_lt_setting->link_settings.link_rate =
- link_training_setting->link_settings.link_rate;
- max_lt_setting->link_settings.lane_count =
- link_training_setting->link_settings.lane_count;
- max_lt_setting->link_settings.link_spread =
- link_training_setting->link_settings.link_spread;
-
- for (lane = 0; lane <
- link_training_setting->link_settings.lane_count;
- lane++) {
- max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
- max_requested.VOLTAGE_SWING;
- max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
- max_requested.PRE_EMPHASIS;
- /*max_lt_setting->laneSettings[lane].postCursor2 =
- * max_requested.postCursor2;
- */
+ for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
+ lane_settings[lane].VOLTAGE_SWING = max_requested.VOLTAGE_SWING;
+ lane_settings[lane].PRE_EMPHASIS = max_requested.PRE_EMPHASIS;
#if defined(CONFIG_DRM_AMD_DC_DCN)
- max_lt_setting->lane_settings[lane].FFE_PRESET =
- max_requested.FFE_PRESET;
+ lane_settings[lane].FFE_PRESET = max_requested.FFE_PRESET;
#endif
}
}
-enum dc_status dp_get_lane_status_and_drive_settings(
+enum dc_status dp_get_lane_status_and_lane_adjust(
struct dc_link *link,
const struct link_training_settings *link_training_setting,
- union lane_status *ln_status,
- union lane_align_status_updated *ln_status_updated,
- struct link_training_settings *req_settings,
+ union lane_status ln_status[LANE_COUNT_DP_MAX],
+ union lane_align_status_updated *ln_align,
+ union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
uint32_t offset)
{
unsigned int lane01_status_address = DP_LANE0_1_STATUS;
uint8_t lane_adjust_offset = 4;
unsigned int lane01_adjust_address;
uint8_t dpcd_buf[6] = {0};
- union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
- struct link_training_settings request_settings = { {0} };
uint32_t lane;
enum dc_status status;
- memset(req_settings, '\0', sizeof(struct link_training_settings));
-
if (is_repeater(link, offset)) {
lane01_status_address =
DP_LANE0_1_STATUS_PHY_REPEATER1 +
@@ -919,11 +864,11 @@ enum dc_status dp_get_lane_status_and_drive_settings(
ln_status[lane].raw =
get_nibble_at_index(&dpcd_buf[0], lane);
- dpcd_lane_adjust[lane].raw =
+ ln_adjust[lane].raw =
get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
}
- ln_status_updated->raw = dpcd_buf[2];
+ ln_align->raw = dpcd_buf[2];
if (is_repeater(link, offset)) {
DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
@@ -962,55 +907,6 @@ enum dc_status dp_get_lane_status_and_drive_settings(
dpcd_buf[lane_adjust_offset + 1]);
}
- /*copy to req_settings*/
- request_settings.link_settings.lane_count =
- link_training_setting->link_settings.lane_count;
- request_settings.link_settings.link_rate =
- link_training_setting->link_settings.link_rate;
- request_settings.link_settings.link_spread =
- link_training_setting->link_settings.link_spread;
-
- for (lane = 0; lane <
- (uint32_t)(link_training_setting->link_settings.lane_count);
- lane++) {
-
-#if defined(CONFIG_DRM_AMD_DC_DCN)
- if (dp_get_link_encoding_format(&link_training_setting->link_settings) ==
- DP_128b_132b_ENCODING) {
- request_settings.lane_settings[lane].FFE_PRESET.raw =
- dpcd_lane_adjust[lane].tx_ffe.PRESET_VALUE;
- } else if (dp_get_link_encoding_format(&link_training_setting->link_settings) ==
- DP_8b_10b_ENCODING) {
- request_settings.lane_settings[lane].VOLTAGE_SWING =
- (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
- VOLTAGE_SWING_LANE);
- request_settings.lane_settings[lane].PRE_EMPHASIS =
- (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
- PRE_EMPHASIS_LANE);
- }
-#else
- request_settings.lane_settings[lane].VOLTAGE_SWING =
- (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
- VOLTAGE_SWING_LANE);
- request_settings.lane_settings[lane].PRE_EMPHASIS =
- (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
- PRE_EMPHASIS_LANE);
-#endif
- }
-
- /*Note: for postcursor2, read adjusted
- * postcursor2 settings from*/
- /*DpcdAddress_AdjustRequestPostCursor2 =
- *0x020C (not implemented yet)*/
-
- /* we find the maximum of the requested settings across all lanes*/
- /* and set this maximum for all lanes*/
- find_max_drive_settings(&request_settings, req_settings);
-
- /* if post cursor 2 is needed in the future,
- * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
- */
-
return status;
}
@@ -1020,7 +916,6 @@ enum dc_status dpcd_set_lane_settings(
uint32_t offset)
{
union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
- uint32_t lane;
unsigned int lane0_set_address;
enum dc_status status;
@@ -1141,17 +1036,18 @@ static bool perform_post_lt_adj_req_sequence(
adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
adj_req_timer++) {
- struct link_training_settings req_settings;
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
union lane_align_status_updated
dpcd_lane_status_updated;
+ union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+ union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX] = { { {0} } };
- dp_get_lane_status_and_drive_settings(
+ dp_get_lane_status_and_lane_adjust(
link,
lt_settings,
dpcd_lane_status,
&dpcd_lane_status_updated,
- &req_settings,
+ dpcd_lane_adjust,
DPRX);
if (dpcd_lane_status_updated.bits.
@@ -1170,10 +1066,9 @@ static bool perform_post_lt_adj_req_sequence(
if (lt_settings->
lane_settings[lane].VOLTAGE_SWING !=
- req_settings.lane_settings[lane].
- VOLTAGE_SWING ||
+ dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_LANE ||
lt_settings->lane_settings[lane].PRE_EMPHASIS !=
- req_settings.lane_settings[lane].PRE_EMPHASIS) {
+ dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_LANE) {
req_drv_setting_changed = true;
break;
@@ -1181,8 +1076,8 @@ static bool perform_post_lt_adj_req_sequence(
}
if (req_drv_setting_changed) {
- dp_update_drive_settings(
- lt_settings, req_settings);
+ dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
+ lt_settings->lane_settings, dpcd_lane_settings);
dc_link_dp_set_drive_settings(link,
lt_settings);
@@ -1262,13 +1157,14 @@ static enum link_training_result perform_channel_equalization_sequence(
struct link_training_settings *lt_settings,
uint32_t offset)
{
- struct link_training_settings req_settings;
enum dc_dp_training_pattern tr_pattern;
uint32_t retries_ch_eq;
uint32_t wait_time_microsec;
enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
union lane_align_status_updated dpcd_lane_status_updated = { {0} };
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
+ union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+ union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX] = { { {0} } };
/* Note: also check that TPS4 is a supported feature*/
@@ -1317,12 +1213,12 @@ static enum link_training_result perform_channel_equalization_sequence(
/* 4. Read lane status and requested
* drive settings as set by the sink*/
- dp_get_lane_status_and_drive_settings(
+ dp_get_lane_status_and_lane_adjust(
link,
lt_settings,
dpcd_lane_status,
&dpcd_lane_status_updated,
- &req_settings,
+ dpcd_lane_adjust,
offset);
/* 5. check CR done*/
@@ -1336,7 +1232,8 @@ static enum link_training_result perform_channel_equalization_sequence(
return LINK_TRAINING_SUCCESS;
/* 7. update VS/PE/PC2 in lt_settings*/
- dp_update_drive_settings(lt_settings, req_settings);
+ dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
+ lt_settings->lane_settings, dpcd_lane_settings);
}
return LINK_TRAINING_EQ_FAIL_EQ;
@@ -1362,10 +1259,11 @@ static enum link_training_result perform_clock_recovery_sequence(
uint32_t retries_cr;
uint32_t retry_count;
uint32_t wait_time_microsec;
- struct link_training_settings req_settings;
enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
union lane_align_status_updated dpcd_lane_status_updated;
+ union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+ union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX] = { { {0} } };
retries_cr = 0;
retry_count = 0;
@@ -1419,12 +1317,12 @@ static enum link_training_result perform_clock_recovery_sequence(
/* 4. Read lane status and requested drive
* settings as set by the sink
*/
- dp_get_lane_status_and_drive_settings(
+ dp_get_lane_status_and_lane_adjust(
link,
lt_settings,
dpcd_lane_status,
&dpcd_lane_status_updated,
- &req_settings,
+ dpcd_lane_adjust,
offset);
/* 5. check CR done*/
@@ -1442,32 +1340,25 @@ static enum link_training_result perform_clock_recovery_sequence(
break;
#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN)
- if ((dp_get_link_encoding_format(<_settings->link_settings) == DP_128b_132b_ENCODING) &&
- lt_settings->lane_settings[0].FFE_PRESET.settings.level ==
- req_settings.lane_settings[0].FFE_PRESET.settings.level)
- retries_cr++;
- else if ((dp_get_link_encoding_format(<_settings->link_settings) == DP_8b_10b_ENCODING) &&
- lt_settings->lane_settings[0].VOLTAGE_SWING ==
- req_settings.lane_settings[0].VOLTAGE_SWING)
- retries_cr++;
- else
- retries_cr = 0;
-#else
/* 7. same lane settings*/
/* Note: settings are the same for all lanes,
* so comparing first lane is sufficient*/
- if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
- req_settings.lane_settings[0].VOLTAGE_SWING)
- && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
- req_settings.lane_settings[0].PRE_EMPHASIS))
+ if ((dp_get_link_encoding_format(<_settings->link_settings) == DP_8b_10b_ENCODING) &&
+ lt_settings->lane_settings[0].VOLTAGE_SWING ==
+ dpcd_lane_adjust[0].bits.VOLTAGE_SWING_LANE)
+ retries_cr++;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+ else if ((dp_get_link_encoding_format(<_settings->link_settings) == DP_128b_132b_ENCODING) &&
+ lt_settings->lane_settings[0].FFE_PRESET.settings.level ==
+ dpcd_lane_adjust[0].tx_ffe.PRESET_VALUE)
retries_cr++;
+#endif
else
retries_cr = 0;
-#endif
/* 8. update VS/PE/PC2 in lt_settings*/
- dp_update_drive_settings(lt_settings, req_settings);
+ dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
+ lt_settings->lane_settings, dpcd_lane_settings);
retry_count++;
}
@@ -2077,9 +1968,10 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
uint8_t loop_count = 0;
uint32_t aux_rd_interval = 0;
uint32_t wait_time = 0;
- struct link_training_settings req_settings;
union lane_align_status_updated dpcd_lane_status_updated = { {0} };
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
+ union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+ union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX] = { { {0} } };
enum link_training_result status = LINK_TRAINING_SUCCESS;
/* Transmit 128b/132b_TPS1 over Main-Link and Set TRAINING_PATTERN_SET to 01h */
@@ -2087,9 +1979,10 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
dpcd_set_training_pattern(link, lt_settings->pattern_for_cr);
/* Adjust TX_FFE_PRESET_VALUE as requested */
- dp_get_lane_status_and_drive_settings(link, lt_settings, dpcd_lane_status,
- &dpcd_lane_status_updated, &req_settings, DPRX);
- dp_update_drive_settings(lt_settings, req_settings);
+ dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
+ &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
+ dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
+ lt_settings->lane_settings, dpcd_lane_settings);
dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval);
dp_set_hw_lane_settings(link, lt_settings, DPRX);
dpcd_set_lane_settings(link, lt_settings, DPRX);
@@ -2103,9 +1996,10 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
loop_count++;
dp_wait_for_training_aux_rd_interval(link, aux_rd_interval);
wait_time += aux_rd_interval;
- dp_get_lane_status_and_drive_settings(link, lt_settings, dpcd_lane_status,
- &dpcd_lane_status_updated, &req_settings, DPRX);
- dp_update_drive_settings(lt_settings, req_settings);
+ dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
+ &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
+ dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
+ lt_settings->lane_settings, dpcd_lane_settings);
dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval);
if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count,
dpcd_lane_status)) {
@@ -2134,8 +2028,8 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
dp_wait_for_training_aux_rd_interval(link,
lt_settings->eq_pattern_time);
wait_time += lt_settings->eq_pattern_time;
- dp_get_lane_status_and_drive_settings(link, lt_settings, dpcd_lane_status,
- &dpcd_lane_status_updated, &req_settings, DPRX);
+ dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
+ &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
}
}
@@ -2148,9 +2042,9 @@ static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
{
/* Assumption: assume hardware has transmitted eq pattern */
enum link_training_result status = LINK_TRAINING_SUCCESS;
- struct link_training_settings req_settings;
union lane_align_status_updated dpcd_lane_status_updated = { {0} };
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
+ union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
uint32_t wait_time = 0;
/* initiate CDS done sequence */
@@ -2161,8 +2055,8 @@ static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
dp_wait_for_training_aux_rd_interval(link,
lt_settings->cds_pattern_time);
wait_time += lt_settings->cds_pattern_time;
- dp_get_lane_status_and_drive_settings(link, lt_settings, dpcd_lane_status,
- &dpcd_lane_status_updated, &req_settings, DPRX);
+ dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
+ &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
if (dp_is_symbol_locked(lt_settings->link_settings.lane_count, dpcd_lane_status) &&
dpcd_lane_status_updated.bits.CDS_INTERLANE_ALIGN_DONE_128b_132b) {
/* pass */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index c70375117519..a6d3d859754a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -121,12 +121,12 @@ enum dc_status dpcd_set_lane_settings(
const struct link_training_settings *link_training_setting,
uint32_t offset);
/* Read training status and adjustment requests from DPCD. */
-enum dc_status dp_get_lane_status_and_drive_settings(
+enum dc_status dp_get_lane_status_and_lane_adjust(
struct dc_link *link,
const struct link_training_settings *link_training_setting,
- union lane_status *ln_status,
- union lane_align_status_updated *ln_status_updated,
- struct link_training_settings *req_settings,
+ union lane_status ln_status[LANE_COUNT_DP_MAX],
+ union lane_align_status_updated *ln_align,
+ union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
uint32_t offset);
void dp_wait_for_training_aux_rd_interval(
@@ -151,9 +151,11 @@ void dp_hw_to_dpcd_lane_settings(
const struct link_training_settings *lt_settings,
const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]);
-void dp_update_drive_settings(
- struct link_training_settings *dest,
- struct link_training_settings src);
+void dp_decide_lane_settings(
+ const struct link_training_settings *lt_settings,
+ const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
+ struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
+ union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]);
uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval);
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 09/24] drm/amd/display: rename lane_settings to hw_lane_settings
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (7 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 08/24] drm/amd/display: implement decide " Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 10/24] drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings Anson Jacob
` (15 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Wenjing Liu,
Jun Lei
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
This is one of the major steps to decouple hw lane settings
from dpcd lane settings.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ++--
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 38 +++++++++----------
.../drm/amd/display/dc/core/dc_link_hwss.c | 4 +-
.../drm/amd/display/dc/dce/dce_link_encoder.c | 6 +--
.../amd/display/dc/dcn10/dcn10_link_encoder.c | 6 +--
.../amd/display/include/link_service_types.h | 16 +++++++-
6 files changed, 46 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 814f67d86a3c..7ceb4a14fa2a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -535,11 +535,11 @@ static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
/* apply phy settings from user */
for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
- link_lane_settings.lane_settings[r].VOLTAGE_SWING =
+ link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
(enum dc_voltage_swing) (param[0]);
- link_lane_settings.lane_settings[r].PRE_EMPHASIS =
+ link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
(enum dc_pre_emphasis) (param[1]);
- link_lane_settings.lane_settings[r].POST_CURSOR2 =
+ link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
(enum dc_post_cursor2) (param[2]);
}
@@ -733,7 +733,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
}
for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
- link_training_settings.lane_settings[i] = link->cur_lane_setting[i];
+ link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
dc_link_set_test_pattern(
link,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8e6af080cbe9..84eabdca8b24 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -554,7 +554,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
}
- dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->lane_settings, dpcd_lane);
+ dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, dpcd_lane);
/* concatenate everything into one buffer*/
@@ -926,7 +926,7 @@ enum dc_status dpcd_set_lane_settings(
((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
dp_hw_to_dpcd_lane_settings(link_training_setting,
- link_training_setting->lane_settings,
+ link_training_setting->hw_lane_settings,
dpcd_lane);
status = core_link_write_dpcd(link,
@@ -1006,7 +1006,7 @@ bool dp_is_max_vs_reached(
for (lane = 0; lane <
(uint32_t)(lt_settings->link_settings.lane_count);
lane++) {
- if (lt_settings->lane_settings[lane].VOLTAGE_SWING
+ if (lt_settings->hw_lane_settings[lane].VOLTAGE_SWING
== VOLTAGE_SWING_MAX_LEVEL)
return true;
}
@@ -1065,9 +1065,9 @@ static bool perform_post_lt_adj_req_sequence(
for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
if (lt_settings->
- lane_settings[lane].VOLTAGE_SWING !=
+ hw_lane_settings[lane].VOLTAGE_SWING !=
dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_LANE ||
- lt_settings->lane_settings[lane].PRE_EMPHASIS !=
+ lt_settings->hw_lane_settings[lane].PRE_EMPHASIS !=
dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_LANE) {
req_drv_setting_changed = true;
@@ -1077,7 +1077,7 @@ static bool perform_post_lt_adj_req_sequence(
if (req_drv_setting_changed) {
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
- lt_settings->lane_settings, dpcd_lane_settings);
+ lt_settings->hw_lane_settings, dpcd_lane_settings);
dc_link_dp_set_drive_settings(link,
lt_settings);
@@ -1233,7 +1233,7 @@ static enum link_training_result perform_channel_equalization_sequence(
/* 7. update VS/PE/PC2 in lt_settings*/
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
- lt_settings->lane_settings, dpcd_lane_settings);
+ lt_settings->hw_lane_settings, dpcd_lane_settings);
}
return LINK_TRAINING_EQ_FAIL_EQ;
@@ -1344,12 +1344,12 @@ static enum link_training_result perform_clock_recovery_sequence(
/* Note: settings are the same for all lanes,
* so comparing first lane is sufficient*/
if ((dp_get_link_encoding_format(<_settings->link_settings) == DP_8b_10b_ENCODING) &&
- lt_settings->lane_settings[0].VOLTAGE_SWING ==
+ lt_settings->hw_lane_settings[0].VOLTAGE_SWING ==
dpcd_lane_adjust[0].bits.VOLTAGE_SWING_LANE)
retries_cr++;
#if defined(CONFIG_DRM_AMD_DC_DCN)
else if ((dp_get_link_encoding_format(<_settings->link_settings) == DP_128b_132b_ENCODING) &&
- lt_settings->lane_settings[0].FFE_PRESET.settings.level ==
+ lt_settings->hw_lane_settings[0].FFE_PRESET.settings.level ==
dpcd_lane_adjust[0].tx_ffe.PRESET_VALUE)
retries_cr++;
#endif
@@ -1358,7 +1358,7 @@ static enum link_training_result perform_clock_recovery_sequence(
/* 8. update VS/PE/PC2 in lt_settings*/
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
- lt_settings->lane_settings, dpcd_lane_settings);
+ lt_settings->hw_lane_settings, dpcd_lane_settings);
retry_count++;
}
@@ -1561,15 +1561,15 @@ static void override_training_settings(
#endif
for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
- lt_settings->lane_settings[lane].VOLTAGE_SWING =
+ lt_settings->hw_lane_settings[lane].VOLTAGE_SWING =
lt_settings->voltage_swing != NULL ?
*lt_settings->voltage_swing :
VOLTAGE_SWING_LEVEL0;
- lt_settings->lane_settings[lane].PRE_EMPHASIS =
+ lt_settings->hw_lane_settings[lane].PRE_EMPHASIS =
lt_settings->pre_emphasis != NULL ?
*lt_settings->pre_emphasis
: PRE_EMPHASIS_DISABLED;
- lt_settings->lane_settings[lane].POST_CURSOR2 =
+ lt_settings->hw_lane_settings[lane].POST_CURSOR2 =
lt_settings->post_cursor2 != NULL ?
*lt_settings->post_cursor2
: POST_CURSOR2_DISABLED;
@@ -1826,8 +1826,8 @@ static void print_status_message(
link_rate,
lt_settings->link_settings.lane_count,
lt_result,
- lt_settings->lane_settings[0].VOLTAGE_SWING,
- lt_settings->lane_settings[0].PRE_EMPHASIS,
+ lt_settings->hw_lane_settings[0].VOLTAGE_SWING,
+ lt_settings->hw_lane_settings[0].PRE_EMPHASIS,
lt_spread);
}
@@ -1982,7 +1982,7 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
- lt_settings->lane_settings, dpcd_lane_settings);
+ lt_settings->hw_lane_settings, dpcd_lane_settings);
dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval);
dp_set_hw_lane_settings(link, lt_settings, DPRX);
dpcd_set_lane_settings(link, lt_settings, DPRX);
@@ -1999,7 +1999,7 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
- lt_settings->lane_settings, dpcd_lane_settings);
+ lt_settings->hw_lane_settings, dpcd_lane_settings);
dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval);
if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count,
dpcd_lane_status)) {
@@ -2113,7 +2113,7 @@ static enum link_training_result dp_perform_8b_10b_link_training(
}
for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
- lt_settings->lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0;
+ lt_settings->hw_lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0;
}
if (status == LINK_TRAINING_SUCCESS) {
@@ -3628,7 +3628,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
}
for (i = 0; i < 4; i++)
- link_training_settings.lane_settings[i] =
+ link_training_settings.hw_lane_settings[i] =
link_settings.lane_settings[i];
link_training_settings.link_settings = link_settings.link;
link_training_settings.allow_invalid_msa_timing_param = false;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 368e834c6809..2666af299bc2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -364,7 +364,7 @@ void dp_set_hw_lane_settings(
link->hpo_dp_link_enc->funcs->set_ffe(
link->hpo_dp_link_enc,
&link_settings->link_settings,
- link_settings->lane_settings[0].FFE_PRESET.raw);
+ link_settings->hw_lane_settings[0].FFE_PRESET.raw);
} else if (dp_get_link_encoding_format(&link_settings->link_settings)
== DP_8b_10b_ENCODING) {
encoder->funcs->dp_set_lane_settings(encoder, link_settings);
@@ -373,7 +373,7 @@ void dp_set_hw_lane_settings(
encoder->funcs->dp_set_lane_settings(encoder, link_settings);
#endif
memmove(link->cur_lane_setting,
- link_settings->lane_settings,
+ link_settings->hw_lane_settings,
sizeof(link->cur_lane_setting));
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 1e77ffee71b3..af4dcd6714cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -1348,9 +1348,9 @@ void dce110_link_encoder_dp_set_lane_settings(
/* translate lane settings */
training_lane_set.bits.VOLTAGE_SWING_SET =
- link_settings->lane_settings[lane].VOLTAGE_SWING;
+ link_settings->hw_lane_settings[lane].VOLTAGE_SWING;
training_lane_set.bits.PRE_EMPHASIS_SET =
- link_settings->lane_settings[lane].PRE_EMPHASIS;
+ link_settings->hw_lane_settings[lane].PRE_EMPHASIS;
/* post cursor 2 setting only applies to HBR2 link rate */
if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
@@ -1358,7 +1358,7 @@ void dce110_link_encoder_dp_set_lane_settings(
* to program post cursor 2 level */
training_lane_set.bits.POST_CURSOR2_SET =
- link_settings->lane_settings[lane].POST_CURSOR2;
+ link_settings->hw_lane_settings[lane].POST_CURSOR2;
}
cntl.lane_select = lane;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index 2dc4b4e4ba02..a8982ae7e876 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -1124,9 +1124,9 @@ void dcn10_link_encoder_dp_set_lane_settings(
/* translate lane settings */
training_lane_set.bits.VOLTAGE_SWING_SET =
- link_settings->lane_settings[lane].VOLTAGE_SWING;
+ link_settings->hw_lane_settings[lane].VOLTAGE_SWING;
training_lane_set.bits.PRE_EMPHASIS_SET =
- link_settings->lane_settings[lane].PRE_EMPHASIS;
+ link_settings->hw_lane_settings[lane].PRE_EMPHASIS;
/* post cursor 2 setting only applies to HBR2 link rate */
if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
@@ -1134,7 +1134,7 @@ void dcn10_link_encoder_dp_set_lane_settings(
* to program post cursor 2 level
*/
training_lane_set.bits.POST_CURSOR2_SET =
- link_settings->lane_settings[lane].POST_CURSOR2;
+ link_settings->hw_lane_settings[lane].POST_CURSOR2;
}
cntl.lane_select = lane;
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 9ffea7b40545..007274e73347 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -90,7 +90,6 @@ enum lttpr_mode {
struct link_training_settings {
struct dc_link_settings link_settings;
- struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
enum dc_voltage_swing *voltage_swing;
enum dc_pre_emphasis *pre_emphasis;
@@ -117,6 +116,21 @@ struct link_training_settings {
bool enhanced_framing;
bool allow_invalid_msa_timing_param;
enum lttpr_mode lttpr_mode;
+
+
+ /* TODO: Move hw_lane_settings along with lane adjust,
+ * lane align, offset and all other training states
+ * into a new structure called link training states,
+ * so link_training_settings becomes a constant input
+ * pre-decided prior to link training.
+ *
+ * The goal is to strictly decouple link training settings
+ * decision making process from link training states to
+ * prevent it from messy code practice of changing training
+ * decision on the fly.
+ */
+ struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX];
+
};
/*TODO: Move this enum test harness*/
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 10/24] drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (8 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 09/24] drm/amd/display: rename lane_settings to hw_lane_settings Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 11/24] drm/amd/display: add two lane settings training options Anson Jacob
` (14 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Wenjing Liu,
Jun Lei
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
As DP features expands, we have encountered many situations where we
must configure a different DPCD lane setting from hw lane settings we output.
The change is to decouple hw lane settings from dpcd lane settings to provide
flexibility to configure dpcd and hw individually.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 154 +++++++-----------
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 5 -
.../amd/display/include/link_service_types.h | 19 ++-
3 files changed, 70 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 84eabdca8b24..f13bf8ca93aa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -515,10 +515,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
enum dc_dp_training_pattern pattern,
uint32_t offset)
{
- union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
-
uint32_t dpcd_base_lt_offset;
-
uint8_t dpcd_lt_buffer[5] = {0};
union dpcd_training_pattern dpcd_pattern = { {0} };
uint32_t size_in_bytes;
@@ -554,16 +551,14 @@ static void dpcd_set_lt_pattern_and_lane_settings(
dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
}
- dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, dpcd_lane);
-
/* concatenate everything into one buffer*/
-
- size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
+ size_in_bytes = lt_settings->link_settings.lane_count *
+ sizeof(lt_settings->dpcd_lane_settings[0]);
// 0x00103 - 0x00102
memmove(
&dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
- dpcd_lane,
+ lt_settings->dpcd_lane_settings,
size_in_bytes);
if (is_repeater(link, offset)) {
@@ -575,7 +570,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
__func__,
offset,
dpcd_base_lt_offset,
- dpcd_lane[0].tx_ffe.PRESET_VALUE);
+ lt_settings->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
else if (dp_get_link_encoding_format(<_settings->link_settings) ==
DP_8b_10b_ENCODING)
#endif
@@ -584,10 +579,10 @@ static void dpcd_set_lt_pattern_and_lane_settings(
__func__,
offset,
dpcd_base_lt_offset,
- dpcd_lane[0].bits.VOLTAGE_SWING_SET,
- dpcd_lane[0].bits.PRE_EMPHASIS_SET,
- dpcd_lane[0].bits.MAX_SWING_REACHED,
- dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
+ lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
+ lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
+ lt_settings->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
+ lt_settings->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
} else {
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dp_get_link_encoding_format(<_settings->link_settings) ==
@@ -595,17 +590,17 @@ static void dpcd_set_lt_pattern_and_lane_settings(
DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X TX_FFE_PRESET_VALUE = %x\n",
__func__,
dpcd_base_lt_offset,
- dpcd_lane[0].tx_ffe.PRESET_VALUE);
+ lt_settings->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
else if (dp_get_link_encoding_format(<_settings->link_settings) ==
DP_8b_10b_ENCODING)
#endif
DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
__func__,
dpcd_base_lt_offset,
- dpcd_lane[0].bits.VOLTAGE_SWING_SET,
- dpcd_lane[0].bits.PRE_EMPHASIS_SET,
- dpcd_lane[0].bits.MAX_SWING_REACHED,
- dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
+ lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
+ lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
+ lt_settings->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
+ lt_settings->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
}
if (edp_workaround) {
/* for eDP write in 2 parts because the 5-byte burst is
@@ -620,7 +615,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
core_link_write_dpcd(
link,
DP_TRAINING_LANE0_SET,
- (uint8_t *)(dpcd_lane),
+ (uint8_t *)(lt_settings->dpcd_lane_settings),
size_in_bytes);
#if defined(CONFIG_DRM_AMD_DC_DCN)
@@ -915,7 +910,6 @@ enum dc_status dpcd_set_lane_settings(
const struct link_training_settings *link_training_setting,
uint32_t offset)
{
- union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
unsigned int lane0_set_address;
enum dc_status status;
@@ -925,34 +919,11 @@ enum dc_status dpcd_set_lane_settings(
lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
- dp_hw_to_dpcd_lane_settings(link_training_setting,
- link_training_setting->hw_lane_settings,
- dpcd_lane);
-
status = core_link_write_dpcd(link,
lane0_set_address,
- (uint8_t *)(dpcd_lane),
+ (uint8_t *)(link_training_setting->dpcd_lane_settings),
link_training_setting->link_settings.lane_count);
- /*
- if (LTSettings.link.rate == LinkRate_High2)
- {
- DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
- for ( uint32_t lane = 0;
- lane < lane_count_DPMax; lane++)
- {
- dpcd_lane2[lane].bits.post_cursor2_set =
- static_cast<unsigned char>(
- LTSettings.laneSettings[lane].postCursor2);
- dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
- }
- m_pDpcdAccessSrv->WriteDpcdData(
- DpcdAddress_Lane0Set2,
- reinterpret_cast<unsigned char*>(dpcd_lane2),
- LTSettings.link.lanes);
- }
- */
-
if (is_repeater(link, offset)) {
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dp_get_link_encoding_format(&link_training_setting->link_settings) ==
@@ -962,7 +933,7 @@ enum dc_status dpcd_set_lane_settings(
__func__,
offset,
lane0_set_address,
- dpcd_lane[0].tx_ffe.PRESET_VALUE);
+ link_training_setting->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
else if (dp_get_link_encoding_format(&link_training_setting->link_settings) ==
DP_8b_10b_ENCODING)
#endif
@@ -971,10 +942,10 @@ enum dc_status dpcd_set_lane_settings(
__func__,
offset,
lane0_set_address,
- dpcd_lane[0].bits.VOLTAGE_SWING_SET,
- dpcd_lane[0].bits.PRE_EMPHASIS_SET,
- dpcd_lane[0].bits.MAX_SWING_REACHED,
- dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
+ link_training_setting->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
+ link_training_setting->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
+ link_training_setting->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
+ link_training_setting->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
} else {
#if defined(CONFIG_DRM_AMD_DC_DCN)
@@ -983,17 +954,17 @@ enum dc_status dpcd_set_lane_settings(
DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X TX_FFE_PRESET_VALUE = %x\n",
__func__,
lane0_set_address,
- dpcd_lane[0].tx_ffe.PRESET_VALUE);
+ link_training_setting->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
else if (dp_get_link_encoding_format(&link_training_setting->link_settings) ==
DP_8b_10b_ENCODING)
#endif
DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
__func__,
lane0_set_address,
- dpcd_lane[0].bits.VOLTAGE_SWING_SET,
- dpcd_lane[0].bits.PRE_EMPHASIS_SET,
- dpcd_lane[0].bits.MAX_SWING_REACHED,
- dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
+ link_training_setting->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
+ link_training_setting->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
+ link_training_setting->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
+ link_training_setting->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
}
return status;
@@ -1006,7 +977,7 @@ bool dp_is_max_vs_reached(
for (lane = 0; lane <
(uint32_t)(lt_settings->link_settings.lane_count);
lane++) {
- if (lt_settings->hw_lane_settings[lane].VOLTAGE_SWING
+ if (lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET
== VOLTAGE_SWING_MAX_LEVEL)
return true;
}
@@ -1040,7 +1011,6 @@ static bool perform_post_lt_adj_req_sequence(
union lane_align_status_updated
dpcd_lane_status_updated;
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
- union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX] = { { {0} } };
dp_get_lane_status_and_lane_adjust(
link,
@@ -1065,9 +1035,9 @@ static bool perform_post_lt_adj_req_sequence(
for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
if (lt_settings->
- hw_lane_settings[lane].VOLTAGE_SWING !=
+ dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET !=
dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_LANE ||
- lt_settings->hw_lane_settings[lane].PRE_EMPHASIS !=
+ lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET !=
dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_LANE) {
req_drv_setting_changed = true;
@@ -1077,7 +1047,7 @@ static bool perform_post_lt_adj_req_sequence(
if (req_drv_setting_changed) {
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
- lt_settings->hw_lane_settings, dpcd_lane_settings);
+ lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
dc_link_dp_set_drive_settings(link,
lt_settings);
@@ -1164,10 +1134,8 @@ static enum link_training_result perform_channel_equalization_sequence(
union lane_align_status_updated dpcd_lane_status_updated = { {0} };
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
- union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX] = { { {0} } };
/* Note: also check that TPS4 is a supported feature*/
-
tr_pattern = lt_settings->pattern_for_eq;
#if defined(CONFIG_DRM_AMD_DC_DCN)
@@ -1233,7 +1201,7 @@ static enum link_training_result perform_channel_equalization_sequence(
/* 7. update VS/PE/PC2 in lt_settings*/
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
- lt_settings->hw_lane_settings, dpcd_lane_settings);
+ lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
}
return LINK_TRAINING_EQ_FAIL_EQ;
@@ -1263,7 +1231,6 @@ static enum link_training_result perform_clock_recovery_sequence(
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
union lane_align_status_updated dpcd_lane_status_updated;
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
- union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX] = { { {0} } };
retries_cr = 0;
retry_count = 0;
@@ -1344,12 +1311,12 @@ static enum link_training_result perform_clock_recovery_sequence(
/* Note: settings are the same for all lanes,
* so comparing first lane is sufficient*/
if ((dp_get_link_encoding_format(<_settings->link_settings) == DP_8b_10b_ENCODING) &&
- lt_settings->hw_lane_settings[0].VOLTAGE_SWING ==
+ lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET ==
dpcd_lane_adjust[0].bits.VOLTAGE_SWING_LANE)
retries_cr++;
#if defined(CONFIG_DRM_AMD_DC_DCN)
else if ((dp_get_link_encoding_format(<_settings->link_settings) == DP_128b_132b_ENCODING) &&
- lt_settings->hw_lane_settings[0].FFE_PRESET.settings.level ==
+ lt_settings->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE ==
dpcd_lane_adjust[0].tx_ffe.PRESET_VALUE)
retries_cr++;
#endif
@@ -1358,7 +1325,7 @@ static enum link_training_result perform_clock_recovery_sequence(
/* 8. update VS/PE/PC2 in lt_settings*/
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
- lt_settings->hw_lane_settings, dpcd_lane_settings);
+ lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
retry_count++;
}
@@ -1488,6 +1455,7 @@ static inline void decide_8b_10b_training_settings(
lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
lt_settings->enhanced_framing = 1;
lt_settings->should_set_fec_ready = true;
+ dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
}
#if defined(CONFIG_DRM_AMD_DC_DCN)
@@ -1513,6 +1481,8 @@ static inline void decide_128b_132b_training_settings(struct dc_link *link,
link->dpcd_caps.lttpr_caps.phy_repeater_cnt) + 1) * 20000;
lt_settings->lttpr_mode = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) ?
LTTPR_MODE_NON_TRANSPARENT : LTTPR_MODE_TRANSPARENT;
+ dp_hw_to_dpcd_lane_settings(lt_settings,
+ lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
}
#endif
@@ -1574,6 +1544,8 @@ static void override_training_settings(
*lt_settings->post_cursor2
: POST_CURSOR2_DISABLED;
}
+ dp_hw_to_dpcd_lane_settings(lt_settings,
+ lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
/* Initialize training timings */
if (overrides->cr_pattern_time != NULL)
@@ -1838,6 +1810,9 @@ void dc_link_dp_set_drive_settings(
/* program ASIC PHY settings*/
dp_set_hw_lane_settings(link, lt_settings, DPRX);
+ dp_hw_to_dpcd_lane_settings(lt_settings,
+ lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
+
/* Notify DP sink the PHY settings from source */
dpcd_set_lane_settings(link, lt_settings, DPRX);
}
@@ -1971,7 +1946,6 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
union lane_align_status_updated dpcd_lane_status_updated = { {0} };
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
- union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX] = { { {0} } };
enum link_training_result status = LINK_TRAINING_SUCCESS;
/* Transmit 128b/132b_TPS1 over Main-Link and Set TRAINING_PATTERN_SET to 01h */
@@ -1982,7 +1956,7 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
- lt_settings->hw_lane_settings, dpcd_lane_settings);
+ lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval);
dp_set_hw_lane_settings(link, lt_settings, DPRX);
dpcd_set_lane_settings(link, lt_settings, DPRX);
@@ -1999,7 +1973,7 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
- lt_settings->hw_lane_settings, dpcd_lane_settings);
+ lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval);
if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count,
dpcd_lane_status)) {
@@ -2113,7 +2087,7 @@ static enum link_training_result dp_perform_8b_10b_link_training(
}
for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
- lt_settings->hw_lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0;
+ lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET = VOLTAGE_SWING_LEVEL0;
}
if (status == LINK_TRAINING_SUCCESS) {
@@ -3461,15 +3435,13 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
#endif
unsigned int test_pattern_size = 0;
enum dp_test_pattern test_pattern;
- struct dc_link_training_settings link_settings;
union lane_adjust dpcd_lane_adjust;
unsigned int lane;
struct link_training_settings link_training_settings;
- int i = 0;
dpcd_test_pattern.raw = 0;
memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
- memset(&link_settings, 0, sizeof(link_settings));
+ memset(&link_training_settings, 0, sizeof(link_training_settings));
/* get phy test pattern and pattern parameters from DP receiver */
core_link_read_dpcd(
@@ -3590,47 +3562,37 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
#endif
/* prepare link training settings */
- link_settings.link = link->cur_link_settings;
+ link_training_settings.link_settings = link->cur_link_settings;
for (lane = 0; lane <
(unsigned int)(link->cur_link_settings.lane_count);
lane++) {
dpcd_lane_adjust.raw =
get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
-#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dp_get_link_encoding_format(&link->cur_link_settings) ==
- DP_128b_132b_ENCODING) {
- link_settings.lane_settings[lane].FFE_PRESET.raw =
- dpcd_lane_adjust.tx_ffe.PRESET_VALUE;
- } else if (dp_get_link_encoding_format(&link->cur_link_settings) ==
DP_8b_10b_ENCODING) {
- link_settings.lane_settings[lane].VOLTAGE_SWING =
+ link_training_settings.hw_lane_settings[lane].VOLTAGE_SWING =
(enum dc_voltage_swing)
(dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
- link_settings.lane_settings[lane].PRE_EMPHASIS =
+ link_training_settings.hw_lane_settings[lane].PRE_EMPHASIS =
(enum dc_pre_emphasis)
(dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
- link_settings.lane_settings[lane].POST_CURSOR2 =
+ link_training_settings.hw_lane_settings[lane].POST_CURSOR2 =
(enum dc_post_cursor2)
((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
}
-#else
- link_settings.lane_settings[lane].VOLTAGE_SWING =
- (enum dc_voltage_swing)
- (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
- link_settings.lane_settings[lane].PRE_EMPHASIS =
- (enum dc_pre_emphasis)
- (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
- link_settings.lane_settings[lane].POST_CURSOR2 =
- (enum dc_post_cursor2)
- ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+ else if (dp_get_link_encoding_format(&link->cur_link_settings) ==
+ DP_128b_132b_ENCODING) {
+ link_training_settings.hw_lane_settings[lane].FFE_PRESET.raw =
+ dpcd_lane_adjust.tx_ffe.PRESET_VALUE;
+ }
#endif
}
- for (i = 0; i < 4; i++)
- link_training_settings.hw_lane_settings[i] =
- link_settings.lane_settings[i];
- link_training_settings.link_settings = link_settings.link;
+ dp_hw_to_dpcd_lane_settings(&link_training_settings,
+ link_training_settings.hw_lane_settings,
+ link_training_settings.dpcd_lane_settings);
link_training_settings.allow_invalid_msa_timing_param = false;
/*Usage: Measure DP physical lane signal
* by DP SI test equipment automatically.
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index a5e798b5da79..515125fdd7b3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -174,11 +174,6 @@ struct dc_lane_settings {
#endif
};
-struct dc_link_training_settings {
- struct dc_link_settings link;
- struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
-};
-
struct dc_link_training_overrides {
enum dc_voltage_swing *voltage_swing;
enum dc_pre_emphasis *pre_emphasis;
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 007274e73347..3fc868b19f2f 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -91,12 +91,14 @@ enum lttpr_mode {
struct link_training_settings {
struct dc_link_settings link_settings;
+ /* TODO: turn lane settings below into mandatory fields
+ * as initial lane configuration
+ */
enum dc_voltage_swing *voltage_swing;
enum dc_pre_emphasis *pre_emphasis;
enum dc_post_cursor2 *post_cursor2;
bool should_set_fec_ready;
#if defined(CONFIG_DRM_AMD_DC_DCN)
- /* TODO - factor lane_settings out because it changes during LT */
union dc_dp_ffe_preset *ffe_preset;
#endif
@@ -118,11 +120,14 @@ struct link_training_settings {
enum lttpr_mode lttpr_mode;
- /* TODO: Move hw_lane_settings along with lane adjust,
- * lane align, offset and all other training states
- * into a new structure called link training states,
- * so link_training_settings becomes a constant input
- * pre-decided prior to link training.
+ /*****************************************************************
+ * training states - parameters that can change in link training
+ *****************************************************************/
+ /* TODO: Move hw_lane_settings and dpcd_lane_settings
+ * along with lane adjust, lane align, offset and all
+ * other training states into a new structure called
+ * training states, so link_training_settings becomes
+ * a constant input pre-decided prior to link training.
*
* The goal is to strictly decouple link training settings
* decision making process from link training states to
@@ -130,7 +135,7 @@ struct link_training_settings {
* decision on the fly.
*/
struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX];
-
+ union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX];
};
/*TODO: Move this enum test harness*/
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 11/24] drm/amd/display: add two lane settings training options
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (9 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 10/24] drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 12/24] drm/amd/display: Fix for link encoder access for MST Anson Jacob
` (13 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Wenjing Liu,
Jun Lei
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
option 1: disallow different lanes to have different lane settings
option 2: dpcd lane settings will always use the same hw lane settings
even if it doesn't match requested lane adjust
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 18 ++++++++++++------
.../amd/display/include/link_service_types.h | 6 +++++-
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index f13bf8ca93aa..f55dac1c7ea1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -733,12 +733,16 @@ void dp_decide_lane_settings(
#endif
}
- /*
- * We find the maximum of the requested settings across all lanes
- * and set this maximum for all lanes
- */
- maximize_lane_settings(hw_lane_settings);
dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings);
+
+ if (lt_settings->disallow_per_lane_settings) {
+ /* we find the maximum of the requested settings across all lanes*/
+ /* and set this maximum for all lanes*/
+ maximize_lane_settings(hw_lane_settings);
+ if (lt_settings->always_match_dpcd_with_hw_lane_settings)
+ dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings);
+ }
+
}
static uint8_t get_nibble_at_index(const uint8_t *buf,
@@ -1455,6 +1459,8 @@ static inline void decide_8b_10b_training_settings(
lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
lt_settings->enhanced_framing = 1;
lt_settings->should_set_fec_ready = true;
+ lt_settings->disallow_per_lane_settings = true;
+ lt_settings->always_match_dpcd_with_hw_lane_settings = true;
dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
}
@@ -1481,6 +1487,7 @@ static inline void decide_128b_132b_training_settings(struct dc_link *link,
link->dpcd_caps.lttpr_caps.phy_repeater_cnt) + 1) * 20000;
lt_settings->lttpr_mode = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) ?
LTTPR_MODE_NON_TRANSPARENT : LTTPR_MODE_TRANSPARENT;
+ lt_settings->disallow_per_lane_settings = true;
dp_hw_to_dpcd_lane_settings(lt_settings,
lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
}
@@ -3593,7 +3600,6 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
dp_hw_to_dpcd_lane_settings(&link_training_settings,
link_training_settings.hw_lane_settings,
link_training_settings.dpcd_lane_settings);
- link_training_settings.allow_invalid_msa_timing_param = false;
/*Usage: Measure DP physical lane signal
* by DP SI test equipment automatically.
* PHY test pattern request is generated by equipment via HPD interrupt.
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 3fc868b19f2f..e94bcdb3e134 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -116,9 +116,13 @@ struct link_training_settings {
#endif
bool enhanced_framing;
- bool allow_invalid_msa_timing_param;
enum lttpr_mode lttpr_mode;
+ /* disallow different lanes to have different lane settings */
+ bool disallow_per_lane_settings;
+ /* dpcd lane settings will always use the same hw lane settings
+ * even if it doesn't match requested lane adjust */
+ bool always_match_dpcd_with_hw_lane_settings;
/*****************************************************************
* training states - parameters that can change in link training
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 12/24] drm/amd/display: Fix for link encoder access for MST.
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (10 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 11/24] drm/amd/display: add two lane settings training options Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 13/24] drm/amd/display: Fix MST link encoder availability check Anson Jacob
` (12 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu,
Meenakshikumar Somasundaram, Jun Lei
From: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
[Why]
Link encoder in the link could be null for certain links.
[How]
If link encoder in the link is null then get the link encoder
from the stream.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index cab7993b4cc5..f3a1219c0bb9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3305,7 +3305,7 @@ enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
{
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
- struct link_encoder *link_encoder = link->link_enc;
+ struct link_encoder *link_encoder = NULL;
struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
struct dp_mst_stream_allocation_table proposed_table = {0};
struct fixed31_32 avg_time_slots_per_mtp;
@@ -3315,6 +3315,13 @@ enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
enum act_return_status ret;
DC_LOGGER_INIT(link->ctx->logger);
+ /* Link encoder may have been dynamically assigned to non-physical display endpoint. */
+ if (link->ep_type == DISPLAY_ENDPOINT_PHY)
+ link_encoder = link->link_enc;
+ else if (link->dc->res_pool->funcs->link_encs_assign)
+ link_encoder = link_enc_cfg_get_link_enc_used_by_stream(pipe_ctx->stream->ctx->dc, stream);
+ ASSERT(link_encoder);
+
/* enable_link_dp_mst already check link->enabled_stream_count
* and stream is in link->stream[]. This is called during set mode,
* stream_enc is available.
@@ -3392,7 +3399,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
{
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
- struct link_encoder *link_encoder = link->link_enc;
+ struct link_encoder *link_encoder = NULL;
struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
struct dp_mst_stream_allocation_table proposed_table = {0};
struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
@@ -3400,6 +3407,13 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
bool mst_mode = (link->type == dc_connection_mst_branch);
DC_LOGGER_INIT(link->ctx->logger);
+ /* Link encoder may have been dynamically assigned to non-physical display endpoint. */
+ if (link->ep_type == DISPLAY_ENDPOINT_PHY)
+ link_encoder = link->link_enc;
+ else if (link->dc->res_pool->funcs->link_encs_assign)
+ link_encoder = link_enc_cfg_get_link_enc_used_by_stream(pipe_ctx->stream->ctx->dc, stream);
+ ASSERT(link_encoder);
+
/* deallocate_mst_payload is called before disable link. When mode or
* disable/enable monitor, new stream is created which is not in link
* stream[] yet. For this, payload is not allocated yet, so de-alloc
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 13/24] drm/amd/display: Fix MST link encoder availability check.
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (11 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 12/24] drm/amd/display: Fix for link encoder access for MST Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 14/24] drm/amd/display: Add PPS immediate update flag for DCN2 Anson Jacob
` (11 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Jimmy Kizito,
Jun Lei
From: Jimmy Kizito <Jimmy.Kizito@amd.com>
[Why]
MST streams share the same link and should share the same encoder.
The current availability check may erroneously determine that an
encoder is unavailable for MST streams.
[How]
When checking for link encoder availability, check if an encoder
in use shares a link with the stream for which the availability
check is being conducted. If the link is shared, then the link
encoder should be shared too and will be deemed available.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
---
.../drm/amd/display/dc/core/dc_link_enc_cfg.c | 23 +++++++++++++++----
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index 4dce25c39b75..1cab4bf06abe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -1,5 +1,4 @@
-/*
- * Copyright 2021 Advanced Micro Devices, Inc.
+/* Copyright 2021 Advanced Micro Devices, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -177,13 +176,27 @@ static enum engine_id find_first_avail_link_enc(
return eng_id;
}
-static bool is_avail_link_enc(struct dc_state *state, enum engine_id eng_id)
+/* Check for availability of link encoder eng_id. */
+static bool is_avail_link_enc(struct dc_state *state, enum engine_id eng_id, struct dc_stream_state *stream)
{
bool is_avail = false;
int eng_idx = eng_id - ENGINE_ID_DIGA;
- if (eng_id != ENGINE_ID_UNKNOWN && state->res_ctx.link_enc_cfg_ctx.link_enc_avail[eng_idx] != ENGINE_ID_UNKNOWN)
+ /* An encoder is available if it is still in the availability pool. */
+ if (eng_id != ENGINE_ID_UNKNOWN && state->res_ctx.link_enc_cfg_ctx.link_enc_avail[eng_idx] != ENGINE_ID_UNKNOWN) {
is_avail = true;
+ } else {
+ struct dc_stream_state *stream_assigned = NULL;
+
+ /* MST streams share the same link and should share the same encoder.
+ * If a stream that has already been assigned a link encoder uses as the
+ * same link as the stream checking for availability, it is an MST stream
+ * and should use the same link encoder.
+ */
+ stream_assigned = get_stream_using_link_enc(state, eng_id);
+ if (stream_assigned && stream != stream_assigned && stream->link == stream_assigned->link)
+ is_avail = true;
+ }
return is_avail;
}
@@ -296,7 +309,7 @@ void link_enc_cfg_link_encs_assign(
if (stream == prev_stream && stream->link == prev_stream->link &&
prev_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[j].valid) {
eng_id = prev_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[j].eng_id;
- if (is_avail_link_enc(state, eng_id))
+ if (is_avail_link_enc(state, eng_id, stream))
add_link_enc_assignment(state, stream, eng_id);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 14/24] drm/amd/display: Add PPS immediate update flag for DCN2
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (12 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 13/24] drm/amd/display: Fix MST link encoder availability check Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 15/24] drm/amd/display: Add an extra check for dcn10 OPTC data format Anson Jacob
` (10 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Ilya,
Wenjing Liu
From: Ilya <Ilya.Bakoulin@amd.com>
[Why]
This change is needed for DCN2 to make use of the immediate_update
flag. With this flag, update to PPS will be immediate, rather than
always taking place on dig_update signal.
[How]
Set AFMT_GENERIC7_FRAME/IMMEDIATE_UPDATE bits depending on flag
value.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Ilya <Ilya.Bakoulin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 5 +++++
.../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 9 ++++++---
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index f6e747f25ebe..c90b8516dcc1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -467,6 +467,11 @@ void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
(h_blank_start - 200 - 1) / optc1->opp_count,
MASTER_UPDATE_LOCK_DB_Y,
v_blank_start - 1);
+
+ REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
+ MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
+ MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
+ OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
}
void optc2_lock_doublebuffer_disable(struct timing_generator *optc)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index 11c50b508754..aab25ca8343a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -211,7 +211,8 @@ static void enc2_stream_encoder_stop_hdmi_info_packets(
/* Update GSP7 SDP 128 byte long */
static void enc2_update_gsp7_128_info_packet(
struct dcn10_stream_encoder *enc1,
- const struct dc_info_packet_128 *info_packet)
+ const struct dc_info_packet_128 *info_packet,
+ bool immediate_update)
{
uint32_t i;
@@ -266,7 +267,9 @@ static void enc2_update_gsp7_128_info_packet(
REG_WRITE(AFMT_GENERIC_7, *content++);
}
- REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, 1);
+ REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC7_FRAME_UPDATE, !immediate_update,
+ AFMT_GENERIC7_IMMEDIATE_UPDATE, immediate_update);
}
/* Set DSC-related configuration.
@@ -309,7 +312,7 @@ static void enc2_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
pps_sdp.hb2 = 127;
pps_sdp.hb3 = 0;
memcpy(&pps_sdp.sb[0], dsc_packed_pps, sizeof(pps_sdp.sb));
- enc2_update_gsp7_128_info_packet(enc1, &pps_sdp);
+ enc2_update_gsp7_128_info_packet(enc1, &pps_sdp, immediate_update);
/* Enable Generic Stream Packet 7 (GSP) transmission */
//REG_UPDATE(DP_SEC_CNTL,
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 15/24] drm/amd/display: Add an extra check for dcn10 OPTC data format
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (13 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 14/24] drm/amd/display: Add PPS immediate update flag for DCN2 Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 16/24] drm/amd/display: [FW Promotion] Release 0.0.86 Anson Jacob
` (9 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Oliver Logush,
Charlene Liu, Jun Lei
From: Oliver Logush <oliver.logush@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Oliver Logush <oliver.logush@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 6 ------
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 1 -
3 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
index f0e0d07b0311..1ca4907b144d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
@@ -62,12 +62,6 @@
#define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
#define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
-#define CURSOR1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
-#define CURSOR1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
-#define CURSOR2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
-#define CURSOR2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
-#define CURSOR3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
-#define CURSOR3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
#define IPP_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 37848f4577b1..3d2a2848857a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -304,7 +304,7 @@ void optc1_program_timing(
if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
h_div = H_TIMING_DIV_BY2;
- if (REG(OPTC_DATA_FORMAT_CONTROL)) {
+ if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) {
uint32_t data_fmt = 0;
if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
index ec28cb9c3a8e..9ccbb2b519b7 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
@@ -171,7 +171,6 @@ struct dwbc {
bool dwb_is_efc_transition;
bool dwb_is_drc;
int wb_src_plane_inst;/*hubp, mpcc, inst*/
- bool update_privacymask;
uint32_t mask_id;
int otg_inst;
bool mvc_cfg;
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 16/24] drm/amd/display: [FW Promotion] Release 0.0.86
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (14 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 15/24] drm/amd/display: Add an extra check for dcn10 OPTC data format Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 17/24] drm/amd/display: 3.2.155 Anson Jacob
` (8 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 4a41549109dd..f5974562aa23 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0xeb0940cc
+#define DMUB_FW_VERSION_GIT_HASH 0x42c0e74b
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 85
+#define DMUB_FW_VERSION_REVISION 86
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 17/24] drm/amd/display: 3.2.155
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (15 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 16/24] drm/amd/display: [FW Promotion] Release 0.0.86 Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 18/24] drm/amd/display: Replace referral of dal with dc Anson Jacob
` (7 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Aric Cyr
From: Aric Cyr <aric.cyr@amd.com>
This version brings along following fixes:
- Fixes to backlight, LUT, PPS, MST
- Use correct vpg for 128b/132b encoding
- Improved logging for VCP
- Replace referral of dal with dc
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index a46c663ed8c5..8cc9626fc111 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -45,7 +45,7 @@
/* forward declaration */
struct aux_payload;
-#define DC_VER "3.2.154"
+#define DC_VER "3.2.155"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 18/24] drm/amd/display: Replace referral of dal with dc
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (16 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 17/24] drm/amd/display: 3.2.155 Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 19/24] drm/amd/display: Defer LUT memory powerdown until LUT bypass latches Anson Jacob
` (6 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Qingqing Zhuo
From: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
[Why]
DC should be used in place of DAL in
upstream.
[How]
Replace dal with dc in function names.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c | 2 +-
drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.h | 2 +-
drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c | 2 +-
drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 315466f5aade..2108bff49d4e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -243,7 +243,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
pp_smu = &dc->res_pool->pp_smu->nv_funcs;
for (irq_src = DC_IRQ_SOURCE_HPD1; irq_src <= DC_IRQ_SOURCE_HPD6; irq_src++) {
- hpd_state = dal_get_hpd_state_dcn20(dc->res_pool->irqs, irq_src);
+ hpd_state = dc_get_hpd_state_dcn20(dc->res_pool->irqs, irq_src);
if (hpd_state)
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 3fabf32a0558..ac2d4c4f04e4 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -152,7 +152,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
display_count = rn_get_active_display_cnt_wa(dc, context);
for (irq_src = DC_IRQ_SOURCE_HPD1; irq_src <= DC_IRQ_SOURCE_HPD5; irq_src++) {
- hpd_state = dal_get_hpd_state_dcn21(dc->res_pool->irqs, irq_src);
+ hpd_state = dc_get_hpd_state_dcn21(dc->res_pool->irqs, irq_src);
if (hpd_state)
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
index 49d87fe5c167..9ccafe007b23 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
@@ -132,7 +132,7 @@ enum dc_irq_source to_dal_irq_source_dcn20(
}
}
-uint32_t dal_get_hpd_state_dcn20(struct irq_service *irq_service, enum dc_irq_source source)
+uint32_t dc_get_hpd_state_dcn20(struct irq_service *irq_service, enum dc_irq_source source)
{
const struct irq_source_info *info;
uint32_t addr;
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.h b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.h
index f60a203e7188..4d69ab24ca25 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.h
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.h
@@ -31,6 +31,6 @@
struct irq_service *dal_irq_service_dcn20_create(
struct irq_service_init_data *init_data);
-uint32_t dal_get_hpd_state_dcn20(struct irq_service *irq_service, enum dc_irq_source source);
+uint32_t dc_get_hpd_state_dcn20(struct irq_service *irq_service, enum dc_irq_source source);
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
index 685528734575..78940cb20e10 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
@@ -135,7 +135,7 @@ enum dc_irq_source to_dal_irq_source_dcn21(
return DC_IRQ_SOURCE_INVALID;
}
-uint32_t dal_get_hpd_state_dcn21(struct irq_service *irq_service, enum dc_irq_source source)
+uint32_t dc_get_hpd_state_dcn21(struct irq_service *irq_service, enum dc_irq_source source)
{
const struct irq_source_info *info;
uint32_t addr;
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h
index 3df2ceeb2b70..616470e32380 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h
@@ -31,6 +31,6 @@
struct irq_service *dal_irq_service_dcn21_create(
struct irq_service_init_data *init_data);
-uint32_t dal_get_hpd_state_dcn21(struct irq_service *irq_service, enum dc_irq_source source);
+uint32_t dc_get_hpd_state_dcn21(struct irq_service *irq_service, enum dc_irq_source source);
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 19/24] drm/amd/display: Defer LUT memory powerdown until LUT bypass latches
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (17 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 18/24] drm/amd/display: Replace referral of dal with dc Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 20/24] drm/amd/display: initialize backlight_ramping_override to false Anson Jacob
` (5 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu,
Michael Strauss, Eric Yang
From: Michael Strauss <michael.strauss@amd.com>
[WHY]
Blnd, 3dlut, and shaper LUT select registers are double buffered, however
their accompanying LUT memory shutdown registers are not. As a result,
shutting down LUT memory immediately after setting a block to bypass causes
corruption as bypass only happens at next Vupdate.
[HOW]
Re-enable mem low power for CM block
Force optimization on next flip and disable LUT memory during optimization
sequence if LUT select field is then set to bypass
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 19 ++++++
.../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 59 +++++++++++++++++--
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 12 ++++
4 files changed, 85 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 644005846433..0f0440408a16 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1793,6 +1793,23 @@ static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
return false;
}
+/* Perform updates here which need to be deferred until next vupdate
+ *
+ * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
+ * but forcing lut memory to shutdown state is immediate. This causes
+ * single frame corruption as lut gets disabled mid-frame unless shutdown
+ * is deferred until after entering bypass.
+ */
+static void process_deferred_updates(struct dc *dc)
+{
+ int i;
+
+ if (dc->debug.enable_mem_low_power.bits.cm)
+ for (i = 0; i < dc->dcn_ip->max_num_dpp; i++)
+ if (dc->res_pool->dpps[i]->funcs->dpp_deferred_update)
+ dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
+}
+
void dc_post_update_surfaces_to_stream(struct dc *dc)
{
int i;
@@ -1818,6 +1835,8 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
}
+ process_deferred_updates(dc);
+
dc->hwss.optimize_bandwidth(dc, context);
dc->optimized_required = false;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
index 23a52d47e61c..ef5f6da5248a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
@@ -488,6 +488,40 @@ void dpp3_cnv_set_bias_scale(
REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue);
}
+void dpp3_deferred_update(
+ struct dpp *dpp_base)
+{
+ int bypass_state;
+ struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
+
+ if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) {
+ REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &bypass_state);
+ if (bypass_state == 0) { // only program if bypass was latched
+ REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 3);
+ } else
+ ASSERT(0); // LUT select was updated again before vupdate
+ dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false;
+ }
+
+ if (dpp_base->deferred_reg_writes.bits.disable_3dlut) {
+ REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &bypass_state);
+ if (bypass_state == 0) { // only program if bypass was latched
+ REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 3);
+ } else
+ ASSERT(0); // LUT select was updated again before vupdate
+ dpp_base->deferred_reg_writes.bits.disable_3dlut = false;
+ }
+
+ if (dpp_base->deferred_reg_writes.bits.disable_shaper) {
+ REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &bypass_state);
+ if (bypass_state == 0) { // only program if bypass was latched
+ REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 3);
+ } else
+ ASSERT(0); // LUT select was updated again before vupdate
+ dpp_base->deferred_reg_writes.bits.disable_shaper = false;
+ }
+}
+
static void dpp3_power_on_blnd_lut(
struct dpp *dpp_base,
bool power_on)
@@ -495,9 +529,13 @@ static void dpp3_power_on_blnd_lut(
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
- REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, power_on ? 0 : 3);
- if (power_on)
+ if (power_on) {
+ REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0);
REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5);
+ } else {
+ dpp_base->ctx->dc->optimized_required = true;
+ dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
+ }
} else {
REG_SET(CM_MEM_PWR_CTRL, 0,
BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);
@@ -511,9 +549,13 @@ static void dpp3_power_on_hdr3dlut(
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
- REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, power_on ? 0 : 3);
- if (power_on)
+ if (power_on) {
+ REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0);
REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5);
+ } else {
+ dpp_base->ctx->dc->optimized_required = true;
+ dpp_base->deferred_reg_writes.bits.disable_3dlut = true;
+ }
}
}
@@ -524,9 +566,13 @@ static void dpp3_power_on_shaper(
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
- REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, power_on ? 0 : 3);
- if (power_on)
+ if (power_on) {
+ REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0);
REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5);
+ } else {
+ dpp_base->ctx->dc->optimized_required = true;
+ dpp_base->deferred_reg_writes.bits.disable_shaper = true;
+ }
}
}
@@ -1400,6 +1446,7 @@ static struct dpp_funcs dcn30_dpp_funcs = {
.dpp_program_blnd_lut = dpp3_program_blnd_lut,
.dpp_program_shaper_lut = dpp3_program_shaper,
.dpp_program_3dlut = dpp3_program_3dlut,
+ .dpp_deferred_update = dpp3_deferred_update,
.dpp_program_bias_and_scale = NULL,
.dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
.set_cursor_attributes = dpp3_set_cursor_attributes,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 6f0c788d1904..613d34bde7dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1013,7 +1013,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.i2c = true,
.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
.dscl = true,
- .cm = false, // visible flicker on OLED eDPs
+ .cm = true,
.mpc = true,
.optc = true,
.vpg = true,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 00fc81431b43..9f12792b7e59 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -29,6 +29,15 @@
#include "transform.h"
+union defer_reg_writes {
+ struct {
+ bool disable_blnd_lut:1;
+ bool disable_3dlut:1;
+ bool disable_shaper:1;
+ } bits;
+ uint32_t raw;
+};
+
struct dpp {
const struct dpp_funcs *funcs;
struct dc_context *ctx;
@@ -43,6 +52,7 @@ struct dpp {
struct pwl_params regamma_params;
struct pwl_params degamma_params;
struct dpp_cursor_attributes cur_attr;
+ union defer_reg_writes deferred_reg_writes;
struct pwl_params shaper_params;
bool cm_bypass_mode;
@@ -245,6 +255,8 @@ struct dpp_funcs {
bool dppclk_div,
bool enable);
+ void (*dpp_deferred_update)(
+ struct dpp *dpp);
bool (*dpp_program_blnd_lut)(
struct dpp *dpp,
const struct pwl_params *params);
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 20/24] drm/amd/display: initialize backlight_ramping_override to false
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (18 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 19/24] drm/amd/display: Defer LUT memory powerdown until LUT bypass latches Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 21/24] drm/amd/display: make verified link cap not exceeding max link cap Anson Jacob
` (4 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Josip Pavic,
Roman Li
From: Josip Pavic <Josip.Pavic@amd.com>
[Why]
Stack variable params.backlight_ramping_override is uninitialized, so it
contains junk data
[How]
Initialize the variable to false
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 07adac1a8c42..18899a391597 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1961,6 +1961,7 @@ static int dm_late_init(void *handle)
linear_lut[i] = 0xFFFF * i / 15;
params.set = 0;
+ params.backlight_ramping_override = false;
params.backlight_ramping_start = 0xCCCC;
params.backlight_ramping_reduction = 0xCCCCCCCC;
params.backlight_lut_array_size = 16;
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 21/24] drm/amd/display: make verified link cap not exceeding max link cap
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (19 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 20/24] drm/amd/display: initialize backlight_ramping_override to false Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 22/24] drm/amd/display: Handle Y carry-over in VCP X.Y calculation Anson Jacob
` (3 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Wenjing Liu,
Jimmy Kizito
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
There is a chance verified link cap can be greater than max link cap.
This causes software hang because we cannot power up PHY with link rate
that cannot handle.
The change is to guard verfieid link cap from becoming larger than max link cap
our PHy can support.
Reviewed-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 43 ++++++++++++-------
1 file changed, 28 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index f55dac1c7ea1..ccfb0aceea5b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2710,14 +2710,25 @@ bool dp_verify_link_cap(
enum link_training_result status;
union hpd_irq_data irq_data;
+ /* link training starts with the maximum common settings
+ * supported by both sink and ASIC.
+ */
+ max_link_cap = get_max_link_cap(link);
+ initial_link_settings = get_common_supported_link_settings(
+ *known_limit_link_setting,
+ max_link_cap);
+
/* Accept reported capabilities if link supports flexible encoder mapping or encoder already in use. */
if (link->dc->debug.skip_detection_link_training ||
link->is_dig_mapping_flexible) {
+ /* TODO - should we check link encoder's max link caps here?
+ * How do we know which link encoder to check from?
+ */
link->verified_link_cap = *known_limit_link_setting;
return true;
} else if (link->link_enc && link->dc->res_pool->funcs->link_encs_assign &&
!link_enc_cfg_is_link_enc_avail(link->ctx->dc, link->link_enc->preferred_engine)) {
- link->verified_link_cap = *known_limit_link_setting;
+ link->verified_link_cap = initial_link_settings;
return true;
}
@@ -2725,8 +2736,6 @@ bool dp_verify_link_cap(
success = false;
skip_link_training = false;
- max_link_cap = get_max_link_cap(link);
-
/* Grant extended timeout request */
if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
@@ -2748,12 +2757,6 @@ bool dp_verify_link_cap(
dp_cs_id = get_clock_source_id(link);
- /* link training starts with the maximum common settings
- * supported by both sink and ASIC.
- */
- initial_link_settings = get_common_supported_link_settings(
- *known_limit_link_setting,
- max_link_cap);
cur_link_setting = initial_link_settings;
/* Temporary Renoir-specific workaround for SWDEV-215184;
@@ -2847,7 +2850,7 @@ bool dp_verify_link_cap_with_retries(
link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
break;
} else if (dp_verify_link_cap(link,
- &link->reported_link_cap,
+ known_limit_link_setting,
&fail_count) && fail_count == 0) {
success = true;
break;
@@ -2862,11 +2865,21 @@ bool dp_verify_mst_link_cap(
{
struct dc_link_settings max_link_cap = {0};
- max_link_cap = get_max_link_cap(link);
- link->verified_link_cap = get_common_supported_link_settings(
- link->reported_link_cap,
- max_link_cap);
-
+ if (dp_get_link_encoding_format(&link->reported_link_cap) ==
+ DP_8b_10b_ENCODING) {
+ max_link_cap = get_max_link_cap(link);
+ link->verified_link_cap = get_common_supported_link_settings(
+ link->reported_link_cap,
+ max_link_cap);
+ }
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+ else if (dp_get_link_encoding_format(&link->reported_link_cap) ==
+ DP_128b_132b_ENCODING) {
+ dp_verify_link_cap_with_retries(link,
+ &link->reported_link_cap,
+ LINK_TRAINING_MAX_VERIFY_RETRY);
+ }
+#endif
return true;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 22/24] drm/amd/display: Handle Y carry-over in VCP X.Y calculation
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (20 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 21/24] drm/amd/display: make verified link cap not exceeding max link cap Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 23/24] drm/amd/display: Update VCP X.Y logging to improve usefulness Anson Jacob
` (2 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, George Shen,
Wenjing Liu
From: George Shen <george.shen@amd.com>
[Why/How]
Theoretically rare corner case where ceil(Y) results in rounding
up to an integer. If this happens, the 1 should be carried over to
the X value.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 687c3c6881a9..b0c08ee6bc2c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -647,6 +647,12 @@ void enc1_stream_encoder_set_throttled_vcp_size(
x),
26));
+ // If y rounds up to integer, carry it over to x.
+ if (y >> 26) {
+ x += 1;
+ y = 0;
+ }
+
REG_SET_2(DP_MSE_RATE_CNTL, 0,
DP_MSE_RATE_X, x,
DP_MSE_RATE_Y, y);
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 23/24] drm/amd/display: Update VCP X.Y logging to improve usefulness
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (21 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 22/24] drm/amd/display: Handle Y carry-over in VCP X.Y calculation Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-24 19:09 ` [PATCH 24/24] drm/amd/display: Pass PCI deviceid into DC Anson Jacob
2021-09-27 13:21 ` [PATCH 00/24] DC Patches Sep 24, 2021 Wheeler, Daniel
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, George Shen,
Wenjing Liu
From: George Shen <george.shen@amd.com>
[Why]
Recently debugging efforts have involved setting/checking the
X.Y value used during payload allocation. Current output for
Y was calculated with incorrect bitshift. Y value is also not
human readable.
[How]
Refactor logging into separate function. Fix Y calculation error
and format output to be human readable.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 49 ++++++++++---------
1 file changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index f3a1219c0bb9..02c7a18c095f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3197,6 +3197,29 @@ static void update_mst_stream_alloc_table(
work_table[i];
}
#if defined(CONFIG_DRM_AMD_DC_DCN)
+static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
+{
+ const uint32_t VCP_Y_PRECISION = 1000;
+ uint64_t vcp_x, vcp_y;
+
+ // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
+ avg_time_slots_per_mtp = dc_fixpt_add(
+ avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));
+
+ vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
+ vcp_y = dc_fixpt_floor(
+ dc_fixpt_mul_int(
+ dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
+ VCP_Y_PRECISION));
+
+ if (link->type == dc_connection_mst_branch)
+ DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
+ "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
+ else
+ DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
+ "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
+}
+
/*
* Payload allocation/deallocation for SST introduced in DP2.0
*/
@@ -3214,18 +3237,7 @@ enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx, bool alloca
if (!allocate) {
avg_time_slots_per_mtp = dc_fixpt_from_int(0);
- DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream"
- "X: %d "
- "Y: %d",
- dc_fixpt_floor(
- avg_time_slots_per_mtp),
- dc_fixpt_ceil(
- dc_fixpt_shl(
- dc_fixpt_sub_int(
- avg_time_slots_per_mtp,
- dc_fixpt_floor(
- avg_time_slots_per_mtp)),
- 26)));
+ dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
hpo_dp_link_encoder,
@@ -3272,18 +3284,7 @@ enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx, bool alloca
if (allocate) {
avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
- DC_LOG_DP2("SST Update Payload: "
- "slot.X: %d "
- "slot.Y: %d",
- dc_fixpt_floor(
- avg_time_slots_per_mtp),
- dc_fixpt_ceil(
- dc_fixpt_shl(
- dc_fixpt_sub_int(
- avg_time_slots_per_mtp,
- dc_fixpt_floor(
- avg_time_slots_per_mtp)),
- 26)));
+ dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
hpo_dp_link_encoder,
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 24/24] drm/amd/display: Pass PCI deviceid into DC
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (22 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 23/24] drm/amd/display: Update VCP X.Y logging to improve usefulness Anson Jacob
@ 2021-09-24 19:09 ` Anson Jacob
2021-09-27 13:21 ` [PATCH 00/24] DC Patches Sep 24, 2021 Wheeler, Daniel
24 siblings, 0 replies; 26+ messages in thread
From: Anson Jacob @ 2021-09-24 19:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Charlene Liu,
Zhan Liu
From: Charlene Liu <Charlene.Liu@amd.com>
[why]
pci deviceid not passed to dal dc, without proper break,
dcn2.x falls into dcn3.x code path
[how]
pass in pci deviceid, and break once dal_version initialized.
Reviewed-by: Zhan Liu <Zhan.Liu@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 18899a391597..e676d0a56d50 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1319,6 +1319,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
init_data.asic_id.pci_revision_id = adev->pdev->revision;
init_data.asic_id.hw_internal_rev = adev->external_rev_id;
+ init_data.asic_id.chip_id = adev->pdev->device;
init_data.asic_id.vram_width = adev->gmc.vram_width;
/* TODO: initialize init_data.asic_id.vram_type here!!!! */
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* RE: [PATCH 00/24] DC Patches Sep 24, 2021
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
` (23 preceding siblings ...)
2021-09-24 19:09 ` [PATCH 24/24] drm/amd/display: Pass PCI deviceid into DC Anson Jacob
@ 2021-09-27 13:21 ` Wheeler, Daniel
24 siblings, 0 replies; 26+ messages in thread
From: Wheeler, Daniel @ 2021-09-27 13:21 UTC (permalink / raw)
To: Jacob, Anson, amd-gfx
Cc: Wentland, Harry, Li, Sun peng (Leo),
Lakha, Bhawanpreet, Siqueira, Rodrigo, Pillai, Aurabindo, Zhuo,
Qingqing, Lipski, Mikita, Li, Roman, Jacob, Anson, Lin, Wayne,
Wang, Chao-kai (Stylon),
Chiu, Solomon
[Public]
Hi all,
This week this patchset was tested on the following systems:
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
AMD Ryzen 9 5900H, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
Sapphire Pulse RX5700XT with the following display types:
4k 60hz (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Reference AMD RX6800 with the following display types:
4k 60hz (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz, and 3x 1080p 60hz on all systems.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Thank you,
Dan Wheeler
Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
Facebook | Twitter | amd.com
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Anson Jacob
Sent: September 24, 2021 3:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Zhuo, Qingqing <Qingqing.Zhuo@amd.com>; Lipski, Mikita <Mikita.Lipski@amd.com>; Li, Roman <Roman.Li@amd.com>; Jacob, Anson <Anson.Jacob@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>
Subject: [PATCH 00/24] DC Patches Sep 24, 2021
This DC patchset brings improvements in multiple areas. In summary, we
have:
- Fixes to backlight, LUT, PPS, MST
- Use correct vpg for 128b/132b encoding
- Improved logging for VCP
- Replace referral of dal with dc
Anthony Koo (2):
drm/amd/display: [FW Promotion] Release 0.0.85
drm/amd/display: [FW Promotion] Release 0.0.86
Aric Cyr (1):
drm/amd/display: 3.2.155
Charlene Liu (1):
drm/amd/display: Pass PCI deviceid into DC
David Galiffi (1):
drm/amd/display: Add debug support to override the Minimum DRAM Clock
Eric Yang (1):
drm/amd/display: add vsync notify to dmub for abm pause
George Shen (2):
drm/amd/display: Handle Y carry-over in VCP X.Y calculation
drm/amd/display: Update VCP X.Y logging to improve usefulness
Ilya (1):
drm/amd/display: Add PPS immediate update flag for DCN2
Jimmy Kizito (1):
drm/amd/display: Fix MST link encoder availability check.
Josip Pavic (1):
drm/amd/display: initialize backlight_ramping_override to false
Meenakshikumar Somasundaram (1):
drm/amd/display: Fix for link encoder access for MST.
Michael Strauss (2):
drm/amd/display: Don't enable AFMT for DP audio stream
drm/amd/display: Defer LUT memory powerdown until LUT bypass latches
Oliver Logush (1):
drm/amd/display: Add an extra check for dcn10 OPTC data format
Qingqing Zhuo (1):
drm/amd/display: Replace referral of dal with dc
Wenjing Liu (8):
drm/amd/display: use correct vpg instance for 128b/132b encoding
drm/amd/display: update cur_lane_setting to an array one for each lane
drm/amd/display: add function to convert hw to dpcd lane settings
drm/amd/display: implement decide lane settings
drm/amd/display: rename lane_settings to hw_lane_settings
drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings
drm/amd/display: add two lane settings training options
drm/amd/display: make verified link cap not exceeding max link cap
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 14 +-
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +-
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 73 +++
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 73 ++- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 591 +++++++----------- .../drm/amd/display/dc/core/dc_link_enc_cfg.c | 23 +-
.../drm/amd/display/dc/core/dc_link_hwss.c | 5 +-
drivers/gpu/drm/amd/display/dc/dc.h | 5 +-
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 5 -
drivers/gpu/drm/amd/display/dc/dc_link.h | 2 +-
.../drm/amd/display/dc/dce/dce_link_encoder.c | 6 +-
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 21 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 6 -
.../amd/display/dc/dcn10/dcn10_link_encoder.c | 6 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 2 +-
.../display/dc/dcn10/dcn10_stream_encoder.c | 11 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 5 +
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +
.../display/dc/dcn20/dcn20_stream_encoder.c | 9 +-
.../dc/dcn30/dcn30_dio_stream_encoder.c | 2 -
.../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 59 +-
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
.../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 21 +-
drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 12 +
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 1 -
.../display/dc/irq/dcn20/irq_service_dcn20.c | 2 +-
.../display/dc/irq/dcn20/irq_service_dcn20.h | 2 +-
.../display/dc/irq/dcn21/irq_service_dcn21.c | 2 +-
.../display/dc/irq/dcn21/irq_service_dcn21.h | 2 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 58 +-
.../amd/display/include/link_service_types.h | 29 +-
34 files changed, 583 insertions(+), 477 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 26+ messages in thread